WO2024000651A1 - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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Publication number
WO2024000651A1
WO2024000651A1 PCT/CN2022/105292 CN2022105292W WO2024000651A1 WO 2024000651 A1 WO2024000651 A1 WO 2024000651A1 CN 2022105292 W CN2022105292 W CN 2022105292W WO 2024000651 A1 WO2024000651 A1 WO 2024000651A1
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Prior art keywords
region
active
gate
channel
pull
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PCT/CN2022/105292
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English (en)
French (fr)
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刘志拯
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长鑫存储技术有限公司
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Priority to US18/364,039 priority Critical patent/US20240008240A1/en
Publication of WO2024000651A1 publication Critical patent/WO2024000651A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions

Definitions

  • Embodiments of the present disclosure relate to the field of semiconductors, and in particular, to a semiconductor structure and a manufacturing method thereof.
  • Memory is a memory device used to store information in modern information technology. It is widely used in various electronic products. Memory can be divided into internal memory and external memory according to whether it can be directly read by the central processor. Memory can be divided into dynamic random access memory DRAM (Dynamic Random Access Memory) and static random access memory SRAM (Static Random Access Memory).
  • DRAM Dynamic Random Access Memory
  • SRAM Static Random Access Memory
  • the static random access memory As long as the static random access memory remains powered on, the data stored in the static random access memory can be maintained constantly. When the power supply is stopped, the data in the static random access memory will disappear. The data stored in the dynamic random access memory needs to be updated periodically.
  • Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, which can at least reduce the size of a static random access memory.
  • embodiments of the present disclosure provide a semiconductor structure, including: a substrate, the substrate includes first active regions spaced apart along a first direction and adjacent first active regions There are two second active regions spaced apart between them. The first active region and the second active region both extend along the second direction. The first active region defines a pull-down transistor, and the third active region defines a pull-down transistor.
  • Two active regions define a pull-up transistor, the first active region has a first source region, a first channel region and a first drain region arranged along the second direction, and the second active region has a second source region, a second channel region and a second drain region arranged along the second direction; a first gate electrode and a second gate electrode, both of which are arranged along the second direction.
  • the first direction extends, the first gate covers the first channel region of the first active region and the second channel region of the second active region, and the The second gate electrode covers the first channel region of the other first active region and the second channel region of the other second active region; a third gate extending along the second direction
  • a conductive channel is located in the substrate and between the adjacent second active areas, and is used to electrically connect the second source areas of the adjacent second active areas.
  • a second conductive channel is further included, the second conductive channel extends along the second direction, and the second conductive channel is located in the first active area away from the second active area. The outside of the region is used to electrically connect the first gate.
  • a third active region is further included, the third active region extends along the second direction and is spaced apart along the first direction, and the third active region is separated from the third active region.
  • the first active area is connected, the third active area defines a storage transistor, and the third active area has a third source area, a third channel area and a third drain area arranged along the second direction. region; a third gate covering the third channel region.
  • two first active areas arranged at intervals, two second active areas between the first active areas, two third active areas, two One of the first gates, two of the second gates and two of the third gates form a static memory cell, and the static memory cells arranged along the second direction share the first conductive channel.
  • the pull-down transistor and the pull-up transistor form a common gate structure.
  • the spacing between the first conductive channel and the two first active regions adjacent to the first conductive channel is equal.
  • the pull-up transistor includes a first pull-up transistor and a second pull-up transistor
  • the first pull-up transistor includes the first gate and the gate covered by the first gate.
  • a second active region the second pull-up transistor includes the second gate and the second active region covered by the second gate, the first pull-up transistor and the second The pull-up transistors are distributed symmetrically around the center.
  • the method further includes: an interconnection layer located above the substrate; a conductive plug located between the interconnection layer and the first conductive channel. electrically connecting the first conductive channel and the interconnection layer.
  • the conductive plug is also located between the interconnection layer and the second conductive channel for electrically connecting the second conductive channel and the interconnection layer.
  • another aspect of the present disclosure further provides a method for manufacturing a semiconductor structure, including: providing a substrate, the substrate including first active regions spaced apart along a first direction and adjacent regions. There are two second active areas arranged at intervals between the first active areas, the first active area and the second active area both extend along the second direction, and the first active area defines a pull-down transistor, the second active region defines a pull-up transistor, the first active region has a first source region, a first channel region and a first drain region arranged along the second direction, the The second active region has a second source region, a second channel region and a second drain region arranged along the second direction; a first conductive channel is formed, and the first conductive channel extends along the second direction.
  • first gate and a second Two gates located in the substrate and between the adjacent second active regions, for electrically connecting the second source regions of the adjacent second active regions; forming a first gate and a second Two gates, the first gate and the second gate both extend along the first direction, and the first gate covers a first channel region of the first active region and a the second channel region of the second active region, the second gate covering the first channel region of the other first active region and the first channel of the other second active region district.
  • a method of forming the first conductive channel includes: forming an isolation structure that fills a gap between the first active region and the second active region; patterning the an isolation structure to form a first groove, the first groove being located between the second active areas; and forming a first conductive channel, the first conductive channel being located within the first groove.
  • the step of forming the first groove includes: forming a graphic layer, the graphic layer being located on the surface of the isolation structure; using the graphic layer as a mask, etching the isolation structure to The first groove is formed.
  • the step of forming the pattern layer includes: forming a first hard mask layer located on the surface of the isolation structure; forming a first intermediate layer located on the surface of the isolation structure; The surface of the first hard mask layer forms a first mask pattern, the first mask pattern is located on the surface of the first intermediate layer, and the first mask patterns are spaced along the first direction; so The first mask pattern is a mask for etching the first hard mask layer and the first intermediate layer, and the remaining first hard mask layer and the first intermediate layer serve as the pattern layer.
  • the step of forming the first mask pattern includes: forming a second hard mask layer, the second hard mask layer being located on the surface of the first intermediate layer; forming a second intermediate layer, The second intermediate layer is located on the surface of the second hard mask layer; a mask layer is formed, and the mask layer is located on the surface of the second intermediate layer; the mask layer is used as a mask for etching.
  • the second hard mask layer and the second intermediate layer are spaced to form the second hard mask layer and the second intermediate layer; a spacer layer is formed, and the spacer layer surrounds the second The hard mask layer and the sidewalls of the second intermediate layer; etching the sidewall layer to form the first mask pattern spaced along the first direction.
  • the method before forming the first gate and the second gate, the method further includes: forming a second conductive channel, the second conductive channel extending along the second direction, and the third conductive channel extending along the second direction. Two conductive channels are located outside the first active area away from the second active area and are used to electrically connect the first gate.
  • the substrate further includes: a third active region extending along the second direction and arranged at intervals along the first direction, the third active region and The first active area is connected, the third active area defines a storage transistor, and the third active area has a third source area, a third channel area and a third area arranged along the second direction. drain region, the process of forming the first gate and the second gate also includes: forming a third gate, the third gate covering the third channel region
  • a pull-down transistor is defined by a first active region, and the pull-down transistor includes: a first source region, a first channel region, and a first drain region of a first active region and a first gate covering the first channel region.
  • Another pull-down transistor includes: a first source region, a first channel region, a first drain region of another first active region and a first gate covering the first channel.
  • the second gate of the region; the pull-up transistor is defined by the second active region.
  • a pull-up transistor includes: a second source region of the second active region, a second channel region, a second drain region and a second gate region covering the second active region.
  • the channel region covers the first gate of the second channel region
  • the other pull-up transistor includes: a second source region, a second channel region, a second drain region of another second active region and a second gate electrode covering the second active region.
  • the second gate of the second channel region and by arranging a first conductive channel in the substrate, and providing electrical signals to the static memory unit including the pull-down transistor and the pull-up transistor through the first conductive channel, wiring in subsequent processes can be reduced required space.
  • Figure 1 is a circuit diagram of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 2 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 3 is a top view of a semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 4 is a schematic layout diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • 5 to 14 are structural schematic diagrams corresponding to each step of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.
  • a static random access memory unit it usually includes three states, namely, read, write and hold.
  • M4 is turned off, M3 is turned on, M2 is turned on, M1 is turned off, BLB keeps the voltage unchanged, but after M3 is turned on, the current flows from BL to GND, causing the BL potential to drop, the BL voltage is lower than BLB, and 0 is read out.
  • BL represents the bit line
  • BLB represents the complementary bit line
  • WL represents the word line
  • M1 represents the first pull-down transistor
  • M2 represents the first pull-up transistor
  • M3 represents the second pull-down transistor
  • M4 represents the second pull-up transistor
  • M5 represents the first storage transistor
  • M6 represents the second storage transistor
  • M1, M3, M5 and M6 are NMOS transistors
  • M2 and M4 are PMOS transistors
  • Q is the first node
  • Embodiments of the present disclosure provide a first conductive channel in the substrate, and the first conductive channel is electrically connected to the second source region of the second active region, so that the corresponding number of wiring can be reduced during subsequent wiring, and other connections can be increased.
  • the layout space of the lines can, for example, increase the space for subsequent formation of word lines, reduce the resistance of the word lines, and improve the conduction rate of the word lines.
  • FIG. 2 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 3 is a top view of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure. A schematic diagram of the layout of a semiconductor structure is provided.
  • the semiconductor structure includes: a substrate 100.
  • the substrate 100 includes first active regions 110 spaced apart along the first direction X and two spaced-apart second active regions 120 between adjacent first active regions 110.
  • An active region 110 and a second active region 120 both extend along the second direction Y.
  • the first active region 110 defines the pull-down transistor 160 and the second active region 120 defines the pull-up transistor 170.
  • the first active region 110 has The first source region 111, the first channel region 112 and the first drain region 113 are arranged along the second direction Y.
  • the second active region 120 has the second source region 121, the second source region 121 arranged along the second direction Y.
  • the second source areas 121 of adjacent second active areas 120 are connected.
  • the wiring space for the power supply voltage can be reduced during subsequent wiring, and the space originally used for wiring the power supply voltage can be used for laying out other structures, taking word lines as an example.
  • the layout space of the word line can be increased, thereby reducing the resistance of the word line, improving the ability of the word line to transmit electrical signals, and thereby reducing the delay of the semiconductor structure.
  • the semiconductor structure further includes: an isolation structure 180.
  • an isolation structure 180 By providing the isolation structure 180, the adjacent first active region 110 and the second active region 120 can be isolated, thereby preventing the first active region 110 from The second active region 120 is in direct contact, and the semiconductor structure can be filled through the isolation structure 180 , which can facilitate the subsequent production process and can support the subsequent formation of structures on the isolation structure 180 .
  • the semiconductor structure may further include: a conductive layer 190 located on the top surface of the first conductive channel 150 , and the first conductive channel 150 may be led out of the surface of the substrate 100 through the conductive layer 190 .
  • the first conductive channel 150 may be provided with an electrical signal, for example, a power supply voltage may be provided to the first conductive channel 150 through the conductive layer 190 .
  • the material of the substrate 100 can be silicon, germanium or silicon germanium, and the material of the substrate 100 can also be doped. Taking the material of the substrate 100 as silicon as an example, the material of the substrate 100 can be doped. Doping trace amounts of trivalent elements, such as: boron, indium, gallium or aluminum, etc., thereby forming a P-type substrate; similarly, doping trace amounts of pentavalent elements, such as: phosphorus, antimony, arsenic, etc., into the substrate 100, thereby forming a P-type substrate. An N-type substrate can be formed, and the selection of doping elements of the substrate 100 can be considered based on actual needs and product performance. The embodiments of the present disclosure do not limit the materials and doped elements of the substrate 100 .
  • the structure of the first active region 110 and the structure of the second active region 120 may be different.
  • the first active region 110 may be a continuous film layer in the second direction Y
  • the second active region 120 may be a continuous film layer in the second direction Y.
  • 120 may be a plurality of film layers arranged at intervals in the second direction Y.
  • the pull-down transistor 160 includes a first pull-down transistor and a second pull-down transistor, wherein the first pull-down transistor and the second pull-down transistor are spaced apart along the first direction X and the second direction Y, and the first pull-down transistor 160 is spaced along the first direction X and the second direction Y.
  • the pull-down transistor and the second pull-down transistor are centrally symmetrically distributed.
  • the first pull-down transistor includes: a first gate 130 and a first channel region 112 of the first active region 110 covered by the first gate 130 , and located on both sides of the first channel region 112 The first source region 111 and the first drain region 113 on the side; the second pull-down transistor includes: a second gate 140 and a first channel region 112 of another first active region 110 covered by the second gate 140, and the first source region 111 and the first drain region 113 located on both sides of the first channel region 112 .
  • the first gate 130 covering the first active region 110 serves as the gate of the first pull-down transistor, and the first source region 111 and the first drain region 113 located on both sides of the first gate 130 serve as the first pull-down transistor respectively.
  • the pull-up transistor 170 includes a first pull-up transistor and a second pull-up transistor
  • the first pull-up transistor includes a first gate 130 and a second active region 120 covered by the first gate 130
  • the second pull-up transistor includes a second gate 140 and a second active region 120 covered by the second gate 140.
  • the first pull-up transistor and the second pull-up transistor are centrally symmetrically distributed. By arranging a centrally symmetrical third The first pull-up transistor and the second pull-up transistor can improve the versatility of the semiconductor structure.
  • the first gate 130 covering the second active region 120 serves as the gate of the first pull-up transistor, and the second source region 121 and the second drain region 123 located on both sides of the first gate 130 serve as the gate of the first pull-up transistor.
  • Source and drain; the second gate 140 covering the second active region 120 serves as the gate of the second pull-up transistor, and the second source region 121 and the second drain region 123 located on both sides of the second gate 140 serve as The source and drain of the second pull-up transistor.
  • the first gate 130 and the second gate 140 are located on the top surface of the first active region 110 and the second active region 120 and are in contact with the first active region 110 and the second active region 120 Contact connection.
  • the top surface of the first conductive channel 150 is lower than the bottom surface of the second active area 120 .
  • the first conductive channel 150 can be avoided.
  • the distance between the channel 150 and the adjacent second active area 120 is too close to avoid electrical connection or electrical signal interference between the first conductive channel 150 and the second active area 120; in other embodiments, the The top surface of a conductive channel can be flush with the bottom surface of the first active area or higher than the first active area; the present disclosure does not limit the height of the first conductive channel 150 and can be adjusted according to actual needs.
  • the material of the first conductive channel 150 may be a conductive material such as tungsten.
  • a diffusion barrier layer (not shown in the figure) may also be included.
  • the diffusion barrier layer is located between the first conductive channel 150 and the substrate 100 to prevent metal ions in the first conductive channel 150 from diffusing into the substrate 100 , causing the substrate 100 to be contaminated, preventing performance degradation of the substrate 100 and improving the reliability of the semiconductor structure.
  • the material of the isolation structure 180 may be an insulating material such as silicon oxide, silicon oxynitride, or the like.
  • the semiconductor structure may further include: a second conductive channel 200 extending along the second direction Y, and the second conductive channel 200 is located in the first active region 110 away from the second active region 120 The outer side is used to electrically connect the first gate 130.
  • the second conductive channel 200 By providing the second conductive channel 200, the wiring space required for subsequent formation of the semiconductor structure can be reduced.
  • the space for laying out ground wires can be used.
  • Laying out other structures, taking bit lines as an example can increase the space for subsequent layout of bit lines and increase the area of the bit lines. By increasing the area of the bit lines, the resistance of the bit lines can be reduced and the transmission current of the bit lines can be improved. signal capability, thereby reducing the delay of the semiconductor structure.
  • the second conductive channel 200 and the first conductive channel 150 may be formed in the same process, and the materials of the second conductive channel 200 and the first conductive channel 150 may be the same.
  • the top surface of the second conductive channel 200 is lower than the bottom surface of the first active area 110.
  • the second conductive channel 200 By arranging the second conductive channel 200 lower than the bottom surface of the first active area 110, it is possible to avoid the second conductive channel 200 being connected to the bottom surface of the first active area 110.
  • the distance between adjacent first active areas 110 is too close to avoid electrical connection or electrical signal interference between the second conductive channel 200 and the first active area 110; in other embodiments, the second conductive channel is The top surface can be flush with the bottom surface of the first active area or higher than the first active area; the present disclosure does not limit the height of the second conductive channel 200 and can be adjusted according to actual needs.
  • a third active region 210 is also included.
  • the third active region 210 extends along the second direction Y and is spaced apart along the first direction X.
  • the third active region 210 and the first active region 110 connection, the third active region 210 defines the storage transistor 220, and the third active region 210 has a third source region 211, a third channel region 212 and a third drain region 213 arranged along the second direction Y;
  • the gate electrode 230 and the third gate electrode 230 cover the third channel region 212 .
  • the third source region 211 of the third active region 210 serves as the source of the storage transistor 220
  • the third drain region 213 serves as the drain of the storage transistor 220
  • the third gate 230 covering the third channel region 212 serves as the drain of the storage transistor 220 .
  • the gate, through memory transistor 220, can access the bit line voltage.
  • the drain of the storage transistor 220 is connected to the source of the first pull-down transistor, sharing the active region.
  • the pull-down transistor 160 and the pull-up transistor 170 form a common gate structure, that is, the first pull-down transistor and the first pull-up transistor share the first gate 130 to form a common gate structure, and the second pull-down transistor and the second pull-up transistor share the second gate 140 to form a common gate structure.
  • the structural density of the semiconductor structure can be increased.
  • the second source region 121 of the first pull-up transistor is connected to the second gate 140 of the second pull-up transistor, and the second drain region 123 of the second pull-up transistor is connected to the second pull-up transistor.
  • a gate 130 is connected.
  • the electrode 130, the two second gates 140 and the two third gates 230 form a static memory cell
  • the static memory cells arranged along the second direction Y share the first conductive channel 150.
  • the two storage transistors 220 , the two pull-down transistors 160 and the two pull-up transistors 170 form a static storage unit.
  • the static storage units arranged along the second direction share the first conductive channel 150 , and are arranged along the second direction.
  • Directionally arranged static memory cells sharing the first conductive channels 150 can reduce the number of the first conductive channels 150 , thereby reducing the space required for the first conductive channels 150 and increasing the structural density of the semiconductor structure.
  • a first gate 130 and a second gate 140 are further included between the static memory cells spaced apart along the second direction X.
  • the spacing between the first conductive channel 150 and the two first active areas 110 adjacent to the first conductive channel 150 is equal. That is to say, the projection of the first conductive channel 150 on the surface of the substrate 100 , the spacing between the projections of the two adjacent first active areas 110 on the surface of the substrate 100 is equal.
  • the distance between the first conductive channel and the two first active areas adjacent to the first conductive channel may also be unequal, and may be adjusted according to actual production conditions and actual needs.
  • it also includes: an interconnection layer 240 located above the substrate 100; a conductive plug 250 located between the interconnection layer 240 and the first conductive channel 150 for electrical connection.
  • the first conductive channel 150 can be led out through the conductive plug 250 and electrically connected to the interconnection layer 240 through the conductive plug 250.
  • a corresponding electrical signal can be provided to the interconnection layer 240, and the electrical signal passes through the conductive plug. 250 is passed to the conductive layer 190 and subsequently provided to the first conductive channel 150, so that the first conductive channel 150 provides a corresponding electrical signal to the second source region 121.
  • the material of the interconnect layer 240 may be a metal material, and in other embodiments, the material of the interconnect layer 240 may also be other conductive materials.
  • the conductive plug 250 is also located between the interconnection layer 240 and the second conductive channel 200 for electrically connecting the second conductive channel 200 and the interconnection layer 240.
  • the channel 200 is connected to the interconnection layer 240 by providing corresponding electrical signals to the interconnection layer 240 .
  • a first wiring layer 260 is also included.
  • the first wiring layer 260 includes: a first word line layer 261, a bit line layer 262, a first node layer 263, a second node layer 264 and a complementary bit line layer 265. .
  • the first wiring layer 260 is located on the interconnect layer 240.
  • a second wiring layer 270 is also included, and the second wiring layer 270 may be used to form word lines.
  • the embodiment of the present disclosure defines a pull-down transistor in the first active region 110.
  • the pull-down transistor includes: the first source region 111 of the first active region 110, the first channel region 112, the first drain region 113 and the first drain region covering the first active region 110.
  • a first gate 130 of a channel region 112 and another pull-down transistor include: a first source region 111 of the first active region 110, a first channel region 112, a first drain region 113 and covering the first channel
  • the second gate 140 of the region 112; a pull-up transistor is defined through the second active region 120.
  • a pull-up transistor includes: the second source region 121 of the second active region 120, the second channel region 122, the second drain region 123 and a first gate 130 covering the second channel region 122, and another pull-up transistor includes: a second source region 121 of another second active region 120, The second channel region 122, the second drain region 123 and the second gate 140 covering the second channel region 122; and by arranging the first conductive channel 150 in the substrate 100, the space required for wiring in subsequent processes can be reduced.
  • the space originally used for wiring the power supply voltage can be used to lay out other structures.
  • the layout space of the word line can be increased, thereby reducing the resistance of the word line and improving the resistance of the word line. The ability to transmit electrical signals, thereby reducing the delay of semiconductor structures.
  • Another embodiment of the present disclosure also provides a method for manufacturing a semiconductor structure.
  • the method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure will be described below with reference to the accompanying drawings. What needs to be explained are the same or corresponding parts of the previous embodiment. Reference may be made to the corresponding descriptions of the foregoing embodiments, which will not be described in detail below.
  • FIG. 5 to FIG. 8 and FIG. 2 are structural schematic diagrams corresponding to each step of a semiconductor structure manufacturing method provided by an embodiment of the present disclosure.
  • FIG. 6 is a partially enlarged schematic diagram within the dotted line in FIG. 5 , providing a substrate 100 .
  • the substrate 100 includes first active regions 110 spaced apart along the first direction X and adjacent first active regions 110 .
  • Two second active areas 120 are spaced between the active areas 110.
  • the first active area 110 and the second active area 120 both extend along the second direction Y.
  • the first active area 110 defines a pull-down transistor. 160.
  • the second active region 120 defines the pull-up transistor 170.
  • the first active region 110 has a first source region 111, a first channel region 112 and a first drain region 113 arranged along the second direction Y.
  • the second The active region 120 has a second source region 121, a second channel region 122 and a second drain region 123 arranged along the second direction Y.
  • the substrate 100 further includes: a third active region 210 extending along the second direction Y and arranged at intervals along the first direction X.
  • the third active region 210 is separated from the first The active areas 110 are connected, and the third active area 210 defines a storage transistor.
  • the third active area 210 has a third source area 211, a third channel area 212 and a third drain area 213 arranged along the second direction Y. The formation of the third active region 210 provides a process basis for subsequent formation of memory transistors, thereby forming a static memory cell.
  • a first conductive channel 150 extending along the second direction Y is formed in the substrate 100 and between adjacent second active regions 120 for electrically connecting adjacent second active regions 120 .
  • Second source area 121 of area 120 is formed in the substrate 100.
  • the wiring space for the power supply voltage can be reduced during subsequent wiring, and the space originally used for wiring the power supply voltage can be used for laying out other structures, taking word lines as an example.
  • the layout space of the word line can be increased, thereby reducing the resistance of the word line, improving the ability of the word line to transmit electrical signals, thereby reducing the delay of the semiconductor structure.
  • Figures 9 to 14 are structural schematic diagrams corresponding to each step of forming the first conductive channel 150, in which view AA is a cross-sectional view along the first direction X and perpendicular to the surface of the substrate 100, and view BB is It's a top view.
  • the method of forming the first conductive channel 150 may include: forming the isolation structure 180, which fills the gap between the first active region 110 and the second active region 120; patterning the isolation structure 180 to form the first active region 180; A groove 340.
  • the first groove 340 is located between the second active areas 120; a first conductive channel 150 is formed, and the first conductive channel 150 is located in the first groove 340.
  • the step of forming the pattern layer 360 may include: forming a first hard mask layer 280 located on the surface of the isolation structure 180 ; forming a first intermediate layer 290 , the first intermediate layer 290 is located on the surface of the first hard mask layer 280; a first mask pattern 350 is formed, the first mask pattern 350 is located on the surface of the first intermediate layer 290, and the first mask patterns 350 are spaced along the first direction X; A mask pattern 350 is used to etch the first hard mask layer 280 and the first intermediate layer 290, and the remaining first hard mask layer 280 and the first intermediate layer 290 serve as the pattern layer 360.
  • the pattern layer 360 it can be used as a mask for subsequent formation of the first groove 340, thereby improving the accuracy of the formed first groove 340.
  • it also includes forming a second hard mask layer 300, the second hard mask layer 300 is located on the surface of the first intermediate layer 290; forming a second intermediate layer 310, the second intermediate layer 310 is located on the second hard mask layer 300; a mask layer 320 is formed, and the mask layer 320 is located on the surface of the second intermediate layer 310.
  • the first hard mask layer 280 may be made of the same material as the second hard mask layer 300
  • the first intermediate layer 290 may be made of the same material as the second intermediate layer 310 .
  • the second hard mask layer 300 and the second intermediate layer 310 are etched using the mask layer 320 as a mask to form spaced second hard mask layers 300 and second intermediate layers 310 .
  • a spacer layer 330 is formed.
  • the spacer layer 330 surrounds the sidewalls of the second hard mask layer 300 and the second intermediate layer 310 .
  • the spacer layer 330 is etched to form first mask patterns 350 spaced along the first direction X.
  • first mask pattern 350 a mask is provided for subsequent formation of the pattern layer, thereby improving the accuracy of the formed pattern layer.
  • a graphics layer 360 is formed, and the graphics layer 360 is located on the surface of the isolation structure 180; using the graphics layer 360 as a mask, the isolation structure 180 is etched to form the first groove 340; the first conductive channel 150 is formed , the first conductive channel is located in the substrate 100 .
  • the method further includes: forming a conductive layer 190 located on the top surface of the first conductive channel 150 .
  • the method further includes: forming a second conductive channel 200 located outside the first active region 110 .
  • a first gate 130 and a second gate 140 are formed.
  • the first gate 130 and the second gate 140 both extend along the first direction X.
  • the first gate 130 covers a first active region 110
  • the second gate 140 covers the first channel region 112 of the other first active region 110 and the other second active region 112.
  • the second channel region 122 of the source region 120 By forming the first gate 130 and the second gate 140, the pull-up transistor and the pull-down transistor gate structures can be used.
  • the pull-down transistor 160 includes a first pull-down transistor and a second pull-down transistor.
  • the first pull-down transistor includes: a first gate 130 and a first channel region 112 of the first active region 110 covered by the first gate 130 , and the first source region 111 and the first drain region 113 located on both sides of the first channel region 112;
  • the second pull-down transistor includes: a second gate 140 and another first active region covered by the second gate 140 The first channel region 112 of the region 110, and the first source region 111 and the first drain region 113 located on both sides of the first channel region 112.
  • the first gate 130 covering the first active region 110 serves as the gate of the first pull-down transistor, and the first source region 111 and the first drain region 113 located on both sides of the first gate 130 serve as the first pull-down transistor respectively.
  • the pull-up transistor 170 includes a first pull-up transistor and a second pull-up transistor
  • the first pull-up transistor includes a first gate 130 and a second active region 120 covered by the first gate 130
  • the second pull-up transistor includes a second gate 140 and a second active region 120 covered by the second gate 140
  • the method before forming the first gate 130 and the second gate 140, the method further includes: forming a second conductive channel 200, the second conductive channel 200 extends along the second direction Y, and the second conductive channel 200 is located at The outer side of the first active region 110 away from the second active region 120 is used to electrically connect the first gate 130 .
  • the wiring space required for subsequent formation of the semiconductor structure can be reduced.
  • the space for laying out the ground conductor can be used for laying out other structures.
  • the subsequent wiring space can be increased. It is used to lay out the space of the bit line, and can increase the area of the bit line. By increasing the area of the bit line, the resistance of the bit line can be reduced, and the ability of the bit line to transmit electrical signals can be improved, thereby reducing the delay of the semiconductor structure.
  • the power supply voltage and the ground voltage can be provided for the static memory unit, thereby reducing the wiring space required for the power supply voltage and the ground voltage in the subsequent wiring process, thereby reducing the size of the semiconductor.
  • the volume of the structure can also increase the wiring space of other structures, such as increasing the wiring space of word lines or bit lines, which can also reduce the resistance of word lines or bit lines and increase the conduction rate of word lines or bit lines.
  • the process of forming the first gate 130 and the second gate 140 further includes forming a third gate 230 covering the third channel region 212 .
  • the gate of the storage transistor 220 can be formed, providing a process basis for forming the storage transistor 220 .
  • the third source region 211 of the third active region 210 serves as the source of the storage transistor 220
  • the third drain region 213 serves as the drain of the storage transistor 220
  • the third gate covering the third channel region 212 serves as the gate of the storage transistor 220 pole
  • Embodiments of the present disclosure define the pull-down transistor 160 by forming the first active region 110 , define the pull-up transistor 170 by forming the second active region 120 , and define the pull-up transistor 170 by forming the second active region 120 .
  • the first gate 130 and the second gate 140 are formed as gates of the pull-up transistor 170 and/or the pull-down transistor 160 respectively, and the first conductive channel 150 is formed to provide electrical signals for the pull-down transistor 160, thereby reducing the need for subsequent semiconductor processing.
  • the wiring space required for structural wiring and can provide larger layout space for subsequent layout of other structures.

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Abstract

本公开实施例涉及半导体领域，提供一种半导体结构及其制作方法，其中，半导体结构包括：基底，基底包括第一有源区及位于相邻第一有源区之间的两个第二有源区，第一有源区定义下拉晶体管，第二有源区定义上拉晶体管，第一有源区具有沿第二方向排布的第一源区、第一沟道区以及第一漏区，第二有源区具有第二源区、第二沟道区以及第二漏区；第一栅极以及第二栅极，第一栅极覆盖一第一有源区的第一沟道区以及一第二有源区的第二沟道区，第二栅极覆盖另一第一有源区的第一沟道区以及另一第二有源区的第二沟道区；第一导电通道位于基底内且位于相邻的第二有源区之间，用于电连接相邻的第二有源区的第二源区。可以缩小静态随机存储器的尺寸。

Description

半导体结构及其制作方法
交叉引用
本公开要求于2022年06月29日递交的名称为“半导体结构及其制作方法”、申请号为202210764449.X的中国专利申请的优先权，其通过引用被全部并入本公开。
技术领域
本公开实施例涉及半导体领域，特别涉及一种半导体结构及其制作方法。
背景技术
存储器是现代信息技术中用于保存信息的记忆设备，其广泛应用于各种电子产品中。存储器按照是否可以直接被中央处理器读取，可以分为内存和外存，内存又可以分为动态随机存储器DRAM(Dynamic Random Access Memory)及静态随机存储器SRAM(Static Random Access Memory)等。
其中，静态随机存储器只要保持通电，静态随机存储器中存储的数据可以恒常保持，当电力停止供应时，静态随机存储器中的数据会消失动态随机里面存储的数据需要周期性地更新。
发明内容
本公开实施例提供一种半导体结构及其制作方法，至少可以缩小静态随机存储器的尺寸。
根据本公开一些实施例，本公开实施例一方面提供一种半导体结构，包括：基底，所述基底包括沿第一方向间隔设置的第一有源区及位于相邻所述第一有源区之间的两个间隔设置的第二有源区，所述第一有源区及所述第二有源区均沿第二方向延伸，所述第一有源区定义下拉晶体管，所述第二有源区定义上拉晶体管，所述第一有源区具有沿所述第二方向排布的第一源区、第一沟道区以及第一漏区，所述第二有源区具有沿所述第二方向排布的第二源区、第二沟道区以及第二漏区；第一栅极以及第二栅极，所述第一栅极以及所述第二栅极均沿所述第一方向延伸，所述第一栅极覆盖一所述第一有源区的所述第一沟道区以及一所述第二有源区的所述第二沟道区，所述第二栅极覆盖另一所述第一有源区的所述第一沟道区以及另一所述第二有源区的所述第二沟道区；沿所述第二方向延伸的第一导电通道，位于所述基底内且位于相邻的所述第二有源区之间，用于电连接相邻的所述第二有源区的所述第二源区。
在一些实施例中，还包括：第二导电通道，所述第二导电通道沿所述第二方向延伸，且所述第二导电通道位于所述第一有源区远离所述第二有源区的外侧用于电性连接所述第一栅极。
在一些实施例中，还包括：第三有源区，所述第三有源区沿所述第二方向延伸，且沿所述第一方向间隔排布，所述第三有源区与所述第一有源区连接，所述第三有源区定义存储晶体管，所述第三有源区具有沿所述第二方向排布的第三源区、第三沟道区及第三漏区；第三栅极，所述第三栅极覆盖所述第三沟道区。
在一些实施例中，两个间隔设置的所述第一有源区、所述第一有源区之间的两个所述第二有源区、两个所述第三有源区、两个所述第一栅极、两个所述第二栅极及两个所述第三栅极构成一静态存储单元，沿所述第二方向排布的所述静态存储单元共用所述第一导电通道。
在一些实施例中，所述下拉晶体管与所述上拉晶体管构成共栅结构。
在一些实施例中，所述第一导电通道到与所述第一导电通道相邻的两个所述第一有源区之间的间距相等。
在一些实施例中，所述上拉晶体管包括第一上拉晶体管及第二上拉晶体管，所述第一上拉晶体管包括所述第一栅极及被所述第一栅极覆盖的所述第二有源区，所述第二上拉晶体管包括所述第二栅极及被所述第二栅极覆盖的所述第二有源区，所述第一上拉晶体管与所述第二上拉晶体管呈中心对称分布。
在一些实施例中，还包括：互连层，所述互连层位于所述基底上方；导电插塞，所述导电插塞位于所述互连层与所述第一导电通道之间，用于电连接所述第一导电通道及所述互连层。
在一些实施例中，所述导电插塞还位于所述互连层与所述第二导电通道之间，用于电性连接所述第二导电通道及所述互连层。
根据本公开一些实施例，本公开实施例另一方面还提供一种半导体结构的制作方法，包括：提供基底，所述基底包括沿第一方向间隔设置的第一有源区及位于相邻所述第一有源区之间的两个间隔设置的第二有源区，所述第一有源区及所述第二有源区均沿第二方向延伸，所述第一有源区定义下拉晶体管，所述第二有源区定义上拉晶体管，所述第一有源区具有沿所述第二方向排布的第一源区、第一沟道区以及第一漏区，所述第二有源区具有沿所述第二方向排布的第二源区、第二沟道区以及第二漏区；形成第一导电通道，所述第一导电通道沿所述第二方向延伸，位于所述基底内且位于相邻的所述第二有源区之间，用于电连接相邻的所述第二有源区的所述第二源区；形成第一栅极以及第二栅极，所述第一栅极以及所述第二栅极均沿所述第一方向延伸，所述第一栅极覆盖一所述第一有源区的第一沟道区以及一所述第二有源区的第二沟道区，所述第二栅极覆盖另一所述第一有源区的第一沟道区以及另一所述第二有源区的第一沟道区。
在一些实施例中，形成所述第一导电通道的方法包括：形成隔离结构，所述隔离结构填充所述第一有源区及所述第二有源区之间的间隙；图形化所述隔离结构，以形成第一凹槽，所述第一凹槽位于所述第二有源区之间；形成第一导电通道，所述第一导电通道位于所述第一凹槽内。
在一些实施例中，形成所述第一凹槽的步骤包括：形成图形层，所述图形层位于所述隔离结构的表面；以所述图形层为掩膜，刻蚀所述隔离结构，以形成所述第一凹槽。
在一些实施例中，形成图形层的步骤包括：形成第一硬掩膜层，所述第一硬掩膜层位于所述隔离结构的表面；形成第一中间层，所述第一中间层位于所述第一硬掩膜层的表面；形成第一掩膜图案，所述第一掩膜图案位于第一中间层的表面，所述第一掩膜图案沿所述第一方向间隔；以所述第一掩膜图案为掩膜刻蚀所述第一硬掩膜层及所述第一中间层，剩余所述第一硬掩膜层及所述第一中间层作为所述图形层。
在一些实施例中，形成所述第一掩膜图案的步骤包括：形成第二硬掩膜层，所述第二硬掩膜层位于所述第一中间层的表面；形成第二中间层，所述第二中间层位于所述第二硬掩膜层的表面；形成掩膜层，所述掩膜层位于所述第二中间层的表面；以所述掩膜层为掩膜刻蚀所述第二硬掩膜层及所述第二中间层，以形成间隔的所述第二硬掩膜层及所述第二中间层；形成侧墙层，所述侧墙层环绕所述第二硬掩膜层及所述第二中间层的侧壁；刻蚀所述侧墙层，以形成沿所述第一方向间隔的所述第一掩膜图案。
在一些实施例中，在形成所述第一栅极以及所述第二栅极之前，还包括：形成第二导电通道，所述第二导电通道沿所述第二方向延伸，且所述第二导电通道位于所述第一有源区远离所述第二有源区的外侧用于电性连接所述第一栅极。
在一些实施例中，所述基底还包括：第三有源区，所述第三有源区沿第二方向延伸，且沿所述第一方向间隔排布，所述第三有源区与所述第一有源区连接，所述第三有源区定义存储晶体管，所述第三有源区具有沿所述第二方向排布的第三源区、第三沟道区及第三漏区，形成所述第一栅极及所述第二栅极的过程中还包括：形成第三栅极，所述第三栅极覆盖所述第三沟道区
本公开实施例提供的技术方案至少具有以下优点：通过第一有源区定义下拉晶体管，一下拉晶体管包括：一第一有源区的第一源区、第一沟道区、第一漏区及覆盖该第一沟道区的第一栅极，另一下拉晶体管包括：另一第一有源区的第一源区、第一沟道区、第一漏区及覆盖该第一沟道区的第二栅极；通过第二有源区定义上拉晶体管，一上拉晶体管包括：第二有源区的第二源区、第二沟道区、第二漏区及覆盖该第二沟道区的覆盖该第二沟道区第一栅极，另一上拉晶体管包括：另一第二有源区的第二源区、第二沟道区、第二漏区及覆盖该第二沟道区的第二栅极；并通过在基底内设置第一导电通道，并可以通过第一导电通道向包括下拉晶体管及上拉晶体管的静态存储单元提供电信号，可以减少后续工艺中布线所需的空间。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制；为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一实施例提供的一种半导体结构的电路图；
图2为本公开一实施例提供的一种半导体结构的结构示意图；
图3为本公开一实施例提供的一种半导体结构的俯视图；
图4为本公开一实施例提供的一种半导体结构的版图结构示意图；
图5至图14为本公开一实施例提供的一种半导体结构的制作方法各步骤对应的结构示意图。
具体实施方式
经分析发现，参考图1，对于一个静态随机存储器单元来说，通常包括三个状态，即， 读、写及保持，读状态时，假设静态随机存储器单元内存储的数据为0时，对应Q＝0，
Figure PCTCN2022105292-appb-000001
静态随机存储器单元内存储的数据为1时，对应Q＝1，
Figure PCTCN2022105292-appb-000002
假设目前静态随机存储器单元内存储的数据为0时，在读取的过程中，对BL及BLB进行预充电，即BL＝BLB＝WL＝1，Q处于低电位，
Figure PCTCN2022105292-appb-000003
处于高电位，M4关断，M3开启，M2开启，M1关断，BLB保持电压不变，但是M3开启后，导致电流从BL流向GND，导致BL电位下降，BL电压低于BLB，读出0；同理，当目前静态随机存储器单元内存储的数据为1时，BL电压高于BLB，读出1。写状态时，假设目前静态随机存储器单元内存储的数据为0需要写入1时，对BL进行预充电，即，BL＝1，BLB＝0，WL＝1，此时Q仍处于低电位，
Figure PCTCN2022105292-appb-000004
仍处于高电位，M4关断，M3开启，由于
Figure PCTCN2022105292-appb-000005
的电位会下降，随着
Figure PCTCN2022105292-appb-000006
的电位下降，M4打开，M3关闭，这样Q的电位上升，M1打开，M2关闭数据进行翻转，写操作完成；同理，假设目前静态随机存储器单元内存储的数据为1需要写入0时，对BLB进行预充电，即，BL＝0，BLB＝1，WL＝1，
Figure PCTCN2022105292-appb-000007
电位上升，Q电位下降，数据翻转，写入操作完成。保持状态时，设置BL＝BLB＝1，WL＝0，无法对静态随机存储器单元内的数据进行修改。
其中，BL表示位线，BLB表示互补位线，WL表示字线，M1表示第一下拉晶体管，M2表示第一上拉晶体管，M3表示第二下拉晶体管，M4表示第二上拉晶体管，M5表示第一存储晶体管，M6表示第二存储晶体管，M1、M3、M5及M6为NMOS管，M2及M4为PMOS管，Q为第一节点，
Figure PCTCN2022105292-appb-000008
为第二节点。
本公开实施例通过设置位于基底内第一导电通道，且第一导电通道电连接第二有源区的第二源区，从而后续进行布线的时候可以减少相应的布线数量，且可以增加其他连线的布局空间，例如可以增加后续形成字线的空间，还可以降低字线的电阻，提高字线传导速率。
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开所要求保护的技术方案。
参考图2至图4，图2为本公开一实施例提供的一种半导体结构的结构示意图，图3为本公开一实施例提供的一种半导体结构的俯视图，图4为本公开一实施例提供的一种半导体结构的版图示意图。
半导体结构包括：基底100，基底100包括沿第一方向X间隔设置的第一有源区110及位于相邻第一有源区110之间的两个间隔设置的第二有源区120，第一有源区110及第二有源区120均沿第二方向Y延伸，第一有源区110定义下拉晶体管160，第二有源区120定义上拉晶体管170，第一有源区110具有沿第二方向Y排布的第一源区111、第一沟道区112以及第一漏区113，第二有源区120具有沿第二方向Y排布的第二源区121、第二沟道区122以及第二漏区123；第一栅极130以及第二栅极140，第一栅极130以及第二栅极140均沿第一方向X延伸，第一栅极130覆盖一第一有源区110的第一沟道区112以及一第二有源区120的第二沟道区122，第二栅极140覆盖另一第一有源区110的第一沟道区112以及另一第二有源区120的第二沟道区122；沿第二方向Y延伸的第一导电通道150，位于基底100内且位于相邻的第二有源区120之间，用于电连接相邻的第二有源区120的第二源区121。通过 设置位于基底100内的第一导电通道150可以减少后续在布线的时候，减少电源电压的布线空间，且可以将原本用于布线电源电压的空间用于布局其他结构，以字线为例，可以增加字线的布局空间，从而可以减少字线的电阻，提高字线的传递电信号的能力，进而降低半导体结构的延时。
在一些实施例中，半导体结构还包括：隔离结构180，通过设置隔离结构180可以将相邻的第一有源区110及第二有源区120进行隔离，从而避免第一有源区110与第二有源区120直接接触，且通过隔离结构180可以对半导体结构进行填充，可以便于后续的生产过程，且可以对后续在隔离结构180上形成结构起到支撑作用。
在一些实施例中，半导体结构还可以包括：导电层190，导电层190位于第一导电通道150的顶面，且可以通过导电层190将第一导电通道150引出基底100表面，通过导电层190可以给第一导电通道150提供电信号，例如可以通过导电层190提供给第一导电通道150电源电压。
在一些实施例中，基底100的材料可以是硅、锗或者锗化硅等材料，且还可以在基底100的材料中进行掺杂，以基底100的材料是硅为例，在基底100中掺杂微量的三价元素，例如：硼、铟、镓或铝等，从而可以形成P型基底；同理，在基底100中掺杂微量的五价元素，例如：磷、锑、砷等，从而可以形成N型基底，基底100掺杂元素的选择可以根据实际的需求及产品性能等方面进行考量，本公开实施例不对基底100的材料及掺杂的元素进行限制。
在一些实施例中，第一有源区110的结构与第二有源区120的结构可以不同，第一有源区110在第二方向Y上可以是连续的膜层，第二有源区120在第二方向Y上可以是多个间隔设置的膜层。
在一些实施例中，下拉晶体管160包括第一下拉晶体管及的第二下拉晶体管，其中，第一下拉晶体管和第二下拉晶体管沿第一方向X及第二方向Y间隔分布，且第一下拉晶体管和第二下拉晶体管呈中心对称分布，通过设置第一下拉晶体管及第二下拉晶体管呈中心对称可以使半导体结构旋转180°后仍可以使用，提高半导体结构的通用性。
在一些实施例中，第一下拉晶体管包括：第一栅极130及被第一栅极130覆盖的第一有源区110的第一沟道区112，以及位于第一沟道区112两侧的第一源区111及第一漏区113；第二下拉晶体管包括：第二栅极140及被第二栅极140覆盖的另一第一有源区110的第一沟道区112，以及位于第一沟道区112两侧的第一源区111及第一漏区113。
覆盖第一有源区110的第一栅极130作为第一下拉晶体管的栅极，位于第一栅极130两侧的第一源区111及第一漏区113分别作为第一下拉晶体管的源极及漏极；覆盖第一有源区110的第二栅极140作为第二下拉晶体管的栅极，位于第二栅极140两侧的第一源区111及第一漏区113分别作为第二下拉晶体管的源极及漏极。
在一些实施例中，上拉晶体管170包括第一上拉晶体管及第二上拉晶体管，第一上拉晶体管包括第一栅极130及被第一栅极130覆盖的第二有源区120，第二上拉晶体管包括第二栅极140及被第二栅极140覆盖的第二有源区120，第一上拉晶体管与第二上拉晶体管呈中心对称分布，通过设置呈中心对称的第一上拉晶体管及第二上拉晶体管可以提高半导体结 构的通用性。
覆盖第二有源区120的第一栅极130作为第一上拉晶体管的栅极，位于第一栅极130两侧的第二源区121及第二漏区123作为第一上拉晶体管的源极及漏极；覆盖第二有源区120的第二栅极140作为第二上拉晶体管的栅极，位于第二栅极140两侧的第二源区121及第二漏区123作为第二上拉晶体管的源极及漏极。
在一些实施例中，第一栅极130及第二栅极140位于第一有源区110及第二有源区120的顶面，且与第一有源区110及第二有源区120接触连接。
在一些实施例中，第一导电通道150的顶面低于第二有源区120的底面，通过设置第一导电通道150的顶面低于第二有源区120的底面可以避免第一导电通道150与相邻的第二有源区120之间的间距太近，避免第一导电通道150与第二有源区120之间电连接或者出现电信号干扰；在另一些实施例中，第一导电通道的顶面可以与第一有源区的底面齐平或者高于第一有源区；本公开不对第一导电通道150的高度进行限制，可以根据实际的需求进行调整。
在一些实施例中，第一导电通道150的材料可以是钨等导电材料。
在一些实施例中，还可以包括扩散阻挡层(图中未示意)，扩散阻挡层位于第一导电通道150及基底100之间，用于避免第一导电通道150的金属离子扩散至基底100中，导致基底100被污染，避免基底100的性能下降，提高半导体结构的可靠性。
在一些实施例中，隔离结构180的材料可以是氧化硅、氮氧化硅等绝缘材料。
在一些实施例中，半导体结构还可以包括：第二导电通道200，第二导电通道200沿第二方向Y延伸，且第二导电通道200位于第一有源区110远离第二有源区120的外侧用于电性连接第一栅极130，通过设置第二导电通道200可以减少后续形成半导体结构所需的布线空间，通过设置第二导电通道200可以用于将布局接地导线的空间用于布局其他结构，以位线为例，可以增加后续用于布局位线的空间，且可以增加位线的面积，通过增加位线的面积可以减少位线的电阻，且可以提高位线的传递电信号的能力，进而降低半导体结构的延时。
在一些实施例中，第二导电通道200与第一导电通道150可以在同一步工艺中形成，且第二导电通道200与第一导电通道150的材料可以相同。
在一些实施例中，第二导电通道200的顶面低于第一有源区110的底面，通过设置第二导电通道200低于第一有源区110的底面可以避免第二导电通道200与相邻的第一有源区110之间的间距太近，避免第二导电通道200与第一有源区110之间电连接或者电信号干扰；在另一些实施例中，第二导电通道的顶面可以与第一有源区的底面齐平或者高于第一有源区；本公开不对第二导电通道200的高度进行限制，可以根据实际的需求进行调整。
在一些实施例中，还包括第三有源区210，第三有源区210沿第二方向Y延伸，且沿第一方向X间隔排布，第三有源区210与第一有源区110连接，第三有源区210定义存储晶体管220，第三有源区210具有沿第二方向Y排布的第三源区211、第三沟道区212及第三漏区213；第三栅极230，第三栅极230覆盖第三沟道区212。
第三有源区210的第三源区211作为存储晶体管220源极，第三漏区213作为存储晶体管220的漏极，覆盖第三沟道区212的第三栅极230作为存储晶体管220的栅极，通过存 储晶体管220可以接入位线电压。
在一些实施例中，存储晶体管220的漏极与第一下拉晶体管的源极相连接，共用有源区。
在一些实施例中，下拉晶体管160与上拉晶体管170构成共栅结构，也就是说，第一下拉晶体管与第一上拉晶体管共用第一栅极130以形成共栅结构，第二下拉晶体管及第二上拉晶体管共用第二栅极140以形成共栅结构。通过设置下拉晶体管160与上拉晶体管170构成共栅结构，可以提高半导体结构的结构密度。
在一些实施例中，第一上拉晶体管的第二源区121与第二上拉晶体管的第二栅极140相连，第二上拉晶体管的第二漏区123与第一上拉晶体管的第一栅极130相连。
在一些实施例中，两个间隔设置的第一有源区110、第一有源区110之间的两个第二有源区120、两个第三有源区210、两个第一栅极130、两个第二栅极140及两个第三栅极230构成一静态存储单元，沿第二方向Y排布的静态存储单元共用第一导电通道150。换句话说，两个存储晶体管220，两个下拉晶体管160及两个上拉晶体管170构成一静态存储单元，沿第二方向排布的静态存储单元共用第一导电通道150，通过设置沿第二方向排布的静态存储单元共用第一导电通道150可以减少设置第一导电通道150的数量，从而降低设置第一导电通道150所需的占用的空间，提高半导体结构的结构密度。
在一些实施例中，沿第二方向X间隔排布的静态存储单元之间还包括一第一栅极130及一第二栅极140。
在一些实施例中，第一导电通道150到与第一导电通道150相邻的两个第一有源区110之间的间距相等，也就是说，第一导电通道150在基底100表面的投影，与其相邻的两个第一有源区110在基底100表面的投影之间的间距相等。通过设置第一导电通道150到与第一导电通道150相邻的两个第一有源区110之间的间距相等可以提高半导体结构的稳定性及半导体结构的美观。
在另一些实施例中，第一导电通道到与第一导电通道相邻的两个第一有源区之间的间距也可以不相等，可以根据实际的生产情况及实际需求进行调整。
在一些实施例中，还包括：互连层240，互连层240位于基底100上方；导电插塞250，导电插塞250位于互连层240与第一导电通道150之间，用于电连接第一导电通道150及互连层240。可以通过导电插塞250将第一导电通道150引出，并通过导电插塞250与互连层240接触电连接，后续可以通过给互连层240提供对应的电信号，该电信号通过导电插塞250传递给导电层190并后续提供给第一导电通道150，以使第一导电通道150提供对应的电信号给第二源区121。
在一些实施例中，互连层240的材料可以是金属材料，在另一些实施例中，互连层的材料也可以是其他导电材料。
在一些实施例中，导电插塞250还位于互连层240与第二导电通道200之间，用于电性连接第二导电通道200及互连层240，通过导电插塞250将第二导电通道200与互连层240相连可以通过向互连层240提供对应的电信号。
在一些实施例中，还包括第一布线层260，第一布线层260包括：第一字线层261， 位线层262，第一节点层263，第二节点层264及互补位线层265。第一布线层260位于互连层240上。
在一些实施例中，还包括：第二布线层270，第二布线层270可以用于形成字线。
本公开实施例通过在第一有源区110定义下拉晶体管，一下拉晶体管包括：第一有源区110的第一源区111、第一沟道区112、第一漏区113及覆盖该第一沟道区112的第一栅极130，另一下拉晶体管包括：第一有源区110的第一源区111、第一沟道区112、第一漏区113及覆盖该第一沟道区112的第二栅极140；通过第二有源区120定义上拉晶体管，一上拉晶体管包括：第二有源区120的第二源区121、第二沟道区122、第二漏区123及覆盖该第二沟道区122的覆盖该第二沟道区122的第一栅极130，另一上拉晶体管包括：另一第二有源区120的第二源区121、第二沟道区122、第二漏区123及覆盖该第二沟道区122的第二栅极140；并通过在基底100内设置第一导电通道150，可以减少后续工艺中布线所需的空间，以第一导电通道150代替电源电压为例，可以将原本用于布线电源电压的空间用于布局其他结构，例如可以增加字线的布局空间，从而可以减少字线的电阻，提高字线的传递电信号的能力，进而降低半导体结构的延时。
本公开另一实施例还提供一种半导体结构的制作方法，以下将结合附图对本公开另一实施例提供的半导体结构的制作方法进行说明，需要说明的是前述实施例相同或相应的部分，可参考前述实施例的相应说明，以下将不做赘述。
参考图5至图8以及图2，图5至图8以及图2为本公开一实施例提供的一种半导体结构制作方法各步骤对应的结构示意图。
具体的，参考图5及图6，其中，图6为图5虚线内的局部放大示意图，提供基底100，基底100包括沿第一方向X间隔设置的第一有源区110及位于相邻第一有源区110之间的两个间隔设置的第二有源区120，第一有源区110及第二有源区120均沿第二方向Y延伸，第一有源区110定义下拉晶体管160，第二有源区120定义上拉晶体管170，第一有源区110具有沿第二方向Y排布的第一源区111、第一沟道区112以及第一漏区113，第二有源区120具有沿第二方向Y排布的第二源区121、第二沟道区122以及第二漏区123。
在一些实施例中，基底100还包括：第三有源区210，第三有源区210沿第二方向Y延伸，且沿第一方向X间隔排布，第三有源区210与第一有源区110连接，第三有源区210定义存储晶体管，第三有源区210具有沿第二方向Y排布的第三源区211、第三沟道区212及第三漏区213。通过形成第三有源区210为后续形成存储晶体管提供工艺基础，进而可以形成静态存储单元。
参考图7及图8，形成沿第二方向Y延伸的第一导电通道150，位于基底100内且位于相邻的第二有源区120之间，用于电连接相邻的第二有源区120的第二源区121。通过形成位于基底100内的第一导电通道150可以减少后续在布线的时候，减少电源电压的布线空间，且可以将原本用于布线电源电压的空间用于布局其他结构，以字线为例，可以增加字线的布局空间，从而可以减少字线的电阻，提高字线的传递电信号的能力，进而降低半导体结构的延时。
参考图9至图14，图9至图14为形成第一导电通道150各步骤所对应的结构示意图， 其中AA视图为沿第一方向X且垂直于基底100表面的方向的剖面图，BB视图为俯视图。
具体的，形成第一导电通道150的方法可以包括：形成隔离结构180，隔离结构180填充第一有源区110及第二有源区120之间的间隙；图形化隔离结构180，以形成第一凹槽340。第一凹槽340位于第二有源区120之间；形成第一导电通道150，第一导电通道150位于第一凹槽340内。
参考图9至图13，形成图形层360的步骤可以包括：形成第一硬掩膜层280，第一硬掩膜层280位于隔离结构180的表面；形成第一中间层290，第一中间层290位于第一硬掩膜层280的表面；形成第一掩膜图案350，第一掩膜图案350位于第一中间层290的表面，第一掩膜图案350沿第一方向X间隔；以第一掩膜图案350为掩膜刻蚀第一硬掩膜层280及第一中间层290，剩余第一硬掩膜层280及第一中间层290作为图形层360。通过形成图形层360可以作为后续形成第一凹槽340的掩膜，从而可以提高形成的第一凹槽340的精确性。
参考图9，还包括形成第二硬掩膜层300，第二硬掩膜层300位于第一中间层290的表面；形成第二中间层310，第二中间层310位于第二硬掩膜层300的表面；形成掩膜层320，掩膜层320位于第二中间层310的表面。
在一些实施例中，第一硬掩膜层280的材料可以与第二硬掩膜层300的材料相同，第一中间层290的材料可以与第二中间层310的材料相同。
参考图10，以掩膜层320为掩膜刻蚀第二硬掩膜层300及第二中间层310，以形成间隔的第二硬掩膜层300及第二中间层310。
参考图11，形成侧墙层330，侧墙层330环绕第二硬掩膜层300及第二中间层310的侧壁。
参考图12，刻蚀侧墙层330，以形成沿第一方向X间隔的第一掩膜图案350。通过形成第一掩膜图案350为后续形成图形层提供掩膜，从而可以提高形成的图形层的精确性。
参考图13及图14，形成图形层360，图形层360位于隔离结构180的表面；以图形层360为掩膜，刻蚀隔离结构180，以形成第一凹槽340；形成第一导电通道150，第一导电通道位于基底100内。
在一些实施例中，还包括：形成导电层190，导电层190位于第一导电通道150的顶面。
在一些实施例中，还包括：形成第二导电通道200，第二导电通道200位于第一有源区110的外侧。
继续参考图2，形成第一栅极130以及第二栅极140，第一栅极130以及第二栅极140均沿第一方向X延伸，第一栅极130覆盖一第一有源区110的第一沟道区112以及一第二有源区120的第二沟道区122，第二栅极140覆盖另一第一有源区110的第一沟道区112以及另一第二有源区120的第二沟道区122。通过形成第一栅极130及第二栅极140可以作为上拉晶体管和下拉晶体管栅极结构。
下拉晶体管160包括第一下拉晶体管及的第二下拉晶体管，第一下拉晶体管包括：第一栅极130及被第一栅极130覆盖的第一有源区110的第一沟道区112，以及位于第一沟道区112两侧的第一源区111及第一漏区113；第二下拉晶体管包括：第二栅极140及被第二栅 极140覆盖的另一第一有源区110的第一沟道区112，以及位于第一沟道区112两侧的第一源区111及第一漏区113。
覆盖第一有源区110的第一栅极130作为第一下拉晶体管的栅极，位于第一栅极130两侧的第一源区111及第一漏区113分别作为第一下拉晶体管的源极及漏极；覆盖第一有源区110的第二栅极140作为第二下拉晶体管的栅极，位于第二栅极140两侧的第一源区111及第一漏区113分别作为第二下拉晶体管的源极及漏极。
在一些实施例中，上拉晶体管170包括第一上拉晶体管及第二上拉晶体管，第一上拉晶体管包括第一栅极130及被第一栅极130覆盖的第二有源区120，第二上拉晶体管包括第二栅极140及被第二栅极140覆盖的第二有源区120，
在一些实施例中，在形成第一栅极130及第二栅极140之前，还包括：形成第二导电通道200，第二导电通道200沿第二方向Y延伸，且第二导电通道200位于第一有源区110远离第二有源区120的外侧用于电性连接第一栅极130。通过形成第二导电通道200可以减少后续形成半导体结构所需的布线空间，通过设置第二导电通道200可以用于将布局接地导线的空间用于布局其他结构，以位线为例，可以增加后续用于布局位线的空间，且可以增加位线的面积，通过增加位线的面积可以减少位线的电阻，且可以提高位线的传递电信号的能力，进而降低半导体结构的延时。
通过形成第一导电通道150及第二导电通道200可以为静态存储单元提供电源电压及接地电压，从而可以减少后续在布线的过程中减少电源电压及接地电压的走线空间，从而可以减小半导体结构的体积，也可以增加其他结构的走线空间，例如增加字线或者位线的走线空间，从而还可以降低字线或者位线的电阻，提高字线或者位线的传导速率。
在一些实施例中，形成第一栅极130及第二栅极140的过程中还包括：形成第三栅极230，第三栅极230覆盖第三沟道区212。通过形成第三栅极230可以形成存储晶体管220的栅极，为形成存储晶体管220提供工艺基础。
第三有源区210的第三源区211作为存储晶体管220源极，第三漏区213作为存储晶体管220的漏极，覆盖第三沟道区212的第三栅极作为存储晶体管220的栅极，通过存储晶体管220可以接入位线电压。
本公开实施例通过形成第一有源区110，通过形成第一有源区110定义下拉晶体管160，通过形成第二有源区120，通过第二有源区120定义上拉晶体管170，并通过形成第一栅极130及第二栅极140分别作为上拉晶体管170和/或下拉晶体管160的栅极，通过形成第一导电通道150为下拉晶体管160提供电信号，从而可以减少后续在为半导体结构布线时所需的布线空间，且可以为后续布局其他结构提供更大的布局空间。
本领域的普通技术人员可以理解，上述各实施方式是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开实施例的精神和范围。任何本领域技术人员，在不脱离本公开实施例的精神和范围内，均可作各自更动与修改，因此本公开实施例的保护范围应当以权利要求限定的范围为准。

Claims (16)

  1. 一种半导体结构，包括：
    基底，所述基底包括沿第一方向间隔设置的第一有源区及位于相邻所述第一有源区之间的两个间隔设置的第二有源区，所述第一有源区及所述第二有源区均沿第二方向延伸，所述第一有源区定义下拉晶体管，所述第二有源区定义上拉晶体管，所述第一有源区具有沿所述第二方向排布的第一源区、第一沟道区以及第一漏区，所述第二有源区具有沿所述第二方向排布的第二源区、第二沟道区以及第二漏区；
    第一栅极以及第二栅极，所述第一栅极以及所述第二栅极均沿所述第一方向延伸，所述第一栅极覆盖一所述第一有源区的所述第一沟道区以及一所述第二有源区的所述第二沟道区，所述第二栅极覆盖另一所述第一有源区的所述第一沟道区以及另一所述第二有源区的所述第二沟道区；
    沿所述第二方向延伸的第一导电通道，位于所述基底内且位于相邻的所述第二有源区之间，用于电连接相邻的所述第二有源区的所述第二源区。
  2. 根据权利要求1所述的半导体结构，其中，还包括：第二导电通道，所述第二导电通道沿所述第二方向延伸，且所述第二导电通道位于所述第一有源区远离所述第二有源区的外侧，用于电性连接所述第一栅极。
  3. 根据权利要求2所述的半导体结构，其中，还包括：
    第三有源区，所述第三有源区沿所述第二方向延伸，且沿所述第一方向间隔排布，所述第三有源区与所述第一有源区连接，所述第三有源区定义存储晶体管，所述第三有源区具有沿所述第二方向排布的第三源区、第三沟道区及第三漏区；
    第三栅极，所述第三栅极覆盖所述第三沟道区。
  4. 根据权利要求3所述的半导体结构，其中，两个间隔设置的所述第一有源区、所述第一有源区之间的两个所述第二有源区、两个所述第三有源区、两个所述第一栅极、两个所述第二栅极及两个所述第三栅极构成一静态存储单元，沿所述第二方向排布的所述静态存储单元共用所述第一导电通道。
  5. 根据权利要求1所述的半导体结构，其中，所述下拉晶体管与所述上拉晶体管构成共栅结构。
  6. 根据权利要求1所述的半导体结构，其中，所述第一导电通道到与所述第一导电通道相邻的两个所述第一有源区之间的间距相等。
  7. 根据权利要求1所述的半导体结构，其中，所述上拉晶体管包括第一上拉晶体管及第二 上拉晶体管，所述第一上拉晶体管包括所述第一栅极及被所述第一栅极覆盖的所述第二有源区，所述第二上拉晶体管包括所述第二栅极及被所述第二栅极覆盖的所述第二有源区，所述第一上拉晶体管与所述第二上拉晶体管呈中心对称分布。
  8. 根据权利要求2所述的半导体结构，其中，还包括：互连层，所述互连层位于所述基底上方；
    导电插塞，所述导电插塞位于所述互连层与所述第一导电通道之间，用于电连接所述第一导电通道及所述互连层。
  9. 根据权利要求8所述的半导体结构，其中，所述导电插塞还位于所述互连层与所述第二导电通道之间，用于电性连接所述第二导电通道及所述互连层。
  10. 一种半导体结构的制作方法，包括：
    提供基底，所述基底包括沿第一方向间隔设置的第一有源区及位于相邻所述第一有源区之间的两个间隔设置的第二有源区，所述第一有源区及所述第二有源区均沿第二方向延伸，所述第一有源区定义下拉晶体管，所述第二有源区定义上拉晶体管，所述第一有源区具有沿所述第二方向排布的第一源区、第一沟道区以及第一漏区，所述第二有源区具有沿所述第二方向排布的第二源区、第二沟道区以及第二漏区；
    形成第一导电通道，所述第一导电通道沿所述第二方向延伸，位于所述基底内且位于相邻的所述第二有源区之间，用于电连接相邻的所述第二有源区的所述第二源区；
    形成第一栅极以及第二栅极，所述第一栅极以及所述第二栅极均沿所述第一方向延伸，所述第一栅极覆盖一所述第一有源区的第一沟道区以及一所述第二有源区的第二沟道区，所述第二栅极覆盖另一所述第一有源区的第一沟道区以及另一所述第二有源区的第一沟道区。
  11. 根据权利要求10所述的半导体结构的制作方法，其中，形成所述第一导电通道的方法包括：
    形成隔离结构，所述隔离结构填充所述第一有源区及所述第二有源区之间的间隙；
    图形化所述隔离结构，以形成第一凹槽，所述第一凹槽位于所述第二有源区之间；
    形成第一导电通道，所述第一导电通道位于所述第一凹槽内。
  12. 根据权利要求11所述的半导体结构的制作方法，其中，形成所述第一凹槽的步骤包括：
    形成图形层，所述图形层位于所述隔离结构的表面；
    以所述图形层为掩膜，刻蚀所述隔离结构，以形成所述第一凹槽。
  13. 根据权利要求12所述的半导体结构的制作方法，其中，形成图形层的步骤包括：
    形成第一硬掩膜层，所述第一硬掩膜层位于所述隔离结构的表面；
    形成第一中间层，所述第一中间层位于所述第一硬掩膜层的表面；
    形成第一掩膜图案，所述第一掩膜图案位于第一中间层的表面，所述第一掩膜图案沿所述第一方向间隔；
    以所述第一掩膜图案为掩膜刻蚀所述第一硬掩膜层及所述第一中间层，剩余所述第一硬掩膜层及所述第一中间层作为所述图形层。
  14. 根据权利要求13所述的半导体结构的制作方法，其中，形成所述第一掩膜图案的步骤包括：
    形成第二硬掩膜层，所述第二硬掩膜层位于所述第一中间层的表面；
    形成第二中间层，所述第二中间层位于所述第二硬掩膜层的表面；
    形成掩膜层，所述掩膜层位于所述第二中间层的表面；
    以所述掩膜层为掩膜刻蚀所述第二硬掩膜层及所述第二中间层，以形成间隔的所述第二硬掩膜层及所述第二中间层；
    形成侧墙层，所述侧墙层环绕所述第二硬掩膜层及所述第二中间层的侧壁；
    刻蚀所述侧墙层，以形成沿所述第一方向间隔的所述第一掩膜图案。
  15. 根据权利要求10所述的半导体结构的制作方法，其中，在形成所述第一栅极以及所述第二栅极之前，还包括：
    形成第二导电通道，所述第二导电通道沿所述第二方向延伸，且所述第二导电通道位于所述第一有源区远离所述第二有源区的外侧用于电性连接所述第一栅极。
  16. 根据权利要求10所述的半导体结构的制作方法，其中，所述基底还包括：第三有源区，所述第三有源区沿所述第二方向延伸，且沿所述第一方向间隔排布，所述第三有源区与所述第一有源区连接，所述第三有源区定义存储晶体管，所述第三有源区具有沿所述第二方向排布的第三源区、第三沟道区及第三漏区，形成所述第一栅极及所述第二栅极的过程中还包括：形成第三栅极，所述第三栅极覆盖所述第三沟道区。
PCT/CN2022/105292 2022-06-29 2022-07-12 半导体结构及其制作方法 WO2024000651A1 (zh)

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