WO2022188040A1 - 一种铁电晶体管、存储阵列、存储器及制备方法 - Google Patents

一种铁电晶体管、存储阵列、存储器及制备方法 Download PDF

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Publication number
WO2022188040A1
WO2022188040A1 PCT/CN2021/079825 CN2021079825W WO2022188040A1 WO 2022188040 A1 WO2022188040 A1 WO 2022188040A1 CN 2021079825 W CN2021079825 W CN 2021079825W WO 2022188040 A1 WO2022188040 A1 WO 2022188040A1
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metal layer
gate
layer
ferroelectric
ferroelectric transistor
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PCT/CN2021/079825
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English (en)
French (fr)
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黄凯亮
景蔚亮
冯君校
王正波
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华为技术有限公司
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Priority to PCT/CN2021/079825 priority Critical patent/WO2022188040A1/zh
Priority to CN202180085762.4A priority patent/CN116711084A/zh
Publication of WO2022188040A1 publication Critical patent/WO2022188040A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a ferroelectric transistor, a memory array, a memory and a preparation method.
  • FeFET ferroelectric field effect transistor
  • PCFET phase change transistor
  • magnetic field transistor magnetic field effect transistor
  • MFET magnetic field effect transistor
  • FeFET has gradually become the most commonly used mainstream transistor due to its fast switching speed, high storage density, long-term storage and radiation resistance.
  • FeFETs in the current stage are usually arranged in a planar manner, for example, by arranging the electrode regions side by side on the same plane.
  • the planar area occupied by a single FeFET is at least the sum of the areas of the electrode regions contained in the single FeFET.
  • each FeFET needs to occupy a large plane area, which obviously cannot meet the current demand for setting more FeFETs in a fixed-area storage array, which is not conducive to improving the storage density of the storage array. .
  • the present application provides a ferroelectric transistor to reduce the occupied area of the ferroelectric transistor.
  • the present application provides a ferroelectric transistor, a memory array, a memory and a preparation method, which are used to reduce the occupied area of the ferroelectric transistor.
  • the present application provides a ferroelectric transistor, comprising a gate metal layer, a ferroelectric dielectric layer and a channel layer stacked in sequence, and a drain metal layer and a source metal layer respectively contacting the channel layer; wherein the The gate metal layer, the drain metal layer and the source metal layer in the ferroelectric transistor are arranged in an overlapping manner and do not contact each other.
  • the projected area of each electrode region in a single ferroelectric transistor on the same plane that is, the plane area occupied by a single ferroelectric transistor
  • It is smaller than the sum of the projected areas of each electrode area, which effectively reduces the occupation area of a single ferroelectric transistor.
  • using ferroelectric transistors with smaller footprints to build a storage array also helps to arrange more ferroelectric transistors in a fixed-area storage array, effectively improving the storage density and storage capacity of the storage array.
  • each metal layer in the ferroelectric transistor can be routed to its corresponding electrode power supply on its own plane.
  • the electrode metal layer is connected to the drain power supply on the plane where it is located, and the source metal layer is connected to the source power supply on the same plane to reduce the difficulty of the multi-layer stack design of multiple ferroelectric transistors and increase the storage density and storage capacity. .
  • the ferroelectric transistor may further include a gate-tuning dielectric layer between the drain metal layer and the source metal layer, and a gate-tuning metal layer wrapped in the gate-tuning dielectric layer.
  • the gate-adjusting dielectric layer may contact the channel layer, the drain metal layer and the source metal layer respectively.
  • the gate-adjusting metal layer may be located on a different plane from the gate metal layer, the source metal layer and the drain metal layer, respectively.
  • the gate-adjusted metal layer can also be connected to the gate-adjusted power supply on the plane where it is located, without overlapping the traces of the gate metal layer, the source metal layer and the drain metal layer, which effectively reduces the risk of multi-layer stacked ferroelectric transistors. preparation difficulty.
  • the gate-adjusting dielectric layer may have an opening on a side away from the channel layer, and the gate-adjusting metal layer is enclosed in the opening.
  • the wrapping design can increase the contact area between the gate-tuned metal layer and the gate-tuned dielectric layer, and is convenient to improve the compensation speed of the source-drain current in the channel layer.
  • the ferroelectric transistors can be in columnar structures, such as cylinders. In this way, by arranging the ferroelectric transistors in a regular columnar structure, it is convenient to stack another ferroelectric transistor above or below one ferroelectric transistor, so as to obtain a memory array including multi-layer ferroelectric transistors and improve the storage capacity of the memory array. density and storage capacity.
  • the channel layer may be an annular trench, and the source metal layer and the drain metal layer may be connected through the annular trench, so as to form a source-drain current in the annular trench.
  • the annular groove could be type cross section
  • the source metal layer is set in type cross-section annular trench bottom
  • the drain metal layer is provided on The stepped bottom of the annular groove of the cross section. This kind of structure design helps to form the source-drain current in the vertical direction from the drain metal layer to the source metal layer in the annular trench.
  • the gate metal layer, the ferrodielectric layer and the channel layer can be nested in sequence to form a columnar structure, so as to increase the contact area between them, so that the channel layer can form a source-drain current faster.
  • the columnar structure may be a T-shaped column in order to achieve a regular structure of a ferroelectric transistor.
  • the drain metal layer and the source metal layer can be respectively annular structures with side surfaces flush with the side surfaces of the channel layer, so that the side surfaces of the entire ferroelectric transistor are flush, and it is convenient to arrange multiple ferroelectric transistors in rows and columns. Ferroelectric transistors.
  • an insulating layer may also be arranged between the channel layer and any metal layer, for example, a first insulating layer is arranged between the channel layer and the source metal layer, or the channel layer and the drain metal layer A second insulating layer is disposed therebetween.
  • the thickness of the first insulating layer or the second insulating layer may be smaller than the preset thickness, and the preset thickness is the minimum thickness capable of forming an effective current control in the channel layer by applying electricity to the gate metal layer.
  • the insulating layer of this thickness can not only effectively isolate the metal layer and the channel layer, but also try to avoid the metal layer caused by poor contact between the special metal element and the channel layer when the metal layer contains special metal elements. The phenomenon of a decrease in electrical conductivity.
  • an ohmic contact may also be formed between the channel layer and any metal layer, for example, a first ohmic contact is formed between the channel layer and the source metal layer, or the channel layer and the drain metal layer A second ohmic contact is formed therebetween, so that the conductive ions in the metal layer can more easily move toward the direction of the channel layer, thereby accelerating the current conduction between the metal layer and the channel layer.
  • the ferroelectric layer may consist of a ferroelectric material, as well as a metallic material and/or a conventional dielectric material, eg only a ferroelectric material, or a ferroelectric material and a metallic material, or a ferroelectric material
  • the material is composed of conventional dielectric materials, or composed of ferroelectric materials, metallic materials and conventional dielectric materials simultaneously.
  • the ferroelectric material may be a hafnium oxide material doped with one or more of silicon, zirconium, lanthanum, aluminum, yttrium, calcium, magnesium, strontium, erbium or rare earth elements.
  • the metallic material may be a conductive material composed of one or more of titanium nitride, titanium, gold, tungsten, molybdenum, oxides composed of tin and indium, aluminum, copper, ruthenium, or silver.
  • the conventional dielectric material may be an insulating material composed of one or more of silicon dioxide, aluminum oxide, hafnium dioxide, zirconium dioxide, titanium dioxide, yttrium oxide, or silicon nitride.
  • the gate-tuning dielectric layer may be composed of one or more of ferroelectric materials, metallic materials, or conventional dielectric materials.
  • the channel layer may be made of one or more of silicon, polysilicon, amorphous silicon, oxides composed of indium, gallium, and zinc, zinc oxide, indium tin oxide, titanium dioxide, or molybdenum disulfide Item element composition.
  • the gate metal layer, the source metal layer, the drain metal layer, or the gate metal layer may be composed of titanium nitride, titanium, gold, tungsten, molybdenum, oxides composed of tin and indium, One or more elements of aluminum, copper, ruthenium or silver.
  • the present application provides a memory array, comprising a plurality of ferroelectric transistors designed as provided in any one of the above-mentioned first aspects, and the plurality of ferroelectric transistors can be arranged in at least two rows, columns or stacks Arrange in the direction to form a storage array, for example, it can be arranged only in rows and columns, or only in rows and stacks, or only in columns and stacks to form a two-dimensional storage array, or it can be arranged in rows and columns at the same time. and stacked to form a three-dimensional storage array.
  • one or more ferroelectric transistors in the plurality of ferroelectric transistors may share the same gate tuning metal layer.
  • each ferroelectric transistor can independently adjust the read threshold according to its own requirements, which is suitable for scenarios where each ferroelectric transistor has different read threshold shifts.
  • the memory array can simultaneously compensate the read thresholds of multiple ferroelectric transistors in one gate-tuning operation, which is suitable for multiple ferroelectric transistors with the same read threshold shift. Scenes.
  • the ferroelectric transistors in the same row share the same source metal layer
  • the ferroelectric transistors in the same column share the same drain metal layer and the same gate metal layer for read control of each ferroelectric transistor.
  • the present application provides a memory, including the storage array provided by any one of the above-mentioned designs in the second aspect, and a storage controller coupled to the storage array.
  • the storage array can be used to store data, and the storage controller can write data to the storage array, or read data from the storage array.
  • the memory controller can also adjust one or more gate-tuning metal layers that share the gate-tuning metal layer through the gate-tuning metal layer read threshold of each ferroelectric transistor.
  • the present application provides an electronic device, comprising a printed circuit board (PCB) and the memory provided by any one of the designs in the above-mentioned third aspect, the memory being provided on the surface of the PCB.
  • PCB printed circuit board
  • the electronic devices include, but are not limited to: smart phones, smart watches, tablet computers, virtual reality (VR) devices, augmented reality (AR) devices, in-vehicle devices, desktop computers, personal computers, handheld computer or personal digital assistant.
  • VR virtual reality
  • AR augmented reality
  • the present application provides a method for preparing a ferroelectric transistor, the method comprising: firstly epitaxially extending a source metal layer and a gate-tuning dielectric layer, then depositing a gate-tuning metal layer on both sides of the gate-tuning dielectric layer, and then The gate-adjusting dielectric layer is epitaxially covered until the gate-adjusting metal layer is covered, and the drain metal layer is epitaxial on the gate-adjusting dielectric layer, and then the drain metal layer and the gate-adjusting dielectric layer are etched until the surface of the source metal layer is formed to form grooves.
  • a channel layer and a ferroelectric dielectric layer are sequentially epitaxial in the groove to form a nested structure with an upward opening, and finally a gate metal layer is deposited in the opening to obtain a ferroelectric transistor.
  • FIG. 1 exemplarily shows a schematic structural diagram of a ferroelectric transistor
  • FIG. 2 exemplarily shows a schematic structural diagram of a ferroelectric transistor provided by an embodiment of the present application
  • FIG. 3 exemplarily shows a schematic structural diagram of a ferroelectric dielectric layer provided by an embodiment of the present application
  • FIG. 4 exemplarily shows the correlation diagram between the read current and the read threshold of a ferroelectric transistor provided by an embodiment of the present application
  • FIG. 5 exemplarily shows a schematic structural diagram of a gate-tuning dielectric layer provided by an embodiment of the present application
  • FIG. 6 exemplarily shows a cross-sectional top view of a ferroelectric transistor provided by an embodiment of the present application
  • FIG. 7 exemplarily shows a schematic structural diagram of another ferroelectric transistor provided by an embodiment of the present application.
  • FIG. 8 exemplarily shows a schematic structural diagram of another ferroelectric transistor provided by an embodiment of the present application.
  • FIG. 9 exemplarily shows a flow chart of a method for preparing a ferroelectric transistor provided by an embodiment of the present application.
  • FIG. 10 exemplarily shows a schematic structural diagram of a storage array provided by an embodiment of the present application.
  • the traditional dynamic random access memory uses the amount of electric charge stored in the capacitor to represent the binary data to be stored, which requires additional capacitors, resulting in limited structural scaling capability, and the capacitor charging capacity is limited.
  • the long time required for discharge also results in a limited ability to improve access speed.
  • Existing DRAMs have reached saturation both in terms of structural design and access speed, making it difficult to further improve.
  • the traditional static random access memory (SRAM) requires about six transistors to form a storage unit. Under the condition of a certain storage area, the existing SRAM is extremely limited in storage density and storage capacity. .
  • Ferroelectric memories consist of one or more ferroelectric transistors. Ferroelectric transistors contain ferroelectric materials. By utilizing the characteristics that the spontaneous polarization direction of ferroelectric materials changes with the applied electric field, the ferroelectric transistors can efficiently complete data storage in about 1 nanosecond. Moreover, even if the applied electric field is removed after the data is stored, the spontaneous polarization direction of the ferroelectric material will not change, so the ferroelectric transistor can theoretically achieve an almost permanent retention time. It is precisely because of this characteristic of efficient data access and permanent data access, ferroelectric crystals have gradually become the most popular storage medium in current research.
  • FIG. 1 exemplarily shows a structure diagram of such a ferroelectric transistor.
  • the ferroelectric transistor includes a channel layer at the bottom, a source metal layer, a ferroelectric dielectric layer, and a drain metal layer that are laid on top of the channel layer in sequence without contacting each other, and a gate metal layer disposed over the ferrodielectric layer.
  • the source metal layer leads out pins on the upper surface of the source metal layer to connect to the source power supply VS (the source power supply VS is generally a ground circuit) to form the source of the ferroelectric transistor, and the gate metal layer is connected to the gate of the ferroelectric transistor.
  • the lead pin on the upper surface of the electrode metal layer is connected to the gate power supply V G to form the gate of the ferroelectric transistor, and the lead pin of the drain metal layer is connected to the drain power supply V D on the upper surface of the drain metal layer to form the iron The drain of the electrical transistor.
  • the ferroelectric transistor shown in FIG. 1 can realize data access according to the current flowing in the channel layer. Taking the n-channel ferroelectric transistor as an example to illustrate:
  • a source-drain voltage is applied between the source metal layer and the drain metal layer through the source power supply V S and the drain power supply V D in advance, so that the channel layer is formed by the drain metal layer.
  • the source-drain current flowing from the layer to the source metal layer is a horizontal current from right to left as shown in FIG. 1 .
  • the polarization state in the ferrodielectric layer will not change, so that the magnitude of the current in the channel layer is basically unchanged.
  • the current in the channel layer can be directly read. If the read current is greater than the reference current, it means that data "1" is currently stored. If the read current is less than the reference current, then Indicates that data "0" is currently stored.
  • the ferroelectric transistor shown in FIG. 1 can complete data access in the above manner, the ferroelectric transistor with this structure still has some difficult problems to overcome.
  • the ferroelectric transistor shown in Figure 1 is actually arranged in parallel with the source metal layer, the drain metal layer and the gate metal layer in the horizontal direction.
  • the characteristic length of the lithography is F
  • a single ferroelectric transistor A space of at least 3F is required in the horizontal direction shown in FIG. 1, and a space of at least F is required in the direction perpendicular to the horizontal direction shown in FIG. 1 (inward along the plane shown in FIG. 1). Therefore, A single ferroelectric transistor requires a layout area of at least 3F 2 (3F ⁇ F).
  • a ferroelectric transistor in the memory array needs at least 8F 2 (4F ⁇ 2F) layout area. It can be seen that the ferroelectric transistors shown in FIG. 1 need to occupy a large layout area.
  • ferroelectric transistor shown in FIG. 1 basically sets the source metal layer, the drain metal layer and the gate metal layer on the same plane, so that each metal region can only be routed above to connect the corresponding power supply.
  • the wiring of the multiple ferroelectric transistors is more complicated, which not only increases the difficulty of preparing the multi-layer stack, but also may cause the actual memory cell to exceed
  • the above-mentioned occupied area of 8F 2 further reduces the storage density and storage capacity of the storage array.
  • the present application provides a ferroelectric transistor that occupies a small area and is easy to stack and fabricate.
  • the ferroelectric transistor can be applied to a device with a data storage function, for example, it can be applied to a storage device that only has a data storage function, such as a memory, or can be applied to an electronic device that has a data storage function and also has other functions, such as Portable electronic devices with functions such as personal digital assistants and/or music players, such as mobile phones, tablet computers, wearable devices (such as smart watches) with wireless communication functions, or in-vehicle devices.
  • Exemplary embodiments of portable electronic devices include, but are not limited to, carry-on Or portable electronic devices with other operating systems.
  • the aforementioned portable electronic device may also be, for example, a laptop computer (Laptop) having a touch-sensitive surface (eg, a touch panel).
  • the above-mentioned electronic device may also be a desktop computer having a touch-sensitive surface (eg, a touch panel).
  • FIG. 2 exemplarily shows a schematic structural diagram of a ferroelectric transistor provided by an embodiment of the present application.
  • the ferroelectric transistor includes a gate metal layer, a ferroelectric dielectric layer, and a channel layer stacked in sequence, and further includes The drain metal layer and the source metal layer of the channel layer are respectively contacted, and the gate metal layer, the drain metal layer and the source metal layer overlap up and down without contacting each other.
  • the gate metal layer, the drain metal layer and the source metal layer are overlapped up and down, which may refer to the overlapping of the gate metal layer at the top, the drain metal layer at the middle, and the source metal layer at the bottom, or Refers to the overlap where the gate metal layer is at the top, the source metal layer is in the middle, and the drain metal layer is at the bottom. It can also mean that the drain metal layer is at the top, the source metal layer is in the middle, and the gate The metal layer is at the bottom of the overlap, and so on.
  • Overlapping may mean that the partial areas of the three metal layers overlap with each other, or that the entire areas of the three metal layers overlap each other, or that a partial area of one of the metal layers overlaps with one or two other metal layers.
  • a single ferroelectric transistor can occupy only 1F of space in the horizontal direction shown in FIG. 2, and can only occupy 1F of space in the inward direction of the plane shown in FIG. 2. Therefore, the space shown in FIG. 2 A single ferroelectric transistor with the structure shown in FIG.
  • 1 can only occupy a layout area of 1F 2 (1F ⁇ 1F), which can save about 2/3 of the layout area compared with a single ferroelectric transistor with the structure shown in FIG. 1 .
  • a plurality of ferroelectric transistors form a memory array according to the horizontal and inward directions shown in FIG. 2, if there is a space of F between two adjacent ferroelectric transistors, one ferroelectric transistor in the memory array will be in the memory array.
  • the horizontal direction shown in FIG. 2 can occupy only 2F of space, and the inward direction of the plane shown in FIG. 2 can only occupy 2F of space. Therefore, the ferroelectric transistor of the structure shown in FIG. 2 can be used in the memory array.
  • the ferroelectric dielectric layer may be composed of a ferroelectric material, or a ferroelectric material and one or more other dielectric materials (such as metal materials or conventional materials).
  • Figure 3 A schematic diagram of the structure of a ferrodielectric layer, as shown in Figure 3:
  • the ferroelectric layer may be composed of only the ferroelectric material as shown in (A) in FIG. 3 ; or the ferroelectric layer may be composed of both the ferroelectric material and the metal material as shown in (B) in FIG. 3 ; or The ferroelectric dielectric layer may also be composed of ferroelectric materials and conventional dielectric materials at the same time as shown in (C) in FIG. 3 ; or the ferroelectric dielectric layer may be composed of ferroelectric materials, It is composed of metal materials and conventional dielectric materials.
  • the ferroelectric material may refer to a metal or metal oxide material doped with one or more elements of silicon, zirconium, lanthanum, aluminum, yttrium, calcium, magnesium, strontium, erbium and rare earth elements, such as hafnium oxide , zirconium oxide, tantalum oxide, zirconium and hafnium, etc., can also be lead zirconate titanate, barium strontium titanate or transition metal oxides doped with one or more of the above elements, or can be other similar polar A material with properties that change the electric field with applied gate voltage.
  • Metal materials refer to conductive materials composed of metal elements, metal-containing alloys or other compositions, such as including but not limited to titanium nitride, titanium, gold, tungsten, molybdenum, oxides composed of tin and indium, aluminum, copper, Ruthenium or silver etc.
  • the conventional dielectric material refers to an insulating material composed of one or more of silicon dioxide, aluminum oxide, hafnium dioxide, zirconium dioxide, titanium dioxide, yttrium oxide, silicon nitride or other insulating elements.
  • the gate metal layer, the drain metal layer, or the source metal layer may be composed of conductive materials such as metal elements, metal-containing alloys, or other compositions, such as but not limited to titanium nitride, titanium, gold, Tungsten, molybdenum, oxides composed of tin and indium, aluminum, copper, ruthenium or silver, etc.
  • the gate metal layer, the drain metal layer and the source metal layer are respectively used to form the gate, drain and source of the ferroelectric transistor. Exemplarily, continuing to refer to FIG. 2 , by arranging the gate metal layer, the drain metal layer and the source metal layer on top of each other, the gate metal layer, the drain metal layer and the source metal layer can be located at different positions respectively.
  • the gate metal layer When connecting the power supply of each electrode, the gate metal layer can be connected to the gate power supply (V G ) horizontally on the plane to form the gate of the ferroelectric transistor, and the drain metal layer can be horizontal on the plane.
  • the trace is connected to the drain power supply (V D ) to form the drain of the ferroelectric transistor, and the source metal layer can be horizontally traced to the source power supply (V S ) on the same plane to form the source of the ferroelectric transistor.
  • the channel layer may be composed of one or more semiconductor materials, such as, but not limited to, single crystal semiconductors such as silicon, polysilicon or amorphous silicon, oxides composed of indium, gallium and zinc, oxide Oxide semiconductors such as zinc, indium tin oxide or titanium dioxide, and low-dimensional thin-film semiconductors such as molybdenum disulfide, etc.
  • the channel layer is used to form a conductive channel.
  • the drain metal layer and the source metal layer are overlapped as shown in FIG. 2, the source-drain current flowing from the drain metal layer to the source metal layer flows vertically in the channel layer shown in FIG. A conductive channel in a vertical direction is formed, therefore, the ferroelectric transistor with the structure shown in FIG. 2 is also called a ferroelectric transistor with a vertical structure.
  • the ferroelectric transistor shown in Figure 2 can realize data access according to the magnitude of the source-drain current flowing in the channel layer, for example:
  • a source-drain voltage is applied between the source metal layer and the drain metal layer through the source power supply V S and the drain power supply V D in advance, so that a vertical direction flowing from the drain metal layer to the source metal layer is formed in the channel layer. source-drain current.
  • a forward gate voltage greater than the ferroelectric switching voltage of the ferroelectric transistor
  • V G the gate power supply
  • the source-drain current in the layer increases, and when the increase is greater than the preset reference current, the ferroelectric transistor successfully stores the data "1".
  • a negative gate voltage greater than the ferroelectric switching voltage of the ferroelectric transistor
  • V G the gate power supply V G
  • the negative gate voltage will be generated in the ferroelectric dielectric layer from the channel layer to the gate
  • the polarized electric field on the bottom surface of the polar metal layer causes the ferroelectric dielectric layer to repel electrons in the channel layer downward under the action of the electric field, resulting in a decrease in the concentration of charge carriers in the channel layer, and an increase in the resistance of the channel layer.
  • the source-drain current in the channel layer is reduced, and when the reduction is smaller than the preset reference current, the ferroelectric transistor successfully stores the data "0". After the data is successfully stored, even if the forward gate voltage or the negative gate voltage is removed, the polarization state in the ferrodielectric layer will not change, so that the magnitude of the current in the channel layer is basically unchanged. In this way, when reading data, the current in the channel layer can be directly read. If the read current is greater than the reference current, it means that data "1" is stored in the ferroelectric transistor. If the read current is less than the reference current current, it means that data "0" is stored in the ferroelectric transistor.
  • the ferroelectric transistor has a read threshold when reading data, and the read threshold and the gate voltage work together to affect the "0-1" judgment of the data stored in the ferroelectric transistor.
  • the normal read threshold is a fixed value.
  • the ferroelectric dielectric layer may experience fatigue phenomenon, which leads to the readout of the ferroelectric transistor.
  • the threshold value drifts.
  • FIG. 4 exemplarily shows the relationship between the read current and the read threshold in a ferroelectric transistor provided by an embodiment of the present application, wherein (A) in FIG.
  • the source-drain current increases with the increase of the gate voltage, and decreases with the decrease of the gate voltage.
  • the polarizing electric field of the ferroelectric layer towards the channel layer produces a source-drain current in the channel layer that is greater than the reference current, so that "1" is stored in the ferroelectric transistor, while the ferroelectric layer
  • the polarized electric field towards the gate metal layer produces a source-drain current in the channel layer that is smaller than the reference current, "0" is stored in the ferroelectric transistor.
  • the source-drain current corresponding to storing "1" in the ferroelectric transistor is distributed on the right side of the reference current
  • the source-drain current corresponding to storing "0" in the ferroelectric transistor is distributed on the left side of the reference current side, as shown by the solid line in (B) in FIG. 4 .
  • the correlation curve between the source-drain current and the gate voltage tends to (A) in FIG. 4 .
  • the left side drift as shown makes the source-drain current at the original gate voltage larger.
  • the source-drain current in the channel layer is smaller than the reference current, but larger
  • the actually read source-drain current will be larger than the reference current, resulting in the storage of the ferroelectric transistor in the ferroelectric transistor.
  • the data is misjudged as "1".
  • the source-drain current is no longer the source-drain current corresponding to the originally stored data, but may be smaller than the source-drain current when "1" was originally stored, or smaller than that when "1" was originally stored.
  • the source-drain current at 0” is large, which causes the window between the source-drain current and the reference current to become smaller or even disappear, which affects the accuracy of the ferroelectric transistor reading.
  • the ferroelectric transistor may further include a drain metal layer and a source metal layer. A gate-adjusting dielectric layer therebetween, and a gate-adjusting metal layer wrapped in the gate-adjusting dielectric layer.
  • the gate-tuning dielectric layer contacts the channel layer, the drain metal layer and the source metal layer respectively, and the gate-tuning metal layer is used to connect the gate-tuning power supply V T to form the gate-tuning electrode of the ferroelectric transistor.
  • a forward gate-tuning voltage can be applied to the gate-tuning metal layer through the gate-tuning power supply V T to drive the gate-tuning dielectric layer to attract electrons in the channel layer.
  • the resistance of the channel layer becomes smaller, and the source-drain current in the channel layer increases.
  • the source-drain current in the channel layer can be reversely compensated under the condition of read threshold shift, which helps to improve the read accuracy of the ferroelectric transistor.
  • the above only takes the overall shift of the read threshold value to the left or the overall right to the right as an example to exemplarily introduce a specific implementation process of a gate tuning scheme.
  • the drift of the read threshold may not be in a fixed direction.
  • the ferroelectric transistor can also choose different compensation methods according to the specific stored data.
  • the specific implementation process of the compensation in this manner the above solution may be directly referred to, which will not be repeated in this application.
  • the gate-tuning dielectric layer may be composed of one or more of ferroelectric materials, metal materials, conventional dielectric materials, or other dielectric materials that can control the concentration of ions in the channel layer, as shown in FIG. 5 .
  • a schematic structural diagram of a gate-tuning dielectric layer provided by an embodiment of the present application is shown in FIG. 5 :
  • the gate-tuning dielectric layer may be composed of only ferroelectric materials as shown in (A) in FIG. 5 ; or the gate-tuning dielectric layer may be composed of only metal materials as shown in (B) in FIG. 5 ; or The dielectric layer can also be composed of only conventional dielectric materials as shown in (C) in FIG. 5 ; or the gate-tuning dielectric layer can be composed of ferroelectric materials and metal materials at the same time as shown in (D) in FIG. 5 ; Alternatively, the gate-tuning dielectric layer may also be composed of a ferroelectric material and a conventional dielectric material as shown in (E) in FIG. 5 ; or the gate-tuning dielectric layer may also be composed of a metal as shown in (F) in FIG. materials and conventional dielectric materials; or the gate-adjusting dielectric layer may also be composed of ferroelectric materials, metal materials and conventional dielectric materials at the same time as shown in (G) in FIG. 5 .
  • the gate-adjusting metal layer may be composed of conductive materials such as metal elements, metal-containing alloys, or other compositions, such as, but not limited to, titanium nitride, titanium, gold, tungsten, molybdenum, tin and indium. oxides, aluminum, copper, ruthenium or silver, etc.
  • the gate-tuning metal layer may also be located on a different plane from the gate metal layer, the source metal layer and the drain metal layer.
  • the gate-tuning The metal layer can also be routed to the gate-adjusted power supply at the level of the plane where it is located to form the gate-adjusted electrode of the ferroelectric transistor, which further reduces the difficulty of fabrication of the multi-layer stacked ferroelectric transistor.
  • the ferroelectric transistor may exhibit a columnar structure, such as a cylinder.
  • FIG. 6 exemplarily shows a cross-sectional top view of a ferroelectric transistor provided by an embodiment of the present application, and the cross-sectional top view is obtained by cutting the ferroelectric transistor along the cross-section P1 shown in FIG. 2 .
  • FIG. 2 can correspond to the cross-sectional front view obtained by cutting the ferroelectric transistor along the diameter of the circular surface corresponding to the cylinder.
  • one ferroelectric transistor can be directly stacked above or below another ferroelectric transistor, which is convenient to realize the stacking design of multiple ferroelectric transistors, and obtains a multi-layer ferroelectric transistor including multi-layer ferroelectric transistors.
  • the storage array can improve the storage density and storage capacity of the storage array.
  • the gate metal layer, the ferroelectric dielectric layer and the channel layer can be nested in sequence to form a columnar structure, such as sequentially
  • the nesting constitutes a T-shaped column as shown in Figure 2, or the nesting constitutes an L-shaped column, a U-shaped column or a cylinder in sequence.
  • the gate metal layer may be configured as a T-shaped cylinder as shown in FIG. 2 , or may be other columnar structures, such as a cylinder.
  • the ferrodielectric layer and the channel layer can be arranged as shown in Figure 2 It can also be set to other ring structures or columnar structures that can nest gate metal layers, such as the ferroelectric dielectric layer and the channel layer are set as U-shaped rings, or the ferroelectric dielectric layer is set as a U-shaped ring and the channel layer is set as a U-shaped ring. Layer is set to ring, or the ferrodielectric layer is set as a T-shaped cylinder and the channel layer is set as ring, etc., which are not specifically limited;
  • the source metal layer and the drain metal layer can be connected in a vertical direction through the ring-shaped trench.
  • the source metal layer can be arranged in type annular trench bottom, the drain metal layer can be arranged on In this way, the source-drain current can flow through the drain metal layer and the The stepped bottom of the annular groove, and then flows in the vertical direction to the bottom of the annular trench, and then flow to the source metal layer, where A vertical conductive channel is formed in the annular groove;
  • the drain metal layer may be arranged in a ring structure, such as a columnar ring as illustrated in FIG. 2 and FIG. 6 .
  • the source metal layer may be arranged in a columnar structure, such as the columns shown in FIG. 2 and FIG. 6 .
  • each layer in the ferroelectric transistor can be flush with the sides, that is, the side of the drain metal layer, the side of the source metal layer, the side of the channel layer, the side of the gate-tuning dielectric layer, the side of the gate-tuning layer.
  • an annular accommodating space may be formed between the channel layer, the source metal layer and the drain metal layer, such as the columnar ring shown in FIG. 2 and FIG. 6 .
  • the gate-adjusting dielectric layer may surround the inner wall of the columnar ring, and respectively contact the channel layer, the source metal layer and the drain metal layer.
  • the gate-adjustment dielectric layer may also have an opening on the side away from the channel layer, and the opening is used to wrap the gate-adjustment metal layer.
  • an ohmic contact may also be formed between the channel layer and any metal layer (source metal layer or drain metal layer), for example, a first ohmic contact may be formed between the channel layer and the source metal layer An ohmic contact forms a second ohmic contact between the channel layer and the drain metal layer.
  • the conductive ions in the metal layer can more easily move toward the direction of the channel layer, which helps to accelerate the current conduction between the metal layer and the channel layer.
  • an insulating layer may also be arranged between the channel layer and any metal layer, for example, a first insulating layer is arranged between the channel layer and the source metal layer, and the channel layer and the drain metal layer A second insulating layer is provided between the layers.
  • the thickness of the insulating layer may be smaller than the minimum thickness of the channel layer to form effective current control by applying electricity to the gate metal layer, and may be set to a value between 0.1 nm and 2 nm (distance unit, ie nanometer). In this way, the insulating layer of this thickness can not only effectively isolate the metal layer and the channel layer, try to avoid the diffusion of conductive ions in the metal layer to the channel layer, and maintain the conductivity of the metal layer.
  • the problem that the electrical conductivity of the metal layer is degraded ie, the Fermi pinning problem
  • the above-mentioned embodiment is only an example of stacking a gate metal layer, a ferroelectric dielectric layer and a channel layer in sequence in the upper and lower directions, and introduces a specific structure of a ferroelectric transistor.
  • This application does not limit the gate metal layer, The ferrodielectric layer and the channel layer can only have such a stacked structure.
  • the gate metal layer, the ferroelectric dielectric layer, and the channel layer may also be stacked in a left-right direction, a front-rear direction, or even an oblique direction.
  • the following is an example to introduce a ferroelectric transistor obtained by stacking a gate metal layer, a ferroelectric dielectric layer and a channel layer in the left-right direction with the second embodiment.
  • FIG. 7 exemplarily shows a schematic structural diagram of another ferroelectric transistor provided by an embodiment of the present application.
  • the ferroelectric transistor has a cylindrical structure as a whole, wherein (A) in FIG. 7 shows that the A cross-sectional front view of the ferroelectric transistor obtained, and FIG. 7(B) shows a cross-sectional top view obtained by cutting the ferroelectric transistor along the P 2 plane indicated in FIG. 7(A) . As shown in FIG. 7(A) and FIG.
  • the ferroelectric transistor includes a gate metal layer, a ferrodielectric layer, and a channel layer sequentially stacked to the left, and further includes contacting The drain metal layer and the source metal layer of the channel layer, the drain metal layer, the gate metal layer and the source metal layer are sequentially overlapped from top to bottom and are not in contact with each other.
  • the gate metal layer shown in FIG. 7 has the same structure as the gate-tuned metal layer shown in FIG. 2 in the first embodiment
  • the ferroelectric dielectric layer shown in FIG. 7 has the same structure as the gate-tuned dielectric shown in FIG. 2 in the first embodiment.
  • the layers have the same structure.
  • the ferroelectric transistor may further include a gate-tuned metal layer and a gate-tuned dielectric layer that are stacked downward in sequence, and a lower bottom surface of the gate-tuned dielectric layer is nested in the channel layer.
  • the gate-tuning metal layer shown in FIG. 7 has the same structure as the gate metal layer shown in FIG. 2 in the first embodiment, and the gate-tuning dielectric layer shown in FIG. 7 has the same structure as the ferroelectric dielectric shown in FIG. 2 in the first embodiment.
  • the layers have the same structure.
  • the ferroelectric transistor shown in FIG. 7 uses the gate metal layer and the ferroelectric dielectric layer to access data
  • how to use the gate-tuned metal layer and the gate-tuned dielectric layer to adjust the read threshold please refer to the above-mentioned first embodiment for details, here It will not be repeated.
  • the above-mentioned first and second embodiments only take the example of arranging the gate metal layer, the drain dielectric layer and the source metal layer in order from top to bottom to introduce the specific structure of the ferroelectric transistor.
  • This application It is not limited that the gate metal layer, the drain dielectric layer and the source metal layer can only be arranged in a top-to-bottom order.
  • the gate metal layer, the source dielectric layer and the drain metal layer can also be arranged in a top-to-bottom order overlappingly, or in a top-down order.
  • the source dielectric layer, the drain metal layer, and the gate metal layer are distributed, or the drain dielectric layer, the source metal layer, and the gate metal layer are sequentially overlapped and arranged in a top-to-bottom order, and so on.
  • the following is an example to introduce a ferroelectric transistor obtained by overlapping and arranging a gate metal layer, a source dielectric layer and a drain metal layer in order from top to bottom in the third embodiment.
  • FIG. 8 exemplarily shows a schematic structural diagram of another ferroelectric transistor provided by an embodiment of the present application.
  • the ferroelectric transistor has a cylindrical structure as a whole, wherein (A) in FIG. 8 shows that the ferroelectric transistor is cut according to the diameter of the cylindrical surface A cross-sectional front view of the ferroelectric transistor obtained, and FIG. 8(B) shows a cross-sectional top view obtained by cutting the ferroelectric transistor along the P3 plane indicated in FIG. 8(A) . As shown in FIG. 8(A) and FIG.
  • the ferroelectric transistor includes a gate metal layer, a ferrodielectric layer, and a channel layer that are sequentially stacked downward, and further includes contacting The source metal layer and the drain metal layer of the channel layer, the gate metal layer, the source metal layer and the drain metal layer are sequentially overlapped from top to bottom and do not contact each other.
  • the ferroelectric transistor may further include a gate-tuned metal layer and a gate-tuned dielectric layer stacked to the left in sequence, and the left side of the gate-tuned dielectric layer is nested in the channel layer.
  • each layer shown in FIG. 8 has the same structure as each layer shown in FIG. 2 in the first embodiment.
  • the ferroelectric transistor shown in FIG. 8 uses the gate metal layer and the ferroelectric dielectric layer to access data, and how to use the gate-tuned metal layer and the gate-tuned dielectric layer to adjust the read threshold, please refer to the above-mentioned first embodiment for details, here It will not be repeated.
  • FIG. 2 , FIG. 6 , FIG. 7 , and FIG. 8 are merely examples to introduce three possible structures of ferroelectric transistors.
  • the present application does not limit that the ferroelectric transistor must have this kind of structure. Any ferroelectric transistors capable of arranging the electrode regions up and down overlapping each other are within the protection scope of the present application, and the present application will not list them one by one.
  • FIG. 9 exemplarily shows a structure diagram of a process for preparing a ferroelectric transistor provided by an embodiment of the present application. As shown in FIG. 9 , the preparation process includes:
  • Step 1 epitaxial source metal layer to obtain a structure as shown in (A) in FIG. 9 ;
  • Step 2 epitaxially adjust the gate dielectric layer above the source metal layer to obtain a structure as shown in (B) in FIG. 9 ;
  • Step 3 depositing a gate tuning metal at intervals on the left and right sides above the gate tuning dielectric layer to obtain a structure as shown in (C) in FIG. 9 ;
  • Step 4 epitaxial gate tuning dielectric layer until the gate tuning metal on both sides is completely wrapped to obtain a structure as shown in (D) in FIG. 9 ;
  • Step 5 grinding the surface of the gate-adjusting dielectric layer to be flat and free of scratches by chemical mechanical polishing (chemical mechanical polishing, CMP) technology, to obtain a structure as shown in (E) in FIG. 9 ;
  • CMP chemical mechanical polishing
  • step 6 the drain metal layer is epitaxial on the top of the gate-adjusting dielectric layer to obtain a structure as shown in (F) in FIG. 9 ;
  • Step 7 Avoid the gate tuning metal on both sides, and sequentially etch the drain metal layer and the gate tuning dielectric layer until the upper surface of the source metal layer, so that the remaining drain metal layer, gate tuning dielectric layer and source metal layer are etched. An accommodating groove is formed between them to obtain a structure as shown in (G) in FIG. 9 ;
  • Step 8 Epitaxial channel material is formed in the interior of the accommodating groove to form a channel layer that is open upward to obtain a structure as shown in (H) in FIG. 9 ;
  • Step 9 nesting a ferroelectric dielectric on the opening and the upper surface of the channel layer to form a ferroelectric dielectric layer with an upward opening to obtain a structure as shown in (I) in FIG. 9 ;
  • step ten the gate metal is filled in the opening and the upper surface of the ferrodielectric layer, so as to obtain a structure in which the side faces are flush with the ferrodielectric layer as shown in (J 1 ) in FIG. 9 , or as shown in FIG. 2 ) A structure in which the side surface is slightly shorter than the ferrodielectric layer is obtained, or a structure in which the side surface is slightly longer than the ferrodielectric layer is obtained as shown in (J 3 ) in FIG. 9 .
  • a memory array can also be obtained by combining a plurality of ferroelectric transistors in at least two directions of rows, columns or stacks.
  • FIG. 10 exemplarily shows a schematic structural diagram of a memory array provided by an embodiment of the present application, where the memory array is obtained by combining four ferroelectric transistors as shown in FIG. 2 and FIG. 6 according to the row and column directions.
  • (A) in FIG. 10 shows a cross-sectional front view of the memory array
  • (B) in FIG. 10 shows a cross-sectional side view of the memory array
  • two ferroelectric transistors in the same row share the same source, such as the source metal layer of the ferroelectric transistor FeFET11 and the source metal layer of the ferroelectric transistor FeFET12 in the first row
  • the layers are connected to the same source power supply V S1
  • the source metal layer of the ferroelectric transistor FeFET21 and the source metal layer of the ferroelectric transistor FeFET22 in the second row are connected to the same source power supply V S2 .
  • Two ferroelectric transistors in the same column share the same drain and the same gate, for example, the drain metal layer of the ferroelectric transistor FeFET11 and the drain metal layer of the ferroelectric transistor FeFET21 in the first column are connected to the same drain power supply V D1 , the gate metal layer of the ferroelectric transistor FeFET11 in the first column and the gate metal layer of the ferroelectric transistor FeFET21 are connected to the same gate power supply V G1 , the drain metal layer of the ferroelectric transistor FeFET12 in the second column and The drain metal layer of the ferroelectric transistor FeFET22 is connected to the same drain supply V D2 , and the gate metal layer of the ferroelectric transistor FeFET12 and the gate metal layer of the ferroelectric transistor FeFET22 in the second column are connected to the same gate supply V G2 .
  • the storage array may be connected to a storage controller, for example, each electrode power supply in the storage array is connected to the storage controller.
  • the memory controller can first pass the source power supply V S2 corresponding to the second row Turn on the ferroelectric transistor FeFET21 and the ferroelectric transistor FeFET22 in the second row, and then turn on the ferroelectric transistor FeFET12 and the ferroelectric transistor FeFET22 in the second column through the drain power supply V D2 corresponding to the second column, so that the second row A conductive channel is formed in the channel layer of the ferroelectric transistor FeFET22 at the second column, and then a positive gate voltage or a negative gate voltage is applied to the turned-on ferroelectric transistor FeFET22 through the gate power supply V S2 corresponding to the second column, to successfully write data.
  • the memory controller can sequentially control the source corresponding to the second row according to the same operation.
  • the power supply V S2 and the drain power supply V D2 corresponding to the second column are used to turn on the ferroelectric transistor FeFET22 at the second row and the second column, and then a read operation is performed in the turned-on ferroelectric transistor FeFET22.
  • At least two ferroelectric transistors in the plurality of ferroelectric transistors may share the same gate tuning metal layer.
  • four ferroelectric transistors are all connected together through a gate-tuned metal, in which case the four ferroelectric transistors may share the same gate-tuned metal.
  • the memory controller can simultaneously compensate the read thresholds of four ferroelectric transistors through one gate adjustment operation, and this solution can be applied to scenarios where multiple ferroelectric transistors have the same read threshold shift. It should be understood that the at least two ferroelectric transistors sharing the same tuning gate is only an optional implementation.
  • the tuning gates of any two ferroelectric transistors can also be separated by a tuning gate dielectric layer, so that each ferroelectric transistor has its own corresponding tuning gate. In this way, each ferroelectric transistor has its own tuning gate. All electric transistors can individually adjust the read threshold according to their own needs, so as to be suitable for scenarios where each ferroelectric transistor has different read threshold drifts.
  • FIG. 10 only takes the combination of multiple ferroelectric memories in the row and column directions as an example to introduce the specific structure of the memory array, and the memory array assembled in this way has a single-layer structure.
  • the present application can also stack ferroelectric transistors to obtain a memory array with a multi-layer structure, such as combining two directions of row and stack, or combining two directions of column and stack to form a two-dimensional multi-layer structure.
  • the storage array is combined according to the three directions of row, column and stack to form a three-dimensional storage array with a multi-layer structure, which further improves the storage density and storage capacity of the storage array.
  • the memory array in the present application can also be a stack of existing ferroelectric transistors, as well as the ferroelectric transistors shown in FIGS. 2 and 6 , the ferroelectric transistors shown in FIG. 7 or the ferroelectric transistors shown in FIG. 8 .
  • This is obtained by stacking the ferroelectric transistor illustrated in FIGS. 2 and 6 under the ferroelectric transistor illustrated in FIG. 1 . It can be seen that by setting such a regular ferroelectric transistor structure, it is also easy to realize the stacking design with the ferroelectric transistors with irregular structures in the prior art, and on the basis of not overturning the existing memory array, increase the ferroelectric transistor included in the memory array. increase the storage density and storage capacity of the storage array.
  • the present application also provides a memory, which includes the storage array as described above, and a storage controller coupled to the storage array, where the storage controller is configured to read and write data in the storage array.
  • the memory controller may further adjust one or more of the shared gate-tuning metal layers through the gate-tuning metal layer read threshold of each ferroelectric transistor.
  • the present application also provides a chip, including a substrate and the memory as described in the above content, where the memory is arranged on the substrate.
  • the present application also provides an electronic device including the memory or chip as described above.
  • the present application also provides a computer program product, the computer program product includes: computer program code, when the computer program code runs on a computer, the computer is made to execute the storage described in the above content. The method executed by the controller.
  • the present application also provides a computer-readable storage medium, where the computer-readable medium stores program codes, and when the program codes are run on a computer, the computer is made to execute the above-mentioned contents.

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Abstract

一种铁电晶体管、存储阵列、存储器及制备方法，用以降低铁电晶体管的占用面积。铁电晶体管包括依次层叠的栅极金属层、铁电介质层和沟道层，以及分别接触沟道层的漏极金属层和源极金属层，其中，栅极金属层、漏极金属层和源极金属层呈上下重叠排布且互不接触。通过部分重叠或全部重叠铁电晶体管中的各电极区域，能有效降低单个铁电晶体管的占用面积，有助于在固定面积的存储阵列中布局更多的铁电晶体管，有效提高存储阵列的存储密度。

Description

一种铁电晶体管、存储阵列、存储器及制备方法 技术领域
本申请涉及半导体技术领域，尤其涉及一种铁电晶体管、存储阵列、存储器及制备方法。
背景技术
近年来，随着半导体技术的发展与普及，众多新型晶体管也不断涌现，如铁电晶体管(ferroelectric field effect transistor，FeFET)、相变晶体管(phase change field effect transistor，PCFET)和磁性晶体管(magnetic field effect transistor，MFET)等。这些新型晶体管具有更小的尺寸，并能以更低的功耗实现更快的存取速度，在半导体领域中得到越来越广泛的应用。
在众多新型晶体管中，FeFET由于其快速的开关切换速度、较高的存储密度、长久存储性及抗辐射等优点，逐渐成为目前最常用的一种主流晶体管。然而，现阶段中的FeFET通常按照平面方式布局各电极区域，如将各电极区域并列排布在同一平面上。在这种情况下，单个FeFET所占用的平面面积至少为单个FeFET中包含的各电极区域的面积之和。按照现有的FeFET排布方式，每个FeFET都需要占用较大的平面面积，这显然无法满足现阶段对在固定面积的存储阵列中设置更多FeFET的需求，不利于提高存储阵列的存储密度。
有鉴于此，本申请提供一种铁电晶体管，用以降低铁电晶体管的占用面积。
发明内容
本申请提供一种铁电晶体管、存储阵列、存储器及制备方法，用以降低铁电晶体管的占用面积。
第一方面，本申请提供一种铁电晶体管，包括依次层叠的栅极金属层、铁电介质层和沟道层，以及分别接触沟道层的漏极金属层和源极金属层；其中，该铁电晶体管中的栅极金属层、漏极金属层和源极金属层呈上下重叠排布且互不接触。在该设计中，通过部分重叠或全部重叠铁电晶体管中的各电极区域，能使单个铁电晶体管中的各电极区域在同一平面上的投影面积(即单个铁电晶体管所占用的平面面积)小于各电极区域的投影面积之和，有效降低单个铁电晶体管的占用面积。更进一步的，使用占用面积更小的铁电晶体管构建存储阵列，还有助于在固定面积的存储阵列中布局更多的铁电晶体管，有效提高存储阵列的存储密度和存储容量。
在一种可能的设计中，铁电晶体管中的各金属层可以分别在各自所在的平面上走线至各自对应的电极电源，如栅极金属层在所在平面上走线连接栅极电源，漏极金属层在所在平面上走线连接漏极电源，源极金属层在所在平面上走线连接源极电源，以降低多个铁电晶体管多层堆叠设计的难度，增大存储密度和存储容量。
在一种可能的设计中，铁电晶体管还可以包括位于漏极金属层和源极金属层之间的调栅介质层、以及包裹在该调栅介质层内的调栅金属层。其中，调栅介质层可以分别接触沟道层、漏极金属层和源极金属层。在该设计中，通过设置调栅金属层和调栅介质层，能在 读取阈值漂移的情况下对沟道层中的源漏电流进行反向补偿，有助于提高铁电晶体管的读取准确性。
在一种可能的设计中，调栅金属层可以分别与栅极金属层、源极金属层和漏极金属层位于不同的平面。如此，调栅金属层也可以在所在平面上走线连接调栅电源，而无需与栅极金属层、源极金属层和漏极金属层的走线交叠，有效降低多层堆叠铁电晶体管的制备难度。
在一种可能的设计中，调栅介质层可以在背离沟道层的一侧开设开口，该开口内包裹调栅金属层。该种包裹设计能增加调栅金属层与调栅介质层之间的接触面积，便于提高对沟道层中的源漏电流的补偿速度。
在一种可能的设计中，铁电晶体管可以呈柱状结构，如圆柱。如此，通过将铁电晶体管设置为规则的柱状结构，能便于在一个铁电晶体管的上方或下发堆叠另一铁电晶体管，以获得包括多层铁电晶体管的存储阵列，提高存储阵列的存储密度和存储容量。
在一种可能的设计中，沟道层可以为环状沟槽，源极金属层和漏极金属层可以通过环状沟槽实现联通，以便在环状沟槽中形成源漏电流。
在一种可能的设计中，环状沟槽可以呈
Figure PCTCN2021079825-appb-000001
型截面，源极金属层设置在
Figure PCTCN2021079825-appb-000002
型截面的环状沟槽的槽底，而漏极金属层设置在
Figure PCTCN2021079825-appb-000003
型截面的环状沟槽的台阶底。该种结构设计有助于在环状沟槽中形成从漏极金属层指向源极金属层的竖直方向的源漏电流。
在一种可能的设计中，栅极金属层、铁电介质层和沟道层可以依次嵌套构成柱状结构，以提高相互之间的接触面积，便于沟道层能更快形成源漏电流。
在一种可能的设计中，柱状结构可以为T型圆柱，以便实现铁电晶体管的规则结构。
在一种可能的设计中，漏极金属层和源极金属层可以分别为侧面与沟道层的侧面平齐的环状结构，以便整个铁电晶体管的侧面平齐，便于行列排布多个铁电晶体管。
在一种可能的设计中，沟道层与任一金属层之间还可以设置绝缘层，如沟道层与源极金属层之间设置第一绝缘层，或者沟道层与漏极金属层之间设置第二绝缘层。其中，第一绝缘层或第二绝缘层的厚度可以小于预设厚度，预设厚度为能通过在栅极金属层加电使沟道层形成有效电流控制的最小厚度。如此，该厚度的绝缘层不仅能起到有效隔离金属层和沟道层的作用，还能在金属层包含特殊金属元素时，尽量避免特殊金属元素与沟道层接触不佳所导致的金属层的导电性能下降的现象。
在一种可能的设计中，沟道层与任一金属层之间还可以形成欧姆接触，如沟道层与源极金属层之间形成第一欧姆接触，或者沟道层与漏极金属层之间形成第二欧姆接触，以便金属层中的导电离子能更容易地向沟道层的方向移动，加速金属层与沟道层之间的电流传导。
在一种可能的设计中，铁电介质层可以由铁电材料、以及金属材料和/或常规介质材料构成，例如仅由铁电材料构成，或者由铁电材料和金属材料构成，或者由铁电材料和常规介质材料构成，或者由铁电材料、金属材料和常规介质材料同时构成。其中，铁电材料可以为掺杂有硅、锆、镧、铝、钇、钙、镁、锶、铒或稀土元素中的一项或多项的氧化铪材料。金属材料可以为由氮化钛、钛、金、钨、钼、由锡和铟构成的氧化物、铝、铜、钌或银中的一项或多项构成的导电材料。常规介质材料可以为由二氧化硅、三氧化二铝、二氧化铪、二氧化锆、二氧化钛、三氧化二钇或氮化硅中的一项或多项构成的绝缘材料。
在一种可能的设计中，调栅介质层可以由铁电材料、金属材料或常规介质材料中的一 项或多项构成。
在一种可能的设计中，沟道层可以由硅、多晶硅、非晶硅、由铟、镓和锌构成的氧化物、氧化锌、氧化铟锡、二氧化钛或二硫化钼中的一项或多项元素构成。
在一种可能的设计中，栅极金属层、源极金属层、漏极金属层或调栅金属层可以由氮化钛、钛、金、钨、钼、由锡和铟构成的氧化物、铝、铜、钌或银中的一项或多项元素构成。
第二方面，本申请提供一种存储阵列，包括多个如上述第一方面中的任一项设计所提供的铁电晶体管，多个铁电晶体管可以按照行、列或堆叠中的至少两个方向进行排布以构成存储阵列，例如可以仅按照行和列排布、或仅按照行和堆叠排布、或仅按照列和堆叠排列以构成二维的存储阵列，也可以同时按照行、列和堆叠排布以构成三维的存储阵列。
在一种可能的设计中，多个铁电晶体管中的一个或多个铁电晶体管可以共享同一调栅金属层。当每个铁电晶体管都具有各自对应的调栅金属层时，每个铁电晶体管都可以按照自己的需求单独调节读取阈值，以适用于各铁电晶体管具有不同读取阈值漂移的场景。当多个铁电晶体管共享同一调栅金属层时，存储阵列可以在一次调栅操作中同时补偿多个铁电晶体管的读取阈值，以适用于多个铁电晶体管具有相同读取阈值漂移的场景。
在一种可能的设计中，当多个铁电晶体管按照行和列进行排布时，处于同一行的铁电晶体管共享同一源极金属层，处于同一列的铁电晶体管共享同一漏极金属层和同一栅极金属层，以便实现对每个铁电晶体管的读取控制。
第三方面，本申请提供一种存储器，包括如上述第二方面中的任一项设计所提供的存储阵列、以及与该存储阵列耦合的存储控制器。其中，存储阵列可以用于存储数据，而存储控制器可以向该存储阵列写入数据，或，从该存储阵列中读取数据。
在一种可能的设计中，当存储阵列中的一个或多个铁电晶体管共享同一调栅金属层时，存储控制器还可以通过该调栅金属层调节共享该调栅金属层的一个或多个铁电晶体管的读取阈值。
第四方面，本申请提供一种电子设备，包括印刷电路板(printed circuit board，PCB)和如上述第三方面中的任一项设计所提供的存储器，该存储器设置在PCB的表面。
具体地，该电子设备包括但不限于：智能手机、智能手表、平板电脑、虚拟现实(virtual reality，VR)设备、增强现实(augmented reality，AR)设备、车载设备、台式计算机、个人计算机、手持式计算机或个人数字助理。
第五方面，本申请提供一种制备铁电晶体管的方法，该方法包括：先依次外延源极金属层和调栅介质层，再在调栅介质层的两侧淀积调栅金属层，然后外延调栅介质层直至覆盖调栅金属层，并在调栅介质层上外延漏极金属层，之后刻蚀漏极金属层和调栅介质层直至源极金属层的表面以形成凹槽，在凹槽内依次外延沟道层和铁电介质层以形成向上开口的嵌套结构，最后在开口内淀积栅极金属层，以得到铁电晶体管。
本申请的上述各个方面或其它方面具体将在以下的实施例中进行详细的介绍。
附图说明
图1示例性示出一种铁电晶体管的结构示意图；
图2示例性示出本申请实施例提供的一种铁电晶体管的结构示意图；
图3示例性示出本申请实施例提供的一种铁电介质层的结构示意图；
图4示例性示出本申请实施例提供的一种铁电晶体管的读取电流与读取阈值的关联关系图；
图5示例性示出本申请实施例提供的一种调栅介质层的结构示意图；
图6示例性示出本申请实施例提供的一种铁电晶体管的截面俯视图；
图7示例性示出本申请实施例提供的另一种铁电晶体管的结构示意图；
图8示例性示出本申请实施例提供的另一种铁电晶体管的结构示意图；
图9示例性示出本申请实施例提供的一种制备铁电晶体管的流程结构图；
图10示例性示出本申请实施例提供的一种存储阵列的结构示意图。
具体实施方式
随着半导体技术的不断演进，现阶段越来越倾向于在存储器的单位面积上设置更多的晶体管，以提高存储器的存储密度(即单位面积所能存储的数据量)和存储容量，满足信息时代下人们对于大数据处理的需求。然而，传统的存储介质已逐渐跟不上人们的这种需求。例如，传统的动态随机存取存储器(dynamic random access memory，DRAM)利用电容器内所存储的电荷的数量表征待存储的二进制数据，其需要额外设置电容器的特性导致其结构微缩能力有限，而电容器充放电所需时间较长的特性又导致其存取速度提升能力有限，现有的DRAM无论是在结构设计上还是在存取速度上都已达到饱和，难以进一步提升。而传统的静态随机存取存储器(static random access memory，SRAM)则需要大约六个晶体管才能构成一个存储单元，在存储面积一定的情况下，现有的SRAM在存储密度和存储容量上极为受限。
为解决现阶段存储器所遇到的存储密度瓶颈或存储容量瓶颈等问题，目前试图基于新型材料构建新型结构的存储器，如铁电存储器。铁电存储器由一个或多个铁电晶体管构成。铁电晶体管内包含铁电材料，通过利用铁电材料自发极化方向随外加电场改变的特性，使得铁电晶体管能在大概1纳秒的时间内高效完成数据存储。且，即使在存完数据后撤掉外加电场，铁电材料的自发极化方向也不会发生改变，因此铁电晶体管理论上还能实现几乎永久的保持时间。正是具有这种高效存取数据和永久存取数据的特性，铁电晶体逐渐成为目前研究最为热门的一种存储介质。
现阶段，业界通常直接暨用传统硅基晶体管(如薄膜晶体管(thin film transistor，TFT))来设置铁电晶体管，图1示例性示出该种铁电晶体管的一种结构示意图。如图1所示，在该示例中，铁电晶体管包括位于最底部的沟道层、依次平铺于沟道层上方且互不接触的源极金属层、铁电介质层和漏极金属层、以及设置在铁电介质层上方的栅极金属层。其中，源极金属层在源极金属层的上表面上引出引脚连接源极电源V S(源极电源V S一般为接地电路)以构成铁电晶体管的源极，栅极金属层在栅极金属层的上表面上引出引脚连接栅极电源V G以构成铁电晶体管的栅极，漏极金属层在漏极金属层的上表面上引出引脚连接漏极电源V D以构成铁电晶体管的漏极。
图1所示意的铁电晶体管能根据沟道层中流动的电流大小实现数据存取，以n型沟道铁电晶体管为例进行示例性说明：
在n型沟道铁电晶体管中，预先通过源极电源V S和漏极电源V D在源极金属层和漏极金属层之间施加源漏电压，使沟道层中形成由漏极金属层流向源极金属层的源漏电流，如图1所示意的由右向左方向的水平电流。在存储数据“1”时，假设通过栅极电源V G施加 正向栅压(大于铁电晶体管的铁电翻转电压)，该正向栅压会在铁电介质层中产生由栅极金属层指向沟道层表面的极化电场，使得铁电介质层在该电场作用下向上吸引沟道层中的电子，导致沟道层中的电荷载流子浓度提高，沟道层的电阻变小，沟道层中的源漏电流增大，当增大至大于预先设置的参考电流时，铁电晶体管成功存储数据“1”。在存储数据“0”时，假设通过栅极电源V G施加负向栅压(大于铁电晶体管的铁电翻转电压)，该负向栅压会在铁电介质层中产生由沟道层指向栅极金属层底面的极化电场，使得铁电介质层在该电场作用下向下排斥沟道层中的电子，导致沟道层中的载流子浓度降低，沟道层的电阻变大，沟道层中的源漏电流减小，当减小至小于预先设置的参考电流时，铁电晶体管成功存储数据“0”。在成功存储完数据后，即使撤销正向栅压或负向栅压，铁电介质层中的极化状态也不会发生变化，从而沟道层中的电流大小基本不变。如此，在读取数据时，可以直接读取沟道层中的电流，若读取到的电流大于参考电流，则说明当前存储有数据“1”，如果读取到的电流小于参考电流，则说明当前存储有数据“0”。
虽然图1所示意的铁电晶体管能通过上述方式完成数据存取，但是该种结构的铁电晶体管仍存在一些较难克服的问题。首先，图1所示意的铁电晶体管实际上是按照水平方向并列排布源极金属层、漏极金属层和栅极金属层，在光刻的特征长度为F的情况下，单个铁电晶体管在图1所示意的水平方向上至少需要3F的空间，在图1所示意的与水平方向垂直的方向(沿着图1所示意的平面向里的方向)上至少需要F的空间，因此，单个铁电晶体管至少需要3F 2(3F×F)的布局面积。当多个铁电晶体管按照图1所示意的水平方向和图1所示意的平面向里的方向构成存储阵列时，如果相邻两个铁电晶体管之间间隔F的空间，则一个铁电晶体管在图1所示意的水平方向上至少需要4F的空间，在图1所示意的平面向里的方向上至少需要2F的空间，因此，存储阵列中的一个铁电晶体管至少需要8F 2(4F×2F)的布局面积。可知，图1所示意的铁电晶体管需要占用较大的布局面积，在存储阵列的存储面积一定的情况下，整个存储阵列中只能部署少量的铁电晶体管，不利于提高存储阵列的存储密度和存储容量。再者，图1所示意的铁电晶体管基本将源极金属层、漏极金属层和栅极金属层都设置在同一平面，导致各金属区域只能在上方走线以连接对应的电源，在这种情况下，当堆叠多个铁电晶体管形成多层结构时，多个铁电晶体管的走线较为复杂，不仅会增大多层堆叠的制备难度，还很有可能会使实际的存储单元超过上述8F 2的占用面积，进一步降低存储阵列的存储密度和存储容量。
有鉴于此，本申请提供一种占用面积小、易于堆叠和制备的铁电晶体管。该铁电晶体管能适用于具有数据存储功能的设备，例如可以适用于只具有数据存储功能的存储设备，如存储器，也可以适用于具有数据存储功能且还具有其它功能的电子设备，如包含诸如个人数字助理和/或音乐播放器等功能的便携式电子设备，诸如手机、平板电脑、具备无线通讯功能的可穿戴设备(如智能手表)、或车载设备等。便携式电子设备的示例性实施例包括但不限于搭载
Figure PCTCN2021079825-appb-000004
或者其它操作系统的便携式电子设备。上述便携式电子设备也可以是诸如具有触敏表面(例如触控面板)的膝上型计算机(Laptop)等。在本申请其它一些实施例中，上述电子设备还可以是具有触敏表面(例如触控面板)的台式计算机。
下面将结合附图对本申请作进一步地详细描述。需要说明的是，在本申请的描述中“至少一个”是指一个或多个，其中，多个是指两个或两个以上。鉴于此，本发明实施例中也可以将“多个”理解为“至少两个”。“和/或”，描述关联对象的关联关系，表示可以存在三种关 系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，字符“/”，如无特殊说明，一般表示前后关联对象是一种“或”的关系。
另外，需要理解的是，在本申请的描述中，“第一”、“第二”等词汇，仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。例如，“第一绝缘层”和“第二绝缘层”，只是示例性地指出不同位置处的绝缘层，而并不意味着这两个绝缘层的重要程度或优先级的不同。
【实施例一】
图2示例性示出本申请实施例提供的一种铁电晶体管的结构示意图，如图2所示，该铁电晶体管包括依次层叠的栅极金属层、铁电介质层和沟道层，还包括分别接触沟道层的漏极金属层和源极金属层，栅极金属层、漏极金属层和源极金属层上下重叠且互不接触。其中，栅极金属层、漏极金属层和源极金属层上下重叠，可以是指栅极金属层位于最上方、漏极金属层位于中间、且源极金属层位于最下方的重叠，也可以是指栅极金属层位于最上方、源极金属层位于中间、且漏极金属层位于最下方的重叠，还可以是指漏极金属层位于最上方、源极金属层位于中间、且栅极金属层位于最下方的重叠，等等。重叠可以是指这三个金属层的部分区域各自重叠，也可以是指这三个金属层的全部区域相互重叠，还可以是指其中某个金属层的部分区域与另外一个或两个金属层的全部区域重叠等。在图2所示意的重叠方式中，源极金属层和栅极金属层的全部区域相互重叠，而漏极金属层的全部区域与源极金属层的部分区域和栅极金属层的部分区域重叠。按照该种重叠方式，单个铁电晶体管在图2所示意的水平方向上可以只占据1F的空间，在图2所示意的平面向里的方向上可以只占据1F的空间，因此，图2所示结构的单个铁电晶体管可以只占据1F 2(1F×1F)的布局面积，能比图1所示结构的单个铁电晶体管节省大约2/3的布局面积。当多个铁电晶体管按照图2所示意的水平方向和平面向里的方向构成存储阵列时，如果两个相邻的铁电晶体管之间间隔F的空间，则存储阵列中的一个铁电晶体管在图2所示意的水平方向上可以只占据2F的空间，在图2所示意的平面向里的方向上可以只占据2F的空间，因此，图2所示结构的铁电晶体管在存储阵列中可以只占据4F 2(2F×2F)的布局面积，能比图1所示结构的铁电晶体管在存储阵列中节省大约一半的布局面积。采用如图2所示的结构设置铁电晶体管，有助于在固定面积的存储阵列中布局更多的铁电晶体管(在只考虑平面布局的情况下，大概能比图1所示结构的铁电晶体管数量多一倍)，有效提高存储阵列的存储密度和存储容量。
本申请实施例中，铁电介质层可以由铁电材料、或铁电材料和其它一种或多种介质材料(如金属材料或常规材料等)构成，图3示例性示出本申请实施例提供的一种铁电介质层的结构示意图，如图3所示：
铁电介质层可以如图3中的(A)所示意的仅由铁电材料构成；或者铁电介质层也可以如图3中的(B)所示意的同时由铁电材料和金属材料构成；或者铁电介质层还可以如图3中的(C)所示意的同时由铁电材料和常规介质材料构成；或者铁电介质层又可以如图3中的(D)所示意的同时由铁电材料、金属材料和常规介质材料构成。
其中，铁电材料可以是指掺杂有硅、锆、镧、铝、钇、钙、镁、锶、铒及稀土元素中的一项或多项元素的金属或金属氧化物材料，如氧化铪、氧化锆、氧化钽、锆及铪等，也可以为掺杂有上述一项或多项元素的锆钛酸铅、钛酸锶钡或过度金属氧化物等，还可以为 其它具有类似的极化电场随外加栅压而改变的特性的材料。金属材料是指由金属元素、含金属合金或其它组成物构成的导电材料，如包括但不限于氮化钛、钛、金、钨、钼、由锡和铟构成的氧化物、铝、铜、钌或银等。常规介质材料是指由二氧化硅、三氧化二铝、二氧化铪、二氧化锆、二氧化钛、三氧化二钇、氮化硅或其它绝缘元素中的一项或多项构成的绝缘材料。
本申请实施例中，栅极金属层、漏极金属层或源极金属层可以由金属元素、含金属合金或其它组成物等导电材料构成，如包括但不限于氮化钛、钛、金、钨、钼、由锡和铟构成的氧化物、铝、铜、钌或银等。其中，栅极金属层、漏极金属层和源极金属层分别用于形成铁电晶体管的栅极、漏极和源极。示例性地，继续参照图2所示，通过上下重叠排布栅极金属层、漏极金属层和源极金属层，能使栅极金属层、漏极金属层和源极金属层分别位于不同的平面，在连接各电极电源时，栅极金属层可在所在平面上水平走线连接至栅极电源(V G)以构成铁电晶体管的栅极，漏极金属层可在所在平面上水平走线连接至漏极电源(V D)以构成铁电晶体管的漏极，源极金属层可在所在平面上水平走线连接至源极电源(V S)以构成铁电晶体管的源极。如此，即使在铁电晶体管的上方或下方堆叠其它铁电晶体管，也能不打乱各铁电晶体管中的原本走线，有助于降低多层堆叠铁电晶体管的制备难度。
本申请实施例中，沟道层可以由一种或多种半导体材料构成，如可以包括但不限于硅、多晶硅或非晶硅等单晶半导体、由铟、镓和锌构成的氧化物、氧化锌、氧化铟锡或二氧化钛等氧化物半导体、以及二硫化钼等低维薄膜半导体等。沟道层用于形成导电沟道。在按照图2所示意的方式重叠漏极金属层和源极金属层时，漏极金属层流向源极金属层的源漏电流在图2所示意的沟道层中垂直流动，沟道层中形成垂直方向的导电沟道，因此，图2所示结构的铁电晶体管也称为垂直结构的铁电晶体管。
图2所示意的铁电晶体管能根据沟道层中流动的源漏电流的大小实现数据存取，示例来说：
预先通过源极电源V S和漏极电源V D在源极金属层和漏极金属层之间施加源漏电压，使沟道层中形成由漏极金属层流向源极金属层的竖直方向的源漏电流。在存储数据“1”时，假设通过栅极电源V G施加正向栅压(大于铁电晶体管的铁电翻转电压)，该正向栅压会在铁电介质层中产生由栅极金属层指向沟道层表面的极化电场，使得铁电介质层在该电场作用下向上吸引沟道层中的电子，导致沟道层中的电荷载流子浓度提高，沟道层的电阻变小，沟道层中的源漏电流增大，当增大至大于预先设置的参考电流时，铁电晶体管成功存储数据“1”。在存储数据“0”时，假设通过栅极电源V G施加负向栅压(大于铁电晶体管的铁电翻转电压)，该负向栅压会在铁电介质层中产生由沟道层指向栅极金属层底面的极化电场，使得铁电介质层在该电场作用下向下排斥沟道层中的电子，导致沟道层中的电荷载流子浓度降低，沟道层的电阻变大，沟道层中的源漏电流减小，当减小至小于预先设置的参考电流时，铁电晶体管成功存储数据“0”。在成功存储完数据后，即使撤销正向栅压或负向栅压，铁电介质层中的极化状态也不会发生变化，从而沟道层中的电流大小基本不变。如此，在读取数据时，可以直接读取沟道层中的电流，若读取到的电流大于参考电流，则说明铁电晶体管中存储有数据“1”，如果读取到的电流小于参考电流，则说明铁电晶体管中存储有数据“0”。
本申请实施例中，铁电晶体管在读取数据时存在读取阈值，该读取阈值与栅极电压共 同作用影响对铁电晶体管所存数据的“0-1”判断。正常情况下的读取阈值是一个固定的值。然而，由于铁电材料的印记效应、铁电介质层与沟道层之间接触界面的陷阱效应以及铁电介质层中的离子迁移效应等，铁电介质层可能会出现疲劳现象，导致铁电晶体管的读取阈值发生漂移。图4示例性示出本申请实施例提供的一种铁电晶体管中的读取电流与读取阈值的关联关系图，其中，图4中的(A)示意出栅极电压和源漏电流之间的关联曲线随读取阈值的漂移而产生的变化情况，图4中的(B)示意出铁电晶体管在“0”、“1”状态下所读取到的源漏电流随读取阈值的漂移而产生的变化情况。如图4中的(A)所示，各条实线对应为不同读取阈值下的源漏电流和栅极电压之间的关联曲线：
根据任一读取阈值下的关联曲线可知，源漏电流会随着栅极电压的增大而增大，并随着栅极电压的减小而减小。当不存在读取阈值的漂移时，铁电介质层朝向沟道层的极化电场在沟道层中产生大于参考电流的源漏电流时，使得铁电晶体管中存储“1”，而铁电介质层朝向栅级金属层的极化电场在沟道层中产生小于参考电流的源漏电流时，使得铁电晶体管中存储“0”。在这种情况下，铁电晶体管中存储“1”时所对应的源漏电流分布在参考电流的右侧，铁电晶体管中存储“0”时所对应的源漏电流分布在参考电流的左侧，如图4中的(B)中的实线所示。
根据各读取阈值下的各条关联曲线可知，当由于铁电介质层的印记效应等导致读取阈值变小时，源漏电流和栅极电压之间的关联曲线会向着图4中的(A)所示意的左侧漂移，使得原栅极电压下的源漏电流变大，在铁电晶体管中存储“0”的情况下，理论上沟道层中的源漏电流小于参考电流，但是变大的读取阈值导致沟道层中的源漏电流也变大，当源漏电流变大至超过参考电流时，实际读取到的源漏电流会大于参考电流，导致将铁电晶体管中存储的数据误判为“1”。反之，当读取阈值变大时，源漏电流和栅极电压之间的关联曲线会向着图4中的(A)所示意的右侧移动，使得原栅极电压下的源漏电流变小，在铁电晶体管中存储“1”的情况下，理论上沟道层中的源漏电流大于参考电流，但是变小的读取阈值导致沟道层中的源漏电流也变小，当源漏电流变小至低于参考电流时，实际读取到的源漏电流会小于参考电流，导致将铁电晶体管中存储的数据误判为“0”，如图4中的(B)中的虚线分布峰所示。由此可知，随着读取阈值的漂移，源漏电流不再是原本存储的数据所对应的源漏电流，而可能会比原本存储“1”时的源漏电流小，或比原本存储“0”时的源漏电流大，导致源漏电流与参考电流之前的窗口变小甚至消失，影响铁电晶体管读数的准确性。
为避免读取阈值漂移所造成的读数不准确的现象发生，在一种可选地实施方式中，继续参照图2所示，该铁电晶体管还可以包括位于漏极金属层和源极金属层之间的调栅介质层、以及包裹在调栅介质层内的调栅金属层。其中，调栅介质层分别接触沟道层、漏极金属层和源极金属层，调栅金属层用于连接调栅电源V T以构成铁电晶体管的调栅电极。在实施中，当检测到读取阈值向图4中的(A)所示意的左侧漂移时，说明沟道层中的源漏电流随着读取阈值的该种漂移而变大，在这种情况下，可以通过调栅电源V T向调栅金属层施加负向调栅电压，以驱使调栅介质层排斥沟道层中的电子，如此，随着沟道层中的电荷载流子变少，沟道层的电阻变大，沟道层中的源漏电流降低。反之，当检测到读取阈值向图4中的(A)所示意的右侧漂移时，说明沟道层中的源漏电流随着读取阈值的该种漂移而变小，在这种情况下，可以通过调栅电源V T向调栅金属层施加正向调栅电压，以驱使调栅介质层吸引沟道层中的电子，如此，随着沟道层中的电荷载流子变多，沟道层的电 阻变小，沟道层中的源漏电流增大。如此，通过设置调栅金属层和调栅介质层，能在读取阈值漂移的情况下对沟道层中的源漏电流进行反向补偿，有助于提高铁电晶体管的读取准确性。
需要说明的是，上述只是以读取阈值整体向左侧或整体向右侧漂移为例，示例性介绍一种调栅方案的具体实现过程。在其它示例中，读取阈值的漂移也可能不是一个固定的方向，例如，随着铁电介质层的使用次数增多，铁电介质层吸引电子或排斥电子的能力变弱，导致沟道层在存储不同数据时的源漏电流差值变小。在这种情况，铁电晶体管还可以根据具体存储数据的不同选取不同的补偿方式。关于该种方式下补偿的具体实现过程，可直接参照上述方案，本申请对此不作重复介绍。
本申请实施例中，调栅介质层可由铁电材料、金属材料、常规介质材料或能控制沟道层中载离子浓度的其它介质材料中的一种或多种构成，图5示例性示出本申请实施例提供的一种调栅介质层的结构示意图，如图5所示：
调栅介质层可以如图5中的(A)所示意的仅由铁电材料构成；或者调栅介质层也可以如图5中的(B)所示意的仅由金属材料构成；或者调栅介质层还可以如图5中的(C)所示意的仅由常规介质材料构成；或者调栅介质层又可以如图5中的(D)所示意的同时由铁电材料和金属材料构成；或者调栅介质层还可以如图5中的(E)所示意的同时由铁电材料和常规介质材料构成；或者调栅介质层还可以如图5中的(F)所示意的同时由金属材料和常规介质材料构成；或者调栅介质层还可以如图5中的(G)所示意的同时由铁电材料、金属材料和常规介质材料构成。
本申请实施例中，调栅金属层可以由金属元素、含金属合金或其它组成物等导电材料构成，如包括但不限于氮化钛、钛、金、钨、钼、由锡和铟构成的氧化物、铝、铜、钌或银等。示例性地，继续参照图2所示，调栅金属层也可以与栅极金属层、源极金属层和漏极金属层位于不同的平面，如此，在连接调栅电源V T时，调栅金属层也可在所在平面水平走线至调栅电源以形成铁电晶体管的调栅电极，进一步降低多层堆叠铁电晶体管的制备难度。
在一种可选地实施方式中，铁电晶体管可以呈现为柱状结构，如圆柱。图6示例性示出本申请实施例提供的一种铁电晶体管的截面俯视图，该截面俯视图为沿着图2所示意的横截面P 1切割铁电晶体管而得到的，这种情况下，图2可以对应为沿着圆柱所对应圆面的直径切割铁电晶体管而得到的截面主视图。通过将整个铁电晶体管设置为规则的圆柱结构，能直接将一个铁电晶体管堆叠在另一铁电晶体管的上方或下方，便于实现多个铁电晶体管的堆叠设计，获得包括多层铁电晶体管的存储阵列，提高存储阵列的存储密度和存储容量。
示例性地，本申请实施例中，当铁电晶体管呈现为圆柱时，如图2和图6所示：栅极金属层、铁电介质层和沟道层可以依次嵌套构成柱状结构，如依次嵌套构成如图2所示意的T型圆柱，或者依次嵌套构成L型柱、U型柱或圆柱等。在该示例中，栅极金属层可以设置为如图2所示意的T型圆柱，还可以为其它柱状结构，如圆柱。铁电介质层和沟道层可以设置为如图2所示意的
Figure PCTCN2021079825-appb-000005
型环，也可以设置为能够嵌套栅极金属层的其它环状结构或柱状结构，如铁电介质层和沟道层都设置为U型环，或铁电介质层设置为U型环且沟道层设置为
Figure PCTCN2021079825-appb-000006
型环，或铁电介质层设置为T型圆柱而沟道层设置为
Figure PCTCN2021079825-appb-000007
型环等，具体不作限定；
示例性地，当沟道层设置为环状沟槽时，源极金属层和漏极金属层可以通过该环状沟槽实现竖直方向的联通。以图2所示意的
Figure PCTCN2021079825-appb-000008
型环状沟槽为例，源极金属层可以设置在
Figure PCTCN2021079825-appb-000009
型 环状沟槽的槽底，漏极金属层可以设置在
Figure PCTCN2021079825-appb-000010
型环状沟槽的台阶底，如此，源漏电流能够依次流经漏极金属层和
Figure PCTCN2021079825-appb-000011
型环状沟槽的台阶底，之后沿着竖直方向流至
Figure PCTCN2021079825-appb-000012
型环状沟槽的槽底，再流至源极金属层，在
Figure PCTCN2021079825-appb-000013
型环状沟槽中形成竖直方向的导电沟道；
一个示例性的例子，漏极金属层可以设置为环状结构，如图2和图6所示意的柱状环。又一个示例性的例子，源极金属层可以设置为柱状结构，如图2和图6所示意的圆柱。再一个示例性的例子，铁电晶体管中的各层均可侧面平齐，即漏极金属层的侧面、源极金属层的侧面、沟道层的侧面、调栅介质层的侧面、调栅金属层的侧面、栅极金属层的侧面和铁电介质层的侧面均平齐，以实现铁电晶体管的圆柱结构。有一个示例性的例子，沟道层、源极金属层和漏极金属层之间可以形成环状的容置空间，如图2和图6所示意的柱状环。如图2所示，调栅介质层可以围绕在该柱状环的内壁周围，并分别接触沟道层、源极金属层和漏极金属层。且，调栅介质层还可以在背离沟道层的一侧开设开口，该开口用于包裹调栅金属层。
在一种可选地实施方式中，沟道层与任一金属层(源级金属层或漏极金属层)之间还可以形成欧姆接触，例如沟道层与源极金属层之间形成第一欧姆接触，沟道层与漏极金属层之间形成第二欧姆接触。在该实施方式中，通过设置欧姆接触，使得金属层中的导电离子能更容易地向沟道层的方向移动，有助于加速金属层与沟道层之间的电流传导。
在一种可选地实施方式中，沟道层与任一金属层之间还可以设置绝缘层，例如沟道层与源极金属层之间设置第一绝缘层，沟道层与漏极金属层之间设置第二绝缘层。其中，绝缘层的厚度可以小于通过在栅极金属层加电使沟道层形成有效电流控制的最小厚度，如可以设置为0.1nm～2nm(距离单位，即纳米)之间的一个值。如此，该厚度的绝缘层不仅能起到有效隔离金属层和沟道层的作用，尽量避免金属层中的导电离子向沟道层扩散，维持金属层的导电性能，还能在金属层包含特殊金属元素时，有效避免特殊金属元素与沟道层接触不佳所导致的金属层的导电性能下降的问题(即费米钉扎问题)。
需要说明的是，上述实施例一只是以上下方向依次层叠栅极金属层、铁电介质层和沟道层为例，介绍一种铁电晶体管的具体结构，本申请并不限定栅极金属层、铁电介质层和沟道层只能具有该种层叠结构。例如，在其它可选地实施方式中，栅极金属层、铁电介质层和沟道层还可以按照左右方向、前后方向甚至倾斜方向等进行层叠。下面示例性以实施例二介绍一种按照左右方向层叠栅极金属层、铁电介质层和沟道层所得到的铁电晶体管。
【实施例二】
图7示例性示出本申请实施例提供的另一种铁电晶体管的结构示意图，该铁电晶体管整体呈圆柱结构，其中，图7中的(A)示意出按照圆柱圆面的直径切割该铁电晶体管所得到的截面主视图，图7中的(B)示意出沿着图7中的(A)所示意的P 2面切割该铁电晶体管所得到的截面俯视图。如图7中的(A)和图7中的(B)所示，在该示例中，铁电晶体管包括依次向左层叠的栅极金属层、铁电介质层和沟道层，还包括分别接触沟道层的漏极金属层和源极金属层，漏极金属层、栅极金属层和源极金属层由上向下依次重叠且互不接触。其中，图7所示意的栅极金属层与实施例一中图2所示意的调栅金属层具有相同结构，图7所示意的铁电介质层与实施例一中图2所示意的调栅介质层具有相同结构。
示例性地，铁电晶体管还可以包括依次向下层叠的调栅金属层和调栅介质层，调栅介质层的下底面嵌套在沟道层中。其中，图7所示意的调栅金属层与实施例一中图2所示意 的栅极金属层具有相同结构，图7所示意的调栅介质层与实施例一中图2所示意的铁电介质层具有相同结构。
关于图7所示意的铁电晶体管如何利用栅极金属层和铁电介质层存取数据、以及如何利用调栅金属层和调栅介质层调节读取阈值，请具体参照上述实施例一，此处不再重复赘述。
需要说明的是，上述实施例一和实施例二只是以由上向下依次重叠排布栅极金属层、漏极介质层和源极金属层为例，介绍铁电晶体管的具体结构，本申请并不限定栅极金属层、漏极介质层和源极金属层只能按照该种由上向下的顺序依次重叠排布。例如，在其它可选地实施方式中，也可以按照由上向下的顺序依次重叠排布栅极金属层、源极介质层和漏极金属层，或者按照由上向下的顺序依次重叠排布源极介质层、漏极金属层和栅极金属层，或者按照由上向下的顺序依次重叠排布漏极介质层、源极金属层和栅极金属层，等等。下面示例性以实施例三介绍一种按照由上向下的顺序依次重叠排布栅极金属层、源极介质层和漏极金属层所得到的铁电晶体管。
【实施例三】
图8示例性示出本申请实施例提供的又一种铁电晶体管的结构示意图，该铁电晶体管整体呈圆柱结构，其中，图8中的(A)示意出按照圆柱圆面的直径切割该铁电晶体管所得到的截面主视图，图8中的(B)示意出沿着图8中的(A)所示意的P 3面切割该铁电晶体管所得到的截面俯视图。如图8中的(A)和图8中的(B)所示，在该示例中，铁电晶体管包括依次向下层叠的栅极金属层、铁电介质层和沟道层，还包括分别接触沟道层的源极金属层和漏极金属层，栅极金属层、源极金属层和漏极金属层由上向下依次重叠且互不接触。示例性地，铁电晶体管还可以包括依次向左层叠的调栅金属层和调栅介质层，调栅介质层的左侧面嵌套在沟道层中。
需要说明的是，图8所示意的各层均与实施例一中图2所示意的各层具有相同结构。关于图8所示意的铁电晶体管如何利用栅极金属层和铁电介质层存取数据、以及如何利用调栅金属层和调栅介质层调节读取阈值，请具体参照上述实施例一，此处不再重复赘述。
需要说明的是，图2和图6、图7、以及图8仅是示例性地介绍三种铁电晶体管的可能结构。本申请并不限定铁电晶体管必须具有该种结构，凡是能够实现上下重叠排布各电极区域的铁电晶体管都在本申请的保护范围内，本申请对此不再一一列举。
继续以图2所示意的铁电晶体管为例，示例性介绍一种铁电晶体管的具体制备流程。图9示例性示出本申请实施例提供的一种制备铁电晶体管的流程结构图，如图9所示，该制备流程包括：
步骤一，外延源极金属层，获得如图9中的(A)所示意的结构；
步骤二，在源极金属层的上方外延调栅介质层，获得如图9中的(B)所示意的结构；
步骤三，在调栅介质层的上方左右两侧间隔淀积调栅金属，获得如图9中的(C)所示意的结构；
步骤四，外延调栅介质层直至完全包裹住两侧的调栅金属，获得如图9中的(D)所示意的结构；
步骤五，通过化学机械抛光(chemical mechanical polishing，CMP)技术将调栅介质层的表面打磨至平坦且无划痕，获得如图9中的(E)所示意的结构；
步骤六，在调栅介质层的上方外延漏极金属层，获得如图9中的(F)所示意的结构；
步骤七，避开两侧的调栅金属，依次刻蚀漏极金属层和调栅介质层直至源极金属层的上表面，使剩余的漏极金属层、调栅介质层和源极金属层之间构成容置凹槽，获得如图9中的(G)所示意的结构；
步骤八，在容置凹槽的内部外延沟道材料，形成向上开口的沟道层，获得如图9中的(H)所示意的结构；
步骤九，在沟道层的开口及上表面嵌套铁电介质，形成向上开口的铁电介质层，获得如图9中的(I)所示意的结构；
步骤十，在铁电介质层的开口及上表面填充栅极金属，以获得如图9中的(J 1)所示意的侧面平齐于铁电介质层的结构，或获得如图9中的(J 2)所示意的侧面略短于铁电介质层的结构，或获得如图9中的(J 3)所示意的侧面略长于铁电介质层的结构。
本申请实施例中，还可以按照行、列或堆叠中的至少两个方向组合多个铁电晶体管得到存储阵列。图10示例性示出本申请实施例提供的一种存储阵列的结构示意图，该存储阵列为按照行列方向组合四个如图2和图6所示意的铁电晶体管而得到的。其中，图10中的(A)示意出该存储阵列的截面主视图，图10中的(B)示意出该存储阵列的截面侧视图，图10中的(C)示意出按照图10中的(A)或图10中的(B)的P 4截面切割该存储阵列而得到的截面俯视图。如图10所示，在该存储阵列中，处于同一行的两个铁电晶体管共享同一源极，如处于第一行的铁电晶体管FeFET11的源极金属层和铁电晶体管FeFET12的源极金属层连通至同一源极电源V S1，处于第二行的铁电晶体管FeFET21的源极金属层和铁电晶体管FeFET22的源极金属层连通至同一源极电源V S2。处于同一列的两个铁电晶体管共享同一漏极和同一栅极，如处于第一列的铁电晶体管FeFET11的漏极金属层和铁电晶体管FeFET21的漏极金属层连通至同一漏极电源V D1，处于第一列的铁电晶体管FeFET11的栅极金属层和铁电晶体管FeFET21的栅极金属层连通至同一栅极电源V G1，处于第二列的铁电晶体管FeFET12的漏极金属层和铁电晶体管FeFET22的漏极金属层连通至同一漏极电源V D2，处于第二列的铁电晶体管FeFET12的栅极金属层和铁电晶体管FeFET22的栅极金属层连通至同一栅极电源V G2。
本申请实施例中，存储阵列可以连接存储控制器，如存储阵列中的各个电极电源连接存储控制器。具体实施中，在需要向某一铁电晶体管(如位于第二行第二列的铁电晶体管FeFET22)中写入数据时，存储控制器可以先通过第二行所对应的源极电源V S2打开第二行中的铁电晶体管FeFET21和铁电晶体管FeFET22，再通过第二列所对应的漏极电源V D2打开第二列中的铁电晶体管FeFET12和铁电晶体管FeFET22，以使第二行第二列处的铁电晶体管FeFET22的沟道层中形成导电沟道，之后通过第二列所对应的栅极电源V S2向打开的铁电晶体管FeFET22施加正向栅压或负向栅压，以成功写入数据。对应的，在需要读取某一铁电晶体管(如位于第二行第二列的铁电晶体管FeFET22)中的数据时，存储控制器可以按照相同的操作依次控制第二行所对应的源极电源V S2和第二列所对应的漏极电源V D2，以打开第二行第二列处的铁电晶体管FeFET22，之后在打开的铁电晶体管FeFET22中执行读取操作。
本申请实施例中，多个铁电晶体管中的至少两个铁电晶体管可以共享同一调栅金属层。 例如，继续参照图10所示，四个铁电晶体管均通过调栅金属连接在一起，在这种情况下，四个铁电晶体管可以共享同一调栅金属。存储控制器通过一次调栅操作可以同时补偿四个铁电晶体管的读取阈值，该方案能适用于多个铁电晶体管具有相同读取阈值漂移的场景。应理解，至少两个铁电晶体管共享同一调栅只是一种可选地实施方式。在另一种可选地实施方式中，也可以通过调栅介质层隔开任意两个铁电晶体管的调栅，以使每个铁电晶体管都具有各自对应的调栅，如此，每个铁电晶体管都可以按照自己的需求单独调节读取阈值，以适用于各铁电晶体管具有不同读取阈值漂移的场景。
需要说明的是，图10只是以按照行列方向组合多个铁电存储器为例介绍存储阵列的具体结构，该种方式组合出的存储阵列具有单层结构。更进一步的，本申请还可以堆叠铁电晶体管得到具有多层结构的存储阵列，如按照行和堆叠这两个方向组合、或者按照列和堆叠这两个方向组合以构成多层结构的二维存储阵列，又如按照行、列和堆叠这三个方向组合以构成多层结构的三维存储阵列，进一步提高存储阵列的存储密度和存储容量。此外，本申请中的存储阵列还可以是堆叠现有的铁电晶体管、以及图2和图6所示意的铁电晶体管、图7所示意的铁电晶体管或图8所示意的铁电晶体管而得到的，如将图2和图6所示意的铁电晶体管堆叠在图1所示意的铁电晶体管的下方而得到。可知，通过设置该种规则的铁电晶体管结构，还易于实现与现有技术中不规则结构的铁电晶体管的堆叠设计，在不推翻现有存储阵列的基础上增加存储阵列中包含铁电晶体管的数量，增大存储阵列的存储密度和存储容量。
本申请还提供一种存储器，该存储器包括如上述内容所介绍的存储阵列、以及与该存储阵列耦合的存储控制器，存储控制器用于读写存储阵列中的数据。
在一种可选地实施方式中，当存储阵列中的一个或多个铁电晶体管共享同一调栅金属层时，存储控制器还可以通过调栅金属层调节共享调栅金属层的一个或多个铁电晶体管的读取阈值。
本申请还提供一种芯片，包括基板和如上述内容所介绍的存储器，存储器设置在基板上。
本申请还提供一种电子设备，包括如上述内容所介绍的存储器或芯片。
根据本申请实施例提供的方法，本申请还提供一种计算机程序产品，该计算机程序产品包括：计算机程序代码，当该计算机程序代码在计算机上运行时，使得该计算机执行上述内容所介绍的存储控制器所执行的方法。
根据本申请实施例提供的方法，本申请还提供一种计算机可读存储介质，该计算机可读介质存储有程序代码，当该程序代码在计算机上运行时，使得该计算机执行上述内容所介绍的存储控制器所执行的方法。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (21)

  1. 一种铁电晶体管，其特征在于，包括：
    依次层叠的栅极金属层、铁电介质层和沟道层；以及，
    分别接触所述沟道层的漏极金属层和源极金属层；
    其中，所述栅极金属层、所述漏极金属层和所述源极金属层上下重叠分布且互不接触。
  2. 如权利要求1所述的铁电晶体管，其特征在于，还包括：
    位于所述漏极金属层和所述源极金属层之间的调栅介质层；以及，
    包裹在所述调栅介质层内的调栅金属层；
    其中，所述调栅介质层分别接触所述沟道层、所述漏极金属层和所述源极金属层。
  3. 如权利要求1或2所述的铁电晶体管，其特征在于，所述铁电晶体管呈柱状结构。
  4. 如权利要求1至3中任一项所述的铁电晶体管，其特征在于，所述沟道层为环状沟槽，所述源极金属层和所述漏极金属层通过所述环状沟槽实现联通。
  5. 如权利要求4所述的铁电晶体管，其特征在于，所述环状沟槽呈
    Figure PCTCN2021079825-appb-100001
    型截面，所述源极金属层设置在所述
    Figure PCTCN2021079825-appb-100002
    型截面的环状沟槽的槽底，所述漏极金属层设置在所述
    Figure PCTCN2021079825-appb-100003
    型截面的环状沟槽的台阶底。
  6. 如权利要求4或5所述的铁电晶体管，其特征在于，所述栅极金属层、所述铁电介质层和所述沟道层依次嵌套构成柱状结构。
  7. 如权利要求6所述的铁电晶体管，其特征在于，所述柱状结构为T型圆柱。
  8. 如权利要求4至7中任一项所述的铁电晶体管，其特征在于，所述漏极金属层和所述源极金属层分别为侧面与所述沟道层的侧面平齐的环状结构。
  9. 如权利要求8所述的铁电晶体管，其特征在于，当包括所述调栅介质层和所述调栅介质层时：
    所述调栅介质层在背离所述沟道层的一侧开设开口，所述开口用于包裹所述调栅金属层。
  10. 如权利要求1至9中任一项所述的铁电晶体管，其特征在于，
    所述源极金属层与所述沟道层之间设置第一绝缘层；和/或，
    所述漏极金属层与所述沟道层之间设置第二绝缘层；
    其中，所述第一绝缘层或所述第二绝缘层的厚度小于预设厚度，所述预设厚度为能通过在所述栅极金属层加电使所述沟道层形成有效电流控制的最小厚度。
  11. 如权利要求1至10中任一项所述的铁电晶体管，其特征在于，所述源极金属层和漏极金属层分别与所述沟道层形成欧姆接触。
  12. 如权利要求1至11中任一项所述的铁电晶体管，其特征在于，所述铁电介质层由铁电材料、以及金属材料和/或常规介质材料构成；其中：
    所述铁电材料为掺杂有硅、锆、镧、铝、钇、钙、镁、锶、铒或稀土元素中的一项或多项的氧化铪材料；
    所述金属材料为由氮化钛、钛、金、钨、钼、由锡和铟构成的氧化物、铝、铜、钌或银中的一项或多项构成的导电材料；
    所述常规介质材料为由二氧化硅、三氧化二铝、二氧化铪、二氧化锆、二氧化钛、三氧化二钇或氮化硅中的一项或多项构成的绝缘材料。
  13. 如权利要求12所述的铁电晶体管，其特征在于，当包括所述调栅介质层时，所述调栅介质层由所述铁电材料、所述金属材料或所述常规介质材料中的一项或多项构成。
  14. 如权利要求1至13中任一项所述的铁电晶体管，其特征在于，所述沟道层由硅、多晶硅、非晶硅、由铟、镓和锌构成的氧化物、氧化锌、氧化铟锡、二氧化钛或二硫化钼中的一项或多项元素构成。
  15. 如权利要求1至14中任一项所述的铁电晶体管，其特征在于，所述栅极金属层、所述源极金属层、所述漏极金属层、或所述调栅金属层由如下一项或多项元素构成：
    氮化钛、钛、金、钨、钼、由锡和铟构成的氧化物、铝、铜、钌或银。
  16. 一种存储阵列，其特征在于，包括多个如权利要求1至15任一所述的铁电晶体管，多个铁电晶体管按照行、列或堆叠中的至少两个方向进行排布以构成所述存储阵列。
  17. 如权利要求16所述的存储阵列，其特征在于，所述多个铁电晶体管中的一个或多个铁电晶体管共享同一调栅金属层。
  18. 如权利要求16或17所述的存储阵列，其特征在于，当所述多个铁电晶体管按照行列进行排布时：
    处于同一行的铁电晶体管共享同一源极金属层，处于同一列的铁电晶体管共享同一漏极金属层和同一栅极金属层。
  19. 一种存储器，其特征在于，包括：
    如权利要求16至18任一所述的存储阵列；以及
    与所述存储阵列耦合的存储控制器；
    其中，所述存储控制器，用于读写所述存储阵列中的数据。
  20. 如权利要求19所述的存储器，其特征在于，当所述存储阵列中的一个或多个铁电晶体管共享同一调栅金属层时：
    所述存储控制器，还用于通过所述调栅金属层调节共享所述调栅金属层的所述一个或多个铁电晶体管的读取阈值。
  21. 一种制备铁电晶体管的方法，其特征在于，包括：
    依次外延源极金属层和调栅介质层；
    在所述调栅介质层的两侧淀积调栅金属层；
    外延所述调栅介质层至覆盖所述调栅金属层；
    在所述调栅介质层上外延漏极金属层；
    刻蚀所述漏极金属层和所述调栅介质层至所述源极金属层的表面以形成凹槽；
    在所述凹槽内依次外延沟道层和铁电介质层以形成向上开口的嵌套结构；
    在所述开口内淀积栅极金属层。
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