WO2024045860A1 - 薄膜晶体管及其电子器件 - Google Patents

薄膜晶体管及其电子器件 Download PDF

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Publication number
WO2024045860A1
WO2024045860A1 PCT/CN2023/104225 CN2023104225W WO2024045860A1 WO 2024045860 A1 WO2024045860 A1 WO 2024045860A1 CN 2023104225 W CN2023104225 W CN 2023104225W WO 2024045860 A1 WO2024045860 A1 WO 2024045860A1
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Prior art keywords
layer
doped
doping
thin film
film transistor
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PCT/CN2023/104225
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English (en)
French (fr)
Inventor
李治福
刘广辉
艾飞
宋德伟
罗成志
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US18/560,932 priority Critical patent/US20250081522A1/en
Publication of WO2024045860A1 publication Critical patent/WO2024045860A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6706—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing leakage current 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6728—Vertical TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H10D62/292—Non-planar channels of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/834—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants

Definitions

  • the present application relates to the field of display technology, and specifically to a thin film transistor and an electronic device thereof.
  • array substrates are required to have ultra-high resolution and sub-micron level device sizes.
  • thin film transistors on the array substrate are required.
  • the size and occupied area of the device should be reduced as much as possible.
  • conventional thin film transistors are limited by exposure accuracy and etching accuracy.
  • the channel length of the active layer is usually greater than 1 micron, making it difficult to further improve the size and occupied area of thin film transistor devices. decrease.
  • the present application provides a thin film transistor and its electronic device to improve the technical problem of the current thin film transistor device with a vertical structure, which causes an increase in leakage current due to too small a channel length, thereby causing a decrease in device stability.
  • This application provides a thin film transistor, including:
  • An active layer is provided on the insulating substrate, the active layer includes a first active layer, a channel layer and a second active layer arranged in a stack;
  • the first active layer includes a first doping part and a second doping part, the first doping part is connected to the channel layer and the second doping part, and the first doping part is The doping ion concentration in the doping part is smaller than the doping ion concentration in the second doping part.
  • the ratio of the doping ion concentration in the first doping part to the doping ion concentration in the second doping part is 1/10 to 1/5.
  • the first doped part and the second doped part are arranged on the insulating substrate in the same layer, and in a direction perpendicular to the insulating substrate, the second doped part
  • the thickness of the doped part is less than or equal to the thickness of the first doped part.
  • a ratio of the thickness of the second doped part to the thickness of the first doped part is 1/4 to 1.
  • the channel layer corresponds to the first doped portion
  • the orthographic projection of the channel layer on the first active layer partially overlaps with the first doped part and the second doped part.
  • the channel layer corresponds to the first doped portion
  • the orthographic projection of the channel layer on the first active layer is located in the first doping part, and the orthographic projection of the channel layer on the first active layer is in line with the third The two doped parts do not overlap.
  • the thin film transistor further includes a gate layer, and the gate layer is annularly insulated and arranged on the peripheral side of the channel layer;
  • an orthographic projection of the channel layer on the gate layer at least partially overlaps the gate layer.
  • the gate layer includes a first gate part and a second gate part that are connected together as a whole.
  • the first gate part is disposed above the insulating substrate, and the third gate part is disposed above the insulating substrate.
  • the two gate parts are insulated and arranged above the second doped part;
  • the orthographic projection of the channel layer on the first gate part is located within the first gate part, and the orthographic projection of the channel layer on the second gate part is in contact with the third gate part.
  • the two gate portions at least partially overlap.
  • an orthographic projection of the second gate portion on the insulating substrate partially overlaps with an orthographic projection of the channel layer on the insulating substrate.
  • the channel layer includes doped ions, and the doping ion concentration on the side of the channel layer away from the insulating substrate is greater than the doping ion concentration on the side of the channel layer close to the insulating substrate. doping ion concentration.
  • the thin film transistor further includes a first insulating layer disposed between the active layer and the gate layer;
  • the first insulating layer covers the surface of the second doped part, the surface of the second doped part and part of the surface of the insulating substrate.
  • the thin film transistor further includes a second insulating layer and a source and drain layer.
  • the second insulating layer covers the first insulating layer and the gate layer.
  • the source and drain layer disposed on the second insulating layer;
  • first via holes and second via holes are provided on the first insulating layer and the second insulating layer, and the source and drain layers are connected to the second doping part through the first via holes. , and the source and drain layers are connected to the second doped portion through the second via hole.
  • the thin film transistor further includes a light shielding layer disposed in the insulating substrate, and the orthographic projection of the active layer on the light shielding layer is located in the light shielding layer;
  • the gate layer and the light shielding layer are connected through a third via hole.
  • This application also proposes an electronic device, including a thin film transistor, and the thin film transistor includes:
  • An active layer is provided on the insulating substrate, the active layer includes a first active layer, a channel layer and a second active layer arranged in a stack;
  • the first active layer includes a first doping part and a second doping part, the first doping part is connected to the channel layer and the second doping part, and the first doping part is The doping ion concentration in the doping part is smaller than the doping ion concentration in the second doping part.
  • the ratio of the doping ion concentration in the first doping part to the doping ion concentration in the second doping part is 1/10 to 1/5.
  • the first doped part and the second doped part are arranged on the insulating substrate in the same layer, and in a direction perpendicular to the insulating substrate, the second doped part
  • the thickness of the doped part is less than or equal to the thickness of the first doped part.
  • a ratio of the thickness of the second doped part to the thickness of the first doped part is 1/4 to 1.
  • the channel layer corresponds to the first doped portion
  • the orthographic projection of the channel layer on the first active layer partially overlaps with the first doped part and the second doped part.
  • the channel layer corresponds to the first doped portion
  • the orthographic projection of the channel layer on the first active layer is located in the first doping part, and the orthographic projection of the channel layer on the first active layer is in line with the third The two doped parts do not overlap.
  • the thin film transistor further includes a gate layer, and the gate layer is annularly insulated and arranged on the peripheral side of the channel layer;
  • an orthographic projection of the channel layer on the gate layer at least partially overlaps the gate layer.
  • the first active layer is configured to include a first doping part and a second doping part with different doping ion concentrations, so that the second doping part and the second active layer serve as the
  • the channel layer and the first doped portion constitute the "channel region" of the thin film transistor, which is equivalent to increasing the channel length, thereby reducing leakage.
  • Current since the first doped portion is doped with ions, its mobility is higher than the mobility of the channel layer, which is equivalent to increasing the mobility of the "channel region" of the thin film transistor. Therefore, , the thin film transistor provided by this application can better solve the problems of excessive leakage current and low mobility.
  • Figure 1 is a schematic diagram of the first stacked structure of the thin film transistor described in this application.
  • Figure 2 is a schematic plan view of the thin film transistor described in this application.
  • Figure 3 is a schematic diagram of the second stacked structure of the thin film transistor described in this application.
  • Figure 4 is a schematic diagram of the third stacked structure of the thin film transistor described in this application.
  • Figure 5 is a schematic diagram of the fourth stacked structure of the thin film transistor described in this application.
  • Figure 6 is a schematic diagram of the fifth stacked structure of the thin film transistor described in this application.
  • Figure 7 is a flow chart of the manufacturing method of the thin film transistor described in this application.
  • FIGS 8 to 13 are schematic diagrams of the manufacturing flow of the thin film transistor manufacturing method described in this application.
  • Active layer 210. First active layer; 211. First doping part; 212. Second doping part; 220. Channel layer; 230. Second active layer;
  • Gate layer 410. First gate part; 420. Second gate part;
  • Source-drain layer 610. Source; 620. Drain;
  • the present application provides a thin film transistor, including an insulating substrate 100 and an active layer 200 disposed on the insulating substrate 100 .
  • the active layer 200 includes a stacked first layer.
  • the first active layer 210 includes a first doping part 211 and a second doping part 212.
  • the first doping part 211 and the The channel layer 220 and the second doped portion 212 are connected, and the doping ion concentration in the first doping portion 211 is smaller than the ion doping concentration in the second doping portion 212 .
  • the second doping part 212 and the second active layer 230 respectively serve as two "doped regions" of the thin film transistor, and the channel layer 220 and the first doped portion 211 constitute the "channel region" of the thin film transistor, which is equivalent to increasing the channel size.
  • the channel length is thereby reduced, thereby reducing the leakage current; moreover, since the first doped portion 211 is doped with ions, its mobility is higher than the mobility of the channel layer 220, which is equivalent to improving the "mobility" of the thin film transistor. Therefore, the thin film transistor provided by this application can better solve the problems of excessive leakage current and low mobility of vertical thin film transistors.
  • the insulating substrate 100 may include a base substrate 110 and a buffer layer 120 disposed on the base substrate 110.
  • the base substrate 110 may be a glass substrate.
  • the buffer layer 120 may be an inorganic film layer such as SiOx, SiNx, SiON, or a stack thereof.
  • the material of the active layer 200 may be polysilicon material.
  • the first active layer 210 and the second active layer 230 may be phosphorus ion-doped polysilicon film layers.
  • the doping concentration of phosphorus ions in the second doped portion 212 of the first active layer 210 may be the same as the doping concentration of phosphorus ions in the second active layer 230. Or the doping concentration of phosphorus ions in the second doped portion 212 may be greater than the doping concentration of phosphorus ions in the second active layer 230 .
  • the doping concentration of phosphorus ions in the first doped portion 211 of the first active layer 210 may be the same as that of the second doped portion 212 and the second active layer 230
  • the doping concentration of phosphorus ions inside is different.
  • the doping concentration of phosphorus ions in the first doping part 211 may be smaller than the doping concentration of phosphorus ions in the second doping part 212 and the doping concentration of phosphorus ions in the second active layer 230 .
  • the first doped part 211, the second doped part 212 and the second active layer 230 in the first active layer 210 can be realized by different doping times. Differences in doping concentration of phosphorus ions.
  • the first doped portion 211 of the first active layer 210 can be formed by one doping, and the second doped portion 212 or/and the second active layer 230 can be formed by two or more dopings. .
  • the number of dopings in the first doping part 211, the second doping part 212 and the second active layer 230 is not limited to once, twice, three times..., The specific number of doping times can be adjusted according to the different requirements of the phosphorus ion doping concentrations of the three, and this application does not impose specific restrictions on this.
  • the ratio of the doping ion concentration in the first doping part 211 to the doping ion concentration in the second doping part 212 may be anywhere from 1/10 to 1/5. numerical value.
  • the ratio of the doping ion concentration in the first doping part 211 to the doping ion concentration in the second doping part 212 may be 1:10.
  • the ratio of the doping ion concentration in the first doping part 211 to the doping ion concentration in the second doping part 212 may be 3:20.
  • the ratio of the doping ion concentration in the first doping part 211 to the doping ion concentration in the second doping part 212 may be 1:5.
  • the ratio of the doping ion concentration in the first doping part 211 to the doping ion concentration in the second doping part 212 can also be other values between 1/10 and 1/5.
  • the numerical values in this embodiment are only examples and are not exhaustive.
  • the first doping ion concentration in the first doping part 211 to the doping ion concentration in the second doping part 212 is 1/10 to 1/5.
  • the channel layer 220 may also include doping ions.
  • the doping ions may be phosphorus ions.
  • the doping ion concentration on the side of the channel layer 220 away from the insulating substrate 100 may be greater than the doping ion concentration on the side of the channel layer 220 close to the insulating substrate 100 , so
  • the doping ions in the channel layer 220 may be caused by the downward penetration of phosphorus ions during the doping process of the second active layer 230. Therefore, the concentration of the doping ions penetrating into the channel layer 220 is along the The direction away from the second active layer 230 gradually decreases until there is no doped ion.
  • the first doped part 211 and the second doped part 212 may be disposed on the insulating substrate 100 in the same layer.
  • the first doped portion 211 and the second doped portion 212 can be integrally formed on the insulating substrate 100 by using the polysilicon material that forms the first active layer 210, and then the polysilicon material is modified. A certain degree of doping process is performed to form the first doped portion 211 and the second doped portion 212 which are arranged in the same layer but have different ion doping concentrations.
  • the thickness of the second doped part 212 may be less than or equal to the thickness of the first doped part 211 .
  • the thickness of the second doped part 212 is equal to the thickness of the first doped part 211
  • the first doped part 211 and the second doped part 212 are The portion 212 is a same film layer integrally formed on the insulating substrate 100 by the polysilicon material forming the first active layer 210 .
  • the only difference between the first doped part 211 and the second doped part 212 is the doping ion concentration.
  • the first doped part 211 and the second doped part 212 only need to be manufactured through different times of doping processes.
  • the second doping part 212 has a simple overall manufacturing process and low cost.
  • the first doped part 211 and the second doped part 212 is formed by: after forming the polysilicon material of the first active layer 210 on the insulating substrate 100, photolithography is performed at a position corresponding to the second doped portion 212, so that the second The thickness of the polysilicon material corresponding to the doped portion 212 is smaller than the thickness of the polysilicon material corresponding to the first doping portion 211 .
  • the height of the surface of the second doped portion 212 away from the insulating substrate 100 is lower than that of the second doped portion 212 .
  • the surface height of a doped portion 211 away from the insulating substrate 100 is such that there is a gap between the channel layer 220 and the second doped portion 212 on the first doped portion 211 to avoid Or reduce the possibility of direct contact between the channel layer 220 and the second doped part 212, thereby reducing the direct transmission of carriers from the channel layer 220 to the second doped part 212 or from the second doped part 212
  • the risk of transmission to the channel layer 220 is conducive to further improving the stability of reducing the leakage current of the thin film transistor.
  • the ratio of the thickness of the second doped part 212 to the thickness of the first doped part 211 may be between 1/4 and 1. any value between. Specifically, for example, in one embodiment, the ratio of the thickness of the second doped part 212 to the thickness of the first doped part 211 may be 1/4. In another embodiment, the ratio of the thickness of the second doped part 212 to the thickness of the first doped part 211 may be 1/2. In another embodiment, the ratio of the thickness of the second doped part 212 to the thickness of the first doped part 211 may be 1. It should be noted that the ratio of the thickness of the second doped part 212 to the thickness of the first doped part 211 can also be other values between 1/4 and 1. This embodiment is only for illustration. Rather than being exhaustive.
  • the thickness of the second doped part 212 can satisfy both requirements.
  • the stability requirement of reducing the leakage current of the thin film transistor can also be taken into consideration of the mobility requirement of carriers in the active layer 200 of the thin film transistor to achieve balanced performance.
  • the channel layer 220 in the direction perpendicular to the insulating substrate 100 , the channel layer 220 may correspond to the first doping part 211 , or in other words, the channel layer 220 may correspond to the first doping part 211 .
  • the channel layer 220 may be disposed on the first doped part 211 so that carriers need to pass through the first doped part when transporting between the channel layer 220 and the second doped part 212 211, thereby achieving the effect of extending the channel length of the "channel area" and thereby reducing leakage current.
  • the orthographic projection of the channel layer 220 on the first active layer 210 may partially overlap with the first doped part 211 and the second doped part 212 . That is, the channel layer 220 is disposed on the first doped portion 211 and the second doped portion 212 at the same time, or in other words, the channel layer 220 spans the first doped portion 211 and the second doped portion 212 . the second doped portion 212.
  • the width of the channel layer 220 is extended, which is equivalent to increasing the width of the "channel region", that is, By increasing the "channel width-to-length ratio" of the channel region, the probability of carriers not being captured by the interface gap state during migration is greater, that is, carriers are more likely to drift, which is beneficial to reducing the threshold voltage of the thin film transistor.
  • the distance between the channel layer 220 and the second doped part 212 There are two transmission paths for carriers: path one is that the channel layer 220 is directly connected to the second doping part 212, and path two is that the channel layer 220 is connected to the first doping part 211 through the first doping part 211.
  • the second doping part 212 is connected.
  • the thickness of the second doped part 212 is different from the thickness of the first doped part 211 , then at this time, the distance between the channel layer 220 and the second doped part 212 There is only one transmission path for carriers: the channel layer 220 is connected to the second doping part 212 through the first doping part 211, that is, the second path. At this time, compared with the aforementioned method of transporting carriers through path one and path two, the mobility of the thin film transistor is reduced, but the leakage current can be significantly improved.
  • the orthographic projection of the channel layer 220 on the first active layer 210 is located at Inside the first doped portion 211 and the orthographic projection of the channel layer 220 on the first active layer 210 does not overlap with the second doped portion 212 .
  • the edge of the channel layer 220 does not exceed the boundary line between the first doped portion 211 and the second doped portion 212 , so that the edge of the channel layer 220 is in contact with the second doped portion 212 .
  • the thin film transistor may further include a first insulating layer 300 disposed on the active layer 200 and a gate layer disposed on the first insulating layer 300 . 400, the second insulating layer 500 and the source and drain layer 600 disposed on the second insulating layer 500.
  • the first insulating layer 300 is continuously disposed and covers the surface of the active layer 200 and the surface of the insulating substrate 100 except for the area where the active layer 200 is located. At this time, the first insulating layer 300 covers the surface of the second active layer 230 and the second doped portion 212 of the active layer 200 located on the surface of the stacked structure, so that the second active layer 230 is located on the surface of the stacked structure.
  • the source layer 230 can be insulated from other film layers.
  • the first insulating layer 300 may be an inorganic film layer such as SiOx, SiNx, SiON, or a stack thereof, and the thickness of the first insulating layer 300 may be from 30 nanometers to 200 nanometers.
  • the gate layer 400 may be metal such as Mo, Ti, W, or a stack thereof, and the thickness of the gate layer 400 is 0.1 micron to 1 micron.
  • the second insulating layer 500 may be a stack of SiOx and SiNx.
  • the source and drain layer 600 may be metal such as Mo, Ti, W, Al, Cu, or a stack thereof.
  • the gate layer 400 may be disposed in an annular shape on a side of the first insulating layer 300 away from the active layer 200. Specifically, the gate layer 400 may be disposed with a stacked layer. The first doped portion 211 , the channel layer 220 and the sidewalls of the first insulating layer 300 on the second active layer 230 are disposed in close contact with each other. The annular gate layer 400 surrounds the stacked structure composed of the first doped portion 211 , the channel layer 220 and the second active layer 230 .
  • the orthographic projection of the channel layer 220 on the gate layer 400 at least partially overlaps with the gate layer 400, so that the gate layer 400 can 220 is at least partially opposite, thereby exerting a control effect and realizing the switching control function of the thin film transistor.
  • the annular gate layer 400 has a stronger ability to control the channel layer 220 and can further reduce the leakage current of the vertically structured thin film transistor.
  • the second insulating layer 500 covers the surfaces of the first insulating layer 300 and the gate layer 400 , and the surface of the second insulating layer 500 away from the insulating substrate 100 Arrange it flatly, so that the source and drain layer 600 can be disposed relatively stably on the surface of the second insulating layer 500 .
  • the source and drain layer 600 may include a source electrode 610 and a drain electrode 620, and the first insulating layer 300 and the second insulating layer 500 are provided with the source electrode 610 and the drain electrode respectively.
  • the first via hole 101 and the second via hole 102 corresponding to the pole 620 are along the stack of the first insulating layer 300 and the second insulating layer 500 direction extension.
  • the orthographic projection of the first via hole 101 on the insulating substrate 100 is located within the orthographic projection of the second active layer 230 on the insulating substrate 100
  • the second via hole 102 is located on the insulating substrate 100.
  • the orthographic projection on the insulating substrate 100 is located within the orthographic projection of the second doped portion 212 on the insulating substrate 100 .
  • the source electrode 610 is connected to the second active layer 230 through the first via hole 101
  • the drain electrode 620 is connected to the second doped portion 212 through the second via hole 102 .
  • the first via hole 101 and the second via hole are provided on the first insulating layer 300 and the second insulating layer 500 corresponding to the second active layer 230 and the second doping part 212.
  • hole 102 and connect the source and drain layer 600 to the second active layer 230 and the second doping part 212 through the first via hole 101 and the second via hole 102, so that the The carrier migration path of the thin film transistor needs to pass through the first doping part 211, thereby extending the length of the "channel region", reducing leakage current while taking into account higher mobility; moreover, the source and drain electrodes described in this application
  • the connection structure between the layer 600 and the active layer 200 is simple, the manufacturing process is easy, and the manufacturing cost can be reduced.
  • the gate layer 400 may include a first gate part 410 and a second gate part 420 that are connected together.
  • the first gate part 410 and the second gate part 420 are made integrally. However, due to the stacking height of the second doped part 212, the second gate part 410 and the second gate part 420 are The gate portion on the doped portion 212 protrudes from the gate portions at other locations, that is, the first gate portion 410 and the second gate portion 420 are formed. It can be understood that, due to the “raising” effect of the second doped portion 212 , the second gate portion 420 is positioned away from the surface on the side of the insulating substrate 100 to The distance between the insulating substrate 100 and the insulating substrate 100 is greater than the distance from the surface of the first gate portion 410 away from the insulating substrate 100 to the insulating substrate 100 .
  • the orthographic projection of the channel layer 220 on the first gate portion 410 is located in the first gate portion 410 , and the channel layer 220 is located on the second gate portion 410 .
  • the orthographic projection on the portion 420 at least partially overlaps the second gate portion 420 .
  • the second gate portion 420 when the thickness of the second doped portion 212 is smaller than the thickness of the first doped portion 211, the second gate portion 420 The “bucking" effect it receives is reduced, and the "directly facing" area between it and the channel layer 220 can be increased accordingly, and even the channel layer 220 and the second gate portion 420 are completely opposite to each other. Yes, that is, the orthographic projection of the channel layer 220 on the second gate portion 420 completely overlaps with the second gate portion 420 .
  • the first gate portion 410 since the first gate portion 410 is not “raised” by the second doped portion 212, it can be completely opposite to the channel layer 220, thereby improving the The channel layer 220 has a good control effect.
  • the thin film transistor may further include a light-shielding layer 700 disposed in the insulating substrate 100 .
  • the light-shielding layer 700 is a conductive metal layer, such as Mo, Metals such as Ti and W or their laminates, etc.
  • the orthographic projection of the active layer 200 on the light-shielding layer 700 is located within the light-shielding layer 700 .
  • the light-shielding layer 700 may be disposed between the base substrate 110 and the buffer layer 120 .
  • the buffer layer 120 is provided with a structure connected to the first gate part. 410 corresponds to the third via hole 103, the first gate portion 410 can be connected to the light shielding layer 700 through the third via hole 103, so that the accumulated charges on the gate layer 400 can be introduced into the on the light-shielding layer 700 to reduce charge accumulation on the gate layer 400 and improve the device stability of the thin film transistor.
  • the first active layer 210 is configured to include a first doping part 211 and a second doping part 212 with different doping ion concentrations, so that the second doping part 212 is different from the second active layer 212 .
  • the source layer 230 serves as two "doped regions" of the thin film transistor, and the channel layer 220 and the first doped portion 211 constitute the "channel region" of the thin film transistor, which is equivalent to increasing the The channel length is increased, and a ring-shaped gate layer 400 surrounding the channel layer 220 is provided to enhance the control capability of the channel layer 220, thereby reducing leakage current; furthermore, the first doped portion 211 is doped
  • the mobility of mixed ions is higher than the mobility of the channel layer 220, which is equivalent to improving the mobility of the "channel region" of the thin film transistor. Therefore, the thin film transistor provided by the present application can be better Ground to solve the problems of excessive leakage current and low mobility.
  • embodiments of the present application also provide a method for manufacturing a thin film transistor, which is used to manufacture the thin film transistor described in the above embodiment.
  • the manufacturing method of the thin film transistor may include:
  • S400 Form an insulating source-drain layer 600 on the gate layer 400, and connect the source-drain layer 600 to the first active layer 210 and the second active layer 230, as shown in Shown in Figure 12 and Figure 13.
  • the thin film transistor is manufactured through the above steps, so that the thin film transistor can not only reduce the occupied area and size by using a vertical structure, but also extend the length of the "channel region" through the first doping part 211. This further improves mobility and achieves lower leakage current, and also utilizes the annular gate layer 400 disposed on the peripheral side of the active layer 200 to achieve enhanced control of the channel layer 220, thereby further reducing the vertical structure. reduce the leakage current of the thin film transistor and improve the device performance and stability of the thin film transistor.
  • the S200 step may include:
  • the thickness of the first polysilicon material layer may be 10 to 100 nanometers, and the first polysilicon material layer may be transformed from an a-Si material layer through laser annealing and other processes. .
  • S220 Lightly dope the first polysilicon material layer to form a lightly doped material layer, as shown in Figure 9.
  • the doping ions for lightly doping the first polysilicon material layer may be phosphorus ions.
  • the channel layer 220 can be made from an a-Si material layer with a thickness of 10 nanometers to 200 nanometers, which is converted into a polysilicon material through processes such as laser annealing.
  • S240 Form a second polysilicon material layer on the channel layer 220, as shown in Figure 10.
  • the second polysilicon material layer can be formed by converting an a-Si material layer with a thickness of 50 nanometers to 300 nanometers into polysilicon material through processes such as laser annealing.
  • the first doped part 211, the second doped part 212 and the second active layer 230 of the first active layer 210 are formed through the above steps, so that the second active layer 230
  • the first doped portion 211 and the second doped portion 212 can be formed at the same time, which can effectively improve the production efficiency of the active layer 200 and save mask costs.
  • An embodiment of the present application also provides an electronic device, which may include the thin film transistor described in the above embodiment.

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  • Thin Film Transistor (AREA)

Abstract

本申请提出了一种薄膜晶体管及其电子器件；薄膜晶体管中的有源层包括叠层设置的第一有源层、沟道层和第二有源层，第一有源层包括第一掺杂部和第二掺杂部，第一掺杂部与沟道层、第二掺杂部连接，以及第一掺杂部内的掺杂离子浓度小于第二掺杂部内的离子掺杂浓度；减小了漏电流，并提高了薄膜晶体管的"沟道区"的迁移率。

Description

薄膜晶体管及其电子器件 技术领域
本申请涉及显示技术的领域，具体涉及一种薄膜晶体管及其电子器件。
 背景技术
随着显示技术的不断发展，显示面板对分辨率参数提出了越来越高的要求，因此需要阵列基板具有超高分辨率和亚微米级别的器件尺寸，为了达到这些要求，阵列基板上薄膜晶体管器件的尺寸和占用面积要尽可能地减小，但是常规的薄膜晶体管受到曝光精度和刻蚀精度限制，有源层的沟道长度通常大于1微米，导致薄膜晶体管器件的尺寸和占用面积难以进一步减小。
现阶段，存在垂直结构的薄膜晶体管器件，其通过将有源层的掺杂部与沟道部叠层设置，可以克服尺寸和占用面积较大的问题，同时，为了提高多晶硅（Poly-Si）有源层的迁移率，还需要尽可能地减小沟道长度。但是，垂直结构的薄膜晶体管的沟道长度过小，容易导致漏电流增大，不利于薄膜晶体管的器件稳定性。
 发明概述
本申请提供一种薄膜晶体管及其电子器件，以改善当前垂直结构的薄膜晶体管器件因沟道长度过小导致漏电流增大，进而引起器件稳定性下降的技术问题。
为解决上述问题，本申请提供的技术方案如下：
本申请提供一种薄膜晶体管，包括：
绝缘衬底；以及
有源层，设置于所述绝缘衬底上，所述有源层包括叠层设置的第一有源层、沟道层和第二有源层；
其中，所述第一有源层包括第一掺杂部和第二掺杂部，所述第一掺杂部与所述沟道层、所述第二掺杂部连接，以及所述第一掺杂部内的掺杂离子浓度小于所述第二掺杂部内的掺杂离子浓度。
在本申请的薄膜晶体管中，所述第一掺杂部内的掺杂离子浓度与所述第二掺杂部内的掺杂离子浓度的比值为1/10至1/5。
在本申请的薄膜晶体管中，所述第一掺杂部与所述第二掺杂部同层设置在所述绝缘衬底上，在垂直于所述绝缘衬底的方向上，所述第二掺杂部的厚度小于或等于所述第一掺杂部的厚度。
在本申请的薄膜晶体管中，在垂直于所述绝缘衬底的方向上，所述第二掺杂部的厚度与所述第一掺杂部的厚度的比值为1/4至1。
在本申请的薄膜晶体管中，在垂直于所述绝缘衬底的方向上，所述沟道层与所述第一掺杂部对应；
其中，所述沟道层在所述第一有源层上的正投影与所述第一掺杂部、所述第二掺杂部部分交叠。
在本申请的薄膜晶体管中，在垂直于所述绝缘衬底的方向上，所述沟道层与所述第一掺杂部对应；
其中，所述沟道层在所述第一有源层上的正投影位于所述第一掺杂部内，以及所述沟道层在所述第一有源层上的正投影与所述第二掺杂部不交叠。
在本申请的薄膜晶体管中，所述薄膜晶体管还包括栅极层，所述栅极层呈环形绝缘设置在所述沟道层的周侧；
其中，所述沟道层在所述栅极层上的正投影与所述栅极层至少部分交叠。
在本申请的薄膜晶体管中，所述栅极层包括连接成一体的第一栅极部和第二栅极部，所述第一栅极部设置于所述绝缘衬底的上方，所述第二栅极部绝缘设置于所述第二掺杂部的上方；
其中，所述沟道层在所述第一栅极部上的正投影位于所述第一栅极部内，以及所述沟道层在所述第二栅极部上的正投影与所述第二栅极部至少部分重叠。
在本申请的薄膜晶体管中，所述第二栅极部在所述绝缘衬底上的正投影与所述沟道层在所述绝缘衬底上的正投影部分重叠。
在本申请的薄膜晶体管中，所述沟道层包括掺杂离子，所述沟道层远离所述绝缘衬底一侧的掺杂离子浓度大于所述沟道层靠近所述绝缘衬底一侧的掺杂离子浓度。
在本申请的薄膜晶体管中，所述薄膜晶体管还包括设置于所述有源层与所述栅极层之间的第一绝缘层；
其中，所述第一绝缘层覆盖所述第二掺杂部的表面、所述第二掺杂部的表面和部分所述绝缘衬底的表面。
在本申请的薄膜晶体管中，所述薄膜晶体管还包括第二绝缘层和源漏极层，所述第二绝缘层覆盖所述第一绝缘层和所述栅极层，所述源漏极层设置于所述第二绝缘层上；
其中，所述第一绝缘层和所述第二绝缘层上设置有第一过孔和第二过孔，所述源漏极层通过所述第一过孔与所述第二掺杂部连接，以及所述源漏极层通过所述第二过孔与所述第二掺杂部连接。
在本申请的薄膜晶体管中，所述薄膜晶体管还包括设置于所述绝缘衬底内的遮光层，所述有源层在所述遮光层上的正投影位于所述遮光层内；
其中，所述栅极层与所述遮光层通过第三过孔连接。
本申请还提出了一种电子器件，包括薄膜晶体管，所述薄膜晶体管包括：
绝缘衬底；以及
有源层，设置于所述绝缘衬底上，所述有源层包括叠层设置的第一有源层、沟道层和第二有源层；
其中，所述第一有源层包括第一掺杂部和第二掺杂部，所述第一掺杂部与所述沟道层、所述第二掺杂部连接，以及所述第一掺杂部内的掺杂离子浓度小于所述第二掺杂部内的掺杂离子浓度。
在本申请的电子器件中，所述第一掺杂部内的掺杂离子浓度与所述第二掺杂部内的掺杂离子浓度的比值为1/10至1/5。
在本申请的电子器件中，所述第一掺杂部与所述第二掺杂部同层设置在所述绝缘衬底上，在垂直于所述绝缘衬底的方向上，所述第二掺杂部的厚度小于或等于所述第一掺杂部的厚度。
在本申请的电子器件中，在垂直于所述绝缘衬底的方向上，所述第二掺杂部的厚度与所述第一掺杂部的厚度的比值为1/4至1。
在本申请的电子器件中，在垂直于所述绝缘衬底的方向上，所述沟道层与所述第一掺杂部对应；
其中，所述沟道层在所述第一有源层上的正投影与所述第一掺杂部、所述第二掺杂部部分交叠。
在本申请的电子器件中，在垂直于所述绝缘衬底的方向上，所述沟道层与所述第一掺杂部对应；
其中，所述沟道层在所述第一有源层上的正投影位于所述第一掺杂部内，以及所述沟道层在所述第一有源层上的正投影与所述第二掺杂部不交叠。
在本申请的电子器件中，所述薄膜晶体管还包括栅极层，所述栅极层呈环形绝缘设置在所述沟道层的周侧；
其中，所述沟道层在所述栅极层上的正投影与所述栅极层至少部分交叠。
有益效果
本申请通过将第一有源层设置为包括掺杂离子浓度不同的第一掺杂部和第二掺杂部，使所述第二掺杂部与所述第二有源层分别作为所述薄膜晶体管的两个“掺杂区”，而所述沟道层与所述第一掺杂部构成所述薄膜晶体管的“沟道区”，相当于增大了沟道长度，从而减小漏电流；而且，所述第一掺杂部因掺杂有离子，其迁移率高于所述沟道层的迁移率，相当于提高了所述薄膜晶体管的“沟道区”的迁移率，因此，本申请提供的所述薄膜晶体管可以较好地解决漏电流过大与迁移率较低的问题。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请所述薄膜晶体管的第一种叠层结构示意图；
图2是本申请所述薄膜晶体管的平面结构示意图；
图3是本申请所述薄膜晶体管的第二种叠层结构示意图；
图4是本申请所述薄膜晶体管的第三种叠层结构示意图；
图5是本申请所述薄膜晶体管的第四种叠层结构示意图；
图6是本申请所述薄膜晶体管的第五种叠层结构示意图；
图7是本申请所述薄膜晶体管的制作方法的流程框图；
图8至图13是本申请所述薄膜晶体管的制作方法的制作流程示意图。
附图标记说明：
100、绝缘衬底；101、第一过孔；102、第二过孔；103、第三过孔；110、衬底基板；120、缓冲层；
200、有源层；210、第一有源层；211、第一掺杂部；212、第二掺杂部；220、沟道层；230、第二有源层；
300、第一绝缘层；
400、栅极层；410、第一栅极部；420、第二栅极部；
500、第二绝缘层；
600、源漏极层；610、源极；620、漏极；
700、遮光层。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。此外，应当理解的是，此处所描述的具体实施方式仅用于说明和解释本申请，并不用于限制本申请。在本申请中，在未作相反说明的情况下，使用的方位词如“上”和“下”通常是指装置实际使用或工作状态下的上和下，具体为附图中的图面方向；而“内”和“外”则是针对装置的轮廓而言的。
现阶段，存在垂直结构的薄膜晶体管器件，其通过将有源层的掺杂部与沟道部叠层设置，可以克服尺寸和占用面积较大的问题，同时，为了提高多晶硅（Poly-Si）有源层的迁移率，还需要尽可能地减小沟道长度。但是，垂直结构的薄膜晶体管的沟道长度过小，容易导致漏电流增大，不利于薄膜晶体管的器件稳定性。本申请基于上述技术问题提出了以下方案。
请参阅图1至图6，本申请提供一种薄膜晶体管，包括绝缘衬底100和设置在所述绝缘衬底100上的有源层200，所述有源层200包括叠层设置的第一有源层210、沟道层220和第二有源层230，所述第一有源层210包括第一掺杂部211和第二掺杂部212，所述第一掺杂部211与所述沟道层220、所述第二掺杂部212连接，以及所述第一掺杂部211内的掺杂离子浓度小于所述第二掺杂部212内的离子掺杂浓度。
本申请通过将第一有源层210设置为包括掺杂离子浓度不同的第一掺杂部211和第二掺杂部212，使所述第二掺杂部212与所述第二有源层230分别作为所述薄膜晶体管的两个“掺杂区”，而所述沟道层220与所述第一掺杂部211构成所述薄膜晶体管的“沟道区”，相当于增大了沟道长度，从而减小漏电流；而且，所述第一掺杂部211因掺杂有离子，其迁移率高于所述沟道层220的迁移率，相当于提高了所述薄膜晶体管的“沟道区”的迁移率，因此，本申请提供的所述薄膜晶体管可以较好地解决垂直薄膜晶体管的漏电流过大与迁移率较低的问题。
现结合具体实施例对本申请的技术方案进行描述。需说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。
请参阅图1，在本申请的薄膜晶体管中，所述绝缘衬底100可以包括衬底基板110和设置在所述衬底基板110上的缓冲层120，所述衬底基板110可以是玻璃基板或者聚酰亚胺基板，所述缓冲层120可以是为SiOx、SiNx、SiON等无机膜层或其叠层。
在本实施例中，所述有源层200的材料可以是多晶硅材料。
在本实施例中，所述第一有源层210与所述第二有源层230可以是磷离子掺杂的多晶硅膜层。
在本实施例中，所述第一有源层210中的所述第二掺杂部212内磷离子的掺杂浓度可以与所述第二有源层230内磷离子的掺杂浓度相同，或者所述第二掺杂部212内磷离子的掺杂浓度可以大于所述第二有源层230内磷离子的掺杂浓度。
在本实施例中，所述第一有源层210中的所述第一掺杂部211内磷离子的掺杂浓度可以与所述第二掺杂部212及所述第二有源层230内的磷离子的掺杂浓度不同。具体地，所述第一掺杂部211内磷离子的掺杂浓度可以小于所述第二掺杂部212内磷离子的掺杂浓度及所述第二有源层230内磷离子掺杂浓度。
在本实施例中，所述第一有源层210中的所述第一掺杂部211、所述第二掺杂部212及所述第二有源层230可以通过不同的掺杂次数实现磷离子的掺杂浓度差异。例如，所述第一有源层210的第一掺杂部211可以通过一次掺杂形成，而第二掺杂部212或/和第二有源层230可以通过两次及以上次数掺杂形成。需要说明的是，本实施例中所述第一掺杂部211、第二掺杂部212及所述第二有源层230内的掺杂次数并不限于一次、两次、三次……，具体掺杂次数可根据三者的磷离子掺杂浓度差异需求进行调整，本申请对此不作具体限制。
在本实施例中，所述第一掺杂部211内的掺杂离子浓度与所述第二掺杂部212内的掺杂离子浓度的比值可以是1/10至1/5之间的任意数值。例如，在一实施例中，所述第一掺杂部211内的掺杂离子浓度与第二掺杂部212内的掺杂离子浓度的比值可以是1:10。在另一实施例中，所述第一掺杂部211内的掺杂离子浓度与第二掺杂部212内的掺杂离子浓度的比值可以是3:20。在另一实施例中，所述第一掺杂部211内的掺杂离子浓度与第二掺杂部212内的掺杂离子浓度的比值可以是1:5。需要说明的是，所述第一掺杂部211内的掺杂离子浓度与所述第二掺杂部212内的掺杂离子浓度的比值还可以为1/10至1/5之间的其他数值，本实施例仅作举例说明，而并非穷举。
本实施例通过将第一掺杂部211内的掺杂离子浓度与所述第二掺杂部212内的掺杂离子浓度的比值设置为1/10至1/5，可以使所述第一掺杂部211与所述第二掺杂部212之间具有适宜的掺杂离子浓度差，从而兼顾减小漏电流和提高沟道迁移率的效果。
在本实施例中，所述沟道层220也可以包括掺杂离子，具体地，所述掺杂离子可以是磷离子。
在本实施例中，所述沟道层220远离所述绝缘衬底100一侧的掺杂离子浓度可以大于所述沟道层220靠近所述绝缘衬底100一侧的掺杂离子浓度，所述沟道层220内的掺杂离子可以由所述第二有源层230掺杂过程中磷离子向下渗透而来，因此，渗透进所述沟道层220内的掺杂离子浓度沿着远离所述第二有源层230的方向逐渐减小，直至无掺杂离子。
请参阅图1和图2，在本申请的薄膜晶体管中，所述第一掺杂部211与所述第二掺杂部212可以同层设置在所述绝缘衬底100上，具体地，所述第一掺杂部211与所述第二掺杂部212可以由形成所述第一有源层210的多晶硅材料一体形成在所述绝缘衬底100上，然后再对所述多晶硅材料进行不同程度的掺杂工艺，以形成同层设置但离子掺杂浓度不同的所述第一掺杂部211与所述第二掺杂部212。
在本实施例中，在垂直于所述绝缘衬底100的方向上，所述第二掺杂部212的厚度可以小于或等于所述第一掺杂部211的厚度。
具体地，请参阅图1和图2，当所述第二掺杂部212的厚度等于所述第一掺杂部211的厚度时，所述第一掺杂部211与所述第二掺杂部212即为由形成所述第一有源层210的多晶硅材料一体形成在所述绝缘衬底100上的同层膜层。此时，所述第一掺杂部211与所述第二掺杂部212的区别仅在于掺杂离子浓度不同，只需通过不同次数的掺杂工艺制作所述第一掺杂部211与所述第二掺杂部212，整体制程简单，成本较低。
请参阅图2和图3，当所述第二掺杂部212的厚度小于或等于所述第一掺杂部211的厚度时，所述第一掺杂部211与所述第二掺杂部212的形成方式为：在所述绝缘衬底100形成所述第一有源层210的多晶硅材料之后，再在对应所述第二掺杂部212的位置进行光刻显影，使所述第二掺杂部212对应的所述多晶硅材料的厚度小于所述第一掺杂部211对应的多晶硅材料的厚度。此时，以所述绝缘衬底100靠近所述第一有源层210的表面为基准面，所述第二掺杂部212远离所述绝缘衬底100一侧的表面高度低于所述第一掺杂部211远离所述绝缘衬底100一侧的表面高度，使得所述第一掺杂部211上的所述沟道层220与所述第二掺杂部212之间存在间隙，避免或降低所述沟道层220与所述第二掺杂部212直接接触的可能性，从而降低载流子直接由沟道层220传输至第二掺杂部212或由第二掺杂部212传输至沟道层220的风险，有利于进一步提高减小薄膜晶体管漏电流的稳定性。
在本实施例中，在垂直于所述绝缘衬底100的方向上，所述第二掺杂部212的厚度与所述第一掺杂部211的厚度的比值可以是1/4至1之间的任意数值。具体地，例如，在一实施例中，所述第二掺杂部212的厚度与所述第一掺杂部211的厚度的比值可以是1/4。在另一实施例中，所述第二掺杂部212的厚度与所述第一掺杂部211的厚度的比值可以是1/2。在另一实施例中，所述第二掺杂部212的厚度与所述第一掺杂部211的厚度的比值可以是1。需要说明的是，所述第二掺杂部212的厚度与所述第一掺杂部211的厚度的比值还可以为1/4至1之间的其他数值，本实施例仅作举例说明，而并非穷举。
本实施例通过将所述第二掺杂部212的厚度与所述第一掺杂部211的厚度的比值设置为1/4至1，使所述第二掺杂部212的厚度既能满足减小薄膜晶体管漏电流的稳定性要求，也可兼顾所述薄膜晶体管的有源层200内载流子的迁移率要求，实现性能均衡。
请参阅图4，在本申请的薄膜晶体管中，在垂直于所述绝缘衬底100的方向上，所述沟道层220可以与所述第一掺杂部211对应，或者说，所述沟道层220可以设置在所述第一掺杂部211上，以使载流子在所述沟道层220至所述第二掺杂部212之间传输时需经过所述第一掺杂部211，从而达到延长“沟道区”的沟道长度，进而减小漏电流的效果。
在本实施例中，所述沟道层220在所述第一有源层210上的正投影可以与所述第一掺杂部211、所述第二掺杂部212部分交叠。即，所述沟道层220同时设置在所述第一掺杂部211与所述第二掺杂部212上，或者说，所述沟道层220横跨所述第一掺杂部211与所述第二掺杂部212。此时，在所述第一掺杂部211至所述第二掺杂部212的方向上，所述沟道层220的宽度得到延长，相当于增大了“沟道区”的宽度，即增大了沟道区的“沟道宽长比”，载流子迁移过程中不被界面隙态捕获的几率越大，即载流子更容易漂移，有利于减小薄膜晶体管的阈值电压。
在本实施例中，若所述第二掺杂部212的厚度与所述第一掺杂部211的厚度相同，那么此时所述沟道层220至所述第二掺杂部212之间的载流子存在两个传输路径：路径一为所述沟道层220与第二掺杂部212直接连通，路径二为所述沟道层220通过所述第一掺杂部211与所述第二掺杂部212连通。在薄膜晶体管工作时，大部分的载流子通过所述路径一传输，小部分的载流子通过所述路径传输。此时，所述薄膜晶体管的载流子迁移率更高，但漏电流较大。
在本实施例中，若所述第二掺杂部212的厚度与所述第一掺杂部211的厚度不同，那么此时所述沟道层220至所述第二掺杂部212之间的载流子只存在一个传输路径：所述沟道层220通过所述第一掺杂部211与所述第二掺杂部212连通，即所述路径二。此时，相较于前述的通过路径一和路径二传输载流子的方式而言，所述薄膜晶体管的迁移率有所降低，但漏电流可以得到明显改善。
请参阅图1和图5，在本申请的薄膜晶体管中，在垂直于所述绝缘衬底100的方向上，所述沟道层220在所述第一有源层210上的正投影位于所述第一掺杂部211内，以及所述沟道层220在所述第一有源层210上的正投影与所述第二掺杂部212不交叠。换言之，所述沟道层220的边缘不超出所述第一掺杂部211与所述第二掺杂部212的交界线，从而使所述沟道层220的边缘与所述第二掺杂部212之间在所述第一掺杂部211至所述第二掺杂部212的方向上存在间距，同样可以避免或降低所述沟道层220与所述第二掺杂部212直接接触的可能性，从而降低载流子直接由沟道层220传输至第二掺杂部212或由第二掺杂部212传输至沟道层220的风险，有利于进一步提高减小薄膜晶体管漏电流的稳定性。
请参阅图1，在本申请的薄膜晶体管中，所述薄膜晶体管还可以包括设置于所述有源层200上的第一绝缘层300、设置于所述第一绝缘层300上的栅极层400和第二绝缘层500以及设置于所述第二绝缘层500上的源漏极层600。
在本实施例中，所述第一绝缘层300连续设置并且覆盖所述有源层200的表面和所述绝缘衬底100除了所述有源层200所在区域的表面。此时，所述第一绝缘层300覆盖所述有源层200位于叠层结构表面的所述第二有源层230和所述第二掺杂部212的表面，以使所述第二有源层230能够与其他膜层实现绝缘设置。
在本实施例中，所述第一绝缘层300可以是SiOx、SiNx、SiON等无机膜层或其叠层，所述第一绝缘层300的厚度可以是30纳米至200纳米。
在本实施例中，所述栅极层400可以是Mo、Ti、W等金属或其叠层，所述栅极层400的厚度为0.1微米至1微米。
在本实施例中，所述第二绝缘层500可以是SiOx和SiNx的叠层。
在本实施例中，所述源漏极层600可以是Mo、Ti、W、Al、Cu等金属或其叠层。
在本实施例中，所述栅极层400可以呈环形设置在所述第一绝缘层300远离所述有源层200的一侧，具体地，所述栅极层400可以与叠层设置的所述第一掺杂部211、所述沟道层220及所述第二有源层230上的所述第一绝缘层300的侧壁贴靠设置。环形的所述栅极层400环绕在所述第一掺杂部211、所述沟道层220及所述第二有源层230构成的叠层结构周侧。
在本实施例中，所述沟道层220在所述栅极层400上的正投影与所述栅极层400至少部分交叠，以使所述栅极层400能够对所述沟道层220至少部分正对，从而起到控制效果，实现薄膜晶体管的开关控制功能。环形的所述栅极层400对所述沟道层220的控制能力更强，可进一步减小垂直结构的薄膜晶体管的漏电流。
在本实施例中，所述第二绝缘层500覆盖所述第一绝缘层300和所述栅极层400的表面，以及所述第二绝缘层500远离所述绝缘衬底100一侧的表面平整设置，以使所述源漏极层600可以较为稳定地设置在所述第二绝缘层500的表面。
在本实施例中，所述源漏极层600可以包括源极610和漏极620，所述第一绝缘层300和所述第二绝缘层500上设置有分别与所述源极610和漏极620对应的第一过孔101和第二过孔102，所述第一过孔101与所述第二过孔102沿所述第一绝缘层300与所述第二绝缘层500的叠层方向延伸。其中，所述第一过孔101在所述绝缘衬底100上的正投影位于所述第二有源层230在所述绝缘衬底100上的正投影内，所述第二过孔102在所述绝缘衬底100上的正投影位于所述第二掺杂部212在所述绝缘衬底100上的正投影内。所述源极610通过所述第一过孔101与所述第二有源层230连接，所述漏极620通过所述第二过孔102与所述第二掺杂部212连接。
本实施例通过在所述第二有源层230和所述第二掺杂部212对应的所述第一绝缘层300和所述第二绝缘层500上设置第一过孔101与第二过孔102，并将所述源漏极层600通过所述第一过孔101、所述第二过孔102与所述第二有源层230、所述第二掺杂部212连接，使所述薄膜晶体管的载流子迁移路径需经过所述第一掺杂部211，从而实现延长“沟道区”长度，减小漏电流同时兼顾较高迁移率；而且，本申请所述源漏极层600与所述有源层200的连接结构简单，制程容易，可较好地降低制作成本。
请参阅图1和图3，在本申请的薄膜晶体管中，所述栅极层400可以包括连接成一体的第一栅极部410和第二栅极部420，所述第一栅极部410设置于所述绝缘衬底100上的上方，所述第二栅极部420绝缘设置于所述第二掺杂部212的上方。
在本实施例中，所述第一栅极部410与所述第二栅极部420为一体制作而成，但由于所述第二掺杂部212的叠层高度作用，使得所述第二掺杂部212上的所述栅极部分凸出于其他位置的栅极部分，即形成所述第一栅极部410与所述第二栅极部420。可以理解的是，所述第二栅极部420由于所述第二掺杂部212的“垫高”作用，使得所述第二栅极部420远离所述绝缘衬底100一侧的表面至所述绝缘衬底100的间距大于所述第一栅极部410远离所述绝缘衬底100一侧的表面至所述绝缘衬底100的间距。
在本实施例中，所述沟道层220在所述第一栅极部410上的正投影位于所述第一栅极部410内，以及所述沟道层220在所述第二栅极部420上的正投影与所述第二栅极部420至少部分重叠。
可以理解的是，请参阅图1，当所述第二掺杂部212的厚度与所述第一掺杂部211的厚度相同时，由于受到所述第二掺杂部212的“垫高”作用的影响，所述第二栅极部420与所述沟道层220之间的“正对”面积减小，致使所述沟道层220在所述第二栅极部420上的正投影与所述第二栅极部420部分重叠；请参阅图3，而当所述第二掺杂部212的厚度小于所述第一掺杂部211的厚度时，所述第二栅极部420受到的“垫高”作用减小，其与所述沟道层220的“正对”面积可相应地有所增大，甚至所述沟道层220与所述第二栅极部420完全正对，即所述沟道层220在所述第二栅极部420上的正投影与所述第二栅极部420全部重叠。
在本实施例中，所述第一栅极部410由于未受到所述第二掺杂部212的“垫高”作用，其与所述沟道层220可以实现完全正对，从而对所述沟道层220起到良好的控制效果。
请参阅图1和图6，在本申请的薄膜晶体管中，所述薄膜晶体管还可以包括设置于所述绝缘衬底100内的遮光层700，所述遮光层700为导电金属层，例如Mo、Ti、W等金属或其叠层等。所述有源层200在所述遮光层700上的正投影位于所述遮光层700内。
请参阅图3，在本实施例中，所述遮光层700可以设置在所述衬底基板110和所述缓冲层120之间，所述缓冲层120上设置有与所述第一栅极部410对应的第三过孔103，所述第一栅极部410可以通过所述第三过孔103与所述遮光层700连接，以使所述栅极层400上的积存电荷可以导入至所述遮光层700上，减少所述栅极层400上的电荷积存，提高薄膜晶体管的器件稳定性。
本申请实施例通过将第一有源层210设置为包括掺杂离子浓度不同的第一掺杂部211和第二掺杂部212，使所述第二掺杂部212与所述第二有源层230分别作为所述薄膜晶体管的两个“掺杂区”，而所述沟道层220与所述第一掺杂部211构成所述薄膜晶体管的“沟道区”，相当于增大了沟道长度，并且设置环绕所述沟道层220的环形的栅极层400以增强对沟道层220的控制能力，从而减小漏电流；而且，所述第一掺杂部211因掺杂有离子，其迁移率高于所述沟道层220的迁移率，相当于提高了所述薄膜晶体管的“沟道区”的迁移率，因此，本申请提供的所述薄膜晶体管可以较好地解决漏电流过大与迁移率较低的问题。
请参阅图7至图13，本申请实施例还提供一种薄膜晶体管的制作方法，用于制作上述实施例所述的薄膜晶体管。
在本实施例中，所述薄膜晶体管的制作方法可以包括：
S100、提供一绝缘衬底100，如图8所示；
S200、在所述绝缘衬底100上依次形成叠层设置的第一有源层210、沟道层220和第二有源层230，以构成所述薄膜晶体管的有源层200，如图9和图10所示；
S300、在所述有源层200的周侧形成栅极层400，如图11所示；
S400、在所述栅极层400上形成绝缘设置的源漏极层600，并使所述源漏极层600与所述第一有源层210、所述第二有源层230连接，如图12和图13所示。
本实施例通过以上步骤制作所述薄膜晶体管，使所述薄膜晶体管既可利用垂直结构来减小占用面积和尺寸，还能通过所述第一掺杂部211延长“沟道区”的长度，进而提高迁移率并实现较低的漏电流，而且还利用设置在所述有源层200周侧的环形的栅极层400实现对所述沟道层220的加强控制，进而进一步减小垂直结构的薄膜晶体管的漏电流，提高所述薄膜晶体管的器件性能和稳定性。
在本实施例中，所述S200步骤可以包括：
S210、在所述绝缘衬底100上形成第一多晶硅材料层，如图8所示。
在本实施例中，所述第一多晶硅材料层的厚度可以是10至100纳米，以及所述第一多晶硅材料层可以由a-Si材料层通过激光退火等工艺处理转变而来。
S220、对所述第一多晶硅材料层进行轻掺杂，形成轻掺杂材料层，如图9所示。
在本实施例中，对所述第一多晶硅材料层进行轻掺杂的掺杂离子可以是磷离子。
S230、在部分所述轻掺杂材料层上形成沟道层220，如图10所示。
在本实施例中，所述沟道层220可以由厚度为10纳米至200纳米的a-Si材料层通过激光退火等工艺处理转变为多晶硅材料而成。
S240、在所述沟道层220上形成第二多晶硅材料层，如图10所示。
在本实施例中，所述第二多晶硅材料层可以由厚度为50纳米至300纳米的a-Si材料层通过激光退火等工艺处理转变为多晶硅材料而成。
S250、对所述第二多晶硅材料层和所述轻掺杂材料层除了所述沟道层220对应的区域进行二次掺杂，同时形成位于所述沟道层220远离所述绝缘衬底100一侧的第二有源层230和位于所述沟道层220一侧下方的所述第二掺杂部212，所述轻掺杂材料层未被二次掺杂的部分即为所述第一掺杂部211，如图10所示。
本实施例通过以上步骤形成所述第一有源层210的所述第一掺杂部211、第二掺杂部212以及所述第二有源层230，使所述第二有源层230与所述第一掺杂部211、所述第二掺杂部212可以同时形成，可有效提升所述有源层200的制作效率，节省光罩成本。
本申请实施例还提供一种电子器件，所述电子器件可以包括以上实施例所述的薄膜晶体管。
以上对本申请实施例所提供的一种薄膜晶体管及其电子器件进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种薄膜晶体管，其包括：
    绝缘衬底；以及
    有源层，设置于所述绝缘衬底上，所述有源层包括叠层设置的第一有源层、沟道层和第二有源层；
    其中，所述第一有源层包括第一掺杂部和第二掺杂部，所述第一掺杂部与所述沟道层、所述第二掺杂部连接，以及所述第一掺杂部内的掺杂离子浓度小于所述第二掺杂部内的掺杂离子浓度。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述第一掺杂部内的掺杂离子浓度与所述第二掺杂部内的掺杂离子浓度的比值为1/10至1/5。
  3. 根据权利要求1所述的薄膜晶体管，其中，所述第一掺杂部与所述第二掺杂部同层设置在所述绝缘衬底上，在垂直于所述绝缘衬底的方向上，所述第二掺杂部的厚度小于或等于所述第一掺杂部的厚度。
  4. 根据权利要求3所述的薄膜晶体管，其中，在垂直于所述绝缘衬底的方向上，所述第二掺杂部的厚度与所述第一掺杂部的厚度的比值为1/4至1。
  5. 根据权利要求3所述的薄膜晶体管，其中，在垂直于所述绝缘衬底的方向上，所述沟道层与所述第一掺杂部对应；
    其中，所述沟道层在所述第一有源层上的正投影与所述第一掺杂部、所述第二掺杂部部分交叠。
  6. 根据权利要求3所述的薄膜晶体管，其中，在垂直于所述绝缘衬底的方向上，所述沟道层与所述第一掺杂部对应；
    其中，所述沟道层在所述第一有源层上的正投影位于所述第一掺杂部内，以及所述沟道层在所述第一有源层上的正投影与所述第二掺杂部不交叠。
  7. 根据权利要求6所述的薄膜晶体管，其中，所述薄膜晶体管还包括栅极层，所述栅极层呈环形绝缘设置在所述沟道层的周侧；
    其中，所述沟道层在所述栅极层上的正投影与所述栅极层至少部分交叠。
  8. 根据权利要求7所述的薄膜晶体管，其中，所述栅极层包括连接成一体的第一栅极部和第二栅极部，所述第一栅极部设置于所述绝缘衬底的上方，所述第二栅极部绝缘设置于所述第二掺杂部的上方；
    其中，所述沟道层在所述第一栅极部上的正投影位于所述第一栅极部内，以及所述沟道层在所述第二栅极部上的正投影与所述第二栅极部至少部分重叠。
  9. 根据权利要求8所述的薄膜晶体管，其中，所述第二栅极部在所述绝缘衬底上的正投影与所述沟道层在所述绝缘衬底上的正投影部分重叠。
  10. 根据权利要求1所述的薄膜晶体管，其中，所述沟道层包括掺杂离子，所述沟道层远离所述绝缘衬底一侧的掺杂离子浓度大于所述沟道层靠近所述绝缘衬底一侧的掺杂离子浓度。
  11. 根据权利要求7所述的薄膜晶体管，其中，所述薄膜晶体管还包括设置于所述有源层与所述栅极层之间的第一绝缘层；
    其中，所述第一绝缘层覆盖所述第二掺杂部的表面、所述第二掺杂部的表面和部分所述绝缘衬底的表面。
  12. 根据权利要求11所述的薄膜晶体管，其中，所述薄膜晶体管还包括第二绝缘层和源漏极层，所述第二绝缘层覆盖所述第一绝缘层和所述栅极层，所述源漏极层设置于所述第二绝缘层上；
    其中，所述第一绝缘层和所述第二绝缘层上设置有第一过孔和第二过孔，所述源漏极层通过所述第一过孔与所述第二掺杂部连接，以及所述源漏极层通过所述第二过孔与所述第二掺杂部连接。
  13. 根据权利要求7所述的薄膜晶体管，其中，所述薄膜晶体管还包括设置于所述绝缘衬底内的遮光层，所述有源层在所述遮光层上的正投影位于所述遮光层内；
    其中，所述栅极层与所述遮光层通过第三过孔连接。
  14. 一种电子器件，其包括薄膜晶体管，所述薄膜晶体管包括：
    绝缘衬底；以及
    有源层，设置于所述绝缘衬底上，所述有源层包括叠层设置的第一有源层、沟道层和第二有源层；
    其中，所述第一有源层包括第一掺杂部和第二掺杂部，所述第一掺杂部与所述沟道层、所述第二掺杂部连接，以及所述第一掺杂部内的掺杂离子浓度小于所述第二掺杂部内的掺杂离子浓度。
  15. 如权利要求14所述的电子器件，其中，所述第一掺杂部内的掺杂离子浓度与所述第二掺杂部内的掺杂离子浓度的比值为1/10至1/5。
  16. 如权利要求14所述的电子器件，其中，所述第一掺杂部与所述第二掺杂部同层设置在所述绝缘衬底上，在垂直于所述绝缘衬底的方向上，所述第二掺杂部的厚度小于或等于所述第一掺杂部的厚度。
  17. 如权利要求16所述的电子器件，其中，在垂直于所述绝缘衬底的方向上，所述第二掺杂部的厚度与所述第一掺杂部的厚度的比值为1/4至1。
  18. 如权利要求16所述的电子器件，其中，在垂直于所述绝缘衬底的方向上，所述沟道层与所述第一掺杂部对应；
    其中，所述沟道层在所述第一有源层上的正投影与所述第一掺杂部、所述第二掺杂部部分交叠。
  19. 如权利要求16所述的电子器件，其中，在垂直于所述绝缘衬底的方向上，所述沟道层与所述第一掺杂部对应；
    其中，所述沟道层在所述第一有源层上的正投影位于所述第一掺杂部内，以及所述沟道层在所述第一有源层上的正投影与所述第二掺杂部不交叠。
  20. 如权利要求19所述的电子器件，其中，所述薄膜晶体管还包括栅极层，所述栅极层呈环形绝缘设置在所述沟道层的周侧；
    其中，所述沟道层在所述栅极层上的正投影与所述栅极层至少部分交叠。
PCT/CN2023/104225 2022-08-30 2023-06-29 薄膜晶体管及其电子器件 Ceased WO2024045860A1 (zh)

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