WO2024045731A1 - 一种三维封装结构及其制备方法 - Google Patents

一种三维封装结构及其制备方法 Download PDF

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Publication number
WO2024045731A1
WO2024045731A1 PCT/CN2023/097801 CN2023097801W WO2024045731A1 WO 2024045731 A1 WO2024045731 A1 WO 2024045731A1 CN 2023097801 W CN2023097801 W CN 2023097801W WO 2024045731 A1 WO2024045731 A1 WO 2024045731A1
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WIPO (PCT)
Prior art keywords
layer
tsv
rewiring
substrates
bridge
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PCT/CN2023/097801
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English (en)
French (fr)
Inventor
陈彦亨
林正忠
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盛合晶微半导体(江阴)有限公司
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Publication of WO2024045731A1 publication Critical patent/WO2024045731A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques

Definitions

  • the present invention relates to the field of semiconductor packaging, and in particular to a three-dimensional packaging structure and a preparation method thereof.
  • SiP System In a Package
  • SiP integrates multiple functional chips, including processors, memory and other functional wafers, into one package to achieve a basically complete function.
  • TSV interposer interposer substrate with through silicon vias
  • the diameter of its through hole is between 1 ⁇ m-50 ⁇ m, which is difficult to produce and the yield rate is low.
  • the larger the area of the TSV interposer the lower its yield rate is. , so the cost of the entire interposer substrate used by SIP is relatively high.
  • the electrical signal transmission between these heterogeneous chips and external circuits relies on the packaging substrate located under the TSV interposer substrate.
  • the packaging substrate implements low-density interconnection.
  • the internal connection lines and solder joints (such as C4 solder joints) are not as dense as those inside the TSV interposer substrate (such as C2 solder joints), because the low-density packaging substrate is directly bonded to the high-density TSV interposer substrate.
  • the packaging substrate must have many interconnection layers to meet the connection requirements.
  • the solder joint bonding of layer substrates must make the solder joints of the packaging substrate very densely designed, which further increases the production cost of the packaging substrate.
  • the purpose of the present invention is to provide a three-dimensional packaging structure and a preparation method thereof to solve the problem that the existing packaging technology uses a whole TSV interposer substrate to realize interconnection of heterogeneous chips and integrate TSV interposers.
  • the layer substrate is directly electrically connected to the packaging substrate, causing problems such as increased cost and low yield.
  • the present invention provides a method for preparing a three-dimensional packaging structure.
  • the preparation method includes:
  • S1 provide a temporary carrier board, and form a rewiring layer on the upper surface of the temporary carrier board;
  • S4 provide several chips, and bond and connect several of the chips to several of the TSV bridge substrates;
  • S7 Provide a packaging substrate with packaging pads, and bond the rewiring layer to the packaging substrate through the packaging pads and the rewiring layer solder joints.
  • the preparation method of the rewiring layer described in S1 includes:
  • the method for preparing the redistribution layer further includes: S17, repeating steps S11 to S16 at least once to prepare multiple layers of the redistribution layer.
  • the preparation method of the rewiring layer also includes: S10, the step of forming a metal seed layer on the upper surface of the temporary carrier; at this time, after removing the second mask layer in S15 , before forming the first dielectric layer, further including the step of removing the metal seed layer not covered by the first metal pattern layer.
  • the step of forming a release layer on the upper surface of the temporary carrier board is also included; at this time, when the temporary carrier board is removed in S6, It also includes the step of removing the release layer.
  • S4 after a plurality of the chips are bonded and connected to a plurality of the TSV bridge substrates, it also includes the step of filling the gaps between the several chips and the plurality of TSV bridge substrates with a filling material layer. ;
  • the rewiring layer and the packaging substrate are further included in the step.
  • the preparation method further includes: S8, the step of arranging a heat dissipation plate on a surface of the packaging substrate connected to the rewiring layer, wherein the heat dissipation plate covers a plurality of the chips therein. .
  • the three-dimensional packaging structure includes:
  • Packaging substrate rewiring layer, several TSV bridge substrates, several chips and plastic packaging material layers; among them,
  • the rewiring layer is located on the upper surface of the packaging substrate and is bonded to the packaging substrate;
  • a plurality of the TSV bridge substrates are located on the upper surface of the redistribution layer, and are bonded and connected to the redistribution layer;
  • a plurality of the chips are located on the upper surfaces of a plurality of the TSV bridge substrates, which are bonded and connected to a plurality of the TSV bridge substrates;
  • the plastic sealing material layer is formed on the upper surface of the redistribution layer, and covers a plurality of the TSV bridge substrates and a plurality of the chips.
  • the three-dimensional packaging structure further includes a heat dissipation plate, which is disposed on the upper surface of the packaging substrate and encloses several of the chips therein.
  • the three-dimensional packaging structure further includes a filling material layer formed in the gaps between a plurality of the TSV bridge substrates and the rewiring layer, a plurality of the chips and a plurality of the TSV bridge substrates. Within the gap of bonding connection, and within the gap of bonding connection between the redistribution layer and the packaging substrate.
  • TSV bridge substrates Use several smaller TSV bridge substrates to replace the entire TSV interposer substrate to achieve high-density interconnection between different chips. This can increase the production yield of TSV bridge substrates and reduce costs without affecting the interconnection function;
  • the high connection density TSV bridge substrate is first connected to the medium connection density rewiring layer, and then the rewiring layer is connected to the lower density packaging substrate, which reduces the number of interconnection layers inside the packaging substrate and avoids the need for multi-layer substrates. Risk of low production yield;
  • the rewiring layer produced by the new process has good flatness and high signal transmission reliability.
  • Figure 1 shows a flow chart of a method for preparing a three-dimensional packaging structure according to the present invention.
  • FIG. 2 shows a flow chart of the preparation method of the redistribution layer according to the present invention.
  • Figure 3 shows a schematic structural diagram after forming the release layer according to the present invention.
  • FIG. 4 shows a schematic structural diagram after forming a metal seed layer according to an embodiment of the present invention.
  • FIG. 5 shows a schematic structural diagram after forming the first mask layer according to the present invention.
  • FIG. 6 shows a schematic structural diagram after forming the first metal pattern layer according to the present invention.
  • FIG. 7 is a schematic structural diagram after removing the first mask layer according to the present invention.
  • FIG. 8 shows a schematic structural diagram after forming the second mask layer according to the present invention.
  • FIG. 9 is a schematic structural diagram after forming the first metal pillar layer according to the present invention.
  • FIG. 10 shows a schematic structural diagram after removing the second mask layer and the metal seed layer according to an embodiment of the present invention.
  • FIG. 11 is a schematic structural diagram after forming the first dielectric layer according to the present invention.
  • FIG. 12 shows a schematic structural diagram after thinning the first dielectric layer according to the present invention.
  • Figure 13 shows a schematic structural diagram after forming a multi-layer redistribution layer according to the present invention.
  • Figure 14 shows a schematic structural diagram of the TSV bridge substrate and the rewiring layer after bonding according to the present invention.
  • FIG. 15 shows a schematic structural diagram after forming the first plastic sealing layer according to the embodiment of the present invention.
  • FIG. 16 shows a schematic structural diagram after thinning the first plastic sealing layer according to the embodiment of the present invention.
  • Figure 17 shows a schematic structural diagram of the chip and the TSV bridge substrate after bonding according to the present invention.
  • FIG. 18 is a schematic structural diagram after forming the second plastic sealing layer according to the embodiment of the present invention.
  • Figure 19 shows a schematic structural diagram after thinning the second plastic sealing layer according to the embodiment of the present invention.
  • Figure 20 shows a schematic structural diagram after removing the temporary carrier board according to the present invention.
  • FIG. 21 is a schematic structural diagram after forming a protective layer according to an embodiment of the present invention.
  • FIG. 22 shows a schematic structural diagram after forming a protective layer mask layer according to the embodiment of the present invention.
  • FIG. 23 shows a schematic structural diagram after forming the rewiring layer solder joints according to the present invention.
  • Figure 24 shows a schematic structural diagram of the redistribution layer and the packaging substrate after bonding according to the present invention.
  • Figure 25 shows a schematic structural diagram after filling the filling material layer according to the present invention.
  • Figure 26 shows a schematic structural diagram after installing a heat dissipation plate according to the present invention.
  • 10 Three-dimensional packaging structure
  • 100 Rewiring layer
  • 101 Rewiring layer solder joints
  • 110 Temporary carrier board
  • 111 Release layer
  • 112 Protective layer
  • 113 Window
  • 114 Solder joint mask layer
  • 115 opening
  • 121 first mask layer
  • 122 second mask layer
  • 130 metal seed layer
  • 140 first metal pattern layer
  • 150 first metal pillar layer
  • 160 first dielectric layer
  • 200 TSV bridge substrate
  • 300 plastic encapsulation layer
  • 310 first plastic encapsulation layer
  • 320 second plastic encapsulation layer
  • 400 chip
  • 410 first type chip
  • 420 second type chip
  • 500 packaging substrate
  • 600 heat sink
  • 700 Filling material layer.
  • This embodiment provides a method for preparing a three-dimensional packaging structure 10.
  • the method for preparing the three-dimensional packaging structure 10 includes: steps S1) to step S7). Specifically, step S8) is also included.
  • Step S1) Provide a temporary carrier board 110, and form the redistribution layer 100 on the upper surface of the temporary carrier board 110.
  • the temporary carrier 110 may be a glass carrier, a ceramic carrier, etc.
  • a release layer 111 is formed on the upper surface of the temporary carrier board 110 .
  • the upper surface of the release layer 111 is equivalent to the upper surface of the temporary carrier 110 , that is, the redistribution layer 100 is formed on the upper surface of the release layer 111 ; it can be formed on the temporary carrier by, for example, spin coating.
  • a release layer 111 is formed on the board 110; the release layer 111 can be formed of an adhesive, such as ultraviolet glue, photothermal conversion adhesive and other types of adhesives; the release layer 111 can be decomposed under the action of light and heat, so that it can be The temporary carrier 110 is detached from the overlying structure formed in subsequent steps.
  • the preparation method of the redistribution layer 100 includes: steps S11) to step S16). More specifically, it also includes step S10) and step S17).
  • Step S10) As shown in FIG. 4 , a metal seed layer 130 is formed on the upper surface of the temporary carrier 110 .
  • the metal seed layer 130 covers the upper surface of the release layer 111; the metal seed layer 130 can be formed by sputtering or a suitable technology; it should be noted that the metal seed layer 130 can include a first metal layer and a second metal layer located on the first metal layer.
  • a second metal layer on a metal layer, the first metal layer is, for example, a titanium layer, and the second metal layer is, for example, a copper layer.
  • the first mask layer 121 is, for example, patterned photoresist, which has a first opening pattern that exposes the upper surface of the temporary carrier 110 , that is, exposes the upper surface of the metal seed layer 130 .
  • electroplating or chemical plating is used to grow and form the first metal pattern layer 140; in some embodiments, sputtering, deposition, etc. may also be used to form the first metal pattern layer 140.
  • a temporary carrier is used to form the first metal pattern layer 140.
  • the first mask layer 121 can be removed through a process such as ashing, and the opening shape of the second mask layer 122 can be circular, elliptical or similar.
  • the first metal pillar layer 150 is grown and formed by electroplating or electroless plating. This method also requires temporary processing before forming the first mask layer 121 .
  • a metal seed layer is formed on the upper surface of the carrier plate 110 by sputtering or a suitable technique, and then based on the first metal pattern layer exposed by the second mask layer 122, the first metal pillar is grown by electroplating or chemical plating.
  • Layer 150 in some embodiments, sputtering, deposition, etc. may also be used to form the first metal pillar layer 150.
  • the metal seed layer 130 does not need to be formed on the upper surface of the temporary carrier 110. That is, step S10) is not required.
  • the second mask layer 122 is removed by, for example, an ashing process; the first dielectric layer 160 can be formed by methods such as spin coating, lamination, and deposition; in this embodiment, electroplating or chemical
  • the first metal pattern layer 140 and the first metal pillar layer 150 are grown by plating. Therefore, before forming the first dielectric layer 160, as shown in FIG. 10, it is necessary to use flash etching or similar processes to remove unused first metal layers.
  • the pattern layer 140 covers the metal seed layer 130 .
  • a chemical mechanical polishing (CMP) process may be used to grind and thin the first dielectric layer 160 .
  • CMP chemical mechanical polishing
  • the first dielectric layer 160 after grinding and polishing is flat, and the metal pattern layer and metal pillar layer formed by the subsequent process will not have unevenness, which can make the lines of the metal pattern layer flat and uniform, and the formed rewiring layer can be used even in ultra-high frequencies.
  • the components will not cause signal attenuation or loss.
  • Step S17 As shown in FIG. 13 , repeat steps S11 to S16 at least once to prepare multiple layers of the rewiring layer 100 .
  • steps S11 to S16 can be repeated multiple times to complete the preparation of the multi-layer rewiring layer 100.
  • a metal pattern layer is first formed, and then a metal pillar layer is formed based on the metal pattern layer. Finally, then a dielectric layer covering the metal pattern layer and metal pillar layer is formed. The dielectric layer is polished and smoothed, which does not affect the flatness of the subsequent rewiring layer, ultimately ensuring that the connection lines of the multi-layer rewiring layer are flat.
  • Figure 13 a multi-layer redistribution layer with a 3-layer structure is shown.
  • Step S2) As shown in FIG. 14 , several TSV bridge substrates 200 are provided, and the plurality of TSV bridge substrates 200 are bonded and connected to the rewiring layer 100 .
  • TSV bridge substrates 200 there are several TSV bridge substrates 200, which are bonded and connected to the rewiring layer 100 respectively.
  • the size and density of the through silicon vias TSVs in each TSV bridge substrate 200 can be flexibly adjusted, and the solder joints formed on the surface of the TSV bridge substrate 200 can be flexibly adjusted.
  • the density of points can also be adjusted flexibly.
  • a TSV bridge substrate 200 with a high density of through silicon vias is used for interconnection
  • a TSV bridge substrate 200 with a lower density of through silicon vias is used for interconnection.
  • the structural chips are interconnected through an entire TSV interposer substrate. When manufacturing multiple TSV bridge substrates, the yield rate is higher and the manufacturing cost is lower. It should be noted that in some embodiments, after bonding several TSV bridge substrates 200 to the redistribution layer 100, a material layer (not shown) needs to be filled in the gaps between them.
  • Step S3) As shown in FIGS. 15 and 16 , a first plastic sealing layer 310 is formed on the upper surface of the redistribution layer 100 , and the first plastic sealing layer 310 exposes the solder joints of the TSV bridge substrate 200 .
  • a first plastic sealing layer 310 is formed on the upper side of the redistribution layer 100 , and the first plastic sealing layer 310 covers the TSV bridge substrate 200 ; then, as shown in FIG. 16 , thin the first plastic encapsulation layer 310 until the upper surface of the TSV bridge substrate 200 is exposed.
  • the method of forming the first plastic sealing layer 310 includes but is not limited to compression molding, molding, liquid sealing molding, vacuum lamination and spin coating, and its materials include but is not limited to polyimide, silicone and epoxy resin; less
  • the method of thinning the first plastic encapsulation layer 310 includes but is not limited to grinding process (ie, backside grinding).
  • Step S4) As shown in Figure 17, several chips 400 are provided, and several of the chips 400 are bonded to several of the TSV bridge substrates 200.
  • the chip 400 provided can be either a bare chip or a preliminarily packaged chip; the number of the chips 400 should be at least two, and usually, it is greater than or equal to 3; and, the chip 400 can be Application specific integrated circuit (ASIC) chips, analog chips, sensor chips, wireless and radio frequency chips, voltage regulator chips or memory chips. Different types of chips usually have different process accuracy, and the density and diameter of the surface pads are also different. .
  • ASIC Application specific integrated circuit
  • the first type chip 410 has a higher density of solder joints on the active surface and a smaller diameter of solder joints than the second type chip 420; therefore, compared with the second type chip 420,
  • the TSV bridge substrate 200 bonded to the first type chip 410 has a higher through silicon hole density, smaller surface solder joint diameter, higher manufacturing difficulty and higher cost; the TSV bridge bonded to the second type chip 420
  • the substrate 200 has a relatively low density of through silicon holes, a relatively large diameter of surface solder joints, low manufacturing difficulty, and low cost.
  • multiple smaller TSV bridge substrates 200 can flexibly adjust the process accuracy, improve yield, and reduce costs. It should be noted that in some embodiments, after bonding several chips 400 to several TSV bridge substrates 200 , a material layer (not shown) needs to be filled in the gaps between them.
  • Step S5) As shown in Figure 18, a second plastic sealing layer 320 is formed on the upper surface of the first plastic sealing layer.
  • the method of forming the second plastic sealing layer 320 is the same as the method of forming the first plastic sealing layer 310. It should be noted that the second plastic sealing layer 320 can be thinned to a certain thickness to meet the thickness requirements of the three-dimensional packaging structure. , you may also choose not to thin the second plastic sealing layer 320; as shown in FIG. 19, in this embodiment, the second plastic sealing layer 320 is thinned to expose the upper surface of the second type chip.
  • Step S6) As shown in FIGS. 20 to 23 , the temporary carrier board 110 is removed, and the redistribution layer solder joints 101 are formed on a surface of the redistribution layer 100 away from the TSV bridge substrate 200 .
  • heating and/or lighting means can be used to reduce the viscosity of the release layer 111 and the temporary carrier plate 110 is removed. Then, processing methods such as tearing and lighting can be used. , to peel off the release layer 111; of course, the laser peeling process can also be directly used to peel off the laser peeling and rewiring layer 100 from each other. The laser peeling process directly vaporizes the release layer 111 to achieve the separation of the temporary carrier board 110 and the rewiring layer 100. The peeling effect of the rewiring layer 100 results in high processing precision and few remaining impurities.
  • a protective layer 112 can be first formed on the lower surface of the rewiring layer 100 (the side away from the TSV bridge substrate 200).
  • the protective layer 112 can be made of silicon oxide, Silicon nitride, silicon oxynitride or a combination thereof.
  • a laser drilling process, an exposure and development process, a photolithography and etching process or a combination thereof can be used to form the window 113 in the protective layer.
  • forming a solder joint mask layer 114 with an opening 115 in the protective layer is formed with an opening 115 in the protective layer. The opening 115 overlaps the window 113, exposing the first metal pattern layer 140 in the rewiring layer 100.
  • the redistribution layer solder joints 101 are formed in the windows 113.
  • the materials of the redistribution layer solder joints 101 include copper, aluminum, lead-free alloys (for example, gold, tin, silver, aluminum or copper alloys) or lead alloys (for example, lead -Pin alloy).
  • the rewiring layer solder joints 101 can be conductive bumps, C4 (controlled collapse chip connection, C4) bumps, solder balls and other structures.
  • Step S7) As shown in Figure 24, provide a packaging substrate 500 with packaging pads, and bond the rewiring layer 100 to the packaging substrate through the packaging pads and the rewiring layer solder joints. 500 on.
  • ultrasonic bonding, thermocompression bonding or thermo-ultrasonic bonding can be used to realize the bonding connection between the rewiring layer 100 and the packaging substrate 500 .
  • the bonded structure is the three-dimensional packaging structure 10 .
  • a material layer 700 needs to be filled in the gap between the rewiring layer 100 and the packaging substrate 500 .
  • the upper and lower positional relationships of the inter-layer structures within the three-dimensional packaging structure 10 also change accordingly. The resulting limitations on the positional relationships may be inconsistent with the previous and subsequent descriptions, which should be understood.
  • Step S8) As shown in FIG. 26, a heat dissipation plate 600 is provided above the packaging substrate 500, wherein the heat dissipation plate 600 covers a plurality of the chips 400 therein.
  • the heat dissipation plate 600 conducts and dissipates the heat generated by the chip.
  • the three-dimensional packaging structure 10 includes: a packaging substrate 500, a rewiring layer 100, a plurality of TSV bridge substrates 200, a plurality of chips 400 and Plastic material layer 300 , wherein the rewiring layer 100 is located on the upper surface of the packaging substrate 500 and is bonded to the packaging substrate 500 ; the plurality of TSV bridge substrates 200 are located on the rewiring layer 100 The upper surface is bonded and connected to the rewiring layer 100; the plurality of chips 400 are located on the upper surface of the TSV bridge substrate 200, which is bonded and connected to the TSV bridge substrate 200; the plastic packaging material layer 300 It is formed on the upper surface of the redistribution layer 100 and covers a plurality of the TSV bridge substrates 200 and a plurality of the chips 400 .
  • the packaging substrate 500, the rewiring layer 100, the TSV bridge substrate 200, and the chip 400 are stacked in sequence from bottom to top, and each layer is connected by bonding; the wiring density of the packaging substrate 500 is lower than that of the rewiring layer.
  • the wiring density of the wiring layer 100 and the wiring density of the rewiring layer 100 is lower than that of the TSV bridge substrate 200.
  • Several heterogeneous chips 400 communicate with each other through multiple TSV bridge substrates 200 with different wiring densities. The lines are short and the communication quality is low.
  • the TSV bridge substrate 200 is electrically connected to the packaging substrate 500 through the rewiring layer 100, and the rewiring layer 100 serves as a buffer structure between the two, replacing part of the electrical connection function of the packaging substrate 500. This enables the packaging substrate 500 to complete electrical signal transmission without preparing more layers, thereby reducing the preparation cost of the multi-layer packaging substrate.
  • the three-dimensional packaging structure also includes a filling material layer 700 and a heat dissipation plate 600.
  • the filling material layer 700 is formed on a plurality of TSV bridge substrates 200 and the rewiring layer 100 that are bonded and connected.
  • the heat dissipation plate 600 is provided on the upper surface of the packaging substrate 500 .
  • the material of the filling material layer 700 includes but is not limited to epoxy resin.
  • the filling material layer 700 can protect the rewiring layer 100 from the influence of the environment and reduce the influence of thermal expansion mismatch between the rewiring layer 100 and the packaging substrate 500, so that the reliability of the component can be greatly improved.
  • the heat sink 600 conducts and dissipates heat for the chip 400 .
  • the three-dimensional packaging structure and its preparation method of the present invention use several smaller TSV bridge substrates instead of the entire TSV interposer substrate to achieve high-density interconnection between different chips without affecting the interconnection function. It can increase the production yield of the interposer substrate and reduce the cost; the high connection density interposer substrate is first connected to the medium connection density rewiring layer, and then the rewiring layer is connected to the lower density packaging substrate, so that the inside of the packaging substrate The number of interconnection layers is reduced, avoiding the risk of low yield in multi-layer substrate production; the rewiring layer produced by the new process has good flatness and high signal transmission reliability.

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Abstract

一种三维封装结构（10）及其制备方法，三维封装结构（10）包括：封装基板（500）、重布线层（100）、若干个TSV桥接基板（200）、若干个芯片（400）及塑封材料层（300）；其中，重布线层（100）位于封装基板（500）的上表面，其与封装基板（500）键合连接；若干个TSV桥接基板（200）位于重布线层（100）的上表面，其与重布线层（100）键合连接；若干个芯片（400）位于若干个TSV桥接基板（200）的上表面，其与若干个TSV桥接基板（200）键合连接；塑封材料层（300）形成于重布线层（100）的上表面。能够解决现有封装技术中采用整片的TSV中介层基板实现异构芯片互联、将TSV中介层基板直接与封装基板电连接，造成的成本增加并且良率较低的问题。

Description

一种三维封装结构及其制备方法 技术领域
本发明涉及半导体封装领域，特别是涉及一种三维封装结构及其制备方法。
背景技术
由于终端使用者希望他们使用的设备更小、更快、更节能、性能更高，因此在单一晶元中封装更多的功能，必然成为半导体封装未来的一个的重要趋势。SiP(System In a Package，系统级封装)是一种系统级别的封装，它将两个或多个异构半导体芯片和无源器件组装到一起，形成一个实现特定功能的标准封装体。从架构上来讲，SiP是将多种功能芯片，包括处理器、内存等功能晶元集成在一个封装体内，从而实现一个基本完整的功能。
其通常具有多个呈阵列排布的异构芯片，这些异构芯片依靠位于其下侧的TSV interposer(带硅通孔的中介层基板)实现高密度互联，完成很多运算和数据交流，这样做比较省电，增加带宽。
由于TSV interposer的焊接凸点密度高，精度高，通常情况下，其通孔直径介于1μm-50μm，制作难度高，良率较低，而且TSV interposer的面积愈大，其良率就愈低，因此SIP采用的整片的中介层基板成本较高。
另外，这些异构芯片与外部电路的电信号传输则依靠位于TSV中介层基板下侧的封装基板实现，相较于TSV中介层基板实现的高密度互联，封装基板实现的是低密度互联，其内部的连接线路及焊点(譬如C4焊点)都不如TSV中介层基板内部的连接线路及焊点(譬如C2焊点)密集，由于低密度的封装基板与高密度的TSV中介层基板直接键合连接，封装基板必须具有很多互联层，才能满足连接需求，而封装基板的层数愈多，其制作良率就愈低，成本就愈高；并且，为了使封装基板的焊点与TSV中介层基板的焊点键合，必然要使封装基板的焊点设计的非常密集，这又进一步增加了封装基板的制作成本。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种三维封装结构及其制备方法，用于解决现有封装技术采用整片的TSV中介层基板实现异构芯片互联、将TSV中介层基板直接与封装基板电连接，造成的成本增加并且良率较低的问题。
为实现上述目的，本发明提供一种三维封装结构的制备方法，所述制备方法包括：
S1，提供一临时载板，于所述临时载板上表面形成重布线层；
S2，提供若干个TSV桥接基板，将若干个所述TSV桥接基板与所述重布线层键合连接；
S3，于所述重布线层的上表面形成第一塑封层，所述第一塑封层暴露出所述TSV桥接基板的焊点；
S4，提供若干个芯片，将若干个所述芯片与若干个所述TSV桥接基板键合连接；
S5，于所述第一塑封层的上表面形成第二塑封层；
S6，去除所述临时载板，于所述重布线层远离所述TSV桥接基板的一表面形成重布线层焊点；
S7，提供一带有封装焊盘的封装基板，并通过所述封装焊盘和所述重布线层焊点将所述重布线层键合至所述封装基板上。
可选地，S1中所述重布线层的制备方法包括：
S11，于所述临时载板上表面形成具有第一开口图形的第一掩膜层；
S12，基于所述第一开口图形形成第一金属图形层；
S13，去除所述第一掩膜层，于所述第一金属图形层上形成具有第二开口图形的第二掩膜层，所述第二开口图形至少暴露出所述第一金属图形层的部分上表面；
S14，基于所述第二开口图形形成第一金属柱层；
S15，去除所述第二掩膜层，并于所述临时载板的上表面形成第一介质层，所述第一介质层包覆所述第一金属图形层及所述第一金属柱层；
S16，研磨所述第一介质层直至暴露出所述第一金属柱层的上表面。
可选地，所述重布线层的制备方法还包括：S17，至少重复一次步骤S11～S16，制备得到多层所述重布线层。
可选地，在S11之前，所述重布线层的制备方法还包括：S10，于所述临时载板上表面形成金属种子层的步骤；此时，S15中去除所述第二掩膜层之后，形成所述第一介质层之前，还包括去除未被所述第一金属图形层覆盖的金属种子层的步骤。
可选地，S1中于所述临时载板上表面形成重布线层之前，还包括于所述临时载板上表面形成离型层的步骤；此时，S6中去除所述临时载板时，还包括去除所述离型层的步骤。
可选地，S2中将若干个所述TSV桥接基板与所述重布线层键合连接之后，还包括于若干个所述TSV桥接基板与所述重布线层键合连接的缝隙内填充入填充材料层的步骤；
S4中将若干个所述芯片与若干个所述TSV桥接基板键合连接之后，还包括于若干个所述芯片与若干个所述TSV桥接基板键合连接的缝隙内填充入填充材料层的步骤；
S7中将所述重布线层键合至所述封装基板上之后，还包括于所述重布线层与所述封装基 板键合连接的缝隙内填充入填充材料层的步骤。
可选地，所述制备方法还包括：S8，于所述封装基板连接所述重布线层的一表面设置散热板的步骤，其中，所述散热板将若干个所述芯片包覆于其内。
可选地，所述三维封装结构包括：
封装基板、重布线层、若干个TSV桥接基板、若干个芯片及塑封材料层；其中，
所述重布线层位于所述封装基板的上表面，其与所述封装基板键合连接；
若干个所述TSV桥接基板位于所述重布线层的上表面，其与所述重布线层键合连接；
若干个所述芯片位于若干个所述TSV桥接基板的上表面，其与若干个所述TSV桥接基板键合连接；
所述塑封材料层形成于所述重布线层的上表面，其包覆若干个所述TSV桥接基板及若干个所述芯片。
可选地，所述三维封装结构还包括散热板，其设置在所述封装基板的上表面，将若干个所述芯片包覆于其内。
可选地，所述三维封装结构还包括填充材料层，形成于若干个所述TSV桥接基板与所述重布线层键合连接的缝隙内、若干个所述芯片与若干个所述TSV桥接基板键合连接的缝隙内、及所述重布线层与所述封装基板键合连接的缝隙内。
如上所述，本发明的三维封装结构及其制备方法，
1、采用若干个的较小的TSV桥接基板代替整片的TSV中介层基板实现不同芯片间的高密度互联，在不影响互联功能的基础上能够增加TSV桥接基板的制作良率，减少成本；
2、高连接密度的TSV桥接基板先与中等连接密度的重布线层连接，再由重布线层与更低密度的封装基板连接，使得封装基板内部的互联层层数减少，规避了多层基板制作良率低的风险；
3、新的工艺制作的重布线层，制作形成的重布线层平坦度良好，信号传递可靠性高。
附图说明
图1显示为本发明所述三维封装结构的制备方法的流程图。
图2显示为本发明所述重布线层的制备方法的流程图。
图3显示为本发明所述形成离型层后的结构示意图。
图4显示为本发明实施例所述形成金属种子层后的结构示意图。
图5显示为本发明所述形成第一掩膜层后的结构示意图。
图6显示为本发明所述形成第一金属图形层后的结构示意图。
图7显示为本发明所述去除第一掩膜层后的结构示意图。
图8显示为本发明所述形成第二掩膜层后的结构示意图。
图9显示为本发明所述形成第一金属柱层后的结构示意图。
图10显示为本发明实施例所述去除第二掩膜层及所述金属种子层后的结构示意图。
图11显示为本发明所述形成第一介质层后的结构示意图。
图12显示为本发明所述减薄第一介质层后的结构示意图。
图13显示为本发明所述形成多层重布线层后的结构示意图。
图14显示为本发明所述将TSV桥接基板与重布线层键合后的结构示意图。
图15显示为本发明实施例所述形成第一塑封层后的结构示意图。
图16显示为本发明实施例所述减薄第一塑封层后的结构示意图。
图17显示为本发明所述将芯片与TSV桥接基板键合后的结构示意图。
图18显示为本发明实施例所述形成第二塑封层后的结构示意图。
图19显示为本发明实施例所述减薄第二塑封层后的结构示意图。
图20显示为本发明所述去除临时载板后的结构示意图。
图21显示为本发明实施例所述形成保护层后的结构示意图。
图22显示为本发明实施例所述形成保护层掩膜层后的结构示意图。
图23显示为本发明所述形成重布线层焊点后的结构示意图。
图24显示为本发明所述重布线层与封装基板键合后的结构示意图。
图25显示为本发明所述填充了填充材料层后的结构示意图。
图26显示为本发明所述设置散热板后的结构示意图。
组件标号说明
10：三维封装结构，100：重布线层，101：重布线层焊点，110：临时载板，111：离型层，112：保护层，113：窗，114：焊点掩模层，115：开口，121：第一掩膜层，122：第二掩膜层，130：金属种子层，140：第一金属图形层，150：第一金属柱层，160：第一介质层，200：TSV桥接基板，300：塑封层，310：第一塑封层，320：第二塑封层，400：芯片，410：第一类型芯片，420：第二类型芯片，500：封装基板，600：散热板，700：填充材料层。
10                   三维封装结构
110                  临时载板
111                  离型层
101                  重布线层焊点
112                  保护层
113                  窗
114                  焊点掩模层
115                  开口
100                  重布线层
121                  第一掩膜层
122                  第二掩膜层
130                  金属种子层
140                  第一金属图形层
150                  第一金属柱层
160                  第一介质层
200                  TSV桥接基板
300                  塑封层
310                  第一塑封层
320                  第二塑封层
400                  芯片
410                  第一类型芯片
420                  第二类型芯片
500                  封装基板
600                  散热板
700                  填充材料层
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图1至图26。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
本实施例提供一种三维封装结构10的制备方法，如图1所示，所述三维封装结构10的制备方法包括：步骤S1)～步骤S7)。具体的，还包括步骤S8)。
步骤S1)：提供一临时载板110，于所述临时载板110上表面形成重布线层100。
本实施例中，临时载板110可以是玻璃载板、陶瓷载板等。
具体的，如图3所示，于所述临时载板110上表面形成重布线层100前，于所述临时载板110上表面形成离型层111。
在本实施例中，离型层111的上表面就相当于临时载板110的上表面，也即，重布线层100形成于离型层111的上表面；可以通过例如旋涂法在临时载板110上形成离型层111；离型层111可以由粘合剂形成，例如紫外线胶、光热转换胶等类型的粘合剂；离型层111可在光热作用下分解，从而可将临时载板110在后续步骤中形成的上覆结构中脱离。
具体的，如图2所示，所述重布线层100的制备方法包括：步骤S11)～步骤S16)。更具体的，还包括步骤S10)及步骤S17)。
步骤S10)：如图4所示，于所述临时载板110上表面形成金属种子层130。
本实施例中，金属种子层130覆盖在离型层111上表面；可以采用溅镀或合适的技术形成金属种子层130；需要说明的是，金属种子层130可以包括第一金属层和位于第一金属层上的第二金属层，第一金属层例如是钛层，第二金属层例如是铜层。
步骤S11)：如图5所示，于所述临时载板110的上表面形成具有第一开口图形的第一掩膜层121。
本实施例中，第一掩膜层121例如是图案化的光刻胶，其具有的第一开口图形暴露出临时载板110的上表面，也即暴露出金属种子层130的上表面。
步骤S12)：如图6所示，基于所述第一开口图形形成第一金属图形层140。
本实施例中，采用电镀或化学镀的方式生长形成第一金属图形层140；在一些实施例中，也可以采用溅射、沉积等方式形成第一金属图形层140，相应的，临时载板110上表面就不需要形成金属种子层130，也即不需要步骤S10)；其中，第一金属图形层140可以是铜或其他合适的金属。
步骤S13)：如图7所示，去除所述第一掩膜层121，如图8所示，于所述第一金属图形 层140上形成具有第二开口图形的第二掩膜层122，所述第二开口图形至少暴露出所述第一金属图形层140的部分上表面。
本实施例中，可以通过灰化等工艺移除第一掩膜层121，第二掩膜层122的开口形状可以是圆形、椭圆形或类似形状。
步骤S14)：如图9所示，基于所述第二开口图形形成第一金属柱层150。
本实施例中，与形成第一金属图形层140的方式类似，采用电镀或化学镀的方式生长形成第一金属柱层150；采用此方式也需要在形成第一掩膜层121前，于临时载板110的上表面采用溅镀或合适的技术形成金属种子层，然后以被第二掩膜层122暴露出第一金属图形层为基础，采用电镀或化学镀的方式生长形成第一金属柱层150；在一些实施例中，也可以采用溅射、沉积等方式形成第一金属柱层150，相应的，采用这样的方式时，临时载板110上表面就不需要形成金属种子层130，也即不需要步骤S10)。
步骤S15)：如图10所示，去除所述第二掩膜层122，如图11所示，于所述临时载板110的上表面形成第一介质层160，所述第一介质层160包覆所述金属图形层140及所述金属柱层150。
本实施例中，通过例如灰化工艺移除第二掩膜层122；可以采用例如旋涂、层压(lamination)、沉积等方式形成第一介质层160；其中，本实施例采用电镀或化学镀的方式生长形成第一金属图形层140及第一金属柱层150，因此，在形成第一介质层160前，如图10所示，还需要采用闪蚀等类似工艺去除未被第一金属图形层140覆盖的金属种子层130。
步骤S16)：如图12所示，研磨所述第一介质层160直至暴露出所述第一金属柱层150的上表面。
本实施例中，可以采用化学机械抛光(CMP)工艺研磨减薄第一介质层160。研磨抛光后的第一介质层160平坦，后续制程形成的金属图形层及金属柱层不会有凹凸的状况，能够使得金属图形层线条平坦，均匀，形成的重布线层即使运用在超高频组件中也不会造成讯号衰减、丢失。
步骤S17)：如图13所示，至少重复一次步骤S11～S16，制备得到多层所述重布线层100。
本实施例中，可以多次重复步骤S11～S16完成多层重布线层100的制备，每层的重布线层在制作时，首先形成金属图形层，再基于金属图形层形成金属柱层，最后再形成覆盖在金属图形层及金属柱层上的介质层，介质层被抛光打磨坦化，不影响后续重布线层的平坦性，最终确保了多层重布线层的连接线路平坦。作为示例，如图13所示，显示的是具有3层结构的多层重布线层。
步骤S2)：如图14所示，提供若干个TSV桥接基板200，将若干个所述TSV桥接基板200与所述重布线层100键合连接。
本实施例中，TSV桥接基板200有若干片，分别与重布线层100键合连接，每个TSV桥接基板200内的的硅通孔TSV的大小及密度可以灵活调整，形成于其表面的焊点的密度也可以灵活调整，对于逻辑芯片处使用硅通孔密度高的TSV桥接基板200互联，对于存储芯片处使用硅通孔密度较低的TSV桥接基板200互联，相对于将不同种类的异构芯片通过一整片TSV中介层基板互联，多个TSV桥接基板制造时良率更高，制造成本更低。需要说明的是，在一些实施例中，将若干个TSV桥接基板200与重布线层100键合后，还需于它们键合连接的缝隙内填充材料层(未示出)。
步骤S3)：如图15及图16所示，于所述重布线层100的上表面形成第一塑封层310，所述第一塑封层310暴露出所述TSV桥接基板200的焊点。
本实施例中，首先，如图15所示，于所述重布线层100上侧形成第一塑封层310，所述第一塑封层310包覆TSV桥接基板200；接着，如图16所示，减薄第一塑封层310，直至显露出TSV桥接基板200的上表面。其中，形成第一塑封层310的方法包括但不限于压缩成型、模塑成型、液封成型、真空层压及旋涂，其材料包括但不限于聚酰亚胺、硅胶以及环氧树脂；减薄第一塑封层310的方法包括但不限于磨削工艺(即backside grinding)。
步骤S4)：如图17所示，提供若干个芯片400，将若干个所述芯片400与若干个所述TSV桥接基板200键合连接。
本实施例中，提供的芯片400既可以是裸芯片，也可以是初步封装的芯片；所述芯片400的数量应至少有两个，通常情况下，大于等于3个；并且，芯片400可以是专用的集成电路(ASIC)芯片、模拟芯片、传感器芯片、无线和射频芯片、电压稳压器芯片或存储器芯片，不同类型的芯片通常具有不同的制程精度，表面焊盘的密度及直径大小也不同。本实施例以两种类型芯片作为示例，如图1所示，第一类型芯片410相较于第二类型芯片420，其有源面焊点密度更高，焊点直径更小；因此，与第一类型芯片410键合连接的TSV桥接基板200的硅通孔密度更高，表面焊点直径也更小，制作难度更高，成本较高；与第二类型芯片420键合连接的TSV桥接基板200的硅通孔密度相对较低，表面焊点直径相对较大，制作难度较低，成本较低。相较于通过一整片的TSV桥接基板200互联，多个较小的TSV桥接基板200，可以灵活调整制程精度，提高良率，降低成本。需要说明的是，在一些实施例中，将若干个芯片400与若干个TSV桥接基板200键合后，还需于它们键合连接的缝隙内填充材料层(未示出)。
步骤S5)：如图18所示，于所述第一塑封层上表面形成第二塑封层320。
本实施例中，形成第二塑封层320的方法与形成第一塑封层310的方法相同，需要说明的是，可以选择减薄第二塑封层320至一定厚度，以满足三维封装结构的厚度需求，也可以选择不减薄第二塑封层320；如图19所示，本实施例中，减薄所述第二塑封层320使其暴露出所述第二类型芯片的上表面。
步骤S6)：如图20至图23所示，去除所述临时载板110，于所述重布线层100远离所述TSV桥接基板200的一表面形成重布线层焊点101。
本实施例中，首先，如图20所示，可以采用加热和/或光照手段将离型层111的粘性下降，去除所述临时载板110，接着，可以采用如撕裂、光照等处理方式，剥离所述离型层111；当然，也可以直接采用激光剥离工艺将激光剥离与重布线层100相互剥离，激光剥离工艺直接将离型层111气化，实现将所述临时载板110与所述重布线层100剥离的效果，其加工的精度高，且存留的杂质少。
在形成重布线层焊点101时，如图21所示，可以首先在重布线层100的下表面(远离所述TSV桥接基板200的一面)形成保护层112，保护层112可以采用氧化硅、氮化硅、氧氮化硅或其组合，接着，在保护层内可以采用激光钻孔工艺、曝光和显影工艺、光刻及刻蚀工艺或其组合形成窗113，之后，如图22所示，在保护层形成具有开口115的焊点掩模层114，开口115与窗113交叠，暴露出重布线层100内的第一金属图形层140，最后，如图23所示，在开口115及窗113内形成重布线层焊点101，重布线层焊点101的材料包括铜、铝、无铅合金(例如，金、锡、银、铝或铜的合金)或铅合金(例如、铅-锡合金)。重布线层焊点101可以是导电凸块、C4(controlled collapse chip connection，C4)凸块，焊料球等结构。
步骤S7)：如图24所示，提供一带有封装焊盘的封装基板500，并通过所述封装焊盘和所述重布线层焊点将所述重布线层100键合至所述封装基板500上。
本实施例中，可以采用超声波键合、热压键合或热超声键合等方式实现重布线层100与封装基板500的键合连接，键合后的结构即为所述三维封装结构10。
在一些实施例中，将重布线层100与封装基板500键合后，如图25所示，还需于所述重布线层100与所述封装基板500键合连接的缝隙内填充材料层700。需要说明的是，由于倒置，三维封装结构10内部各层间结构的上下位置关系也相应的改变，由此导致的关于位置关系的限定，会有前后文描述不统一的情况，应当被理解。
步骤S8)：如图26所示，于所述封装基板500的上方设置散热板600，其中，所述散热板600将若干个所述芯片400包覆于其内。
本实施例中，散热板600将芯片产生的热量传导散发。
相应的，本实施例还提供一种三维封装结构10，如图24所示，所述三维封装结构10包括：封装基板500、重布线层100、若干个TSV桥接基板200、若干个芯片400及塑封材料层300，其中，所述重布线层100位于所述封装基板500的上表面，其与所述封装基板500键合连接；所述若干个TSV桥接基板200位于所述重布线层100的上表面，其与所述重布线层100键合连接；所述若干个芯片400位于所述TSV桥接基板200的上表面，其与所述TSV桥接基板200键合连接；所述塑封材料层300形成于所述重布线层100的上表面，其包覆若干个所述TSV桥接基板200及若干个所述芯片400。
本实施例中，从下至上依次叠层设置了封装基板500、重布线层100、TSV桥接基板200、芯片400，每层之间以键合的方式连接；封装基板500的布线密度低于重布线层100的布线密度，重布线层100的布线密度低于TSV桥接基板200的布线密度，若干个异构的芯片400通过多个布线密度不同的TSV桥接基板200互相通讯，线路短，通讯质量优，能够增加良率，减少制作成本；TSV桥接基板200通过重布线层100与封装基板500电连接，重布线层100作为两者间的缓冲结构，代替了部分封装基板500的电连接功能，使得封装基板500无须制备更多的层数即可完成电信号传输，降低了多层封装基板的制备成本。
具体的，所述三维封装结构还包括填充材料层700及散热板600，如图25所示，填充材料层700形成于若干个所述TSV桥接基板200与所述重布线层100键合连接的缝隙内、若干个所述芯片400与若干个所述TSV桥接基板200键合连接的缝隙内、及所述重布线层100与所述封装基板500键合连接的缝隙内；如图26所示，散热板600设置在所述封装基板500的上表面。
本实施例中，填充材料层700的材料包括但不限于环氧树脂。填充材料层700可以保护重布线层100免受环境的影响、减小重布线层100与封装基板500间热膨胀不适配的影响，使得组件的可靠性可以得到极大的提高。散热板600为芯片400导热、散热。
综上所述，本发明的三维封装结构及其制备方法，采用若干个的较小的TSV桥接基板代替整片的TSV中介层基板实现不同芯片间的高密度互联，在不影响互联功能的基础上能够增加中介层基板的制作良率，减少成本；高连接密度的中介层基板先与中等连接密度的重布线层连接，再由重布线层与更低密度的封装基板连接，使得封装基板内部的互联层层数减少，规避了多层基板制作良率低的风险；新的工艺制作的重布线层，制作形成的重布线层平坦度良好，信号传递可靠性高。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技 术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (10)

  1. 一种三维封装结构的制备方法，其特征在于，所述制备方法包括：
    S1，提供一临时载板，于所述临时载板上表面形成重布线层；
    S2，提供若干个TSV桥接基板，将若干个所述TSV桥接基板与所述重布线层键合连接；
    S3，于所述重布线层的上表面形成第一塑封层，所述第一塑封层暴露出所述TSV桥接基板的焊点；
    S4，提供若干个芯片，将若干个所述芯片与若干个所述TSV桥接基板键合连接；
    S5，于所述第一塑封层的上表面形成第二塑封层；
    S6，去除所述临时载板，于所述重布线层远离所述TSV桥接基板的一表面形成重布线层焊点；
    S7，提供一带有封装焊盘的封装基板，并通过所述封装焊盘和所述重布线层焊点将所述重布线层键合至所述封装基板上。
  2. 根据权利要求1所述的三维封装结构的制备方法，其特征在于，S1中所述重布线层的制备方法包括：
    S11，于所述临时载板上表面形成具有第一开口图形的第一掩膜层；
    S12，基于所述第一开口图形形成第一金属图形层；
    S13，去除所述第一掩膜层，于所述第一金属图形层上形成具有第二开口图形的第二掩膜层，所述第二开口图形至少暴露出所述第一金属图形层的部分上表面；
    S14，基于所述第二开口图形形成第一金属柱层；
    S15，去除所述第二掩膜层，并于所述临时载板的上表面形成第一介质层，所述第一介质层包覆所述第一金属图形层及所述第一金属柱层；
    S16，研磨所述第一介质层直至暴露出所述第一金属柱层的上表面。
  3. 根据权利要求2所述的三维封装结构的制备方法，其特征在于，所述重布线层的制备方法还包括：S17，至少重复一次步骤S11～S16，制备得到多层所述重布线层。
  4. 根据权利要求2或3所述的三维封装结构的制备方法，其特征在于，在S11之前，所述重布线层的制备方法还包括：S10，于所述临时载板上表面形成金属种子层的步骤；此时，S15中去除所述第二掩膜层之后，形成所述第一介质层之前，还包括去除未被所述第一金属图形层覆盖的金属种子层的步骤。
  5. 根据权利要求1所述的三维封装结构的制备方法，其特征在于，S1中于所述临时载板上表面形成重布线层之前，还包括于所述临时载板上表面形成离型层的步骤；此时，S6中去除所述临时载板时，还包括去除所述离型层的步骤。
  6. 根据权利要求1所述的三维封装结构的制备方法，其特征在于，
    S2中将若干个所述TSV桥接基板与所述重布线层键合连接之后，还包括于若干个所述TSV桥接基板与所述重布线层键合连接的缝隙内填充入填充材料层的步骤；
    S4中将若干个所述芯片与若干个所述TSV桥接基板键合连接之后，还包括于若干个所述芯片与若干个所述TSV桥接基板键合连接的缝隙内填充入填充材料层的步骤；
    S7中将所述重布线层键合至所述封装基板上之后，还包括于所述重布线层与所述封装基板键合连接的缝隙内填充入填充材料层的步骤。
  7. 根据权利要求1所述的三维封装结构的制备方法，其特征在于，所述制备方法还包括：S8，于所述封装基板连接所述重布线层的一表面设置散热板的步骤，其中，所述散热板将若干个所述芯片包覆于其内。
  8. 一种三维封装结构，其特征在于，所述三维封装结构包括：
    封装基板、重布线层、若干个TSV桥接基板、若干个芯片及塑封材料层；其中，
    所述重布线层位于所述封装基板的上表面，其与所述封装基板键合连接；
    若干个所述TSV桥接基板位于所述重布线层的上表面，其与所述重布线层键合连接；
    若干个所述芯片位于若干个所述TSV桥接基板的上表面，其与若干个所述TSV桥接基板键合连接；
    所述塑封材料层形成于所述重布线层的上表面，其包覆若干个所述TSV桥接基板及若干个所述芯片。
  9. 根据权利要求8所述的三维封装结构，其特征在于，所述三维封装结构还包括散热板，其设置在所述封装基板的上表面，将若干个所述芯片包覆于其内。
  10. 根据权利要求8所述的三维封装结构，其特征在于，所述三维封装结构还包括填充材料层，形成于若干个所述TSV桥接基板与所述重布线层键合连接的缝隙内、若干个所述 芯片与若干个所述TSV桥接基板键合连接的缝隙内、及所述重布线层与所述封装基板键合连接的缝隙内。
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