WO2024042404A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2024042404A1
WO2024042404A1 PCT/IB2023/057887 IB2023057887W WO2024042404A1 WO 2024042404 A1 WO2024042404 A1 WO 2024042404A1 IB 2023057887 W IB2023057887 W IB 2023057887W WO 2024042404 A1 WO2024042404 A1 WO 2024042404A1
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Prior art keywords
insulating layer
layer
semiconductor device
semiconductor
transistor
Prior art date
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PCT/IB2023/057887
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English (en)
French (fr)
Japanese (ja)
Inventor
山崎舜平
國武寛司
松嵜隆徳
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to JP2024542436A priority Critical patent/JPWO2024042404A1/ja
Priority to CN202380060987.3A priority patent/CN119769190A/zh
Publication of WO2024042404A1 publication Critical patent/WO2024042404A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/20—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices

Definitions

  • One embodiment of the present invention relates to a semiconductor device.
  • one embodiment of the present invention is not limited to the above technical field.
  • the technical field of the invention disclosed in this specification and the like relates to products, methods, or manufacturing methods.
  • one aspect of the present invention relates to a process, machine, manufacture, or composition of matter.
  • examples of the technical field according to one embodiment of the present invention include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, storage devices, signal processing devices, processors, electronic devices, systems, and the like. Examples include driving methods, methods of manufacturing them, methods of testing them, and methods of using them.
  • Non-Patent Document 1 research and development of memories using ferroelectrics are actively being conducted.
  • Non-Patent Document 2 research on ferroelectric HfO 2 -based materials (Non-Patent Document 2), research on ferroelectricity of hafnium oxide thin films (Non-Patent Document 3), HfO 2 Research on ferroelectricity of thin films (Non-Patent Document 4), and demonstration of integration of FeRAM (Ferroelectric Random Access Memory) using ferroelectric material Hf 0.5 Zr 0.5 O 2 with CMOS (Non-Patent Document 5) ) and other studies related to hafnium oxide are also actively being conducted.
  • FeRAM Feroelectric Random Access Memory
  • An object of one embodiment of the present invention is to provide a novel semiconductor device. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device that occupies a small area. Alternatively, an object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device with a large storage capacity.
  • problems related to one embodiment of the present invention are not limited to the problems listed above.
  • the issues listed above do not preclude the existence of other issues.
  • Other issues are those that are not mentioned in this section and are described below.
  • Problems not mentioned in this section can be derived from the descriptions, drawings, etc. by those skilled in the art, and can be extracted as appropriate from these descriptions.
  • one embodiment of the present invention does not need to solve all of the problems listed above and other problems.
  • One embodiment of the present invention solves at least one of the problems listed above and other problems.
  • One embodiment of the present invention includes a capacitor and a transistor on the capacitor, and the capacitor includes a first conductive layer, a first insulating layer on the first conductive layer, and a transistor on the first insulating layer.
  • the transistor includes a second insulating layer on the second conductive layer, a third conductive layer on the second insulating layer, and an opening provided in the second insulating layer and the third conductive layer.
  • This is a semiconductor device that includes a dielectric.
  • Another embodiment of the present invention includes a plurality of stacked layers and a first electrode penetrating the plurality of layers, and each of the plurality of layers includes a capacitor and a transistor on the capacitor.
  • the capacitor has a first conductive layer, a first insulating layer on the first conductive layer, and a second conductive layer on the first insulating layer
  • the transistor has a first conductive layer on the second conductive layer.
  • a fourth conductive layer on the third insulating layer, the opening overlaps with the second conductive layer
  • the first insulating layer includes a ferroelectric material
  • the third conductive layer is electrically connected to the first electrode.
  • the angle between the side surface of the second insulating layer and the bottom surface of the second insulating layer in the opening is preferably 45 degrees or more and 90 degrees or less.
  • the semiconductor device has a memory retention period of 10 days or more at an environmental temperature of 150°C.
  • the second insulating layer may include a fourth insulating layer, a fifth insulating layer on the fourth insulating layer, and a sixth insulating layer on the fifth insulating layer.
  • each of the fourth insulating layer and the sixth insulating layer may include nitrogen and silicon.
  • the fifth insulating layer may include oxygen and silicon.
  • each of the fourth insulating layer and the sixth insulating layer may contain hydrogen.
  • an oxide semiconductor may be used as the semiconductor layer.
  • the semiconductor layer contains at least one of indium and zinc, and oxygen.
  • the first electrode may include a plurality of conductive layers.
  • the first insulating layer contains hafnium, zirconium, and oxygen.
  • the first conductive layer and the second conductive layer contain titanium and nitrogen.
  • a novel semiconductor device can be provided.
  • a semiconductor device that occupies a small area can be provided.
  • a highly reliable semiconductor device can be provided.
  • a semiconductor device with low power consumption can be provided.
  • a semiconductor device with a large storage capacity can be provided.
  • the effects of one embodiment of the present invention are not limited to the effects listed above.
  • the effects listed above do not preclude the existence of other effects. Therefore, one embodiment of the present invention may not have the effects listed above.
  • other effects are effects that are not mentioned in this item and are described below.
  • Other effects can be derived from descriptions such as the specification or drawings by those skilled in the art, and can be extracted as appropriate from these descriptions.
  • One embodiment of the present invention has at least one of the effects listed above and other effects.
  • FIG. 1A and FIG. 1B are diagrams illustrating a configuration example of a semiconductor device.
  • FIGS. 1C and 1D are equivalent circuit diagrams of the semiconductor device.
  • 2A to 2C are diagrams showing configuration examples of a semiconductor device.
  • 3A to 3E are diagrams showing configuration examples of semiconductor devices.
  • 4A and 4B are diagrams illustrating a configuration example of a semiconductor device.
  • 5A and 5B are diagrams illustrating a configuration example of a semiconductor device.
  • 6A to 6C are diagrams showing configuration examples of semiconductor devices.
  • 7A to 7C are diagrams showing configuration examples of semiconductor devices.
  • 8A to 8C are diagrams showing configuration examples of semiconductor devices.
  • 9A and 9B are diagrams illustrating a configuration example of a semiconductor device.
  • FIG. 9C is an equivalent circuit diagram of the semiconductor device.
  • FIG. 10 is a diagram showing a configuration example of a semiconductor device.
  • FIG. 11 is an equivalent circuit diagram of the semiconductor device.
  • FIG. 12 is a diagram showing a configuration example of a semiconductor device.
  • FIG. 13 is an equivalent circuit diagram of the semiconductor device.
  • FIG. 14A is a diagram illustrating an example of a circuit configuration of a memory cell.
  • FIG. 14B is a graph showing an example of hysteresis characteristics.
  • FIG. 14C is a timing chart showing an example of a method for driving a memory cell.
  • 15A to 15C are diagrams showing configuration examples of storage devices.
  • FIG. 16A is a diagram illustrating a configuration example of a storage device.
  • FIG. 16A is a diagram illustrating a configuration example of a storage device.
  • FIG. 16A is a diagram illustrating a configuration example of a storage device.
  • FIG. 16A is a diagram illustrating a
  • FIG. 16B is a schematic diagram of a memory string included in the storage device.
  • FIG. 17A is a diagram illustrating a configuration example of a storage device.
  • FIG. 17B is a schematic diagram of a memory string included in the storage device.
  • FIG. 18 is a diagram showing an example of a cross-sectional configuration of a storage device.
  • 19A and 19B are schematic diagrams of a semiconductor device according to one embodiment of the present invention.
  • 20A and 20B are perspective views showing an example of an electronic component.
  • 21A to 21J are diagrams illustrating an example of an electronic device.
  • 22A to 22E are diagrams illustrating an example of an electronic device.
  • 23A to 23C are diagrams illustrating an example of an electronic device.
  • FIG. 24 is a diagram showing an example of space equipment.
  • a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having the same circuit, and the like. It also refers to any device that can function by utilizing the characteristics of semiconductors. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component containing a chip in a package are examples of semiconductor devices. Furthermore, storage devices, display devices, light emitting devices, lighting devices, electronic devices, and the like are themselves semiconductor devices and may include semiconductor devices.
  • arrows indicating the X direction (direction along the X axis), Y direction (direction along the Y axis), and Z direction (direction along the Z axis) may be provided.
  • the "X direction” refers to the direction along the X axis, and there is no distinction between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction” and the "Z direction”.
  • the X direction, the Y direction, and the Z direction are directions that intersect with each other. More specifically, the X direction, the Y direction, and the Z direction are directions that are orthogonal to each other.
  • one of the X direction, the Y direction, or the Z direction may be referred to as a "first direction” or a “first direction.” Further, the other direction may be referred to as a “second direction” or “second direction”. Further, the remaining one may be referred to as a "third direction” or "third direction.”
  • ordinal numbers such as “first,” “second,” and “third” are added to avoid confusion of constituent elements. Therefore, the number of components is not limited. Further, the order of the constituent elements is not limited. For example, a component referred to as “first” in one embodiment such as this specification is a component referred to as “second” in other embodiments, claims, etc. It is possible. Furthermore, for example, a component referred to as “first” in one of the embodiments of this specification etc. may be omitted in other embodiments or claims.
  • electrode B does not need to be formed directly on insulating layer A, and there is no need to form another structure between insulating layer A and electrode B. Do not exclude things that contain elements.
  • electrode B overlapping insulating layer A is not limited to the state in which electrode B is formed on insulating layer A, but also the state in which electrode B is formed under insulating layer A, or A state in which the electrode B is formed on the right side (or left side) of the insulating layer A is not excluded.
  • the terms “adjacent” and “nearby” do not limit that components are in direct contact.
  • insulating layer A and electrode B do not need to be formed in direct contact with each other, and other components may be placed between insulating layer A and electrode B. Do not exclude what is included.
  • the term “conductive layer” or “conductive film” may be changed to the term “conductor.”
  • the term “conductor” may be changed to the term “conductive layer” or “conductive film.”
  • the term “insulating layer” or “insulating film” may be changed to the term “insulator.”
  • the term “insulator” may be changed to the term “insulating layer” or “insulating film.”
  • voltage refers to the potential difference between two points, and potential refers to the electrostatic energy (electrical potential energy) possessed by a unit charge in an electrostatic field at a certain point.
  • a potential difference between a potential at a certain point and a reference potential is simply called a potential or a voltage, and potential and voltage are often used synonymously. Therefore, in this specification and the like, unless explicitly stated, a potential may be read as a voltage, and a voltage may be read as a potential.
  • Electrode In this specification and the like, terms such as “electrode,” “wiring,” and “terminal” do not functionally limit these components.
  • an “electrode” may be used as part of a “wiring” and vice versa.
  • the term “electrode” or “wiring” includes cases where a plurality of “electrodes” or “wirings” are formed integrally.
  • a “terminal” may be used as part of a “wiring” or “electrode,” and vice versa.
  • the term “terminal” also includes cases where a plurality of "electrodes", “wirings", “terminals”, etc. are formed integrally.
  • an “electrode” can be a part of a “wiring” or a “terminal,” and, for example, a “terminal” can be a part of a “wiring” or a “electrode.”
  • terms such as “electrode,” “wiring,” and “terminal” may be replaced with terms such as "region” depending on the case.
  • terms such as “wiring,” “signal line,” and “power line” can be interchanged depending on the situation or situation. For example, it may be possible to change the term “wiring” to the term “signal line.” Furthermore, for example, it may be possible to change the term “wiring” to a term such as “power line”. The reverse is also true, and terms such as “signal line” and “power line” may sometimes be changed to the term “wiring”. Terms such as “power line” may be changed to terms such as “signal line”. Moreover, the reverse is also true, and a term such as “signal line” may be changed to a term such as “power line”. Further, depending on the case or the situation, the term “potential” applied to the wiring may be changed to a term such as “signal”. Moreover, the reverse is also true, and a term such as “signal” may be changed to the term “potential”.
  • a “capacitive element” refers to, for example, a circuit element having a capacitance value higher than 0F, a wiring region having a capacitance value higher than 0F, a parasitic capacitance, or It can be the gate capacitance of a transistor.
  • capacitor element can sometimes be replaced with the term “capacitance.”
  • capacitor may be translated into the terms “capacitive element,” “parasitic capacitance,” or “gate capacitance.”
  • a “capacitor” (including a “capacitor” having three or more terminals) has a configuration including an insulator and a pair of conductors sandwiching the insulator.
  • the term “pair of conductors” in “capacitance” can be paraphrased as “pair of electrodes,” “pair of conductive regions,” “pair of regions,” or “pair of terminals.” Further, the term “one of a pair of terminals” may also be referred to as “one terminal” or “first terminal.” Moreover, the term “the other of a pair of terminals” may be referred to as “the other terminal” or “the second terminal.” Note that the value of the capacitance can be, for example, 0.05 fF or more and 10 pF or less. Further, for example, it may be set to 1 pF or more and 10 ⁇ F or less.
  • source and drain may be interchanged, such as when using transistors of different polarity or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms “source” and “drain” can be used interchangeably.
  • gate refers to part or all of a gate electrode and a gate wiring.
  • the gate wiring refers to a wiring for electrically connecting the gate electrode of at least one transistor to another electrode or another wiring.
  • source refers to part or all of a source region, a source electrode, and a source wiring.
  • the source region refers to a region of the semiconductor layer where the resistivity is below a certain value.
  • a source electrode refers to a conductive layer including a portion connected to a source region.
  • the source wiring refers to a wiring for electrically connecting the source electrode of at least one transistor to another electrode or another wiring.
  • drain refers to part or all of a drain region, a drain electrode, and a drain wiring.
  • the drain region refers to a region of the semiconductor layer where the resistivity is below a certain value.
  • a drain electrode refers to a conductive layer including a portion connected to a drain region.
  • the drain wiring refers to a wiring for electrically connecting the drain electrode of at least one transistor to another electrode or another wiring.
  • the transistors shown in this specification and the like are enhancement type (normally-off type) field effect transistors.
  • the transistors described in this specification and the like are n-channel transistors, and unless otherwise specified, the threshold voltage (also referred to as "Vth") of the transistors is greater than 0V.
  • the transistor shown in this specification and the like is a p-channel transistor, and unless otherwise specified, the threshold voltage (also referred to as "Vth”) of the transistor is 0V or less.
  • the Vth of a plurality of transistors of the same conductivity type are all equal.
  • off-state current refers to the current (current) that flows between the source and drain when the transistor is in the off state (also referred to as the "non-conducting state” or “blocking state”).
  • drain current also referred to as “drain current” or “Id.”
  • an off state is defined as an n-channel transistor in which the potential difference between the gate and source (also referred to as “gate voltage” or “Vg”) with respect to the source is lower than the threshold voltage.
  • Vg gate voltage
  • the off-state current of an n-channel transistor may refer to the drain current when Vg is lower than Vth.
  • off-state current may refer to, for example, a current flowing between a source and a drain when a transistor is in an off state.
  • on-current refers to Id when a transistor is in an on-state (also referred to as a "conductive state").
  • the on-state refers to a state in which Vg is greater than or equal to Vth for an n-channel transistor, and a state in which Vg is less than or equal to Vth for a p-channel transistor.
  • the on-current of an n-channel transistor may refer to the drain current when Vg is equal to or higher than Vth.
  • parallel refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case where the temperature is greater than or equal to -5 degrees and less than or equal to 5 degrees is also included.
  • substantially parallel or “substantially parallel” refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less.
  • perpendicular refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, cases where the angle is greater than or equal to 85 degrees and less than or equal to 95 degrees are also included.
  • substantially perpendicular or “substantially perpendicular” refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.
  • the conductive layer 242 may be shown divided into a conductive layer 242a and a conductive layer 242b.
  • FIG. 1A is a top view of a semiconductor device 10A.
  • FIG. 1B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 1A, viewed from the Y direction. Note that in the top view of FIG. 1A, some elements are omitted for clarity.
  • FIGS. 1C and 1D show equivalent circuit diagrams of the semiconductor device 10A.
  • one of the source and drain of the transistor 100 is electrically connected to the wiring BL, and the other is electrically connected to one electrode of the capacitor 110.
  • a gate of the transistor 100 is electrically connected to the wiring WL.
  • the other electrode of the capacitive element 110 is electrically connected to the wiring PL.
  • the semiconductor device 10A functions as a memory circuit (also referred to as a "memory element” or "memory cell").
  • FIG. 1C is an equivalent circuit diagram when the capacitive element 110 includes a ferroelectric material
  • FIG. 1D is an equivalent circuit diagram when the capacitive element 110 does not include a ferroelectric material.
  • FIG. 2A is a cross-sectional view of the portion indicated by the dashed line A3-A4 in FIG. 1A, viewed from the X direction.
  • FIG. 2B is an enlarged cross-sectional view of the portion shown by the dashed line B1-B2 in FIG. 2A when viewed from the Z direction.
  • FIG. 2C is an enlarged cross-sectional view of the portion shown by the dashed line B3-B4 in FIG. 2A when viewed from the Z direction.
  • a semiconductor device 10A of one embodiment of the present invention includes an insulating layer 153, and a conductive layer 151 and a conductive layer 152 that are embedded in the insulating layer 153.
  • the conductive layer 151 and the conductive layer 152 can be formed at the same time using the same material and in the same manufacturing process. Further, it is preferable that the positions (positions in the Z direction) of the upper surfaces of the insulating layer 153, the conductive layer 151, and the conductive layer 152 match or substantially match using a chemical mechanical polishing (CMP) method or the like.
  • CMP chemical mechanical polishing
  • an insulating layer 154 is provided over the insulating layer 153, the conductive layer 151, and the conductive layer 152, and a conductive layer 155 is provided over the insulating layer 154.
  • the conductive layer 151 and the conductive layer 155 have a region where they overlap with each other with the insulating layer 154 in between.
  • the semiconductor device 10A has an insulating layer 157 on the insulating layer 154 and the conductive layer 155, an insulating layer 158 on the insulating layer 157, and an insulating layer 159 on the insulating layer 158.
  • the insulating layer 157, the insulating layer 158, and the insulating layer 159 may be collectively referred to as the insulating layer 156 or a spacer layer.
  • a conductive layer 161 is provided on the insulating layer 159.
  • openings 162 are provided in the conductive layer 161, the insulating layer 159, the insulating layer 158, and the insulating layer 157 in a region overlapping with a part of the conductive layer 155 (see FIG. 1B and FIG. 2A).
  • the semiconductor device 10A has a semiconductor layer 163 that covers the opening 162.
  • the semiconductor layer 163 has a region that overlaps with the bottom of the opening 162 and a region that overlaps with the side surface of the opening 162. That is, the semiconductor layer 163 has a region in contact with the insulating layer 156.
  • the semiconductor layer 163 has a region in contact with the side surface of the insulating layer 157, a region in contact with the side surface of the insulating layer 158, and a region in contact with the side surface of the insulating layer 159.
  • the semiconductor layer 163 has a region in contact with the conductive layer 155 and a region in contact with the conductive layer 161. That is, a portion of the semiconductor layer 163 is electrically connected to the conductive layer 155, and another portion of the semiconductor layer 163 is electrically connected to the conductive layer 161. Further, the semiconductor layer 163 may have a region extending beyond the edge of the conductive layer 161 (see FIGS. 1A and 2A).
  • an insulating layer 164 is provided over the insulating layer 159, the conductive layer 161, and the semiconductor layer 163. Further, a conductive layer 165 is provided on the insulating layer 164.
  • the conductive layer 165 has a region that overlaps with the opening 162, and in this region, a region that overlaps with the side surface and bottom of the opening 162 via the insulating layer 164 and the semiconductor layer 163 (see FIG. 1B, FIG. 2A, FIG. 2B, and FIG. (See 2C).
  • the thickness of the semiconductor layer 163 is preferably 1 nm or more, 3 nm or more, or 5 nm or more, and 20 nm or less, 15 nm or less, 12 nm or less, or 10 nm or less.
  • the thickness of the insulating layer 164 is preferably 0.5 nm or more and 15 nm or less, more preferably 0.5 nm or more and 12 nm or less, and even more preferably 0.5 nm or more and 10 nm or less.
  • the insulating layer 164 only needs to have a region with the thickness described above at least in part.
  • an insulating layer 166 is provided on the insulating layer 164. It is preferable that the positions (positions in the Z direction) of the upper surfaces of the conductive layer 165 and the insulating layer 166 match or substantially match. For example, by performing CMP processing or the like, the positions of the upper surfaces of the conductive layer 165 and the insulating layer 166 (positions in the Z direction) are made to match or substantially match, thereby improving the coverage of the insulating layer and the conductive layer that will be formed later. can be increased.
  • an insulating layer 167 is provided over the conductive layer 165 and the insulating layer 166. Further, in the region overlapping with the conductive layer 152, the conductive layer 167, the insulating layer 166, the insulating layer 164, the conductive layer 161, the insulating layer 159, the insulating layer 158, the insulating layer 157, and a part of the insulating layer 154 are embedded. It has a layer 168. Conductive layer 168 is electrically connected to conductive layer 161 and conductive layer 152. Conductive layer 168 and conductive layer 152 function as contact plugs.
  • the conductive layer 155 functions as one electrode of the capacitive element 110.
  • the conductive layer 151 functions as the other electrode of the capacitive element 110.
  • a region of the insulating layer 154 overlapping with the conductive layer 155 and the conductive layer 151 functions as a dielectric of the capacitive element 110.
  • Each of conductive layer 165 and conductive layer 151 extends in the Y direction.
  • the conductive layer 165 functions as the wiring WL or a part of the wiring WL
  • the conductive layer 151 functions as the wiring PL or a part of the wiring PL.
  • the conductive layer 168 and the conductive layer 152 function as the wiring BL or a part of the wiring BL.
  • a transistor 100 and a capacitor 110 are provided in an overlapping manner. By overlapping the transistor 100 and the capacitor 110, the area occupied by the semiconductor device 10A can be reduced.
  • the conductive layer 161 functions as either a source electrode or a drain electrode of the transistor 100. Further, the conductive layer 155 functions as the other of the source electrode and the drain electrode of the transistor 100. For example, if the conductive layer 161 functions as a drain electrode of the transistor 100, the conductive layer 155 functions as a source electrode of the transistor 100. Note that the conductive layer 161 can also be said to function as the wiring BL or a part of the wiring BL.
  • the semiconductor layer 163 functions as a semiconductor layer in which a channel of the transistor 100 is formed (a semiconductor layer including a channel formation region), the insulating layer 164 functions as a gate insulating layer, and the conductive layer 165 functions as a gate electrode. Therefore, it can be said that the transistor 100 is provided in a region including the opening 162.
  • the transistor 100 has a source electrode and a drain electrode arranged in the Z direction. That is, the source and drain of the transistor 100 are arranged at different heights. In other words, the source and drain of the transistor 100 are arranged at different positions in the Z direction.
  • Such a transistor is also referred to as a “vertical channel transistor,” “vertical channel transistor,” “vertical transistor,” or “VFET (Vertical Field Effect Transistor).”
  • a source electrode and a drain electrode are arranged in the Z direction. That is, the channel formation region, the source region, and the drain region are arranged in the Z direction.
  • the vertical transistor can reduce the area occupied by the transistor 100 compared to a conventional transistor in which a channel formation region, a source region, and a drain region are provided separately on the XY plane.
  • the area occupied by the semiconductor device can be reduced.
  • high integration of the semiconductor device can be achieved.
  • the storage capacity per unit area of a storage device using the semiconductor device can be increased.
  • the channel length is set by the exposure limit of photolithography.
  • the channel length can be set by the thickness of the insulating layer 156 or the insulating layer 158. Therefore, the channel length of the transistor 100 is set to a very fine structure below the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, but 1 nm or more, or 5 nm or more).
  • the on-state current of the transistor 100 increases, and frequency characteristics can be improved.
  • a vertical channel transistor a semiconductor device with high operating speed can be provided.
  • ⁇ Capacitive element 110> A region where the conductive layer 151 and the conductive layer 155 overlap each other with the insulating layer 154 in between functions as the capacitive element 110. It is preferable to use a ferroelectric material for the insulating layer 154. Ferroelectric materials have the property that polarization occurs internally when an electric field is applied from the outside, and the polarization remains even when the electric field is reduced to zero. Therefore, a nonvolatile memory element can be realized using a capacitive element (also referred to as a "ferroelectric capacitor”) using this material as a dielectric.
  • a capacitive element also referred to as a "ferroelectric capacitor
  • the capacitive element 110 functions as a ferroelectric capacitor
  • a material that easily causes polarization in the insulating layer 154 as the conductive layer 151 and the conductive layer 155 in contact with the insulating layer 154 which is a ferroelectric material.
  • titanium nitride as the conductive layer 151 and the conductive layer 155.
  • a nonvolatile memory element using a ferroelectric capacitor is sometimes called a "FeRAM” or a “ferroelectric memory.” Materials that can have ferroelectricity will be explained in detail later.
  • a material with a high dielectric constant (also referred to as a "high-k material”) may be used for the insulating layer 154.
  • a high-k material As the insulating layer 154, the capacitance necessary for the capacitive element 110 can be ensured, and the insulating layer 154 can be made thick.
  • the dielectric strength voltage between the conductive layer 151 and the conductive layer 155 is increased, and electrostatic breakdown is suppressed. Therefore, the reliability of the capacitive element 110 is improved. Therefore, the reliability of the semiconductor device using the capacitor 110 is improved.
  • the material used for the substrate there are no major restrictions on the material used for the substrate.
  • the material may be determined by taking into account the presence or absence of translucency and heat resistance to withstand heat treatment.
  • an insulating substrate, a semiconductor substrate, or a conductive substrate may be used.
  • a glass substrate such as barium borosilicate glass or aluminoborosilicate glass
  • a ceramic substrate such as barium borosilicate glass or aluminoborosilicate glass
  • a ceramic substrate such as barium borosilicate glass or aluminoborosilicate glass
  • a ceramic substrate such as barium borosilicate glass or aluminoborosilicate glass
  • a ceramic substrate such as barium borosilicate glass or aluminoborosilicate glass
  • a ceramic substrate such as barium borosilicate glass or aluminoborosilicate glass
  • a ceramic substrate such as barium borosilicate glass or alumino
  • the semiconductor substrate examples include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. . Furthermore, there is a semiconductor substrate having an insulator region inside the semiconductor substrate described above, such as an SOI (Silicon On Insulator) substrate. Furthermore, the semiconductor substrate may be a single crystal semiconductor or a polycrystalline semiconductor.
  • the conductive substrate examples include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate.
  • substrates containing metal nitrides examples include substrates containing metal oxides, and the like.
  • substrates in which an insulator substrate is provided with a conductor or a semiconductor a semiconductor substrate in which a conductor or an insulator is provided, and a conductor substrate in which a semiconductor or an insulator is provided.
  • polyester resins such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile resins, acrylic resins, polyimide resins, polymethyl methacrylate resins, and polycarbonate (PC).
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • PC polycarbonate
  • ) resin polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin , polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc.
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • PES polyethersulfone
  • PEN polyamide resin
  • polystyrene resin polyamide
  • a lightweight semiconductor device including the transistor 100 can be provided. Furthermore, by using the above material as a substrate, a semiconductor device that is resistant to impact can be provided. Further, by using the above material as a substrate, a semiconductor device that is less likely to be damaged can be provided.
  • these substrates provided with elements may be used.
  • Elements provided on the substrate include capacitive elements, resistive elements, switch elements, light emitting elements, and memory elements.
  • an insulating oxide, nitride, oxynitride, nitride oxide, metal oxide, metal oxynitride, metal nitride oxide, or the like can be used.
  • An insulating material selected from lanthanum, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, etc. is used in a single layer or in a stacked manner.
  • a mixture of a plurality of materials among oxide materials, nitride materials, oxynitride materials, and nitrided oxide materials may be used.
  • nitrided oxide refers to a material containing more nitrogen than oxygen.
  • oxynitride refers to a material containing more oxygen than nitrogen. Note that the content of each element can be measured using, for example, Rutherford Backscattering Spectrometry (RBS).
  • RBS Rutherford Backscattering Spectrometry
  • gate insulating layers become thinner, which may cause problems such as leakage current.
  • a high-k material high dielectric constant material, material with high relative permittivity
  • the insulating layer a material having a high dielectric constant such as lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), (Ba,Sr)TiO 3 (BST) may be used in some cases.
  • PZT lead zirconate titanate
  • SBa,Sr)TiO 3 BST
  • the material should be selected depending on the function required of the insulating layer.
  • Materials with high dielectric constants include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, and oxides containing silicon and hafnium. These include oxynitrides or nitrides with silicon and hafnium.
  • materials with low dielectric constants include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, and vacancies.
  • silicon oxides and resins that have
  • the method for forming the insulating material is not particularly limited, and various methods such as vapor deposition, ALD, CVD, sputtering, and spin coating can be used.
  • the insulating layer 153 and the insulating layer 167 are preferably formed using an insulating material through which impurities hardly pass.
  • insulating materials containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorous, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum, in a single layer or It may be used in a laminated manner.
  • Examples of insulating materials that are difficult for impurities to pass through include aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, Examples include silicon nitride.
  • an insulating layer that can function as a planarization layer may be used as the insulating layer.
  • materials that function as the flattening layer include acrylic resin, polyimide, epoxy resin, polyamide, polyimide amide, siloxane resin, benzocyclobutene resin, phenol resin, and precursors thereof.
  • low-k materials low dielectric constant materials, materials with small dielectric constants
  • siloxane resins PSG (phosphorus glass), BPSG (phosphorus boron glass), etc.
  • a plurality of insulating layers formed of these materials may be stacked.
  • the siloxane resin corresponds to a resin containing Si-O-Si bonds formed using a siloxane-based material as a starting material.
  • an organic group for example, an alkyl group or an aryl group
  • a fluoro group may be used as a substituent. Further, the organic group may have a fluoro group.
  • insulating layer 154 that functions as a dielectric of the capacitive element 110
  • three insulating layers also referred to as "ZAZ" in which aluminum oxide is sandwiched between two layers of zirconium oxide may be used.
  • ZAZ is a material with a high dielectric constant, and by using ZAZ as the dielectric of the capacitive element 110, the area occupied by the capacitive element 110 can be reduced.
  • the capacitive element 110 functions as a ferroelectric capacitor.
  • hafnium oxide as the material that can have ferroelectricity.
  • a metal oxide such as zirconium oxide or HfZrOx ( X is a real number larger than 0; hereinafter also referred to as "HfZrOx" may be used as a material that can have ferroelectricity.
  • hafnium oxide can be combined with element J1 (here, element J1 is zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), A material to which one or more selected from lanthanum (La), strontium (Sr), etc. is added may be used.
  • the ratio of the number of atoms of hafnium atoms and element J1 can be set as appropriate.
  • the number of hafnium atoms and zirconium atoms may be set to 1:1 or around 1:1.
  • materials that can have ferroelectricity include zirconium oxide and element J2 (here, element J2 is hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y)). , lanthanum (La), strontium (Sr), etc.) can be used.
  • the ratio of the number of atoms of zirconium atoms and element J2 can be set as appropriate, for example, the number of atoms of zirconium atoms and element J2 may be set to 1:1 or around 1:1.
  • materials that can have ferroelectricity lead titanate (PbTiO x ), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuthate tantalate (SBT), Piezoelectric ceramics having a perovskite structure, such as bismuth ferrite (BFO) and barium titanate, may also be used.
  • materials that can have ferroelectricity include aluminum scandium nitride (Al 1-a Sc a N b (a is a real number greater than 0 and less than 0.5, and b is a value of 1 or a value near it). (hereinafter simply referred to as AlScN)), Al-Ga-Sc nitride, Ga-Sc nitride, etc. can be used.
  • AlScN aluminum scandium nitride
  • Al-Ga-Sc nitride Al-Ga-Sc nitride
  • Ga-Sc nitride etc.
  • a metal nitride containing element M1, element M2, and nitrogen can be used as a material that can have ferroelectricity.
  • the element M1 is one or more selected from aluminum (Al), gallium (Ga), indium (In), and the like.
  • Element M2 is boron (B), scandium (Sc), yttrium (Y), lanthanoids (lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium ( Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu)), Actinides (15 elements from actinium (Ac) to lawrenium (Lr)), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium ( Cr), etc.
  • Actinides (15 elements from actinium (Ac) to lawrenium (Lr)), titanium (Ti
  • the ratio between the number of atoms of element M1 and the number of atoms of element M2 can be set as appropriate.
  • a metal oxide containing element M1 and nitrogen may have ferroelectricity even if it does not contain element M2.
  • a material that can have ferroelectricity a material obtained by adding element M3 to the metal nitride described above can be used.
  • the element M3 is one or more selected from magnesium (Mg), calcium (Ca), strontium (Sr), zinc (Zn), cadmium (Cd), and the like.
  • the ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be set as appropriate.
  • the metal nitride contains at least a group 13 element and nitrogen, which is a group 15 element
  • the metal nitride can be used as a group 13-15 ferroelectric material or a group 13 nitride ferroelectric material. Sometimes called dielectric.
  • perovskite oxynitrides such as SrTaO 2 N and BaTaO 2 N, GaFeO 3 having a ⁇ alumina structure, and the like can be used.
  • the material that can have ferroelectricity for example, a mixture or compound consisting of a plurality of materials selected from the materials listed above can be used.
  • the material capable of having ferroelectricity may have a laminated structure made of a plurality of materials selected from the materials listed above.
  • materials that exhibit ferroelectricity are referred to as In addition to being called a material, it is also called a material that can have ferroelectric properties or a material that has ferroelectric properties.
  • hafnium oxide or a material containing hafnium oxide and zirconium oxide can have ferroelectricity even when processed into a thin film of several nm. Therefore, it is suitable.
  • the thickness of the insulating layer 154 is preferably 100 nm or less, more preferably 50 nm or less, even more preferably 20 nm or less, and even more preferably 10 nm or less (typically 2 nm or more and 9 nm or less).
  • the thickness of the insulating layer 154 is preferably 8 nm or more and 12 nm or less.
  • AlScN aluminum scandium nitride
  • AlScN aluminum scandium nitride
  • AlScN aluminum scandium nitride
  • the film thickness of the material that can have ferroelectricity can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and still more preferably 10 nm or less (typically 2 nm or more and 9 nm or less). .
  • the film thickness is preferably 8 nm or more and 12 nm or less.
  • a material that can have ferroelectricity is sometimes referred to as a ferroelectric material.
  • a layered material that can have ferroelectric properties is sometimes referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film.
  • a device having such a ferroelectric layer, metal oxide film, or metal nitride film may be referred to as a ferroelectric device in this specification and the like.
  • HfZrOx when used as a material that can have ferroelectricity, it is preferable to form a film using an ALD method, particularly a thermal ALD method. Further, when forming a film of a material that can have ferroelectricity using a thermal ALD method, it is preferable to use a material that does not contain hydrocarbon (also referred to as HC) as a precursor. When a material that can have ferroelectric properties contains one or both of hydrogen and carbon, crystallization of the material that can have ferroelectric properties may be inhibited. Therefore, as described above, it is preferable to reduce the concentration of one or both of hydrogen and carbon in a material that can have ferroelectric properties by using a precursor that does not contain hydrocarbons.
  • examples of precursors that do not contain hydrocarbons include chlorine-based materials.
  • HfZrOx hafnium oxide and zirconium oxide
  • HfCl 4 and/or ZrCl 4 may be used as the precursor.
  • a dopant typically silicon, carbon, etc.
  • a forming method using a material containing a hydrocarbon as a precursor may be used as one means for adding carbon as a dopant.
  • the impurity concentration of the material that can have ferroelectricity is low.
  • lower concentrations of hydrogen (H) and carbon (C) are more preferable.
  • the hydrogen concentration of the material that can have ferroelectricity is preferably 5 ⁇ 10 20 atoms/cm 3 or less, more preferably 1 ⁇ 10 20 atoms/cm 3 or less.
  • the carbon concentration of the material that can have ferroelectricity is preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less.
  • HfZrOx is used as a material that can have ferroelectricity
  • H 2 O or O 3 can be used as the oxidizing agent.
  • the oxidizing agent for ALD is not limited to this.
  • the oxidizing agent in the ALD method may include one or more selected from O 2 , O 3 , N 2 O, NO 2 , H 2 O, and H 2 O 2 .
  • a material that can have ferroelectricity it is preferable to have a rectangular crystal structure because it exhibits ferroelectricity.
  • other crystal structures may be included.
  • it may have one or more crystal structures selected from cubic, tetragonal, and monoclinic.
  • a layer for increasing crystallinity may be formed before forming the material that can have ferroelectricity.
  • a metal oxide such as hafnium oxide or zirconium oxide, or hafnium or zirconium can be used as the layer that increases crystallinity.
  • AlScN is used as a material that can have ferroelectricity
  • other crystal structures may be included in addition to the hexagonal crystal structure.
  • a metal nitride such as aluminum nitride or scandium nitride, or aluminum or scandium.
  • the layer for increasing crystallinity may be formed after forming the material that can have ferroelectricity.
  • the material that can have ferroelectricity may have a composite structure having an amorphous structure and a crystalline structure.
  • Conductive materials used for conductive layers such as various wirings and electrodes that make up semiconductor devices include aluminum (Al), chromium (Cr), copper (Cu), silver (Ag), gold (Au), platinum (Pt), Tantalum (Ta), nickel (Ni), titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), vanadium (V), niobium (Nb), manganese (Mn), magnesium (Mg), A metal element selected from zirconium (Zr), beryllium (Be), etc., an alloy containing the above-mentioned metal elements, an alloy containing a combination of the above-mentioned metal elements, etc. can be used.
  • tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are difficult to oxidize.
  • a conductive material or a material that maintains conductivity even if it absorbs oxygen.
  • a semiconductor having high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • the method for forming the conductive material is not particularly limited, and various methods such as vapor deposition, atomic layer deposition (ALD), CVD, sputtering, and spin coating can be used.
  • a Cu-X alloy (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be applied as the conductive material. Since the layer formed of the Cu-X alloy can be processed by a wet etching process, it is possible to suppress manufacturing costs.
  • an aluminum alloy containing one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used as the conductive material.
  • conductive materials that can be used for the conductive layer indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin containing titanium oxide, etc.
  • Conductive materials with oxygen can also be used, such as oxides, indium zinc oxide, indium tin oxide doped with silicon oxide.
  • conductive materials containing nitrogen such as titanium nitride, tantalum nitride, and tungsten nitride can also be used.
  • the conductive layer can also have a laminated structure in which a conductive material containing oxygen, a conductive material containing nitrogen, and a material containing the metal element described above are appropriately combined.
  • the conductive layer may have a single-layer structure of an aluminum layer containing silicon, a two-layer structure in which a titanium layer is stacked on an aluminum layer, a two-layer structure in which a titanium layer is stacked on a titanium nitride layer, or a tungsten layer on a titanium nitride layer.
  • a two-layer structure in which a tungsten layer is laminated on a tantalum nitride layer a two-layer structure in which a tungsten layer is laminated on a tantalum nitride layer, and a three-layer structure in which a titanium layer is laminated, an aluminum layer is laminated on the titanium layer, and a titanium layer is laminated on top of that. good.
  • a plurality of conductive layers formed of the above-mentioned conductive materials may be laminated and used.
  • the conductive layer may have a laminated structure in which a material containing the aforementioned metal element and a conductive material containing oxygen are combined.
  • a laminated structure may be used in which a material containing the aforementioned metal element and a conductive material containing nitrogen are combined.
  • a layered structure may be used in which a material containing the metal element described above, a conductive material containing oxygen, and a conductive material containing nitrogen are combined.
  • a conductive layer is formed by laminating a conductive layer containing copper on a conductive layer containing at least one of indium or zinc and oxygen, and further laminating a conductive layer containing at least one of indium or zinc and oxygen on top of the conductive layer containing at least one of indium or zinc and oxygen. It may also have a three-layer structure. In this case, it is preferable that the side surfaces of the conductive layer containing copper are also covered with a conductive layer containing at least one of indium or zinc and oxygen. Further, for example, a plurality of conductive layers containing at least one of indium or zinc and oxygen may be stacked and used as the conductive layer.
  • the capacitive element 110 functions as a ferroelectric capacitor
  • a material that easily causes polarization in the insulating layer 154 as the conductive layer 151 and the conductive layer 155 in contact with the insulating layer 154 which is a ferroelectric material.
  • titanium nitride as the conductive layer 151 and the conductive layer 155.
  • semiconductor layer 163 As the semiconductor layer 163, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination.
  • semiconductor material silicon, germanium, etc. can be used, for example.
  • a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, or a nitride semiconductor may be used.
  • an organic substance having semiconductor properties or a metal oxide having semiconductor properties also referred to as an oxide semiconductor
  • these semiconductor materials may contain impurities as dopants.
  • the semiconductor layer 163 may be made of single crystal silicon, polycrystalline silicon, microcrystalline silicon, or amorphous silicon.
  • polycrystalline silicon for example, low temperature polysilicon (LTPS) may be used.
  • a transistor using amorphous silicon for the semiconductor layer 163 can be formed over a large glass substrate and can be manufactured at low cost.
  • a transistor using polycrystalline silicon for the semiconductor layer 163 has high field effect mobility and can operate at high speed.
  • a transistor using microcrystalline silicon for the semiconductor layer 163 has higher field effect mobility than a transistor using amorphous silicon, and can operate at high speed.
  • the semiconductor layer 163 may include a layered material that functions as a semiconductor.
  • a layered material is a general term for a group of materials having a layered crystal structure.
  • a layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are laminated via bonds that are weaker than covalent bonds or ionic bonds, such as van der Waals forces.
  • a layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity for the channel formation region, a transistor with high on-state current can be provided.
  • Examples of the layered material include graphene, silicene, and chalcogenide.
  • a chalcogenide is a compound containing chalcogen (an element belonging to Group 16).
  • examples of chalcogenides include transition metal chalcogenides, group 13 chalcogenides, and the like.
  • transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS 2 ), molybdenum selenide (typically MoSe 2 ), and molybdenum tellurium (typically MoTe 2 ) .
  • tungsten sulfide typically WS 2
  • tungsten selenide typically WSe 2
  • tungsten tellurium typically WTe 2
  • hafnium sulfide typically HfS 2
  • hafnium selenide typically HfSe 2
  • zirconium sulfide typically ZrS 2
  • zirconium selenide typically ZrSe 2
  • an oxide semiconductor has a band gap of 2 eV or more
  • a transistor (also referred to as an "OS transistor") using an oxide semiconductor, which is a type of metal oxide, for the semiconductor layer in which a channel is formed has an off-state current of are significantly less. Therefore, power consumption of a semiconductor device including an OS transistor can be reduced.
  • the OS transistor operates stably even in a high-temperature environment, with little variation in characteristics. For example, the off-state current hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even under an environmental temperature of room temperature or higher and 200° C. or lower. Furthermore, the on-state current is less likely to decrease even in a high-temperature environment. Therefore, a semiconductor device including an OS transistor operates stably even in a high-temperature environment and has high reliability.
  • the refresh operation frequency needs to be approximately 1 time/60 msec, but in the storage device of one embodiment of the present invention, the refresh operation frequency is approximately 1 time/10 sec, and 10 msec.
  • the refresh operation frequency can be set to be twice or more or 100 times or more. Note that with the storage device of one embodiment of the present invention, the refresh operation can be performed once every 1 sec or more and 100 sec or less, preferably once every 5 sec or more and 50 sec or less.
  • an OS transistor as the transistor 100. Since the OS transistor has a high dielectric strength voltage between the source and the drain, the channel length can be shortened. Therefore, the on-state current can be increased.
  • the OS transistor is suitable for a vertical channel type transistor.
  • the metal oxide contains at least indium (In) or zinc (Zn).
  • the metal oxide has two or three selected from indium, element M, and zinc.
  • the element M is a metal element or a metalloid element that has a high bonding energy with oxygen, for example, a metal element or a metalloid element that has a higher bonding energy with oxygen than indium.
  • the element M includes aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, and calcium. , strontium, barium, boron, silicon, germanium, and antimony.
  • the element M included in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and further gallium. preferable. Note that in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may include semimetal elements.
  • indium zinc oxide In-Zn oxide
  • indium tin oxide In-Sn oxide
  • indium titanium oxide In-Ti oxide
  • indium gallium oxide In-Ga oxide
  • Indium gallium aluminum oxide Indium gallium aluminum oxide
  • indium gallium tin oxide In-Ga-Sn oxide
  • gallium zinc oxide Ga-Zn oxide, also referred to as "GZO”
  • aluminum Zinc oxide Al-Zn oxide, also written as "AZO”
  • indium aluminum zinc oxide In-Al-Zn oxide, also written as "IAZO”
  • indium tin zinc oxide In-Sn- Zn oxide
  • indium titanium zinc oxide In-Ti-Zn oxide
  • indium gallium tin zinc oxide In-Ga-Sn-Zn oxide, also written as "IGZTO”
  • indium gallium aluminum zinc oxide In-Ga-
  • the field effect mobility of the transistor can be increased.
  • the metal oxide may include one or more metal elements having a large number of periods instead of indium.
  • the metal oxide may contain one or more metal elements having a large number of periods in addition to indium. The greater the overlap between the orbits of the metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including a metal element with a large number of periods, the field effect mobility of the transistor may be increased. Examples of metal elements having a large number of periods include metal elements belonging to the fifth period and metal elements belonging to the sixth period.
  • the metal element examples include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.
  • the metal oxide may contain one or more types of nonmetallic elements.
  • the metal oxide contains a nonmetal element, the field effect mobility of the transistor can be increased in some cases.
  • nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.
  • the metal oxide becomes highly crystalline, and impurities in the metal oxide can be reduced. It can suppress the spread. Therefore, fluctuations in the electrical characteristics of the transistor are suppressed, and reliability can be improved.
  • the electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide applied to the semiconductor layer. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be realized.
  • a metal oxide in which the atomic ratio of indium is greater than or equal to the atomic ratio of zinc may be used.
  • a metal oxide in which the atomic ratio of indium is greater than or equal to the atomic ratio of tin may be used.
  • a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of tin may be used. Furthermore, it is preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of tin.
  • a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of aluminum may be used. Furthermore, it is preferable to use a metal oxide in which the atomic ratio of zinc is higher than that of aluminum.
  • the atomic ratio of indium to the sum of the number of atoms of metal elements contained in the In-Ga-Zn oxide is higher than the atomic ratio of gallium.
  • Metal oxides may also be used.
  • the atomic ratio of indium to the sum of the number of atoms of metal elements contained in the In-M-Zn oxide is higher than the atomic ratio of element M.
  • High metal oxides may also be used.
  • the nearby composition includes a range of ⁇ 30% of the desired atomic ratio.
  • the element M it is preferable to use gallium.
  • the sum of the atomic ratios of the metal elements can be the atomic ratio of the element M.
  • the atomic ratio of the element M can be the sum of the atomic ratio of gallium and the atomic ratio of aluminum.
  • the atomic ratio of indium, element M, and zinc is within the above range.
  • the ratio of the number of atoms of indium to the sum of the number of atoms of metal elements is 30 atom % or more and 100 atom % or less, preferably 30 atom % or more and 95 atom % or less, more preferably is from 35 atom % to 95 atom %, more preferably from 35 atom % to 90 atom %, more preferably from 40 atom % to 90 atom %, more preferably from 45 atom % to 90 atom %, more preferably from 50 atom % to 90 atom %.
  • the ratio of the number of indium atoms to the total number of atoms of indium, element M, and zinc is within the above range.
  • the field effect mobility of the transistor can be increased by increasing the ratio of the number of indium atoms to the sum of the number of atoms of the metal elements.
  • a circuit that can operate at high speed can be manufactured. Furthermore, it becomes possible to reduce the area occupied by the circuit.
  • the analysis of the composition of the composition of metal oxides for example, the energy distributed X -ray optical method (EDX: ENERGY DISPERSIVE X -RAY SPECTROSCOPY), X -ray optical electron division of light (XPS: X -Ray PhotoElECTRON SPECTROSCOP). Y), guidance bond plasma mass analysis method (ICP-MS: Inductively Coupled Plasma-Mass Spectrometry), or Inductively Coupled Plasma-Atomic Emis (ICP-AES) sion Spectrometry) can be used. Alternatively, analysis may be performed by combining two or more of these methods. Note that for elements with low content rates, the actual content rate and the content rate obtained by analysis may differ due to the influence of analysis accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.
  • a sputtering method or an atomic layer deposition (ALD) method can be suitably used to form the metal oxide.
  • the atomic ratio of the target and the atomic ratio of the metal oxide may be different.
  • the atomic ratio of the metal oxide may be smaller than the atomic ratio of the target.
  • the atomic ratio of zinc contained in the target may be about 40% or more and 90% or less.
  • the above atomic ratio is not limited to the atomic ratio of the formed metal oxide, but also the atomic ratio of the sputtering target used for forming the metal oxide film. It may be.
  • GBT Gate Bias Temperature
  • PBTS Positive Bias Temperature Stress
  • NBTS Negative Bias Temperature Stress
  • PBTS test and NBTS test performed under light irradiation are respectively PBTIS (Positive Bias Temperature Illumination Stress) test and NBTIS (Negative Bias Temperature I) test. Illumination Stress) test.
  • n-type transistors In n-type transistors, a positive potential is applied to the gate when the transistor is turned on, so the amount of variation in threshold voltage in the PBTS test is an important indicator of transistor reliability. This is one of the items.
  • a transistor with high reliability against application of a positive bias can be obtained.
  • a transistor with a small threshold voltage variation in the PBTS test can be obtained.
  • the gallium content is lower than the indium content.
  • One of the factors that causes the threshold voltage to fluctuate in the PBTS test is the defect level at or near the interface between the semiconductor layer and the gate insulating layer.
  • gallium contained in metal oxides has a property of attracting oxygen more easily than other metal elements (for example, indium or zinc). Therefore, it is presumed that at the interface between the metal oxide containing a large amount of gallium and the gate insulating layer, gallium combines with excess oxygen in the gate insulating layer, making it easier to generate carrier (electron in this case) trap sites. . Therefore, when a positive potential is applied to the gate, carriers are trapped at the interface between the semiconductor layer and the gate insulating layer, which may cause the threshold voltage to fluctuate.
  • a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of gallium can be applied to the semiconductor layer.
  • a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of gallium it is preferable to apply a metal oxide in which the atomic ratio of metal elements satisfies In>Ga and Zn>Ga to the semiconductor layer.
  • the ratio of the number of gallium atoms to the number of atoms of the metal element contained is greater than 0 atom % and less than 50 atom %, preferably from 0.1 atom % to 40 atom %, more preferably 0.1 atomic % or more and 35 atomic % or less, more preferably 0.1 atomic % or more and 30 atomic % or less, more preferably 0.1 atomic % or more and 25 atomic % or less, more preferably 0.1 atomic % or more and 20 atomic % or less % or less, more preferably 0.1 atomic % or more and 15 atomic % or less, more preferably 0.1 atomic % or more and 10 atomic % or less.
  • V O oxygen vacancy
  • a metal oxide that does not contain gallium may be applied to the semiconductor layer of the OS transistor.
  • In--Zn oxide can be applied to the semiconductor layer.
  • the field effect mobility of the transistor can be increased by increasing the ratio of the number of atoms of indium to the number of atoms of the metal element contained in the metal oxide.
  • the metal oxide becomes highly crystalline, which suppresses fluctuations in the electrical characteristics of the transistor and increases reliability. be able to.
  • a metal oxide that does not contain gallium and zinc, such as indium oxide may be applied to the semiconductor layer. By using a metal oxide that does not contain gallium, it is possible to make threshold voltage fluctuations extremely small, especially in PBTS tests.
  • an oxide containing indium and zinc can be used for the semiconductor layer.
  • the present invention can also be applied to a case where element M is used instead of gallium. It is preferable to use a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of element M to the semiconductor layer. Further, it is preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of element M.
  • the semiconductor layer may have a stacked structure having two or more metal oxide layers.
  • the two or more metal oxide layers included in the semiconductor layer may have the same or approximately the same composition.
  • the same sputtering target can be used to form the layers, thereby reducing manufacturing costs.
  • the two or more metal oxide layers included in the semiconductor layer may have different compositions.
  • a first metal oxide layer having a composition of In:M:Zn 1:3:4 [atomic ratio] or a composition close to that, and In:M:Zn provided on the first metal oxide layer.
  • a laminated structure with a second metal oxide layer having an atomic ratio of 1:1:1 or a composition close to this can be suitably used.
  • gallium or aluminum as the element M.
  • a first metal oxide layer having a composition of In:M:Zn 1:1:1 [atomic ratio] or a composition close to that, and an In:Zn layer provided on the first metal oxide layer.
  • a metal oxide layer having crystallinity As the semiconductor layer, a metal oxide layer having crystallinity can be used.
  • a metal oxide layer having a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, a microcrystalline (NC: nano-crystal) structure, etc. can be used.
  • a crystalline metal oxide layer As a semiconductor layer, the density of defect levels in the semiconductor layer can be reduced, and a highly reliable display device can be realized.
  • the semiconductor layer of the OS transistor may have a stacked structure of two or more metal oxide layers having different crystallinity.
  • the layered structure includes a first metal oxide layer and a second metal oxide layer provided on the first metal oxide layer, and the second metal oxide layer
  • the structure can include a region having higher crystallinity than the oxide layer.
  • the second metal oxide layer may have a region having lower crystallinity than the first metal oxide layer.
  • the two or more metal oxide layers included in the semiconductor layer may have the same or approximately the same composition.
  • a stacked structure of two or more metal oxide layers having different crystallinity can be formed.
  • the two or more metal oxide layers included in the semiconductor layer may have different compositions.
  • a material containing hydrogen is preferably used for the insulating layer 157 and the insulating layer 159.
  • the oxide semiconductor in the region in contact with the insulating layer is made n-type and can function as a source region or a drain region.
  • a material containing silicon, nitrogen, and hydrogen may be used as the insulating layer.
  • silicon nitride containing hydrogen, silicon nitride oxide containing hydrogen, or the like may be used.
  • the thickness of the insulating layer 157 and the insulating layer 159 is preferably 1 nm or more and 15 nm or less, more preferably 2 nm or more and 10 nm or less, more preferably 3 nm or more and 7 nm or less, and further preferably 3 nm or more and 5 nm or less.
  • an oxide semiconductor is used for the semiconductor layer 163
  • a region of the semiconductor layer 163 in contact with the insulating layer 157 containing hydrogen and a region in contact with the insulating layer 159 containing hydrogen function as a source region or a drain region.
  • the thickness of the insulating layer 158 is preferably 1 nm or more and 50 nm or less, more preferably 2 nm or more and 30 nm or less, and even more preferably 3 nm or more and 2 nm or less.
  • the thicknesses of the insulating layer 157, the insulating layer 158, and the insulating layer 159 may be appropriately set according to the characteristics required of the transistor 100.
  • the insulating layer 157, the insulating layer 158, and the insulating layer 159 be formed successively without being exposed to the atmospheric environment midway.
  • the interface between the insulating layer 157 and the insulating layer 158 and its vicinity, as well as the insulating layer 158 and Impurities or moisture from the atmospheric environment can be prevented from adhering to the interface of the insulating layer 159 and its vicinity.
  • the conductive layer 155 in contact with the semiconductor layer 163 and the conductive layer 161 in contact with the semiconductor layer 163 can be formed using a conductive material that converts the oxide semiconductor into n-type.
  • a conductive material containing nitrogen may be used.
  • a conductive material containing titanium or tantalum and nitrogen may be used.
  • another conductive material may be provided over the conductive material containing nitrogen.
  • a material containing reduced hydrogen and oxygen for the insulating layer 158.
  • a material containing silicon and oxygen may be used. Specifically, silicon oxide, silicon oxynitride, or the like may be used. Since hydrogen is an impurity element in an oxide semiconductor, the semiconductor layer 163 which is an oxide semiconductor and the insulating layer 158 with reduced hydrogen are in contact with each other, making it difficult for the semiconductor layer 163 to become n-type. Further, since the semiconductor layer 163, which is an oxide semiconductor, and the insulating layer 158 containing oxygen are in contact with each other, oxygen vacancies in the semiconductor layer 163 are reduced, the characteristics of the transistor 100 are stabilized, and reliability is improved.
  • the insulating layer 158 preferably contains excess oxygen.
  • excess oxygen refers to oxygen released by heating.
  • a material containing excess oxygen it is preferable that a material through which oxygen does not easily permeate is used for the insulating layer 157 and the insulating layer 159.
  • an oxide containing one or both of aluminum and hafnium, silicon nitride, and the like can be used as the material that is difficult for oxygen to pass through.
  • an insulating layer containing silicon and oxygen may be provided between two insulating layers containing silicon and nitrogen (insulating layer 157, insulating layer 159).
  • the region of the semiconductor layer 163 in contact with the insulating layer 157 and the insulating layer 159 of the semiconductor layer 163 can be Hydrogen is supplied to the contacting regions, and each region of the semiconductor layer 163 becomes n-type. Therefore, a region of the semiconductor layer 163 in contact with the conductive layer 161 and a region of the semiconductor layer 163 in contact with the insulating layer 159 function as either a source (source region) or a drain (drain region). Further, a region of the semiconductor layer 163 in contact with the conductive layer 155 and a region of the semiconductor layer 163 in contact with the insulating layer 157 function as the other of the source (source region) and the drain (drain region).
  • FIG. 3A is an enlarged cross-sectional view of the transistor 100 shown in FIG. 1B.
  • FIGS. 4A and 4B are modified examples of FIG. 3A, and correspond to enlarged cross-sectional views of the transistor 100 shown in FIG. 1B.
  • the insulating layer 157 and the insulating layer 159 may be made of a material that does not contain hydrogen or contains very little hydrogen.
  • silicon nitride with extremely low hydrogen content or silicon nitride oxide with extremely low hydrogen content may be used.
  • the region where the semiconductor layer 163 contacts the insulating layer 157 and the region where the semiconductor layer 163 contacts the insulating layer 159 are not converted to n-type. Therefore, a region of the semiconductor layer 163 in contact with the conductive layer 161 functions as either a source (source region) or a drain (drain region). Further, a region of the semiconductor layer 163 in contact with the conductive layer 155 functions as the other of a source (source region) and a drain (drain region). Further, a region of the semiconductor layer 163 in contact with the insulating layer 158 functions as a channel formation region.
  • the channel length L of the transistor 100 is determined according to the total thickness ts of the respective thicknesses of the insulating layer 157, the insulating layer 158, and the insulating layer 159.
  • the insulating layer 158 may be provided without providing the insulating layer 157 and the insulating layer 159, and the insulating layer 158 may be in contact with the conductive layer 155 and the conductive layer 161 (see FIG. 4A).
  • the length of the side surface of the insulating layer 158 when viewed from the X direction or the Y direction is the channel length L. Therefore, the channel length L of the transistor 100 is determined according to the thickness t of the insulating layer 158.
  • the insulating layer 158 may be referred to as an insulating layer 156.
  • the insulating layer 157 and the insulating layer 159 contain hydrogen.
  • the hydrogen contained in the semiconductor layer 163 and the excess oxygen contained in the insulating layer 158 combine, and sufficient hydrogen is not supplied to the region of the semiconductor layer 163 in contact with the insulating layer 157 and the region of the semiconductor layer 163 in contact with the insulating layer 159, making it difficult to convert into n-type. .
  • sufficient oxygen is no longer supplied to the region of the semiconductor layer 163 in contact with the insulating layer 158.
  • an insulating layer 171 through which oxygen and nitrogen are difficult to permeate is provided between the insulating layer 157 and the insulating layer 158, and an insulating layer 172 through which oxygen and nitrogen are difficult to permeate is provided between the insulating layer 159 and the insulating layer 158.
  • a material that is difficult for oxygen and nitrogen to permeate can be realized using, for example, silicon nitride. Note that in the case of the structure shown in FIG. 4B, the insulating layer 157, the insulating layer 171, the insulating layer 158, the insulating layer 172, and the insulating layer 159 may be collectively referred to as an insulating layer 156.
  • the bond between the hydrogen contained in the insulating layer 157 and the insulating layer 159 and the excess oxygen contained in the insulating layer 158 is inhibited. Therefore, sufficient hydrogen is supplied to the region of the semiconductor layer 163 in contact with the insulating layer 157 and the region of the semiconductor layer 163 in contact with the insulating layer 159. Similarly, sufficient oxygen is supplied to the region of the semiconductor layer 163 in contact with the insulating layer 158.
  • the channel length L is the sum of the lengths of the side surfaces of the insulating layer 171, the insulating layer 158, and the insulating layer 172 when viewed from the X direction or the Y direction. Therefore, the channel length L of the transistor 100 is determined according to the total thickness tm of the thicknesses of the insulating layer 171, the insulating layer 158, and the insulating layer 172.
  • the channel length L is determined depending on the thickness of the insulating layer provided between the conductive layer 161 and the conductive layer 155. Therefore, a transistor with a short channel length L can be manufactured with high precision. Furthermore, variations in characteristics among the plurality of transistors 100 are also reduced. Therefore, the operation of the semiconductor device including the transistor 100 is stabilized, and reliability can be improved. Further, when characteristic variations are reduced, the degree of freedom in circuit design of the semiconductor device increases, and the operating voltage can also be reduced. Therefore, power consumption of the semiconductor device can be reduced.
  • a structure in which three insulating layers (insulating layer 157, insulating layer 158, and insulating layer 159) are provided between conductive layer 155 and conductive layer 161 is shown;
  • the number of insulating layers between layers 161 is not limited to this.
  • the number of insulating layers between the conductive layer 155 and the conductive layer 161 may be one or two layers, or may be four or more layers.
  • the taper angle ⁇ of the side surface of the opening 162 may be greater than or equal to 45 degrees and less than or equal to 90 degrees, preferably greater than or equal to 50 degrees and less than or equal to 75 degrees.
  • the taper angle ⁇ of the side surface of a layer refers to the angle formed between the bottom surface and the side surface of the layer (see FIG. 3A).
  • the circumferential length of the opening 162 when viewed from the Z direction becomes the channel width W of the transistor 100 (see FIG. 3B).
  • the circumferential length may be determined, for example, at a position at half the thickness t (t/2) of the insulating layer 158 or at a position at half the thickness ts (ts/2).
  • the length of the circumference of an arbitrary position of the opening 162 may be set as the channel width W.
  • the length of the circumference at the bottom of the opening 162 may be set as the channel width W, or the length of the circumference at the top of the opening 162 may be set as the channel width W.
  • the channel length L is preferably smaller than at least the channel width W.
  • the channel length L of one aspect of the present invention is 0.1 times or more and 0.99 times or less, preferably 0.5 times or more and 0.8 times or less, with respect to the channel width W.
  • the outline (planar shape) of the opening 162 viewed from the Z direction is shown as a circle, but the shape is not limited to this.
  • the outline of the opening 162 viewed from the Z direction may be elliptical (see FIG. 3C) or rectangular (see FIG. 3D).
  • FIG. 3D shows a rectangle with curved corners.
  • the outline of the opening 162 viewed from the Z direction may have a shape including one or both of a straight part and a curved part (see FIG. 3E).
  • the opening 162 is preferably fine.
  • the maximum width of the opening 162 (the maximum diameter if the opening 162 is circular) as viewed from the Z direction is preferably 60 nm or less, more preferably 50 nm or less, even more preferably 40 nm or less, and extremely preferably 30 nm or less.
  • the maximum width of the opening 162 viewed from the Z direction may be 20 nm or less.
  • the minimum width of the opening 162 (minimum diameter when the opening 162 is circular) as viewed from the Z direction is preferably 1 nm or more, more preferably 5 nm or more. In order to form such a minute opening 162, it is preferable to use a lithography method using short wavelength light such as EUV light or an electron beam.
  • FIG. 5A and 5B show an example of a planar layout in which semiconductor devices 10A are arranged in a matrix.
  • FIG. 5A shows a region where conductive layers 168 and openings 162 (semiconductor device 10A) are arranged alternately along the X direction, a region where conductive layers 168 are repeatedly arranged along the Y direction, and an opening along the Y direction.
  • This is a planar layout in which a region in which 162 (semiconductor devices 10A) are repeatedly arranged is generated.
  • the conductive layer 168 and the opening 162 overlap when viewed from the X direction.
  • FIG. 5B shows a region where the conductive layer 168 is repeatedly arranged along the X direction, a region where the opening 162 (semiconductor device 10A) is repeatedly arranged along the X direction, and a region where the conductive layer 168 is repeatedly arranged along the Y direction.
  • This is a planar layout in which there are regions where the openings 162 (semiconductor device 10A) are repeatedly arranged along the Y direction.
  • the conductive layer 168 and the opening 162 are arranged diagonally. Further, in FIG. 5B, the conductive layer 161 that electrically connects the conductive layer 168 and the semiconductor device 10A is arranged obliquely. That is, when viewed from the Z direction, the straight line connecting the center of the conductive layer 168 and the center of the opening 162 is neither perpendicular to the X direction nor perpendicular to the Y direction.
  • the semiconductor device 10A may be arranged efficiently. Therefore, the degree of integration of the semiconductor device 10A may be improved, and the storage capacity per unit area of the storage device including the semiconductor device 10A may be increased.
  • FIG. 6A and 6B show a semiconductor device 10B that is a modification of the semiconductor device 10A.
  • FIG. 6A is a top view of the semiconductor device 10B.
  • FIG. 6B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 6A.
  • FIG. 6C is a cross-sectional view of the portion indicated by the dashed line A3-A4 in FIG. 6A.
  • the taper angle ⁇ of the side surface of the opening 162 can be increased without increasing the area occupied by the semiconductor device 10B.
  • the coverage of the semiconductor layer 163, the insulating layer 164, and the conductive layer 165 can be improved.
  • the conductive layer 165 within the opening 162 may become thinner toward the bottom of the opening 162.
  • Such a shape of the conductive layer 165 is sometimes called “acicular” or “conical”.
  • FIG. 7A and 7B show a semiconductor device 10C that is a modification of the semiconductor device 10A.
  • FIG. 7A is a top view of the semiconductor device 10C.
  • FIG. 7B is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 7A.
  • FIG. 7C is a cross-sectional view of the portion indicated by the dashed line A3-A4 in FIG. 7A.
  • the side surface of the opening 162 is not provided with a taper angle. If there is no problem in covering the semiconductor layer 163, the insulating layer 164, and the conductive layer 165, the side surfaces of the opening 162 may be vertical or substantially vertical. By making the side surfaces of the opening 162 vertical or substantially vertical, the area occupied by the transistor 100 can be reduced. Therefore, the area occupied by the semiconductor device including the transistor 100 can be reduced.
  • FIG. 8A and 8B show a semiconductor device 10D that is a modification of the semiconductor device 10C.
  • FIG. 8A is a top view of the semiconductor device 10D.
  • FIG. 8B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 8A.
  • FIG. 8C is a cross-sectional view of the portion indicated by the dashed line A3-A4 in FIG. 8A.
  • a semiconductor device 10D shown in FIG. 8 has a configuration in which the conductive layer 155 is removed from the semiconductor device 10A. By not providing the conductive layer 155, the manufacturing process of the semiconductor device 10D is shorter than that of the semiconductor device 10A, and productivity can be improved. Note that in the semiconductor device 10D, a portion of the semiconductor layer 163 functions as one electrode of the capacitive element 110. Specifically, at the bottom of the opening 162, a region of the semiconductor layer 163 that overlaps with the insulating layer 154 and the conductive layer 151 functions as one electrode of the capacitive element 110.
  • FIG. 9A is a cross-sectional view showing a configuration example in which two semiconductor devices 10A (semiconductor device 10Aa and semiconductor device 10Ab) are electrically connected to one wiring BL (conductive layer 168 and conductive layer 152).
  • FIG. 9B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 9A, viewed from the Y direction.
  • FIG. 9C is an equivalent circuit diagram of the cross-sectional view shown in FIG. 9B.
  • Semiconductor device 10Aa is electrically connected to wiring WLa, wiring PLa, and wiring BL.
  • Semiconductor device 10Ab is electrically connected to wiring WLb, wiring PLb, and wiring BL.
  • the conductive layer 165 included in the semiconductor device 10Aa functions as part of the wiring WLa.
  • the conductive layer 151 included in the semiconductor device 10Aa functions as a wiring PLa.
  • the conductive layer 165 included in the semiconductor device 10Ab functions as part of the wiring WLb.
  • the conductive layer 151 included in the semiconductor device 10Ab functions as the wiring PLb.
  • the conductive layer 165 extending in the Y direction can be used as the conductive layer 165 of a plurality of semiconductor devices 10A arranged in the Y direction (see FIG. 9A).
  • the conductive layer 165 of the semiconductor device 10Aa may be electrically connected to the conductive layer 165 of another semiconductor device 10Aa arranged in the Y direction.
  • the conductive layer 151 extending in the Y direction can be used as the conductive layer 151 of a plurality of semiconductor devices 10A arranged in the Y direction.
  • the conductive layer 151 of the semiconductor device 10Aa may be electrically connected to the conductive layer 151 of another semiconductor device 10Aa arranged in the Y direction.
  • ⁇ Modification 5> By stacking the plurality of semiconductor devices 10A, the area occupied by the semiconductor devices 10A can be reduced. For example, by stacking two semiconductor devices 10A, the area occupied by each semiconductor device 10A is halved.
  • FIG. 10 is a cross section showing a configuration example in which four semiconductor devices 10A (semiconductor device 10A[1], semiconductor device 10A[2], semiconductor device 10A[3], and semiconductor device 10A[4]) are stacked in the Z direction. It is a diagram.
  • FIG. 11 is an equivalent circuit diagram of the stacked structure example shown in FIG. 10.
  • the semiconductor device 10A formed in the first layer is indicated as a semiconductor device 10A[1]
  • the semiconductor device 10A formed in the second layer is indicated as a semiconductor device 10A[2]
  • the semiconductor device 10A formed in the third layer is indicated as a semiconductor device 10A[2].
  • the semiconductor device 10A formed in the fourth layer is indicated as a semiconductor device 10A[3], and the semiconductor device 10A formed in the fourth layer is indicated as a semiconductor device 10A[4].
  • the first layer is referred to as a "first layer”
  • the second layer is referred to as a "second layer”
  • the third layer is referred to as a "third layer”
  • the fourth layer is referred to as a "fourth layer.”
  • layers sometimes called "layers”.
  • the semiconductor device 10A[1] is electrically connected to the wiring WL[1], the wiring PL[1], and the wiring BL (see FIG. 11).
  • the semiconductor device 10A[2] is electrically connected to the wiring WL[2], the wiring PL[2], and the wiring BL.
  • the semiconductor device 10A[3] is electrically connected to the wiring WL[3], the wiring PL[3], and the wiring BL.
  • the semiconductor device 10A[4] is electrically connected to the wiring WL[4], the wiring PL[4], and the wiring BL.
  • the conductive layer 165 included in the semiconductor device 10A[1] is electrically connected to the wiring WL[1]. Further, the conductive layer 165 included in the semiconductor device 10A[1] may function as the wiring WL[1] or a part of the wiring WL[1].
  • the conductive layer 151 included in the semiconductor device 10A[1] is electrically connected to the wiring PL[1]. Furthermore, the conductive layer 151 included in the semiconductor device 10A[1] may function as the wiring PL[1] or a part of the wiring PL[1].
  • the conductive layer 165 included in the semiconductor device 10A[2] is electrically connected to the wiring WL[2]. Further, the conductive layer 165 included in the semiconductor device 10A[2] may function as the wiring WL[2] or a part of the wiring WL[2].
  • the conductive layer 151 included in the semiconductor device 10A[2] is electrically connected to the wiring PL[2]. Furthermore, the conductive layer 151 included in the semiconductor device 10A[2] may function as the wiring PL[2] or a part of the wiring PL[2].
  • the conductive layer 165 included in the semiconductor device 10A[3] is electrically connected to the wiring WL[3]. Further, the conductive layer 165 included in the semiconductor device 10A[3] may function as the wiring WL[3] or a part of the wiring WL[3].
  • the conductive layer 151 included in the semiconductor device 10A[3] is electrically connected to the wiring PL[3]. Further, the conductive layer 151 included in the semiconductor device 10A[3] may function as the wiring PL[3] or a part of the wiring PL[3].
  • the conductive layer 165 included in the semiconductor device 10A[4] is electrically connected to the wiring WL[4]. Further, the conductive layer 165 included in the semiconductor device 10A[4] may function as the wiring WL[4] or a part of the wiring WL[4].
  • the conductive layer 151 included in the semiconductor device 10A[4] is electrically connected to the wiring PL[4]. Further, the conductive layer 151 included in the semiconductor device 10A[4] may function as the wiring PL[4] or a part of the wiring PL[4].
  • a semiconductor device 10A[2] is provided on the semiconductor device 10A[1]
  • a semiconductor device 10A[3] is provided on the semiconductor device 10A[2]
  • a semiconductor device 10A[3] is provided on the semiconductor device 10A[3].
  • a device 10A[4] is provided.
  • Each of semiconductor devices 10A[1] to 10A[4] shown in FIG. 10 includes a conductive layer 152 and a conductive layer 168. The conductive layer 168 of each of the semiconductor devices 10A[1] to 10A[4] shown in FIG. connected.
  • the conductive layer 152 of the semiconductor device 10A[1] is electrically connected to the conductive layer 152 of the semiconductor device 10A[2] via the conductive layer 168 of the semiconductor device 10A[1]. connected to. Further, the conductive layer 152 of the semiconductor device 10A[2] is electrically connected to the conductive layer 152 of the semiconductor device 10A[3] via the conductive layer 168 of the semiconductor device 10A[2]. Furthermore, the conductive layer 152 of the semiconductor device 10A[3] is electrically connected to the conductive layer 152 of the semiconductor device 10A[4] via the conductive layer 168 of the semiconductor device 10A[3]. As shown in FIG.
  • the plurality of conductive layers 168 and the plurality of conductive layers 152 are electrically connected to function as one electrode extending in the Z direction.
  • the plurality of conductive layers 168 and the plurality of conductive layers 152 function as one wiring BL.
  • the transistors 100 included in each of the semiconductor devices 10A[1] to 10A[4] are electrically connected to the wiring BL. Specifically, one of the source or drain of the transistor 100 included in the semiconductor device 10A[1], one of the source or drain of the transistor 100 included in the semiconductor device 10A[2], and one of the source or drain of the transistor 100 included in the semiconductor device 10A[3]. One of the source or drain and one of the source or drain of the transistor 100 included in the semiconductor device 10A[4] are electrically connected to the wiring BL.
  • the area occupied by the semiconductor devices including the semiconductor device 10A can be reduced. Further, by providing a plurality of semiconductor devices 10A one on top of the other in the Z direction, the area occupied by the semiconductor devices 10A can be reduced. Therefore, the area occupied by semiconductor devices including the semiconductor device 10A can be further reduced. Further, by providing a plurality of semiconductor devices 10A in an overlapping manner in the Z direction, it is possible to increase the storage capacity per unit area of a storage device including the semiconductor devices 10A.
  • FIG. 12 is a cross-sectional view showing an example of a stacked structure of a plurality of semiconductor devices 10A.
  • FIG. 13 is an equivalent circuit diagram of the configuration example shown in FIG. 12. Note that in FIGS. 12 and 13, two semiconductor devices 10A (semiconductor device 10Aa and semiconductor device 10Ab) formed on the same plane are considered as one set, and one set of semiconductor devices 10A is referred to as four layers (or "stages"). ) This shows an example of overlapping.
  • the semiconductor device 10Aa included in the first layer is shown as a semiconductor device 10Aa[1], and the semiconductor device 10Ab is shown as a semiconductor device 10Ab[1].
  • the semiconductor device 10Aa included in the second layer is indicated as a semiconductor device 10Aa[2], and the semiconductor device 10Ab is indicated as a semiconductor device 10Ab[2].
  • the semiconductor device 10Aa included in the third layer is shown as a semiconductor device 10Aa[3], and the semiconductor device 10Ab is shown as a semiconductor device 10Ab[3].
  • the semiconductor device 10Aa included in the fourth layer is indicated as a semiconductor device 10Aa[4], and the semiconductor device 10Ab is indicated as a semiconductor device 10Ab[4].
  • the semiconductor device 10Aa[1] is electrically connected to the wiring WLa[1], the wiring PLa[1], and the wiring BL (see FIG. 13).
  • Semiconductor device 10Ab[1] is electrically connected to wiring WLb[1], wiring PLb[1], and wiring BL.
  • Semiconductor device 10Aa[2] is electrically connected to wiring WLa[2], wiring PLa[2], and wiring BL.
  • Semiconductor device 10Ab[2] is electrically connected to wiring WLb[2], wiring PLb[2], and wiring BL.
  • Semiconductor device 10Aa[3] is electrically connected to wiring WLa[3], wiring PLa[3], and wiring BL.
  • Semiconductor device 10Ab[3] is electrically connected to wiring WLb[3], wiring PLb[3], and wiring BL.
  • Semiconductor device 10Aa[4] is electrically connected to wiring WLa[4], wiring PLa[4], and wiring BL.
  • Semiconductor device 10Ab[4] is electrically connected to wiring WLb[4], wiring PLb[4], and wiring BL.
  • the area occupied by the semiconductor devices including the semiconductor device 10A can be further reduced. Furthermore, the storage capacity per unit area of the storage device including the semiconductor device 10A can be increased.
  • FIG. 14A shows an equivalent circuit diagram of the semiconductor device 10.
  • the semiconductor device 10 shown in FIG. 14A functions as a DRAM type (1Tr1C type) storage element (memory cell) having one transistor M and one capacitive element Cfe.
  • the capacitive element Cfe is a ferroelectric capacitor having a material capable of having ferroelectricity as a dielectric layer between two electrodes. Therefore, the semiconductor device 10 functions as a FeRAM.
  • the transistor M shown in FIG. 14A corresponds to the transistor 100, and the capacitive element Cfe corresponds to the capacitive element 110.
  • semiconductor layer in which the channel of the transistor M is formed can be used as the semiconductor layer in which the channel of the transistor M is formed.
  • a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination.
  • the semiconductor material for example, silicon or germanium can be used.
  • compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors may be used.
  • an OS transistor has a characteristic of high dielectric strength between a source and a drain. Therefore, by using the transistor M as an OS transistor, a high voltage can be applied to the transistor M even if the transistor M is miniaturized. By miniaturizing the transistor M, the area occupied by the semiconductor device 10 can be reduced. For example, the area occupied by each semiconductor device 10 shown in FIG. 14A can be set to 1/3 to 1/6 of the area occupied by one cell of an SRAM (Static Random Access Memory). Therefore, the semiconductor devices 10 can be arranged with high density. This makes it possible to realize a storage device with a large storage capacity.
  • SRAM Static Random Access Memory
  • OS memory when an OS transistor is used as a transistor included in a memory cell, the memory cell can be referred to as an "OS memory.”
  • DOSRAM registered trademark
  • FeDOSRAM FeDOSRAM
  • the wiring WL has a function as a word line, and by controlling the potential of the wiring WL, the on state and off state of the transistor M can be controlled. For example, if the transistor M is an n-channel transistor, the transistor M is turned on by setting the potential of the wiring WL to a high potential, and the transistor M is turned off by setting the potential of the wiring WL to a low potential. It can be done.
  • the wiring BL has a function as a bit line, and when the transistor M is in an on state, the potential of the wiring BL is supplied to one electrode of the capacitive element Cfe.
  • the wiring PL has a function as a plate line.
  • the other electrode of the capacitive element Cfe is supplied with a potential via the wiring PL.
  • FIG. 14B is a graph showing an example of the hysteresis characteristic.
  • the horizontal axis indicates the voltage applied to the ferroelectric layer.
  • the voltage can be, for example, the difference between the potential of one electrode of the capacitive element Cfe and the potential of the other electrode of the capacitive element Cfe.
  • the vertical axis indicates the polarization of the ferroelectric layer, and in the case of a positive value, positive charges are biased toward one electrode side of the capacitive element Cfe, and negative charges are biased toward the other electrode side of the capacitive element Cfe. Show that you are biased.
  • the polarization has a negative value, it indicates that positive charges are biased toward the other electrode of the capacitive element Cfe, and negative charges are biased toward one electrode of the capacitive element Cfe.
  • the voltage shown on the horizontal axis of the graph in FIG. 14B may be the difference between the potential of the other electrode of the capacitive element Cfe and the potential of one electrode of the capacitive element Cfe.
  • the polarization shown on the vertical axis of the graph in FIG. 14B is set to a positive value when positive charges are biased toward the other electrode side of the capacitive element Cfe and negative charges are biased toward one electrode side of the capacitive element Cfe, A negative value may be used when positive charges are biased towards one electrode of the capacitive element Cfe and negative charges are biased towards the other electrode of the capacitive element Cfe.
  • the hysteresis characteristics of the ferroelectric layer can be represented by a curve 51 and a curve 52.
  • the voltages at the intersections of the curves 51 and 52 are defined as VSP and -VSP. It can be said that VSP and -VSP have different polarities.
  • VSP and -VSP can be said to be saturation polarization voltages.
  • VSP may be referred to as a first saturation polarization voltage
  • -VSP may be referred to as a second saturation polarization voltage.
  • FIG. 14B shows a case where the absolute value of the first saturation polarization voltage and the absolute value of the second saturation polarization voltage are equal, the absolute values thereof may be different.
  • the voltage applied to the ferroelectric layer when the polarization of the ferroelectric layer changes according to the curve 51 and the polarization of the ferroelectric layer is 0 is defined as Vc.
  • the voltage applied to the ferroelectric layer when the polarization of the ferroelectric layer is 0 is defined as -Vc.
  • Vc and -Vc can be said to be coercive voltages.
  • the value of Vc and the value of -Vc can be said to be values between -VSP and VSP.
  • Vc may be referred to as a first coercive voltage
  • -Vc may be referred to as a second coercive voltage.
  • FIG. 14B it is assumed that the absolute value of the first coercive voltage and the absolute value of the second coercive voltage are equal, but the absolute values may be different.
  • the maximum value of polarization when no voltage is applied to the ferroelectric layer is called “remanent polarization Pr”, and the minimum value is called “remanent polarization -Pr”. Further, the difference between the remanent polarization Pr and the remanent polarization -Pr is called “remanent polarization 2Pr”.
  • the voltage applied to the ferroelectric layer of the capacitive element Cfe can be expressed by the difference between the potential of one electrode of the capacitive element Cfe and the potential of the other electrode of the capacitive element Cfe.
  • the other electrode of the capacitive element Cfe is electrically connected to the wiring PL. Therefore, by controlling the potential of the wiring PL, it is possible to control the voltage applied to the ferroelectric layer of the capacitive element Cfe.
  • the voltage applied to the ferroelectric layer of the capacitive element Cfe is the potential difference between the potential of one electrode of the capacitive element Cfe and the potential of the other electrode (wiring PL) of the capacitive element Cfe.
  • the transistor M is an n-channel transistor.
  • FIG. 14C is a timing chart showing an example of a method for driving the semiconductor device 10.
  • FIG. 14C shows an example of writing and reading binary digital data into the semiconductor device 10. Specifically, in FIG. 14C, data "1" is written in the semiconductor device 10 from time T01 to time T02, read and rewritten from time T03 to time T05, read from time T11 to time T13, and the semiconductor device 10 is written. An example is shown in which data "0" is written to the semiconductor device 10, read and rewritten from time T14 to time T16, and read and data "1" is written to the semiconductor device 10 from time T17 to time T19. ing.
  • Vref is supplied as a reference potential to the sense amplifier electrically connected to the wiring BL.
  • Vref is supplied as a reference potential to the sense amplifier electrically connected to the wiring BL.
  • the potential of the wiring WL is set to a high potential.
  • transistor M is turned on.
  • the potential of the wiring BL is assumed to be Vw. Since the transistor M is in the on state, the potential of one electrode of the capacitive element Cfe becomes Vw. Further, the potential of the wiring PL is set to GND. From the above, the voltage applied to the ferroelectric layer of the capacitive element Cfe becomes "Vw-GND". Thereby, data "1" can be written into the semiconductor device 10. Therefore, it can be said that the period from time T01 to time T02 is a period during which a write operation is performed.
  • Vw is preferably equal to or greater than VSP, for example, preferably equal to VSP.
  • GND is a ground potential in this specification and the like, it does not necessarily have to be a ground potential as long as the semiconductor device 10 can be driven to satisfy the purpose of one embodiment of the present invention. For example, if the absolute value of the first saturation polarization voltage is different from the absolute value of the second saturation polarization voltage, and the absolute value of the first coercive voltage is different from the absolute value of the second coercive voltage. In this case, GND can be set to a potential other than ground.
  • the potential of the wiring BL and the potential of the wiring PL are set to GND.
  • the voltage applied to the ferroelectric layer of the capacitive element Cfe becomes 0V. Since the voltage "Vw-GND" applied to the ferroelectric layer of the capacitive element Cfe from time T01 to time T02 can be higher than VSP, the voltage "Vw-GND” applied to the ferroelectric layer of the capacitive element Cfe from time T02 to time T03 is The amount of polarization changes according to curve 52 shown in FIG. 14B. As described above, polarization reversal does not occur in the ferroelectric layer of the capacitive element Cfe between time T02 and time T03.
  • the potential of the wiring WL is set to a low potential. This turns transistor M off. As described above, the write operation is completed and data "1" is held in the semiconductor device 10.
  • the potentials of the wiring BL and the wiring PL are such that polarization reversal does not occur in the ferroelectric layer of the capacitive element Cfe, that is, the voltage applied to the ferroelectric layer of the capacitive element Cfe is the second coercive voltage. Any potential can be used as long as it is equal to or higher than Vc.
  • the potential of the wiring WL is set to a high potential.
  • transistor M is turned on.
  • the potential of the wiring PL is assumed to be Vw.
  • the voltage applied to the ferroelectric layer of the capacitive element Cfe becomes "GND-Vw".
  • the voltage applied to the ferroelectric layer of the capacitive element Cfe from time T01 to time T02 is "Vw-GND”. Therefore, polarization inversion occurs in the ferroelectric layer of the capacitive element Cfe.
  • a current flows through the wiring BL, and the potential of the wiring BL becomes higher than Vref.
  • time T03 to time T04 can be said to be a period in which a read operation is performed.
  • Vref is assumed to be higher than GND and lower than Vw, it may be higher than Vw, for example.
  • time T04 to time T05 is a period in which a rewriting operation is performed.
  • the potential of the wiring BL and the potential of the wiring PL are set to GND. After that, the potential of the wiring WL is set to a low potential. With the above, the rewrite operation is completed and data "1" is held in the semiconductor device 10.
  • the potential of the wiring WL is set to a high potential, and the potential of the wiring PL is set to Vw. Since the data “1” is held in the semiconductor device 10, the potential of the wiring BL becomes higher than Vref, and the data “1” held in the semiconductor device 10 is read out. Therefore, it can be said that the period from time T11 to time T12 is a period in which a read operation is performed.
  • time T12 to time T13 the potential of the wiring BL is set to GND. Since the transistor M is in the on state, the potential of one electrode of the capacitive element Cfe becomes GND. Further, the potential of the wiring PL is assumed to be Vw. From the above, the voltage applied to the ferroelectric layer of the capacitive element Cfe becomes "GND-Vw". Thereby, data "0" can be written into the semiconductor device 10. Therefore, it can be said that time T12 to time T13 is a period in which a write operation is performed.
  • the potential of the wiring BL and the potential of the wiring PL are set to GND.
  • the voltage applied to the ferroelectric layer of the capacitive element Cfe becomes 0V. Since the voltage "GND-Vw" applied to the ferroelectric layer of the capacitive element Cfe from time T12 to time T13 can be set to -VSP or less, the voltage "GND-Vw” applied to the ferroelectric layer of the capacitive element Cfe from time T13 to time T14 is The amount of polarization changes according to a curve 51 shown in FIG. 14B. As described above, polarization reversal does not occur in the ferroelectric layer of the capacitive element Cfe between time T13 and time T14.
  • the potential of the wiring WL is set to a low potential. This turns transistor M off.
  • the write operation is completed and data "0" is held in the semiconductor device 10.
  • the potentials of the wiring BL and the wiring PL are such that polarization reversal does not occur in the ferroelectric layer of the capacitive element Cfe, that is, the voltage applied to the ferroelectric layer of the capacitive element Cfe is a first coercive voltage Vc. Any potential can be used as long as it is below.
  • the potential of the wiring WL is set to a high potential.
  • transistor M is turned on.
  • the potential of the wiring PL is assumed to be Vw.
  • the voltage applied to the ferroelectric layer of the capacitive element Cfe becomes "GND-Vw".
  • the voltage applied to the ferroelectric layer of the capacitive element Cfe from time T12 to time T13 is "GND-Vw”. Therefore, polarization reversal does not occur in the ferroelectric layer of the capacitive element Cfe.
  • the bit line driver circuit can read data "0" held in the semiconductor device 10. Therefore, it can be said that time T14 to time T15 is a period in which a read operation is performed.
  • the period from time T15 to time T16 is a period in which a rewriting operation is performed.
  • the potential of the wiring BL and the potential of the wiring PL are set to GND. After that, the potential of the wiring WL is set to a low potential. With the above, the rewrite operation is completed and data "0" is held in the semiconductor device 10.
  • time T17 to time T18 the potential of the wiring WL is set to a high potential, and the potential of the wiring PL is set to Vw. Since the data "0" is held in the semiconductor device 10, the potential of the wiring BL becomes lower than Vref, and the data "0" held in the semiconductor device 10 is read out. Therefore, it can be said that time T17 to time T18 is a period in which a read operation is performed.
  • time T18 to time T19 the potential of the wiring BL is set to Vw. Since the transistor M is in the on state, the potential of one electrode of the capacitive element Cfe becomes Vw. Further, the potential of the wiring PL is set to GND. From the above, the voltage applied to the ferroelectric layer of the capacitive element Cfe becomes "Vw-GND". Thereby, data "1" can be written into the semiconductor device 10. Therefore, time T18 to time T19 can be said to be a period in which a write operation is performed.
  • the potential of the wiring BL and the potential of the wiring PL are set to GND. After that, the potential of the wiring WL is set to a low potential. As described above, the write operation is completed and data "1" is held in the semiconductor device 10.
  • the semiconductor device 10 using a ferroelectric layer for the capacitive element Cfe functions as a nonvolatile memory element that can retain written information even if power supply is stopped.
  • DRAM Dynamic Random Access Memory
  • a memory element or a memory circuit including a ferroelectric layer is sometimes referred to as a "ferroelectric memory” or "FE memory.” Therefore, the semiconductor device 10 is both a ferroelectric memory and an FE memory.
  • the FE memory can be expected to achieve a rewriting frequency of 1 ⁇ 10 10 or more, preferably 1 ⁇ 10 12 or more, more preferably 1 ⁇ 10 15 or more. Furthermore, the FE memory can be expected to achieve an operating frequency of 10 MHz or higher, preferably 1 GHz or higher.
  • FE memory can be expected to have a memory retention period of 10 days or more, preferably 1 year or more, and more preferably 10 years or more at an environmental temperature of 150° C. or 200° C.
  • the FE memory can also be applied to cache memories and registers of CPUs (Central Processing Units), GPUs (Graphics Processing Units), and the like.
  • CPUs Central Processing Units
  • GPUs Graphics Processing Units
  • the FE memory can also be applied to cache memories and registers of CPUs (Central Processing Units), GPUs (Graphics Processing Units), and the like.
  • an off-CPU Normally off CPU
  • Noff-GPU Normally off GPU
  • FIG. 15A shows a block diagram illustrating a configuration example of a storage device 300 according to one embodiment of the present invention.
  • the storage device 300 shown in FIG. 15A includes a drive circuit 21 and a memory array 20.
  • Memory array 20 includes a plurality of semiconductor devices 10.
  • FIG. 15A shows an example in which the memory array 20 includes a plurality of semiconductor devices 10 arranged in a matrix of m rows and n columns (m and n are integers of 2 or more).
  • the rows and columns extend in directions perpendicular to each other.
  • the Y direction is defined as a "row” and the X direction is defined as a "column,” but the Y direction may be defined as a "column” and the X direction may be defined as a "row.”
  • the semiconductor device 10 in the first row and first column is shown as a semiconductor device 10[1,1] and the semiconductor device 10 in the mth row and nth column is shown as a semiconductor device 10[m,n].
  • the semiconductor device 10 in the mth row and nth column is shown as a semiconductor device 10[m,n].
  • i line when indicating an arbitrary line, it may be written as i line.
  • column j when indicating an arbitrary column, it may be written as column j. Therefore, i is an integer of 1 or more and m or less, and j is an integer of 1 or more and n or less.
  • the semiconductor device 10 in the i-th row and j-th column is referred to as a semiconductor device 10[i,j].
  • the memory array 20 also includes m wires WL extending in the row direction (Y direction), m wires PL extending in the row direction (Y direction), and n wires extending in the Z direction.
  • a wiring BL is provided. Note that although the n wires BL extend in the Z direction, in order to make it easier to understand the relationship between the wires WL, the wires PL, and the wires BL, in FIG. 15A, the n wires BL extend in the column direction (X direction). It is shown as follows.
  • the wiring WL provided in the first (first row) is referred to as wiring WL[1], and the wiring WL provided in m-th (m-th row) is referred to as wiring WL[m]. .
  • the first wiring PL (first row) is designated as wiring PL[1]
  • the mth wiring PL (mth row) is designated as wiring PL[m].
  • the wiring BL provided in the first (first column) is referred to as wiring BL[1]
  • the wiring BL provided in the nth (nth column) is referred to as wiring BL[n].
  • the plurality of semiconductor devices 10 provided in the i-th row are electrically connected to the i-th wiring WL (wiring WL[i]) and the i-th wiring PL (wiring PL[i]).
  • the plurality of semiconductor devices 10 provided in the j-th column are electrically connected to the wiring BL (wiring BL[j]) in the j-th column.
  • the drive circuit 21 includes a PSW 22 (power switch), a PSW 23, and a peripheral circuit 31.
  • the peripheral circuit 31 includes a peripheral circuit 41, a control circuit 32, and a voltage generation circuit 33.
  • each circuit, each signal, and each voltage can be removed or discarded as necessary. Alternatively, other circuits or other signals may be added.
  • Signal BW, signal CE, signal GW, signal CLK, signal WAKE, signal ADDR, signal WDA, signal PON1, and signal PON2 are input signals from the outside, and signal RDA is an output signal to the outside.
  • Signal CLK is a clock signal.
  • signal BW, the signal CE, and the signal GW are control signals.
  • Signal CE is a chip enable signal
  • signal GW is a global write enable signal
  • signal BW is a byte write enable signal.
  • Signal ADDR is an address signal.
  • Signal WDA is write data
  • signal RDA is read data.
  • Signal PON1 and signal PON2 are power gating control signals. Note that the signal PON1 and the signal PON2 may be generated by the control circuit 32.
  • the control circuit 32 is a logic circuit that has a function of controlling the overall operation of the storage device 300. For example, the control circuit performs a logical operation on the signal CE, the signal GW, and the signal BW to determine the operation mode (eg, write operation, read operation) of the storage device 300. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.
  • the control circuit performs a logical operation on the signal CE, the signal GW, and the signal BW to determine the operation mode (eg, write operation, read operation) of the storage device 300.
  • the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.
  • the voltage generation circuit 33 has a function of generating voltage.
  • the signal WAKE has a function of controlling input of the signal CLK to the voltage generation circuit 33. For example, when an H level signal is applied to the signal WAKE, the signal CLK is input to the voltage generation circuit 33, and the voltage generation circuit 33 generates a voltage.
  • the peripheral circuit 41 is a circuit for writing and reading data to and from the semiconductor device 10.
  • the peripheral circuit 41 includes a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, and an output circuit 48 ( It has an Output Cir.) and a sense amplifier 46 (Sense Amplifier).
  • Row decoder 42 and column decoder 44 have the function of decoding signal ADDR.
  • the row decoder 42 is a circuit for specifying a row to be accessed
  • the column decoder 44 is a circuit for specifying a column to be accessed.
  • the row driver 43 has a function of selecting the wiring WL specified by the row decoder 42.
  • the column driver 45 has a function of writing data into the semiconductor device 10, a function of reading data from the semiconductor device 10, a function of holding the read data, and the like.
  • Input circuit 47 has a function of holding signal WDA.
  • the data held by the input circuit 47 is output to the column driver 45.
  • the output data of the input circuit 47 is the data (Din) to be written into the semiconductor device 10.
  • the data (Dout) read from the semiconductor device 10 by the column driver 45 is output to the output circuit 48.
  • the output circuit 48 has a function of holding Dout. Further, the output circuit 48 has a function of outputting Dout to the outside of the storage device 300.
  • the data output from the output circuit 48 is the signal RDA.
  • the PSW 22 has a function of controlling the supply of VDD to the peripheral circuit 31.
  • the PSW 23 has a function of controlling the supply of VHM to the row driver 43.
  • the high power supply voltage of the storage device 300 is VDD
  • the low power supply voltage is GND (ground potential).
  • VHM is a high power supply voltage used to bring the word line to a high level, and is higher than VDD.
  • the signal PON1 controls the on/off of the PSW22
  • the signal PON2 controls the on/off of the PSW23.
  • the number of power domains to which VDD is supplied is one, but the number may be plural. In this case, a power switch may be provided for each power domain.
  • the drive circuit 21 and the memory array 20 may be provided on the same plane. Furthermore, as shown in FIG. 15B, a layer containing the memory array 20 may be provided directly above the layer containing the drive circuit 21. By overlapping the drive circuit 21 and the memory array 20, the signal propagation distance between the drive circuit 21 and the memory array 20 can be shortened. Therefore, resistance and parasitic capacitance between drive circuit 21 and memory array 20 are reduced, and power consumption and signal delay can be reduced. Furthermore, the storage device 300 can be made smaller.
  • FIG. 15B one layer of the memory array 20 is provided on the drive circuit 21, but a plurality of layers of memory arrays 20 may be provided on the drive circuit 21.
  • FIG. 15C shows an example in which k-layer (k is an integer of 2 or more) memory arrays 20 are stacked on the drive circuit 21.
  • the memory array 20 provided in the first layer is indicated as memory array 20[1]
  • the memory array 20 provided in the second layer is indicated as memory array 20[2]
  • the memory array 20 provided in the kth layer is indicated as memory array 20[2].
  • the memory array 20 thus obtained is designated as memory array 20[k].
  • FIG. 16A shows a schematic diagram illustrating a configuration example of the storage device 300.
  • a memory device 300 shown in FIG. 16A has a six-layer memory array 20 provided on a drive circuit 21.
  • the memory array 20 provided in the third layer is indicated as memory array 20[3]
  • the memory array 20 provided in the fourth layer is indicated as memory array 20[4]
  • the memory array 20 provided in the fifth layer is indicated as memory array 20[5]
  • the memory array 20 provided in the sixth layer is indicated as memory array 20[6].
  • the memory array 20 in each layer includes a plurality of semiconductor devices 10 arranged in a matrix, and a wiring WL and a wiring PL extending in the Y direction. Note that in order to make the drawing easier to read, the wiring WL and wiring PL included in each of the first to fifth memory arrays 20 are omitted.
  • the storage device 300 shown in FIG. 16A has a plurality of wirings BL extending in the Z direction.
  • the wiring BL is formed through each of the six layers of memory arrays 20 and electrically connected to the drive circuit 21.
  • the plurality of wirings BL are arranged in a matrix.
  • connection distance between the semiconductor device 10 and the drive circuit 21 can be made shorter than when the wiring BL is extended in the X or Y direction. Can be shortened. Therefore, since the signal propagation distance between the semiconductor device 10 and the drive circuit 21 is shortened, the operating speed of the memory device can be increased. Furthermore, since the parasitic capacitance attached to the wiring BL is reduced, power consumption can be reduced.
  • each of the memory arrays 20 in each layer one of the plurality of semiconductor devices 10 included in the memory array 20 is electrically connected to one of the plurality of wirings BL. Therefore, in the memory device 300 shown in FIG. 16A, a total of six semiconductor devices 10, one from each layer of the memory array 20, are electrically connected to one wiring BL.
  • a configuration in which a plurality of memory cells (semiconductor devices 10) are electrically connected to one wiring BL is also referred to as a "memory string.” Therefore, it can be said that the storage device 300 shown in FIG. 16A is configured to include a plurality of memory strings.
  • FIG. 16B shows a schematic diagram of a memory string included in the storage device 300 shown in FIG. 16A. Note that in order to make the drawing easier to read, the wiring WL and wiring PL electrically connected to the semiconductor device 10 are omitted in the schematic diagram of the memory string shown in FIG. 16B. Further, a part of the equivalent circuit of the memory string is added to FIG. 16B.
  • FIG. 17A shows a schematic diagram illustrating a configuration example of the storage device 300.
  • the storage device 300 shown in FIG. 17A is a modification of the storage device 300 shown in FIG. 16A. Therefore, in order to reduce the repetition of explanation, mainly the points different from the storage device 300 shown in FIG. 16A will be explained.
  • each of the memory arrays 20 in each layer two of the plurality of semiconductor devices 10 included in the memory array 20 are electrically connected to one of the plurality of wirings BL. This is different from the storage device 300 shown in FIG. That is, a total of 12 semiconductor devices 10 are electrically connected to one wiring BL.
  • FIG. 17B shows a schematic diagram of a memory string included in the storage device 300 shown in FIG. 17A. Further, a part of the equivalent circuit of the memory string is added to FIG. 17B.
  • the number of wirings BL can be reduced more than in the storage device 300 shown in FIG. 16A. Therefore, the area occupied by the storage device 300 is reduced.
  • the semiconductor device 10 is an FE memory, and can retain written information for a long period of time even if power supply is stopped. Furthermore, since the refresh operation required in DRAM is not required, a storage device 300 with low power consumption can be realized.
  • FIG. 18 shows an example of a cross-sectional configuration of a storage device 300 according to one embodiment of the present invention.
  • a memory device 300 shown in FIG. 18 has a k-layer memory array 20 above a drive circuit 21.
  • the configuration shown in FIGS. 11 and 17 is illustrated as the k-layer memory array 20.
  • explanation of the k-layer memory array 20 will be omitted here.
  • FIG. 18 illustrates a transistor 400 included in the drive circuit 21.
  • the transistor 400 is provided over a substrate 311 and includes a conductive layer 316 that functions as a gate, an insulating layer 315 that functions as a gate insulator, a semiconductor region 313 that is a part of the substrate 311, and a low layer that functions as a source region or a drain region. It has a resistance region 314a and a low resistance region 314b.
  • the transistor 400 may be either a p-channel transistor or an n-channel transistor.
  • the substrate 311 for example, a single crystal silicon substrate can be used.
  • a semiconductor region 313 (a part of the substrate 311) in which a channel is formed has a convex shape.
  • a conductive layer 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulating layer 315 interposed therebetween.
  • the conductive layer 316 may be formed using a material that adjusts the work function.
  • Such a transistor 400 is also called a FIN type transistor because it utilizes a convex portion of a semiconductor substrate.
  • an insulator may be provided in contact with the upper portion of the convex portion to function as a mask for forming the convex portion.
  • a semiconductor film having a convex shape may be formed by processing an SOI (Silicon on Insulator) substrate.
  • transistor 400 illustrated in FIG. 18 is an example, and the structure is not limited, and an appropriate transistor may be used depending on the circuit configuration or driving method.
  • a wiring layer including an interlayer film, wiring, plug, etc. may be provided between each structure. Further, a plurality of wiring layers can be provided depending on the design. Further, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.
  • an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are sequentially stacked and provided as interlayer films. Further, a conductive layer 328, a conductive layer 330, and the like that are electrically connected to the conductive layer 152 are embedded in the insulating layer 320, the insulating layer 322, the insulating layer 324, and the insulating layer 326. Note that the conductive layer 328 and the conductive layer 330 function as a contact plug or a wiring.
  • the insulator that functions as an interlayer film may function as a flattening film that covers the uneven shape below it.
  • the upper surface of the insulating layer 322 may be subjected to CMP treatment or the like to improve flatness.
  • a wiring layer may be provided over the insulating layer 326 and the conductive layer 330.
  • an insulating layer 350, an insulating layer 352, and an insulating layer 354 are sequentially stacked on an insulating layer 326 and a conductive layer 330.
  • a conductive layer 356 is formed on the insulating layer 350, the insulating layer 352, and the insulating layer 354.
  • the conductive layer 356 functions as a contact plug or a wiring.
  • Conductive layer 356 is electrically connected to conductive layer 152.
  • This embodiment mode describes a metal oxide (hereinafter also referred to as an oxide semiconductor) that can be used for the OS transistor described in the above embodiment mode.
  • the metal oxide used in the OS transistor preferably contains at least indium or zinc, more preferably indium and zinc.
  • metal oxides include indium and M (M is gallium, aluminum, yttrium, tin, silicon, boron, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium). , hafnium, tantalum, tungsten, magnesium, and cobalt) and zinc.
  • M is preferably one or more selected from gallium, aluminum, yttrium, antimony, and tin, with gallium being more preferred.
  • Metal oxides can be produced by chemical vapor deposition (CVD) methods such as sputtering, metal organic chemical vapor deposition (MOCVD), or atomic layer deposition (AL).
  • CVD chemical vapor deposition
  • MOCVD metal organic chemical vapor deposition
  • A atomic layer deposition
  • D Atomic Layer Deposition
  • oxides containing indium (In), gallium (Ga), and zinc (Zn) will be described as examples of metal oxides.
  • an oxide containing indium (In), gallium (Ga), and zinc (Zn) may be referred to as an In-Ga-Zn oxide.
  • the crystal structures of oxide semiconductors include amorphous (including completely amorphous), CAAC (c-axis-aligned crystalline), nc (nanocrystalline), CAC (cloud-aligned composite), and single crystal ( single crystal), and polycrystalline (poly crystal), etc.
  • the crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum.
  • XRD X-ray diffraction
  • it can be evaluated using an XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement.
  • GIXD Gram-Incidence XRD
  • the GIXD method is also referred to as a thin film method or Seemann-Bohlin method.
  • the XRD spectrum obtained by GIXD measurement may be simply referred to as an XRD spectrum.
  • the shape of the peak in the XRD spectrum is approximately symmetrical.
  • the peak shape of the XRD spectrum is asymmetrical.
  • the fact that the peak shape of the XRD spectrum is asymmetrical indicates the presence of crystals in the film or substrate. In other words, if the shape of the peak in the XRD spectrum is not bilaterally symmetrical, the film or substrate cannot be said to be in an amorphous state.
  • the crystal structure of a film or substrate can be evaluated based on a diffraction pattern (also referred to as a nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED).
  • a diffraction pattern also referred to as a nanobeam electron diffraction pattern
  • NBED nanobeam electron diffraction
  • the In-Ga-Zn oxide film formed at room temperature is neither single crystal nor polycrystalline, nor is it in an amorphous state, but in an intermediate state, and it cannot be concluded that it is in an amorphous state. be done.
  • oxide semiconductors may be classified into a different classification from the above.
  • oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors.
  • non-single crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS.
  • non-single crystal oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS), amorphous oxide semiconductors, and the like.
  • CAAC-OS is an oxide semiconductor that has a plurality of crystal regions, and the c-axes of the plurality of crystal regions are oriented in a specific direction.
  • the specific direction is the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film.
  • a crystal region is a region having periodicity in atomic arrangement. Note that if the atomic arrangement is regarded as a lattice arrangement, a crystal region is also a region with a uniform lattice arrangement.
  • the CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and this region may have distortion.
  • CAAC-OS is an oxide semiconductor that has c-axis orientation and no obvious orientation in the a-b plane direction.
  • each of the plurality of crystal regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm).
  • the maximum diameter of the crystal region is less than 10 nm.
  • the maximum diameter of the crystal region may be about several tens of nanometers.
  • CAAC-OS indium (In) and oxygen (hereinafter referred to as In layer), and a layer containing gallium (Ga), zinc (Zn), and oxygen (hereinafter referred to as In layer).
  • In layer a layer containing indium (In) and oxygen
  • In layer a layer containing gallium (Ga), zinc (Zn), and oxygen
  • the (Ga, Zn) layer may contain indium.
  • the In layer may contain gallium.
  • the In layer may contain zinc.
  • the layered structure is observed, for example, as a lattice image in a high-resolution TEM (Transmission Electron Microscope) image.
  • the position of the peak indicating c-axis orientation (2 ⁇ value) may vary depending on the type, composition, etc. of the metal element constituting the CAAC-OS.
  • a plurality of bright points are observed in the electron diffraction pattern of the CAAC-OS film. Note that a certain spot and another spot are observed at points symmetrical positions with the spot of the incident electron beam transmitted through the sample (also referred to as a direct spot) as the center of symmetry.
  • the lattice arrangement within the crystal region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon but may be a non-regular hexagon. Further, the above distortion may have a pentagonal, heptagonal, etc. lattice arrangement.
  • CAAC-OS clear grain boundaries cannot be confirmed even in the vicinity of strain. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction, the bond distance between atoms changes due to substitution of metal atoms, etc. It is thought that this is because of this.
  • CAAC-OS in which clear grain boundaries are not confirmed, is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor.
  • a configuration including Zn is preferable.
  • In--Zn oxide and In--Ga--Zn oxide are more suitable than In oxide because they can suppress the generation of grain boundaries.
  • CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, it can be said that in CAAC-OS, reduction in electron mobility due to grain boundaries is less likely to occur. Further, since the crystallinity of an oxide semiconductor may be reduced due to the incorporation of impurities and/or the generation of defects, CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the oxide semiconductor having CAAC-OS has stable physical properties. Therefore, an oxide semiconductor including a CAAC-OS is resistant to heat and has high reliability. Furthermore, CAAC-OS is stable even at high temperatures (so-called thermal budget) during the manufacturing process. Therefore, if CAAC-OS is used for the OS transistor, the degree of freedom in the manufacturing process can be expanded.
  • nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less).
  • the nc-OS has minute crystals.
  • the size of the microcrystal is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the microcrystal is also referred to as a nanocrystal.
  • no regularity is observed in crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film.
  • nc-OS may be indistinguishable from a-like OS and amorphous oxide semiconductor.
  • a-like OS and amorphous oxide semiconductor For example, when an nc-OS film is subjected to structural analysis using an XRD device, no peak indicating crystallinity is detected in out-of-plane XRD measurement using a ⁇ /2 ⁇ scan.
  • electron diffraction also called selected area electron diffraction
  • an electron beam with a probe diameter larger than that of nanocrystals for example, 50 nm or more
  • an nc-OS film is subjected to electron beam diffraction (also referred to as nanobeam electron diffraction) using an electron beam with a probe diameter that is close to the size of a nanocrystal or smaller than a nanocrystal (for example, from 1 nm to 30 nm)
  • An electron diffraction pattern in which a plurality of spots are observed within a ring-shaped region centered on a direct spot may be obtained.
  • the a-like OS is an oxide semiconductor having a structure between that of an nc-OS and an amorphous oxide semiconductor.
  • A-like OS has holes or low density areas. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and the CAAC-OS.
  • CAC-OS relates to material composition.
  • CAC-OS is, for example, a structure of a material in which elements constituting a metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof.
  • the metal oxide one or more metal elements are unevenly distributed, and the region having the metal element has a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or a size in the vicinity thereof.
  • the mixed state is also called a mosaic or a patch.
  • CAC-OS has a structure in which the material is separated into a first region and a second region, resulting in a mosaic shape, and the first region is distributed throughout the film (hereinafter also referred to as cloud shape). ). That is, CAC-OS is a composite metal oxide having a configuration in which the first region and the second region are mixed.
  • the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are expressed as [In], [Ga], and [Zn], respectively.
  • the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film.
  • the second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film.
  • [In] is larger than [In] in the second region
  • [Ga] is smaller than [Ga] in the second region.
  • the second region is a region in which [Ga] is larger than [Ga] in the first region, and [In] is smaller than [In] in the first region.
  • the first region is a region whose main component is indium oxide, indium zinc oxide, or the like.
  • the second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like.
  • the first region can be rephrased as a region containing In as a main component.
  • the second region can be rephrased as a region containing Ga as a main component.
  • CAC-OS in In-Ga-Zn oxide is a material composition containing In, Ga, Zn, and O, with a region mainly composed of Ga and a region mainly composed of In. Each area has a mosaic shape, and these areas exist randomly. Therefore, it is presumed that CAC-OS has a structure in which metal elements are unevenly distributed.
  • the CAC-OS can be formed, for example, by sputtering without intentionally heating the substrate.
  • one or more selected from inert gas (typically argon), oxygen gas, and nitrogen gas may be used as the film-forming gas. good.
  • the lower the flow rate ratio of oxygen gas to the total flow rate of film-forming gas during film formation the more preferable it is.
  • the flow rate ratio of oxygen gas to the total flow rate of film forming gas during film formation is set to 0% or more and less than 30%, preferably 0% or more and 10% or less.
  • EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) reveals regions mainly composed of In. It can be confirmed that the structure has a structure in which the (first region) and the region (second region) whose main component is Ga are unevenly distributed and mixed.
  • the first region is a region with higher conductivity than the second region.
  • carriers flow through the first region, thereby exhibiting conductivity as a metal oxide. Therefore, by distributing the first region in a cloud shape in the metal oxide, high field effect mobility ( ⁇ ) can be achieved.
  • the second region is a region with higher insulation than the first region. That is, by distributing the second region in the metal oxide, leakage current can be suppressed.
  • CAC-OS when CAC-OS is used in a transistor, the conductivity caused by the first region and the insulation caused by the second region act complementary to each other, thereby providing a switching function (on/off). functions) can be added to CAC-OS.
  • a part of the material has a conductive function
  • a part of the material has an insulating function
  • the entire material has a semiconductor function.
  • CAC-OS is optimal for various semiconductor devices including display devices.
  • Oxide semiconductors have a variety of structures, each with different properties.
  • the oxide semiconductor of one embodiment of the present invention includes two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS. It's okay.
  • ⁇ OS transistor> By using the metal oxide (oxide semiconductor) of one embodiment of the present invention for a transistor, a transistor with high field-effect mobility can be achieved. Furthermore, a highly reliable transistor can be realized. Further, it is possible to realize miniaturized or highly integrated transistors. For example, a transistor with a channel length of 2 nm or more and 30 nm or less can be manufactured.
  • the carrier concentration in the channel formation region of the oxide semiconductor is 1 ⁇ 10 18 cm ⁇ 3 or less, preferably 1 ⁇ 10 17 cm ⁇ 3 or less, more preferably 1 ⁇ 10 15 cm ⁇ 3 or less, more preferably 1 ⁇ It is 1013 cm -3 or less, more preferably 1x1011 cm -3 or less, even more preferably less than 1x1010 cm- 3 , and 1x10-9 cm- 3 or more. Note that in the case of lowering the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be lowered to lower the defect level density.
  • low impurity concentration and low defect level density are referred to as high purity intrinsic or substantially high purity intrinsic.
  • an oxide semiconductor with a low carrier concentration is sometimes referred to as a high-purity intrinsic oxide semiconductor or a substantially high-purity intrinsic oxide semiconductor.
  • the trap level density may also be low.
  • charges captured in trap levels of an oxide semiconductor may take a long time to disappear, and may behave as if they were fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap level density may have unstable electrical characteristics.
  • the impurity in the oxide semiconductor refers to, for example, a substance other than the main component that constitutes the oxide semiconductor.
  • an element having a concentration of less than 0.1 atomic% can be considered an impurity.
  • the band gap of the oxide semiconductor is preferably larger than the band gap of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and even more preferably 3.0 eV or more. It is.
  • the off-state current (also referred to as Ioff) of the transistor can be reduced.
  • Si transistors transistors in which silicon is used as a semiconductor layer in which a channel is formed
  • a short channel effect also referred to as SCE
  • silicon has a small band gap.
  • an OS transistor uses an oxide semiconductor, which is a semiconductor material with a large band gap, short channel effects can be suppressed.
  • an OS transistor is a transistor that has no short channel effect or has very little short channel effect.
  • the short channel effect is a deterioration in electrical characteristics that becomes apparent as transistors become smaller (reduction in channel length).
  • Specific examples of short channel effects include a decrease in threshold voltage, an increase in subthreshold swing value (sometimes referred to as S value), and an increase in leakage current.
  • the S value refers to the amount of change in gate voltage in a subthreshold region that causes a drain current to change by one order of magnitude with a constant drain voltage.
  • characteristic length is widely used as an index of resistance to short channel effects.
  • the characteristic length is an index of the bendability of the potential in the channel forming region. The smaller the characteristic length, the more steeply the potential rises, so it can be said to be resistant to short channel effects.
  • the OS transistor is an accumulation type transistor, and the Si transistor is an inversion type transistor. Therefore, compared to a Si transistor, an OS transistor has a smaller characteristic length between the source region and the channel forming region and a smaller characteristic length between the drain region and the channel forming region. Therefore, OS transistors are more resistant to short channel effects than Si transistors. That is, when it is desired to manufacture a transistor with a short channel length, an OS transistor is more suitable than a Si transistor.
  • the carrier concentration of the oxide semiconductor is lowered until the channel formation region becomes i-type or substantially i-type, conduction in the channel formation region decreases due to the conduction-band-lowering (CBL) effect in short-channel transistors. Since the lower end of the conduction band is lowered, the energy difference at the lower end of the conduction band between the source region or the drain region and the channel formation region may be reduced to 0.1 eV or more and 0.2 eV or less.
  • the OS transistor has an n + /n- / n + accumulation type junction-less transistor structure, in which the channel forming region becomes an n - type region and the source and drain regions become n + -type regions, or , n + /n ⁇ /n + storage type non-junction transistor structure.
  • the OS transistor By making the OS transistor have the above structure, it is possible to have good electrical characteristics even if the semiconductor device is miniaturized or highly integrated. For example, even if the channel length or gate length of an OS transistor is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less, and it is 1 nm or more, 3 nm or more, or 5 nm or more, good electrical characteristics can be obtained. Obtainable. On the other hand, since a short channel effect occurs in a Si transistor, it may be difficult to set the gate length to 20 nm or less or 15 nm or less. Therefore, the OS transistor can be suitably used as a transistor having a shorter channel length than a Si transistor. Note that the gate length is the length of the gate electrode in the direction in which carriers move inside the channel formation region during transistor operation.
  • the high frequency characteristics of the transistor can be improved.
  • the cutoff frequency of the transistor can be improved.
  • the cutoff frequency of the transistor can be set to 50 GHz or more, preferably 100 GHz or more, more preferably 150 GHz or more, for example in a room temperature environment.
  • OS transistors have excellent effects compared to Si transistors, such as a smaller off-state current and the ability to manufacture a transistor with a short channel length.
  • the carbon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 19 atoms /cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 18 atoms/cm 3 or less, even more preferably 1 ⁇ 10 18 atoms/cm 3 or less.
  • the silicon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, and more preferably 3 ⁇ 10 19 atoms/cm 3 or less. cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 18 atoms/cm 3 or less, even more preferably 1 ⁇ 10 18 atoms/cm 3 or less.
  • the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, and more preferably 1 ⁇ 10 19 atoms/cm 3 or less. cm 3 or less, more preferably 5 ⁇ 10 18 atoms/cm 3 or less, more preferably 1 ⁇ 10 18 atoms/cm 3 or less, still more preferably 5 ⁇ 10 17 atoms/cm 3 or less.
  • hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to become water, which may result in the formation of oxygen vacancies.
  • oxygen vacancies When hydrogen enters the oxygen vacancies, electrons, which are carriers, may be generated. Further, a portion of hydrogen may combine with oxygen that is bonded to a metal atom to generate electrons, which are carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. Therefore, it is preferable that hydrogen in the channel formation region of the oxide semiconductor be reduced as much as possible.
  • the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is less than 1 ⁇ 10 20 atoms/cm 3 , preferably less than 5 ⁇ 10 19 atoms/cm 3 , more preferably 1 ⁇ 10 19 atoms/cm 3 , more preferably less than 5 ⁇ 10 18 atoms/cm 3 , even more preferably less than 1 ⁇ 10 18 atoms/cm 3 .
  • the concentration of alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms/cm 3 or less, preferably 2 ⁇ 10 16 atoms/cm 3 or less.
  • FIGS. 19A and 19B An example of a chip 1200 on which a semiconductor device of the present invention is mounted is shown using FIGS. 19A and 19B.
  • a plurality of circuits (systems) are mounted on the chip 1200.
  • SoC system on chip
  • the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog calculation units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.
  • the chip 1200 is provided with bumps (not shown) and is connected to the first surface of the package substrate 1201, as shown in FIG. 19B. Furthermore, a plurality of bumps 1202 are provided on the back surface of the first surface of the package substrate 1201 and are connected to a motherboard 1203.
  • the motherboard 1203 may be provided with storage devices such as a storage device 1221 and a flash memory 1222.
  • the semiconductor device 10 can be used as the storage device 1221. Further, for example, the semiconductor device 10 may be used instead of the flash memory 1222.
  • the CPU 1211 has multiple CPU cores.
  • the GPU 1212 has a plurality of GPU cores.
  • the CPU 1211 and the GPU 1212 may each have a memory that temporarily stores data.
  • a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200.
  • the semiconductor device 10 can be used for the memory.
  • the GPU 1212 is suitable for parallel calculation of a large amount of data, and can be used for image processing or product-sum calculation. By providing the GPU 1212 with an image processing circuit using an oxide semiconductor or a product-sum calculation circuit, image processing and product-sum calculation can be performed with low power consumption.
  • the CPU 1211 and the GPU 1212 are provided on the same chip, the wiring between the CPU 1211 and the GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212 and between the memory of the CPU 1211 and the GPU 1212 is possible. , and after the calculation by the GPU 1212, the calculation result can be transferred from the GPU 1212 to the CPU 1211 at high speed.
  • the analog calculation unit 1213 has one or both of an A/D (analog/digital) conversion circuit and a D/A (digital/analog) conversion circuit. Further, the analog calculation section 1213 may be provided with the above product-sum calculation circuit.
  • the memory controller 1214 includes a circuit that functions as a controller for the storage device 1221 and a circuit that functions as an interface for the flash memory 1222.
  • the interface 1215 has an interface circuit with externally connected devices such as a display device, speaker, microphone, camera, and controller. Controllers include mice, keyboards, game controllers, and the like. As such an interface, USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used.
  • USB Universal Serial Bus
  • HDMI registered trademark
  • High-Definition Multimedia Interface High-Definition Multimedia Interface
  • the network circuit 1216 includes a network circuit such as a LAN (Local Area Network). It may also include a circuit for network security.
  • LAN Local Area Network
  • the above circuit (system) can be formed on the chip 1200 using the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.
  • a package substrate 1201 provided with a chip 1200 having a GPU 1212, a motherboard 1203 provided with a storage device 1221, and a flash memory 1222 can be called a GPU module 1204.
  • the GPU module 1204 includes a chip 1200 using SoC technology, its size can be reduced. Furthermore, since it is excellent in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (portable) game machines.
  • a product-sum calculation circuit using the GPU 1212 can be used to create deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks ( DBN), etc.
  • the chip 1200 can be used as an AI chip or the GPU module 1204 can be used as an AI system module.
  • This embodiment mode shows an example of an electronic component incorporating the semiconductor device described in the above embodiment mode.
  • FIG. 20A shows a perspective view of an electronic component 700 and a board (mounted board 704) on which the electronic component 700 is mounted.
  • the electronic component 700 shown in FIG. 20A includes a storage device 720 within a mold 711. In FIG. 20A, a part is omitted to show the inside of the electronic component 700.
  • the electronic component 700 has a land 712 on the outside of the mold 711. Land 712 is electrically connected to electrode pad 713, and electrode pad 713 is electrically connected to memory device 720 by wire 714.
  • the electronic component 700 is mounted on a printed circuit board 702, for example.
  • a mounting board 704 is completed by combining a plurality of such electronic components and electrically connecting them on the printed circuit board 702.
  • the memory device 720 includes a drive circuit layer 721 and a memory circuit layer 722.
  • the storage device 300 can be used as the storage device 720. Therefore, the drive circuit layer 721 can be said to be a layer including the drive circuit 21. Furthermore, a single-layer or multi-layer memory array 20 can be used for the memory circuit layer 722. Therefore, the drive circuit layer 721 can be said to be a layer that includes the memory array 20.
  • FIG. 20B shows a perspective view of the electronic component 730.
  • the electronic component 730 is an example of a SiP (System in package) or an MCM (Multi Chip Module).
  • an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of storage devices 720 are provided on the interposer 731.
  • the storage device 720 is used as a high bandwidth memory (HBM).
  • HBM high bandwidth memory
  • the semiconductor device 735 an integrated circuit (semiconductor device) such as a CPU, GPU, or FPGA can be used.
  • the package substrate 732 a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used.
  • the interposer 731 a silicon interposer, a resin interposer, or the like can be used.
  • the interposer 731 has a plurality of wiring lines and has a function of electrically connecting a plurality of integrated circuits having different terminal pitches.
  • the plurality of wirings are provided in a single layer or in multiple layers.
  • the interposer 731 has a function of electrically connecting the integrated circuit provided on the interposer 731 to the electrodes provided on the package substrate 732.
  • interposers are sometimes called "rewiring boards” or “intermediate boards.”
  • a through electrode is provided in the interposer 731, and the integrated circuit and the package substrate 732 are electrically connected using the through electrode.
  • TSV Three Silicon Via
  • interposer 731 It is preferable to use a silicon interposer as the interposer 731. Since silicon interposers do not require active elements, they can be manufactured at lower cost than integrated circuits. On the other hand, since wiring formation in a silicon interposer can be performed by a semiconductor process, it is easy to form fine wiring, which is difficult to do with a resin interposer.
  • HBM In HBM, it is necessary to connect many wires to realize a wide memory bandwidth. For this reason, an interposer mounting an HBM is required to form fine and high-density wiring. Therefore, it is preferable to use a silicon interposer as the interposer for mounting the HBM.
  • a silicon interposer in SiP, MCM, etc. using a silicon interposer, reliability is less likely to deteriorate due to a difference in expansion coefficient between the integrated circuit and the interposer. Furthermore, since the silicon interposer has a highly flat surface, poor connection between the integrated circuit provided on the silicon interposer and the silicon interposer is less likely to occur. In particular, it is preferable to use a silicon interposer in a 2.5D package (2.5-dimensional packaging) in which a plurality of integrated circuits are arranged side by side on an interposer.
  • 2.5D package 2.5-dimensional packaging
  • a heat sink may be provided to overlap the electronic component 730.
  • a heat sink it is preferable that the heights of the integrated circuits provided on the interposer 731 are the same.
  • the storage device 720 and the semiconductor device 735 have the same height.
  • an electrode 733 may be provided at the bottom of the package substrate 732.
  • FIG. 20B shows an example in which the electrode 733 is formed with a solder ball. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be realized.
  • the electrode 733 may be formed of a conductive pin. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be realized.
  • the electronic component 730 can be mounted on other boards using various mounting methods, not limited to BGA and PGA.
  • SPGA Sttaggered Pin Grid Array
  • LGA Land Grid Array
  • QFP Quad Flat Package
  • QFJ Quad Flat J-leaded pack
  • QFN Quad Flat Non-leaded package
  • the semiconductor device is, for example, a memory device for various electronic devices (for example, an information terminal, a computer, a smartphone, an electronic book terminal, a digital still camera, a video camera, a recording/playback device, a navigation system, a game console, etc.). Applicable to equipment. Moreover, it can also be used for image sensors, IoT (Internet of Things), healthcare-related equipment, and the like.
  • computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system.
  • FIGS. 21A to 21J and 22A to 22E illustrate how each electronic device includes an electronic component 700 or an electronic component 730 having the semiconductor device.
  • Information terminal 5500 shown in FIG. 21A is a mobile phone (smartphone) that is a type of information terminal.
  • the information terminal 5500 includes a housing 5510 and a display section 5511.
  • the display section 5511 is equipped with a touch panel
  • the housing 5510 is equipped with buttons.
  • the information terminal 5500 can hold temporary files that are generated when an application is executed (for example, a cache when a web browser is used).
  • FIG. 21B illustrates an information terminal 5900 that is an example of a wearable terminal.
  • the information terminal 5900 includes a housing 5901, a display portion 5902, an operation switch 5903, an operation switch 5904, a band 5905, and the like.
  • the wearable terminal can hold temporary files generated when an application is executed by applying a semiconductor device according to one embodiment of the present invention.
  • the desktop information terminal 5300 includes an information terminal main body 5301, a display section 5302, and a keyboard 5303.
  • the desktop information terminal 5300 can hold temporary files generated when an application is executed by applying a semiconductor device according to one embodiment of the present invention.
  • a smartphone, a wearable terminal, and a desktop information terminal are shown as examples of electronic devices in FIGS. 21A to 21C, but information terminals other than smartphones, wearable terminals, and desktop information terminals may also be applied. can. Examples of information terminals other than smartphones, wearable terminals, and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, and workstations.
  • PDAs Personal Digital Assistants
  • FIG. 21D shows an electric refrigerator-freezer 5800 as an example of an electrical appliance.
  • the electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.
  • the electric refrigerator-freezer 5800 is an electric refrigerator-freezer that is compatible with IoT (Internet of Things).
  • a semiconductor device can be applied to an electric refrigerator-freezer 5800.
  • the electric refrigerator-freezer 5800 can send and receive information such as the foods stored in the electric refrigerator-freezer 5800 and the expiration date of the foods to an information terminal or the like via the Internet or the like.
  • the electric refrigerator-freezer 5800 can hold a temporary file generated when transmitting the information in the semiconductor device.
  • an electric refrigerator-freezer was explained as an electric appliance, but other electric appliances include air conditioners including vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cookers, water servers, and air conditioners. Examples include appliances, washing machines, dryers, and audio-visual equipment.
  • FIG. 21E shows a portable game machine 5200, which is an example of a game machine.
  • the portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.
  • FIG. 21F shows a stationary game machine 7500, which is an example of a game machine.
  • Stationary game machine 7500 includes a main body 7520 and a controller 7522.
  • a controller 7522 can be connected to the main body 7520 wirelessly or by wire.
  • the controller 7522 can include a touch panel, a stick, a rotary knob, a sliding knob, or the like that serves as an input interface other than a display unit that displays game images, buttons, or the like.
  • the shape of the controller 7522 is not limited to the shape shown in FIG. 21F, and the shape of the controller 7522 may be changed in various ways depending on the genre of the game.
  • a trigger in a shooting game such as FPS (First Person Shooter), a trigger can be a button and a controller shaped like a gun can be used.
  • a controller shaped like a musical instrument, music device, etc. can be used.
  • the stationary game machine may not use a controller, but instead may be equipped with a camera, a depth sensor, a microphone, etc., and be operated by the game player's gestures or voice.
  • the video of the game machine described above can be output by a display device such as a television device, a display for a personal computer, a display for a game, a head-mounted display, or the like.
  • a display device such as a television device, a display for a personal computer, a display for a game, a head-mounted display, or the like.
  • the portable game machine 5200 or the stationary game machine 7500 By applying the semiconductor device described in the above embodiment to the portable game machine 5200 or the stationary game machine 7500, the portable game machine 5200 or the stationary game machine 7500 with low power consumption can be realized. . Furthermore, low power consumption makes it possible to reduce heat generation from the circuit, thereby reducing the effect of heat generation on the circuit itself, peripheral circuits, and modules.
  • FIG. 21E A portable game machine is shown in FIG. 21E as an example of a game machine. Further, FIG. 21F shows a home-use stationary game machine. Note that the electronic device of one embodiment of the present invention is not limited to this. Examples of electronic devices according to one embodiment of the present invention include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.), pitching machines for batting practice installed in sports facilities, and the like.
  • the semiconductor device described in the above embodiments can be applied to an automobile, which is a moving object, and to the vicinity of the driver's seat of the automobile.
  • FIG. 21G shows an automobile 5700 that is an example of a moving object.
  • the 5700 car is equipped with an instrument panel near the driver's seat that provides a variety of information by displaying speedometer, tachometer, mileage, fuel gauge, gear status, air conditioner settings, etc. Further, a display device showing such information may be provided around the driver's seat.
  • the semiconductor device described in the above embodiment mode can temporarily hold information
  • the semiconductor device can be used, for example, in a system that performs automatic driving of the automobile 5700, road guidance, danger prediction, etc. It can be used to temporarily hold information.
  • the display device may be configured to display temporary information such as road guidance and danger prediction.
  • a configuration may be adopted in which images from a driving recorder installed in the automobile 5700 are held.
  • moving body is not limited to a car.
  • moving objects include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets).
  • FIG. 21H illustrates a digital camera 6240 that is an example of an imaging device.
  • the digital camera 6240 includes a housing 6241, a display section 6242, an operation switch 6243, a shutter button 6244, and the like, and a detachable lens 6246 is attached to the digital camera 6240.
  • the digital camera 6240 is configured here so that the lens 6246 can be removed from the housing 6241 and replaced, the lens 6246 and the housing 6241 may be integrated. Further, the digital camera 6240 may have a configuration in which a strobe device, a viewfinder, etc. can be separately attached.
  • the digital camera 6240 By applying the semiconductor device described in the above embodiment to the digital camera 6240, the digital camera 6240 with low power consumption can be realized. Furthermore, low power consumption makes it possible to reduce heat generation from the circuit, thereby reducing the effect of heat generation on the circuit itself, peripheral circuits, and modules.
  • Video camera The semiconductor device described in the above embodiment can be applied to a video camera.
  • FIG. 21I illustrates a video camera 6300, which is an example of an imaging device.
  • the video camera 6300 includes a first housing 6301, a second housing 6302, a display portion 6303, an operation switch 6304, a lens 6305, a connecting portion 6306, and the like.
  • the operation switch 6304 and the lens 6305 are provided in the first casing 6301, and the display portion 6303 is provided in the second casing 6302.
  • the first casing 6301 and the second casing 6302 are connected by a connecting part 6306, and the angle between the first casing 6301 and the second casing 6302 can be changed by the connecting part 6306. be.
  • the image on the display section 6303 may be switched according to the angle between the first casing 6301 and the second casing 6302 at the connection section 6306.
  • the video camera 6300 When recording video captured by the video camera 6300, it is necessary to perform encoding according to the data recording format. By using the semiconductor device described above, the video camera 6300 can hold temporary files generated during encoding.
  • ICD implantable cardioverter defibrillator
  • FIG. 21J is a schematic cross-sectional view showing an example of an ICD.
  • the ICD main body 5400 includes at least a battery 5401, an electronic component 700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.
  • the ICD main body 5400 is surgically installed in the body, and the two wires are passed through the subclavian vein 5405 and the superior vena cava 5406, and the tip of one wire is placed in the right ventricle and the tip of the other wire is placed in the right atrium. to be done.
  • the ICD main body 5400 has a function as a pacemaker, and paces the heart when the heart rate falls outside of a specified range. In addition, if the heart rate does not improve with pacing (such as rapid ventricular tachycardia or ventricular fibrillation), electric shock treatment is performed.
  • pacing such as rapid ventricular tachycardia or ventricular fibrillation
  • the ICD main body 5400 needs to constantly monitor heart rate in order to properly perform pacing and electric shock. Therefore, ICD main body 5400 has a sensor for detecting heart rate. Further, the ICD main body 5400 can store heart rate data acquired by the sensor, the number of times pacing treatment has been performed, time, etc. in the electronic component 700.
  • the ICD main body 5400 can have higher safety by having a plurality of batteries. Specifically, even if some of the batteries in the ICD main body 5400 become unusable, the remaining batteries can function, so it also functions as an auxiliary power source.
  • antenna 5404 may have an antenna that can transmit physiological signals.
  • a system may be configured to monitor cardiac activity.
  • FIG. 22A shows, as an example of the expansion device, an expansion device 6100 that is portable and equipped with a chip that can store information and is externally attached to a PC.
  • the expansion device 6100 can store information using the chip by connecting it to a PC via, for example, a USB (Universal Serial Bus).
  • FIG. 22A illustrates a portable expansion device 6100
  • the expansion device according to one embodiment of the present invention is not limited to this, and for example, a relatively portable expansion device equipped with a cooling fan or the like. It may also be a large form expansion device.
  • Expansion device 6100 includes a housing 6101, a cap 6102, a USB connector 6103, and a board 6104.
  • a board 6104 is housed in a housing 6101.
  • a circuit for driving the semiconductor device described in the above embodiment mode or the like is provided on the substrate 6104.
  • an electronic component 700 and a controller chip 6106 are attached to the board 6104.
  • the USB connector 6103 functions as an interface for connecting to an external device.
  • SD card The semiconductor device described in the above embodiments can be applied to an SD card that can be attached to electronic devices such as information terminals and digital cameras.
  • FIG. 22B is a schematic diagram of the external appearance of the SD card
  • FIG. 22C is a schematic diagram of the internal structure of the SD card.
  • the SD card 5110 has a housing 5111, a connector 5112, and a board 5113.
  • a connector 5112 functions as an interface for connecting to an external device.
  • the board 5113 is housed in a housing 5111.
  • the substrate 5113 is provided with a semiconductor device and a circuit for driving the semiconductor device.
  • an electronic component 700 and a controller chip 5115 are attached to the board 5113.
  • the circuit configurations of the electronic component 700 and the controller chip 5115 are not limited to those described above, and the circuit configurations may be changed as appropriate depending on the situation. For example, a write circuit, a row driver, a read circuit, etc. included in the electronic component may be incorporated into the controller chip 5115 instead of the electronic component 700.
  • the capacity of the SD card 5110 can be increased.
  • a wireless chip having a wireless communication function may be provided on the substrate 5113. Thereby, wireless communication can be performed between the external device and the SD card 5110, and data can be read from and written to the electronic component 700.
  • SSD Solid State Drive
  • electronic device such as an information terminal.
  • FIG. 22D is a schematic diagram of the external appearance of the SSD
  • FIG. 22E is a schematic diagram of the internal structure of the SSD.
  • the SSD 5150 includes a housing 5151, a connector 5152, and a board 5153.
  • a connector 5152 functions as an interface for connecting to an external device.
  • the board 5153 is housed in a housing 5151.
  • the substrate 5153 is provided with a memory device and a circuit that drives the memory device.
  • an electronic component 700, a memory chip 5155, and a controller chip 5156 are attached to the board 5153.
  • the capacity of the SSD 5150 can be increased.
  • a work memory is incorporated in the memory chip 5155.
  • a DRAM chip may be used as the memory chip 5155.
  • the controller chip 5156 incorporates a processor, an ECC circuit, and the like. Note that the circuit configurations of the electronic component 700, the memory chip 5155, and the controller chip 5115 are not limited to those described above, and the circuit configurations may be changed as appropriate depending on the situation.
  • the controller chip 5156 may also be provided with a memory that functions as a work memory.
  • a computer 5600 shown in FIG. 23A is an example of a large computer (supercomputer) mainly used for scientific and technical calculations. Scientific and technical calculations require high-speed processing of huge amounts of calculations, which consumes a lot of power and generates a lot of heat from the chip. For example, in a data center having a plurality of computers 5600, the amount of digital data used becomes extremely large. Specifically, the amount of digital data in the world is expected to exceed 10 24 (yotta) bytes or 10 30 (quetta) bytes.
  • a supercomputer with low power consumption can be realized. Furthermore, low power consumption makes it possible to reduce heat generation from the circuit, thereby reducing the effect of heat generation on the circuit itself, peripheral circuits, and modules. Furthermore, by using the semiconductor device of one embodiment of the present invention, a supercomputer with low power consumption can be realized. This is expected to reduce the amount of digital data in the world and make a major contribution to global warming countermeasures.
  • a plurality of rack-mounted computers 5620 are stored in a rack 5610.
  • the computer 5620 can have, for example, the configuration shown in the perspective view shown in FIG. 23B.
  • a computer 5620 has a motherboard 5630, and the motherboard 5630 has a plurality of slots 5631 and a plurality of connection terminals.
  • a PC card 5621 is inserted into the slot 5631.
  • the PC card 5621 has a connection terminal 5623, a connection terminal 5624, and a connection terminal 5625, each of which is connected to the motherboard 5630.
  • a PC card 5621 shown in FIG. 23C is an example of a processing board that includes a CPU, a GPU, a storage device, and the like.
  • PC card 5621 has a board 5622.
  • the board 5622 includes a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629.
  • semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 are illustrated in FIG. The description of the semiconductor device 5628 may be referred to.
  • connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630.
  • Examples of the standard of the connection terminal 5629 include PCIe.
  • connection terminal 5623, the connection terminal 5624, and the connection terminal 5625 can be used as an interface for supplying power, inputting signals, etc. to the PC card 5621, for example. Further, for example, it can be used as an interface for outputting a signal calculated by the PC card 5621.
  • the respective standards of the connection terminal 5623, connection terminal 5624, and connection terminal 5625 include, for example, USB (Universal Serial Bus), SATA (Serial ATA), SCSI (Small Computer System Interface), etc. Can be mentioned.
  • the respective standards include HDMI (registered trademark).
  • the semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and by inserting the terminal into a socket (not shown) provided on the board 5622, the semiconductor device 5626 and the board 5622 can be connected. Can be electrically connected.
  • the semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 and the board 5622 are electrically connected by, for example, reflow soldering the terminals to wiring provided on the board 5622. be able to.
  • Examples of the semiconductor device 5627 include an FPGA (Field Programmable Gate Array), a GPU, and a CPU.
  • an electronic component 730 can be used as the semiconductor device 5627.
  • the semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 are electrically connected by, for example, reflow soldering the terminals to wiring provided on the board 5622. be able to.
  • Examples of the semiconductor device 5628 include a storage device.
  • the electronic component 700 can be used as the semiconductor device 5628.
  • Computer 5600 can also function as a parallel computer. By using the computer 5600 as a parallel computer, for example, large-scale calculations required for artificial intelligence learning and inference can be performed.
  • the electronic devices can be made smaller and have lower power consumption. Further, since the semiconductor device of one embodiment of the present invention consumes less power, heat generated from the circuit can be reduced. Therefore, the adverse effect of the heat generation on the circuit itself, peripheral circuits, and module can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, an electronic device that operates stably even in a high-temperature environment can be achieved. Therefore, the reliability of electronic equipment can be improved.
  • a semiconductor device of one embodiment of the present invention includes an OS transistor.
  • the OS transistor has small variations in electrical characteristics due to radiation irradiation. In other words, since it has high resistance to radiation, it can be suitably used in environments where radiation may be incident. For example, OS transistors can be suitably used when used in outer space.
  • OS transistors can be suitably used when used in outer space.
  • FIG. 24 shows an artificial satellite 6800 as an example of space equipment.
  • the artificial satellite 6800 includes a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807.
  • a planet 6804 is illustrated in outer space.
  • outer space refers to, for example, an altitude of 100 km or more, but outer space described in this specification may include the thermosphere, mesosphere, and stratosphere.
  • outer space is an environment with more than 100 times higher radiation levels than on the ground.
  • radiation include electromagnetic waves (electromagnetic radiation) represented by X-rays and gamma rays, and particle radiation represented by alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, meson rays, etc. It will be done.
  • the solar panel 6802 By irradiating the solar panel 6802 with sunlight, electric power necessary for the operation of the artificial satellite 6800 is generated. However, for example, in a situation where the solar panel is not irradiated with sunlight, or in a situation where the amount of sunlight irradiated onto the solar panel is small, less electric power is generated. Therefore, the power necessary for satellite 6800 to operate may not be generated. In order to operate the artificial satellite 6800 even in a situation where generated power is small, it is preferable to provide the artificial satellite 6800 with a secondary battery 6805. Note that the solar panel is sometimes called a solar cell module.
  • Satellite 6800 can generate signals.
  • the signal is transmitted via antenna 6803 and can be received by, for example, a ground-based receiver or other satellite.
  • the position of the receiver that received the signal can be measured.
  • the artificial satellite 6800 can constitute a satellite positioning system.
  • control device 6807 has a function of controlling the artificial satellite 6800.
  • the control device 6807 is configured using one or more selected from, for example, a CPU, a GPU, and a storage device.
  • a semiconductor device including an OS transistor which is one embodiment of the present invention, is preferably used for the control device 6807.
  • OS transistors Compared to Si transistors, OS transistors have smaller fluctuations in electrical characteristics due to radiation irradiation. In other words, it is highly reliable and can be suitably used even in environments where radiation may be incident.
  • the artificial satellite 6800 can be configured to include a sensor.
  • the artificial satellite 6800 can have a function of detecting sunlight reflected by hitting an object provided on the ground.
  • the artificial satellite 6800 can have a function of detecting thermal infrared rays emitted from the earth's surface.
  • the artificial satellite 6800 can have the function of, for example, an earth observation satellite.
  • an artificial satellite is illustrated as an example of space equipment, but the present invention is not limited to this.
  • the semiconductor device of one embodiment of the present invention can be suitably used for space equipment such as a spacecraft, a space capsule, and a space probe.

Landscapes

  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016131253A (ja) * 2011-03-03 2016-07-21 株式会社半導体エネルギー研究所 半導体装置
JP2016149552A (ja) * 2015-02-11 2016-08-18 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
WO2022043825A1 (ja) * 2020-08-27 2022-03-03 株式会社半導体エネルギー研究所 半導体装置
JP2022049605A (ja) * 2020-09-16 2022-03-29 キオクシア株式会社 半導体装置及び半導体記憶装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016131253A (ja) * 2011-03-03 2016-07-21 株式会社半導体エネルギー研究所 半導体装置
JP2016149552A (ja) * 2015-02-11 2016-08-18 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
WO2022043825A1 (ja) * 2020-08-27 2022-03-03 株式会社半導体エネルギー研究所 半導体装置
JP2022049605A (ja) * 2020-09-16 2022-03-29 キオクシア株式会社 半導体装置及び半導体記憶装置

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