WO2024042404A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2024042404A1
WO2024042404A1 PCT/IB2023/057887 IB2023057887W WO2024042404A1 WO 2024042404 A1 WO2024042404 A1 WO 2024042404A1 IB 2023057887 W IB2023057887 W IB 2023057887W WO 2024042404 A1 WO2024042404 A1 WO 2024042404A1
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WIPO (PCT)
Prior art keywords
insulating layer
layer
semiconductor device
semiconductor
transistor
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PCT/IB2023/057887
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French (fr)
Japanese (ja)
Inventor
山崎舜平
國武寛司
松嵜隆徳
Original Assignee
株式会社半導体エネルギー研究所
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Publication of WO2024042404A1 publication Critical patent/WO2024042404A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/20—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region

Definitions

  • One embodiment of the present invention relates to a semiconductor device.
  • one embodiment of the present invention is not limited to the above technical field.
  • the technical field of the invention disclosed in this specification and the like relates to products, methods, or manufacturing methods.
  • one aspect of the present invention relates to a process, machine, manufacture, or composition of matter.
  • examples of the technical field according to one embodiment of the present invention include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, storage devices, signal processing devices, processors, electronic devices, systems, and the like. Examples include driving methods, methods of manufacturing them, methods of testing them, and methods of using them.
  • Non-Patent Document 1 research and development of memories using ferroelectrics are actively being conducted.
  • Non-Patent Document 2 research on ferroelectric HfO 2 -based materials (Non-Patent Document 2), research on ferroelectricity of hafnium oxide thin films (Non-Patent Document 3), HfO 2 Research on ferroelectricity of thin films (Non-Patent Document 4), and demonstration of integration of FeRAM (Ferroelectric Random Access Memory) using ferroelectric material Hf 0.5 Zr 0.5 O 2 with CMOS (Non-Patent Document 5) ) and other studies related to hafnium oxide are also actively being conducted.
  • FeRAM Feroelectric Random Access Memory
  • An object of one embodiment of the present invention is to provide a novel semiconductor device. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device that occupies a small area. Alternatively, an object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device with a large storage capacity.
  • problems related to one embodiment of the present invention are not limited to the problems listed above.
  • the issues listed above do not preclude the existence of other issues.
  • Other issues are those that are not mentioned in this section and are described below.
  • Problems not mentioned in this section can be derived from the descriptions, drawings, etc. by those skilled in the art, and can be extracted as appropriate from these descriptions.
  • one embodiment of the present invention does not need to solve all of the problems listed above and other problems.
  • One embodiment of the present invention solves at least one of the problems listed above and other problems.
  • One embodiment of the present invention includes a capacitor and a transistor on the capacitor, and the capacitor includes a first conductive layer, a first insulating layer on the first conductive layer, and a transistor on the first insulating layer.
  • the transistor includes a second insulating layer on the second conductive layer, a third conductive layer on the second insulating layer, and an opening provided in the second insulating layer and the third conductive layer.
  • This is a semiconductor device that includes a dielectric.
  • Another embodiment of the present invention includes a plurality of stacked layers and a first electrode penetrating the plurality of layers, and each of the plurality of layers includes a capacitor and a transistor on the capacitor.
  • the capacitor has a first conductive layer, a first insulating layer on the first conductive layer, and a second conductive layer on the first insulating layer
  • the transistor has a first conductive layer on the second conductive layer.
  • a fourth conductive layer on the third insulating layer, the opening overlaps with the second conductive layer
  • the first insulating layer includes a ferroelectric material
  • the third conductive layer is electrically connected to the first electrode.
  • the angle between the side surface of the second insulating layer and the bottom surface of the second insulating layer in the opening is preferably 45 degrees or more and 90 degrees or less.
  • the semiconductor device has a memory retention period of 10 days or more at an environmental temperature of 150°C.
  • the second insulating layer may include a fourth insulating layer, a fifth insulating layer on the fourth insulating layer, and a sixth insulating layer on the fifth insulating layer.
  • each of the fourth insulating layer and the sixth insulating layer may include nitrogen and silicon.
  • the fifth insulating layer may include oxygen and silicon.
  • each of the fourth insulating layer and the sixth insulating layer may contain hydrogen.
  • an oxide semiconductor may be used as the semiconductor layer.
  • the semiconductor layer contains at least one of indium and zinc, and oxygen.
  • the first electrode may include a plurality of conductive layers.
  • the first insulating layer contains hafnium, zirconium, and oxygen.
  • the first conductive layer and the second conductive layer contain titanium and nitrogen.
  • a novel semiconductor device can be provided.
  • a semiconductor device that occupies a small area can be provided.
  • a highly reliable semiconductor device can be provided.
  • a semiconductor device with low power consumption can be provided.
  • a semiconductor device with a large storage capacity can be provided.
  • the effects of one embodiment of the present invention are not limited to the effects listed above.
  • the effects listed above do not preclude the existence of other effects. Therefore, one embodiment of the present invention may not have the effects listed above.
  • other effects are effects that are not mentioned in this item and are described below.
  • Other effects can be derived from descriptions such as the specification or drawings by those skilled in the art, and can be extracted as appropriate from these descriptions.
  • One embodiment of the present invention has at least one of the effects listed above and other effects.
  • FIG. 1A and FIG. 1B are diagrams illustrating a configuration example of a semiconductor device.
  • FIGS. 1C and 1D are equivalent circuit diagrams of the semiconductor device.
  • 2A to 2C are diagrams showing configuration examples of a semiconductor device.
  • 3A to 3E are diagrams showing configuration examples of semiconductor devices.
  • 4A and 4B are diagrams illustrating a configuration example of a semiconductor device.
  • 5A and 5B are diagrams illustrating a configuration example of a semiconductor device.
  • 6A to 6C are diagrams showing configuration examples of semiconductor devices.
  • 7A to 7C are diagrams showing configuration examples of semiconductor devices.
  • 8A to 8C are diagrams showing configuration examples of semiconductor devices.
  • 9A and 9B are diagrams illustrating a configuration example of a semiconductor device.
  • FIG. 9C is an equivalent circuit diagram of the semiconductor device.
  • FIG. 10 is a diagram showing a configuration example of a semiconductor device.
  • FIG. 11 is an equivalent circuit diagram of the semiconductor device.
  • FIG. 12 is a diagram showing a configuration example of a semiconductor device.
  • FIG. 13 is an equivalent circuit diagram of the semiconductor device.
  • FIG. 14A is a diagram illustrating an example of a circuit configuration of a memory cell.
  • FIG. 14B is a graph showing an example of hysteresis characteristics.
  • FIG. 14C is a timing chart showing an example of a method for driving a memory cell.
  • 15A to 15C are diagrams showing configuration examples of storage devices.
  • FIG. 16A is a diagram illustrating a configuration example of a storage device.
  • FIG. 16A is a diagram illustrating a configuration example of a storage device.
  • FIG. 16A is a diagram illustrating a configuration example of a storage device.
  • FIG. 16A is a diagram illustrating a
  • FIG. 16B is a schematic diagram of a memory string included in the storage device.
  • FIG. 17A is a diagram illustrating a configuration example of a storage device.
  • FIG. 17B is a schematic diagram of a memory string included in the storage device.
  • FIG. 18 is a diagram showing an example of a cross-sectional configuration of a storage device.
  • 19A and 19B are schematic diagrams of a semiconductor device according to one embodiment of the present invention.
  • 20A and 20B are perspective views showing an example of an electronic component.
  • 21A to 21J are diagrams illustrating an example of an electronic device.
  • 22A to 22E are diagrams illustrating an example of an electronic device.
  • 23A to 23C are diagrams illustrating an example of an electronic device.
  • FIG. 24 is a diagram showing an example of space equipment.
  • a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having the same circuit, and the like. It also refers to any device that can function by utilizing the characteristics of semiconductors. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component containing a chip in a package are examples of semiconductor devices. Furthermore, storage devices, display devices, light emitting devices, lighting devices, electronic devices, and the like are themselves semiconductor devices and may include semiconductor devices.
  • arrows indicating the X direction (direction along the X axis), Y direction (direction along the Y axis), and Z direction (direction along the Z axis) may be provided.
  • the "X direction” refers to the direction along the X axis, and there is no distinction between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction” and the "Z direction”.
  • the X direction, the Y direction, and the Z direction are directions that intersect with each other. More specifically, the X direction, the Y direction, and the Z direction are directions that are orthogonal to each other.
  • one of the X direction, the Y direction, or the Z direction may be referred to as a "first direction” or a “first direction.” Further, the other direction may be referred to as a “second direction” or “second direction”. Further, the remaining one may be referred to as a "third direction” or "third direction.”
  • ordinal numbers such as “first,” “second,” and “third” are added to avoid confusion of constituent elements. Therefore, the number of components is not limited. Further, the order of the constituent elements is not limited. For example, a component referred to as “first” in one embodiment such as this specification is a component referred to as “second” in other embodiments, claims, etc. It is possible. Furthermore, for example, a component referred to as “first” in one of the embodiments of this specification etc. may be omitted in other embodiments or claims.
  • electrode B does not need to be formed directly on insulating layer A, and there is no need to form another structure between insulating layer A and electrode B. Do not exclude things that contain elements.
  • electrode B overlapping insulating layer A is not limited to the state in which electrode B is formed on insulating layer A, but also the state in which electrode B is formed under insulating layer A, or A state in which the electrode B is formed on the right side (or left side) of the insulating layer A is not excluded.
  • the terms “adjacent” and “nearby” do not limit that components are in direct contact.
  • insulating layer A and electrode B do not need to be formed in direct contact with each other, and other components may be placed between insulating layer A and electrode B. Do not exclude what is included.
  • the term “conductive layer” or “conductive film” may be changed to the term “conductor.”
  • the term “conductor” may be changed to the term “conductive layer” or “conductive film.”
  • the term “insulating layer” or “insulating film” may be changed to the term “insulator.”
  • the term “insulator” may be changed to the term “insulating layer” or “insulating film.”
  • voltage refers to the potential difference between two points, and potential refers to the electrostatic energy (electrical potential energy) possessed by a unit charge in an electrostatic field at a certain point.
  • a potential difference between a potential at a certain point and a reference potential is simply called a potential or a voltage, and potential and voltage are often used synonymously. Therefore, in this specification and the like, unless explicitly stated, a potential may be read as a voltage, and a voltage may be read as a potential.
  • Electrode In this specification and the like, terms such as “electrode,” “wiring,” and “terminal” do not functionally limit these components.
  • an “electrode” may be used as part of a “wiring” and vice versa.
  • the term “electrode” or “wiring” includes cases where a plurality of “electrodes” or “wirings” are formed integrally.
  • a “terminal” may be used as part of a “wiring” or “electrode,” and vice versa.
  • the term “terminal” also includes cases where a plurality of "electrodes", “wirings", “terminals”, etc. are formed integrally.
  • an “electrode” can be a part of a “wiring” or a “terminal,” and, for example, a “terminal” can be a part of a “wiring” or a “electrode.”
  • terms such as “electrode,” “wiring,” and “terminal” may be replaced with terms such as "region” depending on the case.
  • terms such as “wiring,” “signal line,” and “power line” can be interchanged depending on the situation or situation. For example, it may be possible to change the term “wiring” to the term “signal line.” Furthermore, for example, it may be possible to change the term “wiring” to a term such as “power line”. The reverse is also true, and terms such as “signal line” and “power line” may sometimes be changed to the term “wiring”. Terms such as “power line” may be changed to terms such as “signal line”. Moreover, the reverse is also true, and a term such as “signal line” may be changed to a term such as “power line”. Further, depending on the case or the situation, the term “potential” applied to the wiring may be changed to a term such as “signal”. Moreover, the reverse is also true, and a term such as “signal” may be changed to the term “potential”.
  • a “capacitive element” refers to, for example, a circuit element having a capacitance value higher than 0F, a wiring region having a capacitance value higher than 0F, a parasitic capacitance, or It can be the gate capacitance of a transistor.
  • capacitor element can sometimes be replaced with the term “capacitance.”
  • capacitor may be translated into the terms “capacitive element,” “parasitic capacitance,” or “gate capacitance.”
  • a “capacitor” (including a “capacitor” having three or more terminals) has a configuration including an insulator and a pair of conductors sandwiching the insulator.
  • the term “pair of conductors” in “capacitance” can be paraphrased as “pair of electrodes,” “pair of conductive regions,” “pair of regions,” or “pair of terminals.” Further, the term “one of a pair of terminals” may also be referred to as “one terminal” or “first terminal.” Moreover, the term “the other of a pair of terminals” may be referred to as “the other terminal” or “the second terminal.” Note that the value of the capacitance can be, for example, 0.05 fF or more and 10 pF or less. Further, for example, it may be set to 1 pF or more and 10 ⁇ F or less.
  • source and drain may be interchanged, such as when using transistors of different polarity or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms “source” and “drain” can be used interchangeably.
  • gate refers to part or all of a gate electrode and a gate wiring.
  • the gate wiring refers to a wiring for electrically connecting the gate electrode of at least one transistor to another electrode or another wiring.
  • source refers to part or all of a source region, a source electrode, and a source wiring.
  • the source region refers to a region of the semiconductor layer where the resistivity is below a certain value.
  • a source electrode refers to a conductive layer including a portion connected to a source region.
  • the source wiring refers to a wiring for electrically connecting the source electrode of at least one transistor to another electrode or another wiring.
  • drain refers to part or all of a drain region, a drain electrode, and a drain wiring.
  • the drain region refers to a region of the semiconductor layer where the resistivity is below a certain value.
  • a drain electrode refers to a conductive layer including a portion connected to a drain region.
  • the drain wiring refers to a wiring for electrically connecting the drain electrode of at least one transistor to another electrode or another wiring.
  • the transistors shown in this specification and the like are enhancement type (normally-off type) field effect transistors.
  • the transistors described in this specification and the like are n-channel transistors, and unless otherwise specified, the threshold voltage (also referred to as "Vth") of the transistors is greater than 0V.
  • the transistor shown in this specification and the like is a p-channel transistor, and unless otherwise specified, the threshold voltage (also referred to as "Vth”) of the transistor is 0V or less.
  • the Vth of a plurality of transistors of the same conductivity type are all equal.
  • off-state current refers to the current (current) that flows between the source and drain when the transistor is in the off state (also referred to as the "non-conducting state” or “blocking state”).
  • drain current also referred to as “drain current” or “Id.”
  • an off state is defined as an n-channel transistor in which the potential difference between the gate and source (also referred to as “gate voltage” or “Vg”) with respect to the source is lower than the threshold voltage.
  • Vg gate voltage
  • the off-state current of an n-channel transistor may refer to the drain current when Vg is lower than Vth.
  • off-state current may refer to, for example, a current flowing between a source and a drain when a transistor is in an off state.
  • on-current refers to Id when a transistor is in an on-state (also referred to as a "conductive state").
  • the on-state refers to a state in which Vg is greater than or equal to Vth for an n-channel transistor, and a state in which Vg is less than or equal to Vth for a p-channel transistor.
  • the on-current of an n-channel transistor may refer to the drain current when Vg is equal to or higher than Vth.
  • parallel refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case where the temperature is greater than or equal to -5 degrees and less than or equal to 5 degrees is also included.
  • substantially parallel or “substantially parallel” refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less.
  • perpendicular refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, cases where the angle is greater than or equal to 85 degrees and less than or equal to 95 degrees are also included.
  • substantially perpendicular or “substantially perpendicular” refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.
  • the conductive layer 242 may be shown divided into a conductive layer 242a and a conductive layer 242b.
  • FIG. 1A is a top view of a semiconductor device 10A.
  • FIG. 1B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 1A, viewed from the Y direction. Note that in the top view of FIG. 1A, some elements are omitted for clarity.
  • FIGS. 1C and 1D show equivalent circuit diagrams of the semiconductor device 10A.
  • one of the source and drain of the transistor 100 is electrically connected to the wiring BL, and the other is electrically connected to one electrode of the capacitor 110.
  • a gate of the transistor 100 is electrically connected to the wiring WL.
  • the other electrode of the capacitive element 110 is electrically connected to the wiring PL.
  • the semiconductor device 10A functions as a memory circuit (also referred to as a "memory element” or "memory cell").
  • FIG. 1C is an equivalent circuit diagram when the capacitive element 110 includes a ferroelectric material
  • FIG. 1D is an equivalent circuit diagram when the capacitive element 110 does not include a ferroelectric material.
  • FIG. 2A is a cross-sectional view of the portion indicated by the dashed line A3-A4 in FIG. 1A, viewed from the X direction.
  • FIG. 2B is an enlarged cross-sectional view of the portion shown by the dashed line B1-B2 in FIG. 2A when viewed from the Z direction.
  • FIG. 2C is an enlarged cross-sectional view of the portion shown by the dashed line B3-B4 in FIG. 2A when viewed from the Z direction.
  • a semiconductor device 10A of one embodiment of the present invention includes an insulating layer 153, and a conductive layer 151 and a conductive layer 152 that are embedded in the insulating layer 153.
  • the conductive layer 151 and the conductive layer 152 can be formed at the same time using the same material and in the same manufacturing process. Further, it is preferable that the positions (positions in the Z direction) of the upper surfaces of the insulating layer 153, the conductive layer 151, and the conductive layer 152 match or substantially match using a chemical mechanical polishing (CMP) method or the like.
  • CMP chemical mechanical polishing
  • an insulating layer 154 is provided over the insulating layer 153, the conductive layer 151, and the conductive layer 152, and a conductive layer 155 is provided over the insulating layer 154.
  • the conductive layer 151 and the conductive layer 155 have a region where they overlap with each other with the insulating layer 154 in between.
  • the semiconductor device 10A has an insulating layer 157 on the insulating layer 154 and the conductive layer 155, an insulating layer 158 on the insulating layer 157, and an insulating layer 159 on the insulating layer 158.
  • the insulating layer 157, the insulating layer 158, and the insulating layer 159 may be collectively referred to as the insulating layer 156 or a spacer layer.
  • a conductive layer 161 is provided on the insulating layer 159.
  • openings 162 are provided in the conductive layer 161, the insulating layer 159, the insulating layer 158, and the insulating layer 157 in a region overlapping with a part of the conductive layer 155 (see FIG. 1B and FIG. 2A).
  • the semiconductor device 10A has a semiconductor layer 163 that covers the opening 162.
  • the semiconductor layer 163 has a region that overlaps with the bottom of the opening 162 and a region that overlaps with the side surface of the opening 162. That is, the semiconductor layer 163 has a region in contact with the insulating layer 156.
  • the semiconductor layer 163 has a region in contact with the side surface of the insulating layer 157, a region in contact with the side surface of the insulating layer 158, and a region in contact with the side surface of the insulating layer 159.
  • the semiconductor layer 163 has a region in contact with the conductive layer 155 and a region in contact with the conductive layer 161. That is, a portion of the semiconductor layer 163 is electrically connected to the conductive layer 155, and another portion of the semiconductor layer 163 is electrically connected to the conductive layer 161. Further, the semiconductor layer 163 may have a region extending beyond the edge of the conductive layer 161 (see FIGS. 1A and 2A).
  • an insulating layer 164 is provided over the insulating layer 159, the conductive layer 161, and the semiconductor layer 163. Further, a conductive layer 165 is provided on the insulating layer 164.
  • the conductive layer 165 has a region that overlaps with the opening 162, and in this region, a region that overlaps with the side surface and bottom of the opening 162 via the insulating layer 164 and the semiconductor layer 163 (see FIG. 1B, FIG. 2A, FIG. 2B, and FIG. (See 2C).
  • the thickness of the semiconductor layer 163 is preferably 1 nm or more, 3 nm or more, or 5 nm or more, and 20 nm or less, 15 nm or less, 12 nm or less, or 10 nm or less.
  • the thickness of the insulating layer 164 is preferably 0.5 nm or more and 15 nm or less, more preferably 0.5 nm or more and 12 nm or less, and even more preferably 0.5 nm or more and 10 nm or less.
  • the insulating layer 164 only needs to have a region with the thickness described above at least in part.
  • an insulating layer 166 is provided on the insulating layer 164. It is preferable that the positions (positions in the Z direction) of the upper surfaces of the conductive layer 165 and the insulating layer 166 match or substantially match. For example, by performing CMP processing or the like, the positions of the upper surfaces of the conductive layer 165 and the insulating layer 166 (positions in the Z direction) are made to match or substantially match, thereby improving the coverage of the insulating layer and the conductive layer that will be formed later. can be increased.
  • an insulating layer 167 is provided over the conductive layer 165 and the insulating layer 166. Further, in the region overlapping with the conductive layer 152, the conductive layer 167, the insulating layer 166, the insulating layer 164, the conductive layer 161, the insulating layer 159, the insulating layer 158, the insulating layer 157, and a part of the insulating layer 154 are embedded. It has a layer 168. Conductive layer 168 is electrically connected to conductive layer 161 and conductive layer 152. Conductive layer 168 and conductive layer 152 function as contact plugs.
  • the conductive layer 155 functions as one electrode of the capacitive element 110.
  • the conductive layer 151 functions as the other electrode of the capacitive element 110.
  • a region of the insulating layer 154 overlapping with the conductive layer 155 and the conductive layer 151 functions as a dielectric of the capacitive element 110.
  • Each of conductive layer 165 and conductive layer 151 extends in the Y direction.
  • the conductive layer 165 functions as the wiring WL or a part of the wiring WL
  • the conductive layer 151 functions as the wiring PL or a part of the wiring PL.
  • the conductive layer 168 and the conductive layer 152 function as the wiring BL or a part of the wiring BL.
  • a transistor 100 and a capacitor 110 are provided in an overlapping manner. By overlapping the transistor 100 and the capacitor 110, the area occupied by the semiconductor device 10A can be reduced.
  • the conductive layer 161 functions as either a source electrode or a drain electrode of the transistor 100. Further, the conductive layer 155 functions as the other of the source electrode and the drain electrode of the transistor 100. For example, if the conductive layer 161 functions as a drain electrode of the transistor 100, the conductive layer 155 functions as a source electrode of the transistor 100. Note that the conductive layer 161 can also be said to function as the wiring BL or a part of the wiring BL.
  • the semiconductor layer 163 functions as a semiconductor layer in which a channel of the transistor 100 is formed (a semiconductor layer including a channel formation region), the insulating layer 164 functions as a gate insulating layer, and the conductive layer 165 functions as a gate electrode. Therefore, it can be said that the transistor 100 is provided in a region including the opening 162.
  • the transistor 100 has a source electrode and a drain electrode arranged in the Z direction. That is, the source and drain of the transistor 100 are arranged at different heights. In other words, the source and drain of the transistor 100 are arranged at different positions in the Z direction.
  • Such a transistor is also referred to as a “vertical channel transistor,” “vertical channel transistor,” “vertical transistor,” or “VFET (Vertical Field Effect Transistor).”
  • a source electrode and a drain electrode are arranged in the Z direction. That is, the channel formation region, the source region, and the drain region are arranged in the Z direction.
  • the vertical transistor can reduce the area occupied by the transistor 100 compared to a conventional transistor in which a channel formation region, a source region, and a drain region are provided separately on the XY plane.
  • the area occupied by the semiconductor device can be reduced.
  • high integration of the semiconductor device can be achieved.
  • the storage capacity per unit area of a storage device using the semiconductor device can be increased.
  • the channel length is set by the exposure limit of photolithography.
  • the channel length can be set by the thickness of the insulating layer 156 or the insulating layer 158. Therefore, the channel length of the transistor 100 is set to a very fine structure below the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, but 1 nm or more, or 5 nm or more).
  • the on-state current of the transistor 100 increases, and frequency characteristics can be improved.
  • a vertical channel transistor a semiconductor device with high operating speed can be provided.
  • ⁇ Capacitive element 110> A region where the conductive layer 151 and the conductive layer 155 overlap each other with the insulating layer 154 in between functions as the capacitive element 110. It is preferable to use a ferroelectric material for the insulating layer 154. Ferroelectric materials have the property that polarization occurs internally when an electric field is applied from the outside, and the polarization remains even when the electric field is reduced to zero. Therefore, a nonvolatile memory element can be realized using a capacitive element (also referred to as a "ferroelectric capacitor”) using this material as a dielectric.
  • a capacitive element also referred to as a "ferroelectric capacitor
  • the capacitive element 110 functions as a ferroelectric capacitor
  • a material that easily causes polarization in the insulating layer 154 as the conductive layer 151 and the conductive layer 155 in contact with the insulating layer 154 which is a ferroelectric material.
  • titanium nitride as the conductive layer 151 and the conductive layer 155.
  • a nonvolatile memory element using a ferroelectric capacitor is sometimes called a "FeRAM” or a “ferroelectric memory.” Materials that can have ferroelectricity will be explained in detail later.
  • a material with a high dielectric constant (also referred to as a "high-k material”) may be used for the insulating layer 154.
  • a high-k material As the insulating layer 154, the capacitance necessary for the capacitive element 110 can be ensured, and the insulating layer 154 can be made thick.
  • the dielectric strength voltage between the conductive layer 151 and the conductive layer 155 is increased, and electrostatic breakdown is suppressed. Therefore, the reliability of the capacitive element 110 is improved. Therefore, the reliability of the semiconductor device using the capacitor 110 is improved.
  • the material used for the substrate there are no major restrictions on the material used for the substrate.
  • the material may be determined by taking into account the presence or absence of translucency and heat resistance to withstand heat treatment.
  • an insulating substrate, a semiconductor substrate, or a conductive substrate may be used.
  • a glass substrate such as barium borosilicate glass or aluminoborosilicate glass
  • a ceramic substrate such as barium borosilicate glass or aluminoborosilicate glass
  • a ceramic substrate such as barium borosilicate glass or aluminoborosilicate glass
  • a ceramic substrate such as barium borosilicate glass or aluminoborosilicate glass
  • a ceramic substrate such as barium borosilicate glass or aluminoborosilicate glass
  • a ceramic substrate such as barium borosilicate glass or aluminoborosilicate glass
  • a ceramic substrate such as barium borosilicate glass or alumino
  • the semiconductor substrate examples include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. . Furthermore, there is a semiconductor substrate having an insulator region inside the semiconductor substrate described above, such as an SOI (Silicon On Insulator) substrate. Furthermore, the semiconductor substrate may be a single crystal semiconductor or a polycrystalline semiconductor.
  • the conductive substrate examples include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate.
  • substrates containing metal nitrides examples include substrates containing metal oxides, and the like.
  • substrates in which an insulator substrate is provided with a conductor or a semiconductor a semiconductor substrate in which a conductor or an insulator is provided, and a conductor substrate in which a semiconductor or an insulator is provided.
  • polyester resins such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile resins, acrylic resins, polyimide resins, polymethyl methacrylate resins, and polycarbonate (PC).
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • PC polycarbonate
  • ) resin polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin , polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc.
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • PES polyethersulfone
  • PEN polyamide resin
  • polystyrene resin polyamide
  • a lightweight semiconductor device including the transistor 100 can be provided. Furthermore, by using the above material as a substrate, a semiconductor device that is resistant to impact can be provided. Further, by using the above material as a substrate, a semiconductor device that is less likely to be damaged can be provided.
  • these substrates provided with elements may be used.
  • Elements provided on the substrate include capacitive elements, resistive elements, switch elements, light emitting elements, and memory elements.
  • an insulating oxide, nitride, oxynitride, nitride oxide, metal oxide, metal oxynitride, metal nitride oxide, or the like can be used.
  • An insulating material selected from lanthanum, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, etc. is used in a single layer or in a stacked manner.
  • a mixture of a plurality of materials among oxide materials, nitride materials, oxynitride materials, and nitrided oxide materials may be used.
  • nitrided oxide refers to a material containing more nitrogen than oxygen.
  • oxynitride refers to a material containing more oxygen than nitrogen. Note that the content of each element can be measured using, for example, Rutherford Backscattering Spectrometry (RBS).
  • RBS Rutherford Backscattering Spectrometry
  • gate insulating layers become thinner, which may cause problems such as leakage current.
  • a high-k material high dielectric constant material, material with high relative permittivity
  • the insulating layer a material having a high dielectric constant such as lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), (Ba,Sr)TiO 3 (BST) may be used in some cases.
  • PZT lead zirconate titanate
  • SBa,Sr)TiO 3 BST
  • the material should be selected depending on the function required of the insulating layer.
  • Materials with high dielectric constants include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, and oxides containing silicon and hafnium. These include oxynitrides or nitrides with silicon and hafnium.
  • materials with low dielectric constants include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, and vacancies.
  • silicon oxides and resins that have
  • the method for forming the insulating material is not particularly limited, and various methods such as vapor deposition, ALD, CVD, sputtering, and spin coating can be used.
  • the insulating layer 153 and the insulating layer 167 are preferably formed using an insulating material through which impurities hardly pass.
  • insulating materials containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorous, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum, in a single layer or It may be used in a laminated manner.
  • Examples of insulating materials that are difficult for impurities to pass through include aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, Examples include silicon nitride.
  • an insulating layer that can function as a planarization layer may be used as the insulating layer.
  • materials that function as the flattening layer include acrylic resin, polyimide, epoxy resin, polyamide, polyimide amide, siloxane resin, benzocyclobutene resin, phenol resin, and precursors thereof.
  • low-k materials low dielectric constant materials, materials with small dielectric constants
  • siloxane resins PSG (phosphorus glass), BPSG (phosphorus boron glass), etc.
  • a plurality of insulating layers formed of these materials may be stacked.
  • the siloxane resin corresponds to a resin containing Si-O-Si bonds formed using a siloxane-based material as a starting material.
  • an organic group for example, an alkyl group or an aryl group
  • a fluoro group may be used as a substituent. Further, the organic group may have a fluoro group.
  • insulating layer 154 that functions as a dielectric of the capacitive element 110
  • three insulating layers also referred to as "ZAZ" in which aluminum oxide is sandwiched between two layers of zirconium oxide may be used.
  • ZAZ is a material with a high dielectric constant, and by using ZAZ as the dielectric of the capacitive element 110, the area occupied by the capacitive element 110 can be reduced.
  • the capacitive element 110 functions as a ferroelectric capacitor.
  • hafnium oxide as the material that can have ferroelectricity.
  • a metal oxide such as zirconium oxide or HfZrOx ( X is a real number larger than 0; hereinafter also referred to as "HfZrOx" may be used as a material that can have ferroelectricity.
  • hafnium oxide can be combined with element J1 (here, element J1 is zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), A material to which one or more selected from lanthanum (La), strontium (Sr), etc. is added may be used.
  • the ratio of the number of atoms of hafnium atoms and element J1 can be set as appropriate.
  • the number of hafnium atoms and zirconium atoms may be set to 1:1 or around 1:1.
  • materials that can have ferroelectricity include zirconium oxide and element J2 (here, element J2 is hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y)). , lanthanum (La), strontium (Sr), etc.) can be used.
  • the ratio of the number of atoms of zirconium atoms and element J2 can be set as appropriate, for example, the number of atoms of zirconium atoms and element J2 may be set to 1:1 or around 1:1.
  • materials that can have ferroelectricity lead titanate (PbTiO x ), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuthate tantalate (SBT), Piezoelectric ceramics having a perovskite structure, such as bismuth ferrite (BFO) and barium titanate, may also be used.
  • materials that can have ferroelectricity include aluminum scandium nitride (Al 1-a Sc a N b (a is a real number greater than 0 and less than 0.5, and b is a value of 1 or a value near it). (hereinafter simply referred to as AlScN)), Al-Ga-Sc nitride, Ga-Sc nitride, etc. can be used.
  • AlScN aluminum scandium nitride
  • Al-Ga-Sc nitride Al-Ga-Sc nitride
  • Ga-Sc nitride etc.
  • a metal nitride containing element M1, element M2, and nitrogen can be used as a material that can have ferroelectricity.
  • the element M1 is one or more selected from aluminum (Al), gallium (Ga), indium (In), and the like.
  • Element M2 is boron (B), scandium (Sc), yttrium (Y), lanthanoids (lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium ( Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu)), Actinides (15 elements from actinium (Ac) to lawrenium (Lr)), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium ( Cr), etc.
  • Actinides (15 elements from actinium (Ac) to lawrenium (Lr)), titanium (Ti
  • the ratio between the number of atoms of element M1 and the number of atoms of element M2 can be set as appropriate.
  • a metal oxide containing element M1 and nitrogen may have ferroelectricity even if it does not contain element M2.
  • a material that can have ferroelectricity a material obtained by adding element M3 to the metal nitride described above can be used.
  • the element M3 is one or more selected from magnesium (Mg), calcium (Ca), strontium (Sr), zinc (Zn), cadmium (Cd), and the like.
  • the ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be set as appropriate.
  • the metal nitride contains at least a group 13 element and nitrogen, which is a group 15 element
  • the metal nitride can be used as a group 13-15 ferroelectric material or a group 13 nitride ferroelectric material. Sometimes called dielectric.
  • perovskite oxynitrides such as SrTaO 2 N and BaTaO 2 N, GaFeO 3 having a ⁇ alumina structure, and the like can be used.
  • the material that can have ferroelectricity for example, a mixture or compound consisting of a plurality of materials selected from the materials listed above can be used.
  • the material capable of having ferroelectricity may have a laminated structure made of a plurality of materials selected from the materials listed above.
  • materials that exhibit ferroelectricity are referred to as In addition to being called a material, it is also called a material that can have ferroelectric properties or a material that has ferroelectric properties.
  • hafnium oxide or a material containing hafnium oxide and zirconium oxide can have ferroelectricity even when processed into a thin film of several nm. Therefore, it is suitable.
  • the thickness of the insulating layer 154 is preferably 100 nm or less, more preferably 50 nm or less, even more preferably 20 nm or less, and even more preferably 10 nm or less (typically 2 nm or more and 9 nm or less).
  • the thickness of the insulating layer 154 is preferably 8 nm or more and 12 nm or less.
  • AlScN aluminum scandium nitride
  • AlScN aluminum scandium nitride
  • AlScN aluminum scandium nitride
  • the film thickness of the material that can have ferroelectricity can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and still more preferably 10 nm or less (typically 2 nm or more and 9 nm or less). .
  • the film thickness is preferably 8 nm or more and 12 nm or less.
  • a material that can have ferroelectricity is sometimes referred to as a ferroelectric material.
  • a layered material that can have ferroelectric properties is sometimes referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film.
  • a device having such a ferroelectric layer, metal oxide film, or metal nitride film may be referred to as a ferroelectric device in this specification and the like.
  • HfZrOx when used as a material that can have ferroelectricity, it is preferable to form a film using an ALD method, particularly a thermal ALD method. Further, when forming a film of a material that can have ferroelectricity using a thermal ALD method, it is preferable to use a material that does not contain hydrocarbon (also referred to as HC) as a precursor. When a material that can have ferroelectric properties contains one or both of hydrogen and carbon, crystallization of the material that can have ferroelectric properties may be inhibited. Therefore, as described above, it is preferable to reduce the concentration of one or both of hydrogen and carbon in a material that can have ferroelectric properties by using a precursor that does not contain hydrocarbons.
  • examples of precursors that do not contain hydrocarbons include chlorine-based materials.
  • HfZrOx hafnium oxide and zirconium oxide
  • HfCl 4 and/or ZrCl 4 may be used as the precursor.
  • a dopant typically silicon, carbon, etc.
  • a forming method using a material containing a hydrocarbon as a precursor may be used as one means for adding carbon as a dopant.
  • the impurity concentration of the material that can have ferroelectricity is low.
  • lower concentrations of hydrogen (H) and carbon (C) are more preferable.
  • the hydrogen concentration of the material that can have ferroelectricity is preferably 5 ⁇ 10 20 atoms/cm 3 or less, more preferably 1 ⁇ 10 20 atoms/cm 3 or less.
  • the carbon concentration of the material that can have ferroelectricity is preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less.
  • HfZrOx is used as a material that can have ferroelectricity
  • H 2 O or O 3 can be used as the oxidizing agent.
  • the oxidizing agent for ALD is not limited to this.
  • the oxidizing agent in the ALD method may include one or more selected from O 2 , O 3 , N 2 O, NO 2 , H 2 O, and H 2 O 2 .
  • a material that can have ferroelectricity it is preferable to have a rectangular crystal structure because it exhibits ferroelectricity.
  • other crystal structures may be included.
  • it may have one or more crystal structures selected from cubic, tetragonal, and monoclinic.
  • a layer for increasing crystallinity may be formed before forming the material that can have ferroelectricity.
  • a metal oxide such as hafnium oxide or zirconium oxide, or hafnium or zirconium can be used as the layer that increases crystallinity.
  • AlScN is used as a material that can have ferroelectricity
  • other crystal structures may be included in addition to the hexagonal crystal structure.
  • a metal nitride such as aluminum nitride or scandium nitride, or aluminum or scandium.
  • the layer for increasing crystallinity may be formed after forming the material that can have ferroelectricity.
  • the material that can have ferroelectricity may have a composite structure having an amorphous structure and a crystalline structure.
  • Conductive materials used for conductive layers such as various wirings and electrodes that make up semiconductor devices include aluminum (Al), chromium (Cr), copper (Cu), silver (Ag), gold (Au), platinum (Pt), Tantalum (Ta), nickel (Ni), titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), vanadium (V), niobium (Nb), manganese (Mn), magnesium (Mg), A metal element selected from zirconium (Zr), beryllium (Be), etc., an alloy containing the above-mentioned metal elements, an alloy containing a combination of the above-mentioned metal elements, etc. can be used.
  • tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are difficult to oxidize.
  • a conductive material or a material that maintains conductivity even if it absorbs oxygen.
  • a semiconductor having high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • the method for forming the conductive material is not particularly limited, and various methods such as vapor deposition, atomic layer deposition (ALD), CVD, sputtering, and spin coating can be used.
  • a Cu-X alloy (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be applied as the conductive material. Since the layer formed of the Cu-X alloy can be processed by a wet etching process, it is possible to suppress manufacturing costs.
  • an aluminum alloy containing one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used as the conductive material.
  • conductive materials that can be used for the conductive layer indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin containing titanium oxide, etc.
  • Conductive materials with oxygen can also be used, such as oxides, indium zinc oxide, indium tin oxide doped with silicon oxide.
  • conductive materials containing nitrogen such as titanium nitride, tantalum nitride, and tungsten nitride can also be used.
  • the conductive layer can also have a laminated structure in which a conductive material containing oxygen, a conductive material containing nitrogen, and a material containing the metal element described above are appropriately combined.
  • the conductive layer may have a single-layer structure of an aluminum layer containing silicon, a two-layer structure in which a titanium layer is stacked on an aluminum layer, a two-layer structure in which a titanium layer is stacked on a titanium nitride layer, or a tungsten layer on a titanium nitride layer.
  • a two-layer structure in which a tungsten layer is laminated on a tantalum nitride layer a two-layer structure in which a tungsten layer is laminated on a tantalum nitride layer, and a three-layer structure in which a titanium layer is laminated, an aluminum layer is laminated on the titanium layer, and a titanium layer is laminated on top of that. good.
  • a plurality of conductive layers formed of the above-mentioned conductive materials may be laminated and used.
  • the conductive layer may have a laminated structure in which a material containing the aforementioned metal element and a conductive material containing oxygen are combined.
  • a laminated structure may be used in which a material containing the aforementioned metal element and a conductive material containing nitrogen are combined.
  • a layered structure may be used in which a material containing the metal element described above, a conductive material containing oxygen, and a conductive material containing nitrogen are combined.
  • a conductive layer is formed by laminating a conductive layer containing copper on a conductive layer containing at least one of indium or zinc and oxygen, and further laminating a conductive layer containing at least one of indium or zinc and oxygen on top of the conductive layer containing at least one of indium or zinc and oxygen. It may also have a three-layer structure. In this case, it is preferable that the side surfaces of the conductive layer containing copper are also covered with a conductive layer containing at least one of indium or zinc and oxygen. Further, for example, a plurality of conductive layers containing at least one of indium or zinc and oxygen may be stacked and used as the conductive layer.
  • the capacitive element 110 functions as a ferroelectric capacitor
  • a material that easily causes polarization in the insulating layer 154 as the conductive layer 151 and the conductive layer 155 in contact with the insulating layer 154 which is a ferroelectric material.
  • titanium nitride as the conductive layer 151 and the conductive layer 155.
  • semiconductor layer 163 As the semiconductor layer 163, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination.
  • semiconductor material silicon, germanium, etc. can be used, for example.
  • a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, or a nitride semiconductor may be used.
  • an organic substance having semiconductor properties or a metal oxide having semiconductor properties also referred to as an oxide semiconductor
  • these semiconductor materials may contain impurities as dopants.
  • the semiconductor layer 163 may be made of single crystal silicon, polycrystalline silicon, microcrystalline silicon, or amorphous silicon.
  • polycrystalline silicon for example, low temperature polysilicon (LTPS) may be used.
  • a transistor using amorphous silicon for the semiconductor layer 163 can be formed over a large glass substrate and can be manufactured at low cost.
  • a transistor using polycrystalline silicon for the semiconductor layer 163 has high field effect mobility and can operate at high speed.
  • a transistor using microcrystalline silicon for the semiconductor layer 163 has higher field effect mobility than a transistor using amorphous silicon, and can operate at high speed.
  • the semiconductor layer 163 may include a layered material that functions as a semiconductor.
  • a layered material is a general term for a group of materials having a layered crystal structure.
  • a layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are laminated via bonds that are weaker than covalent bonds or ionic bonds, such as van der Waals forces.
  • a layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity for the channel formation region, a transistor with high on-state current can be provided.
  • Examples of the layered material include graphene, silicene, and chalcogenide.
  • a chalcogenide is a compound containing chalcogen (an element belonging to Group 16).
  • examples of chalcogenides include transition metal chalcogenides, group 13 chalcogenides, and the like.
  • transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS 2 ), molybdenum selenide (typically MoSe 2 ), and molybdenum tellurium (typically MoTe 2 ) .
  • tungsten sulfide typically WS 2
  • tungsten selenide typically WSe 2
  • tungsten tellurium typically WTe 2
  • hafnium sulfide typically HfS 2
  • hafnium selenide typically HfSe 2
  • zirconium sulfide typically ZrS 2
  • zirconium selenide typically ZrSe 2
  • an oxide semiconductor has a band gap of 2 eV or more
  • a transistor (also referred to as an "OS transistor") using an oxide semiconductor, which is a type of metal oxide, for the semiconductor layer in which a channel is formed has an off-state current of are significantly less. Therefore, power consumption of a semiconductor device including an OS transistor can be reduced.
  • the OS transistor operates stably even in a high-temperature environment, with little variation in characteristics. For example, the off-state current hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even under an environmental temperature of room temperature or higher and 200° C. or lower. Furthermore, the on-state current is less likely to decrease even in a high-temperature environment. Therefore, a semiconductor device including an OS transistor operates stably even in a high-temperature environment and has high reliability.
  • the refresh operation frequency needs to be approximately 1 time/60 msec, but in the storage device of one embodiment of the present invention, the refresh operation frequency is approximately 1 time/10 sec, and 10 msec.
  • the refresh operation frequency can be set to be twice or more or 100 times or more. Note that with the storage device of one embodiment of the present invention, the refresh operation can be performed once every 1 sec or more and 100 sec or less, preferably once every 5 sec or more and 50 sec or less.
  • an OS transistor as the transistor 100. Since the OS transistor has a high dielectric strength voltage between the source and the drain, the channel length can be shortened. Therefore, the on-state current can be increased.
  • the OS transistor is suitable for a vertical channel type transistor.
  • the metal oxide contains at least indium (In) or zinc (Zn).
  • the metal oxide has two or three selected from indium, element M, and zinc.
  • the element M is a metal element or a metalloid element that has a high bonding energy with oxygen, for example, a metal element or a metalloid element that has a higher bonding energy with oxygen than indium.
  • the element M includes aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, and calcium. , strontium, barium, boron, silicon, germanium, and antimony.
  • the element M included in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and further gallium. preferable. Note that in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may include semimetal elements.
  • indium zinc oxide In-Zn oxide
  • indium tin oxide In-Sn oxide
  • indium titanium oxide In-Ti oxide
  • indium gallium oxide In-Ga oxide
  • Indium gallium aluminum oxide Indium gallium aluminum oxide
  • indium gallium tin oxide In-Ga-Sn oxide
  • gallium zinc oxide Ga-Zn oxide, also referred to as "GZO”
  • aluminum Zinc oxide Al-Zn oxide, also written as "AZO”
  • indium aluminum zinc oxide In-Al-Zn oxide, also written as "IAZO”
  • indium tin zinc oxide In-Sn- Zn oxide
  • indium titanium zinc oxide In-Ti-Zn oxide
  • indium gallium tin zinc oxide In-Ga-Sn-Zn oxide, also written as "IGZTO”
  • indium gallium aluminum zinc oxide In-Ga-
  • the field effect mobility of the transistor can be increased.
  • the metal oxide may include one or more metal elements having a large number of periods instead of indium.
  • the metal oxide may contain one or more metal elements having a large number of periods in addition to indium. The greater the overlap between the orbits of the metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including a metal element with a large number of periods, the field effect mobility of the transistor may be increased. Examples of metal elements having a large number of periods include metal elements belonging to the fifth period and metal elements belonging to the sixth period.
  • the metal element examples include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.
  • the metal oxide may contain one or more types of nonmetallic elements.
  • the metal oxide contains a nonmetal element, the field effect mobility of the transistor can be increased in some cases.
  • nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.
  • the metal oxide becomes highly crystalline, and impurities in the metal oxide can be reduced. It can suppress the spread. Therefore, fluctuations in the electrical characteristics of the transistor are suppressed, and reliability can be improved.
  • the electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide applied to the semiconductor layer. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be realized.
  • a metal oxide in which the atomic ratio of indium is greater than or equal to the atomic ratio of zinc may be used.
  • a metal oxide in which the atomic ratio of indium is greater than or equal to the atomic ratio of tin may be used.
  • a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of tin may be used. Furthermore, it is preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of tin.
  • a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of aluminum may be used. Furthermore, it is preferable to use a metal oxide in which the atomic ratio of zinc is higher than that of aluminum.
  • the atomic ratio of indium to the sum of the number of atoms of metal elements contained in the In-Ga-Zn oxide is higher than the atomic ratio of gallium.
  • Metal oxides may also be used.
  • the atomic ratio of indium to the sum of the number of atoms of metal elements contained in the In-M-Zn oxide is higher than the atomic ratio of element M.
  • High metal oxides may also be used.
  • the nearby composition includes a range of ⁇ 30% of the desired atomic ratio.
  • the element M it is preferable to use gallium.
  • the sum of the atomic ratios of the metal elements can be the atomic ratio of the element M.
  • the atomic ratio of the element M can be the sum of the atomic ratio of gallium and the atomic ratio of aluminum.
  • the atomic ratio of indium, element M, and zinc is within the above range.
  • the ratio of the number of atoms of indium to the sum of the number of atoms of metal elements is 30 atom % or more and 100 atom % or less, preferably 30 atom % or more and 95 atom % or less, more preferably is from 35 atom % to 95 atom %, more preferably from 35 atom % to 90 atom %, more preferably from 40 atom % to 90 atom %, more preferably from 45 atom % to 90 atom %, more preferably from 50 atom % to 90 atom %.
  • the ratio of the number of indium atoms to the total number of atoms of indium, element M, and zinc is within the above range.
  • the field effect mobility of the transistor can be increased by increasing the ratio of the number of indium atoms to the sum of the number of atoms of the metal elements.
  • a circuit that can operate at high speed can be manufactured. Furthermore, it becomes possible to reduce the area occupied by the circuit.
  • the analysis of the composition of the composition of metal oxides for example, the energy distributed X -ray optical method (EDX: ENERGY DISPERSIVE X -RAY SPECTROSCOPY), X -ray optical electron division of light (XPS: X -Ray PhotoElECTRON SPECTROSCOP). Y), guidance bond plasma mass analysis method (ICP-MS: Inductively Coupled Plasma-Mass Spectrometry), or Inductively Coupled Plasma-Atomic Emis (ICP-AES) sion Spectrometry) can be used. Alternatively, analysis may be performed by combining two or more of these methods. Note that for elements with low content rates, the actual content rate and the content rate obtained by analysis may differ due to the influence of analysis accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.
  • a sputtering method or an atomic layer deposition (ALD) method can be suitably used to form the metal oxide.
  • the atomic ratio of the target and the atomic ratio of the metal oxide may be different.
  • the atomic ratio of the metal oxide may be smaller than the atomic ratio of the target.
  • the atomic ratio of zinc contained in the target may be about 40% or more and 90% or less.
  • the above atomic ratio is not limited to the atomic ratio of the formed metal oxide, but also the atomic ratio of the sputtering target used for forming the metal oxide film. It may be.
  • GBT Gate Bias Temperature
  • PBTS Positive Bias Temperature Stress
  • NBTS Negative Bias Temperature Stress
  • PBTS test and NBTS test performed under light irradiation are respectively PBTIS (Positive Bias Temperature Illumination Stress) test and NBTIS (Negative Bias Temperature I) test. Illumination Stress) test.
  • n-type transistors In n-type transistors, a positive potential is applied to the gate when the transistor is turned on, so the amount of variation in threshold voltage in the PBTS test is an important indicator of transistor reliability. This is one of the items.
  • a transistor with high reliability against application of a positive bias can be obtained.
  • a transistor with a small threshold voltage variation in the PBTS test can be obtained.
  • the gallium content is lower than the indium content.
  • One of the factors that causes the threshold voltage to fluctuate in the PBTS test is the defect level at or near the interface between the semiconductor layer and the gate insulating layer.
  • gallium contained in metal oxides has a property of attracting oxygen more easily than other metal elements (for example, indium or zinc). Therefore, it is presumed that at the interface between the metal oxide containing a large amount of gallium and the gate insulating layer, gallium combines with excess oxygen in the gate insulating layer, making it easier to generate carrier (electron in this case) trap sites. . Therefore, when a positive potential is applied to the gate, carriers are trapped at the interface between the semiconductor layer and the gate insulating layer, which may cause the threshold voltage to fluctuate.
  • a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of gallium can be applied to the semiconductor layer.
  • a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of gallium it is preferable to apply a metal oxide in which the atomic ratio of metal elements satisfies In>Ga and Zn>Ga to the semiconductor layer.
  • the ratio of the number of gallium atoms to the number of atoms of the metal element contained is greater than 0 atom % and less than 50 atom %, preferably from 0.1 atom % to 40 atom %, more preferably 0.1 atomic % or more and 35 atomic % or less, more preferably 0.1 atomic % or more and 30 atomic % or less, more preferably 0.1 atomic % or more and 25 atomic % or less, more preferably 0.1 atomic % or more and 20 atomic % or less % or less, more preferably 0.1 atomic % or more and 15 atomic % or less, more preferably 0.1 atomic % or more and 10 atomic % or less.
  • V O oxygen vacancy
  • a metal oxide that does not contain gallium may be applied to the semiconductor layer of the OS transistor.
  • In--Zn oxide can be applied to the semiconductor layer.
  • the field effect mobility of the transistor can be increased by increasing the ratio of the number of atoms of indium to the number of atoms of the metal element contained in the metal oxide.
  • the metal oxide becomes highly crystalline, which suppresses fluctuations in the electrical characteristics of the transistor and increases reliability. be able to.
  • a metal oxide that does not contain gallium and zinc, such as indium oxide may be applied to the semiconductor layer. By using a metal oxide that does not contain gallium, it is possible to make threshold voltage fluctuations extremely small, especially in PBTS tests.
  • an oxide containing indium and zinc can be used for the semiconductor layer.
  • the present invention can also be applied to a case where element M is used instead of gallium. It is preferable to use a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of element M to the semiconductor layer. Further, it is preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of element M.
  • the semiconductor layer may have a stacked structure having two or more metal oxide layers.
  • the two or more metal oxide layers included in the semiconductor layer may have the same or approximately the same composition.
  • the same sputtering target can be used to form the layers, thereby reducing manufacturing costs.
  • the two or more metal oxide layers included in the semiconductor layer may have different compositions.
  • a first metal oxide layer having a composition of In:M:Zn 1:3:4 [atomic ratio] or a composition close to that, and In:M:Zn provided on the first metal oxide layer.
  • a laminated structure with a second metal oxide layer having an atomic ratio of 1:1:1 or a composition close to this can be suitably used.
  • gallium or aluminum as the element M.
  • a first metal oxide layer having a composition of In:M:Zn 1:1:1 [atomic ratio] or a composition close to that, and an In:Zn layer provided on the first metal oxide layer.
  • a metal oxide layer having crystallinity As the semiconductor layer, a metal oxide layer having crystallinity can be used.
  • a metal oxide layer having a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, a microcrystalline (NC: nano-crystal) structure, etc. can be used.
  • a crystalline metal oxide layer As a semiconductor layer, the density of defect levels in the semiconductor layer can be reduced, and a highly reliable display device can be realized.
  • the semiconductor layer of the OS transistor may have a stacked structure of two or more metal oxide layers having different crystallinity.
  • the layered structure includes a first metal oxide layer and a second metal oxide layer provided on the first metal oxide layer, and the second metal oxide layer
  • the structure can include a region having higher crystallinity than the oxide layer.
  • the second metal oxide layer may have a region having lower crystallinity than the first metal oxide layer.
  • the two or more metal oxide layers included in the semiconductor layer may have the same or approximately the same composition.
  • a stacked structure of two or more metal oxide layers having different crystallinity can be formed.
  • the two or more metal oxide layers included in the semiconductor layer may have different compositions.
  • a material containing hydrogen is preferably used for the insulating layer 157 and the insulating layer 159.
  • the oxide semiconductor in the region in contact with the insulating layer is made n-type and can function as a source region or a drain region.
  • a material containing silicon, nitrogen, and hydrogen may be used as the insulating layer.
  • silicon nitride containing hydrogen, silicon nitride oxide containing hydrogen, or the like may be used.
  • the thickness of the insulating layer 157 and the insulating layer 159 is preferably 1 nm or more and 15 nm or less, more preferably 2 nm or more and 10 nm or less, more preferably 3 nm or more and 7 nm or less, and further preferably 3 nm or more and 5 nm or less.
  • an oxide semiconductor is used for the semiconductor layer 163
  • a region of the semiconductor layer 163 in contact with the insulating layer 157 containing hydrogen and a region in contact with the insulating layer 159 containing hydrogen function as a source region or a drain region.
  • the thickness of the insulating layer 158 is preferably 1 nm or more and 50 nm or less, more preferably 2 nm or more and 30 nm or less, and even more preferably 3 nm or more and 2 nm or less.
  • the thicknesses of the insulating layer 157, the insulating layer 158, and the insulating layer 159 may be appropriately set according to the characteristics required of the transistor 100.
  • the insulating layer 157, the insulating layer 158, and the insulating layer 159 be formed successively without being exposed to the atmospheric environment midway.
  • the interface between the insulating layer 157 and the insulating layer 158 and its vicinity, as well as the insulating layer 158 and Impurities or moisture from the atmospheric environment can be prevented from adhering to the interface of the insulating layer 159 and its vicinity.
  • the conductive layer 155 in contact with the semiconductor layer 163 and the conductive layer 161 in contact with the semiconductor layer 163 can be formed using a conductive material that converts the oxide semiconductor into n-type.
  • a conductive material containing nitrogen may be used.
  • a conductive material containing titanium or tantalum and nitrogen may be used.
  • another conductive material may be provided over the conductive material containing nitrogen.
  • a material containing reduced hydrogen and oxygen for the insulating layer 158.
  • a material containing silicon and oxygen may be used. Specifically, silicon oxide, silicon oxynitride, or the like may be used. Since hydrogen is an impurity element in an oxide semiconductor, the semiconductor layer 163 which is an oxide semiconductor and the insulating layer 158 with reduced hydrogen are in contact with each other, making it difficult for the semiconductor layer 163 to become n-type. Further, since the semiconductor layer 163, which is an oxide semiconductor, and the insulating layer 158 containing oxygen are in contact with each other, oxygen vacancies in the semiconductor layer 163 are reduced, the characteristics of the transistor 100 are stabilized, and reliability is improved.
  • the insulating layer 158 preferably contains excess oxygen.
  • excess oxygen refers to oxygen released by heating.
  • a material containing excess oxygen it is preferable that a material through which oxygen does not easily permeate is used for the insulating layer 157 and the insulating layer 159.
  • an oxide containing one or both of aluminum and hafnium, silicon nitride, and the like can be used as the material that is difficult for oxygen to pass through.
  • an insulating layer containing silicon and oxygen may be provided between two insulating layers containing silicon and nitrogen (insulating layer 157, insulating layer 159).
  • the region of the semiconductor layer 163 in contact with the insulating layer 157 and the insulating layer 159 of the semiconductor layer 163 can be Hydrogen is supplied to the contacting regions, and each region of the semiconductor layer 163 becomes n-type. Therefore, a region of the semiconductor layer 163 in contact with the conductive layer 161 and a region of the semiconductor layer 163 in contact with the insulating layer 159 function as either a source (source region) or a drain (drain region). Further, a region of the semiconductor layer 163 in contact with the conductive layer 155 and a region of the semiconductor layer 163 in contact with the insulating layer 157 function as the other of the source (source region) and the drain (drain region).
  • FIG. 3A is an enlarged cross-sectional view of the transistor 100 shown in FIG. 1B.
  • FIGS. 4A and 4B are modified examples of FIG. 3A, and correspond to enlarged cross-sectional views of the transistor 100 shown in FIG. 1B.
  • the insulating layer 157 and the insulating layer 159 may be made of a material that does not contain hydrogen or contains very little hydrogen.
  • silicon nitride with extremely low hydrogen content or silicon nitride oxide with extremely low hydrogen content may be used.
  • the region where the semiconductor layer 163 contacts the insulating layer 157 and the region where the semiconductor layer 163 contacts the insulating layer 159 are not converted to n-type. Therefore, a region of the semiconductor layer 163 in contact with the conductive layer 161 functions as either a source (source region) or a drain (drain region). Further, a region of the semiconductor layer 163 in contact with the conductive layer 155 functions as the other of a source (source region) and a drain (drain region). Further, a region of the semiconductor layer 163 in contact with the insulating layer 158 functions as a channel formation region.
  • the channel length L of the transistor 100 is determined according to the total thickness ts of the respective thicknesses of the insulating layer 157, the insulating layer 158, and the insulating layer 159.
  • the insulating layer 158 may be provided without providing the insulating layer 157 and the insulating layer 159, and the insulating layer 158 may be in contact with the conductive layer 155 and the conductive layer 161 (see FIG. 4A).
  • the length of the side surface of the insulating layer 158 when viewed from the X direction or the Y direction is the channel length L. Therefore, the channel length L of the transistor 100 is determined according to the thickness t of the insulating layer 158.
  • the insulating layer 158 may be referred to as an insulating layer 156.
  • the insulating layer 157 and the insulating layer 159 contain hydrogen.
  • the hydrogen contained in the semiconductor layer 163 and the excess oxygen contained in the insulating layer 158 combine, and sufficient hydrogen is not supplied to the region of the semiconductor layer 163 in contact with the insulating layer 157 and the region of the semiconductor layer 163 in contact with the insulating layer 159, making it difficult to convert into n-type. .
  • sufficient oxygen is no longer supplied to the region of the semiconductor layer 163 in contact with the insulating layer 158.
  • an insulating layer 171 through which oxygen and nitrogen are difficult to permeate is provided between the insulating layer 157 and the insulating layer 158, and an insulating layer 172 through which oxygen and nitrogen are difficult to permeate is provided between the insulating layer 159 and the insulating layer 158.
  • a material that is difficult for oxygen and nitrogen to permeate can be realized using, for example, silicon nitride. Note that in the case of the structure shown in FIG. 4B, the insulating layer 157, the insulating layer 171, the insulating layer 158, the insulating layer 172, and the insulating layer 159 may be collectively referred to as an insulating layer 156.
  • the bond between the hydrogen contained in the insulating layer 157 and the insulating layer 159 and the excess oxygen contained in the insulating layer 158 is inhibited. Therefore, sufficient hydrogen is supplied to the region of the semiconductor layer 163 in contact with the insulating layer 157 and the region of the semiconductor layer 163 in contact with the insulating layer 159. Similarly, sufficient oxygen is supplied to the region of the semiconductor layer 163 in contact with the insulating layer 158.
  • the channel length L is the sum of the lengths of the side surfaces of the insulating layer 171, the insulating layer 158, and the insulating layer 172 when viewed from the X direction or the Y direction. Therefore, the channel length L of the transistor 100 is determined according to the total thickness tm of the thicknesses of the insulating layer 171, the insulating layer 158, and the insulating layer 172.
  • the channel length L is determined depending on the thickness of the insulating layer provided between the conductive layer 161 and the conductive layer 155. Therefore, a transistor with a short channel length L can be manufactured with high precision. Furthermore, variations in characteristics among the plurality of transistors 100 are also reduced. Therefore, the operation of the semiconductor device including the transistor 100 is stabilized, and reliability can be improved. Further, when characteristic variations are reduced, the degree of freedom in circuit design of the semiconductor device increases, and the operating voltage can also be reduced. Therefore, power consumption of the semiconductor device can be reduced.
  • a structure in which three insulating layers (insulating layer 157, insulating layer 158, and insulating layer 159) are provided between conductive layer 155 and conductive layer 161 is shown;
  • the number of insulating layers between layers 161 is not limited to this.
  • the number of insulating layers between the conductive layer 155 and the conductive layer 161 may be one or two layers, or may be four or more layers.
  • the taper angle ⁇ of the side surface of the opening 162 may be greater than or equal to 45 degrees and less than or equal to 90 degrees, preferably greater than or equal to 50 degrees and less than or equal to 75 degrees.
  • the taper angle ⁇ of the side surface of a layer refers to the angle formed between the bottom surface and the side surface of the layer (see FIG. 3A).
  • the circumferential length of the opening 162 when viewed from the Z direction becomes the channel width W of the transistor 100 (see FIG. 3B).
  • the circumferential length may be determined, for example, at a position at half the thickness t (t/2) of the insulating layer 158 or at a position at half the thickness ts (ts/2).
  • the length of the circumference of an arbitrary position of the opening 162 may be set as the channel width W.
  • the length of the circumference at the bottom of the opening 162 may be set as the channel width W, or the length of the circumference at the top of the opening 162 may be set as the channel width W.
  • the channel length L is preferably smaller than at least the channel width W.
  • the channel length L of one aspect of the present invention is 0.1 times or more and 0.99 times or less, preferably 0.5 times or more and 0.8 times or less, with respect to the channel width W.
  • the outline (planar shape) of the opening 162 viewed from the Z direction is shown as a circle, but the shape is not limited to this.
  • the outline of the opening 162 viewed from the Z direction may be elliptical (see FIG. 3C) or rectangular (see FIG. 3D).
  • FIG. 3D shows a rectangle with curved corners.
  • the outline of the opening 162 viewed from the Z direction may have a shape including one or both of a straight part and a curved part (see FIG. 3E).
  • the opening 162 is preferably fine.
  • the maximum width of the opening 162 (the maximum diameter if the opening 162 is circular) as viewed from the Z direction is preferably 60 nm or less, more preferably 50 nm or less, even more preferably 40 nm or less, and extremely preferably 30 nm or less.
  • the maximum width of the opening 162 viewed from the Z direction may be 20 nm or less.
  • the minimum width of the opening 162 (minimum diameter when the opening 162 is circular) as viewed from the Z direction is preferably 1 nm or more, more preferably 5 nm or more. In order to form such a minute opening 162, it is preferable to use a lithography method using short wavelength light such as EUV light or an electron beam.
  • FIG. 5A and 5B show an example of a planar layout in which semiconductor devices 10A are arranged in a matrix.
  • FIG. 5A shows a region where conductive layers 168 and openings 162 (semiconductor device 10A) are arranged alternately along the X direction, a region where conductive layers 168 are repeatedly arranged along the Y direction, and an opening along the Y direction.
  • This is a planar layout in which a region in which 162 (semiconductor devices 10A) are repeatedly arranged is generated.
  • the conductive layer 168 and the opening 162 overlap when viewed from the X direction.
  • FIG. 5B shows a region where the conductive layer 168 is repeatedly arranged along the X direction, a region where the opening 162 (semiconductor device 10A) is repeatedly arranged along the X direction, and a region where the conductive layer 168 is repeatedly arranged along the Y direction.
  • This is a planar layout in which there are regions where the openings 162 (semiconductor device 10A) are repeatedly arranged along the Y direction.
  • the conductive layer 168 and the opening 162 are arranged diagonally. Further, in FIG. 5B, the conductive layer 161 that electrically connects the conductive layer 168 and the semiconductor device 10A is arranged obliquely. That is, when viewed from the Z direction, the straight line connecting the center of the conductive layer 168 and the center of the opening 162 is neither perpendicular to the X direction nor perpendicular to the Y direction.
  • the semiconductor device 10A may be arranged efficiently. Therefore, the degree of integration of the semiconductor device 10A may be improved, and the storage capacity per unit area of the storage device including the semiconductor device 10A may be increased.
  • FIG. 6A and 6B show a semiconductor device 10B that is a modification of the semiconductor device 10A.
  • FIG. 6A is a top view of the semiconductor device 10B.
  • FIG. 6B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 6A.
  • FIG. 6C is a cross-sectional view of the portion indicated by the dashed line A3-A4 in FIG. 6A.
  • the taper angle ⁇ of the side surface of the opening 162 can be increased without increasing the area occupied by the semiconductor device 10B.
  • the coverage of the semiconductor layer 163, the insulating layer 164, and the conductive layer 165 can be improved.
  • the conductive layer 165 within the opening 162 may become thinner toward the bottom of the opening 162.
  • Such a shape of the conductive layer 165 is sometimes called “acicular” or “conical”.
  • FIG. 7A and 7B show a semiconductor device 10C that is a modification of the semiconductor device 10A.
  • FIG. 7A is a top view of the semiconductor device 10C.
  • FIG. 7B is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 7A.
  • FIG. 7C is a cross-sectional view of the portion indicated by the dashed line A3-A4 in FIG. 7A.
  • the side surface of the opening 162 is not provided with a taper angle. If there is no problem in covering the semiconductor layer 163, the insulating layer 164, and the conductive layer 165, the side surfaces of the opening 162 may be vertical or substantially vertical. By making the side surfaces of the opening 162 vertical or substantially vertical, the area occupied by the transistor 100 can be reduced. Therefore, the area occupied by the semiconductor device including the transistor 100 can be reduced.
  • FIG. 8A and 8B show a semiconductor device 10D that is a modification of the semiconductor device 10C.
  • FIG. 8A is a top view of the semiconductor device 10D.
  • FIG. 8B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 8A.
  • FIG. 8C is a cross-sectional view of the portion indicated by the dashed line A3-A4 in FIG. 8A.
  • a semiconductor device 10D shown in FIG. 8 has a configuration in which the conductive layer 155 is removed from the semiconductor device 10A. By not providing the conductive layer 155, the manufacturing process of the semiconductor device 10D is shorter than that of the semiconductor device 10A, and productivity can be improved. Note that in the semiconductor device 10D, a portion of the semiconductor layer 163 functions as one electrode of the capacitive element 110. Specifically, at the bottom of the opening 162, a region of the semiconductor layer 163 that overlaps with the insulating layer 154 and the conductive layer 151 functions as one electrode of the capacitive element 110.
  • FIG. 9A is a cross-sectional view showing a configuration example in which two semiconductor devices 10A (semiconductor device 10Aa and semiconductor device 10Ab) are electrically connected to one wiring BL (conductive layer 168 and conductive layer 152).
  • FIG. 9B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 9A, viewed from the Y direction.
  • FIG. 9C is an equivalent circuit diagram of the cross-sectional view shown in FIG. 9B.
  • Semiconductor device 10Aa is electrically connected to wiring WLa, wiring PLa, and wiring BL.
  • Semiconductor device 10Ab is electrically connected to wiring WLb, wiring PLb, and wiring BL.
  • the conductive layer 165 included in the semiconductor device 10Aa functions as part of the wiring WLa.
  • the conductive layer 151 included in the semiconductor device 10Aa functions as a wiring PLa.
  • the conductive layer 165 included in the semiconductor device 10Ab functions as part of the wiring WLb.
  • the conductive layer 151 included in the semiconductor device 10Ab functions as the wiring PLb.
  • the conductive layer 165 extending in the Y direction can be used as the conductive layer 165 of a plurality of semiconductor devices 10A arranged in the Y direction (see FIG. 9A).
  • the conductive layer 165 of the semiconductor device 10Aa may be electrically connected to the conductive layer 165 of another semiconductor device 10Aa arranged in the Y direction.
  • the conductive layer 151 extending in the Y direction can be used as the conductive layer 151 of a plurality of semiconductor devices 10A arranged in the Y direction.
  • the conductive layer 151 of the semiconductor device 10Aa may be electrically connected to the conductive layer 151 of another semiconductor device 10Aa arranged in the Y direction.
  • ⁇ Modification 5> By stacking the plurality of semiconductor devices 10A, the area occupied by the semiconductor devices 10A can be reduced. For example, by stacking two semiconductor devices 10A, the area occupied by each semiconductor device 10A is halved.
  • FIG. 10 is a cross section showing a configuration example in which four semiconductor devices 10A (semiconductor device 10A[1], semiconductor device 10A[2], semiconductor device 10A[3], and semiconductor device 10A[4]) are stacked in the Z direction. It is a diagram.
  • FIG. 11 is an equivalent circuit diagram of the stacked structure example shown in FIG. 10.
  • the semiconductor device 10A formed in the first layer is indicated as a semiconductor device 10A[1]
  • the semiconductor device 10A formed in the second layer is indicated as a semiconductor device 10A[2]
  • the semiconductor device 10A formed in the third layer is indicated as a semiconductor device 10A[2].
  • the semiconductor device 10A formed in the fourth layer is indicated as a semiconductor device 10A[3], and the semiconductor device 10A formed in the fourth layer is indicated as a semiconductor device 10A[4].
  • the first layer is referred to as a "first layer”
  • the second layer is referred to as a "second layer”
  • the third layer is referred to as a "third layer”
  • the fourth layer is referred to as a "fourth layer.”
  • layers sometimes called "layers”.
  • the semiconductor device 10A[1] is electrically connected to the wiring WL[1], the wiring PL[1], and the wiring BL (see FIG. 11).
  • the semiconductor device 10A[2] is electrically connected to the wiring WL[2], the wiring PL[2], and the wiring BL.
  • the semiconductor device 10A[3] is electrically connected to the wiring WL[3], the wiring PL[3], and the wiring BL.
  • the semiconductor device 10A[4] is electrically connected to the wiring WL[4], the wiring PL[4], and the wiring BL.
  • the conductive layer 165 included in the semiconductor device 10A[1] is electrically connected to the wiring WL[1]. Further, the conductive layer 165 included in the semiconductor device 10A[1] may function as the wiring WL[1] or a part of the wiring WL[1].
  • the conductive layer 151 included in the semiconductor device 10A[1] is electrically connected to the wiring PL[1]. Furthermore, the conductive layer 151 included in the semiconductor device 10A[1] may function as the wiring PL[1] or a part of the wiring PL[1].
  • the conductive layer 165 included in the semiconductor device 10A[2] is electrically connected to the wiring WL[2]. Further, the conductive layer 165 included in the semiconductor device 10A[2] may function as the wiring WL[2] or a part of the wiring WL[2].
  • the conductive layer 151 included in the semiconductor device 10A[2] is electrically connected to the wiring PL[2]. Furthermore, the conductive layer 151 included in the semiconductor device 10A[2] may function as the wiring PL[2] or a part of the wiring PL[2].
  • the conductive layer 165 included in the semiconductor device 10A[3] is electrically connected to the wiring WL[3]. Further, the conductive layer 165 included in the semiconductor device 10A[3] may function as the wiring WL[3] or a part of the wiring WL[3].
  • the conductive layer 151 included in the semiconductor device 10A[3] is electrically connected to the wiring PL[3]. Further, the conductive layer 151 included in the semiconductor device 10A[3] may function as the wiring PL[3] or a part of the wiring PL[3].
  • the conductive layer 165 included in the semiconductor device 10A[4] is electrically connected to the wiring WL[4]. Further, the conductive layer 165 included in the semiconductor device 10A[4] may function as the wiring WL[4] or a part of the wiring WL[4].
  • the conductive layer 151 included in the semiconductor device 10A[4] is electrically connected to the wiring PL[4]. Further, the conductive layer 151 included in the semiconductor device 10A[4] may function as the wiring PL[4] or a part of the wiring PL[4].
  • a semiconductor device 10A[2] is provided on the semiconductor device 10A[1]
  • a semiconductor device 10A[3] is provided on the semiconductor device 10A[2]
  • a semiconductor device 10A[3] is provided on the semiconductor device 10A[3].
  • a device 10A[4] is provided.
  • Each of semiconductor devices 10A[1] to 10A[4] shown in FIG. 10 includes a conductive layer 152 and a conductive layer 168. The conductive layer 168 of each of the semiconductor devices 10A[1] to 10A[4] shown in FIG. connected.
  • the conductive layer 152 of the semiconductor device 10A[1] is electrically connected to the conductive layer 152 of the semiconductor device 10A[2] via the conductive layer 168 of the semiconductor device 10A[1]. connected to. Further, the conductive layer 152 of the semiconductor device 10A[2] is electrically connected to the conductive layer 152 of the semiconductor device 10A[3] via the conductive layer 168 of the semiconductor device 10A[2]. Furthermore, the conductive layer 152 of the semiconductor device 10A[3] is electrically connected to the conductive layer 152 of the semiconductor device 10A[4] via the conductive layer 168 of the semiconductor device 10A[3]. As shown in FIG.
  • the plurality of conductive layers 168 and the plurality of conductive layers 152 are electrically connected to function as one electrode extending in the Z direction.
  • the plurality of conductive layers 168 and the plurality of conductive layers 152 function as one wiring BL.
  • the transistors 100 included in each of the semiconductor devices 10A[1] to 10A[4] are electrically connected to the wiring BL. Specifically, one of the source or drain of the transistor 100 included in the semiconductor device 10A[1], one of the source or drain of the transistor 100 included in the semiconductor device 10A[2], and one of the source or drain of the transistor 100 included in the semiconductor device 10A[3]. One of the source or drain and one of the source or drain of the transistor 100 included in the semiconductor device 10A[4] are electrically connected to the wiring BL.
  • the area occupied by the semiconductor devices including the semiconductor device 10A can be reduced. Further, by providing a plurality of semiconductor devices 10A one on top of the other in the Z direction, the area occupied by the semiconductor devices 10A can be reduced. Therefore, the area occupied by semiconductor devices including the semiconductor device 10A can be further reduced. Further, by providing a plurality of semiconductor devices 10A in an overlapping manner in the Z direction, it is possible to increase the storage capacity per unit area of a storage device including the semiconductor devices 10A.
  • FIG. 12 is a cross-sectional view showing an example of a stacked structure of a plurality of semiconductor devices 10A.
  • FIG. 13 is an equivalent circuit diagram of the configuration example shown in FIG. 12. Note that in FIGS. 12 and 13, two semiconductor devices 10A (semiconductor device 10Aa and semiconductor device 10Ab) formed on the same plane are considered as one set, and one set of semiconductor devices 10A is referred to as four layers (or "stages"). ) This shows an example of overlapping.
  • the semiconductor device 10Aa included in the first layer is shown as a semiconductor device 10Aa[1], and the semiconductor device 10Ab is shown as a semiconductor device 10Ab[1].
  • the semiconductor device 10Aa included in the second layer is indicated as a semiconductor device 10Aa[2], and the semiconductor device 10Ab is indicated as a semiconductor device 10Ab[2].
  • the semiconductor device 10Aa included in the third layer is shown as a semiconductor device 10Aa[3], and the semiconductor device 10Ab is shown as a semiconductor device 10Ab[3].
  • the semiconductor device 10Aa included in the fourth layer is indicated as a semiconductor device 10Aa[4], and the semiconductor device 10Ab is indicated as a semiconductor device 10Ab[4].
  • the semiconductor device 10Aa[1] is electrically connected to the wiring WLa[1], the wiring PLa[1], and the wiring BL (see FIG. 13).
  • Semiconductor device 10Ab[1] is electrically connected to wiring WLb[1], wiring PLb[1], and wiring BL.
  • Semiconductor device 10Aa[2] is electrically connected to wiring WLa[2], wiring PLa[2], and wiring BL.
  • Semiconductor device 10Ab[2] is electrically connected to wiring WLb[2], wiring PLb[2], and wiring BL.
  • Semiconductor device 10Aa[3] is electrically connected to wiring WLa[3], wiring PLa[3], and wiring BL.
  • Semiconductor device 10Ab[3] is electrically connected to wiring WLb[3], wiring PLb[3], and wiring BL.
  • Semiconductor device 10Aa[4] is electrically connected to wiring WLa[4], wiring PLa[4], and wiring BL.
  • Semiconductor device 10Ab[4] is electrically connected to wiring WLb[4], wiring PLb[4], and wiring BL.
  • the area occupied by the semiconductor devices including the semiconductor device 10A can be further reduced. Furthermore, the storage capacity per unit area of the storage device including the semiconductor device 10A can be increased.
  • FIG. 14A shows an equivalent circuit diagram of the semiconductor device 10.
  • the semiconductor device 10 shown in FIG. 14A functions as a DRAM type (1Tr1C type) storage element (memory cell) having one transistor M and one capacitive element Cfe.
  • the capacitive element Cfe is a ferroelectric capacitor having a material capable of having ferroelectricity as a dielectric layer between two electrodes. Therefore, the semiconductor device 10 functions as a FeRAM.
  • the transistor M shown in FIG. 14A corresponds to the transistor 100, and the capacitive element Cfe corresponds to the capacitive element 110.
  • semiconductor layer in which the channel of the transistor M is formed can be used as the semiconductor layer in which the channel of the transistor M is formed.
  • a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination.
  • the semiconductor material for example, silicon or germanium can be used.
  • compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors may be used.
  • an OS transistor has a characteristic of high dielectric strength between a source and a drain. Therefore, by using the transistor M as an OS transistor, a high voltage can be applied to the transistor M even if the transistor M is miniaturized. By miniaturizing the transistor M, the area occupied by the semiconductor device 10 can be reduced. For example, the area occupied by each semiconductor device 10 shown in FIG. 14A can be set to 1/3 to 1/6 of the area occupied by one cell of an SRAM (Static Random Access Memory). Therefore, the semiconductor devices 10 can be arranged with high density. This makes it possible to realize a storage device with a large storage capacity.
  • SRAM Static Random Access Memory
  • OS memory when an OS transistor is used as a transistor included in a memory cell, the memory cell can be referred to as an "OS memory.”
  • DOSRAM registered trademark
  • FeDOSRAM FeDOSRAM
  • the wiring WL has a function as a word line, and by controlling the potential of the wiring WL, the on state and off state of the transistor M can be controlled. For example, if the transistor M is an n-channel transistor, the transistor M is turned on by setting the potential of the wiring WL to a high potential, and the transistor M is turned off by setting the potential of the wiring WL to a low potential. It can be done.
  • the wiring BL has a function as a bit line, and when the transistor M is in an on state, the potential of the wiring BL is supplied to one electrode of the capacitive element Cfe.
  • the wiring PL has a function as a plate line.
  • the other electrode of the capacitive element Cfe is supplied with a potential via the wiring PL.
  • FIG. 14B is a graph showing an example of the hysteresis characteristic.
  • the horizontal axis indicates the voltage applied to the ferroelectric layer.
  • the voltage can be, for example, the difference between the potential of one electrode of the capacitive element Cfe and the potential of the other electrode of the capacitive element Cfe.
  • the vertical axis indicates the polarization of the ferroelectric layer, and in the case of a positive value, positive charges are biased toward one electrode side of the capacitive element Cfe, and negative charges are biased toward the other electrode side of the capacitive element Cfe. Show that you are biased.
  • the polarization has a negative value, it indicates that positive charges are biased toward the other electrode of the capacitive element Cfe, and negative charges are biased toward one electrode of the capacitive element Cfe.
  • the voltage shown on the horizontal axis of the graph in FIG. 14B may be the difference between the potential of the other electrode of the capacitive element Cfe and the potential of one electrode of the capacitive element Cfe.
  • the polarization shown on the vertical axis of the graph in FIG. 14B is set to a positive value when positive charges are biased toward the other electrode side of the capacitive element Cfe and negative charges are biased toward one electrode side of the capacitive element Cfe, A negative value may be used when positive charges are biased towards one electrode of the capacitive element Cfe and negative charges are biased towards the other electrode of the capacitive element Cfe.
  • the hysteresis characteristics of the ferroelectric layer can be represented by a curve 51 and a curve 52.
  • the voltages at the intersections of the curves 51 and 52 are defined as VSP and -VSP. It can be said that VSP and -VSP have different polarities.
  • VSP and -VSP can be said to be saturation polarization voltages.
  • VSP may be referred to as a first saturation polarization voltage
  • -VSP may be referred to as a second saturation polarization voltage.
  • FIG. 14B shows a case where the absolute value of the first saturation polarization voltage and the absolute value of the second saturation polarization voltage are equal, the absolute values thereof may be different.
  • the voltage applied to the ferroelectric layer when the polarization of the ferroelectric layer changes according to the curve 51 and the polarization of the ferroelectric layer is 0 is defined as Vc.
  • the voltage applied to the ferroelectric layer when the polarization of the ferroelectric layer is 0 is defined as -Vc.
  • Vc and -Vc can be said to be coercive voltages.
  • the value of Vc and the value of -Vc can be said to be values between -VSP and VSP.
  • Vc may be referred to as a first coercive voltage
  • -Vc may be referred to as a second coercive voltage.
  • FIG. 14B it is assumed that the absolute value of the first coercive voltage and the absolute value of the second coercive voltage are equal, but the absolute values may be different.
  • the maximum value of polarization when no voltage is applied to the ferroelectric layer is called “remanent polarization Pr”, and the minimum value is called “remanent polarization -Pr”. Further, the difference between the remanent polarization Pr and the remanent polarization -Pr is called “remanent polarization 2Pr”.
  • the voltage applied to the ferroelectric layer of the capacitive element Cfe can be expressed by the difference between the potential of one electrode of the capacitive element Cfe and the potential of the other electrode of the capacitive element Cfe.
  • the other electrode of the capacitive element Cfe is electrically connected to the wiring PL. Therefore, by controlling the potential of the wiring PL, it is possible to control the voltage applied to the ferroelectric layer of the capacitive element Cfe.
  • the voltage applied to the ferroelectric layer of the capacitive element Cfe is the potential difference between the potential of one electrode of the capacitive element Cfe and the potential of the other electrode (wiring PL) of the capacitive element Cfe.
  • the transistor M is an n-channel transistor.
  • FIG. 14C is a timing chart showing an example of a method for driving the semiconductor device 10.
  • FIG. 14C shows an example of writing and reading binary digital data into the semiconductor device 10. Specifically, in FIG. 14C, data "1" is written in the semiconductor device 10 from time T01 to time T02, read and rewritten from time T03 to time T05, read from time T11 to time T13, and the semiconductor device 10 is written. An example is shown in which data "0" is written to the semiconductor device 10, read and rewritten from time T14 to time T16, and read and data "1" is written to the semiconductor device 10 from time T17 to time T19. ing.
  • Vref is supplied as a reference potential to the sense amplifier electrically connected to the wiring BL.
  • Vref is supplied as a reference potential to the sense amplifier electrically connected to the wiring BL.
  • the potential of the wiring WL is set to a high potential.
  • transistor M is turned on.
  • the potential of the wiring BL is assumed to be Vw. Since the transistor M is in the on state, the potential of one electrode of the capacitive element Cfe becomes Vw. Further, the potential of the wiring PL is set to GND. From the above, the voltage applied to the ferroelectric layer of the capacitive element Cfe becomes "Vw-GND". Thereby, data "1" can be written into the semiconductor device 10. Therefore, it can be said that the period from time T01 to time T02 is a period during which a write operation is performed.
  • Vw is preferably equal to or greater than VSP, for example, preferably equal to VSP.
  • GND is a ground potential in this specification and the like, it does not necessarily have to be a ground potential as long as the semiconductor device 10 can be driven to satisfy the purpose of one embodiment of the present invention. For example, if the absolute value of the first saturation polarization voltage is different from the absolute value of the second saturation polarization voltage, and the absolute value of the first coercive voltage is different from the absolute value of the second coercive voltage. In this case, GND can be set to a potential other than ground.
  • the potential of the wiring BL and the potential of the wiring PL are set to GND.
  • the voltage applied to the ferroelectric layer of the capacitive element Cfe becomes 0V. Since the voltage "Vw-GND" applied to the ferroelectric layer of the capacitive element Cfe from time T01 to time T02 can be higher than VSP, the voltage "Vw-GND” applied to the ferroelectric layer of the capacitive element Cfe from time T02 to time T03 is The amount of polarization changes according to curve 52 shown in FIG. 14B. As described above, polarization reversal does not occur in the ferroelectric layer of the capacitive element Cfe between time T02 and time T03.
  • the potential of the wiring WL is set to a low potential. This turns transistor M off. As described above, the write operation is completed and data "1" is held in the semiconductor device 10.
  • the potentials of the wiring BL and the wiring PL are such that polarization reversal does not occur in the ferroelectric layer of the capacitive element Cfe, that is, the voltage applied to the ferroelectric layer of the capacitive element Cfe is the second coercive voltage. Any potential can be used as long as it is equal to or higher than Vc.
  • the potential of the wiring WL is set to a high potential.
  • transistor M is turned on.
  • the potential of the wiring PL is assumed to be Vw.
  • the voltage applied to the ferroelectric layer of the capacitive element Cfe becomes "GND-Vw".
  • the voltage applied to the ferroelectric layer of the capacitive element Cfe from time T01 to time T02 is "Vw-GND”. Therefore, polarization inversion occurs in the ferroelectric layer of the capacitive element Cfe.
  • a current flows through the wiring BL, and the potential of the wiring BL becomes higher than Vref.
  • time T03 to time T04 can be said to be a period in which a read operation is performed.
  • Vref is assumed to be higher than GND and lower than Vw, it may be higher than Vw, for example.
  • time T04 to time T05 is a period in which a rewriting operation is performed.
  • the potential of the wiring BL and the potential of the wiring PL are set to GND. After that, the potential of the wiring WL is set to a low potential. With the above, the rewrite operation is completed and data "1" is held in the semiconductor device 10.
  • the potential of the wiring WL is set to a high potential, and the potential of the wiring PL is set to Vw. Since the data “1” is held in the semiconductor device 10, the potential of the wiring BL becomes higher than Vref, and the data “1” held in the semiconductor device 10 is read out. Therefore, it can be said that the period from time T11 to time T12 is a period in which a read operation is performed.
  • time T12 to time T13 the potential of the wiring BL is set to GND. Since the transistor M is in the on state, the potential of one electrode of the capacitive element Cfe becomes GND. Further, the potential of the wiring PL is assumed to be Vw. From the above, the voltage applied to the ferroelectric layer of the capacitive element Cfe becomes "GND-Vw". Thereby, data "0" can be written into the semiconductor device 10. Therefore, it can be said that time T12 to time T13 is a period in which a write operation is performed.
  • the potential of the wiring BL and the potential of the wiring PL are set to GND.
  • the voltage applied to the ferroelectric layer of the capacitive element Cfe becomes 0V. Since the voltage "GND-Vw" applied to the ferroelectric layer of the capacitive element Cfe from time T12 to time T13 can be set to -VSP or less, the voltage "GND-Vw” applied to the ferroelectric layer of the capacitive element Cfe from time T13 to time T14 is The amount of polarization changes according to a curve 51 shown in FIG. 14B. As described above, polarization reversal does not occur in the ferroelectric layer of the capacitive element Cfe between time T13 and time T14.
  • the potential of the wiring WL is set to a low potential. This turns transistor M off.
  • the write operation is completed and data "0" is held in the semiconductor device 10.
  • the potentials of the wiring BL and the wiring PL are such that polarization reversal does not occur in the ferroelectric layer of the capacitive element Cfe, that is, the voltage applied to the ferroelectric layer of the capacitive element Cfe is a first coercive voltage Vc. Any potential can be used as long as it is below.
  • the potential of the wiring WL is set to a high potential.
  • transistor M is turned on.
  • the potential of the wiring PL is assumed to be Vw.
  • the voltage applied to the ferroelectric layer of the capacitive element Cfe becomes "GND-Vw".
  • the voltage applied to the ferroelectric layer of the capacitive element Cfe from time T12 to time T13 is "GND-Vw”. Therefore, polarization reversal does not occur in the ferroelectric layer of the capacitive element Cfe.
  • the bit line driver circuit can read data "0" held in the semiconductor device 10. Therefore, it can be said that time T14 to time T15 is a period in which a read operation is performed.
  • the period from time T15 to time T16 is a period in which a rewriting operation is performed.
  • the potential of the wiring BL and the potential of the wiring PL are set to GND. After that, the potential of the wiring WL is set to a low potential. With the above, the rewrite operation is completed and data "0" is held in the semiconductor device 10.
  • time T17 to time T18 the potential of the wiring WL is set to a high potential, and the potential of the wiring PL is set to Vw. Since the data "0" is held in the semiconductor device 10, the potential of the wiring BL becomes lower than Vref, and the data "0" held in the semiconductor device 10 is read out. Therefore, it can be said that time T17 to time T18 is a period in which a read operation is performed.
  • time T18 to time T19 the potential of the wiring BL is set to Vw. Since the transistor M is in the on state, the potential of one electrode of the capacitive element Cfe becomes Vw. Further, the potential of the wiring PL is set to GND. From the above, the voltage applied to the ferroelectric layer of the capacitive element Cfe becomes "Vw-GND". Thereby, data "1" can be written into the semiconductor device 10. Therefore, time T18 to time T19 can be said to be a period in which a write operation is performed.
  • the potential of the wiring BL and the potential of the wiring PL are set to GND. After that, the potential of the wiring WL is set to a low potential. As described above, the write operation is completed and data "1" is held in the semiconductor device 10.
  • the semiconductor device 10 using a ferroelectric layer for the capacitive element Cfe functions as a nonvolatile memory element that can retain written information even if power supply is stopped.
  • DRAM Dynamic Random Access Memory
  • a memory element or a memory circuit including a ferroelectric layer is sometimes referred to as a "ferroelectric memory” or "FE memory.” Therefore, the semiconductor device 10 is both a ferroelectric memory and an FE memory.
  • the FE memory can be expected to achieve a rewriting frequency of 1 ⁇ 10 10 or more, preferably 1 ⁇ 10 12 or more, more preferably 1 ⁇ 10 15 or more. Furthermore, the FE memory can be expected to achieve an operating frequency of 10 MHz or higher, preferably 1 GHz or higher.
  • FE memory can be expected to have a memory retention period of 10 days or more, preferably 1 year or more, and more preferably 10 years or more at an environmental temperature of 150° C. or 200° C.
  • the FE memory can also be applied to cache memories and registers of CPUs (Central Processing Units), GPUs (Graphics Processing Units), and the like.
  • CPUs Central Processing Units
  • GPUs Graphics Processing Units
  • the FE memory can also be applied to cache memories and registers of CPUs (Central Processing Units), GPUs (Graphics Processing Units), and the like.
  • an off-CPU Normally off CPU
  • Noff-GPU Normally off GPU
  • FIG. 15A shows a block diagram illustrating a configuration example of a storage device 300 according to one embodiment of the present invention.
  • the storage device 300 shown in FIG. 15A includes a drive circuit 21 and a memory array 20.
  • Memory array 20 includes a plurality of semiconductor devices 10.
  • FIG. 15A shows an example in which the memory array 20 includes a plurality of semiconductor devices 10 arranged in a matrix of m rows and n columns (m and n are integers of 2 or more).
  • the rows and columns extend in directions perpendicular to each other.
  • the Y direction is defined as a "row” and the X direction is defined as a "column,” but the Y direction may be defined as a "column” and the X direction may be defined as a "row.”
  • the semiconductor device 10 in the first row and first column is shown as a semiconductor device 10[1,1] and the semiconductor device 10 in the mth row and nth column is shown as a semiconductor device 10[m,n].
  • the semiconductor device 10 in the mth row and nth column is shown as a semiconductor device 10[m,n].
  • i line when indicating an arbitrary line, it may be written as i line.
  • column j when indicating an arbitrary column, it may be written as column j. Therefore, i is an integer of 1 or more and m or less, and j is an integer of 1 or more and n or less.
  • the semiconductor device 10 in the i-th row and j-th column is referred to as a semiconductor device 10[i,j].
  • the memory array 20 also includes m wires WL extending in the row direction (Y direction), m wires PL extending in the row direction (Y direction), and n wires extending in the Z direction.
  • a wiring BL is provided. Note that although the n wires BL extend in the Z direction, in order to make it easier to understand the relationship between the wires WL, the wires PL, and the wires BL, in FIG. 15A, the n wires BL extend in the column direction (X direction). It is shown as follows.
  • the wiring WL provided in the first (first row) is referred to as wiring WL[1], and the wiring WL provided in m-th (m-th row) is referred to as wiring WL[m]. .
  • the first wiring PL (first row) is designated as wiring PL[1]
  • the mth wiring PL (mth row) is designated as wiring PL[m].
  • the wiring BL provided in the first (first column) is referred to as wiring BL[1]
  • the wiring BL provided in the nth (nth column) is referred to as wiring BL[n].
  • the plurality of semiconductor devices 10 provided in the i-th row are electrically connected to the i-th wiring WL (wiring WL[i]) and the i-th wiring PL (wiring PL[i]).
  • the plurality of semiconductor devices 10 provided in the j-th column are electrically connected to the wiring BL (wiring BL[j]) in the j-th column.
  • the drive circuit 21 includes a PSW 22 (power switch), a PSW 23, and a peripheral circuit 31.
  • the peripheral circuit 31 includes a peripheral circuit 41, a control circuit 32, and a voltage generation circuit 33.
  • each circuit, each signal, and each voltage can be removed or discarded as necessary. Alternatively, other circuits or other signals may be added.
  • Signal BW, signal CE, signal GW, signal CLK, signal WAKE, signal ADDR, signal WDA, signal PON1, and signal PON2 are input signals from the outside, and signal RDA is an output signal to the outside.
  • Signal CLK is a clock signal.
  • signal BW, the signal CE, and the signal GW are control signals.
  • Signal CE is a chip enable signal
  • signal GW is a global write enable signal
  • signal BW is a byte write enable signal.
  • Signal ADDR is an address signal.
  • Signal WDA is write data
  • signal RDA is read data.
  • Signal PON1 and signal PON2 are power gating control signals. Note that the signal PON1 and the signal PON2 may be generated by the control circuit 32.
  • the control circuit 32 is a logic circuit that has a function of controlling the overall operation of the storage device 300. For example, the control circuit performs a logical operation on the signal CE, the signal GW, and the signal BW to determine the operation mode (eg, write operation, read operation) of the storage device 300. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.
  • the control circuit performs a logical operation on the signal CE, the signal GW, and the signal BW to determine the operation mode (eg, write operation, read operation) of the storage device 300.
  • the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.
  • the voltage generation circuit 33 has a function of generating voltage.
  • the signal WAKE has a function of controlling input of the signal CLK to the voltage generation circuit 33. For example, when an H level signal is applied to the signal WAKE, the signal CLK is input to the voltage generation circuit 33, and the voltage generation circuit 33 generates a voltage.
  • the peripheral circuit 41 is a circuit for writing and reading data to and from the semiconductor device 10.
  • the peripheral circuit 41 includes a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, and an output circuit 48 ( It has an Output Cir.) and a sense amplifier 46 (Sense Amplifier).
  • Row decoder 42 and column decoder 44 have the function of decoding signal ADDR.
  • the row decoder 42 is a circuit for specifying a row to be accessed
  • the column decoder 44 is a circuit for specifying a column to be accessed.
  • the row driver 43 has a function of selecting the wiring WL specified by the row decoder 42.
  • the column driver 45 has a function of writing data into the semiconductor device 10, a function of reading data from the semiconductor device 10, a function of holding the read data, and the like.
  • Input circuit 47 has a function of holding signal WDA.
  • the data held by the input circuit 47 is output to the column driver 45.
  • the output data of the input circuit 47 is the data (Din) to be written into the semiconductor device 10.
  • the data (Dout) read from the semiconductor device 10 by the column driver 45 is output to the output circuit 48.
  • the output circuit 48 has a function of holding Dout. Further, the output circuit 48 has a function of outputting Dout to the outside of the storage device 300.
  • the data output from the output circuit 48 is the signal RDA.
  • the PSW 22 has a function of controlling the supply of VDD to the peripheral circuit 31.
  • the PSW 23 has a function of controlling the supply of VHM to the row driver 43.
  • the high power supply voltage of the storage device 300 is VDD
  • the low power supply voltage is GND (ground potential).
  • VHM is a high power supply voltage used to bring the word line to a high level, and is higher than VDD.
  • the signal PON1 controls the on/off of the PSW22
  • the signal PON2 controls the on/off of the PSW23.
  • the number of power domains to which VDD is supplied is one, but the number may be plural. In this case, a power switch may be provided for each power domain.
  • the drive circuit 21 and the memory array 20 may be provided on the same plane. Furthermore, as shown in FIG. 15B, a layer containing the memory array 20 may be provided directly above the layer containing the drive circuit 21. By overlapping the drive circuit 21 and the memory array 20, the signal propagation distance between the drive circuit 21 and the memory array 20 can be shortened. Therefore, resistance and parasitic capacitance between drive circuit 21 and memory array 20 are reduced, and power consumption and signal delay can be reduced. Furthermore, the storage device 300 can be made smaller.
  • FIG. 15B one layer of the memory array 20 is provided on the drive circuit 21, but a plurality of layers of memory arrays 20 may be provided on the drive circuit 21.
  • FIG. 15C shows an example in which k-layer (k is an integer of 2 or more) memory arrays 20 are stacked on the drive circuit 21.
  • the memory array 20 provided in the first layer is indicated as memory array 20[1]
  • the memory array 20 provided in the second layer is indicated as memory array 20[2]
  • the memory array 20 provided in the kth layer is indicated as memory array 20[2].
  • the memory array 20 thus obtained is designated as memory array 20[k].
  • FIG. 16A shows a schematic diagram illustrating a configuration example of the storage device 300.
  • a memory device 300 shown in FIG. 16A has a six-layer memory array 20 provided on a drive circuit 21.
  • the memory array 20 provided in the third layer is indicated as memory array 20[3]
  • the memory array 20 provided in the fourth layer is indicated as memory array 20[4]
  • the memory array 20 provided in the fifth layer is indicated as memory array 20[5]
  • the memory array 20 provided in the sixth layer is indicated as memory array 20[6].
  • the memory array 20 in each layer includes a plurality of semiconductor devices 10 arranged in a matrix, and a wiring WL and a wiring PL extending in the Y direction. Note that in order to make the drawing easier to read, the wiring WL and wiring PL included in each of the first to fifth memory arrays 20 are omitted.
  • the storage device 300 shown in FIG. 16A has a plurality of wirings BL extending in the Z direction.
  • the wiring BL is formed through each of the six layers of memory arrays 20 and electrically connected to the drive circuit 21.
  • the plurality of wirings BL are arranged in a matrix.
  • connection distance between the semiconductor device 10 and the drive circuit 21 can be made shorter than when the wiring BL is extended in the X or Y direction. Can be shortened. Therefore, since the signal propagation distance between the semiconductor device 10 and the drive circuit 21 is shortened, the operating speed of the memory device can be increased. Furthermore, since the parasitic capacitance attached to the wiring BL is reduced, power consumption can be reduced.
  • each of the memory arrays 20 in each layer one of the plurality of semiconductor devices 10 included in the memory array 20 is electrically connected to one of the plurality of wirings BL. Therefore, in the memory device 300 shown in FIG. 16A, a total of six semiconductor devices 10, one from each layer of the memory array 20, are electrically connected to one wiring BL.
  • a configuration in which a plurality of memory cells (semiconductor devices 10) are electrically connected to one wiring BL is also referred to as a "memory string.” Therefore, it can be said that the storage device 300 shown in FIG. 16A is configured to include a plurality of memory strings.
  • FIG. 16B shows a schematic diagram of a memory string included in the storage device 300 shown in FIG. 16A. Note that in order to make the drawing easier to read, the wiring WL and wiring PL electrically connected to the semiconductor device 10 are omitted in the schematic diagram of the memory string shown in FIG. 16B. Further, a part of the equivalent circuit of the memory string is added to FIG. 16B.
  • FIG. 17A shows a schematic diagram illustrating a configuration example of the storage device 300.
  • the storage device 300 shown in FIG. 17A is a modification of the storage device 300 shown in FIG. 16A. Therefore, in order to reduce the repetition of explanation, mainly the points different from the storage device 300 shown in FIG. 16A will be explained.
  • each of the memory arrays 20 in each layer two of the plurality of semiconductor devices 10 included in the memory array 20 are electrically connected to one of the plurality of wirings BL. This is different from the storage device 300 shown in FIG. That is, a total of 12 semiconductor devices 10 are electrically connected to one wiring BL.
  • FIG. 17B shows a schematic diagram of a memory string included in the storage device 300 shown in FIG. 17A. Further, a part of the equivalent circuit of the memory string is added to FIG. 17B.
  • the number of wirings BL can be reduced more than in the storage device 300 shown in FIG. 16A. Therefore, the area occupied by the storage device 300 is reduced.
  • the semiconductor device 10 is an FE memory, and can retain written information for a long period of time even if power supply is stopped. Furthermore, since the refresh operation required in DRAM is not required, a storage device 300 with low power consumption can be realized.
  • FIG. 18 shows an example of a cross-sectional configuration of a storage device 300 according to one embodiment of the present invention.
  • a memory device 300 shown in FIG. 18 has a k-layer memory array 20 above a drive circuit 21.
  • the configuration shown in FIGS. 11 and 17 is illustrated as the k-layer memory array 20.
  • explanation of the k-layer memory array 20 will be omitted here.
  • FIG. 18 illustrates a transistor 400 included in the drive circuit 21.
  • the transistor 400 is provided over a substrate 311 and includes a conductive layer 316 that functions as a gate, an insulating layer 315 that functions as a gate insulator, a semiconductor region 313 that is a part of the substrate 311, and a low layer that functions as a source region or a drain region. It has a resistance region 314a and a low resistance region 314b.
  • the transistor 400 may be either a p-channel transistor or an n-channel transistor.
  • the substrate 311 for example, a single crystal silicon substrate can be used.
  • a semiconductor region 313 (a part of the substrate 311) in which a channel is formed has a convex shape.
  • a conductive layer 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulating layer 315 interposed therebetween.
  • the conductive layer 316 may be formed using a material that adjusts the work function.
  • Such a transistor 400 is also called a FIN type transistor because it utilizes a convex portion of a semiconductor substrate.
  • an insulator may be provided in contact with the upper portion of the convex portion to function as a mask for forming the convex portion.
  • a semiconductor film having a convex shape may be formed by processing an SOI (Silicon on Insulator) substrate.
  • transistor 400 illustrated in FIG. 18 is an example, and the structure is not limited, and an appropriate transistor may be used depending on the circuit configuration or driving method.
  • a wiring layer including an interlayer film, wiring, plug, etc. may be provided between each structure. Further, a plurality of wiring layers can be provided depending on the design. Further, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.
  • an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are sequentially stacked and provided as interlayer films. Further, a conductive layer 328, a conductive layer 330, and the like that are electrically connected to the conductive layer 152 are embedded in the insulating layer 320, the insulating layer 322, the insulating layer 324, and the insulating layer 326. Note that the conductive layer 328 and the conductive layer 330 function as a contact plug or a wiring.
  • the insulator that functions as an interlayer film may function as a flattening film that covers the uneven shape below it.
  • the upper surface of the insulating layer 322 may be subjected to CMP treatment or the like to improve flatness.
  • a wiring layer may be provided over the insulating layer 326 and the conductive layer 330.
  • an insulating layer 350, an insulating layer 352, and an insulating layer 354 are sequentially stacked on an insulating layer 326 and a conductive layer 330.
  • a conductive layer 356 is formed on the insulating layer 350, the insulating layer 352, and the insulating layer 354.
  • the conductive layer 356 functions as a contact plug or a wiring.
  • Conductive layer 356 is electrically connected to conductive layer 152.
  • This embodiment mode describes a metal oxide (hereinafter also referred to as an oxide semiconductor) that can be used for the OS transistor described in the above embodiment mode.
  • the metal oxide used in the OS transistor preferably contains at least indium or zinc, more preferably indium and zinc.
  • metal oxides include indium and M (M is gallium, aluminum, yttrium, tin, silicon, boron, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium). , hafnium, tantalum, tungsten, magnesium, and cobalt) and zinc.
  • M is preferably one or more selected from gallium, aluminum, yttrium, antimony, and tin, with gallium being more preferred.
  • Metal oxides can be produced by chemical vapor deposition (CVD) methods such as sputtering, metal organic chemical vapor deposition (MOCVD), or atomic layer deposition (AL).
  • CVD chemical vapor deposition
  • MOCVD metal organic chemical vapor deposition
  • A atomic layer deposition
  • D Atomic Layer Deposition
  • oxides containing indium (In), gallium (Ga), and zinc (Zn) will be described as examples of metal oxides.
  • an oxide containing indium (In), gallium (Ga), and zinc (Zn) may be referred to as an In-Ga-Zn oxide.
  • the crystal structures of oxide semiconductors include amorphous (including completely amorphous), CAAC (c-axis-aligned crystalline), nc (nanocrystalline), CAC (cloud-aligned composite), and single crystal ( single crystal), and polycrystalline (poly crystal), etc.
  • the crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum.
  • XRD X-ray diffraction
  • it can be evaluated using an XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement.
  • GIXD Gram-Incidence XRD
  • the GIXD method is also referred to as a thin film method or Seemann-Bohlin method.
  • the XRD spectrum obtained by GIXD measurement may be simply referred to as an XRD spectrum.
  • the shape of the peak in the XRD spectrum is approximately symmetrical.
  • the peak shape of the XRD spectrum is asymmetrical.
  • the fact that the peak shape of the XRD spectrum is asymmetrical indicates the presence of crystals in the film or substrate. In other words, if the shape of the peak in the XRD spectrum is not bilaterally symmetrical, the film or substrate cannot be said to be in an amorphous state.
  • the crystal structure of a film or substrate can be evaluated based on a diffraction pattern (also referred to as a nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED).
  • a diffraction pattern also referred to as a nanobeam electron diffraction pattern
  • NBED nanobeam electron diffraction
  • the In-Ga-Zn oxide film formed at room temperature is neither single crystal nor polycrystalline, nor is it in an amorphous state, but in an intermediate state, and it cannot be concluded that it is in an amorphous state. be done.
  • oxide semiconductors may be classified into a different classification from the above.
  • oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors.
  • non-single crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS.
  • non-single crystal oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS), amorphous oxide semiconductors, and the like.
  • CAAC-OS is an oxide semiconductor that has a plurality of crystal regions, and the c-axes of the plurality of crystal regions are oriented in a specific direction.
  • the specific direction is the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film.
  • a crystal region is a region having periodicity in atomic arrangement. Note that if the atomic arrangement is regarded as a lattice arrangement, a crystal region is also a region with a uniform lattice arrangement.
  • the CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and this region may have distortion.
  • CAAC-OS is an oxide semiconductor that has c-axis orientation and no obvious orientation in the a-b plane direction.
  • each of the plurality of crystal regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm).
  • the maximum diameter of the crystal region is less than 10 nm.
  • the maximum diameter of the crystal region may be about several tens of nanometers.
  • CAAC-OS indium (In) and oxygen (hereinafter referred to as In layer), and a layer containing gallium (Ga), zinc (Zn), and oxygen (hereinafter referred to as In layer).
  • In layer a layer containing indium (In) and oxygen
  • In layer a layer containing gallium (Ga), zinc (Zn), and oxygen
  • the (Ga, Zn) layer may contain indium.
  • the In layer may contain gallium.
  • the In layer may contain zinc.
  • the layered structure is observed, for example, as a lattice image in a high-resolution TEM (Transmission Electron Microscope) image.
  • the position of the peak indicating c-axis orientation (2 ⁇ value) may vary depending on the type, composition, etc. of the metal element constituting the CAAC-OS.
  • a plurality of bright points are observed in the electron diffraction pattern of the CAAC-OS film. Note that a certain spot and another spot are observed at points symmetrical positions with the spot of the incident electron beam transmitted through the sample (also referred to as a direct spot) as the center of symmetry.
  • the lattice arrangement within the crystal region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon but may be a non-regular hexagon. Further, the above distortion may have a pentagonal, heptagonal, etc. lattice arrangement.
  • CAAC-OS clear grain boundaries cannot be confirmed even in the vicinity of strain. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction, the bond distance between atoms changes due to substitution of metal atoms, etc. It is thought that this is because of this.
  • CAAC-OS in which clear grain boundaries are not confirmed, is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor.
  • a configuration including Zn is preferable.
  • In--Zn oxide and In--Ga--Zn oxide are more suitable than In oxide because they can suppress the generation of grain boundaries.
  • CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, it can be said that in CAAC-OS, reduction in electron mobility due to grain boundaries is less likely to occur. Further, since the crystallinity of an oxide semiconductor may be reduced due to the incorporation of impurities and/or the generation of defects, CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the oxide semiconductor having CAAC-OS has stable physical properties. Therefore, an oxide semiconductor including a CAAC-OS is resistant to heat and has high reliability. Furthermore, CAAC-OS is stable even at high temperatures (so-called thermal budget) during the manufacturing process. Therefore, if CAAC-OS is used for the OS transistor, the degree of freedom in the manufacturing process can be expanded.
  • nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less).
  • the nc-OS has minute crystals.
  • the size of the microcrystal is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the microcrystal is also referred to as a nanocrystal.
  • no regularity is observed in crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film.
  • nc-OS may be indistinguishable from a-like OS and amorphous oxide semiconductor.
  • a-like OS and amorphous oxide semiconductor For example, when an nc-OS film is subjected to structural analysis using an XRD device, no peak indicating crystallinity is detected in out-of-plane XRD measurement using a ⁇ /2 ⁇ scan.
  • electron diffraction also called selected area electron diffraction
  • an electron beam with a probe diameter larger than that of nanocrystals for example, 50 nm or more
  • an nc-OS film is subjected to electron beam diffraction (also referred to as nanobeam electron diffraction) using an electron beam with a probe diameter that is close to the size of a nanocrystal or smaller than a nanocrystal (for example, from 1 nm to 30 nm)
  • An electron diffraction pattern in which a plurality of spots are observed within a ring-shaped region centered on a direct spot may be obtained.
  • the a-like OS is an oxide semiconductor having a structure between that of an nc-OS and an amorphous oxide semiconductor.
  • A-like OS has holes or low density areas. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and the CAAC-OS.
  • CAC-OS relates to material composition.
  • CAC-OS is, for example, a structure of a material in which elements constituting a metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof.
  • the metal oxide one or more metal elements are unevenly distributed, and the region having the metal element has a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or a size in the vicinity thereof.
  • the mixed state is also called a mosaic or a patch.
  • CAC-OS has a structure in which the material is separated into a first region and a second region, resulting in a mosaic shape, and the first region is distributed throughout the film (hereinafter also referred to as cloud shape). ). That is, CAC-OS is a composite metal oxide having a configuration in which the first region and the second region are mixed.
  • the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are expressed as [In], [Ga], and [Zn], respectively.
  • the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film.
  • the second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film.
  • [In] is larger than [In] in the second region
  • [Ga] is smaller than [Ga] in the second region.
  • the second region is a region in which [Ga] is larger than [Ga] in the first region, and [In] is smaller than [In] in the first region.
  • the first region is a region whose main component is indium oxide, indium zinc oxide, or the like.
  • the second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like.
  • the first region can be rephrased as a region containing In as a main component.
  • the second region can be rephrased as a region containing Ga as a main component.
  • CAC-OS in In-Ga-Zn oxide is a material composition containing In, Ga, Zn, and O, with a region mainly composed of Ga and a region mainly composed of In. Each area has a mosaic shape, and these areas exist randomly. Therefore, it is presumed that CAC-OS has a structure in which metal elements are unevenly distributed.
  • the CAC-OS can be formed, for example, by sputtering without intentionally heating the substrate.
  • one or more selected from inert gas (typically argon), oxygen gas, and nitrogen gas may be used as the film-forming gas. good.
  • the lower the flow rate ratio of oxygen gas to the total flow rate of film-forming gas during film formation the more preferable it is.
  • the flow rate ratio of oxygen gas to the total flow rate of film forming gas during film formation is set to 0% or more and less than 30%, preferably 0% or more and 10% or less.
  • EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) reveals regions mainly composed of In. It can be confirmed that the structure has a structure in which the (first region) and the region (second region) whose main component is Ga are unevenly distributed and mixed.
  • the first region is a region with higher conductivity than the second region.
  • carriers flow through the first region, thereby exhibiting conductivity as a metal oxide. Therefore, by distributing the first region in a cloud shape in the metal oxide, high field effect mobility ( ⁇ ) can be achieved.
  • the second region is a region with higher insulation than the first region. That is, by distributing the second region in the metal oxide, leakage current can be suppressed.
  • CAC-OS when CAC-OS is used in a transistor, the conductivity caused by the first region and the insulation caused by the second region act complementary to each other, thereby providing a switching function (on/off). functions) can be added to CAC-OS.
  • a part of the material has a conductive function
  • a part of the material has an insulating function
  • the entire material has a semiconductor function.
  • CAC-OS is optimal for various semiconductor devices including display devices.
  • Oxide semiconductors have a variety of structures, each with different properties.
  • the oxide semiconductor of one embodiment of the present invention includes two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS. It's okay.
  • ⁇ OS transistor> By using the metal oxide (oxide semiconductor) of one embodiment of the present invention for a transistor, a transistor with high field-effect mobility can be achieved. Furthermore, a highly reliable transistor can be realized. Further, it is possible to realize miniaturized or highly integrated transistors. For example, a transistor with a channel length of 2 nm or more and 30 nm or less can be manufactured.
  • the carrier concentration in the channel formation region of the oxide semiconductor is 1 ⁇ 10 18 cm ⁇ 3 or less, preferably 1 ⁇ 10 17 cm ⁇ 3 or less, more preferably 1 ⁇ 10 15 cm ⁇ 3 or less, more preferably 1 ⁇ It is 1013 cm -3 or less, more preferably 1x1011 cm -3 or less, even more preferably less than 1x1010 cm- 3 , and 1x10-9 cm- 3 or more. Note that in the case of lowering the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be lowered to lower the defect level density.
  • low impurity concentration and low defect level density are referred to as high purity intrinsic or substantially high purity intrinsic.
  • an oxide semiconductor with a low carrier concentration is sometimes referred to as a high-purity intrinsic oxide semiconductor or a substantially high-purity intrinsic oxide semiconductor.
  • the trap level density may also be low.
  • charges captured in trap levels of an oxide semiconductor may take a long time to disappear, and may behave as if they were fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap level density may have unstable electrical characteristics.
  • the impurity in the oxide semiconductor refers to, for example, a substance other than the main component that constitutes the oxide semiconductor.
  • an element having a concentration of less than 0.1 atomic% can be considered an impurity.
  • the band gap of the oxide semiconductor is preferably larger than the band gap of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and even more preferably 3.0 eV or more. It is.
  • the off-state current (also referred to as Ioff) of the transistor can be reduced.
  • Si transistors transistors in which silicon is used as a semiconductor layer in which a channel is formed
  • a short channel effect also referred to as SCE
  • silicon has a small band gap.
  • an OS transistor uses an oxide semiconductor, which is a semiconductor material with a large band gap, short channel effects can be suppressed.
  • an OS transistor is a transistor that has no short channel effect or has very little short channel effect.
  • the short channel effect is a deterioration in electrical characteristics that becomes apparent as transistors become smaller (reduction in channel length).
  • Specific examples of short channel effects include a decrease in threshold voltage, an increase in subthreshold swing value (sometimes referred to as S value), and an increase in leakage current.
  • the S value refers to the amount of change in gate voltage in a subthreshold region that causes a drain current to change by one order of magnitude with a constant drain voltage.
  • characteristic length is widely used as an index of resistance to short channel effects.
  • the characteristic length is an index of the bendability of the potential in the channel forming region. The smaller the characteristic length, the more steeply the potential rises, so it can be said to be resistant to short channel effects.
  • the OS transistor is an accumulation type transistor, and the Si transistor is an inversion type transistor. Therefore, compared to a Si transistor, an OS transistor has a smaller characteristic length between the source region and the channel forming region and a smaller characteristic length between the drain region and the channel forming region. Therefore, OS transistors are more resistant to short channel effects than Si transistors. That is, when it is desired to manufacture a transistor with a short channel length, an OS transistor is more suitable than a Si transistor.
  • the carrier concentration of the oxide semiconductor is lowered until the channel formation region becomes i-type or substantially i-type, conduction in the channel formation region decreases due to the conduction-band-lowering (CBL) effect in short-channel transistors. Since the lower end of the conduction band is lowered, the energy difference at the lower end of the conduction band between the source region or the drain region and the channel formation region may be reduced to 0.1 eV or more and 0.2 eV or less.
  • the OS transistor has an n + /n- / n + accumulation type junction-less transistor structure, in which the channel forming region becomes an n - type region and the source and drain regions become n + -type regions, or , n + /n ⁇ /n + storage type non-junction transistor structure.
  • the OS transistor By making the OS transistor have the above structure, it is possible to have good electrical characteristics even if the semiconductor device is miniaturized or highly integrated. For example, even if the channel length or gate length of an OS transistor is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less, and it is 1 nm or more, 3 nm or more, or 5 nm or more, good electrical characteristics can be obtained. Obtainable. On the other hand, since a short channel effect occurs in a Si transistor, it may be difficult to set the gate length to 20 nm or less or 15 nm or less. Therefore, the OS transistor can be suitably used as a transistor having a shorter channel length than a Si transistor. Note that the gate length is the length of the gate electrode in the direction in which carriers move inside the channel formation region during transistor operation.
  • the high frequency characteristics of the transistor can be improved.
  • the cutoff frequency of the transistor can be improved.
  • the cutoff frequency of the transistor can be set to 50 GHz or more, preferably 100 GHz or more, more preferably 150 GHz or more, for example in a room temperature environment.
  • OS transistors have excellent effects compared to Si transistors, such as a smaller off-state current and the ability to manufacture a transistor with a short channel length.
  • the carbon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 19 atoms /cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 18 atoms/cm 3 or less, even more preferably 1 ⁇ 10 18 atoms/cm 3 or less.
  • the silicon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, and more preferably 3 ⁇ 10 19 atoms/cm 3 or less. cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 18 atoms/cm 3 or less, even more preferably 1 ⁇ 10 18 atoms/cm 3 or less.
  • the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, and more preferably 1 ⁇ 10 19 atoms/cm 3 or less. cm 3 or less, more preferably 5 ⁇ 10 18 atoms/cm 3 or less, more preferably 1 ⁇ 10 18 atoms/cm 3 or less, still more preferably 5 ⁇ 10 17 atoms/cm 3 or less.
  • hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to become water, which may result in the formation of oxygen vacancies.
  • oxygen vacancies When hydrogen enters the oxygen vacancies, electrons, which are carriers, may be generated. Further, a portion of hydrogen may combine with oxygen that is bonded to a metal atom to generate electrons, which are carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. Therefore, it is preferable that hydrogen in the channel formation region of the oxide semiconductor be reduced as much as possible.
  • the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is less than 1 ⁇ 10 20 atoms/cm 3 , preferably less than 5 ⁇ 10 19 atoms/cm 3 , more preferably 1 ⁇ 10 19 atoms/cm 3 , more preferably less than 5 ⁇ 10 18 atoms/cm 3 , even more preferably less than 1 ⁇ 10 18 atoms/cm 3 .
  • the concentration of alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms/cm 3 or less, preferably 2 ⁇ 10 16 atoms/cm 3 or less.
  • FIGS. 19A and 19B An example of a chip 1200 on which a semiconductor device of the present invention is mounted is shown using FIGS. 19A and 19B.
  • a plurality of circuits (systems) are mounted on the chip 1200.
  • SoC system on chip
  • the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog calculation units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.
  • the chip 1200 is provided with bumps (not shown) and is connected to the first surface of the package substrate 1201, as shown in FIG. 19B. Furthermore, a plurality of bumps 1202 are provided on the back surface of the first surface of the package substrate 1201 and are connected to a motherboard 1203.
  • the motherboard 1203 may be provided with storage devices such as a storage device 1221 and a flash memory 1222.
  • the semiconductor device 10 can be used as the storage device 1221. Further, for example, the semiconductor device 10 may be used instead of the flash memory 1222.
  • the CPU 1211 has multiple CPU cores.
  • the GPU 1212 has a plurality of GPU cores.
  • the CPU 1211 and the GPU 1212 may each have a memory that temporarily stores data.
  • a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200.
  • the semiconductor device 10 can be used for the memory.
  • the GPU 1212 is suitable for parallel calculation of a large amount of data, and can be used for image processing or product-sum calculation. By providing the GPU 1212 with an image processing circuit using an oxide semiconductor or a product-sum calculation circuit, image processing and product-sum calculation can be performed with low power consumption.
  • the CPU 1211 and the GPU 1212 are provided on the same chip, the wiring between the CPU 1211 and the GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212 and between the memory of the CPU 1211 and the GPU 1212 is possible. , and after the calculation by the GPU 1212, the calculation result can be transferred from the GPU 1212 to the CPU 1211 at high speed.
  • the analog calculation unit 1213 has one or both of an A/D (analog/digital) conversion circuit and a D/A (digital/analog) conversion circuit. Further, the analog calculation section 1213 may be provided with the above product-sum calculation circuit.
  • the memory controller 1214 includes a circuit that functions as a controller for the storage device 1221 and a circuit that functions as an interface for the flash memory 1222.
  • the interface 1215 has an interface circuit with externally connected devices such as a display device, speaker, microphone, camera, and controller. Controllers include mice, keyboards, game controllers, and the like. As such an interface, USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used.
  • USB Universal Serial Bus
  • HDMI registered trademark
  • High-Definition Multimedia Interface High-Definition Multimedia Interface
  • the network circuit 1216 includes a network circuit such as a LAN (Local Area Network). It may also include a circuit for network security.
  • LAN Local Area Network
  • the above circuit (system) can be formed on the chip 1200 using the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.
  • a package substrate 1201 provided with a chip 1200 having a GPU 1212, a motherboard 1203 provided with a storage device 1221, and a flash memory 1222 can be called a GPU module 1204.
  • the GPU module 1204 includes a chip 1200 using SoC technology, its size can be reduced. Furthermore, since it is excellent in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (portable) game machines.
  • a product-sum calculation circuit using the GPU 1212 can be used to create deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks ( DBN), etc.
  • the chip 1200 can be used as an AI chip or the GPU module 1204 can be used as an AI system module.
  • This embodiment mode shows an example of an electronic component incorporating the semiconductor device described in the above embodiment mode.
  • FIG. 20A shows a perspective view of an electronic component 700 and a board (mounted board 704) on which the electronic component 700 is mounted.
  • the electronic component 700 shown in FIG. 20A includes a storage device 720 within a mold 711. In FIG. 20A, a part is omitted to show the inside of the electronic component 700.
  • the electronic component 700 has a land 712 on the outside of the mold 711. Land 712 is electrically connected to electrode pad 713, and electrode pad 713 is electrically connected to memory device 720 by wire 714.
  • the electronic component 700 is mounted on a printed circuit board 702, for example.
  • a mounting board 704 is completed by combining a plurality of such electronic components and electrically connecting them on the printed circuit board 702.
  • the memory device 720 includes a drive circuit layer 721 and a memory circuit layer 722.
  • the storage device 300 can be used as the storage device 720. Therefore, the drive circuit layer 721 can be said to be a layer including the drive circuit 21. Furthermore, a single-layer or multi-layer memory array 20 can be used for the memory circuit layer 722. Therefore, the drive circuit layer 721 can be said to be a layer that includes the memory array 20.
  • FIG. 20B shows a perspective view of the electronic component 730.
  • the electronic component 730 is an example of a SiP (System in package) or an MCM (Multi Chip Module).
  • an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of storage devices 720 are provided on the interposer 731.
  • the storage device 720 is used as a high bandwidth memory (HBM).
  • HBM high bandwidth memory
  • the semiconductor device 735 an integrated circuit (semiconductor device) such as a CPU, GPU, or FPGA can be used.
  • the package substrate 732 a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used.
  • the interposer 731 a silicon interposer, a resin interposer, or the like can be used.
  • the interposer 731 has a plurality of wiring lines and has a function of electrically connecting a plurality of integrated circuits having different terminal pitches.
  • the plurality of wirings are provided in a single layer or in multiple layers.
  • the interposer 731 has a function of electrically connecting the integrated circuit provided on the interposer 731 to the electrodes provided on the package substrate 732.
  • interposers are sometimes called "rewiring boards” or “intermediate boards.”
  • a through electrode is provided in the interposer 731, and the integrated circuit and the package substrate 732 are electrically connected using the through electrode.
  • TSV Three Silicon Via
  • interposer 731 It is preferable to use a silicon interposer as the interposer 731. Since silicon interposers do not require active elements, they can be manufactured at lower cost than integrated circuits. On the other hand, since wiring formation in a silicon interposer can be performed by a semiconductor process, it is easy to form fine wiring, which is difficult to do with a resin interposer.
  • HBM In HBM, it is necessary to connect many wires to realize a wide memory bandwidth. For this reason, an interposer mounting an HBM is required to form fine and high-density wiring. Therefore, it is preferable to use a silicon interposer as the interposer for mounting the HBM.
  • a silicon interposer in SiP, MCM, etc. using a silicon interposer, reliability is less likely to deteriorate due to a difference in expansion coefficient between the integrated circuit and the interposer. Furthermore, since the silicon interposer has a highly flat surface, poor connection between the integrated circuit provided on the silicon interposer and the silicon interposer is less likely to occur. In particular, it is preferable to use a silicon interposer in a 2.5D package (2.5-dimensional packaging) in which a plurality of integrated circuits are arranged side by side on an interposer.
  • 2.5D package 2.5-dimensional packaging
  • a heat sink may be provided to overlap the electronic component 730.
  • a heat sink it is preferable that the heights of the integrated circuits provided on the interposer 731 are the same.
  • the storage device 720 and the semiconductor device 735 have the same height.
  • an electrode 733 may be provided at the bottom of the package substrate 732.
  • FIG. 20B shows an example in which the electrode 733 is formed with a solder ball. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be realized.
  • the electrode 733 may be formed of a conductive pin. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be realized.
  • the electronic component 730 can be mounted on other boards using various mounting methods, not limited to BGA and PGA.
  • SPGA Sttaggered Pin Grid Array
  • LGA Land Grid Array
  • QFP Quad Flat Package
  • QFJ Quad Flat J-leaded pack
  • QFN Quad Flat Non-leaded package
  • the semiconductor device is, for example, a memory device for various electronic devices (for example, an information terminal, a computer, a smartphone, an electronic book terminal, a digital still camera, a video camera, a recording/playback device, a navigation system, a game console, etc.). Applicable to equipment. Moreover, it can also be used for image sensors, IoT (Internet of Things), healthcare-related equipment, and the like.
  • computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system.
  • FIGS. 21A to 21J and 22A to 22E illustrate how each electronic device includes an electronic component 700 or an electronic component 730 having the semiconductor device.
  • Information terminal 5500 shown in FIG. 21A is a mobile phone (smartphone) that is a type of information terminal.
  • the information terminal 5500 includes a housing 5510 and a display section 5511.
  • the display section 5511 is equipped with a touch panel
  • the housing 5510 is equipped with buttons.
  • the information terminal 5500 can hold temporary files that are generated when an application is executed (for example, a cache when a web browser is used).
  • FIG. 21B illustrates an information terminal 5900 that is an example of a wearable terminal.
  • the information terminal 5900 includes a housing 5901, a display portion 5902, an operation switch 5903, an operation switch 5904, a band 5905, and the like.
  • the wearable terminal can hold temporary files generated when an application is executed by applying a semiconductor device according to one embodiment of the present invention.
  • the desktop information terminal 5300 includes an information terminal main body 5301, a display section 5302, and a keyboard 5303.
  • the desktop information terminal 5300 can hold temporary files generated when an application is executed by applying a semiconductor device according to one embodiment of the present invention.
  • a smartphone, a wearable terminal, and a desktop information terminal are shown as examples of electronic devices in FIGS. 21A to 21C, but information terminals other than smartphones, wearable terminals, and desktop information terminals may also be applied. can. Examples of information terminals other than smartphones, wearable terminals, and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, and workstations.
  • PDAs Personal Digital Assistants
  • FIG. 21D shows an electric refrigerator-freezer 5800 as an example of an electrical appliance.
  • the electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.
  • the electric refrigerator-freezer 5800 is an electric refrigerator-freezer that is compatible with IoT (Internet of Things).
  • a semiconductor device can be applied to an electric refrigerator-freezer 5800.
  • the electric refrigerator-freezer 5800 can send and receive information such as the foods stored in the electric refrigerator-freezer 5800 and the expiration date of the foods to an information terminal or the like via the Internet or the like.
  • the electric refrigerator-freezer 5800 can hold a temporary file generated when transmitting the information in the semiconductor device.
  • an electric refrigerator-freezer was explained as an electric appliance, but other electric appliances include air conditioners including vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cookers, water servers, and air conditioners. Examples include appliances, washing machines, dryers, and audio-visual equipment.
  • FIG. 21E shows a portable game machine 5200, which is an example of a game machine.
  • the portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.
  • FIG. 21F shows a stationary game machine 7500, which is an example of a game machine.
  • Stationary game machine 7500 includes a main body 7520 and a controller 7522.
  • a controller 7522 can be connected to the main body 7520 wirelessly or by wire.
  • the controller 7522 can include a touch panel, a stick, a rotary knob, a sliding knob, or the like that serves as an input interface other than a display unit that displays game images, buttons, or the like.
  • the shape of the controller 7522 is not limited to the shape shown in FIG. 21F, and the shape of the controller 7522 may be changed in various ways depending on the genre of the game.
  • a trigger in a shooting game such as FPS (First Person Shooter), a trigger can be a button and a controller shaped like a gun can be used.
  • a controller shaped like a musical instrument, music device, etc. can be used.
  • the stationary game machine may not use a controller, but instead may be equipped with a camera, a depth sensor, a microphone, etc., and be operated by the game player's gestures or voice.
  • the video of the game machine described above can be output by a display device such as a television device, a display for a personal computer, a display for a game, a head-mounted display, or the like.
  • a display device such as a television device, a display for a personal computer, a display for a game, a head-mounted display, or the like.
  • the portable game machine 5200 or the stationary game machine 7500 By applying the semiconductor device described in the above embodiment to the portable game machine 5200 or the stationary game machine 7500, the portable game machine 5200 or the stationary game machine 7500 with low power consumption can be realized. . Furthermore, low power consumption makes it possible to reduce heat generation from the circuit, thereby reducing the effect of heat generation on the circuit itself, peripheral circuits, and modules.
  • FIG. 21E A portable game machine is shown in FIG. 21E as an example of a game machine. Further, FIG. 21F shows a home-use stationary game machine. Note that the electronic device of one embodiment of the present invention is not limited to this. Examples of electronic devices according to one embodiment of the present invention include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.), pitching machines for batting practice installed in sports facilities, and the like.
  • the semiconductor device described in the above embodiments can be applied to an automobile, which is a moving object, and to the vicinity of the driver's seat of the automobile.
  • FIG. 21G shows an automobile 5700 that is an example of a moving object.
  • the 5700 car is equipped with an instrument panel near the driver's seat that provides a variety of information by displaying speedometer, tachometer, mileage, fuel gauge, gear status, air conditioner settings, etc. Further, a display device showing such information may be provided around the driver's seat.
  • the semiconductor device described in the above embodiment mode can temporarily hold information
  • the semiconductor device can be used, for example, in a system that performs automatic driving of the automobile 5700, road guidance, danger prediction, etc. It can be used to temporarily hold information.
  • the display device may be configured to display temporary information such as road guidance and danger prediction.
  • a configuration may be adopted in which images from a driving recorder installed in the automobile 5700 are held.
  • moving body is not limited to a car.
  • moving objects include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets).
  • FIG. 21H illustrates a digital camera 6240 that is an example of an imaging device.
  • the digital camera 6240 includes a housing 6241, a display section 6242, an operation switch 6243, a shutter button 6244, and the like, and a detachable lens 6246 is attached to the digital camera 6240.
  • the digital camera 6240 is configured here so that the lens 6246 can be removed from the housing 6241 and replaced, the lens 6246 and the housing 6241 may be integrated. Further, the digital camera 6240 may have a configuration in which a strobe device, a viewfinder, etc. can be separately attached.
  • the digital camera 6240 By applying the semiconductor device described in the above embodiment to the digital camera 6240, the digital camera 6240 with low power consumption can be realized. Furthermore, low power consumption makes it possible to reduce heat generation from the circuit, thereby reducing the effect of heat generation on the circuit itself, peripheral circuits, and modules.
  • Video camera The semiconductor device described in the above embodiment can be applied to a video camera.
  • FIG. 21I illustrates a video camera 6300, which is an example of an imaging device.
  • the video camera 6300 includes a first housing 6301, a second housing 6302, a display portion 6303, an operation switch 6304, a lens 6305, a connecting portion 6306, and the like.
  • the operation switch 6304 and the lens 6305 are provided in the first casing 6301, and the display portion 6303 is provided in the second casing 6302.
  • the first casing 6301 and the second casing 6302 are connected by a connecting part 6306, and the angle between the first casing 6301 and the second casing 6302 can be changed by the connecting part 6306. be.
  • the image on the display section 6303 may be switched according to the angle between the first casing 6301 and the second casing 6302 at the connection section 6306.
  • the video camera 6300 When recording video captured by the video camera 6300, it is necessary to perform encoding according to the data recording format. By using the semiconductor device described above, the video camera 6300 can hold temporary files generated during encoding.
  • ICD implantable cardioverter defibrillator
  • FIG. 21J is a schematic cross-sectional view showing an example of an ICD.
  • the ICD main body 5400 includes at least a battery 5401, an electronic component 700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.
  • the ICD main body 5400 is surgically installed in the body, and the two wires are passed through the subclavian vein 5405 and the superior vena cava 5406, and the tip of one wire is placed in the right ventricle and the tip of the other wire is placed in the right atrium. to be done.
  • the ICD main body 5400 has a function as a pacemaker, and paces the heart when the heart rate falls outside of a specified range. In addition, if the heart rate does not improve with pacing (such as rapid ventricular tachycardia or ventricular fibrillation), electric shock treatment is performed.
  • pacing such as rapid ventricular tachycardia or ventricular fibrillation
  • the ICD main body 5400 needs to constantly monitor heart rate in order to properly perform pacing and electric shock. Therefore, ICD main body 5400 has a sensor for detecting heart rate. Further, the ICD main body 5400 can store heart rate data acquired by the sensor, the number of times pacing treatment has been performed, time, etc. in the electronic component 700.
  • the ICD main body 5400 can have higher safety by having a plurality of batteries. Specifically, even if some of the batteries in the ICD main body 5400 become unusable, the remaining batteries can function, so it also functions as an auxiliary power source.
  • antenna 5404 may have an antenna that can transmit physiological signals.
  • a system may be configured to monitor cardiac activity.
  • FIG. 22A shows, as an example of the expansion device, an expansion device 6100 that is portable and equipped with a chip that can store information and is externally attached to a PC.
  • the expansion device 6100 can store information using the chip by connecting it to a PC via, for example, a USB (Universal Serial Bus).
  • FIG. 22A illustrates a portable expansion device 6100
  • the expansion device according to one embodiment of the present invention is not limited to this, and for example, a relatively portable expansion device equipped with a cooling fan or the like. It may also be a large form expansion device.
  • Expansion device 6100 includes a housing 6101, a cap 6102, a USB connector 6103, and a board 6104.
  • a board 6104 is housed in a housing 6101.
  • a circuit for driving the semiconductor device described in the above embodiment mode or the like is provided on the substrate 6104.
  • an electronic component 700 and a controller chip 6106 are attached to the board 6104.
  • the USB connector 6103 functions as an interface for connecting to an external device.
  • SD card The semiconductor device described in the above embodiments can be applied to an SD card that can be attached to electronic devices such as information terminals and digital cameras.
  • FIG. 22B is a schematic diagram of the external appearance of the SD card
  • FIG. 22C is a schematic diagram of the internal structure of the SD card.
  • the SD card 5110 has a housing 5111, a connector 5112, and a board 5113.
  • a connector 5112 functions as an interface for connecting to an external device.
  • the board 5113 is housed in a housing 5111.
  • the substrate 5113 is provided with a semiconductor device and a circuit for driving the semiconductor device.
  • an electronic component 700 and a controller chip 5115 are attached to the board 5113.
  • the circuit configurations of the electronic component 700 and the controller chip 5115 are not limited to those described above, and the circuit configurations may be changed as appropriate depending on the situation. For example, a write circuit, a row driver, a read circuit, etc. included in the electronic component may be incorporated into the controller chip 5115 instead of the electronic component 700.
  • the capacity of the SD card 5110 can be increased.
  • a wireless chip having a wireless communication function may be provided on the substrate 5113. Thereby, wireless communication can be performed between the external device and the SD card 5110, and data can be read from and written to the electronic component 700.
  • SSD Solid State Drive
  • electronic device such as an information terminal.
  • FIG. 22D is a schematic diagram of the external appearance of the SSD
  • FIG. 22E is a schematic diagram of the internal structure of the SSD.
  • the SSD 5150 includes a housing 5151, a connector 5152, and a board 5153.
  • a connector 5152 functions as an interface for connecting to an external device.
  • the board 5153 is housed in a housing 5151.
  • the substrate 5153 is provided with a memory device and a circuit that drives the memory device.
  • an electronic component 700, a memory chip 5155, and a controller chip 5156 are attached to the board 5153.
  • the capacity of the SSD 5150 can be increased.
  • a work memory is incorporated in the memory chip 5155.
  • a DRAM chip may be used as the memory chip 5155.
  • the controller chip 5156 incorporates a processor, an ECC circuit, and the like. Note that the circuit configurations of the electronic component 700, the memory chip 5155, and the controller chip 5115 are not limited to those described above, and the circuit configurations may be changed as appropriate depending on the situation.
  • the controller chip 5156 may also be provided with a memory that functions as a work memory.
  • a computer 5600 shown in FIG. 23A is an example of a large computer (supercomputer) mainly used for scientific and technical calculations. Scientific and technical calculations require high-speed processing of huge amounts of calculations, which consumes a lot of power and generates a lot of heat from the chip. For example, in a data center having a plurality of computers 5600, the amount of digital data used becomes extremely large. Specifically, the amount of digital data in the world is expected to exceed 10 24 (yotta) bytes or 10 30 (quetta) bytes.
  • a supercomputer with low power consumption can be realized. Furthermore, low power consumption makes it possible to reduce heat generation from the circuit, thereby reducing the effect of heat generation on the circuit itself, peripheral circuits, and modules. Furthermore, by using the semiconductor device of one embodiment of the present invention, a supercomputer with low power consumption can be realized. This is expected to reduce the amount of digital data in the world and make a major contribution to global warming countermeasures.
  • a plurality of rack-mounted computers 5620 are stored in a rack 5610.
  • the computer 5620 can have, for example, the configuration shown in the perspective view shown in FIG. 23B.
  • a computer 5620 has a motherboard 5630, and the motherboard 5630 has a plurality of slots 5631 and a plurality of connection terminals.
  • a PC card 5621 is inserted into the slot 5631.
  • the PC card 5621 has a connection terminal 5623, a connection terminal 5624, and a connection terminal 5625, each of which is connected to the motherboard 5630.
  • a PC card 5621 shown in FIG. 23C is an example of a processing board that includes a CPU, a GPU, a storage device, and the like.
  • PC card 5621 has a board 5622.
  • the board 5622 includes a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629.
  • semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 are illustrated in FIG. The description of the semiconductor device 5628 may be referred to.
  • connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630.
  • Examples of the standard of the connection terminal 5629 include PCIe.
  • connection terminal 5623, the connection terminal 5624, and the connection terminal 5625 can be used as an interface for supplying power, inputting signals, etc. to the PC card 5621, for example. Further, for example, it can be used as an interface for outputting a signal calculated by the PC card 5621.
  • the respective standards of the connection terminal 5623, connection terminal 5624, and connection terminal 5625 include, for example, USB (Universal Serial Bus), SATA (Serial ATA), SCSI (Small Computer System Interface), etc. Can be mentioned.
  • the respective standards include HDMI (registered trademark).
  • the semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and by inserting the terminal into a socket (not shown) provided on the board 5622, the semiconductor device 5626 and the board 5622 can be connected. Can be electrically connected.
  • the semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 and the board 5622 are electrically connected by, for example, reflow soldering the terminals to wiring provided on the board 5622. be able to.
  • Examples of the semiconductor device 5627 include an FPGA (Field Programmable Gate Array), a GPU, and a CPU.
  • an electronic component 730 can be used as the semiconductor device 5627.
  • the semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 are electrically connected by, for example, reflow soldering the terminals to wiring provided on the board 5622. be able to.
  • Examples of the semiconductor device 5628 include a storage device.
  • the electronic component 700 can be used as the semiconductor device 5628.
  • Computer 5600 can also function as a parallel computer. By using the computer 5600 as a parallel computer, for example, large-scale calculations required for artificial intelligence learning and inference can be performed.
  • the electronic devices can be made smaller and have lower power consumption. Further, since the semiconductor device of one embodiment of the present invention consumes less power, heat generated from the circuit can be reduced. Therefore, the adverse effect of the heat generation on the circuit itself, peripheral circuits, and module can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, an electronic device that operates stably even in a high-temperature environment can be achieved. Therefore, the reliability of electronic equipment can be improved.
  • a semiconductor device of one embodiment of the present invention includes an OS transistor.
  • the OS transistor has small variations in electrical characteristics due to radiation irradiation. In other words, since it has high resistance to radiation, it can be suitably used in environments where radiation may be incident. For example, OS transistors can be suitably used when used in outer space.
  • OS transistors can be suitably used when used in outer space.
  • FIG. 24 shows an artificial satellite 6800 as an example of space equipment.
  • the artificial satellite 6800 includes a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807.
  • a planet 6804 is illustrated in outer space.
  • outer space refers to, for example, an altitude of 100 km or more, but outer space described in this specification may include the thermosphere, mesosphere, and stratosphere.
  • outer space is an environment with more than 100 times higher radiation levels than on the ground.
  • radiation include electromagnetic waves (electromagnetic radiation) represented by X-rays and gamma rays, and particle radiation represented by alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, meson rays, etc. It will be done.
  • the solar panel 6802 By irradiating the solar panel 6802 with sunlight, electric power necessary for the operation of the artificial satellite 6800 is generated. However, for example, in a situation where the solar panel is not irradiated with sunlight, or in a situation where the amount of sunlight irradiated onto the solar panel is small, less electric power is generated. Therefore, the power necessary for satellite 6800 to operate may not be generated. In order to operate the artificial satellite 6800 even in a situation where generated power is small, it is preferable to provide the artificial satellite 6800 with a secondary battery 6805. Note that the solar panel is sometimes called a solar cell module.
  • Satellite 6800 can generate signals.
  • the signal is transmitted via antenna 6803 and can be received by, for example, a ground-based receiver or other satellite.
  • the position of the receiver that received the signal can be measured.
  • the artificial satellite 6800 can constitute a satellite positioning system.
  • control device 6807 has a function of controlling the artificial satellite 6800.
  • the control device 6807 is configured using one or more selected from, for example, a CPU, a GPU, and a storage device.
  • a semiconductor device including an OS transistor which is one embodiment of the present invention, is preferably used for the control device 6807.
  • OS transistors Compared to Si transistors, OS transistors have smaller fluctuations in electrical characteristics due to radiation irradiation. In other words, it is highly reliable and can be suitably used even in environments where radiation may be incident.
  • the artificial satellite 6800 can be configured to include a sensor.
  • the artificial satellite 6800 can have a function of detecting sunlight reflected by hitting an object provided on the ground.
  • the artificial satellite 6800 can have a function of detecting thermal infrared rays emitted from the earth's surface.
  • the artificial satellite 6800 can have the function of, for example, an earth observation satellite.
  • an artificial satellite is illustrated as an example of space equipment, but the present invention is not limited to this.
  • the semiconductor device of one embodiment of the present invention can be suitably used for space equipment such as a spacecraft, a space capsule, and a space probe.

Abstract

Provided is a novel semiconductor device. A vertical channel transistor is provided overlapping a capacitive element. A ferroelectric body is used as a dielectric layer of the capacitive element. It is preferable that the ferroelectric body contains hafnium, zirconium, or at least one element that is selected from among group 13 to 15 elements. Using an oxide semiconductor for a semiconductor layer of the vertical channel transistor makes it possible to raise the dielectric breakdown voltage between the source and drain and to reduce the channel length.

Description

半導体装置semiconductor equipment
本発明の一態様は、半導体装置に関する。 One embodiment of the present invention relates to a semiconductor device.
なお本発明の一態様は、上記の技術分野に限定されない。本明細書等で開示する発明の技術分野は、物、方法、または、製造方法に関するものである。または、本発明の一態様は、プロセス、マシン、マニュファクチャ、または、組成物（コンポジション・オブ・マター）に関するものである。 Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to products, methods, or manufacturing methods. Alternatively, one aspect of the present invention relates to a process, machine, manufacture, or composition of matter.
そのため、本発明の一態様に係る技術分野の一例として、半導体装置、表示装置、液晶表示装置、発光装置、蓄電装置、撮像装置、記憶装置、信号処理装置、プロセッサ、電子機器、システム、それらの駆動方法、それらの製造方法、それらの検査方法、またはそれらの使用方法などを挙げることができる。 Therefore, examples of the technical field according to one embodiment of the present invention include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, storage devices, signal processing devices, processors, electronic devices, systems, and the like. Examples include driving methods, methods of manufacturing them, methods of testing them, and methods of using them.
近年、ＬＳＩ、ＣＰＵ、メモリ（記憶装置）などの半導体装置の開発が進められている。これらの半導体装置は、コンピュータ、携帯情報端末など様々な電子機器に使用されている。また、メモリは、演算処理実行時の一時記憶、データの長期記憶など、用途に応じて様々な記憶方式のメモリが開発されている。代表的な記憶方式のメモリとして、ＤＲＡＭ、ＳＲＡＭ、フラッシュメモリなどがある。 In recent years, development of semiconductor devices such as LSIs, CPUs, and memories (storage devices) has been progressing. These semiconductor devices are used in various electronic devices such as computers and portable information terminals. Furthermore, various types of memory have been developed depending on the purpose, such as temporary storage during execution of arithmetic processing and long-term storage of data. Typical memory types include DRAM, SRAM, and flash memory.
また、非特許文献１に示すように、強誘電体（ｆｅｒｒｏｅｌｅｃｔｒｉｃ）を用いたメモリの研究開発が活発に行われている。また、次世代の強誘電体メモリのために、強誘電性のＨｆＯ２ベースの材料の研究（非特許文献２）、ハフニウム酸化物薄膜の強誘電性に関する研究（非特許文献３）、ＨｆＯ２薄膜の強誘電性に関する研究（非特許文献４）、及び強誘電体Ｈｆ０．５Ｚｒ０．５Ｏ２を用いたＦｅＲＡＭ（Ｆｅｒｒｏｅｌｅｃｔｒｉｃ　Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ）とＣＭＯＳとの統合の実証（非特許文献５）など、酸化ハフニウム関連の研究も活発に行われている。 Furthermore, as shown in Non-Patent Document 1, research and development of memories using ferroelectrics are actively being conducted. In addition, for the next generation of ferroelectric memory, research on ferroelectric HfO 2 -based materials (Non-Patent Document 2), research on ferroelectricity of hafnium oxide thin films (Non-Patent Document 3), HfO 2 Research on ferroelectricity of thin films (Non-Patent Document 4), and demonstration of integration of FeRAM (Ferroelectric Random Access Memory) using ferroelectric material Hf 0.5 Zr 0.5 O 2 with CMOS (Non-Patent Document 5) ) and other studies related to hafnium oxide are also actively being conducted.
本発明の一態様は、新規な半導体装置を提供することを課題の一つとする。または、本発明の一態様は、占有面積が小さい半導体装置を提供することを課題の一とする。または、本発明の一態様は、信頼性が高い半導体装置を提供することを課題の一とする。または、本発明の一態様は、消費電力が少ない半導体装置を提供することを課題の一とする。または、本発明の一態様は、記憶容量が大きい半導体装置を提供することを課題の一とする。 An object of one embodiment of the present invention is to provide a novel semiconductor device. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device that occupies a small area. Alternatively, an object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device with a large storage capacity.
なお本発明の一態様に係る課題は、上記列挙した課題に限定されない。上記列挙した課題は、他の課題の存在を妨げるものではない。なお他の課題とは、以下の記載で述べる、本項目で言及していない課題である。本項目で言及していない課題は、当業者であれば明細書または図面等の記載から導き出せるものであり、これらの記載から適宜抽出することができる。なお、本発明の一態様は、上記列挙した課題および他の課題の全てを解決する必要はない。本発明の一態様は、上記列挙した課題および他の課題のうち、少なくとも一つの課題を解決するものである。 Note that the problems related to one embodiment of the present invention are not limited to the problems listed above. The issues listed above do not preclude the existence of other issues. Other issues are those that are not mentioned in this section and are described below. Problems not mentioned in this section can be derived from the descriptions, drawings, etc. by those skilled in the art, and can be extracted as appropriate from these descriptions. Note that one embodiment of the present invention does not need to solve all of the problems listed above and other problems. One embodiment of the present invention solves at least one of the problems listed above and other problems.
本発明の一態様は、容量素子と、容量素子上のトランジスタとを有し、容量素子は、第１導電層と、第１導電層上の第１絶縁層と、第１絶縁層上の第２導電層と、を有し、トランジスタは、第２導電層上の第２絶縁層と、第２絶縁層上の第３導電層と、第２絶縁層および第３導電層に設けられた開口と、開口を覆う半導体層と、半導体層上の第３絶縁層と、第３絶縁層上の第４導電層と、を有し、開口は第２導電層と重なり、第１絶縁層は強誘電体を含む半導体装置である。 One embodiment of the present invention includes a capacitor and a transistor on the capacitor, and the capacitor includes a first conductive layer, a first insulating layer on the first conductive layer, and a transistor on the first insulating layer. two conductive layers, the transistor includes a second insulating layer on the second conductive layer, a third conductive layer on the second insulating layer, and an opening provided in the second insulating layer and the third conductive layer. a semiconductor layer covering the opening, a third insulating layer on the semiconductor layer, and a fourth conductive layer on the third insulating layer, the opening overlaps with the second conductive layer, and the first insulating layer has a strong This is a semiconductor device that includes a dielectric.
本発明の別の一態様は、積層された複数の層と、複数の層を貫通する第１電極と、を有し、複数の層のそれぞれは、容量素子と、容量素子上のトランジスタとを有し、容量素子は、第１導電層と、第１導電層上の第１絶縁層と、第１絶縁層上の第２導電層と、を有し、トランジスタは、第２導電層上の第２絶縁層と、第２絶縁層上の第３導電層と、第２絶縁層および第３導電層に設けられた開口と、開口を覆う半導体層と、半導体層上の第３絶縁層と、第３絶縁層上の第４導電層と、を有し、開口は第２導電層と重なり、第１絶縁層は強誘電体を含み、第３導電層は第１電極と電気的に接続する半導体装置である。 Another embodiment of the present invention includes a plurality of stacked layers and a first electrode penetrating the plurality of layers, and each of the plurality of layers includes a capacitor and a transistor on the capacitor. The capacitor has a first conductive layer, a first insulating layer on the first conductive layer, and a second conductive layer on the first insulating layer, and the transistor has a first conductive layer on the second conductive layer. a second insulating layer, a third conductive layer on the second insulating layer, an opening provided in the second insulating layer and the third conductive layer, a semiconductor layer covering the opening, and a third insulating layer on the semiconductor layer. , a fourth conductive layer on the third insulating layer, the opening overlaps with the second conductive layer, the first insulating layer includes a ferroelectric material, and the third conductive layer is electrically connected to the first electrode. This is a semiconductor device.
上記開口における第２絶縁層の側面と、第２絶縁層の底面のなす角度は、４５度以上９０度以下が好ましい。 The angle between the side surface of the second insulating layer and the bottom surface of the second insulating layer in the opening is preferably 45 degrees or more and 90 degrees or less.
また、上記半導体装置は、１５０℃の環境温度下において、メモリ保持期間が１０日以上であることが好ましい。 Further, it is preferable that the semiconductor device has a memory retention period of 10 days or more at an environmental temperature of 150°C.
第２絶縁層は、第４絶縁層と、第４絶縁層上の第５絶縁層と、第５絶縁層上の第６絶縁層と、を有してもよい。例えば、第４絶縁層と第６絶縁層のそれぞれは、窒素およびシリコンを有してもよい。例えば、第５絶縁層は、酸素およびシリコンを有してもよい。また、第４絶縁層と第６絶縁層のそれぞれは、水素を有してもよい。 The second insulating layer may include a fourth insulating layer, a fifth insulating layer on the fourth insulating layer, and a sixth insulating layer on the fifth insulating layer. For example, each of the fourth insulating layer and the sixth insulating layer may include nitrogen and silicon. For example, the fifth insulating layer may include oxygen and silicon. Furthermore, each of the fourth insulating layer and the sixth insulating layer may contain hydrogen.
半導体層として、例えば、酸化物半導体を用いてもよい。半導体層は、インジウムおよび亜鉛の少なくとも一と、酸素と、を含むことが好ましい。第１電極は、複数の導電層を含んで構成されてもよい。第１絶縁層は、ハフニウム、ジルコニウム、および酸素を含むことが好ましい。第１導電層および第２導電層は、チタンおよび窒素を含むことが好ましい。 For example, an oxide semiconductor may be used as the semiconductor layer. Preferably, the semiconductor layer contains at least one of indium and zinc, and oxygen. The first electrode may include a plurality of conductive layers. Preferably, the first insulating layer contains hafnium, zirconium, and oxygen. Preferably, the first conductive layer and the second conductive layer contain titanium and nitrogen.
本発明の一態様によって、新規な半導体装置を提供できる。または、本発明の一態様によって、占有面積が小さい半導体装置を提供できる。または、本発明の一態様によって、信頼性が高い半導体装置を提供できる。または、本発明の一態様によって、消費電力が少ない半導体装置を提供できる。または、本発明の一態様によって、記憶容量が大きい半導体装置を提供できる。 According to one embodiment of the present invention, a novel semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device that occupies a small area can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with a large storage capacity can be provided.
なお本発明の一態様の効果は、上記列挙した効果に限定されない。上記列挙した効果は、他の効果の存在を妨げるものではない。従って本発明の一態様は、上記列挙した効果を有さない場合もある。なお、他の効果とは、以下の記載で述べる、本項目で言及していない効果である。他の効果は、当業者であれば明細書または図面等の記載から導き出せるものであり、これらの記載から適宜抽出することができる。本発明の一態様は、上記列挙した効果、および他の効果のうち、少なくとも一つの効果を有するものである。 Note that the effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. Therefore, one embodiment of the present invention may not have the effects listed above. Note that other effects are effects that are not mentioned in this item and are described below. Other effects can be derived from descriptions such as the specification or drawings by those skilled in the art, and can be extracted as appropriate from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects.
図１Ａおよび図１Ｂは、半導体装置の構成例を示す図である。図１Ｃおよび図１Ｄは、半導体装置の等価回路図である。
図２Ａ乃至図２Ｃは、半導体装置の構成例を示す図である。
図３Ａ乃至図３Ｅは、半導体装置の構成例を示す図である。
図４Ａおよび図４Ｂは、半導体装置の構成例を示す図である。
図５Ａおよび図５Ｂは、半導体装置の構成例を示す図である。
図６Ａ乃至図６Ｃは、半導体装置の構成例を示す図である。
図７Ａ乃至図７Ｃは、半導体装置の構成例を示す図である。
図８Ａ乃至図８Ｃは、半導体装置の構成例を示す図である。
図９Ａおよび図９Ｂは、半導体装置の構成例を示す図である。図９Ｃは、半導体装置の等価回路図である。
図１０は、半導体装置の構成例を示す図である。
図１１は、半導体装置の等価回路図である。
図１２は、半導体装置の構成例を示す図である。
図１３は、半導体装置の等価回路図である。
図１４Ａは、メモリセルの回路構成例を説明する図である。図１４Ｂは、ヒステリシス特性の一例を示すグラフである。図１４Ｃは、メモリセルの駆動方法例を示すタイミングチャートである。
図１５Ａ乃至図１５Ｃは、記憶装置の構成例を示す図である。
図１６Ａは、記憶装置の構成例を示す図である。図１６Ｂは、記憶装置が有するメモリストリングの模式図である。
図１７Ａは、記憶装置の構成例を示す図である。図１７Ｂは、記憶装置が有するメモリストリングの模式図である。
図１８は、記憶装置の断面構成例を示す図である。
図１９Ａおよび図１９Ｂは本発明の一態様に係る半導体装置の模式図である。
図２０Ａおよび図２０Ｂは電子部品の一例を示す斜視図である。
図２１Ａ乃至図２１Ｊは、電子機器の一例を説明する図である。
図２２Ａ乃至図２２Ｅは、電子機器の一例を説明する図である。
図２３Ａ乃至図２３Ｃは、電子機器の一例を説明する図である。
図２４は、宇宙用機器の一例を示す図である。 FIG. 1A and FIG. 1B are diagrams illustrating a configuration example of a semiconductor device. FIGS. 1C and 1D are equivalent circuit diagrams of the semiconductor device.
2A to 2C are diagrams showing configuration examples of a semiconductor device.
3A to 3E are diagrams showing configuration examples of semiconductor devices.
4A and 4B are diagrams illustrating a configuration example of a semiconductor device.
5A and 5B are diagrams illustrating a configuration example of a semiconductor device.
6A to 6C are diagrams showing configuration examples of semiconductor devices.
7A to 7C are diagrams showing configuration examples of semiconductor devices.
8A to 8C are diagrams showing configuration examples of semiconductor devices.
9A and 9B are diagrams illustrating a configuration example of a semiconductor device. FIG. 9C is an equivalent circuit diagram of the semiconductor device.
FIG. 10 is a diagram showing a configuration example of a semiconductor device.
FIG. 11 is an equivalent circuit diagram of the semiconductor device.
FIG. 12 is a diagram showing a configuration example of a semiconductor device.
FIG. 13 is an equivalent circuit diagram of the semiconductor device.
FIG. 14A is a diagram illustrating an example of a circuit configuration of a memory cell. FIG. 14B is a graph showing an example of hysteresis characteristics. FIG. 14C is a timing chart showing an example of a method for driving a memory cell.
15A to 15C are diagrams showing configuration examples of storage devices.
FIG. 16A is a diagram illustrating a configuration example of a storage device. FIG. 16B is a schematic diagram of a memory string included in the storage device.
FIG. 17A is a diagram illustrating a configuration example of a storage device. FIG. 17B is a schematic diagram of a memory string included in the storage device.
FIG. 18 is a diagram showing an example of a cross-sectional configuration of a storage device.
19A and 19B are schematic diagrams of a semiconductor device according to one embodiment of the present invention.
20A and 20B are perspective views showing an example of an electronic component.
21A to 21J are diagrams illustrating an example of an electronic device.
22A to 22E are diagrams illustrating an example of an electronic device.
23A to 23C are diagrams illustrating an example of an electronic device.
FIG. 24 is a diagram showing an example of space equipment.
以下、実施の形態について図面を参照しながら説明する。ただし、実施の形態は多くの異なる態様で実施することが可能であり、趣旨およびその範囲から逸脱することなくその形態および詳細を様々に変更し得ることは当業者であれば容易に理解される。従って、本発明は、以下の実施の形態の記載内容に限定して解釈されるものではない。 Hereinafter, embodiments will be described with reference to the drawings. However, those skilled in the art will readily understand that the embodiments can be implemented in many different ways and that the form and details thereof can be changed in various ways without departing from the spirit and scope thereof. . Therefore, the present invention should not be construed as being limited to the contents described in the following embodiments.
本明細書等において、半導体装置とは、半導体特性を利用した装置であり、半導体素子（トランジスタ、ダイオード、フォトダイオード等）を含む回路、同回路を有する装置等をいう。また、半導体特性を利用することで機能しうる装置全般をいう。例えば、集積回路、集積回路を備えたチップ、パッケージにチップを収納した電子部品は半導体装置の一例である。また、記憶装置、表示装置、発光装置、照明装置および電子機器等は、それ自体が半導体装置であり、かつ、半導体装置を有している場合がある。 In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having the same circuit, and the like. It also refers to any device that can function by utilizing the characteristics of semiconductors. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component containing a chip in a package are examples of semiconductor devices. Furthermore, storage devices, display devices, light emitting devices, lighting devices, electronic devices, and the like are themselves semiconductor devices and may include semiconductor devices.
本明細書に係る図面等において、大きさ、層の厚さ、または領域は、明瞭化のために誇張されている場合がある。よって、必ずしもその大きさもしくは縦横比などに限定されない。なお図面は、理想的な例を模式的に示したものであり、図面に示す形状または値などに限定されない。 In the drawings and the like related to the present specification, sizes, layer thicknesses, and regions may be exaggerated for clarity. Therefore, it is not necessarily limited to its size or aspect ratio. Note that the drawings schematically show ideal examples and are not limited to the shapes or values shown in the drawings.
なお、実施の形態の発明の構成において、同一部分または同様な機能を有する部分には同一の符号を異なる図面間で共通して用い、その繰り返しの説明は省略する場合がある。また、同様の機能を指す場合には、ハッチパターンを同じくし、特に符号を付さない場合がある。また、図面を理解しやすくするため、斜視図または上面図などにおいて、一部の構成要素の記載を省略している場合がある。 In addition, in the configuration of the invention of the embodiment, the same reference numerals are used in common between different drawings for the same parts or parts having similar functions, and repeated explanation thereof may be omitted. Furthermore, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be attached. Furthermore, in order to make the drawings easier to understand, some components may be omitted in perspective views, top views, or the like.
なお、図面などにおいて、Ｘ方向（Ｘ軸に沿う方向）、Ｙ方向（Ｙ軸に沿う方向）、およびＺ方向（Ｚ軸に沿う方向）を示す矢印を付す場合がある。なお、本明細書等において、「Ｘ方向」とはＸ軸に沿う方向であり、明示する場合を除き、順方向と逆方向を区別しない。「Ｙ方向」および「Ｚ方向」についても同様である。また、Ｘ方向、Ｙ方向、およびＺ方向は、それぞれが互いに交差する方向である。より具体的には、Ｘ方向、Ｙ方向、およびＺ方向は、それぞれが互いに直交する方向である。本明細書などでは、Ｘ方向、Ｙ方向、またはＺ方向の１つを「第１方向」または「第１の方向」と呼ぶ場合がある。また、他の１つを「第２方向」または「第２の方向」と呼ぶ場合がある。また、残りの１つを「第３方向」または「第３の方向」と呼ぶ場合がある。 Note that in drawings and the like, arrows indicating the X direction (direction along the X axis), Y direction (direction along the Y axis), and Z direction (direction along the Z axis) may be provided. Note that in this specification and the like, the "X direction" refers to the direction along the X axis, and there is no distinction between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction". Further, the X direction, the Y direction, and the Z direction are directions that intersect with each other. More specifically, the X direction, the Y direction, and the Z direction are directions that are orthogonal to each other. In this specification and the like, one of the X direction, the Y direction, or the Z direction may be referred to as a "first direction" or a "first direction." Further, the other direction may be referred to as a "second direction" or "second direction". Further, the remaining one may be referred to as a "third direction" or "third direction."
本明細書等において、「第１」、「第２」、「第３」という序数詞は、構成要素の混同を避けるために付したものである。従って、構成要素の数を限定するものではない。また、構成要素の順序を限定するものではない。例えば、本明細書などの実施の形態の一において「第１」に言及された構成要素が、他の実施の形態、あるいは特許請求の範囲などにおいて「第２」に言及された構成要素とすることもありうる。また例えば、本明細書等の実施の形態の一において「第１」に言及された構成要素を、他の実施の形態、あるいは特許請求の範囲などにおいて省略することもありうる。 In this specification and the like, ordinal numbers such as "first," "second," and "third" are added to avoid confusion of constituent elements. Therefore, the number of components is not limited. Further, the order of the constituent elements is not limited. For example, a component referred to as "first" in one embodiment such as this specification is a component referred to as "second" in other embodiments, claims, etc. It is possible. Furthermore, for example, a component referred to as "first" in one of the embodiments of this specification etc. may be omitted in other embodiments or claims.
本明細書等において、「上に」、「下に」、「上方に」、または「下方に」などの配置を示す語句は、構成要素同士の位置関係を、図面を参照して説明するために、便宜上用いている場合がある。また、構成要素同士の位置関係は、各構成を描写する方向に応じて適宜変化するものである。従って、明細書等で説明した語句に限定されず、状況に応じて適切に言い換えることができる。例えば、「導電体の上面に位置する絶縁体」の表現では、示している図面の向きを１８０度回転することによって、「導電体の下面に位置する絶縁体」と言い換えることができる。 In this specification, etc., words indicating arrangement such as "above," "below," "above," or "below" are used to explain the positional relationship between constituent elements with reference to the drawings. In some cases, it is used for convenience. Further, the positional relationship between the components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those explained in the specification, etc., and can be appropriately rephrased depending on the situation. For example, the expression "an insulator located on the upper surface of a conductor" can be translated into "an insulator located on the lower surface of a conductor" by rotating the orientation of the drawing by 180 degrees.
また、「上」および「下」の用語は、構成要素の位置関係が直上または直下で、かつ、直接接していることを限定するものではない。例えば、「絶縁層Ａ上の電極Ｂ」の表現であれば、絶縁層Ａの上に電極Ｂが直接接して形成されている必要はなく、絶縁層Ａと電極Ｂとの間に他の構成要素を含むものを除外しない。 Further, the terms "above" and "below" do not limit the positional relationship of the components to be directly above or below, and directly in contact with each other. For example, if the expression is "electrode B on insulating layer A," electrode B does not need to be formed directly on insulating layer A, and there is no need to form another structure between insulating layer A and electrode B. Do not exclude things that contain elements.
本明細書等において、「重なる」などの用語は、構成要素の積層順などの状態を限定するものではない。例えば、「絶縁層Ａに重なる電極Ｂ」の表現であれば、絶縁層Ａの上に電極Ｂが形成されている状態に限らず、絶縁層Ａの下に電極Ｂが形成されている状態または絶縁層Ａの右側（もしくは左側）に電極Ｂが形成されている状態などを除外しない。 In this specification and the like, terms such as "overlapping" do not limit the state such as the stacking order of components. For example, the expression "electrode B overlapping insulating layer A" is not limited to the state in which electrode B is formed on insulating layer A, but also the state in which electrode B is formed under insulating layer A, or A state in which the electrode B is formed on the right side (or left side) of the insulating layer A is not excluded.
本明細書等において、「隣接」および「近接」の用語は、構成要素が直接接していることを限定するものではない。例えば、「絶縁層Ａに隣接する電極Ｂ」の表現であれば、絶縁層Ａと電極Ｂが直接接して形成されている必要はなく、絶縁層Ａと電極Ｂの間に他の構成要素を含むものを除外しない。 In this specification and the like, the terms "adjacent" and "nearby" do not limit that components are in direct contact. For example, in the expression "electrode B adjacent to insulating layer A", insulating layer A and electrode B do not need to be formed in direct contact with each other, and other components may be placed between insulating layer A and electrode B. Do not exclude what is included.
本明細書等において、「膜」、「層」などの語句は、状況に応じて、互いに入れ替えることが可能である。例えば、「導電層」という用語を、「導電膜」という用語に変更することが可能な場合がある。または、例えば、「絶縁膜」という用語を、「絶縁層」という用語に変更することが可能な場合がある。または、場合によっては、または、状況に応じて、「膜」、「層」などの語句を使わずに、別の用語に入れ替えることが可能である。例えば、「導電層」または「導電膜」という用語を、「導電体」という用語に変更することが可能な場合がある。または、「導電体」という用語を、「導電層」または「導電膜」という用語に変更することが可能な場合がある。または、例えば、「絶縁層」または「絶縁膜」という用語を、「絶縁体」という用語に変更することが可能な場合がある。または、「絶縁体」という用語を、「絶縁層」または「絶縁膜」という用語に変更することが可能な場合がある。 In this specification and the like, terms such as "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be changed to the term "conductive film." Alternatively, for example, the term "insulating film" may be changed to the term "insulating layer." Alternatively, in some cases or depending on the situation, words such as "film" and "layer" may be omitted and replaced with other terms. For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor." Alternatively, the term "conductor" may be changed to the term "conductive layer" or "conductive film." Alternatively, for example, the term "insulating layer" or "insulating film" may be changed to the term "insulator." Alternatively, the term "insulator" may be changed to the term "insulating layer" or "insulating film."
なお、電圧とは２点間における電位差のことをいい、電位とはある一点における静電場の中にある単位電荷が持つ静電エネルギー（電気的な位置エネルギー）のことをいう。ただし、一般的に、ある一点における電位と基準となる電位（例えば接地電位）との電位差のことを、単に電位もしくは電圧と呼び、電位と電圧が同義語として用いられることが多い。このため、本明細書などでは、明示する場合を除き、電位を電圧と読み替えてもよいし、電圧を電位と読み替えてもよいこととする。 Note that voltage refers to the potential difference between two points, and potential refers to the electrostatic energy (electrical potential energy) possessed by a unit charge in an electrostatic field at a certain point. However, in general, a potential difference between a potential at a certain point and a reference potential (for example, ground potential) is simply called a potential or a voltage, and potential and voltage are often used synonymously. Therefore, in this specification and the like, unless explicitly stated, a potential may be read as a voltage, and a voltage may be read as a potential.
本明細書等において「電極」「配線」「端子」などの用語は、これらの構成要素を機能的に限定するものではない。例えば、「電極」は「配線」の一部として用いられることがあり、その逆もまた同様である。さらに、「電極」または「配線」の用語は、複数の「電極」または「配線」が一体となって形成されている場合なども含む。また、例えば、「端子」は「配線」または「電極」の一部として用いられることがあり、その逆もまた同様である。更に、「端子」の用語は、複数の「電極」「配線」「端子」などが一体となって形成されている場合なども含む。そのため、例えば、「電極」は「配線」または「端子」の一部とすることができ、また、例えば、「端子」は「配線」または「電極」の一部とすることができる。また、「電極」「配線」「端子」などの用語は、場合によって、「領域」などの用語に置き換える場合がある。 In this specification and the like, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring" and vice versa. Furthermore, the term "electrode" or "wiring" includes cases where a plurality of "electrodes" or "wirings" are formed integrally. Also, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" also includes cases where a plurality of "electrodes", "wirings", "terminals", etc. are formed integrally. Therefore, for example, an "electrode" can be a part of a "wiring" or a "terminal," and, for example, a "terminal" can be a part of a "wiring" or a "electrode." Further, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" depending on the case.
本明細書等において、「配線」、「信号線」、「電源線」などの用語は、場合によっては、または、状況に応じて、互いに入れ替えることが可能である。例えば、「配線」という用語を、「信号線」という用語に変更することが可能な場合がある。また、例えば、「配線」という用語を、「電源線」などの用語に変更することが可能な場合がある。また、その逆も同様で、「信号線」「電源線」などの用語を、「配線」という用語に変更することが可能な場合がある。「電源線」などの用語は、「信号線」などの用語に変更することが可能な場合がある。また、その逆も同様で「信号線」などの用語は、「電源線」などの用語に変更することが可能な場合がある。また、配線に印加されている「電位」という用語を、場合によっては、または、状況に応じて、「信号」などという用語に変更することが可能な場合がある。また、その逆も同様で、「信号」などの用語は、「電位」という用語に変更することが可能な場合がある。 In this specification and the like, terms such as "wiring," "signal line," and "power line" can be interchanged depending on the situation or situation. For example, it may be possible to change the term "wiring" to the term "signal line." Furthermore, for example, it may be possible to change the term "wiring" to a term such as "power line". The reverse is also true, and terms such as "signal line" and "power line" may sometimes be changed to the term "wiring". Terms such as "power line" may be changed to terms such as "signal line". Moreover, the reverse is also true, and a term such as "signal line" may be changed to a term such as "power line". Further, depending on the case or the situation, the term "potential" applied to the wiring may be changed to a term such as "signal". Moreover, the reverse is also true, and a term such as "signal" may be changed to the term "potential".
また、本明細書等において、「容量素子」とは、例えば、０Ｆよりも高い静電容量の値を有する回路素子、０Ｆよりも高い静電容量の値を有する配線の領域、寄生容量、またはトランジスタのゲート容量とすることができる。また、「容量素子」、「寄生容量」、または「ゲート容量」という用語は、「容量」という用語に言い換えることができる場合がある。逆に、「容量」という用語は、「容量素子」、「寄生容量」、または「ゲート容量」という用語に言い換えることができる場合がある。また、「容量」（３端子以上の「容量」を含む）は、絶縁体と、当該絶縁体を挟んだ一対の導電体と、を含む構成となっている。そのため、「容量」の「一対の導電体」という用語は、「一対の電極」、「一対の導電領域」、「一対の領域」、または「一対の端子」に言い換えることができる。また、「一対の端子の一方」という用語は、「一方の端子」または「第１端子」と呼称する場合がある。また、「一対の端子の他方」という用語は、「他方の端子」または「第２端子」と呼称する場合がある。なお、静電容量の値としては、例えば、０．０５ｆＦ以上１０ｐＦ以下とすることができる。また、例えば、１ｐＦ以上１０μＦ以下としてもよい。 In addition, in this specification and the like, a "capacitive element" refers to, for example, a circuit element having a capacitance value higher than 0F, a wiring region having a capacitance value higher than 0F, a parasitic capacitance, or It can be the gate capacitance of a transistor. Further, the term "capacitive element," "parasitic capacitance," or "gate capacitance" can sometimes be replaced with the term "capacitance." Conversely, the term "capacitance" may be translated into the terms "capacitive element," "parasitic capacitance," or "gate capacitance." Further, a "capacitor" (including a "capacitor" having three or more terminals) has a configuration including an insulator and a pair of conductors sandwiching the insulator. Therefore, the term "pair of conductors" in "capacitance" can be paraphrased as "pair of electrodes," "pair of conductive regions," "pair of regions," or "pair of terminals." Further, the term "one of a pair of terminals" may also be referred to as "one terminal" or "first terminal." Moreover, the term "the other of a pair of terminals" may be referred to as "the other terminal" or "the second terminal." Note that the value of the capacitance can be, for example, 0.05 fF or more and 10 pF or less. Further, for example, it may be set to 1 pF or more and 10 μF or less.
トランジスタの「ソース」および「ドレイン」の機能は、異なる極性のトランジスタを採用する場合、もしくは、回路動作において電流の方向が変化する場合などで入れ替わることがある。このため、本明細書等においては、「ソース」および「ドレイン」の用語は、入れ替えて用いることができるものとする。 The functions of a transistor's "source" and "drain" may be interchanged, such as when using transistors of different polarity or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms "source" and "drain" can be used interchangeably.
本明細書などにおいて、「ゲート」とは、ゲート電極およびゲート配線の一部または全部のことをいう。ゲート配線とは、少なくとも一つのトランジスタのゲート電極と、別の電極または別の配線とを電気的に接続させるための配線のことをいう。 In this specification and the like, the term "gate" refers to part or all of a gate electrode and a gate wiring. The gate wiring refers to a wiring for electrically connecting the gate electrode of at least one transistor to another electrode or another wiring.
本明細書などにおいて、「ソース」とは、ソース領域、ソース電極、およびソース配線の一部または全部のことをいう。ソース領域とは、半導体層のうち、抵抗率が一定値以下の領域のことをいう。ソース電極とは、ソース領域に接続される部分を含む導電層のことをいう。ソース配線とは、少なくとも一つのトランジスタのソース電極と、別の電極または別の配線とを電気的に接続させるための配線のことをいう。 In this specification and the like, the term "source" refers to part or all of a source region, a source electrode, and a source wiring. The source region refers to a region of the semiconductor layer where the resistivity is below a certain value. A source electrode refers to a conductive layer including a portion connected to a source region. The source wiring refers to a wiring for electrically connecting the source electrode of at least one transistor to another electrode or another wiring.
本明細書などにおいて、「ドレイン」とは、ドレイン領域、ドレイン電極、およびドレイン配線の一部または全部のことをいう。ドレイン領域とは、半導体層のうち、抵抗率が一定値以下の領域のことをいう。ドレイン電極とは、ドレイン領域に接続される部分を含む導電層のことをいう。ドレイン配線とは、少なくとも一つのトランジスタのドレイン電極と、別の電極または別の配線とを電気的に接続させるための配線のことをいう。 In this specification and the like, the term "drain" refers to part or all of a drain region, a drain electrode, and a drain wiring. The drain region refers to a region of the semiconductor layer where the resistivity is below a certain value. A drain electrode refers to a conductive layer including a portion connected to a drain region. The drain wiring refers to a wiring for electrically connecting the drain electrode of at least one transistor to another electrode or another wiring.
また、本明細書等に示すトランジスタは、特に断りがない場合、エンハンスメント型（ノーマリーオフ型）の電界効果トランジスタとする。また、本明細書等に示すトランジスタがｎチャネル型トランジスタであり、特に断りがない場合、該トランジスタのしきい値電圧（「Ｖｔｈ」ともいう。）は、０Ｖよりも大きいものとする。また、本明細書等に示すトランジスタがｐチャネル型トランジスタであり、特に断りがない場合、該トランジスタのしきい値電圧（「Ｖｔｈ」ともいう。）は、０Ｖ以下であるものとする。また、特に断りがない場合、同じ導電型の複数のトランジスタのＶｔｈは、全て等しいものとする。 Further, unless otherwise specified, the transistors shown in this specification and the like are enhancement type (normally-off type) field effect transistors. Furthermore, the transistors described in this specification and the like are n-channel transistors, and unless otherwise specified, the threshold voltage (also referred to as "Vth") of the transistors is greater than 0V. Further, the transistor shown in this specification and the like is a p-channel transistor, and unless otherwise specified, the threshold voltage (also referred to as "Vth") of the transistor is 0V or less. Furthermore, unless otherwise specified, the Vth of a plurality of transistors of the same conductivity type are all equal.
また、本明細書等において、特に断りがない場合、オフ電流とは、トランジスタがオフ状態（「非導通状態」または「遮断状態」ともいう）にあるときにソースとドレインの間に流れる電流（「ドレイン電流」または「Ｉｄ」ともいう。）をいう。オフ状態とは、特に断りがない場合、ｎチャネル型トランジスタでは、ソースを基準とした時のゲートとソースの間の電位差（「ゲート電圧」または「Ｖｇ」ともいう。）がしきい値電圧よりも低い状態、ｐチャネル型トランジスタでは、Ｖｇがしきい値電圧よりも高い状態をいう。例えば、ｎチャネル型のトランジスタのオフ電流とは、ＶｇがＶｔｈよりも低いときのドレイン電流を言う場合がある。 In addition, in this specification, etc., unless otherwise specified, off-state current refers to the current (current) that flows between the source and drain when the transistor is in the off state (also referred to as the "non-conducting state" or "blocking state"). (Also referred to as "drain current" or "Id.") Unless otherwise specified, an off state is defined as an n-channel transistor in which the potential difference between the gate and source (also referred to as "gate voltage" or "Vg") with respect to the source is lower than the threshold voltage. For p-channel transistors, this is a state in which Vg is higher than the threshold voltage. For example, the off-state current of an n-channel transistor may refer to the drain current when Vg is lower than Vth.
また、本明細書等では、オフ電流と同じ意味で、リーク電流と記載する場合がある。また、本明細書等において、オフ電流とは、例えば、トランジスタがオフ状態にあるときに、ソースとドレインとの間に流れる電流を指す場合がある。 Further, in this specification and the like, it may be referred to as leak current to have the same meaning as off-state current. Further, in this specification and the like, off-state current may refer to, for example, a current flowing between a source and a drain when a transistor is in an off state.
また、本明細書等において、特に断りがない場合、オン電流とは、トランジスタがオン状態（「導通状態」ともいう。）にあるときのＩｄをいう。オン状態とは、特に断りがない場合、ｎチャネル型トランジスタでは、ＶｇがＶｔｈ以上である状態、ｐチャネル型トランジスタでは、ＶｇがＶｔｈ以下である状態をいう。例えば、ｎチャネル型のトランジスタのオン電流とは、ＶｇがＶｔｈ以上であるときのドレイン電流を言う場合がある。 Further, in this specification and the like, unless otherwise specified, on-current refers to Id when a transistor is in an on-state (also referred to as a "conductive state"). Unless otherwise specified, the on-state refers to a state in which Vg is greater than or equal to Vth for an n-channel transistor, and a state in which Vg is less than or equal to Vth for a p-channel transistor. For example, the on-current of an n-channel transistor may refer to the drain current when Vg is equal to or higher than Vth.
本明細書において、「平行」とは、二つの直線が−１０度以上１０度以下の角度で配置されている状態をいう。したがって、−５度以上５度以下の場合も含まれる。また、「略平行」または「概略平行」とは、二つの直線が−３０度以上３０度以下の角度で配置されている状態をいう。また、「垂直」とは、二つの直線が８０度以上１００度以下の角度で配置されている状態をいう。したがって、８５度以上９５度以下の場合も含まれる。また、「略垂直」または「概略垂直」とは、二つの直線が６０度以上１２０度以下の角度で配置されている状態をいう。 In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case where the temperature is greater than or equal to -5 degrees and less than or equal to 5 degrees is also included. Moreover, "substantially parallel" or "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Moreover, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, cases where the angle is greater than or equal to 85 degrees and less than or equal to 95 degrees are also included. Moreover, "substantially perpendicular" or "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.
本明細書等において、計数値および計量値に関して「同一」、「同じ」、「等しい」または「均一」（これらの同意語を含む）などと言う場合は、明示されている場合を除き、プラスマイナス２０％の誤差を含むものとする。 In this specification, etc., when we refer to count values and measurement values as "same", "same", "equal", "uniform", etc. (including synonyms), we use plus, unless explicitly stated otherwise. It is assumed that an error of -20% is included.
本明細書等において、複数の要素に同じ符号を用いる場合、特に、それらを区別する必要があるときには、符号に“Ａ”、“ｂ”、“＿１”、“［ｎ］”、“［ｍ，ｎ］”などの識別用の符号を付記して記載する場合がある。例えば、導電層２４２を、導電層２４２ａ、および導電層２４２ｂに分けて示す場合がある。 In this specification, etc., when the same code is used for multiple elements, especially when it is necessary to distinguish between them, the code is "A", "b", "_1", "[n]", "[m , n]" may be added and described. For example, the conductive layer 242 may be shown divided into a conductive layer 242a and a conductive layer 242b.
（実施の形態１）
本発明の一態様に係る半導体装置１０Ａについて説明する。半導体装置１０Ａは、容量素子１１０と、容量素子１１０上のトランジスタ１００と、を有する。図１Ａは、半導体装置１０Ａの上面図である。図１Ｂは、図１ＡにＡ１−Ａ２の一点鎖線で示す部位をＹ方向から見た断面図である。なお、図１Ａの上面図では、図の明瞭化のために一部の要素を省いている。 (Embodiment 1)
A semiconductor device 10A according to one embodiment of the present invention will be described. The semiconductor device 10A includes a capacitive element 110 and a transistor 100 on the capacitive element 110. FIG. 1A is a top view of a semiconductor device 10A. FIG. 1B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 1A, viewed from the Y direction. Note that in the top view of FIG. 1A, some elements are omitted for clarity.
図１Ｃおよび図１Ｄに半導体装置１０Ａの等価回路図を示す。図１Ｃおよび図１Ｄにおいて、トランジスタ１００のソースまたはドレインの一方は配線ＢＬと電気的に接続され、他方は容量素子１１０の一方の電極と電気的に接続される。トランジスタ１００のゲートは配線ＷＬと電気的に接続される。また、容量素子１１０の他方の電極は、配線ＰＬと電気的に接続される。半導体装置１０Ａは記憶回路（「記憶素子」または「メモリセル」ともいう。）として機能する。 FIGS. 1C and 1D show equivalent circuit diagrams of the semiconductor device 10A. In FIGS. 1C and 1D, one of the source and drain of the transistor 100 is electrically connected to the wiring BL, and the other is electrically connected to one electrode of the capacitor 110. A gate of the transistor 100 is electrically connected to the wiring WL. Further, the other electrode of the capacitive element 110 is electrically connected to the wiring PL. The semiconductor device 10A functions as a memory circuit (also referred to as a "memory element" or "memory cell").
なお、図１Ｃは容量素子１１０が強誘電体を含む場合の等価回路図であり、図１Ｄは容量素子１１０が強誘電体を含まない場合の等価回路図である。 Note that FIG. 1C is an equivalent circuit diagram when the capacitive element 110 includes a ferroelectric material, and FIG. 1D is an equivalent circuit diagram when the capacitive element 110 does not include a ferroelectric material.
また、図２Ａは、図１ＡにＡ３−Ａ４の一点鎖線で示す部位をＸ方向から見た断面図である。また、図２Ｂは、図２ＡにＢ１−Ｂ２の一点鎖線で示す部位をＺ方向から見た断面を拡大した図である。また、図２Ｃは、図２ＡにＢ３−Ｂ４の一点鎖線で示す部位をＺ方向から見た断面を拡大した図である。 Further, FIG. 2A is a cross-sectional view of the portion indicated by the dashed line A3-A4 in FIG. 1A, viewed from the X direction. Further, FIG. 2B is an enlarged cross-sectional view of the portion shown by the dashed line B1-B2 in FIG. 2A when viewed from the Z direction. Further, FIG. 2C is an enlarged cross-sectional view of the portion shown by the dashed line B3-B4 in FIG. 2A when viewed from the Z direction.
本発明の一態様の半導体装置１０Ａは、絶縁層１５３と、絶縁層１５３に埋め込むように形成された導電層１５１および導電層１５２とを有する。導電層１５１および導電層１５２は、同じ材料を用いて同じ作製工程で同時に形成できる。また、化学機械研磨（ＣＭＰ：Ｃｈｅｍｉｃａｌ　Ｍｅｃｈａｎｉｃａｌ　Ｐｏｌｉｓｈｉｎｇ）法などを用いて、絶縁層１５３、導電層１５１、および導電層１５２の上面の位置（Ｚ方向の位置）を一致または略一致させることが好ましい。ＣＭＰ処理を行うことにより、試料表面の凹凸が低減し、この後形成される絶縁層および導電層の被覆性を高めることができる。 A semiconductor device 10A of one embodiment of the present invention includes an insulating layer 153, and a conductive layer 151 and a conductive layer 152 that are embedded in the insulating layer 153. The conductive layer 151 and the conductive layer 152 can be formed at the same time using the same material and in the same manufacturing process. Further, it is preferable that the positions (positions in the Z direction) of the upper surfaces of the insulating layer 153, the conductive layer 151, and the conductive layer 152 match or substantially match using a chemical mechanical polishing (CMP) method or the like. By performing the CMP treatment, the unevenness on the sample surface can be reduced, and the coverage of the insulating layer and conductive layer that will be formed later can be improved.
また、絶縁層１５３、導電層１５１、および導電層１５２の上に絶縁層１５４を有し、絶縁層１５４上に導電層１５５を有する。導電層１５１と導電層１５５は、絶縁層１５４を介して互いに重なる領域を有する。 Further, an insulating layer 154 is provided over the insulating layer 153, the conductive layer 151, and the conductive layer 152, and a conductive layer 155 is provided over the insulating layer 154. The conductive layer 151 and the conductive layer 155 have a region where they overlap with each other with the insulating layer 154 in between.
また、半導体装置１０Ａは、絶縁層１５４および導電層１５５の上に絶縁層１５７を有し、絶縁層１５７の上に絶縁層１５８を有し、絶縁層１５８の上に絶縁層１５９を有する。なお、絶縁層１５７、絶縁層１５８、および絶縁層１５９をまとめて、絶縁層１５６またはスペーサ層と呼ぶ場合がある。また、絶縁層１５９の上に導電層１６１を有する。 Further, the semiconductor device 10A has an insulating layer 157 on the insulating layer 154 and the conductive layer 155, an insulating layer 158 on the insulating layer 157, and an insulating layer 159 on the insulating layer 158. Note that the insulating layer 157, the insulating layer 158, and the insulating layer 159 may be collectively referred to as the insulating layer 156 or a spacer layer. Further, a conductive layer 161 is provided on the insulating layer 159.
また、導電層１５５の一部と重なる領域において、導電層１６１、絶縁層１５９、絶縁層１５８、および絶縁層１５７に開口１６２が設けられている（図１Ｂおよび図２Ａ参照）。半導体装置１０Ａは、開口１６２を覆う半導体層１６３を有する。半導体層１６３は、開口１６２の底部と重なる領域と、開口１６２の側面と重なる領域と、を有する。すなわち、半導体層１６３は絶縁層１５６と接する領域を有する。図１Ｂでは、半導体層１６３は、絶縁層１５７の側面と接する領域と、絶縁層１５８の側面と接する領域と、絶縁層１５９の側面と接する領域と、を有する。 Further, openings 162 are provided in the conductive layer 161, the insulating layer 159, the insulating layer 158, and the insulating layer 157 in a region overlapping with a part of the conductive layer 155 (see FIG. 1B and FIG. 2A). The semiconductor device 10A has a semiconductor layer 163 that covers the opening 162. The semiconductor layer 163 has a region that overlaps with the bottom of the opening 162 and a region that overlaps with the side surface of the opening 162. That is, the semiconductor layer 163 has a region in contact with the insulating layer 156. In FIG. 1B, the semiconductor layer 163 has a region in contact with the side surface of the insulating layer 157, a region in contact with the side surface of the insulating layer 158, and a region in contact with the side surface of the insulating layer 159.
また、半導体層１６３は導電層１５５と接する領域と、導電層１６１と接する領域を有する。すなわち、半導体層１６３の一部が導電層１５５と電気的に接続し、半導体層１６３の他の一部が導電層１６１と電気的に接続する。また、半導体層１６３は、導電層１６１の端部を越えて延在する領域を有してもよい（図１Ａおよび図２Ａ参照）。 Further, the semiconductor layer 163 has a region in contact with the conductive layer 155 and a region in contact with the conductive layer 161. That is, a portion of the semiconductor layer 163 is electrically connected to the conductive layer 155, and another portion of the semiconductor layer 163 is electrically connected to the conductive layer 161. Further, the semiconductor layer 163 may have a region extending beyond the edge of the conductive layer 161 (see FIGS. 1A and 2A).
また、絶縁層１５９、導電層１６１、および半導体層１６３の上に絶縁層１６４を有する。また、絶縁層１６４の上に導電層１６５を有する。導電層１６５は開口１６２と重なる領域を有し、当該領域において、絶縁層１６４および半導体層１６３を介して開口１６２の側面および底部と重なる領域を有する（図１Ｂ、図２Ａ、図２Ｂ、および図２Ｃ参照）。 Further, an insulating layer 164 is provided over the insulating layer 159, the conductive layer 161, and the semiconductor layer 163. Further, a conductive layer 165 is provided on the insulating layer 164. The conductive layer 165 has a region that overlaps with the opening 162, and in this region, a region that overlaps with the side surface and bottom of the opening 162 via the insulating layer 164 and the semiconductor layer 163 (see FIG. 1B, FIG. 2A, FIG. 2B, and FIG. (See 2C).
半導体層１６３の膜厚は、１ｎｍ以上、３ｎｍ以上、または５ｎｍ以上であって、２０ｎｍ以下、１５ｎｍ以下、１２ｎｍ以下、または１０ｎｍ以下であることが好ましい。絶縁層１６４の膜厚は、０．５ｎｍ以上１５ｎｍ以下とするのが好ましく、０．５ｎｍ以上１２ｎｍ以下とするのがより好ましく、０．５ｎｍ以上１０ｎｍ以下とすることがさらに好ましい。絶縁層１６４は、少なくとも一部において、上記のような膜厚の領域を有していればよい。 The thickness of the semiconductor layer 163 is preferably 1 nm or more, 3 nm or more, or 5 nm or more, and 20 nm or less, 15 nm or less, 12 nm or less, or 10 nm or less. The thickness of the insulating layer 164 is preferably 0.5 nm or more and 15 nm or less, more preferably 0.5 nm or more and 12 nm or less, and even more preferably 0.5 nm or more and 10 nm or less. The insulating layer 164 only needs to have a region with the thickness described above at least in part.
また、絶縁層１６４の上に絶縁層１６６を有する。導電層１６５および絶縁層１６６の上面の位置（Ｚ方向の位置）を一致または略一致させることが好ましい。例えば、ＣＭＰ処理などを行うことにより、導電層１６５および絶縁層１６６の上面の位置（Ｚ方向の位置）を一致または略一致させることで、この後形成される絶縁層および導電層の被覆性を高めることができる。 Further, an insulating layer 166 is provided on the insulating layer 164. It is preferable that the positions (positions in the Z direction) of the upper surfaces of the conductive layer 165 and the insulating layer 166 match or substantially match. For example, by performing CMP processing or the like, the positions of the upper surfaces of the conductive layer 165 and the insulating layer 166 (positions in the Z direction) are made to match or substantially match, thereby improving the coverage of the insulating layer and the conductive layer that will be formed later. can be increased.
また、導電層１６５および絶縁層１６６の上に絶縁層１６７を有する。また、導電層１５２と重なる領域において、絶縁層１６７、絶縁層１６６、絶縁層１６４、導電層１６１、絶縁層１５９、絶縁層１５８、絶縁層１５７、および絶縁層１５４の一部に埋め込むように導電層１６８を有する。導電層１６８は、導電層１６１および導電層１５２と電気的に接続される。導電層１６８および導電層１５２は、コンタクトプラグとして機能する。 Further, an insulating layer 167 is provided over the conductive layer 165 and the insulating layer 166. Further, in the region overlapping with the conductive layer 152, the conductive layer 167, the insulating layer 166, the insulating layer 164, the conductive layer 161, the insulating layer 159, the insulating layer 158, the insulating layer 157, and a part of the insulating layer 154 are embedded. It has a layer 168. Conductive layer 168 is electrically connected to conductive layer 161 and conductive layer 152. Conductive layer 168 and conductive layer 152 function as contact plugs.
また、導電層１５５は容量素子１１０の一方の電極として機能する。導電層１５１は容量素子１１０の他方の電極として機能する。絶縁層１５４の、導電層１５５および導電層１５１と重なる領域が容量素子１１０の誘電体として機能する。 Further, the conductive layer 155 functions as one electrode of the capacitive element 110. The conductive layer 151 functions as the other electrode of the capacitive element 110. A region of the insulating layer 154 overlapping with the conductive layer 155 and the conductive layer 151 functions as a dielectric of the capacitive element 110.
導電層１６５および導電層１５１のそれぞれはＹ方向に延在する。導電層１６５は配線ＷＬまたは配線ＷＬの一部として機能し、導電層１５１は配線ＰＬまたは配線ＰＬの一部として機能する。また、導電層１６８および導電層１５２は、配線ＢＬまたは配線ＢＬの一部として機能する。 Each of conductive layer 165 and conductive layer 151 extends in the Y direction. The conductive layer 165 functions as the wiring WL or a part of the wiring WL, and the conductive layer 151 functions as the wiring PL or a part of the wiring PL. Further, the conductive layer 168 and the conductive layer 152 function as the wiring BL or a part of the wiring BL.
本発明の一態様である半導体装置１０Ａは、トランジスタ１００と容量素子１１０を重ねて設ける。トランジスタ１００と容量素子１１０を重ねて設けることにより、半導体装置１０Ａの占有面積を低減できる。 In a semiconductor device 10A that is one embodiment of the present invention, a transistor 100 and a capacitor 110 are provided in an overlapping manner. By overlapping the transistor 100 and the capacitor 110, the area occupied by the semiconductor device 10A can be reduced.
＜トランジスタ１００＞
導電層１６１は、トランジスタ１００のソース電極またはドレイン電極の一方として機能する。また、導電層１５５は、トランジスタ１００のソース電極またはドレイン電極の他方として機能する。例えば、導電層１６１がトランジスタ１００のドレイン電極として機能する場合、導電層１５５はトランジスタ１００のソース電極として機能する。なお、導電層１６１は、配線ＢＬまたは配線ＢＬの一部として機能するともいえる。 <Transistor 100>
The conductive layer 161 functions as either a source electrode or a drain electrode of the transistor 100. Further, the conductive layer 155 functions as the other of the source electrode and the drain electrode of the transistor 100. For example, if the conductive layer 161 functions as a drain electrode of the transistor 100, the conductive layer 155 functions as a source electrode of the transistor 100. Note that the conductive layer 161 can also be said to function as the wiring BL or a part of the wiring BL.
半導体層１６３は、トランジスタ１００のチャネルが形成される半導体層（チャネル形成領域を含む半導体層）として機能し、絶縁層１６４はゲート絶縁層として機能し、導電層１６５はゲート電極として機能する。よって、トランジスタ１００は、開口１６２を含む領域に設けられていると言える。 The semiconductor layer 163 functions as a semiconductor layer in which a channel of the transistor 100 is formed (a semiconductor layer including a channel formation region), the insulating layer 164 functions as a gate insulating layer, and the conductive layer 165 functions as a gate electrode. Therefore, it can be said that the transistor 100 is provided in a region including the opening 162.
トランジスタ１００はソース電極とドレイン電極がＺ方向に配置される。すなわち、トランジスタ１００のソースとドレインは、それぞれが異なる高さに配置される。言い換えると、トランジスタ１００のソースとドレインは、それぞれがＺ方向の異なる位置に配置される。このようなトランジスタを、「縦チャネル型トランジスタ」、「縦型チャネルトランジスタ」、「縦型トランジスタ」、または「ＶＦＥＴ（Ｖｅｒｔｉｃａｌ　Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）」ともいう。 The transistor 100 has a source electrode and a drain electrode arranged in the Z direction. That is, the source and drain of the transistor 100 are arranged at different heights. In other words, the source and drain of the transistor 100 are arranged at different positions in the Z direction. Such a transistor is also referred to as a "vertical channel transistor," "vertical channel transistor," "vertical transistor," or "VFET (Vertical Field Effect Transistor)."
本発明の一態様に係る縦チャネル型トランジスタは、ソース電極とドレイン電極がＺ方向に配置される。すなわち、チャネル形成領域、ソース領域、およびドレイン領域がＺ方向に配置される。縦型トランジスタは、チャネル形成領域、ソース領域、およびドレイン領域が、ＸＹ平面上に別々に設けられていた従来のトランジスタを比較して、トランジスタ１００の占有面積を低減できる。 In the vertical channel transistor according to one embodiment of the present invention, a source electrode and a drain electrode are arranged in the Z direction. That is, the channel formation region, the source region, and the drain region are arranged in the Z direction. The vertical transistor can reduce the area occupied by the transistor 100 compared to a conventional transistor in which a channel formation region, a source region, and a drain region are provided separately on the XY plane.
また、縦チャネル型トランジスタを半導体装置に用いることにより、半導体装置の占有面積を低減できる。半導体装置に縦チャネル型トランジスタを用いることにより、半導体装置の高集積化を実現できる。また、当該半導体装置を用いた記憶装置の単位面積当たりの記憶容量を大きくすることができる。 Further, by using a vertical channel transistor in a semiconductor device, the area occupied by the semiconductor device can be reduced. By using vertical channel transistors in a semiconductor device, high integration of the semiconductor device can be achieved. Furthermore, the storage capacity per unit area of a storage device using the semiconductor device can be increased.
また、従来のトランジスタでは、チャネル長がフォトリソグラフィの露光限界で設定されていた。本発明の一態様に係る縦チャネル型トランジスタは、絶縁層１５６または絶縁層１５８の膜厚でチャネル長を設定することができる。よって、トランジスタ１００のチャネル長を、フォトリソグラフィの露光限界以下の非常に微細な構造（例えば、６０ｎｍ以下、５０ｎｍ以下、４０ｎｍ以下、３０ｎｍ以下、２０ｎｍ以下、または１０ｎｍ以下であって、１ｎｍ以上、または５ｎｍ以上）にすることができる。これにより、トランジスタ１００のオン電流が大きくなり、周波数特性の向上を図ることができる。縦チャネル型トランジスタを用いることにより、動作速度が速い半導体装置を提供できる。 Furthermore, in conventional transistors, the channel length is set by the exposure limit of photolithography. In the vertical channel transistor according to one embodiment of the present invention, the channel length can be set by the thickness of the insulating layer 156 or the insulating layer 158. Therefore, the channel length of the transistor 100 is set to a very fine structure below the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, but 1 nm or more, or 5 nm or more). As a result, the on-state current of the transistor 100 increases, and frequency characteristics can be improved. By using a vertical channel transistor, a semiconductor device with high operating speed can be provided.
なお、トランジスタ１００のチャネル長Ｌ、チャネル幅Ｗなどについては、追って詳細に説明する。 Note that the channel length L, channel width W, etc. of the transistor 100 will be explained in detail later.
＜容量素子１１０＞
導電層１５１と導電層１５５が、絶縁層１５４を介して互いに重なる領域が容量素子１１０として機能する。絶縁層１５４に強誘電体を用いることが好ましい。強誘電体は、外部から電場を与えることによって内部に分極が生じ、かつ当該電場をゼロにしても分極が残る性質を有する。このため、当該材料を誘電体として用いた容量素子（「強誘電体キャパシタ」ともいう。）を用いて、不揮発性の記憶素子を実現できる。 <Capacitive element 110>
A region where the conductive layer 151 and the conductive layer 155 overlap each other with the insulating layer 154 in between functions as the capacitive element 110. It is preferable to use a ferroelectric material for the insulating layer 154. Ferroelectric materials have the property that polarization occurs internally when an electric field is applied from the outside, and the polarization remains even when the electric field is reduced to zero. Therefore, a nonvolatile memory element can be realized using a capacitive element (also referred to as a "ferroelectric capacitor") using this material as a dielectric.
また、容量素子１１０を強誘電体キャパシタとして機能させる場合は、強誘電体である絶縁層１５４と接する導電層１５１および導電層１５５として、絶縁層１５４に分極を生じさせやすい材料を用いることが好ましい。例えば、導電層１５１および導電層１５５として窒化チタンを用いることが好ましい。 Furthermore, when the capacitive element 110 functions as a ferroelectric capacitor, it is preferable to use a material that easily causes polarization in the insulating layer 154 as the conductive layer 151 and the conductive layer 155 in contact with the insulating layer 154 which is a ferroelectric material. . For example, it is preferable to use titanium nitride as the conductive layer 151 and the conductive layer 155.
なお、強誘電体キャパシタを用いた、不揮発性の記憶素子は、「ＦｅＲＡＭ」または「強誘電体メモリ」などと呼ばれる場合がある。強誘電性を有しうる材料については追って詳細に説明する。 Note that a nonvolatile memory element using a ferroelectric capacitor is sometimes called a "FeRAM" or a "ferroelectric memory." Materials that can have ferroelectricity will be explained in detail later.
また、絶縁層１５４に比誘電率が高い材料（「ｈｉｇｈ−ｋ材料」ともいう。）を用いてもよい。絶縁層１５４としてｈｉｇｈ−ｋ材料を用いることで容量素子１１０に必要な静電容量を確保し、かつ絶縁層１５４を厚くすることができる。絶縁層１５４を厚くすることで、導電層１５１と導電層１５５の間の絶縁耐圧が高まり、静電破壊が抑制される。よって、容量素子１１０の信頼性が向上する。よって、容量素子１１０を用いた半導体装置の信頼性が向上する。 Further, a material with a high dielectric constant (also referred to as a "high-k material") may be used for the insulating layer 154. By using a high-k material as the insulating layer 154, the capacitance necessary for the capacitive element 110 can be ensured, and the insulating layer 154 can be made thick. By increasing the thickness of the insulating layer 154, the dielectric strength voltage between the conductive layer 151 and the conductive layer 155 is increased, and electrostatic breakdown is suppressed. Therefore, the reliability of the capacitive element 110 is improved. Therefore, the reliability of the semiconductor device using the capacitor 110 is improved.
＜半導体装置の構成材料＞
本発明の一態様に係る半導体装置１０Ａに用いることができる材料の一例について説明する。 <Constituent materials of semiconductor devices>
An example of a material that can be used for the semiconductor device 10A according to one embodiment of the present invention will be described.
［基板］
半導体装置１０Ａを基板上に設ける場合、当該基板に用いる材料に大きな制限はない。目的に応じて、透光性の有無および加熱処理に耐えうる程度の耐熱性などを勘案して決定すればよい。例えば、絶縁体基板、半導体基板、または導電体基板を用いればよい。絶縁体基板としては、例えばバリウムホウケイ酸ガラスおよびアルミノホウケイ酸ガラスなどのガラス基板、セラミックス基板、石英基板、サファイア基板、安定化ジルコニア基板（イットリア安定化ジルコニア基板など）などを用いることができる。また、半導体基板、可撓性基板（フレキシブル基板）、樹脂基板などを用いてもよい。 [substrate]
When the semiconductor device 10A is provided on a substrate, there are no major restrictions on the material used for the substrate. Depending on the purpose, the material may be determined by taking into account the presence or absence of translucency and heat resistance to withstand heat treatment. For example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used. As the insulating substrate, for example, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria stabilized zirconia substrate), etc. can be used. Further, a semiconductor substrate, a flexible substrate, a resin substrate, or the like may be used.
半導体基板としては、例えば、シリコン、もしくはゲルマニウムなどを材料とした半導体基板、または炭化シリコン、シリコンゲルマニウム、ヒ化ガリウム、リン化インジウム、酸化亜鉛、もしくは酸化ガリウムを材料とした化合物半導体基板などがある。さらには、前述の半導体基板内部に絶縁体領域を有する半導体基板、例えば、ＳＯＩ（Ｓｉｌｉｃｏｎ　Ｏｎ　Ｉｎｓｕｌａｔｏｒ）基板などがある。また、半導体基板は、単結晶半導体であってもよいし、多結晶半導体であってもよい。 Examples of the semiconductor substrate include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. . Furthermore, there is a semiconductor substrate having an insulator region inside the semiconductor substrate described above, such as an SOI (Silicon On Insulator) substrate. Furthermore, the semiconductor substrate may be a single crystal semiconductor or a polycrystalline semiconductor.
導電体基板としては、黒鉛基板、金属基板、合金基板、導電性樹脂基板などがある。または、金属の窒化物を有する基板、金属の酸化物を有する基板などがある。さらには、絶縁体基板に導電体または半導体が設けられた基板、半導体基板に導電体または絶縁体が設けられた基板、導電体基板に半導体または絶縁体が設けられた基板などがある。 Examples of the conductive substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, there are substrates containing metal nitrides, substrates containing metal oxides, and the like. Furthermore, there are substrates in which an insulator substrate is provided with a conductor or a semiconductor, a semiconductor substrate in which a conductor or an insulator is provided, and a conductor substrate in which a semiconductor or an insulator is provided.
可撓性基板または樹脂基板などの材料としては、例えば、ポリエチレンテレフタレート（ＰＥＴ）、ポリエチレンナフタレート（ＰＥＮ）等のポリエステル樹脂、ポリアクリロニトリル樹脂、アクリル樹脂、ポリイミド樹脂、ポリメチルメタクリレート樹脂、ポリカーボネイト（ＰＣ）樹脂、ポリエーテルスルホン（ＰＥＳ）樹脂、ポリアミド樹脂（ナイロン、アラミド等）、ポリシロキサン樹脂、シクロオレフィン樹脂、ポリスチレン樹脂、ポリアミドイミド樹脂、ポリウレタン樹脂、ポリ塩化ビニル樹脂、ポリ塩化ビニリデン樹脂、ポリプロピレン樹脂、ポリテトラフルオロエチレン（ＰＴＦＥ）樹脂、ＡＢＳ樹脂、セルロースナノファイバーなどを用いることができる。 Examples of materials for the flexible substrate or resin substrate include polyester resins such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile resins, acrylic resins, polyimide resins, polymethyl methacrylate resins, and polycarbonate (PC). ) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin , polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc. can be used.
基板として上記材料を用いることにより、トランジスタ１００を含む軽量な半導体装置を提供できる。また、基板として上記材料を用いることにより、衝撃に強い半導体装置を提供できる。また、基板として上記材料を用いることにより、破損しにくい半導体装置を提供できる。 By using the above material for the substrate, a lightweight semiconductor device including the transistor 100 can be provided. Furthermore, by using the above material as a substrate, a semiconductor device that is resistant to impact can be provided. Further, by using the above material as a substrate, a semiconductor device that is less likely to be damaged can be provided.
または、これらの基板に素子が設けられたものを用いてもよい。基板に設けられる素子としては、容量素子、抵抗素子、スイッチ素子、発光素子、記憶素子などがある。 Alternatively, these substrates provided with elements may be used. Elements provided on the substrate include capacitive elements, resistive elements, switch elements, light emitting elements, and memory elements.
［絶縁層］
絶縁層としては、絶縁性を有する酸化物、窒化物、酸化窒化物、窒化酸化物、金属酸化物、金属酸化窒化物、金属窒化酸化物などを用いることができる。例えば、絶縁層として、窒化アルミニウム、酸化アルミニウム、窒化酸化アルミニウム、酸化窒化アルミニウム、酸化マグネシウム、窒化シリコン、酸化シリコン、窒化酸化シリコン、酸化窒化シリコン、酸化ガリウム、酸化ゲルマニウム、酸化イットリウム、酸化ジルコニウム、酸化ランタン、酸化ネオジム、酸化ハフニウム、酸化タンタル、アルミニウムシリケートなどから選ばれた絶縁性材料を、単層でまたは積層して用いる。また、酸化物材料、窒化物材料、酸化窒化物材料、窒化酸化物材料のうち、複数の材料を混合した材料を用いてもよい。 [Insulating layer]
As the insulating layer, an insulating oxide, nitride, oxynitride, nitride oxide, metal oxide, metal oxynitride, metal nitride oxide, or the like can be used. For example, as an insulating layer, aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, An insulating material selected from lanthanum, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, etc. is used in a single layer or in a stacked manner. Alternatively, a mixture of a plurality of materials among oxide materials, nitride materials, oxynitride materials, and nitrided oxide materials may be used.
なお、本明細書などにおいて、窒化酸化物とは、酸素よりも窒素の含有量が多い材料をいう。また、酸化窒化物とは、窒素よりも酸素の含有量が多い材料をいう。なお、各元素の含有量は、例えば、ラザフォード後方散乱法（ＲＢＳ：Ｒｕｔｈｅｒｆｏｒｄ　Ｂａｃｋｓｃａｔｔｅｒｉｎｇ　Ｓｐｅｃｔｒｏｍｅｔｒｙ）等を用いて測定することができる。 Note that in this specification and the like, nitrided oxide refers to a material containing more nitrogen than oxygen. Further, oxynitride refers to a material containing more oxygen than nitrogen. Note that the content of each element can be measured using, for example, Rutherford Backscattering Spectrometry (RBS).
トランジスタの微細化、および高集積化が進むと、ゲート絶縁層の薄膜化により、リーク電流などの問題が生じる場合がある。ゲート絶縁層として機能する絶縁層にｈｉｇｈ−ｋ材料（高誘電率材料。比誘電率の高い材料。）を用いることで、物理膜厚を保ちながら、トランジスタ動作時のゲート電位の低減が可能となる。また、絶縁層として、チタン酸ジルコン酸鉛（ＰＺＴ）、チタン酸ストロンチウム（ＳｒＴｉＯ３）、（Ｂａ，Ｓｒ）ＴｉＯ３（ＢＳＴ）などの誘電率が高い物質を用いることができる場合もある。一方、層間膜として機能する絶縁層には、比誘電率が低い材料を用いることで、配線間に生じる寄生容量を低減することができる。したがって、絶縁層に求められる機能に応じて、材料を選択するとよい。 As transistors become smaller and more highly integrated, gate insulating layers become thinner, which may cause problems such as leakage current. By using a high-k material (high dielectric constant material, material with high relative permittivity) for the insulating layer that functions as the gate insulating layer, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. Become. Further, as the insulating layer, a material having a high dielectric constant such as lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), (Ba,Sr)TiO 3 (BST) may be used in some cases. On the other hand, by using a material with a low dielectric constant for the insulating layer that functions as an interlayer film, parasitic capacitance occurring between wirings can be reduced. Therefore, the material should be selected depending on the function required of the insulating layer.
また、比誘電率の高い材料としては、酸化ガリウム、酸化ハフニウム、酸化ジルコニウム、アルミニウムおよびハフニウムを有する酸化物、アルミニウムおよびハフニウムを有する酸化窒化物、シリコンおよびハフニウムを有する酸化物、シリコンおよびハフニウムを有する酸化窒化物、またはシリコンおよびハフニウムを有する窒化物などがある。 Materials with high dielectric constants include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, and oxides containing silicon and hafnium. These include oxynitrides or nitrides with silicon and hafnium.
また、比誘電率が低い材料としては、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、窒化シリコン、フッ素を添加した酸化シリコン、炭素を添加した酸化シリコン、炭素および窒素を添加した酸化シリコン、空孔を有する酸化シリコン、または樹脂などがある。 In addition, materials with low dielectric constants include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, and vacancies. There are silicon oxides and resins that have
絶縁性材料の形成方法は特に限定されず、蒸着法、ＡＬＤ法、ＣＶＤ法、スパッタリング法、スピンコート法などの各種形成方法を用いることができる。 The method for forming the insulating material is not particularly limited, and various methods such as vapor deposition, ALD, CVD, sputtering, and spin coating can be used.
例えば、絶縁層１５３および絶縁層１６７は、不純物が透過しにくい絶縁性材料を用いて形成することが好ましい。例えば、ホウ素、炭素、窒素、酸素、フッ素、マグネシウム、アルミニウム、シリコン、リン、塩素、アルゴン、ガリウム、ゲルマニウム、イットリウム、ジルコニウム、ランタン、ネオジム、ハフニウムまたはタンタルを含む絶縁材料を、単層で、または積層で用いればよい。不純物が透過しにくい絶縁性材料の一例として、酸化アルミニウム、窒化アルミニウム、酸化窒化アルミニウム、窒化酸化アルミニウム、酸化ガリウム、酸化ゲルマニウム、酸化イットリウム、酸化ジルコニウム、酸化ランタン、酸化ネオジム、酸化ハフニウム、酸化タンタル、窒化シリコンなどを挙げることができる。 For example, the insulating layer 153 and the insulating layer 167 are preferably formed using an insulating material through which impurities hardly pass. For example, insulating materials containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorous, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum, in a single layer or It may be used in a laminated manner. Examples of insulating materials that are difficult for impurities to pass through include aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, Examples include silicon nitride.
絶縁層１５３に不純物が透過しにくい絶縁性材料を用いることで、絶縁層１５３よりも下側からの不純物の拡散を抑制し、トランジスタ１００の信頼性を高めることができる。すなわち、トランジスタ１００を含む半導体装置の信頼性を高めることができる。絶縁層１６７に不純物が透過しにくい絶縁性材料を用いることで、絶縁層１６７よりも上側からの不純物の拡散を抑制し、トランジスタ１００の信頼性を高めることができる。すなわち、トランジスタ１００を含む半導体装置の信頼性を高めることができる。 By using an insulating material through which impurities hardly pass through the insulating layer 153, diffusion of impurities from below the insulating layer 153 can be suppressed, and the reliability of the transistor 100 can be improved. That is, the reliability of the semiconductor device including the transistor 100 can be improved. By using an insulating material through which impurities are difficult to pass through for the insulating layer 167, diffusion of impurities from above the insulating layer 167 can be suppressed, and the reliability of the transistor 100 can be improved. That is, the reliability of the semiconductor device including the transistor 100 can be improved.
また、絶縁層として平坦化層として機能できる絶縁層を用いてもよい。平坦化層として機能する材料としては、アクリル樹脂、ポリイミド、エポキシ樹脂、ポリアミド、ポリイミドアミド、シロキサン樹脂、ベンゾシクロブテン樹脂、フェノール樹脂、およびこれらの前駆体等が挙げられる。また上記有機材料の他に、ｌｏｗ−ｋ材料（低誘電率材料。比誘電率が小さい材料。）、シロキサン樹脂、ＰＳＧ（リンガラス）、ＢＰＳＧ（リンボロンガラス）等を用いることができる。なお、これらの材料で形成される絶縁層を複数積層してもよい。 Furthermore, an insulating layer that can function as a planarization layer may be used as the insulating layer. Examples of materials that function as the flattening layer include acrylic resin, polyimide, epoxy resin, polyamide, polyimide amide, siloxane resin, benzocyclobutene resin, phenol resin, and precursors thereof. In addition to the above-mentioned organic materials, low-k materials (low dielectric constant materials, materials with small dielectric constants), siloxane resins, PSG (phosphorus glass), BPSG (phosphorus boron glass), etc. can be used. Note that a plurality of insulating layers formed of these materials may be stacked.
なお、シロキサン樹脂とは、シロキサン系材料を出発材料として形成されたＳｉ−Ｏ−Ｓｉ結合を含む樹脂に相当する。シロキサン樹脂は置換基としては有機基（例えばアルキル基またはアリール基）またはフルオロ基を用いても良い。また、有機基はフルオロ基を有していても良い。 Note that the siloxane resin corresponds to a resin containing Si-O-Si bonds formed using a siloxane-based material as a starting material. In the siloxane resin, an organic group (for example, an alkyl group or an aryl group) or a fluoro group may be used as a substituent. Further, the organic group may have a fluoro group.
また、容量素子１１０の誘電体として機能する絶縁層１５４として、２層の酸化ジルコニウムの間に酸化アルミニウムを挟んだ３層の絶縁層（「ＺＡＺ」ともいう。）を用いてもよい。ＺＡＺは比誘電率が高い材料であり、容量素子１１０の誘電体としてＺＡＺを用いることで、容量素子１１０の占有面積を低減できる。 Further, as the insulating layer 154 that functions as a dielectric of the capacitive element 110, three insulating layers (also referred to as "ZAZ") in which aluminum oxide is sandwiched between two layers of zirconium oxide may be used. ZAZ is a material with a high dielectric constant, and by using ZAZ as the dielectric of the capacitive element 110, the area occupied by the capacitive element 110 can be reduced.
前述した通り、絶縁層１５４として強誘電性を有しうる材料を用いて、容量素子１１０を強誘電体キャパシタとして機能させることが好ましい。 As described above, it is preferable to use a material that can have ferroelectricity as the insulating layer 154 so that the capacitive element 110 functions as a ferroelectric capacitor.
強誘電性を有しうる材料として、例えば、酸化ハフニウムを用いることが好ましい。または、強誘電性を有しうる材料として、酸化ジルコニウム、ＨｆＺｒＯＸ（Ｘは０よりも大きい実数とする。以下、「ＨｆＺｒＯｘ」ともいう。）などの金属酸化物を用いてもよい。または、強誘電性を有しうる材料として、酸化ハフニウムに元素Ｊ１（ここでの元素Ｊ１は、ジルコニウム（Ｚｒ）、シリコン（Ｓｉ）、アルミニウム（Ａｌ）、ガドリニウム（Ｇｄ）、イットリウム（Ｙ）、ランタン（Ｌａ）、ストロンチウム（Ｓｒ）などから選ばれた一つ又は複数。）を添加した材料を用いてもよい。 For example, it is preferable to use hafnium oxide as the material that can have ferroelectricity. Alternatively, a metal oxide such as zirconium oxide or HfZrOx ( X is a real number larger than 0; hereinafter also referred to as "HfZrOx") may be used as a material that can have ferroelectricity. Alternatively, as a material that can have ferroelectricity, hafnium oxide can be combined with element J1 (here, element J1 is zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), A material to which one or more selected from lanthanum (La), strontium (Sr), etc. is added may be used.
ここで、ハフニウム原子と元素Ｊ１の原子数の比は適宜設定することができる。例えば、ハフニウム原子とジルコニウム原子の原子数を１：１またはその近傍にすればよい。又は、強誘電性を有しうる材料としては、酸化ジルコニウムに元素Ｊ２（ここでの元素Ｊ２は、ハフニウム（Ｈｆ）、シリコン（Ｓｉ）、アルミニウム（Ａｌ）、ガドリニウム（Ｇｄ）、イットリウム（Ｙ）、ランタン（Ｌａ）、ストロンチウム（Ｓｒ）などから選ばれた一つ又は複数。）を添加した材料などを用いることができる。また、ジルコニウム原子と元素Ｊ２の原子数の比は適宜設定することができ、例えば、ジルコニウム原子と元素Ｊ２の原子数を１：１またはその近傍にすればよい。また、強誘電性を有しうる材料として、チタン酸鉛（ＰｂＴｉＯＸ）、チタン酸バリウムストロンチウム（ＢＳＴ）、チタン酸ストロンチウム、チタン酸ジルコン酸鉛（ＰＺＴ）、タンタル酸ビスマス酸ストロンチウム（ＳＢＴ）、ビスマスフェライト（ＢＦＯ）、チタン酸バリウム、などのペロブスカイト構造を有する圧電性セラミックスを用いてもよい。 Here, the ratio of the number of atoms of hafnium atoms and element J1 can be set as appropriate. For example, the number of hafnium atoms and zirconium atoms may be set to 1:1 or around 1:1. Alternatively, materials that can have ferroelectricity include zirconium oxide and element J2 (here, element J2 is hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y)). , lanthanum (La), strontium (Sr), etc.) can be used. Further, the ratio of the number of atoms of zirconium atoms and element J2 can be set as appropriate, for example, the number of atoms of zirconium atoms and element J2 may be set to 1:1 or around 1:1. In addition, as materials that can have ferroelectricity, lead titanate (PbTiO x ), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuthate tantalate (SBT), Piezoelectric ceramics having a perovskite structure, such as bismuth ferrite (BFO) and barium titanate, may also be used.
また、強誘電性を有しうる材料としては、窒化アルミニウムスカンジウム（Ａｌ１−ａＳｃａＮｂ（ａは０より大きく、０．５より小さい実数であり、ｂは１またはその近傍の値である。以下、単にＡｌＳｃＮとして示す。））、Ａｌ−Ｇａ−Ｓｃ窒化物、Ｇａ−Ｓｃ窒化物などを用いることができる。また、強誘電性を有しうる材料としては、元素Ｍ１と、元素Ｍ２と、窒素と、を有する金属窒化物を用いることができる。ここで、元素Ｍ１は、アルミニウム（Ａｌ）、ガリウム（Ｇａ）、インジウム（Ｉｎ）などから選ばれた一つまたは複数である。また、元素Ｍ２は、ホウ素（Ｂ）、スカンジウム（Ｓｃ）、イットリウム（Ｙ）、ランタノイド（ランタン（Ｌａ）、セリウム（Ｃｅ）、プラセオジム（Ｐｒ）、ネオジム（Ｎｄ）、プロメチウム（Ｐｍ）、サマリウム（Ｓｍ）、ユウロピウム（Ｅｕ）、ガドリニウム（Ｇｄ）、テルビウム（Ｔｂ）、ジスプロシウム（Ｄｙ）、ホルミウム（Ｈｏ）、エルビウム（Ｅｒ）、ツリウム（Ｔｍ）、イッテルビウム（Ｙｂ）、及びルテチウム（Ｌｕ））、アクチノイド（アクチニウム（Ａｃ）からローレンシウム（Ｌｒ）までの１５の元素）、チタン（Ｔｉ）、ジルコニウム（Ｚｒ）、ハフニウム（Ｈｆ）、バナジウム（Ｖ）、ニオブ（Ｎｂ）、タンタル（Ｔａ）、クロム（Ｃｒ）などから選ばれた一つまたは複数である。なお、元素Ｍ１の原子数と元素Ｍ２の原子数の比は適宜設定することができる。また、元素Ｍ１と、窒素と、を有する金属酸化物は、元素Ｍ２を含まなくても、強誘電性を有する場合がある。また、強誘電性を有しうる材料としては、上記金属窒化物に元素Ｍ３が添加された材料を用いることができる。なお、元素Ｍ３は、マグネシウム（Ｍｇ）、カルシウム（Ｃａ）、ストロンチウム（Ｓｒ）、亜鉛（Ｚｎ）、カドミウム（Ｃｄ）などから選ばれた一つまたは複数である。ここで、元素Ｍ１の原子数、元素Ｍ２の原子数、および元素Ｍ３の原子数の比は適宜設定することができる。なお、上記の金属窒化物は、少なくとも、第１３族元素と、第１５族元素である窒素とを含むため、当該金属窒化物を、１３−１５族の強誘電体、１３族窒化物の強誘電体などと呼ぶ場合がある。 In addition, materials that can have ferroelectricity include aluminum scandium nitride (Al 1-a Sc a N b (a is a real number greater than 0 and less than 0.5, and b is a value of 1 or a value near it). (hereinafter simply referred to as AlScN)), Al-Ga-Sc nitride, Ga-Sc nitride, etc. can be used. Further, as a material that can have ferroelectricity, a metal nitride containing element M1, element M2, and nitrogen can be used. Here, the element M1 is one or more selected from aluminum (Al), gallium (Ga), indium (In), and the like. Element M2 is boron (B), scandium (Sc), yttrium (Y), lanthanoids (lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium ( Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu)), Actinides (15 elements from actinium (Ac) to lawrenium (Lr)), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium ( Cr), etc. Note that the ratio between the number of atoms of element M1 and the number of atoms of element M2 can be set as appropriate. Further, a metal oxide containing element M1 and nitrogen may have ferroelectricity even if it does not contain element M2. Moreover, as a material that can have ferroelectricity, a material obtained by adding element M3 to the metal nitride described above can be used. Note that the element M3 is one or more selected from magnesium (Mg), calcium (Ca), strontium (Sr), zinc (Zn), cadmium (Cd), and the like. Here, the ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be set as appropriate. In addition, since the above metal nitride contains at least a group 13 element and nitrogen, which is a group 15 element, the metal nitride can be used as a group 13-15 ferroelectric material or a group 13 nitride ferroelectric material. Sometimes called dielectric.
また、強誘電性を有しうる材料としては、ＳｒＴａＯ２Ｎ、ＢａＴａＯ２Ｎなどのペロブスカイト型酸窒化物、κアルミナ型構造のＧａＦｅＯ３などを用いることができる。 Furthermore, as the material that can have ferroelectricity, perovskite oxynitrides such as SrTaO 2 N and BaTaO 2 N, GaFeO 3 having a κ alumina structure, and the like can be used.
また、強誘電性を有しうる材料としては、例えば、上記に列挙した材料から選ばれた複数の材料からなる混合物又は化合物を用いることができる。又は、強誘電性を有しうる材料としては、上記に列挙した材料から選ばれた複数の材料からなる積層構造とすることができる。ところで、上記に列挙した材料は、成膜条件だけでなく、各種プロセスなどによっても結晶構造、または特性が変わり得る可能性があるため、本明細書等では強誘電性を発現する材料を強誘電体と呼ぶだけでなく、強誘電性を有しうる材料または強誘電性を有する材料とも呼んでいる。 Furthermore, as the material that can have ferroelectricity, for example, a mixture or compound consisting of a plurality of materials selected from the materials listed above can be used. Alternatively, the material capable of having ferroelectricity may have a laminated structure made of a plurality of materials selected from the materials listed above. By the way, since the crystal structure or characteristics of the materials listed above may change not only due to film formation conditions but also due to various processes, in this specification etc., materials that exhibit ferroelectricity are referred to as In addition to being called a material, it is also called a material that can have ferroelectric properties or a material that has ferroelectric properties.
強誘電性を有しうる材料として、酸化ハフニウム、あるいは酸化ハフニウムおよび酸化ジルコニウムを有する材料（代表的にはＨｆＺｒＯｘ）は、数ｎｍといった薄膜に加工しても強誘電性を有しうることができるため好適である。 As a material that can have ferroelectricity, hafnium oxide or a material containing hafnium oxide and zirconium oxide (typically HfZrOx) can have ferroelectricity even when processed into a thin film of several nm. Therefore, it is suitable.
ここで、絶縁層１５４の膜厚は、１００ｎｍ以下が好ましく、５０ｎｍ以下がより好ましく、２０ｎｍ以下がさらに好ましく、１０ｎｍ以下（代表的には、２ｎｍ以上９ｎｍ以下）がさらに好ましい。例えば、絶縁層１５４の膜厚を、８ｎｍ以上１２ｎｍ以下にすることが好ましい。 Here, the thickness of the insulating layer 154 is preferably 100 nm or less, more preferably 50 nm or less, even more preferably 20 nm or less, and even more preferably 10 nm or less (typically 2 nm or more and 9 nm or less). For example, the thickness of the insulating layer 154 is preferably 8 nm or more and 12 nm or less.
または、強誘電性を有しうる材料として、窒化アルミニウムスカンジウム（ＡｌＳｃＮ）は、スパッタリング法により形成することが可能であり、膜中の不純物濃度を低減することができる、または緻密な膜を形成することができるため好適である。強誘電性を有しうる材料として、窒化アルミニウムスカンジウム（ＡｌＳｃＮ）を用いる場合、信頼性の高い膜とすることが期待できる。 Alternatively, aluminum scandium nitride (AlScN), which is a material that can have ferroelectricity, can be formed by a sputtering method, and can reduce the impurity concentration in the film or form a dense film. This is suitable because it allows When aluminum scandium nitride (AlScN) is used as a material that can have ferroelectricity, a highly reliable film can be expected.
また、強誘電性を有しうる材料の膜厚は、１００ｎｍ以下、好ましくは５０ｎｍ以下、より好ましくは２０ｎｍ以下、さらに好ましくは１０ｎｍ以下（代表的には、２ｎｍ以上９ｎｍ以下）にすることができる。例えば、膜厚を、８ｎｍ以上１２ｎｍ以下にすることが好ましい。強誘電性を有しうる材料の膜厚を上記のようにすることで、薄膜化、かつ、強誘電性の発現を図ることができる。薄膜化することで、容量素子の一対の電極に当該強誘電体層を挟むことができ、また、当該容量素子を、微細化されたトランジスタなどの半導体素子と組み合わせて半導体装置を形成することができる。すなわち、占有面積が低減された半導体装置の実現が容易となる。 Further, the film thickness of the material that can have ferroelectricity can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and still more preferably 10 nm or less (typically 2 nm or more and 9 nm or less). . For example, the film thickness is preferably 8 nm or more and 12 nm or less. By setting the thickness of the material that can have ferroelectricity as described above, it is possible to make the film thinner and to exhibit ferroelectricity. By making the film thinner, the ferroelectric layer can be sandwiched between a pair of electrodes of a capacitive element, and the capacitive element can be combined with a semiconductor element such as a miniaturized transistor to form a semiconductor device. can. That is, it becomes easy to realize a semiconductor device with a reduced occupied area.
なお、本明細書等において、強誘電性を有しうる材料を強誘電性材料と呼ぶ場合がある。また、本明細書等において、強誘電性を有しうる材料を層状にしたものを指して、強誘電体層、金属酸化物膜、または金属窒化物膜と呼ぶ場合がある。また、このような、強誘電体層、金属酸化物膜、または金属窒化物膜を有する装置を、本明細書等において、強誘電体デバイスと呼ぶ場合がある。 Note that in this specification and the like, a material that can have ferroelectricity is sometimes referred to as a ferroelectric material. Further, in this specification and the like, a layered material that can have ferroelectric properties is sometimes referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Furthermore, a device having such a ferroelectric layer, metal oxide film, or metal nitride film may be referred to as a ferroelectric device in this specification and the like.
また、強誘電性を有しうる材料としてＨｆＺｒＯｘを用いる場合、ＡＬＤ法、特に熱ＡＬＤ法を用いて成膜することが好ましい。また、熱ＡＬＤ法を用いて、強誘電性を有しうる材料を成膜する場合、プリカーサとして炭化水素（Ｈｙｄｒｏ　Ｃａｒｂｏｎ、ＨＣともいう）を含まない材料を用いると好適である。強誘電性を有しうる材料中に、水素、及び炭素のいずれか一方または双方が含まれる場合、強誘電性を有しうる材料の結晶化を阻害する場合がある。このため、上記のように、炭化水素を含まないプリカーサを用いることで、強誘電性を有しうる材料中の、水素、及び炭素のいずれか一方または双方の濃度を低減することが好ましい。例えば、炭化水素を含まないプリカーサとしては、塩素系材料があげられる。なお、強誘電性を有しうる材料として、酸化ハフニウムおよび酸化ジルコニウムを有する材料（ＨｆＺｒＯｘ）を用いる場合、プリカーサとしては、ＨｆＣｌ４、及び／またはＺｒＣｌ４を用いればよい。一方で、強誘電性を有しうる材料に、分極状態を制御するためのドーパント（代表的にはシリコン、炭素など）を添加してもよい。この場合、ドーパントとして炭素を添加する手段の一つとして、プリカーサに炭化水素を含む材料を用いた形成方法を用いてもよい。 Furthermore, when HfZrOx is used as a material that can have ferroelectricity, it is preferable to form a film using an ALD method, particularly a thermal ALD method. Further, when forming a film of a material that can have ferroelectricity using a thermal ALD method, it is preferable to use a material that does not contain hydrocarbon (also referred to as HC) as a precursor. When a material that can have ferroelectric properties contains one or both of hydrogen and carbon, crystallization of the material that can have ferroelectric properties may be inhibited. Therefore, as described above, it is preferable to reduce the concentration of one or both of hydrogen and carbon in a material that can have ferroelectric properties by using a precursor that does not contain hydrocarbons. For example, examples of precursors that do not contain hydrocarbons include chlorine-based materials. Note that when a material containing hafnium oxide and zirconium oxide (HfZrOx) is used as a material that can have ferroelectricity, HfCl 4 and/or ZrCl 4 may be used as the precursor. On the other hand, a dopant (typically silicon, carbon, etc.) for controlling the polarization state may be added to a material that can have ferroelectricity. In this case, as one means for adding carbon as a dopant, a forming method using a material containing a hydrocarbon as a precursor may be used.
なお、強誘電性を有しうる材料を用いた膜を成膜する場合、膜中の不純物、ここでは水素、炭化水素、及び炭素の少なくとも一以上を徹底的に排除することで、高純度真性な強誘電性を有する膜を形成することができる。なお、高純度真性な強誘電性を有する膜と、後述する実施の形態に示す高純度真性な酸化物半導体とは、製造プロセスの整合性が非常に高い。よって、生産性が高い半導体装置の作製方法を提供することができる。 Note that when forming a film using a material that can have ferroelectricity, it is necessary to thoroughly eliminate impurities in the film, in this case at least one of hydrogen, hydrocarbons, and carbon. A film having strong ferroelectricity can be formed. Note that the manufacturing process of a film having high-purity intrinsic ferroelectricity and a high-purity intrinsic oxide semiconductor described in an embodiment described later is very high. Therefore, a method for manufacturing a semiconductor device with high productivity can be provided.
また、強誘電性を有しうる材料の不純物濃度は低い方が好ましい。特に、水素（Ｈ）および炭素（Ｃ）の濃度が低いほど好ましい。具体的には、強誘電性を有しうる材料の水素濃度は、５×１０２０ａｔｏｍｓ／ｃｍ３以下が好ましく、１×１０２０ａｔｏｍｓ／ｃｍ３以下がより好ましい。また、強誘電性を有しうる材料の炭素濃度は、５×１０１９ａｔｏｍｓ／ｃｍ３以下が好ましく、１×１０１９ａｔｏｍｓ／ｃｍ３以下がより好ましい。 Further, it is preferable that the impurity concentration of the material that can have ferroelectricity is low. In particular, lower concentrations of hydrogen (H) and carbon (C) are more preferable. Specifically, the hydrogen concentration of the material that can have ferroelectricity is preferably 5×10 20 atoms/cm 3 or less, more preferably 1×10 20 atoms/cm 3 or less. Further, the carbon concentration of the material that can have ferroelectricity is preferably 5×10 19 atoms/cm 3 or less, more preferably 1×10 19 atoms/cm 3 or less.
また、強誘電性を有しうる材料としてＨｆＺｒＯｘを用いる場合、ＡＬＤ法を用いて酸化ハフニウムと酸化ジルコニウムとを１：１の組成になるように交互に成膜すると好ましい。 Furthermore, when HfZrOx is used as a material that can have ferroelectricity, it is preferable to alternately form films of hafnium oxide and zirconium oxide at a composition of 1:1 using an ALD method.
また、ＡＬＤ法を用いて、強誘電性を有しうる材料を成膜する場合、酸化剤はＨ２ＯまたはＯ３を用いることができる。ただし、ＡＬＤ法の酸化剤としては、これに限定されない。例えば、ＡＬＤ法の酸化剤としては、Ｏ２、Ｏ３、Ｎ２Ｏ、ＮＯ２、Ｈ２Ｏ、及びＨ２Ｏ２の中から選ばれるいずれか一または複数を含んでもよい。 Further, when forming a film of a material that can have ferroelectricity using the ALD method, H 2 O or O 3 can be used as the oxidizing agent. However, the oxidizing agent for ALD is not limited to this. For example, the oxidizing agent in the ALD method may include one or more selected from O 2 , O 3 , N 2 O, NO 2 , H 2 O, and H 2 O 2 .
特に強誘電性を有しうる材料としては、直方晶系の結晶構造を有すると、強誘電性が発現するため好ましい。なお、直方晶系の結晶構造の他に、他の結晶構造を含んでもよい。例えば、直方晶系の結晶構造の他に、立方晶系、正方晶系、及び単斜晶系の中から選ばれるいずれか一または複数の結晶構造を有してもよい。なお、強誘電性を有しうる材料を形成する前に結晶性を高める層を形成してもよい。例えば、強誘電性を有しうる材料として、ＨｆＺｒＯｘを用いる場合、結晶性を高める層としては、酸化ハフニウム、または酸化ジルコニウムなどの金属酸化物、もしくは、ハフニウム、またはジルコニウムを用いることができる。 In particular, as a material that can have ferroelectricity, it is preferable to have a rectangular crystal structure because it exhibits ferroelectricity. Note that other than the rectangular crystal structure, other crystal structures may be included. For example, in addition to the rectangular crystal structure, it may have one or more crystal structures selected from cubic, tetragonal, and monoclinic. Note that a layer for increasing crystallinity may be formed before forming the material that can have ferroelectricity. For example, when HfZrOx is used as a material that can have ferroelectricity, a metal oxide such as hafnium oxide or zirconium oxide, or hafnium or zirconium can be used as the layer that increases crystallinity.
また、強誘電性を有しうる材料として、ＡｌＳｃＮを用いる場合、六方晶系の結晶構造を有することが好ましい。なお、六方晶系の結晶構造の他に、他の結晶構造を含んでもよい。結晶性を高める層としては、窒化アルミニウム、または窒化スカンジウムなどの金属窒化物、もしくは、アルミニウム、またはスカンジウムを用いると好ましい。 Further, when AlScN is used as a material that can have ferroelectricity, it is preferable to have a hexagonal crystal structure. Note that other crystal structures may be included in addition to the hexagonal crystal structure. As the layer for increasing crystallinity, it is preferable to use a metal nitride such as aluminum nitride or scandium nitride, or aluminum or scandium.
なお、結晶性を高める層は、強誘電性を有しうる材料を形成した後に形成してもよい。または、強誘電性を有しうる材料として、アモルファス構造と、結晶構造とを有する複合構造としてもよい。 Note that the layer for increasing crystallinity may be formed after forming the material that can have ferroelectricity. Alternatively, the material that can have ferroelectricity may have a composite structure having an amorphous structure and a crystalline structure.
［導電層］
半導体装置を構成する各種配線および電極などの導電層に用いる導電性材料として、アルミニウム（Ａｌ）、クロム（Ｃｒ）、銅（Ｃｕ）、銀（Ａｇ）、金（Ａｕ）、白金（Ｐｔ）、タンタル（Ｔａ）、ニッケル（Ｎｉ）、チタン（Ｔｉ）、モリブデン（Ｍｏ）、タングステン（Ｗ）、ハフニウム（Ｈｆ）、バナジウム（Ｖ）、ニオブ（Ｎｂ）、マンガン（Ｍｎ）、マグネシウム（Ｍｇ）、ジルコニウム（Ｚｒ）、ベリリウム（Ｂｅ）等から選ばれた金属元素、上述した金属元素を成分とする合金、または上述した金属元素を組み合わせた合金などを用いることができる。 [Conductive layer]
Conductive materials used for conductive layers such as various wirings and electrodes that make up semiconductor devices include aluminum (Al), chromium (Cr), copper (Cu), silver (Ag), gold (Au), platinum (Pt), Tantalum (Ta), nickel (Ni), titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), vanadium (V), niobium (Nb), manganese (Mn), magnesium (Mg), A metal element selected from zirconium (Zr), beryllium (Be), etc., an alloy containing the above-mentioned metal elements, an alloy containing a combination of the above-mentioned metal elements, etc. can be used.
例えば、窒化タンタル、窒化チタン、タングステン、チタンとアルミニウムを含む窒化物、タンタルとアルミニウムを含む窒化物、酸化ルテニウム、窒化ルテニウム、ストロンチウムとルテニウムを含む酸化物、ランタンとニッケルを含む酸化物などを用いることが好ましい。また、窒化タンタル、窒化チタン、チタンとアルミニウムを含む窒化物、タンタルとアルミニウムを含む窒化物、酸化ルテニウム、窒化ルテニウム、ストロンチウムとルテニウムを含む酸化物、ランタンとニッケルを含む酸化物は、酸化しにくい導電性材料、または、酸素を吸収しても導電性を維持する材料であるため、好ましい。また、リン等の不純物元素を含有させた多結晶シリコンに代表される、電気伝導度が高い半導体、ニッケルシリサイドなどのシリサイドを用いてもよい。導電性材料の形成方法は特に限定されず、蒸着法、原子層堆積（ＡＬＤ：Ａｔｏｍｉｃ　Ｌａｙｅｒ　Ｄｅｐｏｓｉｔｉｏｎ）法、ＣＶＤ法、スパッタリング法、スピンコート法などの各種形成方法を用いることができる。 For example, use of tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. It is preferable. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are difficult to oxidize. It is preferable because it is a conductive material or a material that maintains conductivity even if it absorbs oxygen. Further, a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used. The method for forming the conductive material is not particularly limited, and various methods such as vapor deposition, atomic layer deposition (ALD), CVD, sputtering, and spin coating can be used.
また、導電性材料として、Ｃｕ−Ｘ合金（Ｘは、Ｍｎ、Ｎｉ、Ｃｒ、Ｆｅ、Ｃｏ、Ｍｏ、Ｔａ、またはＴｉ）を適用してもよい。Ｃｕ−Ｘ合金で形成した層は、ウエットエッチングプロセスで加工できるため、製造コストを抑制することが可能となる。また、導電性材料として、チタン、タンタル、タングステン、モリブデン、クロム、ネオジム、スカンジウムから選ばれた一または複数の元素を含むアルミニウム合金を用いてもよい。 Moreover, a Cu-X alloy (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be applied as the conductive material. Since the layer formed of the Cu-X alloy can be processed by a wet etching process, it is possible to suppress manufacturing costs. Alternatively, an aluminum alloy containing one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used as the conductive material.
また、導電層に用いることのできる導電性材料として、インジウム錫酸化物、酸化タングステンを含むインジウム酸化物、酸化タングステンを含むインジウム亜鉛酸化物、酸化チタンを含むインジウム酸化物、酸化チタンを含むインジウム錫酸化物、インジウム亜鉛酸化物、酸化ケイ素を添加したインジウム錫酸化物などの、酸素を有する導電性材料を用いることもできる。また、窒化チタン、窒化タンタル、窒化タングステンなどの、窒素を含む導電性材料を用いることもできる。また、導電層を、酸素を有する導電性材料、窒素を含む導電性材料、前述した金属元素を含む材料を適宜組み合わせた積層構造とすることもできる。 In addition, as conductive materials that can be used for the conductive layer, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin containing titanium oxide, etc. Conductive materials with oxygen can also be used, such as oxides, indium zinc oxide, indium tin oxide doped with silicon oxide. Further, conductive materials containing nitrogen such as titanium nitride, tantalum nitride, and tungsten nitride can also be used. Further, the conductive layer can also have a laminated structure in which a conductive material containing oxygen, a conductive material containing nitrogen, and a material containing the metal element described above are appropriately combined.
例えば、導電層を、シリコンを含むアルミニウム層の単層構造、アルミニウム層上にチタン層を積層する二層構造、窒化チタン層上にチタン層を積層する二層構造、窒化チタン層上にタングステン層を積層する二層構造、窒化タンタル層上にタングステン層を積層する二層構造、チタン層と、そのチタン層上にアルミニウム層を積層し、さらにその上にチタン層を積層する三層構造としてもよい。 For example, the conductive layer may have a single-layer structure of an aluminum layer containing silicon, a two-layer structure in which a titanium layer is stacked on an aluminum layer, a two-layer structure in which a titanium layer is stacked on a titanium nitride layer, or a tungsten layer on a titanium nitride layer. A two-layer structure in which a tungsten layer is laminated on a tantalum nitride layer, a two-layer structure in which a tungsten layer is laminated on a tantalum nitride layer, and a three-layer structure in which a titanium layer is laminated, an aluminum layer is laminated on the titanium layer, and a titanium layer is laminated on top of that. good.
また、上記の導電性材料で形成される導電層を複数積層して用いてもよい。例えば、導電層を前述した金属元素を含む材料と酸素を含む導電性材料を組み合わせた積層構造としてもよい。また、前述した金属元素を含む材料と、窒素を含む導電性材料を組み合わせた積層構造としてもよい。また、前述した金属元素を含む材料、酸素を含む導電性材料、および窒素を含む導電性材料を組み合わせた積層構造としてもよい。 Further, a plurality of conductive layers formed of the above-mentioned conductive materials may be laminated and used. For example, the conductive layer may have a laminated structure in which a material containing the aforementioned metal element and a conductive material containing oxygen are combined. Alternatively, a laminated structure may be used in which a material containing the aforementioned metal element and a conductive material containing nitrogen are combined. Alternatively, a layered structure may be used in which a material containing the metal element described above, a conductive material containing oxygen, and a conductive material containing nitrogen are combined.
例えば、導電層を、インジウムまたは亜鉛の少なくとも一方と酸素とを含む導電層上に、銅を含む導電層を積層し、さらにその上にインジウムまたは亜鉛の少なくとも一方と酸素とを含む導電層を積層する三層構造としてもよい。この場合、銅を含む導電層の側面もインジウムまたは亜鉛の少なくとも一方と酸素とを含む導電層で覆うことが好ましい。また、例えば、導電層としてインジウムまたは亜鉛の少なくとも一方と酸素とを含む導電層を複数積層して用いてもよい。 For example, a conductive layer is formed by laminating a conductive layer containing copper on a conductive layer containing at least one of indium or zinc and oxygen, and further laminating a conductive layer containing at least one of indium or zinc and oxygen on top of the conductive layer containing at least one of indium or zinc and oxygen. It may also have a three-layer structure. In this case, it is preferable that the side surfaces of the conductive layer containing copper are also covered with a conductive layer containing at least one of indium or zinc and oxygen. Further, for example, a plurality of conductive layers containing at least one of indium or zinc and oxygen may be stacked and used as the conductive layer.
また、容量素子１１０を強誘電体キャパシタとして機能させる場合は、強誘電体である絶縁層１５４と接する導電層１５１および導電層１５５として、絶縁層１５４に分極を生じさせやすい材料を用いることが好ましい。例えば、導電層１５１および導電層１５５として窒化チタンを用いることが好ましい。 Furthermore, when the capacitive element 110 functions as a ferroelectric capacitor, it is preferable to use a material that easily causes polarization in the insulating layer 154 as the conductive layer 151 and the conductive layer 155 in contact with the insulating layer 154 which is a ferroelectric material. . For example, it is preferable to use titanium nitride as the conductive layer 151 and the conductive layer 155.
［半導体層］
半導体層１６３として、単結晶半導体、多結晶半導体、微結晶半導体、または非晶質半導体などを、単体でまたは組み合わせて用いることができる。半導体材料としては、例えば、シリコン、ゲルマニウムなどを用いることができる。また、シリコンゲルマニウム、炭化シリコン、ヒ化ガリウム、窒化物半導体などの化合物半導体を用いてもよい。化合物半導体として、半導体特性を有する有機物、または半導体特性を有する金属酸化物（酸化物半導体ともいう）を用いることができる。なお、これらの半導体材料に、ドーパントとして不純物が含まれてもよい。 [Semiconductor layer]
As the semiconductor layer 163, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination. As the semiconductor material, silicon, germanium, etc. can be used, for example. Further, a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, or a nitride semiconductor may be used. As the compound semiconductor, an organic substance having semiconductor properties or a metal oxide having semiconductor properties (also referred to as an oxide semiconductor) can be used. Note that these semiconductor materials may contain impurities as dopants.
例えば、半導体層１６３として、単結晶シリコン、多結晶シリコン、微結晶シリコン、及び非晶質シリコンを用いてもよい。多結晶シリコンとして、例えば、低温ポリシリコン（ＬＴＰＳ：Ｌｏｗ　Ｔｅｍｐｅｒａｔｕｒｅ　Ｐｏｌｙ　Ｓｉｌｉｃｏｎ）を用いてもよい。 For example, the semiconductor layer 163 may be made of single crystal silicon, polycrystalline silicon, microcrystalline silicon, or amorphous silicon. As the polycrystalline silicon, for example, low temperature polysilicon (LTPS) may be used.
半導体層１６３に非晶質シリコンを用いたトランジスタは、大型のガラス基板上に形成でき、低コストで作製することができる。半導体層１６３に多結晶シリコンを用いたトランジスタは、電界効果移動度が高く、高速動作が可能である。また、半導体層１６３に微結晶シリコンを用いたトランジスタは、非晶質シリコンを用いたトランジスタより電界効果移動度が高く、高速動作が可能である。 A transistor using amorphous silicon for the semiconductor layer 163 can be formed over a large glass substrate and can be manufactured at low cost. A transistor using polycrystalline silicon for the semiconductor layer 163 has high field effect mobility and can operate at high speed. Further, a transistor using microcrystalline silicon for the semiconductor layer 163 has higher field effect mobility than a transistor using amorphous silicon, and can operate at high speed.
半導体層１６３は、半導体として機能する層状物質を有してもよい。層状物質とは、層状の結晶構造を有する材料群の総称である。層状の結晶構造は、共有結合またはイオン結合によって形成される層が、ファンデルワールス力のような、共有結合またはイオン結合よりも弱い結合を介して積層している構造である。層状物質は、単位層内における電気伝導性が高く、つまり、２次元電気伝導性が高い。半導体として機能し、かつ、２次元電気伝導性の高い材料をチャネル形成領域に用いることで、オン電流の大きいトランジスタを提供することができる。 The semiconductor layer 163 may include a layered material that functions as a semiconductor. A layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are laminated via bonds that are weaker than covalent bonds or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity for the channel formation region, a transistor with high on-state current can be provided.
上記層状物質として、例えば、グラフェン、シリセン、カルコゲン化物などが挙げられる。カルコゲン化物は、カルコゲン（第１６族に属する元素）を含む化合物である。また、カルコゲン化物として、遷移金属カルコゲナイド、１３族カルコゲナイドなどが挙げられる。トランジスタの半導体層として適用可能な遷移金属カルコゲナイドとして、具体的には、硫化モリブデン（代表的にはＭｏＳ２）、セレン化モリブデン（代表的にはＭｏＳｅ２）、モリブデンテルル（代表的にはＭｏＴｅ２）、硫化タングステン（代表的にはＷＳ２）、セレン化タングステン（代表的にはＷＳｅ２）、タングステンテルル（代表的にはＷＴｅ２）、硫化ハフニウム（代表的にはＨｆＳ２）、セレン化ハフニウム（代表的にはＨｆＳｅ２）、硫化ジルコニウム（代表的にはＺｒＳ２）、セレン化ジルコニウム（代表的にはＺｒＳｅ２）などが挙げられる。 Examples of the layered material include graphene, silicene, and chalcogenide. A chalcogenide is a compound containing chalcogen (an element belonging to Group 16). Furthermore, examples of chalcogenides include transition metal chalcogenides, group 13 chalcogenides, and the like. Specifically, transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS 2 ), molybdenum selenide (typically MoSe 2 ), and molybdenum tellurium (typically MoTe 2 ) . ), tungsten sulfide (typically WS 2 ), tungsten selenide (typically WSe 2 ), tungsten tellurium (typically WTe 2 ), hafnium sulfide (typically HfS 2 ), hafnium selenide (typically HfSe 2 ), zirconium sulfide (typically ZrS 2 ), zirconium selenide (typically ZrSe 2 ), and the like.
また、酸化物半導体はバンドギャップが２ｅＶ以上であるため、チャネルが形成される半導体層に金属酸化物の一種である酸化物半導体を用いたトランジスタ（「ＯＳトランジスタ」ともいう。）は、オフ電流が著しく少ない。よって、ＯＳトランジスタを含む半導体装置の消費電力を低減できる。また、ＯＳトランジスタは高温環境下においても動作が安定し、特性変動が少ない。例えば、高温環境下でもオフ電流がほとんど増加しない。具体的には、室温以上２００℃以下の環境温度下でもオフ電流がほとんど増加しない。また、高温環境下でもオン電流が低下しにくい。よって、ＯＳトランジスタを含む半導体装置は、高温環境下においても動作が安定し、高い信頼性が得られる。 Furthermore, since an oxide semiconductor has a band gap of 2 eV or more, a transistor (also referred to as an "OS transistor") using an oxide semiconductor, which is a type of metal oxide, for the semiconductor layer in which a channel is formed has an off-state current of are significantly less. Therefore, power consumption of a semiconductor device including an OS transistor can be reduced. Furthermore, the OS transistor operates stably even in a high-temperature environment, with little variation in characteristics. For example, the off-state current hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even under an environmental temperature of room temperature or higher and 200° C. or lower. Furthermore, the on-state current is less likely to decrease even in a high-temperature environment. Therefore, a semiconductor device including an OS transistor operates stably even in a high-temperature environment and has high reliability.
このため、容量素子に強誘電体キャパシタを用いない記憶装置においても、書き込まれたデータを長時間保持できる。例えば、一般的なＤＲＡＭにおいては、リフレッシュ動作の頻度を約１回／６０ｍｓｅｃとする必要があるが、本発明の一態様の記憶装置においては、リフレッシュ動作の頻度を約１回／１０ｓｅｃと、１０倍以上または１００倍以上のリフレッシュ動作の頻度とすることができる。なお、本発明の一態様の記憶装置とすることで、リフレッシュ動作は、１ｓｅｃ以上１００ｓｅｃ以下、好ましくは、５ｓｅｃ以上５０ｓｅｃ以下に１回の頻度とすることができる。 Therefore, written data can be retained for a long time even in a storage device that does not use a ferroelectric capacitor as a capacitive element. For example, in a general DRAM, the refresh operation frequency needs to be approximately 1 time/60 msec, but in the storage device of one embodiment of the present invention, the refresh operation frequency is approximately 1 time/10 sec, and 10 msec. The refresh operation frequency can be set to be twice or more or 100 times or more. Note that with the storage device of one embodiment of the present invention, the refresh operation can be performed once every 1 sec or more and 100 sec or less, preferably once every 5 sec or more and 50 sec or less.
なお、本実施の形態などでは、トランジスタ１００としてＯＳトランジスタを用いることが好ましい。ＯＳトランジスタはソースとドレイン間の絶縁耐圧が高いため、チャネル長を短くすることができる。よって、オン電流を大きくすることができる。ＯＳトランジスタは、縦チャネル型トランジスタに好適である。 Note that in this embodiment and the like, it is preferable to use an OS transistor as the transistor 100. Since the OS transistor has a high dielectric strength voltage between the source and the drain, the channel length can be shortened. Therefore, the on-state current can be increased. The OS transistor is suitable for a vertical channel type transistor.
ＯＳトランジスタの半導体層に用いることができる金属酸化物として、例えば、インジウム酸化物、ガリウム酸化物、および亜鉛酸化物が挙げられる。金属酸化物は、少なくともインジウム（Ｉｎ）または亜鉛（Ｚｎ）を含むことが好ましい。また、金属酸化物は、インジウムと、元素Ｍと、亜鉛と、の中から選ばれる二または三を有することが好ましい。なお、元素Ｍは、酸素との結合エネルギーが高い金属元素または半金属元素であり、例えば、酸素との結合エネルギーがインジウムよりも高い金属元素または半金属元素である。 Examples of metal oxides that can be used in the semiconductor layer of the OS transistor include indium oxide, gallium oxide, and zinc oxide. Preferably, the metal oxide contains at least indium (In) or zinc (Zn). Moreover, it is preferable that the metal oxide has two or three selected from indium, element M, and zinc. Note that the element M is a metal element or a metalloid element that has a high bonding energy with oxygen, for example, a metal element or a metalloid element that has a higher bonding energy with oxygen than indium.
元素Ｍとして、具体的には、アルミニウム、ガリウム、スズ、イットリウム、チタン、バナジウム、クロム、マンガン、鉄、コバルト、ニッケル、ジルコニウム、モリブデン、ハフニウム、タンタル、タングステン、ランタン、セリウム、ネオジム、マグネシウム、カルシウム、ストロンチウム、バリウム、ホウ素、シリコン、ゲルマニウム、及びアンチモンなどが挙げられる。金属酸化物が有する元素Ｍは、上記元素のいずれか一種または複数種であることが好ましく、アルミニウム、ガリウム、スズ、及びイットリウムから選ばれた一種または複数種であることがより好ましく、ガリウムがさらに好ましい。なお、本明細書等において、金属元素と半金属元素をまとめて「金属元素」と呼ぶことがあり、本明細書等に記載の「金属元素」には半金属元素が含まれることがある。 Specifically, the element M includes aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, and calcium. , strontium, barium, boron, silicon, germanium, and antimony. The element M included in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and further gallium. preferable. Note that in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may include semimetal elements.
例えば、インジウム亜鉛酸化物（Ｉｎ−Ｚｎ酸化物）、インジウムスズ酸化物（Ｉｎ−Ｓｎ酸化物）、インジウムチタン酸化物（Ｉｎ−Ｔｉ酸化物）、インジウムガリウム酸化物（Ｉｎ−Ｇａ酸化物）、インジウムガリウムアルミニウム酸化物（Ｉｎ−Ｇａ−Ａｌ酸化物）、インジウムガリウムスズ酸化物（Ｉｎ−Ｇａ−Ｓｎ酸化物）、ガリウム亜鉛酸化物（Ｇａ−Ｚｎ酸化物、「ＧＺＯ」とも記す。）、アルミニウム亜鉛酸化物（Ａｌ−Ｚｎ酸化物、「ＡＺＯ」とも記す。）、インジウムアルミニウム亜鉛酸化物（Ｉｎ−Ａｌ−Ｚｎ酸化物、「ＩＡＺＯ」とも記す。）、インジウムスズ亜鉛酸化物（Ｉｎ−Ｓｎ−Ｚｎ酸化物）、インジウムチタン亜鉛酸化物（Ｉｎ−Ｔｉ−Ｚｎ酸化物）、インジウムガリウム亜鉛酸化物（Ｉｎ−Ｇａ−Ｚｎ酸化物、「ＩＧＺＯ」とも記す。）、インジウムガリウムスズ亜鉛酸化物（Ｉｎ−Ｇａ−Ｓｎ−Ｚｎ酸化物、「ＩＧＺＴＯ」とも記す。）、インジウムガリウムアルミニウム亜鉛酸化物（Ｉｎ−Ｇａ−Ａｌ−Ｚｎ酸化物、「ＩＧＡＺＯ」または「ＩＡＧＺＯ」とも記す。）などを用いることができる。または、シリコンを含むインジウムスズ酸化物、ガリウムスズ酸化物（Ｇａ−Ｓｎ酸化物）、アルミニウムスズ酸化物（Ａｌ−Ｓｎ酸化物）などを用いることができる。 For example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), Indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also referred to as "GZO"), aluminum Zinc oxide (Al-Zn oxide, also written as "AZO"), indium aluminum zinc oxide (In-Al-Zn oxide, also written as "IAZO"), indium tin zinc oxide (In-Sn- Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as "IGZO"), indium gallium tin zinc oxide (In -Ga-Sn-Zn oxide, also written as "IGZTO"), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as "IGAZO" or "IAGZO"), etc. can be used. can. Alternatively, indium tin oxide, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. containing silicon can be used.
金属酸化物に含まれる全ての金属元素の原子数の和に対するインジウムの原子数の割合を高くすることにより、トランジスタの電界効果移動度を高めることができる。 By increasing the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the field effect mobility of the transistor can be increased.
なお、金属酸化物は、インジウムに代えて周期の数が大きい金属元素の一種または複数種を有してもよい。または、金属酸化物は、インジウムに加えて周期の数が大きい金属元素の一種または複数種を有してもよい。金属元素の軌道の重なりが大きいほど、金属酸化物におけるキャリア伝導は大きくなる傾向がある。よって、周期の数が大きい金属元素を含むことで、トランジスタの電界効果移動度を高めることができる場合がある。周期の数が大きい金属元素として、第５周期に属する金属元素、及び第６周期に属する金属元素などが挙げられる。当該金属元素として、具体的には、イットリウム、ジルコニウム、銀、カドミウム、スズ、アンチモン、バリウム、鉛、ビスマス、ランタン、セリウム、プラセオジム、ネオジム、プロメチウム、サマリウム、及びユウロピウムなどが挙げられる。なお、ランタン、セリウム、プラセオジム、ネオジム、プロメチウム、サマリウム、及びユウロピウムは、軽希土類元素と呼ばれる。 Note that the metal oxide may include one or more metal elements having a large number of periods instead of indium. Alternatively, the metal oxide may contain one or more metal elements having a large number of periods in addition to indium. The greater the overlap between the orbits of the metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including a metal element with a large number of periods, the field effect mobility of the transistor may be increased. Examples of metal elements having a large number of periods include metal elements belonging to the fifth period and metal elements belonging to the sixth period. Specific examples of the metal element include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.
また、金属酸化物は、非金属元素の一種または複数種を有してもよい。金属酸化物が非金属元素を有することで、トランジスタの電界効果移動度を高めることができる場合がある。非金属元素として、例えば、炭素、窒素、リン、硫黄、セレン、フッ素、塩素、臭素、及び水素などが挙げられる。 Further, the metal oxide may contain one or more types of nonmetallic elements. When the metal oxide contains a nonmetal element, the field effect mobility of the transistor can be increased in some cases. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.
また、金属酸化物に含まれる主成分元素のうち、金属元素の原子数の和に対する亜鉛の原子数の割合を高くすることにより、結晶性の高い金属酸化物となり、金属酸化物中の不純物の拡散を抑制できる。したがって、トランジスタの電気特性の変動が抑制され、信頼性を高めることができる。 In addition, among the main component elements contained in the metal oxide, by increasing the ratio of the number of zinc atoms to the sum of the number of atoms of the metal elements, the metal oxide becomes highly crystalline, and impurities in the metal oxide can be reduced. It can suppress the spread. Therefore, fluctuations in the electrical characteristics of the transistor are suppressed, and reliability can be improved.
また、金属酸化物に含まれる主成分元素のうち、金属元素の原子数の和に対する元素Ｍの原子数の割合を高くすることにより、金属酸化物に酸素欠損が形成されるのを抑制できる。したがって、酸素欠損に起因するキャリア生成が抑制され、オフ電流の小さいトランジスタとすることができる。また、トランジスタの電気特性の変動が抑制され、信頼性を高めることができる。 Further, by increasing the ratio of the number of atoms of element M to the sum of the number of atoms of metal elements among the main component elements contained in the metal oxide, it is possible to suppress the formation of oxygen vacancies in the metal oxide. Therefore, carrier generation due to oxygen vacancies is suppressed, and a transistor with low off-state current can be obtained. Further, fluctuations in the electrical characteristics of the transistor are suppressed, and reliability can be improved.
半導体層に適用する金属酸化物の組成により、トランジスタの電気特性、および信頼性が異なる。したがって、トランジスタに求められる電気特性、および信頼性に応じて金属酸化物の組成を異ならせることにより、優れた電気特性と高い信頼性を両立した半導体装置が実現できる。 The electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide applied to the semiconductor layer. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be realized.
ＯＳトランジスタの半導体層にＩｎ−Ｚｎ酸化物を用いる場合、インジウムの原子数比が亜鉛の原子数比以上である金属酸化物を用いてもよい。例えば、金属元素の原子数比が、Ｉｎ：Ｚｎ＝１：１、Ｉｎ：Ｚｎ＝２：１、Ｉｎ：Ｚｎ＝３：１、Ｉｎ：Ｚｎ＝４：１、Ｉｎ：Ｚｎ＝５：１、Ｉｎ：Ｚｎ＝７：１、またはＩｎ：Ｚｎ＝１０：１、またはこれらの近傍の金属酸化物を用いてもよい。 When using In--Zn oxide for the semiconductor layer of the OS transistor, a metal oxide in which the atomic ratio of indium is greater than or equal to the atomic ratio of zinc may be used. For example, the atomic ratio of the metal elements is In:Zn=1:1, In:Zn=2:1, In:Zn=3:1, In:Zn=4:1, In:Zn=5:1, In:Zn=7:1, In:Zn=10:1, or a metal oxide in the vicinity thereof may be used.
ＯＳトランジスタの半導体層にＩｎ−Ｓｎ酸化物を用いる場合、インジウムの原子数比がスズの原子数比以上である金属酸化物を用いてもよい。例えば、金属元素の原子数比が、Ｉｎ：Ｓｎ＝１：１、Ｉｎ：Ｓｎ＝２：１、Ｉｎ：Ｓｎ＝３：１、Ｉｎ：Ｓｎ＝４：１、Ｉｎ：Ｓｎ＝５：１、Ｉｎ：Ｓｎ＝７：１、またはＩｎ：Ｓｎ＝１０：１、またはこれらの近傍の金属酸化物を用いてもよい。 When using an In-Sn oxide for the semiconductor layer of the OS transistor, a metal oxide in which the atomic ratio of indium is greater than or equal to the atomic ratio of tin may be used. For example, the atomic ratio of the metal elements is In:Sn=1:1, In:Sn=2:1, In:Sn=3:1, In:Sn=4:1, In:Sn=5:1, In:Sn=7:1, In:Sn=10:1, or a metal oxide in the vicinity thereof may be used.
ＯＳトランジスタの半導体層にＩｎ−Ｓｎ−Ｚｎ酸化物を用いる場合、インジウムの原子数比が、スズの原子数比よりも高い金属酸化物を用いてもよい。さらには、亜鉛の原子数比が、スズの原子数比よりも高い金属酸化物を用いることが好ましい。例えば、金属元素の原子数比が、Ｉｎ：Ｓｎ：Ｚｎ＝２：１：３、Ｉｎ：Ｓｎ：Ｚｎ＝３：１：２、Ｉｎ：Ｓｎ：Ｚｎ＝４：２：３、Ｉｎ：Ｓｎ：Ｚｎ＝４：２：４．１、Ｉｎ：Ｓｎ：Ｚｎ＝５：１：３、Ｉｎ：Ｓｎ：Ｚｎ＝５：１：６、Ｉｎ：Ｓｎ：Ｚｎ＝５：１：７、Ｉｎ：Ｓｎ：Ｚｎ＝５：１：８、Ｉｎ：Ｓｎ：Ｚｎ＝６：１：６、Ｉｎ：Ｓｎ：Ｚｎ＝１０：１：３、Ｉｎ：Ｓｎ：Ｚｎ＝１０：１：６、Ｉｎ：Ｓｎ：Ｚｎ＝１０：１：７、Ｉｎ：Ｓｎ：Ｚｎ＝１０：１：８、Ｉｎ：Ｓｎ：Ｚｎ＝５：２：５、Ｉｎ：Ｓｎ：Ｚｎ＝１０：１：１０、Ｉｎ：Ｓｎ：Ｚｎ＝２０：１：１０、Ｉｎ：Ｓｎ：Ｚｎ＝４０：１：１０、またはこれらの近傍の金属酸化物を用いてもよい。 When using In-Sn-Zn oxide for the semiconductor layer of the OS transistor, a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of tin may be used. Furthermore, it is preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of tin. For example, the atomic ratio of the metal elements is In:Sn:Zn=2:1:3, In:Sn:Zn=3:1:2, In:Sn:Zn=4:2:3, In:Sn: Zn=4:2:4.1, In:Sn:Zn=5:1:3, In:Sn:Zn=5:1:6, In:Sn:Zn=5:1:7, In:Sn: Zn=5:1:8, In:Sn:Zn=6:1:6, In:Sn:Zn=10:1:3, In:Sn:Zn=10:1:6, In:Sn:Zn= 10:1:7, In:Sn:Zn=10:1:8, In:Sn:Zn=5:2:5, In:Sn:Zn=10:1:10, In:Sn:Zn=20: 1:10, In:Sn:Zn=40:1:10, or metal oxides in the vicinity thereof may be used.
ＯＳトランジスタの半導体層にＩｎ−Ａｌ−Ｚｎ酸化物を用いる場合、インジウムの原子数比が、アルミニウムの原子数比よりも高い金属酸化物を適用してもよい。さらには、亜鉛の原子数比が、アルミニウムの原子数比よりも高い金属酸化物を用いることが好ましい。例えば、金属元素の原子数比が、Ｉｎ：Ａｌ：Ｚｎ＝２：１：３、Ｉｎ：Ａｌ：Ｚｎ＝３：１：２、Ｉｎ：Ａｌ：Ｚｎ＝４：２：３、Ｉｎ：Ａｌ：Ｚｎ＝４：２：４．１、Ｉｎ：Ａｌ：Ｚｎ＝５：１：３、Ｉｎ：Ａｌ：Ｚｎ＝５：１：６、Ｉｎ：Ａｌ：Ｚｎ＝５：１：７、Ｉｎ：Ａｌ：Ｚｎ＝５：１：８、Ｉｎ：Ａｌ：Ｚｎ＝６：１：６、Ｉｎ：Ａｌ：Ｚｎ＝１０：１：３、Ｉｎ：Ａｌ：Ｚｎ＝１０：１：６、Ｉｎ：Ａｌ：Ｚｎ＝１０：１：７、Ｉｎ：Ａｌ：Ｚｎ＝１０：１：８、Ｉｎ：Ａｌ：Ｚｎ＝５：２：５、Ｉｎ：Ａｌ：Ｚｎ＝１０：１：１０、Ｉｎ：Ａｌ：Ｚｎ＝２０：１：１０、Ｉｎ：Ａｌ：Ｚｎ＝４０：１：１０、またはこれらの近傍の金属酸化物を用いてもよい。 When using In-Al-Zn oxide for the semiconductor layer of the OS transistor, a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of aluminum may be used. Furthermore, it is preferable to use a metal oxide in which the atomic ratio of zinc is higher than that of aluminum. For example, the atomic ratio of the metal elements is In:Al:Zn=2:1:3, In:Al:Zn=3:1:2, In:Al:Zn=4:2:3, In:Al: Zn=4:2:4.1, In:Al:Zn=5:1:3, In:Al:Zn=5:1:6, In:Al:Zn=5:1:7, In:Al: Zn=5:1:8, In:Al:Zn=6:1:6, In:Al:Zn=10:1:3, In:Al:Zn=10:1:6, In:Al:Zn= 10:1:7, In:Al:Zn=10:1:8, In:Al:Zn=5:2:5, In:Al:Zn=10:1:10, In:Al:Zn=20: 1:10, In:Al:Zn=40:1:10, or a metal oxide in the vicinity thereof may be used.
ＯＳトランジスタの半導体層にＩｎ−Ｇａ−Ｚｎ酸化物を用いる場合、Ｉｎ−Ｇａ−Ｚｎ酸化物に含まれる金属元素の原子数の和に対するインジウムの原子数比が、ガリウムの原子数比よりも高い金属酸化物を用いてもよい。さらには、亜鉛の原子数比が、ガリウムの原子数比よりも高い金属酸化物を用いることが好ましい。例えば、半導体層は、金属元素の原子数比が、Ｉｎ：Ｇａ：Ｚｎ＝２：１：３、Ｉｎ：Ｇａ：Ｚｎ＝３：１：２、Ｉｎ：Ｇａ：Ｚｎ＝４：２：３、Ｉｎ：Ｇａ：Ｚｎ＝４：２：４．１、Ｉｎ：Ｇａ：Ｚｎ＝５：１：３、Ｉｎ：Ｇａ：Ｚｎ＝５：１：６、Ｉｎ：Ｇａ：Ｚｎ＝５：１：７、Ｉｎ：Ｇａ：Ｚｎ＝５：１：８、Ｉｎ：Ｇａ：Ｚｎ＝６：１：６、Ｉｎ：Ｇａ：Ｚｎ＝１０：１：３、Ｉｎ：Ｇａ：Ｚｎ＝１０：１：６、Ｉｎ：Ｇａ：Ｚｎ＝１０：１：７、Ｉｎ：Ｇａ：Ｚｎ＝１０：１：８、Ｉｎ：Ｇａ：Ｚｎ＝５：２：５、Ｉｎ：Ｇａ：Ｚｎ＝１０：１：１０、Ｉｎ：Ｇａ：Ｚｎ＝２０：１：１０、Ｉｎ：Ｇａ：Ｚｎ＝４０：１：１０、またはこれらの近傍の金属酸化物を用いてもよい。 When using In-Ga-Zn oxide for the semiconductor layer of an OS transistor, the atomic ratio of indium to the sum of the number of atoms of metal elements contained in the In-Ga-Zn oxide is higher than the atomic ratio of gallium. Metal oxides may also be used. Furthermore, it is preferable to use a metal oxide in which the atomic ratio of zinc is higher than that of gallium. For example, in the semiconductor layer, the atomic ratio of the metal elements is In:Ga:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, In:Ga:Zn=6:1:6, In:Ga:Zn=10:1:3, In:Ga:Zn=10:1:6, In: Ga:Zn=10:1:7, In:Ga:Zn=10:1:8, In:Ga:Zn=5:2:5, In:Ga:Zn=10:1:10, In:Ga: Zn=20:1:10, In:Ga:Zn=40:1:10, or metal oxides in the vicinity thereof may be used.
ＯＳトランジスタの半導体層にＩｎ−Ｍ−Ｚｎ酸化物を用いる場合、Ｉｎ−Ｍ−Ｚｎ酸化物に含まれる金属元素の原子数の和に対するインジウムの原子数比が、元素Ｍの原子数比よりも高い金属酸化物を用いてもよい。さらには、亜鉛の原子数比が、元素Ｍの原子数比よりも高い金属酸化物を用いることが、より好ましい。例えば、半導体層は、金属元素の原子数比が、Ｉｎ：Ｍ：Ｚｎ＝２：１：３、Ｉｎ：Ｍ：Ｚｎ＝３：１：２、Ｉｎ：Ｍ：Ｚｎ＝４：２：３、Ｉｎ：Ｍ：Ｚｎ＝４：２：４．１、Ｉｎ：Ｍ：Ｚｎ＝５：１：３、Ｉｎ：Ｍ：Ｚｎ＝５：１：６、Ｉｎ：Ｍ：Ｚｎ＝５：１：７、Ｉｎ：Ｍ：Ｚｎ＝５：１：８、Ｉｎ：Ｍ：Ｚｎ＝６：１：６、Ｉｎ：Ｍ：Ｚｎ＝１０：１：３、Ｉｎ：Ｍ：Ｚｎ＝１０：１：６、Ｉｎ：Ｍ：Ｚｎ＝１０：１：７、Ｉｎ：Ｍ：Ｚｎ＝１０：１：８、Ｉｎ：Ｍ：Ｚｎ＝５：２：５、Ｉｎ：Ｍ：Ｚｎ＝１０：１：１０、Ｉｎ：Ｍ：Ｚｎ＝２０：１：１０、Ｉｎ：Ｍ：Ｚｎ＝４０：１：１０、またはこれらの近傍の金属酸化物を用いてもよい。 When using In-M-Zn oxide for the semiconductor layer of an OS transistor, the atomic ratio of indium to the sum of the number of atoms of metal elements contained in the In-M-Zn oxide is higher than the atomic ratio of element M. High metal oxides may also be used. Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of element M. For example, in the semiconductor layer, the atomic ratio of the metal elements is In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, In:M:Zn=10:1:3, In:M:Zn=10:1:6, In: M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M: Zn=20:1:10, In:M:Zn=40:1:10, or metal oxides in the vicinity thereof may be used.
半導体層にＩｎ−Ｍ−Ｚｎ酸化物を用いる場合、金属元素の原子数比を、Ｉｎ：Ｍ：Ｚｎ＝１：３：２［原子数比］もしくはその近傍の組成、Ｉｎ：Ｍ：Ｚｎ＝１：３：４［原子数比］もしくはその近傍の組成、Ｉｎ：Ｍ：Ｚｎ＝１：１：０．５［原子数比］もしくはその近傍の組成、Ｉｎ：Ｍ：Ｚｎ＝１：１：１［原子数比］もしくはその近傍の組成、Ｉｎ：Ｍ：Ｚｎ＝１：１：１．２［原子数比］もしくはその近傍の組成、Ｉｎ：Ｍ：Ｚｎ＝１：１：２［原子数比］もしくはその近傍の組成、またはＩｎ：Ｍ：Ｚｎ＝４：２：３［原子数比］もしくはその近傍の組成の金属酸化物を用いてもよい。なお、近傍の組成とは、所望の原子数比の±３０％の範囲を含む。また、元素Ｍとして、ガリウムを用いることが好ましい。 When using In-M-Zn oxide for the semiconductor layer, the atomic ratio of the metal elements is In:M:Zn=1:3:2 [atomic ratio] or a composition in the vicinity thereof, In:M:Zn= Composition at or near 1:3:4 [atomic ratio], In:M:Zn=1:1:0.5 [atomic ratio] or near therein, In:M:Zn=1:1: 1 [atomic ratio] or a composition near it, In:M:Zn=1:1:1.2 [atomic ratio] or a composition near it, In:M:Zn=1:1:2 [number of atoms A metal oxide having a composition of In:M:Zn=4:2:3 [atomic ratio] or a composition near it may be used. Note that the nearby composition includes a range of ±30% of the desired atomic ratio. Further, as the element M, it is preferable to use gallium.
なお、元素Ｍとして複数の金属元素を有する場合は、当該金属元素の原子数比の合計を、元素Ｍの原子数比とすることができる。例えば、元素Ｍとしてガリウムとアルミニウムを有するＩｎ−Ｇａ−Ａｌ−Ｚｎ酸化物の場合、ガリウムの原子数比とアルミニウムの原子数比の合計を元素Ｍの原子数比とすることができる。また、インジウム、元素Ｍ、および亜鉛の原子数比が前述の範囲であることが好ましい。 Note that when the element M includes a plurality of metal elements, the sum of the atomic ratios of the metal elements can be the atomic ratio of the element M. For example, in the case of an In-Ga-Al-Zn oxide having gallium and aluminum as the element M, the atomic ratio of the element M can be the sum of the atomic ratio of gallium and the atomic ratio of aluminum. Further, it is preferable that the atomic ratio of indium, element M, and zinc is within the above range.
金属酸化物に含まれる主成分元素のうち、金属元素の原子数の和に対するインジウムの原子数の割合が、３０原子％以上１００原子％以下、好ましくは３０原子％以上９５原子％以下、より好ましくは３５原子％以上９５原子％以下、より好ましくは３５原子％以上９０原子％以下、より好ましくは４０原子％以上９０原子％以下、より好ましくは４５原子％以上９０原子％以下、より好ましくは５０原子％以上８０原子％以下、より好ましくは６０原子％以上８０原子％以下、より好ましくは７０原子％以上８０原子％以下である金属酸化物を用いることが好ましい。例えば、半導体層にＩｎ−Ｍ−Ｚｎ酸化物を用いる場合、インジウム、元素Ｍ、および亜鉛の原子数の合計に対する、インジウムの原子数の割合が前述の範囲であることが好ましい。 Among the main component elements contained in the metal oxide, the ratio of the number of atoms of indium to the sum of the number of atoms of metal elements is 30 atom % or more and 100 atom % or less, preferably 30 atom % or more and 95 atom % or less, more preferably is from 35 atom % to 95 atom %, more preferably from 35 atom % to 90 atom %, more preferably from 40 atom % to 90 atom %, more preferably from 45 atom % to 90 atom %, more preferably from 50 atom % to 90 atom %. It is preferable to use a metal oxide having a content of at least 60 at % and no more than 80 at %, more preferably at least 60 at % and no more than 80 at %. For example, when using In-M-Zn oxide for the semiconductor layer, it is preferable that the ratio of the number of indium atoms to the total number of atoms of indium, element M, and zinc is within the above range.
前述した通り、金属酸化物に含まれる主成分元素のうち、金属元素の原子数の和に対するインジウムの原子数の割合を高くすることにより、トランジスタの電界効果移動度を高めることができる。当該トランジスタを用いることにより、高速動作が可能な回路を作製することができる。さらには回路の占有面積を縮小することが可能となる。 As described above, among the main component elements contained in the metal oxide, the field effect mobility of the transistor can be increased by increasing the ratio of the number of indium atoms to the sum of the number of atoms of the metal elements. By using this transistor, a circuit that can operate at high speed can be manufactured. Furthermore, it becomes possible to reduce the area occupied by the circuit.
金属酸化物の組成の分析は、例えば、エネルギー分散型Ｘ線分光法（ＥＤＸ：Ｅｎｅｒｇｙ　Ｄｉｓｐｅｒｓｉｖｅ　Ｘ−ｒａｙ　ｓｐｅｃｔｒｏｓｃｏｐｙ）、Ｘ線光電子分光法（ＸＰＳ：Ｘ−ｒａｙ　Ｐｈｏｔｏｅｌｅｃｔｒｏｎ　Ｓｐｅｃｔｒｏｓｃｏｐｙ）、誘導結合プラズマ質量分析法（ＩＣＰ−ＭＳ：Ｉｎｄｕｃｔｉｖｅｌｙ　Ｃｏｕｐｌｅｄ　Ｐｌａｓｍａ−Ｍａｓｓ　Ｓｐｅｃｔｒｏｍｅｔｒｙ）、または誘導結合高周波プラズマ発光分光法（ＩＣＰ−ＡＥＳ：Ｉｎｄｕｃｔｉｖｅｌｙ　Ｃｏｕｐｌｅｄ　Ｐｌａｓｍａ−Ａｔｏｍｉｃ　Ｅｍｉｓｓｉｏｎ　Ｓｐｅｃｔｒｏｍｅｔｒｙ）を用いることができる。または、これらの手法を複数組み合わせて分析を行ってもよい。なお、含有率が低い元素は、分析精度の影響により、実際の含有率と分析によって得られた含有率が異なる場合がある。例えば、元素Ｍの含有率が低い場合、分析によって得られた元素Ｍの含有率が、実際の含有率より低くなる場合がある。 The analysis of the composition of the composition of metal oxides, for example, the energy distributed X -ray optical method (EDX: ENERGY DISPERSIVE X -RAY SPECTROSCOPY), X -ray optical electron division of light (XPS: X -Ray PhotoElECTRON SPECTROSCOP). Y), guidance bond plasma mass analysis method (ICP-MS: Inductively Coupled Plasma-Mass Spectrometry), or Inductively Coupled Plasma-Atomic Emis (ICP-AES) sion Spectrometry) can be used. Alternatively, analysis may be performed by combining two or more of these methods. Note that for elements with low content rates, the actual content rate and the content rate obtained by analysis may differ due to the influence of analysis accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.
金属酸化物の形成は、スパッタリング法、または原子層堆積（ＡＬＤ：Ａｔｏｍｉｃ　Ｌａｙｅｒ　Ｄｅｐｏｓｉｔｉｏｎ）法を好適に用いることができる。なお、金属酸化物をスパッタリング法で形成する場合、ターゲットの原子数比と、当該金属酸化物の原子数比が異なる場合がある。特に、亜鉛は、ターゲットの原子数比よりも金属酸化物の原子数比が小さくなる場合がある。具体的には、ターゲットに含まれる亜鉛の原子数比の４０％以上９０％以下程度となる場合がある。 A sputtering method or an atomic layer deposition (ALD) method can be suitably used to form the metal oxide. Note that when a metal oxide is formed by a sputtering method, the atomic ratio of the target and the atomic ratio of the metal oxide may be different. In particular, for zinc, the atomic ratio of the metal oxide may be smaller than the atomic ratio of the target. Specifically, the atomic ratio of zinc contained in the target may be about 40% or more and 90% or less.
なお、金属酸化物をスパッタリング法により成膜する場合、上記の原子数比は、成膜された金属酸化物の原子数比に限られず、金属酸化物の成膜に用いるスパッタリングターゲットの原子数比であってもよい。 In addition, when forming a metal oxide film by sputtering method, the above atomic ratio is not limited to the atomic ratio of the formed metal oxide, but also the atomic ratio of the sputtering target used for forming the metal oxide film. It may be.
ここで、トランジスタの信頼性について、説明する。トランジスタの信頼性を評価する指標の１つとして、ゲートに電界を印加した状態で保持する、ＧＢＴ（Ｇａｔｅ　Ｂｉａｓ　Ｔｅｍｐｅｒａｔｕｒｅ）ストレス試験がある。その中でも、ソース電位およびドレイン電位に対して、ゲートに正の電位（正バイアス）を与えた状態で、高温下で保持する試験をＰＢＴＳ（Ｐｏｓｉｔｉｖｅ　Ｂｉａｓ　Ｔｅｍｐｅｒａｔｕｒｅ　Ｓｔｒｅｓｓ）試験、ゲートに負の電位（負バイアス）を与えた状態で、高温下で保持する試験をＮＢＴＳ（Ｎｅｇａｔｉｖｅ　Ｂｉａｓ　Ｔｅｍｐｅｒａｔｕｒｅ　Ｓｔｒｅｓｓ）試験と呼ぶ。また、光を照射した状態で行うＰＢＴＳ試験およびＮＢＴＳ試験をそれぞれ、ＰＢＴＩＳ（Ｐｏｓｉｔｉｖｅ　Ｂｉａｓ　Ｔｅｍｐｅｒａｔｕｒｅ　Ｉｌｌｕｍｉｎａｔｉｏｎ　Ｓｔｒｅｓｓ）試験、ＮＢＴＩＳ（Ｎｅｇａｔｉｖｅ　Ｂｉａｓ　Ｔｅｍｐｅｒａｔｕｒｅ　Ｉｌｌｕｍｉｎａｔｉｏｎ　Ｓｔｒｅｓｓ）試験と呼ぶ。 Here, the reliability of the transistor will be explained. One of the indicators for evaluating the reliability of a transistor is a GBT (Gate Bias Temperature) stress test in which an electric field is applied to the gate and maintained. Among them, the PBTS (Positive Bias Temperature Stress) test is a test in which a positive potential (positive bias) is applied to the gate with respect to the source potential and drain potential, and the test is held at high temperature. A test in which the sample is held at a high temperature while applying a bias is called an NBTS (Negative Bias Temperature Stress) test. In addition, the PBTS test and NBTS test performed under light irradiation are respectively PBTIS (Positive Bias Temperature Illumination Stress) test and NBTIS (Negative Bias Temperature I) test. Illumination Stress) test.
ｎ型のトランジスタにおいては、トランジスタをオン状態とする際にゲートに正の電位が与えられるため、ＰＢＴＳ試験でのしきい値電圧の変動量が、トランジスタの信頼性の指標として着目すべき重要な項目の１つとなる。 In n-type transistors, a positive potential is applied to the gate when the transistor is turned on, so the amount of variation in threshold voltage in the PBTS test is an important indicator of transistor reliability. This is one of the items.
半導体層にガリウムを含まない、またはガリウムの含有率の低い金属酸化物を用いることにより、正バイアス印加に対する信頼性が高いトランジスタとすることができる。つまり、ＰＢＴＳ試験でのしきい値電圧の変動量が小さいトランジスタとすることができる。また、ガリウムを含む金属酸化物を用いる場合は、インジウムの含有率よりも、ガリウムの含有率を低くすることが好ましい。これにより、信頼性の高いトランジスタを実現することができる。 By using a metal oxide that does not contain gallium or has a low gallium content in the semiconductor layer, a transistor with high reliability against application of a positive bias can be obtained. In other words, a transistor with a small threshold voltage variation in the PBTS test can be obtained. Further, when using a metal oxide containing gallium, it is preferable that the gallium content is lower than the indium content. Thereby, a highly reliable transistor can be realized.
ＰＢＴＳ試験でのしきい値電圧の変動の１つの要因として、半導体層とゲート絶縁層の界面、または界面近傍における欠陥準位が挙げられる。欠陥準位密度が大きいほど、ＰＢＴＳ試験での劣化が顕著になる。半導体層の、ゲート絶縁層と接する領域におけるガリウムの含有率を低くすることにより、当該欠陥準位の生成を抑制できる。 One of the factors that causes the threshold voltage to fluctuate in the PBTS test is the defect level at or near the interface between the semiconductor layer and the gate insulating layer. The greater the defect level density, the more significant the deterioration in the PBTS test. By lowering the gallium content in the region of the semiconductor layer that is in contact with the gate insulating layer, generation of the defect level can be suppressed.
ガリウムを含まない、またはガリウムの含有率の低い金属酸化物を半導体層に用いることによりＰＢＴＳ試験でのしきい値電圧の変動を抑制できる理由として、例えば、以下のようなことが考えられる。金属酸化物に含まれるガリウムは、他の金属元素（例えば、インジウムまたは亜鉛）と比較して、酸素を誘引しやすい性質を有する。そのため、ガリウムを多く含む金属酸化物と、ゲート絶縁層との界面において、ガリウムがゲート絶縁層中の余剰酸素と結合することにより、キャリア（ここでは電子）トラップサイトを生じさせやすくなると推察される。そのため、ゲートに正の電位を与えた際に、半導体層とゲート絶縁層との界面にキャリアがトラップされることにより、しきい値電圧が変動することが考えられる。 Possible reasons for suppressing threshold voltage fluctuations in the PBTS test by using a metal oxide that does not contain gallium or has a low gallium content in the semiconductor layer are as follows, for example. Gallium contained in metal oxides has a property of attracting oxygen more easily than other metal elements (for example, indium or zinc). Therefore, it is presumed that at the interface between the metal oxide containing a large amount of gallium and the gate insulating layer, gallium combines with excess oxygen in the gate insulating layer, making it easier to generate carrier (electron in this case) trap sites. . Therefore, when a positive potential is applied to the gate, carriers are trapped at the interface between the semiconductor layer and the gate insulating layer, which may cause the threshold voltage to fluctuate.
より具体的には、半導体層にＩｎ−Ｇａ−Ｚｎ酸化物を用いた場合、インジウムの原子数比が、ガリウムの原子数比よりも高い金属酸化物を、半導体層に適用することができる。また、亜鉛の原子数比が、ガリウムの原子数比よりも高い金属酸化物を用いることが、より好ましい。言い換えると、金属元素の原子数比が、Ｉｎ＞Ｇａ、且つＺｎ＞Ｇａを満たす金属酸化物を、半導体層に適用することが好ましい。 More specifically, when an In-Ga-Zn oxide is used for the semiconductor layer, a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of gallium can be applied to the semiconductor layer. Further, it is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of gallium. In other words, it is preferable to apply a metal oxide in which the atomic ratio of metal elements satisfies In>Ga and Zn>Ga to the semiconductor layer.
例えば、ＯＳトランジスタの半導体層に、金属元素の原子数比が、Ｉｎ：Ｇａ：Ｚｎ＝２：１：３、Ｉｎ：Ｇａ：Ｚｎ＝３：１：２、Ｉｎ：Ｇａ：Ｚｎ＝４：２：３、Ｉｎ：Ｇａ：Ｚｎ＝４：２：４．１、Ｉｎ：Ｇａ：Ｚｎ＝５：１：３、Ｉｎ：Ｇａ：Ｚｎ＝５：１：６、Ｉｎ：Ｇａ：Ｚｎ＝５：１：７、Ｉｎ：Ｇａ：Ｚｎ＝５：１：８、Ｉｎ：Ｇａ：Ｚｎ＝６：１：６、Ｉｎ：Ｇａ：Ｚｎ＝１０：１：３、Ｉｎ：Ｇａ：Ｚｎ＝１０：１：６、Ｉｎ：Ｇａ：Ｚｎ＝１０：１：７、Ｉｎ：Ｇａ：Ｚｎ＝１０：１：８、Ｉｎ：Ｇａ：Ｚｎ＝５：２：５、Ｉｎ：Ｇａ：Ｚｎ＝１０：１：１０、Ｉｎ：Ｇａ：Ｚｎ＝２０：１：１０、Ｉｎ：Ｇａ：Ｚｎ＝４０：１：１０、またはこれらの近傍の金属酸化物を用いることができる。 For example, in the semiconductor layer of an OS transistor, the atomic ratio of metal elements is In:Ga:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2. :3, In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1 :7, In:Ga:Zn=5:1:8, In:Ga:Zn=6:1:6, In:Ga:Zn=10:1:3, In:Ga:Zn=10:1:6 , In:Ga:Zn=10:1:7, In:Ga:Zn=10:1:8, In:Ga:Zn=5:2:5, In:Ga:Zn=10:1:10, In :Ga:Zn=20:1:10, In:Ga:Zn=40:1:10, or metal oxides in the vicinity thereof can be used.
ＯＳトランジスタの半導体層は、含有される金属元素の原子数に対するガリウムの原子数の割合が、０原子％より高く５０原子％以下、好ましくは０．１原子％以上４０原子％以下、より好ましくは０．１原子％以上３５原子％以下、より好ましくは０．１原子％以上３０原子％以下、より好ましくは０．１原子％以上２５原子％以下、より好ましくは０．１原子％以上２０原子％以下、より好ましくは０．１原子％以上１５原子％以下、より好ましくは０．１原子％以上１０原子％以下である金属酸化物を用いることが好ましい。半導体層中のガリウムの含有率を低くすることにより、ＰＢＴＳ試験に対する耐性の高いトランジスタとすることができる。なお、金属酸化物にガリウムを含有させることにより、金属酸化物に酸素欠損（ＶＯ：Ｏｘｙｇｅｎ　Ｖａｃａｎｃｙ）が生じにくくなるといった効果を奏する。 In the semiconductor layer of the OS transistor, the ratio of the number of gallium atoms to the number of atoms of the metal element contained is greater than 0 atom % and less than 50 atom %, preferably from 0.1 atom % to 40 atom %, more preferably 0.1 atomic % or more and 35 atomic % or less, more preferably 0.1 atomic % or more and 30 atomic % or less, more preferably 0.1 atomic % or more and 25 atomic % or less, more preferably 0.1 atomic % or more and 20 atomic % or less % or less, more preferably 0.1 atomic % or more and 15 atomic % or less, more preferably 0.1 atomic % or more and 10 atomic % or less. By lowering the gallium content in the semiconductor layer, a transistor with high resistance to the PBTS test can be obtained. Note that by including gallium in the metal oxide, there is an effect that oxygen vacancy (V O ) is less likely to occur in the metal oxide.
ＯＳトランジスタの半導体層に、ガリウムを含まない金属酸化物を適用してもよい。例えば、Ｉｎ−Ｚｎ酸化物を半導体層に適用することができる。このとき、金属酸化物に含まれる金属元素の原子数に対するインジウムの原子数比を高くすることにより、トランジスタの電界効果移動度を高めることができる。一方、金属酸化物に含まれる金属元素の原子数に対する亜鉛の原子数比を高くすることにより、結晶性の高い金属酸化物となるため、トランジスタの電気特性の変動が抑制され、信頼性を高めることができる。また、半導体層には、酸化インジウムなどの、ガリウムおよび亜鉛を含まない金属酸化物を適用してもよい。ガリウムを含まない金属酸化物を用いることにより、特に、ＰＢＴＳ試験におけるしきい値電圧の変動を極めて小さなものとすることができる。 A metal oxide that does not contain gallium may be applied to the semiconductor layer of the OS transistor. For example, In--Zn oxide can be applied to the semiconductor layer. At this time, the field effect mobility of the transistor can be increased by increasing the ratio of the number of atoms of indium to the number of atoms of the metal element contained in the metal oxide. On the other hand, by increasing the ratio of the number of zinc atoms to the number of atoms of the metal elements contained in the metal oxide, the metal oxide becomes highly crystalline, which suppresses fluctuations in the electrical characteristics of the transistor and increases reliability. be able to. Furthermore, a metal oxide that does not contain gallium and zinc, such as indium oxide, may be applied to the semiconductor layer. By using a metal oxide that does not contain gallium, it is possible to make threshold voltage fluctuations extremely small, especially in PBTS tests.
例えば、半導体層に、インジウムと亜鉛を含む酸化物を用いることができる。このとき、金属元素の原子数比が、例えばＩｎ：Ｚｎ＝２：３、Ｉｎ：Ｚｎ＝４：１、またはこれらの近傍である金属酸化物を用いることができる。 For example, an oxide containing indium and zinc can be used for the semiconductor layer. At this time, a metal oxide in which the atomic ratio of metal elements is, for example, In:Zn=2:3, In:Zn=4:1, or in the vicinity thereof can be used.
なお、代表的にガリウムを挙げて説明したが、ガリウムに代えて元素Ｍを用いた場合にも適用できる。半導体層には、インジウムの原子数比が元素Ｍの原子数比よりも高い金属酸化物を適用することが好ましい。また、亜鉛の原子数比が元素Ｍの原子数比よりも高い金属酸化物を適用することが好ましい。 Although the explanation has been given using gallium as a representative example, the present invention can also be applied to a case where element M is used instead of gallium. It is preferable to use a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of element M to the semiconductor layer. Further, it is preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of element M.
半導体層に元素Ｍの含有率が低い金属酸化物を適用することにより、正バイアス印加に対する信頼性が高いトランジスタが実現できる。当該トランジスタを正バイアス印加に対する高い信頼性が求められるトランジスタに適用することにより、高い信頼性を有する半導体装置が実現できる。 By applying a metal oxide with a low content of element M to the semiconductor layer, a transistor with high reliability against application of a positive bias can be realized. By applying this transistor to a transistor that requires high reliability against application of a positive bias, a highly reliable semiconductor device can be realized.
半導体層は、２以上の金属酸化物層を有する積層構造としてもよい。半導体層が有する２以上の金属酸化物層は、組成が互いに同じ、または概略同じであってもよい。組成が同じ金属酸化物層の積層構造とすることで、例えば、同じスパッタリングターゲットを用いて形成できるため、製造コストを削減できる。 The semiconductor layer may have a stacked structure having two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer may have the same or approximately the same composition. By forming a stacked structure of metal oxide layers having the same composition, for example, the same sputtering target can be used to form the layers, thereby reducing manufacturing costs.
半導体層が有する２以上の金属酸化物層は、組成が互いに異なってもよい。例えば、Ｉｎ：Ｍ：Ｚｎ＝１：３：４［原子数比］もしくはその近傍の組成の第１の金属酸化物層と、当該第１の金属酸化物層上に設けられるＩｎ：Ｍ：Ｚｎ＝１：１：１［原子数比］もしくはその近傍の組成の第２の金属酸化物層と、の積層構造を好適に用いることができる。また、元素Ｍとして、ガリウムまたはアルミニウムを用いることが特に好ましい。例えば、インジウム酸化物、インジウムガリウム酸化物、およびＩＧＺＯの中から選ばれるいずれか一と、ＩＡＺＯ、ＩＡＧＺＯ、およびＩＴＺＯ（登録商標）の中から選ばれるいずれか一と、の積層構造などを用いてもよい。 The two or more metal oxide layers included in the semiconductor layer may have different compositions. For example, a first metal oxide layer having a composition of In:M:Zn=1:3:4 [atomic ratio] or a composition close to that, and In:M:Zn provided on the first metal oxide layer. A laminated structure with a second metal oxide layer having an atomic ratio of 1:1:1 or a composition close to this can be suitably used. Moreover, it is particularly preferable to use gallium or aluminum as the element M. For example, using a laminated structure of one selected from indium oxide, indium gallium oxide, and IGZO and one selected from IAZO, IAGZO, and ITZO (registered trademark), etc. Good too.
また、例えば、Ｉｎ：Ｍ：Ｚｎ＝１：１：１［原子数比］もしくはその近傍の組成の第１の金属酸化物層と、当該第１の金属酸化物層上に設けられるＩｎ：Ｚｎ＝４：１［原子数比］もしくはその近傍の組成の第２の金属酸化物層と、の積層構造を用いてもよい。 Further, for example, a first metal oxide layer having a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition close to that, and an In:Zn layer provided on the first metal oxide layer. A stacked structure with a second metal oxide layer having a composition of =4:1 [atomic ratio] or a composition close to this may also be used.
半導体層は、結晶性を有する金属酸化物層を用いることが好ましい。例えば、ＣＡＡＣ（ｃ−ａｘｉｓ　ａｌｉｇｎｅｄ　ｃｒｙｓｔａｌ）構造、多結晶構造、微結晶（ｎｃ：ｎａｎｏ−ｃｒｙｓｔａｌ）構造等を有する金属酸化物層を用いることができる。結晶性を有する金属酸化物層を半導体層に用いることにより、半導体層中の欠陥準位密度を低減でき、信頼性の高い表示装置を実現できる。 It is preferable to use a metal oxide layer having crystallinity as the semiconductor layer. For example, a metal oxide layer having a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, a microcrystalline (NC: nano-crystal) structure, etc. can be used. By using a crystalline metal oxide layer as a semiconductor layer, the density of defect levels in the semiconductor layer can be reduced, and a highly reliable display device can be realized.
半導体層に用いる金属酸化物層の結晶性が高いほど、半導体層中の欠陥準位密度を低減できる。一方、結晶性の低い金属酸化物層を用いることで、大きな電流を流すことができるトランジスタを実現することができる。 The higher the crystallinity of the metal oxide layer used in the semiconductor layer, the more the density of defect levels in the semiconductor layer can be reduced. On the other hand, by using a metal oxide layer with low crystallinity, a transistor that can flow a large current can be realized.
金属酸化物層をスパッタリング法により形成する場合、形成時の基板温度（ステージ温度）が高いほど、結晶性の高い金属酸化物層を形成することができる。また、形成時に用いる成膜ガス全体に対する酸素ガスの流量の割合（以下、酸素流量比ともいう）が高いほど、結晶性の高い金属酸化物層を形成することができる。 When forming a metal oxide layer by a sputtering method, the higher the substrate temperature (stage temperature) during formation, the more crystalline the metal oxide layer can be formed. Furthermore, the higher the ratio of the flow rate of oxygen gas to the entire film-forming gas used during formation (hereinafter also referred to as oxygen flow rate ratio), the more crystalline the metal oxide layer can be formed.
ＯＳトランジスタの半導体層は、結晶性が異なる２以上の金属酸化物層の積層構造であってもよい。例えば、第１の金属酸化物層と、当該第１の金属酸化物層上に設けられる第２の金属酸化物層と、の積層構造とし、第２の金属酸化物層は、第１の金属酸化物層より結晶性が高い領域を有する構成とすることができる。または、第２の金属酸化物層は、第１の金属酸化物層より結晶性が低い領域を有する構成とすることができる。半導体層が有する２以上の金属酸化物層は、組成が互いに同じ、または概略同じであってもよい。組成が同じ金属酸化物層の積層構造とすることで、例えば、同じスパッタリングターゲットを用いて形成できるため、製造コストを削減できる。例えば、同じスパッタリングターゲットを用いて、酸素流量比を異ならせることにより、結晶性が異なる２以上の金属酸化物層の積層構造を形成することができる。なお、半導体層が有する２以上の金属酸化物層は、組成が互いに異なってもよい。 The semiconductor layer of the OS transistor may have a stacked structure of two or more metal oxide layers having different crystallinity. For example, the layered structure includes a first metal oxide layer and a second metal oxide layer provided on the first metal oxide layer, and the second metal oxide layer The structure can include a region having higher crystallinity than the oxide layer. Alternatively, the second metal oxide layer may have a region having lower crystallinity than the first metal oxide layer. The two or more metal oxide layers included in the semiconductor layer may have the same or approximately the same composition. By forming a stacked structure of metal oxide layers having the same composition, for example, the same sputtering target can be used to form the layers, thereby reducing manufacturing costs. For example, by using the same sputtering target and varying the oxygen flow rate ratio, a stacked structure of two or more metal oxide layers having different crystallinity can be formed. Note that the two or more metal oxide layers included in the semiconductor layer may have different compositions.
半導体層１６３に酸化物半導体を用いる場合は、絶縁層１５７と絶縁層１５９に水素を含む材料を用いることが好ましい。水素を含む絶縁層が酸化物半導体に接することで、該絶縁層が接する領域の酸化物半導体がｎ型化され、ソース領域またはドレイン領域として機能できる。該絶縁層として、例えば、シリコン、窒素、および水素を含む材料を用いればよい。具体的には、水素を含む窒化シリコンまたは水素を含む窒化酸化シリコンなどを用いればよい。 When an oxide semiconductor is used for the semiconductor layer 163, a material containing hydrogen is preferably used for the insulating layer 157 and the insulating layer 159. When the insulating layer containing hydrogen is in contact with the oxide semiconductor, the oxide semiconductor in the region in contact with the insulating layer is made n-type and can function as a source region or a drain region. For example, a material containing silicon, nitrogen, and hydrogen may be used as the insulating layer. Specifically, silicon nitride containing hydrogen, silicon nitride oxide containing hydrogen, or the like may be used.
絶縁層１５７および絶縁層１５９の膜厚はそれぞれ、１ｎｍ以上１５ｎｍ以下が好ましく、２ｎｍ以上１０ｎｍ以下がより好ましく、３ｎｍ以上７ｎｍ以下がより好ましく、さらには３ｎｍ以上５ｎｍ以下が好ましい。半導体層１６３に酸化物半導体を用いる場合は、半導体層１６３の水素を含む絶縁層１５７と接する領域と、水素を含む絶縁層１５９と接する領域がソース領域またはドレイン領域として機能する。絶縁層１５７および絶縁層１５９の膜厚を調整することで、半導体層１６３に形成されるソース領域およびドレイン領域の大きさを制御できる。 The thickness of the insulating layer 157 and the insulating layer 159 is preferably 1 nm or more and 15 nm or less, more preferably 2 nm or more and 10 nm or less, more preferably 3 nm or more and 7 nm or less, and further preferably 3 nm or more and 5 nm or less. When an oxide semiconductor is used for the semiconductor layer 163, a region of the semiconductor layer 163 in contact with the insulating layer 157 containing hydrogen and a region in contact with the insulating layer 159 containing hydrogen function as a source region or a drain region. By adjusting the thicknesses of the insulating layer 157 and the insulating layer 159, the sizes of the source region and drain region formed in the semiconductor layer 163 can be controlled.
絶縁層１５８の膜厚は、１ｎｍ以上５０ｎｍ以下が好ましく、２ｎｍ以上３０ｎｍ以下がより好ましく、３ｎｍ以上２ｎｍ以下がさらに好ましい。絶縁層１５８の膜厚を調整することで、半導体層１６３のチャネル形成領域の大きさを制御できる。 The thickness of the insulating layer 158 is preferably 1 nm or more and 50 nm or less, more preferably 2 nm or more and 30 nm or less, and even more preferably 3 nm or more and 2 nm or less. By adjusting the thickness of the insulating layer 158, the size of the channel formation region of the semiconductor layer 163 can be controlled.
絶縁層１５７、絶縁層１５８、および絶縁層１５９の膜厚は、トランジスタ１００に求める特性に合わせて、適宜設定すればよい。 The thicknesses of the insulating layer 157, the insulating layer 158, and the insulating layer 159 may be appropriately set according to the characteristics required of the transistor 100.
また、絶縁層１５７、絶縁層１５８、および絶縁層１５９の成膜は、途中で大気環境にさらすことなく連続して行なうことが好ましい。絶縁層１５７、絶縁層１５８、および絶縁層１５９の成膜を途中で大気環境にさらすことなく連続して行なうことで、絶縁層１５７と絶縁層１５８の界面およびその近傍、ならびに、絶縁層１５８と絶縁層１５９の界面およびその近傍に大気環境からの不純物または水分が付着することを防ぐことができる。 Further, it is preferable that the insulating layer 157, the insulating layer 158, and the insulating layer 159 be formed successively without being exposed to the atmospheric environment midway. By sequentially forming the insulating layer 157, the insulating layer 158, and the insulating layer 159 without exposing them to the atmospheric environment during the process, the interface between the insulating layer 157 and the insulating layer 158 and its vicinity, as well as the insulating layer 158 and Impurities or moisture from the atmospheric environment can be prevented from adhering to the interface of the insulating layer 159 and its vicinity.
また、半導体層１６３に酸化物半導体を用いる場合は、半導体層１６３と接する導電層１５５、および、半導体層１６３と接する導電層１６１は、酸化物半導体をｎ型化する導電性材料を用いることが好ましい。例えば、窒素を含む導電性材料を用いればよい。例えば、チタンまたはタンタルと、窒素と、を含む導電性材料を用いればよい。また、窒素を含む導電性材料に重ねて、他の導電性材料を設けてもよい。 Further, when an oxide semiconductor is used for the semiconductor layer 163, the conductive layer 155 in contact with the semiconductor layer 163 and the conductive layer 161 in contact with the semiconductor layer 163 can be formed using a conductive material that converts the oxide semiconductor into n-type. preferable. For example, a conductive material containing nitrogen may be used. For example, a conductive material containing titanium or tantalum and nitrogen may be used. Further, another conductive material may be provided over the conductive material containing nitrogen.
一方で、絶縁層１５８には水素が低減され、酸素を含む材料を用いることが好ましい。例えば、シリコンおよび酸素を含む材料を用いればよい。具体的には、酸化シリコンまたは酸化窒化シリコンなどを用いればよい。酸化物半導体において水素は不純物元素であるため、酸化物半導体である半導体層１６３と水素が低減された絶縁層１５８が接することで、半導体層１６３がｎ型化されにくくなる。また、酸化物半導体である半導体層１６３と酸素を含む絶縁層１５８が接することで、半導体層１６３の酸素欠損が低減され、トランジスタ１００の特性が安定し、信頼性が向上する。 On the other hand, it is preferable to use a material containing reduced hydrogen and oxygen for the insulating layer 158. For example, a material containing silicon and oxygen may be used. Specifically, silicon oxide, silicon oxynitride, or the like may be used. Since hydrogen is an impurity element in an oxide semiconductor, the semiconductor layer 163 which is an oxide semiconductor and the insulating layer 158 with reduced hydrogen are in contact with each other, making it difficult for the semiconductor layer 163 to become n-type. Further, since the semiconductor layer 163, which is an oxide semiconductor, and the insulating layer 158 containing oxygen are in contact with each other, oxygen vacancies in the semiconductor layer 163 are reduced, the characteristics of the transistor 100 are stabilized, and reliability is improved.
また、半導体層１６３に酸化物半導体を用いる場合は、絶縁層１５８は過剰酸素を含むことが好ましい。本明細書等において、過剰酸素とは、加熱により離脱する酸素のことを示す。また、絶縁層１５８に過剰酸素を含む材料を用いる場合、絶縁層１５７と絶縁層１５９に酸素が透過しにくい材料を用いることが好ましい。酸素が透過しにくい材料として、例えば、アルミニウムおよびハフニウムの一方または双方を含む酸化物、シリコンの窒化物などを用いることができる。絶縁層１５７と絶縁層１５９に酸素が透過しにくい材料を用いることで、絶縁層１５８に含まれる過剰酸素が下層または上層に脱離しにくくなる。よって、酸化物半導体に十分な酸素を供給できる。例えば、シリコンおよび窒素を含む２層の絶縁層（絶縁層１５７、絶縁層１５９）の間に、シリコンおよび酸素を含む絶縁層（絶縁層１５８）を有する構成とすればよい。 Further, when an oxide semiconductor is used for the semiconductor layer 163, the insulating layer 158 preferably contains excess oxygen. In this specification and the like, excess oxygen refers to oxygen released by heating. Further, when a material containing excess oxygen is used for the insulating layer 158, it is preferable that a material through which oxygen does not easily permeate is used for the insulating layer 157 and the insulating layer 159. For example, an oxide containing one or both of aluminum and hafnium, silicon nitride, and the like can be used as the material that is difficult for oxygen to pass through. By using a material that is difficult for oxygen to permeate for the insulating layer 157 and the insulating layer 159, excess oxygen contained in the insulating layer 158 is difficult to desorb into the lower layer or the upper layer. Therefore, sufficient oxygen can be supplied to the oxide semiconductor. For example, an insulating layer containing silicon and oxygen (insulating layer 158) may be provided between two insulating layers containing silicon and nitrogen (insulating layer 157, insulating layer 159).
また、半導体層１６３に酸化物半導体を用いて、絶縁層１５７と絶縁層１５９に水素を含む材料を用いることにより、半導体層１６３の絶縁層１５７と接する領域と、半導体層１６３の絶縁層１５９と接する領域に水素が供給され、半導体層１６３のそれぞれの領域がｎ型化する。よって、半導体層１６３の導電層１６１と接する領域、および、半導体層１６３の絶縁層１５９と接する領域が、ソース（ソース領域）またはドレイン（ドレイン領域）の一方として機能する。また、半導体層１６３の導電層１５５と接する領域、および、半導体層１６３の絶縁層１５７と接する領域が、ソース（ソース領域）またはドレイン（ドレイン領域）の他方として機能する。 Further, by using an oxide semiconductor for the semiconductor layer 163 and using a material containing hydrogen for the insulating layer 157 and the insulating layer 159, the region of the semiconductor layer 163 in contact with the insulating layer 157 and the insulating layer 159 of the semiconductor layer 163 can be Hydrogen is supplied to the contacting regions, and each region of the semiconductor layer 163 becomes n-type. Therefore, a region of the semiconductor layer 163 in contact with the conductive layer 161 and a region of the semiconductor layer 163 in contact with the insulating layer 159 function as either a source (source region) or a drain (drain region). Further, a region of the semiconductor layer 163 in contact with the conductive layer 155 and a region of the semiconductor layer 163 in contact with the insulating layer 157 function as the other of the source (source region) and the drain (drain region).
この場合、Ｘ方向またはＹ方向から見た絶縁層１５８側面の長さがチャネル長Ｌ（チャネル長Ｌ１）になる（図３Ａ参照）。よって、絶縁層１５８の厚さｔに応じてトランジスタ１００のチャネル長Ｌが決定される。図３Ａは、図１Ｂに示したトランジスタ１００を拡大した断面図である。また、図４Ａおよび図４Ｂは、図３Ａの変形例であり、図１Ｂに示したトランジスタ１００を拡大した断面図に相当する。 In this case, the length of the side surface of the insulating layer 158 when viewed from the X direction or the Y direction becomes the channel length L (channel length L1) (see FIG. 3A). Therefore, the channel length L of the transistor 100 is determined according to the thickness t of the insulating layer 158. FIG. 3A is an enlarged cross-sectional view of the transistor 100 shown in FIG. 1B. Further, FIGS. 4A and 4B are modified examples of FIG. 3A, and correspond to enlarged cross-sectional views of the transistor 100 shown in FIG. 1B.
また、絶縁層１５７と絶縁層１５９に、水素を含まないまたは水素が極めて少ない材料を用いてもよい。例えば、水素が極めて少ない窒化シリコンまたは水素が極めて少ない窒化酸化シリコンなどを用いてもよい。この場合は、半導体層１６３が絶縁層１５７と接する領域および半導体層１６３が絶縁層１５９と接する領域がｎ型化されない。よって、半導体層１６３の導電層１６１と接する領域が、ソース（ソース領域）またはドレイン（ドレイン領域）の一方として機能する。また、半導体層１６３の導電層１５５と接する領域が、ソース（ソース領域）またはドレイン（ドレイン領域）の他方として機能する。また、半導体層１６３の絶縁層１５８と接する領域が、チャネル形成領域として機能する。 Further, the insulating layer 157 and the insulating layer 159 may be made of a material that does not contain hydrogen or contains very little hydrogen. For example, silicon nitride with extremely low hydrogen content or silicon nitride oxide with extremely low hydrogen content may be used. In this case, the region where the semiconductor layer 163 contacts the insulating layer 157 and the region where the semiconductor layer 163 contacts the insulating layer 159 are not converted to n-type. Therefore, a region of the semiconductor layer 163 in contact with the conductive layer 161 functions as either a source (source region) or a drain (drain region). Further, a region of the semiconductor layer 163 in contact with the conductive layer 155 functions as the other of a source (source region) and a drain (drain region). Further, a region of the semiconductor layer 163 in contact with the insulating layer 158 functions as a channel formation region.
この場合、Ｘ方向またはＹ方向から見た絶縁層１５７、絶縁層１５８、および絶縁層１５９それぞれの側面の長さの合計がチャネル長Ｌ（チャネル長Ｌ２）になる。よって、絶縁層１５７、絶縁層１５８および絶縁層１５９それぞれの厚さを合算した厚さｔｓに応じてトランジスタ１００のチャネル長Ｌが決定される。 In this case, the sum of the lengths of the side surfaces of the insulating layer 157, the insulating layer 158, and the insulating layer 159 when viewed from the X direction or the Y direction is the channel length L (channel length L2). Therefore, the channel length L of the transistor 100 is determined according to the total thickness ts of the respective thicknesses of the insulating layer 157, the insulating layer 158, and the insulating layer 159.
また、絶縁層１５７と絶縁層１５９を設けずに、絶縁層１５８のみを設けて、絶縁層１５８が導電層１５５と導電層１６１に接する構成としてもよい（図４Ａ参照）。この場合、Ｘ方向またはＹ方向から見た絶縁層１５８の側面の長さがチャネル長Ｌになる。よって、絶縁層１５８の厚さｔに応じてトランジスタ１００のチャネル長Ｌが決定される。また、図４Ａに示す構成の場合、絶縁層１５８を絶縁層１５６と呼ぶ場合がある。 Alternatively, only the insulating layer 158 may be provided without providing the insulating layer 157 and the insulating layer 159, and the insulating layer 158 may be in contact with the conductive layer 155 and the conductive layer 161 (see FIG. 4A). In this case, the length of the side surface of the insulating layer 158 when viewed from the X direction or the Y direction is the channel length L. Therefore, the channel length L of the transistor 100 is determined according to the thickness t of the insulating layer 158. Further, in the case of the structure shown in FIG. 4A, the insulating layer 158 may be referred to as an insulating layer 156.
また、半導体層１６３に酸化物半導体を用いて、絶縁層１５７と絶縁層１５９に水素を含む材料を用い、絶縁層１５８に過剰酸素を含む材料を用いると、絶縁層１５７と絶縁層１５９に含まれる水素と、絶縁層１５８に含まれる過剰酸素が結合し、半導体層１６３の絶縁層１５７と接する領域および半導体層１６３の絶縁層１５９と接する領域に十分な水素が供給されなくなりｎ型化しにくくなる。同様に、半導体層１６３の絶縁層１５８と接する領域に十分な酸素が供給されなくなる。 Further, when an oxide semiconductor is used for the semiconductor layer 163, a material containing hydrogen is used for the insulating layer 157 and the insulating layer 159, and a material containing excess oxygen is used for the insulating layer 158, the insulating layer 157 and the insulating layer 159 contain hydrogen. The hydrogen contained in the semiconductor layer 163 and the excess oxygen contained in the insulating layer 158 combine, and sufficient hydrogen is not supplied to the region of the semiconductor layer 163 in contact with the insulating layer 157 and the region of the semiconductor layer 163 in contact with the insulating layer 159, making it difficult to convert into n-type. . Similarly, sufficient oxygen is no longer supplied to the region of the semiconductor layer 163 in contact with the insulating layer 158.
このような問題を解決するため、酸素および窒素が透過しにくい絶縁層１７１を絶縁層１５７と絶縁層１５８の間に設け、酸素および窒素が透過しにくい絶縁層１７２を絶縁層１５９と絶縁層１５８の間に設けてもよい（図４Ｂ参照）。酸素および窒素が透過しにくい材料は、例えば、シリコンの窒化物などを用いて実現できる。なお、図４Ｂに示す構成の場合、絶縁層１５７、絶縁層１７１、絶縁層１５８、絶縁層１７２、および絶縁層１５９を併せて絶縁層１５６と呼ぶ場合がある。 In order to solve this problem, an insulating layer 171 through which oxygen and nitrogen are difficult to permeate is provided between the insulating layer 157 and the insulating layer 158, and an insulating layer 172 through which oxygen and nitrogen are difficult to permeate is provided between the insulating layer 159 and the insulating layer 158. (See FIG. 4B). A material that is difficult for oxygen and nitrogen to permeate can be realized using, for example, silicon nitride. Note that in the case of the structure shown in FIG. 4B, the insulating layer 157, the insulating layer 171, the insulating layer 158, the insulating layer 172, and the insulating layer 159 may be collectively referred to as an insulating layer 156.
絶縁層１７１と絶縁層１７２に酸素が透過しにくい材料を用いることで、絶縁層１５７と絶縁層１５９に含まれる水素と絶縁層１５８に含まれる過剰酸素の結合が阻害される。よって、半導体層１６３の絶縁層１５７と接する領域および半導体層１６３の絶縁層１５９と接する領域に十分な水素が供給される。同様に、半導体層１６３の絶縁層１５８と接する領域に十分な酸素が供給される。 By using a material that is difficult for oxygen to permeate for the insulating layer 171 and the insulating layer 172, the bond between the hydrogen contained in the insulating layer 157 and the insulating layer 159 and the excess oxygen contained in the insulating layer 158 is inhibited. Therefore, sufficient hydrogen is supplied to the region of the semiconductor layer 163 in contact with the insulating layer 157 and the region of the semiconductor layer 163 in contact with the insulating layer 159. Similarly, sufficient oxygen is supplied to the region of the semiconductor layer 163 in contact with the insulating layer 158.
この場合、Ｘ方向またはＹ方向から見た絶縁層１７１、絶縁層１５８、および絶縁層１７２それぞれの側面の長さの合計がチャネル長Ｌになる。よって、絶縁層１７１、絶縁層１５８および絶縁層１７２それぞれの厚さを合算した厚さｔｍに応じてトランジスタ１００のチャネル長Ｌが決定される。 In this case, the channel length L is the sum of the lengths of the side surfaces of the insulating layer 171, the insulating layer 158, and the insulating layer 172 when viewed from the X direction or the Y direction. Therefore, the channel length L of the transistor 100 is determined according to the total thickness tm of the thicknesses of the insulating layer 171, the insulating layer 158, and the insulating layer 172.
本発明の一態様に係るトランジスタ１００は、導電層１６１と導電層１５５の間に設けられる絶縁層の厚さに応じてチャネル長Ｌが決定される。よって、チャネル長Ｌが短いトランジスタを精度よく作製できる。また、複数のトランジスタ１００間の特性ばらつきも低減される。よって、トランジスタ１００を含む半導体装置の動作が安定し、信頼性を高めることができる。また、特性ばらつきが減ると、半導体装置の回路設計自由度が高くなり、動作電圧も低減できる。よって、半導体装置の消費電力を低減できる。 In the transistor 100 according to one embodiment of the present invention, the channel length L is determined depending on the thickness of the insulating layer provided between the conductive layer 161 and the conductive layer 155. Therefore, a transistor with a short channel length L can be manufactured with high precision. Furthermore, variations in characteristics among the plurality of transistors 100 are also reduced. Therefore, the operation of the semiconductor device including the transistor 100 is stabilized, and reliability can be improved. Further, when characteristic variations are reduced, the degree of freedom in circuit design of the semiconductor device increases, and the operating voltage can also be reduced. Therefore, power consumption of the semiconductor device can be reduced.
なお、本実施の形態では、導電層１５５と導電層１６１の間に３層の絶縁層（絶縁層１５７、絶縁層１５８、絶縁層１５９）を有する構成を示しているが、導電層１５５と導電層１６１の間の絶縁層の層数はこれに限定されない。導電層１５５と導電層１６１の間の絶縁層は１層または２層でもよいし、４層以上であってもよい。 Note that in this embodiment, a structure in which three insulating layers (insulating layer 157, insulating layer 158, and insulating layer 159) are provided between conductive layer 155 and conductive layer 161 is shown; The number of insulating layers between layers 161 is not limited to this. The number of insulating layers between the conductive layer 155 and the conductive layer 161 may be one or two layers, or may be four or more layers.
また、開口１６２内に形成される半導体層１６３、絶縁層１６４、および導電層１６５の被覆性を高めるため、開口１６２側面のテーパー角θ、すなわち、絶縁層１５７、絶縁層１５８、および絶縁層１５９それぞれの側面のテーパー角θを、４５度以上９０度以下、好ましくは５０度以上７５度以下とすればよい。なお、層（絶縁層、導電層、または半導体層）側面のテーパー角θとは、当該層の底面と側面のなす角度を言う（図３Ａ参照）。 In addition, in order to improve the coverage of the semiconductor layer 163, insulating layer 164, and conductive layer 165 formed in the opening 162, the taper angle θ of the side surface of the opening 162, that is, the insulating layer 157, the insulating layer 158, and the insulating layer 159 The taper angle θ of each side surface may be greater than or equal to 45 degrees and less than or equal to 90 degrees, preferably greater than or equal to 50 degrees and less than or equal to 75 degrees. Note that the taper angle θ of the side surface of a layer (insulating layer, conductive layer, or semiconductor layer) refers to the angle formed between the bottom surface and the side surface of the layer (see FIG. 3A).
また、半導体層１６３は開口１６２に設けられているため、Ｚ方向から見た時の開口１６２の周の長さがトランジスタ１００のチャネル幅Ｗとなる（図３Ｂ参照）。周の長さは、例えば、絶縁層１５８の厚さｔの半分（ｔ／２）の位置もしくは、厚さｔｓの半分（ｔｓ／２）の位置で求めればよい。なお、必要に応じて、開口１６２の任意の位置の周の長さをチャネル幅Ｗとしてもよい。例えば、開口１６２の最下部の周の長さをチャネル幅Ｗとしてもよいし、開口１６２の最上部の周の長さをチャネル幅Ｗとしてもよい。 Further, since the semiconductor layer 163 is provided in the opening 162, the circumferential length of the opening 162 when viewed from the Z direction becomes the channel width W of the transistor 100 (see FIG. 3B). The circumferential length may be determined, for example, at a position at half the thickness t (t/2) of the insulating layer 158 or at a position at half the thickness ts (ts/2). Note that, if necessary, the length of the circumference of an arbitrary position of the opening 162 may be set as the channel width W. For example, the length of the circumference at the bottom of the opening 162 may be set as the channel width W, or the length of the circumference at the top of the opening 162 may be set as the channel width W.
また、本発明の一態様の記憶装置においては、チャネル長Ｌは、少なくともチャネル幅Ｗよりも小さいことが好ましい。本発明の一態様のチャネル長Ｌは、チャネル幅Ｗに対し、０．１倍以上０．９９倍以下、好ましくは０．５倍以上０．８倍以下である。 Further, in the storage device of one embodiment of the present invention, the channel length L is preferably smaller than at least the channel width W. The channel length L of one aspect of the present invention is 0.1 times or more and 0.99 times or less, preferably 0.5 times or more and 0.8 times or less, with respect to the channel width W.
また、図３Ｂでは、Ｚ方向から見た開口１６２の輪郭（平面形状）を円形で示しているが、これに限定されない。例えば、Ｚ方向から見た開口１６２の輪郭は、楕円形（図３Ｃ参照）でもよいし、矩形（図３Ｄ参照）でもよい。なお、図３Ｄでは角部が湾曲した矩形を示している。また、例えば、Ｚ方向から見た開口１６２の輪郭は、直線部と曲線部の一方または双方を含む形状（図３Ｅ参照）であってもよい。 Further, in FIG. 3B, the outline (planar shape) of the opening 162 viewed from the Z direction is shown as a circle, but the shape is not limited to this. For example, the outline of the opening 162 viewed from the Z direction may be elliptical (see FIG. 3C) or rectangular (see FIG. 3D). Note that FIG. 3D shows a rectangle with curved corners. Further, for example, the outline of the opening 162 viewed from the Z direction may have a shape including one or both of a straight part and a curved part (see FIG. 3E).
なお、開口１６２は微細であることが好ましい。例えば、Ｚ方向から見た開口１６２の最大幅（開口１６２が円形である場合は最大径。）は、６０ｎｍ以下が好ましく、５０ｎｍ以下がより好ましく、４０ｎｍ以下がさらに好ましく、３０ｎｍ以下が極めて好ましい。Ｚ方向から見た開口１６２の最大幅は２０ｎｍ以下であってもよい。なお、Ｚ方向から見た開口１６２の最小幅（開口１６２が円形である場合は最小径。）は、１ｎｍ以上が好ましく、５ｎｍ以上がより好ましい。このように微細な開口１６２を形成するには、ＥＵＶ光などの短波長の光、または電子ビームを用いたリソグラフィー法を用いることが好ましい。 Note that the opening 162 is preferably fine. For example, the maximum width of the opening 162 (the maximum diameter if the opening 162 is circular) as viewed from the Z direction is preferably 60 nm or less, more preferably 50 nm or less, even more preferably 40 nm or less, and extremely preferably 30 nm or less. The maximum width of the opening 162 viewed from the Z direction may be 20 nm or less. Note that the minimum width of the opening 162 (minimum diameter when the opening 162 is circular) as viewed from the Z direction is preferably 1 nm or more, more preferably 5 nm or more. In order to form such a minute opening 162, it is preferable to use a lithography method using short wavelength light such as EUV light or an electron beam.
図５Ａおよび図５Ｂに、半導体装置１０Ａをマトリクス状に配置した平面レイアウトの一例を示す。図５Ａは、Ｘ方向に沿って導電層１６８と開口１６２（半導体装置１０Ａ）が交互に配置される領域、Ｙ方向に沿って導電層１６８が繰り返し配置される領域、およびＹ方向に沿って開口１６２（半導体装置１０Ａ）が繰り返し配置される領域が生じる平面レイアウトである。図５Ａに示す平面レイアウトでは、Ｘ方向から見た時に、導電層１６８と開口１６２が重なる。 5A and 5B show an example of a planar layout in which semiconductor devices 10A are arranged in a matrix. FIG. 5A shows a region where conductive layers 168 and openings 162 (semiconductor device 10A) are arranged alternately along the X direction, a region where conductive layers 168 are repeatedly arranged along the Y direction, and an opening along the Y direction. This is a planar layout in which a region in which 162 (semiconductor devices 10A) are repeatedly arranged is generated. In the planar layout shown in FIG. 5A, the conductive layer 168 and the opening 162 overlap when viewed from the X direction.
図５Ｂは、Ｘ方向に沿って導電層１６８が繰り返し配置される領域、Ｘ方向に沿って開口１６２（半導体装置１０Ａ）が繰り返し配置される領域、Ｙ方向に沿って導電層１６８が繰り返し配置される領域、およびＹ方向に沿って開口１６２（半導体装置１０Ａ）が繰り返し配置される領域が生じる平面レイアウトである。 FIG. 5B shows a region where the conductive layer 168 is repeatedly arranged along the X direction, a region where the opening 162 (semiconductor device 10A) is repeatedly arranged along the X direction, and a region where the conductive layer 168 is repeatedly arranged along the Y direction. This is a planar layout in which there are regions where the openings 162 (semiconductor device 10A) are repeatedly arranged along the Y direction.
図５Ｂに示す平面レイアウトでは、導電層１６８と開口１６２が斜めに配置されている。また、図５Ｂでは、導電層１６８と半導体装置１０Ａを電気的に接続する導電層１６１が斜めに配置されている。すなわち、Ｚ方向から見た時に、導電層１６８の中央と開口１６２の中央を結ぶ直線が、Ｘ方向と直交せず、Ｙ方向とも直交しない。導電層１６８と開口１６２を斜めに配置することで、半導体装置１０Ａを効率よく配置できる場合がある。よって、半導体装置１０Ａの集積度が向上し、半導体装置１０Ａを含む記憶装置の単位面積当たりの記憶容量を増やすことができる場合がある。 In the planar layout shown in FIG. 5B, the conductive layer 168 and the opening 162 are arranged diagonally. Further, in FIG. 5B, the conductive layer 161 that electrically connects the conductive layer 168 and the semiconductor device 10A is arranged obliquely. That is, when viewed from the Z direction, the straight line connecting the center of the conductive layer 168 and the center of the opening 162 is neither perpendicular to the X direction nor perpendicular to the Y direction. By arranging the conductive layer 168 and the opening 162 diagonally, the semiconductor device 10A may be arranged efficiently. Therefore, the degree of integration of the semiconductor device 10A may be improved, and the storage capacity per unit area of the storage device including the semiconductor device 10A may be increased.
＜変形例１＞
図６Ａおよび図６Ｂに、半導体装置１０Ａの変形例である半導体装置１０Ｂを示す。図６Ａは、半導体装置１０Ｂの上面図である。図６Ｂは、図６ＡにＡ１−Ａ２の一点鎖線で示す部位の断面図である。図６Ｃは、図６ＡにＡ３−Ａ４の一点鎖線で示す部位の断面図である。 <Modification 1>
6A and 6B show a semiconductor device 10B that is a modification of the semiconductor device 10A. FIG. 6A is a top view of the semiconductor device 10B. FIG. 6B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 6A. FIG. 6C is a cross-sectional view of the portion indicated by the dashed line A3-A4 in FIG. 6A.
開口１６２の底部の面積を小さくすることで、半導体装置１０Ｂの占有面積を大きくすることなく開口１６２側面のテーパー角θを大きくすることができる。開口１６２側面のテーパー角θを大きくすることによって、半導体層１６３、絶縁層１６４、および導電層１６５の被覆性を高めることができる。 By reducing the area of the bottom of the opening 162, the taper angle θ of the side surface of the opening 162 can be increased without increasing the area occupied by the semiconductor device 10B. By increasing the taper angle θ of the side surface of the opening 162, the coverage of the semiconductor layer 163, the insulating layer 164, and the conductive layer 165 can be improved.
また、開口１６２の底部の面積を小さくすると、開口１６２内において導電層１６５が開口１６２の底部に向かって細くなる場合がある。このような導電層１６５の形状を「針状」または「錐状」と呼ぶ場合がある。 Furthermore, if the area of the bottom of the opening 162 is reduced, the conductive layer 165 within the opening 162 may become thinner toward the bottom of the opening 162. Such a shape of the conductive layer 165 is sometimes called "acicular" or "conical".
＜変形例２＞
図７Ａおよび図７Ｂに、半導体装置１０Ａの変形例である半導体装置１０Ｃを示す。図７Ａは、半導体装置１０Ｃの上面図である。図７Ｂは、図７ＡにＡ１−Ａ２の一点鎖線で示す部位の断面図である。図７Ｃは、図７ＡにＡ３−Ａ４の一点鎖線で示す部位の断面図である。 <Modification 2>
7A and 7B show a semiconductor device 10C that is a modification of the semiconductor device 10A. FIG. 7A is a top view of the semiconductor device 10C. FIG. 7B is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 7A. FIG. 7C is a cross-sectional view of the portion indicated by the dashed line A3-A4 in FIG. 7A.
半導体装置１０Ｃは、開口１６２の側面にテーパー角を設けていない。半導体層１６３、絶縁層１６４、導電層１６５の被覆性に問題がなければ、開口１６２の側面を垂直または略垂直にしてもよい。開口１６２の側面を垂直または略垂直にすることで、トランジスタ１００の占有面積を低減できる。よって、トランジスタ１００を含む半導体装置の占有面積を低減できる。 In the semiconductor device 10C, the side surface of the opening 162 is not provided with a taper angle. If there is no problem in covering the semiconductor layer 163, the insulating layer 164, and the conductive layer 165, the side surfaces of the opening 162 may be vertical or substantially vertical. By making the side surfaces of the opening 162 vertical or substantially vertical, the area occupied by the transistor 100 can be reduced. Therefore, the area occupied by the semiconductor device including the transistor 100 can be reduced.
＜変形例３＞
図８Ａおよび図８Ｂに、半導体装置１０Ｃの変形例である半導体装置１０Ｄを示す。図８Ａは、半導体装置１０Ｄの上面図である。図８Ｂは、図８ＡにＡ１−Ａ２の一点鎖線で示す部位の断面図である。図８Ｃは、図８ＡにＡ３−Ａ４の一点鎖線で示す部位の断面図である。 <Modification 3>
8A and 8B show a semiconductor device 10D that is a modification of the semiconductor device 10C. FIG. 8A is a top view of the semiconductor device 10D. FIG. 8B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 8A. FIG. 8C is a cross-sectional view of the portion indicated by the dashed line A3-A4 in FIG. 8A.
図８に示す半導体装置１０Ｄは、半導体装置１０Ａから導電層１５５を除いた構成を有する。導電層１５５を設けないことにより、半導体装置１０Ａよりも半導体装置１０Ｄの作製工程が短縮され生産性を高めることができる。なお、半導体装置１０Ｄでは、半導体層１６３の一部が容量素子１１０の一方の電極として機能する。具体的には、開口１６２の底部において、絶縁層１５４および導電層１５１と重なる半導体層１６３の領域が容量素子１１０の一方の電極として機能する。 A semiconductor device 10D shown in FIG. 8 has a configuration in which the conductive layer 155 is removed from the semiconductor device 10A. By not providing the conductive layer 155, the manufacturing process of the semiconductor device 10D is shorter than that of the semiconductor device 10A, and productivity can be improved. Note that in the semiconductor device 10D, a portion of the semiconductor layer 163 functions as one electrode of the capacitive element 110. Specifically, at the bottom of the opening 162, a region of the semiconductor layer 163 that overlaps with the insulating layer 154 and the conductive layer 151 functions as one electrode of the capacitive element 110.
＜変形例４＞
図９Ａは、２つの半導体装置１０Ａ（半導体装置１０Ａａおよび半導体装置１０Ａｂ）が１つの配線ＢＬ（導電層１６８および導電層１５２）と電気的に接続する構成例を示す断面図である。図９Ｂは、図９ＡにＡ１−Ａ２の一点鎖線で示す部位をＹ方向から見た断面図である。図９Ｃは、図９Ｂに示す断面図の等価回路図である。 <Modification 4>
FIG. 9A is a cross-sectional view showing a configuration example in which two semiconductor devices 10A (semiconductor device 10Aa and semiconductor device 10Ab) are electrically connected to one wiring BL (conductive layer 168 and conductive layer 152). FIG. 9B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 9A, viewed from the Y direction. FIG. 9C is an equivalent circuit diagram of the cross-sectional view shown in FIG. 9B.
半導体装置１０Ａａは、配線ＷＬａ、配線ＰＬａ、および配線ＢＬと電気的に接続される。半導体装置１０Ａｂは、配線ＷＬｂ、配線ＰＬｂ、および配線ＢＬと電気的に接続される。２つの半導体装置１０Ａが１つの配線ＢＬと電気的に接続する構成にすることで、半導体装置１０Ａを含む半導体装置の占有面積を低減できる。 Semiconductor device 10Aa is electrically connected to wiring WLa, wiring PLa, and wiring BL. Semiconductor device 10Ab is electrically connected to wiring WLb, wiring PLb, and wiring BL. By configuring the two semiconductor devices 10A to be electrically connected to one wiring BL, the area occupied by the semiconductor devices including the semiconductor device 10A can be reduced.
半導体装置１０Ａａが有する導電層１６５は、配線ＷＬａの一部として機能する。半導体装置１０Ａａが有する導電層１５１は、配線ＰＬａとして機能する。半導体装置１０Ａｂが有する導電層１６５は、配線ＷＬｂの一部として機能する。半導体装置１０Ａｂが有する導電層１５１は、配線ＰＬｂとして機能する。 The conductive layer 165 included in the semiconductor device 10Aa functions as part of the wiring WLa. The conductive layer 151 included in the semiconductor device 10Aa functions as a wiring PLa. The conductive layer 165 included in the semiconductor device 10Ab functions as part of the wiring WLb. The conductive layer 151 included in the semiconductor device 10Ab functions as the wiring PLb.
なお、配線ＰＬａおよび配線ＰＬｂに同じ電位を供給する場合は、両者を電気的に接続してもよい。 Note that when the same potential is supplied to the wiring PLa and the wiring PLb, they may be electrically connected.
また、Ｙ方向に延在する導電層１６５は、Ｙ方向に配置される複数の半導体装置１０Ａの導電層１６５として用いることができる（図９Ａ参照）。換言すると、半導体装置１０Ａａが有する導電層１６５は、Ｙ方向に配置される他の半導体装置１０Ａａの導電層１６５と電気的に接続してもよい。 Further, the conductive layer 165 extending in the Y direction can be used as the conductive layer 165 of a plurality of semiconductor devices 10A arranged in the Y direction (see FIG. 9A). In other words, the conductive layer 165 of the semiconductor device 10Aa may be electrically connected to the conductive layer 165 of another semiconductor device 10Aa arranged in the Y direction.
また、Ｙ方向に延在する導電層１５１は、Ｙ方向に配置される複数の半導体装置１０Ａの導電層１５１として用いることができる。換言すると、半導体装置１０Ａａが有する導電層１５１は、Ｙ方向に配置される他の半導体装置１０Ａａの導電層１５１と電気的に接続してもよい。 Further, the conductive layer 151 extending in the Y direction can be used as the conductive layer 151 of a plurality of semiconductor devices 10A arranged in the Y direction. In other words, the conductive layer 151 of the semiconductor device 10Aa may be electrically connected to the conductive layer 151 of another semiconductor device 10Aa arranged in the Y direction.
＜変形例５＞
複数の半導体装置１０Ａを、重ねて設けることで、半導体装置１０Ａの占有面積を低減できる。例えば、半導体装置１０Ａを２つ重ねて設けることで、半導体装置１０Ａの１つ当たりの占有面積が半分になる。 <Modification 5>
By stacking the plurality of semiconductor devices 10A, the area occupied by the semiconductor devices 10A can be reduced. For example, by stacking two semiconductor devices 10A, the area occupied by each semiconductor device 10A is halved.
図１０は、４つの半導体装置１０Ａ（半導体装置１０Ａ［１］、半導体装置１０Ａ［２］、半導体装置１０Ａ［３］、および半導体装置１０Ａ［４］）をＺ方向に積層した構成例を示す断面図である。図１１は、図１０に示す積層構成例の等価回路図である。図１０および図１１では、１層目に形成された半導体装置１０Ａを半導体装置１０Ａ［１］と示し、２層目に形成された半導体装置１０Ａを半導体装置１０Ａ［２］と示し、３層目に形成された半導体装置１０Ａを半導体装置１０Ａ［３］と示し、４層目に形成された半導体装置１０Ａを半導体装置１０Ａ［４］と示している。なお、本実施の形態などでは、１層目を「第１の層」、２層目を「第２の層」、３層目を「第３の層」、４層目を「第４の層」と呼ぶ場合がある。 FIG. 10 is a cross section showing a configuration example in which four semiconductor devices 10A (semiconductor device 10A[1], semiconductor device 10A[2], semiconductor device 10A[3], and semiconductor device 10A[4]) are stacked in the Z direction. It is a diagram. FIG. 11 is an equivalent circuit diagram of the stacked structure example shown in FIG. 10. In FIGS. 10 and 11, the semiconductor device 10A formed in the first layer is indicated as a semiconductor device 10A[1], the semiconductor device 10A formed in the second layer is indicated as a semiconductor device 10A[2], and the semiconductor device 10A formed in the third layer is indicated as a semiconductor device 10A[2]. The semiconductor device 10A formed in the fourth layer is indicated as a semiconductor device 10A[3], and the semiconductor device 10A formed in the fourth layer is indicated as a semiconductor device 10A[4]. In this embodiment, the first layer is referred to as a "first layer," the second layer is referred to as a "second layer," the third layer is referred to as a "third layer," and the fourth layer is referred to as a "fourth layer." Sometimes called "layers".
半導体装置１０Ａ［１］は、配線ＷＬ［１］、配線ＰＬ［１］、および配線ＢＬと電気的に接続される（図１１参照）。半導体装置１０Ａ［２］は、配線ＷＬ［２］、配線ＰＬ［２］、および配線ＢＬと電気的に接続される。半導体装置１０Ａ［３］は、配線ＷＬ［３］、配線ＰＬ［３］、および配線ＢＬと電気的に接続される。半導体装置１０Ａ［４］は、配線ＷＬ［４］、配線ＰＬ［４］、および配線ＢＬと電気的に接続される。 The semiconductor device 10A[1] is electrically connected to the wiring WL[1], the wiring PL[1], and the wiring BL (see FIG. 11). The semiconductor device 10A[2] is electrically connected to the wiring WL[2], the wiring PL[2], and the wiring BL. The semiconductor device 10A[3] is electrically connected to the wiring WL[3], the wiring PL[3], and the wiring BL. The semiconductor device 10A[4] is electrically connected to the wiring WL[4], the wiring PL[4], and the wiring BL.
半導体装置１０Ａ［１］が有する導電層１６５は、配線ＷＬ［１］と電気的に接続される。また、半導体装置１０Ａ［１］が有する導電層１６５は、配線ＷＬ［１］または配線ＷＬ［１］の一部として機能する場合がある。半導体装置１０Ａ［１］が有する導電層１５１は、配線ＰＬ［１］と電気的に接続される。また、半導体装置１０Ａ［１］が有する導電層１５１は、配線ＰＬ［１］または配線ＰＬ［１］の一部として機能する場合がある。 The conductive layer 165 included in the semiconductor device 10A[1] is electrically connected to the wiring WL[1]. Further, the conductive layer 165 included in the semiconductor device 10A[1] may function as the wiring WL[1] or a part of the wiring WL[1]. The conductive layer 151 included in the semiconductor device 10A[1] is electrically connected to the wiring PL[1]. Furthermore, the conductive layer 151 included in the semiconductor device 10A[1] may function as the wiring PL[1] or a part of the wiring PL[1].
半導体装置１０Ａ［２］が有する導電層１６５は、配線ＷＬ［２］と電気的に接続される。また、半導体装置１０Ａ［２］が有する導電層１６５は、配線ＷＬ［２］または配線ＷＬ［２］の一部として機能する場合がある。半導体装置１０Ａ［２］が有する導電層１５１は、配線ＰＬ［２］と電気的に接続される。また、半導体装置１０Ａ［２］が有する導電層１５１は、配線ＰＬ［２］または配線ＰＬ［２］の一部として機能する場合がある。 The conductive layer 165 included in the semiconductor device 10A[2] is electrically connected to the wiring WL[2]. Further, the conductive layer 165 included in the semiconductor device 10A[2] may function as the wiring WL[2] or a part of the wiring WL[2]. The conductive layer 151 included in the semiconductor device 10A[2] is electrically connected to the wiring PL[2]. Furthermore, the conductive layer 151 included in the semiconductor device 10A[2] may function as the wiring PL[2] or a part of the wiring PL[2].
半導体装置１０Ａ［３］が有する導電層１６５は、配線ＷＬ［３］と電気的に接続される。また、半導体装置１０Ａ［３］が有する導電層１６５は、配線ＷＬ［３］または配線ＷＬ［３］の一部として機能する場合がある。半導体装置１０Ａ［３］が有する導電層１５１は、配線ＰＬ［３］と電気的に接続される。また、半導体装置１０Ａ［３］が有する導電層１５１は、配線ＰＬ［３］または配線ＰＬ［３］の一部として機能する場合がある。 The conductive layer 165 included in the semiconductor device 10A[3] is electrically connected to the wiring WL[3]. Further, the conductive layer 165 included in the semiconductor device 10A[3] may function as the wiring WL[3] or a part of the wiring WL[3]. The conductive layer 151 included in the semiconductor device 10A[3] is electrically connected to the wiring PL[3]. Further, the conductive layer 151 included in the semiconductor device 10A[3] may function as the wiring PL[3] or a part of the wiring PL[3].
半導体装置１０Ａ［４］が有する導電層１６５は、配線ＷＬ［４］と電気的に接続される。また、半導体装置１０Ａ［４］が有する導電層１６５は、配線ＷＬ［４］または配線ＷＬ［４］の一部として機能する場合がある。半導体装置１０Ａ［４］が有する導電層１５１は、配線ＰＬ［４］と電気的に接続される。また、半導体装置１０Ａ［４］が有する導電層１５１は、配線ＰＬ［４］または配線ＰＬ［４］の一部として機能する場合がある。 The conductive layer 165 included in the semiconductor device 10A[4] is electrically connected to the wiring WL[4]. Further, the conductive layer 165 included in the semiconductor device 10A[4] may function as the wiring WL[4] or a part of the wiring WL[4]. The conductive layer 151 included in the semiconductor device 10A[4] is electrically connected to the wiring PL[4]. Further, the conductive layer 151 included in the semiconductor device 10A[4] may function as the wiring PL[4] or a part of the wiring PL[4].
図１０では、半導体装置１０Ａ［１］の上に半導体装置１０Ａ［２］を設け、半導体装置１０Ａ［２］の上に半導体装置１０Ａ［３］を設け、半導体装置１０Ａ［３］の上に半導体装置１０Ａ［４］を設けている。図１０に示す半導体装置１０Ａ［１］乃至半導体装置１０Ａ［４］のそれぞれは、導電層１５２および導電層１６８を有する。図１０に示す半導体装置１０Ａ［１］乃至半導体装置１０Ａ［４］のそれぞれが有する導電層１６８は、半導体装置１０Ａ［１］乃至半導体装置１０Ａ［４］のそれぞれが有する導電層１５２を介して電気的に接続される。 In FIG. 10, a semiconductor device 10A[2] is provided on the semiconductor device 10A[1], a semiconductor device 10A[3] is provided on the semiconductor device 10A[2], and a semiconductor device 10A[3] is provided on the semiconductor device 10A[3]. A device 10A[4] is provided. Each of semiconductor devices 10A[1] to 10A[4] shown in FIG. 10 includes a conductive layer 152 and a conductive layer 168. The conductive layer 168 of each of the semiconductor devices 10A[1] to 10A[4] shown in FIG. connected.
具体的には、図１０において、半導体装置１０Ａ［１］が有する導電層１５２は、半導体装置１０Ａ［１］が有する導電層１６８を介して半導体装置１０Ａ［２］が有する導電層１５２と電気的に接続される。また、半導体装置１０Ａ［２］が有する導電層１５２は、半導体装置１０Ａ［２］が有する導電層１６８を介して半導体装置１０Ａ［３］が有する導電層１５２と電気的に接続される。また、半導体装置１０Ａ［３］が有する導電層１５２は、半導体装置１０Ａ［３］が有する導電層１６８を介して半導体装置１０Ａ［４］が有する導電層１５２と電気的に接続される。図１０に示すように、複数の導電層１６８および複数の導電層１５２が電気的に接続することによって、Ｚ方向に延在する１つの電極として機能する。換言すると、複数の導電層１６８および複数の導電層１５２が１つの配線ＢＬとして機能する。 Specifically, in FIG. 10, the conductive layer 152 of the semiconductor device 10A[1] is electrically connected to the conductive layer 152 of the semiconductor device 10A[2] via the conductive layer 168 of the semiconductor device 10A[1]. connected to. Further, the conductive layer 152 of the semiconductor device 10A[2] is electrically connected to the conductive layer 152 of the semiconductor device 10A[3] via the conductive layer 168 of the semiconductor device 10A[2]. Furthermore, the conductive layer 152 of the semiconductor device 10A[3] is electrically connected to the conductive layer 152 of the semiconductor device 10A[4] via the conductive layer 168 of the semiconductor device 10A[3]. As shown in FIG. 10, the plurality of conductive layers 168 and the plurality of conductive layers 152 are electrically connected to function as one electrode extending in the Z direction. In other words, the plurality of conductive layers 168 and the plurality of conductive layers 152 function as one wiring BL.
図１０および図１１に示すように、半導体装置１０Ａ［１］乃至半導体装置１０Ａ［４］それぞれが有するトランジスタ１００は、配線ＢＬと電気的に接続される。具体的には、半導体装置１０Ａ［１］が有するトランジスタ１００のソースまたはドレインの一方、半導体装置１０Ａ［２］が有するトランジスタ１００のソースまたはドレインの一方、半導体装置１０Ａ［３］が有するトランジスタ１００のソースまたはドレインの一方、および半導体装置１０Ａ［４］が有するトランジスタ１００のソースまたはドレインの一方は、配線ＢＬと電気的に接続される。 As shown in FIGS. 10 and 11, the transistors 100 included in each of the semiconductor devices 10A[1] to 10A[4] are electrically connected to the wiring BL. Specifically, one of the source or drain of the transistor 100 included in the semiconductor device 10A[1], one of the source or drain of the transistor 100 included in the semiconductor device 10A[2], and one of the source or drain of the transistor 100 included in the semiconductor device 10A[3]. One of the source or drain and one of the source or drain of the transistor 100 included in the semiconductor device 10A[4] are electrically connected to the wiring BL.
複数の半導体装置１０Ａが１つの配線ＢＬと電気的に接続すること、すなわち、複数の半導体装置１０Ａで１つの配線ＢＬを共用することによって、半導体装置１０Ａを含む半導体装置の占有面積を低減できる。また、複数の半導体装置１０Ａを、Ｚ方向に重ねて設けることで、半導体装置１０Ａの占有面積を低減できる。よって、半導体装置１０Ａを含む半導体装置の占有面積をさらに低減できる。また、複数の半導体装置１０Ａを、Ｚ方向に重ねて設けることで、半導体装置１０Ａを含む記憶装置の単位面積当たりの記憶容量を増やすことができる。 By electrically connecting a plurality of semiconductor devices 10A to one wiring BL, that is, by allowing a plurality of semiconductor devices 10A to share one wiring BL, the area occupied by the semiconductor devices including the semiconductor device 10A can be reduced. Further, by providing a plurality of semiconductor devices 10A one on top of the other in the Z direction, the area occupied by the semiconductor devices 10A can be reduced. Therefore, the area occupied by semiconductor devices including the semiconductor device 10A can be further reduced. Further, by providing a plurality of semiconductor devices 10A in an overlapping manner in the Z direction, it is possible to increase the storage capacity per unit area of a storage device including the semiconductor devices 10A.
＜変形例６＞
変形例４および変形例５を組み合わせることで、半導体装置１０Ａの１つ当たりの占有面積をさらに低減できる。 <Modification 6>
By combining Modifications 4 and 5, the area occupied by each semiconductor device 10A can be further reduced.
図１２は、複数の半導体装置１０Ａの積層構成例を示す断面図である。図１３は、図１２に示す構成例の等価回路図である。なお、図１２および図１３では、同一平面上に形成された２つの半導体装置１０Ａ（半導体装置１０Ａａおよび半導体装置１０Ａｂ）を一組として、一組の半導体装置１０Ａを４層（または「段」ともいう。）重ねて設ける例を示している。 FIG. 12 is a cross-sectional view showing an example of a stacked structure of a plurality of semiconductor devices 10A. FIG. 13 is an equivalent circuit diagram of the configuration example shown in FIG. 12. Note that in FIGS. 12 and 13, two semiconductor devices 10A (semiconductor device 10Aa and semiconductor device 10Ab) formed on the same plane are considered as one set, and one set of semiconductor devices 10A is referred to as four layers (or "stages"). ) This shows an example of overlapping.
図１２および図１３では、第１の層に含まれる半導体装置１０Ａａを半導体装置１０Ａａ［１］と示し、半導体装置１０Ａｂを半導体装置１０Ａｂ［１］と示している。また、第２の層に含まれる半導体装置１０Ａａを半導体装置１０Ａａ［２］と示し、半導体装置１０Ａｂを半導体装置１０Ａｂ［２］と示している。また、第３の層に含まれる半導体装置１０Ａａを半導体装置１０Ａａ［３］と示し、半導体装置１０Ａｂを半導体装置１０Ａｂ［３］と示している。また、第４の層に含まれる半導体装置１０Ａａを半導体装置１０Ａａ［４］と示し、半導体装置１０Ａｂを半導体装置１０Ａｂ［４］と示している。 In FIGS. 12 and 13, the semiconductor device 10Aa included in the first layer is shown as a semiconductor device 10Aa[1], and the semiconductor device 10Ab is shown as a semiconductor device 10Ab[1]. Further, the semiconductor device 10Aa included in the second layer is indicated as a semiconductor device 10Aa[2], and the semiconductor device 10Ab is indicated as a semiconductor device 10Ab[2]. Furthermore, the semiconductor device 10Aa included in the third layer is shown as a semiconductor device 10Aa[3], and the semiconductor device 10Ab is shown as a semiconductor device 10Ab[3]. Furthermore, the semiconductor device 10Aa included in the fourth layer is indicated as a semiconductor device 10Aa[4], and the semiconductor device 10Ab is indicated as a semiconductor device 10Ab[4].
また、半導体装置１０Ａａ［１］は、配線ＷＬａ［１］、配線ＰＬａ［１］、および配線ＢＬと電気的に接続される（図１３参照）。半導体装置１０Ａｂ［１］は、配線ＷＬｂ［１］、配線ＰＬｂ［１］、および配線ＢＬと電気的に接続される。半導体装置１０Ａａ［２］は、配線ＷＬａ［２］、配線ＰＬａ［２］、および配線ＢＬと電気的に接続される。半導体装置１０Ａｂ［２］は、配線ＷＬｂ［２］、配線ＰＬｂ［２］、および配線ＢＬと電気的に接続される。半導体装置１０Ａａ［３］は、配線ＷＬａ［３］、配線ＰＬａ［３］、および配線ＢＬと電気的に接続される。半導体装置１０Ａｂ［３］は、配線ＷＬｂ［３］、配線ＰＬｂ［３］、および配線ＢＬと電気的に接続される。半導体装置１０Ａａ［４］は、配線ＷＬａ［４］、配線ＰＬａ［４］、および配線ＢＬと電気的に接続される。半導体装置１０Ａｂ［４］は、配線ＷＬｂ［４］、配線ＰＬｂ［４］、および配線ＢＬと電気的に接続される。 Further, the semiconductor device 10Aa[1] is electrically connected to the wiring WLa[1], the wiring PLa[1], and the wiring BL (see FIG. 13). Semiconductor device 10Ab[1] is electrically connected to wiring WLb[1], wiring PLb[1], and wiring BL. Semiconductor device 10Aa[2] is electrically connected to wiring WLa[2], wiring PLa[2], and wiring BL. Semiconductor device 10Ab[2] is electrically connected to wiring WLb[2], wiring PLb[2], and wiring BL. Semiconductor device 10Aa[3] is electrically connected to wiring WLa[3], wiring PLa[3], and wiring BL. Semiconductor device 10Ab[3] is electrically connected to wiring WLb[3], wiring PLb[3], and wiring BL. Semiconductor device 10Aa[4] is electrically connected to wiring WLa[4], wiring PLa[4], and wiring BL. Semiconductor device 10Ab[4] is electrically connected to wiring WLb[4], wiring PLb[4], and wiring BL.
図１２および図１３に示す構成とすることで、半導体装置１０Ａを含む半導体装置の占有面積をより低減できる。また、半導体装置１０Ａを含む記憶装置の単位面積当たりの記憶容量を増やすことができる。 With the configurations shown in FIGS. 12 and 13, the area occupied by the semiconductor devices including the semiconductor device 10A can be further reduced. Furthermore, the storage capacity per unit area of the storage device including the semiconductor device 10A can be increased.
＜半導体装置１０の動作例＞
続いて、半導体装置１０（半導体装置１０Ａ、半導体装置１０Ｃ、および半導体装置１０Ｄ）の動作例について説明する。図１４Ａに半導体装置１０の等価回路図を示す。図１４Ａに示す半導体装置１０は、１つのトランジスタＭと１つの容量素子Ｃｆｅを有するＤＲＡＭ型（１Ｔｒ１Ｃ型）の記憶素子（メモリセル）として機能する。 <Example of operation of semiconductor device 10>
Next, an example of the operation of the semiconductor device 10 (semiconductor device 10A, semiconductor device 10C, and semiconductor device 10D) will be described. FIG. 14A shows an equivalent circuit diagram of the semiconductor device 10. The semiconductor device 10 shown in FIG. 14A functions as a DRAM type (1Tr1C type) storage element (memory cell) having one transistor M and one capacitive element Cfe.
また、容量素子Ｃｆｅは、２つの電極の間に、誘電体層として強誘電性を有しうる材料を有する強誘電体キャパシタである。よって、半導体装置１０は、ＦｅＲＡＭとして機能する。図１４Ａに示すトランジスタＭはトランジスタ１００に相当し、容量素子Ｃｆｅは容量素子１１０に相当する。 Further, the capacitive element Cfe is a ferroelectric capacitor having a material capable of having ferroelectricity as a dielectric layer between two electrodes. Therefore, the semiconductor device 10 functions as a FeRAM. The transistor M shown in FIG. 14A corresponds to the transistor 100, and the capacitive element Cfe corresponds to the capacitive element 110.
トランジスタＭのチャネルが形成される半導体層として、様々な半導体材料を用いることができる。例えば、トランジスタＭのチャネルが形成される半導体層として、単結晶半導体、多結晶半導体、微結晶半導体、または非晶質半導体などを、単体でまたは組み合わせて用いることができる。また、半導体材料としては、例えば、シリコンまたはゲルマニウムなどを用いることができる。また、シリコンゲルマニウム、炭化シリコン、ヒ化ガリウム、酸化物半導体、窒化物半導体などの化合物半導体を用いてもよい。 Various semiconductor materials can be used as the semiconductor layer in which the channel of the transistor M is formed. For example, as the semiconductor layer in which the channel of the transistor M is formed, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination. Further, as the semiconductor material, for example, silicon or germanium can be used. Further, compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors may be used.
特に、トランジスタＭとして、ＯＳトランジスタを用いることが好ましい。ＯＳトランジスタは、ソースとドレイン間の絶縁耐圧が高いという特性を有する。よって、トランジスタＭをＯＳトランジスタとすることにより、トランジスタＭを微細化しても、トランジスタＭに高電圧を印加できる。トランジスタＭを微細化することにより、半導体装置１０の占有面積を小さくすることができる。例えば、図１４Ａに示す半導体装置１０の１個あたりの占有面積は、ＳＲＡＭ（Ｓｔａｔｉｃ　Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ）の１セルあたりの占有面積の１／３乃至１／６とすることができる。よって、半導体装置１０を高密度に配置することができる。これにより、記憶容量が大きな記憶装置を実現できる。 In particular, it is preferable to use an OS transistor as the transistor M. An OS transistor has a characteristic of high dielectric strength between a source and a drain. Therefore, by using the transistor M as an OS transistor, a high voltage can be applied to the transistor M even if the transistor M is miniaturized. By miniaturizing the transistor M, the area occupied by the semiconductor device 10 can be reduced. For example, the area occupied by each semiconductor device 10 shown in FIG. 14A can be set to 1/3 to 1/6 of the area occupied by one cell of an SRAM (Static Random Access Memory). Therefore, the semiconductor devices 10 can be arranged with high density. This makes it possible to realize a storage device with a large storage capacity.
なお、メモリセルを構成するトランジスタにＯＳトランジスタを用いた場合、当該メモリセルを「ＯＳメモリ」と呼ぶことができる。特に、ＤＲＡＭ型のＯＳメモリをＤＯＳＲＡＭ（登録商標）と呼ぶ場合がある。また、メモリセルを構成するトランジスタにＯＳトランジスタを用いたＦｅＲＡＭをＦｅＤＯＳＲＡＭと呼ぶ場合がある。 Note that when an OS transistor is used as a transistor included in a memory cell, the memory cell can be referred to as an "OS memory." In particular, a DRAM type OS memory is sometimes called DOSRAM (registered trademark). Further, an FeRAM using an OS transistor as a transistor constituting a memory cell is sometimes called a FeDOSRAM.
配線ＷＬは、ワード線としての機能を有し、配線ＷＬの電位を制御することにより、トランジスタＭのオン状態とオフ状態を制御できる。例えば、トランジスタＭがｎチャネル型のトランジスタである場合、配線ＷＬの電位を高電位とすることにより、トランジスタＭをオン状態とし、配線ＷＬの電位を低電位とすることにより、トランジスタＭをオフ状態とすることができる。 The wiring WL has a function as a word line, and by controlling the potential of the wiring WL, the on state and off state of the transistor M can be controlled. For example, if the transistor M is an n-channel transistor, the transistor M is turned on by setting the potential of the wiring WL to a high potential, and the transistor M is turned off by setting the potential of the wiring WL to a low potential. It can be done.
配線ＢＬは、ビット線としての機能を有し、トランジスタＭがオン状態である場合において、配線ＢＬの電位が容量素子Ｃｆｅの一方の電極に供給される。 The wiring BL has a function as a bit line, and when the transistor M is in an on state, the potential of the wiring BL is supplied to one electrode of the capacitive element Cfe.
配線ＰＬは、プレート線としての機能を有する。容量素子Ｃｆｅの他方の電極は、配線ＰＬを介して電位が供給される。 The wiring PL has a function as a plate line. The other electrode of the capacitive element Cfe is supplied with a potential via the wiring PL.
＜強誘電体層のヒステリシス特性＞
容量素子Ｃｆｅが有する強誘電体層は、ヒステリシス特性を有する。図１４Ｂは、当該ヒステリシス特性の一例を示すグラフである。図１４Ｂにおいて、横軸は強誘電体層に印加する電圧を示す。当該電圧は、例えば容量素子Ｃｆｅの一方の電極の電位と、容量素子Ｃｆｅの他方の電極の電位と、の差とすることができる。 <Hysteresis characteristics of ferroelectric layer>
The ferroelectric layer included in the capacitive element Cfe has hysteresis characteristics. FIG. 14B is a graph showing an example of the hysteresis characteristic. In FIG. 14B, the horizontal axis indicates the voltage applied to the ferroelectric layer. The voltage can be, for example, the difference between the potential of one electrode of the capacitive element Cfe and the potential of the other electrode of the capacitive element Cfe.
また、図１４Ｂにおいて、縦軸は強誘電体層の分極を示し、正の値の場合は正電荷が容量素子Ｃｆｅの一方の電極側に偏り、負電荷が容量素子Ｃｆｅの他方の電極側に偏っていることを示す。一方、分極が負の値の場合は、正電荷が容量素子Ｃｆｅの他方の電極側に偏り、負電荷が容量素子Ｃｆｅの一方の電極側に偏っていることを示す。 In addition, in FIG. 14B, the vertical axis indicates the polarization of the ferroelectric layer, and in the case of a positive value, positive charges are biased toward one electrode side of the capacitive element Cfe, and negative charges are biased toward the other electrode side of the capacitive element Cfe. Show that you are biased. On the other hand, when the polarization has a negative value, it indicates that positive charges are biased toward the other electrode of the capacitive element Cfe, and negative charges are biased toward one electrode of the capacitive element Cfe.
なお、図１４Ｂのグラフの横軸に示す電圧を、容量素子Ｃｆｅの他方の電極の電位と、容量素子Ｃｆｅの一方の電極の電位と、の差としてもよい。また、図１４Ｂのグラフの縦軸に示す分極を、正電荷が容量素子Ｃｆｅの他方の電極側に偏り、負電荷が容量素子Ｃｆｅの一方の電極側に偏っている場合に正の値とし、正電荷が容量素子Ｃｆｅの一方の電極側に偏り、負電荷が容量素子Ｃｆｅの他方の電極側に偏っている場合に負の値としてもよい。 Note that the voltage shown on the horizontal axis of the graph in FIG. 14B may be the difference between the potential of the other electrode of the capacitive element Cfe and the potential of one electrode of the capacitive element Cfe. Further, the polarization shown on the vertical axis of the graph in FIG. 14B is set to a positive value when positive charges are biased toward the other electrode side of the capacitive element Cfe and negative charges are biased toward one electrode side of the capacitive element Cfe, A negative value may be used when positive charges are biased towards one electrode of the capacitive element Cfe and negative charges are biased towards the other electrode of the capacitive element Cfe.
図１４Ｂに示すように、強誘電体層のヒステリシス特性は、曲線５１と、曲線５２と、により表すことができる。曲線５１と曲線５２の交点における電圧を、ＶＳＰ、および−ＶＳＰとする。ＶＳＰと−ＶＳＰは、極性が異なるということができる。 As shown in FIG. 14B, the hysteresis characteristics of the ferroelectric layer can be represented by a curve 51 and a curve 52. The voltages at the intersections of the curves 51 and 52 are defined as VSP and -VSP. It can be said that VSP and -VSP have different polarities.
強誘電体層に−ＶＳＰ以下の電圧を印加した後に、強誘電体層に印加する電圧を高くしていくと、強誘電体層の分極は、曲線５１に従って増加する。一方、強誘電体層にＶＳＰ以上の電圧を印加した後に、強誘電体層に印加する電圧を低くしていくと、強誘電体層の分極は、曲線５２に従って減少する。よって、ＶＳＰ、および−ＶＳＰは、飽和分極電圧ということができる。なお、例えばＶＳＰを第１の飽和分極電圧と呼び、−ＶＳＰを第２の飽和分極電圧と呼ぶ場合がある。また、図１４Ｂでは、第１の飽和分極電圧の絶対値と第２の飽和分極電圧の絶対値が等しい場合を示しているが、両者の絶対値は異なっていてもよい。 After applying a voltage equal to or lower than -VSP to the ferroelectric layer, when the voltage applied to the ferroelectric layer is increased, the polarization of the ferroelectric layer increases according to a curve 51. On the other hand, when a voltage higher than VSP is applied to the ferroelectric layer and then the voltage applied to the ferroelectric layer is lowered, the polarization of the ferroelectric layer decreases according to curve 52. Therefore, VSP and -VSP can be said to be saturation polarization voltages. Note that, for example, VSP may be referred to as a first saturation polarization voltage, and -VSP may be referred to as a second saturation polarization voltage. Further, although FIG. 14B shows a case where the absolute value of the first saturation polarization voltage and the absolute value of the second saturation polarization voltage are equal, the absolute values thereof may be different.
ここで、強誘電体層の分極が曲線５１に従って変化する際の、強誘電体層の分極が０である場合における、強誘電体層に印加される電圧をＶｃとする。また、強誘電体層の分極が曲線５２に従って変化する際の、強誘電体層の分極が０である場合における、強誘電体層に印加される電圧を−Ｖｃとする。Ｖｃ、および−Ｖｃは、抗電圧ということができる。Ｖｃの値、および−Ｖｃの値は、−ＶＳＰとＶＳＰの間の値であるということができる。なお、例えばＶｃを第１の抗電圧と呼び、−Ｖｃを第２の抗電圧と呼ぶ場合がある。また、図１４Ｂでは、第１の抗電圧の絶対値と、第２の抗電圧の絶対値と、が等しいとしているが、両者の絶対値は異なってもよい。 Here, the voltage applied to the ferroelectric layer when the polarization of the ferroelectric layer changes according to the curve 51 and the polarization of the ferroelectric layer is 0 is defined as Vc. Further, when the polarization of the ferroelectric layer changes according to the curve 52, the voltage applied to the ferroelectric layer when the polarization of the ferroelectric layer is 0 is defined as -Vc. Vc and -Vc can be said to be coercive voltages. The value of Vc and the value of -Vc can be said to be values between -VSP and VSP. Note that, for example, Vc may be referred to as a first coercive voltage, and -Vc may be referred to as a second coercive voltage. Further, in FIG. 14B, it is assumed that the absolute value of the first coercive voltage and the absolute value of the second coercive voltage are equal, but the absolute values may be different.
また、強誘電体層に電圧が印加されていない時の、分極の最大値を「残留分極Ｐｒ」と呼び、最小値を「残留分極−Ｐｒ」と呼ぶ。また、残留分極Ｐｒと残留分極−Ｐｒの差を「残留分極２Ｐｒ」と呼ぶ。 Further, the maximum value of polarization when no voltage is applied to the ferroelectric layer is called "remanent polarization Pr", and the minimum value is called "remanent polarization -Pr". Further, the difference between the remanent polarization Pr and the remanent polarization -Pr is called "remanent polarization 2Pr".
前述のように、容量素子Ｃｆｅが有する強誘電体層に印加される電圧は、容量素子Ｃｆｅの一方の電極の電位と、容量素子Ｃｆｅの他方の電極の電位と、の差により表すことができる。また、前述のように、容量素子Ｃｆｅの他方の電極は、配線ＰＬと電気的に接続される。よって、配線ＰＬの電位を制御することにより、容量素子Ｃｆｅが有する強誘電体層に印加される電圧を制御することができる。 As described above, the voltage applied to the ferroelectric layer of the capacitive element Cfe can be expressed by the difference between the potential of one electrode of the capacitive element Cfe and the potential of the other electrode of the capacitive element Cfe. . Further, as described above, the other electrode of the capacitive element Cfe is electrically connected to the wiring PL. Therefore, by controlling the potential of the wiring PL, it is possible to control the voltage applied to the ferroelectric layer of the capacitive element Cfe.
メモリセルとして機能する半導体装置１０の駆動方法の一例を説明する。以下の説明において、容量素子Ｃｆｅの強誘電体層に印加される電圧とは、容量素子Ｃｆｅの一方の電極の電位と、容量素子Ｃｆｅの他方の電極（配線ＰＬ）の電位の電位差である。また、トランジスタＭは、ｎチャネル型トランジスタとする。 An example of a method for driving the semiconductor device 10 functioning as a memory cell will be described. In the following description, the voltage applied to the ferroelectric layer of the capacitive element Cfe is the potential difference between the potential of one electrode of the capacitive element Cfe and the potential of the other electrode (wiring PL) of the capacitive element Cfe. Furthermore, the transistor M is an n-channel transistor.
図１４Ｃは、半導体装置１０の駆動方法例を示すタイミングチャートである。図１４Ｃでは、半導体装置１０に２値のデジタルデータを書き込み、読み出す例を示している。具体的には、図１４Ｃでは、時刻Ｔ０１乃至時刻Ｔ０２において半導体装置１０にデータ“１”を書き込み、時刻Ｔ０３乃至時刻Ｔ０５において読み出しおよび再書き込みを行い、時刻Ｔ１１乃至時刻Ｔ１３において読み出し、および半導体装置１０へのデータ“０”の書き込みを行い、時刻Ｔ１４乃至時刻Ｔ１６において読み出しおよび再書き込みを行い、時刻Ｔ１７乃至時刻Ｔ１９において読み出し、および半導体装置１０へのデータ“１”の書き込みを行う例を示している。 FIG. 14C is a timing chart showing an example of a method for driving the semiconductor device 10. FIG. 14C shows an example of writing and reading binary digital data into the semiconductor device 10. Specifically, in FIG. 14C, data "1" is written in the semiconductor device 10 from time T01 to time T02, read and rewritten from time T03 to time T05, read from time T11 to time T13, and the semiconductor device 10 is written. An example is shown in which data "0" is written to the semiconductor device 10, read and rewritten from time T14 to time T16, and read and data "1" is written to the semiconductor device 10 from time T17 to time T19. ing.
配線ＢＬと電気的に接続されるセンスアンプには、基準電位としてＶｒｅｆが供給されるものとする。図１４Ｃ等に示す読み出し動作において、配線ＢＬの電位がＶｒｅｆより高い場合は、ビット線ドライバ回路によりデータ“１”が読み出されるものとする。一方、配線ＢＬの電位がＶｒｅｆより低い場合は、ビット線ドライバ回路によりデータ“０”が読み出されるものとする。 It is assumed that Vref is supplied as a reference potential to the sense amplifier electrically connected to the wiring BL. In the read operation shown in FIG. 14C and the like, if the potential of the wiring BL is higher than Vref, data "1" is read by the bit line driver circuit. On the other hand, when the potential of the wiring BL is lower than Vref, data "0" is read by the bit line driver circuit.
時刻Ｔ０１乃至時刻Ｔ０２において、配線ＷＬの電位を高電位とする。これにより、トランジスタＭがオン状態となる。また、配線ＢＬの電位をＶｗとする。トランジスタＭはオン状態であるため、容量素子Ｃｆｅの一方の電極の電位はＶｗとなる。さらに、配線ＰＬの電位をＧＮＤとする。以上より、容量素子Ｃｆｅの強誘電体層に印加される電圧は、“Ｖｗ−ＧＮＤ”となる。これにより、半導体装置１０にデータ“１”を書き込むことができる。よって、時刻Ｔ０１乃至時刻Ｔ０２は、書き込み動作を行う期間であるということができる。 From time T01 to time T02, the potential of the wiring WL is set to a high potential. As a result, transistor M is turned on. Further, the potential of the wiring BL is assumed to be Vw. Since the transistor M is in the on state, the potential of one electrode of the capacitive element Cfe becomes Vw. Further, the potential of the wiring PL is set to GND. From the above, the voltage applied to the ferroelectric layer of the capacitive element Cfe becomes "Vw-GND". Thereby, data "1" can be written into the semiconductor device 10. Therefore, it can be said that the period from time T01 to time T02 is a period during which a write operation is performed.
ここで、Ｖｗは、ＶＳＰ以上とすることが好ましく、例えばＶＳＰと等しくすることが好ましい。また、本明細書等において、ＧＮＤは接地電位であるが、半導体装置１０を本発明の一態様の趣旨を充足するように駆動させることができるのであれば、必ずしも接地電位としなくてもよい。例えば、第１の飽和分極電圧の絶対値と、第２の飽和分極電圧の絶対値と、が異なり、第１の抗電圧の絶対値と、第２の抗電圧の絶対値と、が異なる場合は、ＧＮＤは接地以外の電位とすることができる。 Here, Vw is preferably equal to or greater than VSP, for example, preferably equal to VSP. Further, although GND is a ground potential in this specification and the like, it does not necessarily have to be a ground potential as long as the semiconductor device 10 can be driven to satisfy the purpose of one embodiment of the present invention. For example, if the absolute value of the first saturation polarization voltage is different from the absolute value of the second saturation polarization voltage, and the absolute value of the first coercive voltage is different from the absolute value of the second coercive voltage. In this case, GND can be set to a potential other than ground.
時刻Ｔ０２乃至時刻Ｔ０３において、配線ＢＬの電位、および配線ＰＬの電位をＧＮＤとする。これにより、容量素子Ｃｆｅの強誘電体層に印加される電圧は、０Ｖとなる。時刻Ｔ０１乃至時刻Ｔ０２において容量素子Ｃｆｅの強誘電体層に印加される電圧“Ｖｗ−ＧＮＤ”はＶＳＰ以上とすることができることから、時刻Ｔ０２乃至時刻Ｔ０３において、容量素子Ｃｆｅの強誘電体層の分極量は図１４Ｂに示す曲線５２に従って変化する。以上より、時刻Ｔ０２乃至時刻Ｔ０３では、容量素子Ｃｆｅの強誘電体層において分極反転は発生しない。 From time T02 to time T03, the potential of the wiring BL and the potential of the wiring PL are set to GND. As a result, the voltage applied to the ferroelectric layer of the capacitive element Cfe becomes 0V. Since the voltage "Vw-GND" applied to the ferroelectric layer of the capacitive element Cfe from time T01 to time T02 can be higher than VSP, the voltage "Vw-GND" applied to the ferroelectric layer of the capacitive element Cfe from time T02 to time T03 is The amount of polarization changes according to curve 52 shown in FIG. 14B. As described above, polarization reversal does not occur in the ferroelectric layer of the capacitive element Cfe between time T02 and time T03.
配線ＢＬの電位、および配線ＰＬの電位をＧＮＤとした後、配線ＷＬの電位を低電位とする。これにより、トランジスタＭがオフ状態となる。以上により、書き込み動作が完了し、半導体装置１０へデータ“１”が保持される。なお、配線ＢＬ、および配線ＰＬの電位は、容量素子Ｃｆｅの強誘電体層において分極反転が発生しない、つまり容量素子Ｃｆｅの強誘電体層に印加される電圧が第２の抗電圧である−Ｖｃ以上となるのであれば任意の電位とすることができる。 After the potential of the wiring BL and the potential of the wiring PL are set to GND, the potential of the wiring WL is set to a low potential. This turns transistor M off. As described above, the write operation is completed and data "1" is held in the semiconductor device 10. Note that the potentials of the wiring BL and the wiring PL are such that polarization reversal does not occur in the ferroelectric layer of the capacitive element Cfe, that is, the voltage applied to the ferroelectric layer of the capacitive element Cfe is the second coercive voltage. Any potential can be used as long as it is equal to or higher than Vc.
時刻Ｔ０３乃至時刻Ｔ０４において、配線ＷＬの電位を高電位とする。これにより、トランジスタＭがオン状態となる。また、配線ＰＬの電位をＶｗとする。配線ＰＬの電位をＶｗとすることにより、容量素子Ｃｆｅの強誘電体層に印加される電圧が、“ＧＮＤ−Ｖｗ”となる。前述のように、時刻Ｔ０１乃至時刻Ｔ０２において容量素子Ｃｆｅの強誘電体層に印加される電圧は“Ｖｗ−ＧＮＤ”である。よって、容量素子Ｃｆｅの強誘電体層において分極反転が発生する。分極反転の際に、配線ＢＬに電流が流れ、配線ＢＬの電位はＶｒｅｆより高くなる。よって、ビット線ドライバ回路が、半導体装置１０に保持されたデータ“１”を読み出すことができる。したがって、時刻Ｔ０３乃至時刻Ｔ０４は、読み出し動作を行う期間であるということができる。なお、ＶｒｅｆはＧＮＤより高く、Ｖｗより低いものとしているが、例えばＶｗより高くてもよい。 From time T03 to time T04, the potential of the wiring WL is set to a high potential. As a result, transistor M is turned on. Further, the potential of the wiring PL is assumed to be Vw. By setting the potential of the wiring PL to Vw, the voltage applied to the ferroelectric layer of the capacitive element Cfe becomes "GND-Vw". As described above, the voltage applied to the ferroelectric layer of the capacitive element Cfe from time T01 to time T02 is "Vw-GND". Therefore, polarization inversion occurs in the ferroelectric layer of the capacitive element Cfe. At the time of polarization reversal, a current flows through the wiring BL, and the potential of the wiring BL becomes higher than Vref. Therefore, the bit line driver circuit can read data "1" held in the semiconductor device 10. Therefore, time T03 to time T04 can be said to be a period in which a read operation is performed. Although Vref is assumed to be higher than GND and lower than Vw, it may be higher than Vw, for example.
上記読み出しは、破壊読み出しであるため、半導体装置１０に保持されたデータ“１”は失われる。そこで、時刻Ｔ０４乃至時刻Ｔ０５において、配線ＢＬの電位をＶｗとし、配線ＰＬの電位をＧＮＤとする。これにより、半導体装置１０にデータ“１”を再書き込みする。よって、時刻Ｔ０４乃至時刻Ｔ０５は、再書き込み動作を行う期間であるということができる。 Since the above reading is destructive reading, the data "1" held in the semiconductor device 10 is lost. Therefore, from time T04 to time T05, the potential of the wiring BL is set to Vw, and the potential of the wiring PL is set to GND. As a result, data "1" is rewritten into the semiconductor device 10. Therefore, it can be said that time T04 to time T05 is a period in which a rewriting operation is performed.
時刻Ｔ０５乃至時刻Ｔ１１において、配線ＢＬの電位、および配線ＰＬの電位をＧＮＤとする。その後、配線ＷＬの電位を低電位とする。以上により、再書き込み動作が完了し、半導体装置１０にデータ“１”が保持される。 From time T05 to time T11, the potential of the wiring BL and the potential of the wiring PL are set to GND. After that, the potential of the wiring WL is set to a low potential. With the above, the rewrite operation is completed and data "1" is held in the semiconductor device 10.
時刻Ｔ１１乃至時刻Ｔ１２において、配線ＷＬの電位を高電位とし、配線ＰＬの電位をＶｗとする。半導体装置１０にはデータ“１”が保持されているため、配線ＢＬの電位がＶｒｅｆより高くなり、半導体装置１０に保持されているデータ“１”が読み出される。よって、時刻Ｔ１１乃至時刻Ｔ１２は、読み出し動作を行う期間であるということができる。 From time T11 to time T12, the potential of the wiring WL is set to a high potential, and the potential of the wiring PL is set to Vw. Since the data “1” is held in the semiconductor device 10, the potential of the wiring BL becomes higher than Vref, and the data “1” held in the semiconductor device 10 is read out. Therefore, it can be said that the period from time T11 to time T12 is a period in which a read operation is performed.
時刻Ｔ１２乃至時刻Ｔ１３において、配線ＢＬの電位をＧＮＤとする。トランジスタＭはオン状態であるため、容量素子Ｃｆｅの一方の電極の電位はＧＮＤとなる。また、配線ＰＬの電位をＶｗとする。以上より、容量素子Ｃｆｅの強誘電体層に印加される電圧は、“ＧＮＤ−Ｖｗ”となる。これにより、半導体装置１０にデータ“０”を書き込むことができる。よって、時刻Ｔ１２乃至時刻Ｔ１３は、書き込み動作を行う期間であるということができる。 From time T12 to time T13, the potential of the wiring BL is set to GND. Since the transistor M is in the on state, the potential of one electrode of the capacitive element Cfe becomes GND. Further, the potential of the wiring PL is assumed to be Vw. From the above, the voltage applied to the ferroelectric layer of the capacitive element Cfe becomes "GND-Vw". Thereby, data "0" can be written into the semiconductor device 10. Therefore, it can be said that time T12 to time T13 is a period in which a write operation is performed.
時刻Ｔ１３乃至時刻Ｔ１４において、配線ＢＬの電位、および配線ＰＬの電位をＧＮＤとする。これにより、容量素子Ｃｆｅの強誘電体層に印加される電圧は、０Ｖとなる。時刻Ｔ１２乃至時刻Ｔ１３において容量素子Ｃｆｅの強誘電体層に印加される電圧“ＧＮＤ−Ｖｗ”は−ＶＳＰ以下とすることができることから、時刻Ｔ１３乃至時刻Ｔ１４において、容量素子Ｃｆｅの強誘電体層の分極量は図１４Ｂに示す曲線５１に従って変化する。以上より、時刻Ｔ１３乃至時刻Ｔ１４では、容量素子Ｃｆｅの強誘電体層において分極反転は発生しない。 From time T13 to time T14, the potential of the wiring BL and the potential of the wiring PL are set to GND. As a result, the voltage applied to the ferroelectric layer of the capacitive element Cfe becomes 0V. Since the voltage "GND-Vw" applied to the ferroelectric layer of the capacitive element Cfe from time T12 to time T13 can be set to -VSP or less, the voltage "GND-Vw" applied to the ferroelectric layer of the capacitive element Cfe from time T13 to time T14 is The amount of polarization changes according to a curve 51 shown in FIG. 14B. As described above, polarization reversal does not occur in the ferroelectric layer of the capacitive element Cfe between time T13 and time T14.
配線ＢＬの電位、および配線ＰＬの電位をＧＮＤとした後、配線ＷＬの電位を低電位とする。これにより、トランジスタＭがオフ状態となる。以上により、書き込み動作が完了し、半導体装置１０へデータ“０”が保持される。なお、配線ＢＬ、および配線ＰＬの電位は、容量素子Ｃｆｅの強誘電体層において分極反転が発生しない、つまり容量素子Ｃｆｅの強誘電体層に印加される電圧が第１の抗電圧であるＶｃ以下となるのであれば任意の電位とすることができる。 After the potential of the wiring BL and the potential of the wiring PL are set to GND, the potential of the wiring WL is set to a low potential. This turns transistor M off. Through the above steps, the write operation is completed and data "0" is held in the semiconductor device 10. Note that the potentials of the wiring BL and the wiring PL are such that polarization reversal does not occur in the ferroelectric layer of the capacitive element Cfe, that is, the voltage applied to the ferroelectric layer of the capacitive element Cfe is a first coercive voltage Vc. Any potential can be used as long as it is below.
時刻Ｔ１４乃至時刻Ｔ１５において、配線ＷＬの電位を高電位とする。これにより、トランジスタＭがオン状態となる。また、配線ＰＬの電位をＶｗとする。配線ＰＬの電位をＶｗとすることにより、容量素子Ｃｆｅの強誘電体層に印加される電圧が、“ＧＮＤ−Ｖｗ”となる。前述のように、時刻Ｔ１２乃至時刻Ｔ１３において容量素子Ｃｆｅの強誘電体層に印加される電圧は“ＧＮＤ−Ｖｗ”である。よって、容量素子Ｃｆｅの強誘電体層において分極反転が発生しない。よって、配線ＢＬに流れる電流量は、容量素子Ｃｆｅの強誘電体層において分極反転が発生する場合より小さい。これにより、配線ＢＬの電位の上昇幅は、容量素子Ｃｆｅの強誘電体層において分極反転が発生する場合より小さくなり、具体的には配線ＢＬの電位はＶｒｅｆ以下となる。よって、ビット線ドライバ回路が、半導体装置１０に保持されたデータ“０”を読み出すことができる。したがって、時刻Ｔ１４乃至時刻Ｔ１５は、読み出し動作を行う期間であるということができる。 From time T14 to time T15, the potential of the wiring WL is set to a high potential. As a result, transistor M is turned on. Further, the potential of the wiring PL is assumed to be Vw. By setting the potential of the wiring PL to Vw, the voltage applied to the ferroelectric layer of the capacitive element Cfe becomes "GND-Vw". As described above, the voltage applied to the ferroelectric layer of the capacitive element Cfe from time T12 to time T13 is "GND-Vw". Therefore, polarization reversal does not occur in the ferroelectric layer of the capacitive element Cfe. Therefore, the amount of current flowing through the wiring BL is smaller than when polarization inversion occurs in the ferroelectric layer of the capacitive element Cfe. As a result, the amount of increase in the potential of the wiring BL is smaller than that when polarization inversion occurs in the ferroelectric layer of the capacitive element Cfe, and specifically, the potential of the wiring BL becomes equal to or lower than Vref. Therefore, the bit line driver circuit can read data "0" held in the semiconductor device 10. Therefore, it can be said that time T14 to time T15 is a period in which a read operation is performed.
時刻Ｔ１５乃至時刻Ｔ１６において、配線ＢＬの電位をＧＮＤとし、配線ＰＬの電位をＶｗとする。これにより、半導体装置１０にデータ“０”を再書き込みする。よって、時刻Ｔ１５乃至時刻Ｔ１６は、再書き込み動作を行う期間であるということができる。 From time T15 to time T16, the potential of the wiring BL is set to GND, and the potential of the wiring PL is set to Vw. As a result, data "0" is rewritten into the semiconductor device 10. Therefore, it can be said that the period from time T15 to time T16 is a period in which a rewriting operation is performed.
時刻Ｔ１６乃至時刻Ｔ１７において、配線ＢＬの電位、および配線ＰＬの電位をＧＮＤとする。その後、配線ＷＬの電位を低電位とする。以上により、再書き込み動作が完了し、半導体装置１０にデータ“０”が保持される。 From time T16 to time T17, the potential of the wiring BL and the potential of the wiring PL are set to GND. After that, the potential of the wiring WL is set to a low potential. With the above, the rewrite operation is completed and data "0" is held in the semiconductor device 10.
時刻Ｔ１７乃至時刻Ｔ１８において、配線ＷＬの電位を高電位とし、配線ＰＬの電位をＶｗとする。半導体装置１０にはデータ“０”が保持されているため、配線ＢＬの電位がＶｒｅｆより低くなり、半導体装置１０に保持されているデータ“０”が読み出される。よって、時刻Ｔ１７乃至時刻Ｔ１８は、読み出し動作を行う期間であるということができる。 From time T17 to time T18, the potential of the wiring WL is set to a high potential, and the potential of the wiring PL is set to Vw. Since the data "0" is held in the semiconductor device 10, the potential of the wiring BL becomes lower than Vref, and the data "0" held in the semiconductor device 10 is read out. Therefore, it can be said that time T17 to time T18 is a period in which a read operation is performed.
時刻Ｔ１８乃至時刻Ｔ１９において、配線ＢＬの電位をＶｗとする。トランジスタＭはオン状態であるため、容量素子Ｃｆｅの一方の電極の電位はＶｗとなる。また、配線ＰＬの電位をＧＮＤとする。以上より、容量素子Ｃｆｅの強誘電体層に印加される電圧は、“Ｖｗ−ＧＮＤ”となる。これにより、半導体装置１０にデータ“１”を書き込むことができる。よって、時刻Ｔ１８乃至時刻Ｔ１９は、書き込み動作を行う期間であるということができる。 From time T18 to time T19, the potential of the wiring BL is set to Vw. Since the transistor M is in the on state, the potential of one electrode of the capacitive element Cfe becomes Vw. Further, the potential of the wiring PL is set to GND. From the above, the voltage applied to the ferroelectric layer of the capacitive element Cfe becomes "Vw-GND". Thereby, data "1" can be written into the semiconductor device 10. Therefore, time T18 to time T19 can be said to be a period in which a write operation is performed.
時刻Ｔ１９以降において、配線ＢＬの電位、および配線ＰＬの電位をＧＮＤとする。その後、配線ＷＬの電位を低電位とする。以上により、書き込み動作が完了し、半導体装置１０にデータ“１”が保持される。 After time T19, the potential of the wiring BL and the potential of the wiring PL are set to GND. After that, the potential of the wiring WL is set to a low potential. As described above, the write operation is completed and data "1" is held in the semiconductor device 10.
容量素子Ｃｆｅに強誘電体層を用いた半導体装置１０は、電力供給が停止しても書き込まれた情報を保持可能な不揮発性の記憶素子として機能する。 The semiconductor device 10 using a ferroelectric layer for the capacitive element Cfe functions as a nonvolatile memory element that can retain written information even if power supply is stopped.
また、ＤＲＡＭ（Ｄｙｎａｍｉｃ　Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ）では定期的なリフレッシュ動作が必要になるため消費電力が増加する。容量素子Ｃｆｅに強誘電体層を用いた半導体装置１０はリフレッシュ動作が不要であるため、消費電力を低減できる。 Furthermore, DRAM (Dynamic Random Access Memory) requires periodic refresh operations, which increases power consumption. Since the semiconductor device 10 using a ferroelectric layer for the capacitive element Cfe does not require a refresh operation, power consumption can be reduced.
本明細書等において、強誘電体層を含む記憶素子または記憶回路を「強誘電体メモリ」または「ＦＥメモリ」と呼ぶ場合がある。よって、半導体装置１０は強誘電体メモリであり、ＦＥメモリでもある。ＦＥメモリは、１×１０１０以上、好ましくは１×１０１２以上、より好ましくは１×１０１５以上の書き換え回数の実現が期待できる。また、ＦＥメモリは、１０ＭＨｚ以上、好ましくは１ＧＨｚ以上の動作周波数の実現が期待できる。 In this specification and the like, a memory element or a memory circuit including a ferroelectric layer is sometimes referred to as a "ferroelectric memory" or "FE memory." Therefore, the semiconductor device 10 is both a ferroelectric memory and an FE memory. The FE memory can be expected to achieve a rewriting frequency of 1×10 10 or more, preferably 1×10 12 or more, more preferably 1×10 15 or more. Furthermore, the FE memory can be expected to achieve an operating frequency of 10 MHz or higher, preferably 1 GHz or higher.
また、ＦＥメモリにおいて、残留分極２Ｐｒとデータ保持能力には相関があり、残留分極２Ｐｒが小さくなると、データの保持能力が低下する。本明細書等では、残留分極２Ｐｒが５％低下する（データの保持能力が５％低下する）までの期間を「メモリ保持期間」と呼ぶ。ＦＥメモリは、１５０℃または２００℃の環境温度下において、１０日以上、好ましくは１年以上、より好ましくは１０年以上のメモリ保持期間の実現が期待できる。 Furthermore, in the FE memory, there is a correlation between the residual polarization 2Pr and the data retention ability, and as the residual polarization 2Pr becomes smaller, the data retention ability decreases. In this specification and the like, a period until the residual polarization 2Pr decreases by 5% (data retention ability decreases by 5%) is referred to as a "memory retention period." FE memory can be expected to have a memory retention period of 10 days or more, preferably 1 year or more, and more preferably 10 years or more at an environmental temperature of 150° C. or 200° C.
また、ＦＥメモリは、ＣＰＵ（Ｃｅｎｔｒａｌ　Ｐｒｏｃｅｓｓｉｎｇ　Ｕｎｉｔ）、ＧＰＵ（Ｇｒａｐｈｉｃｓ　Ｐｒｏｃｅｓｓｉｎｇ　Ｕｎｉｔ）などの、キャッシュメモリおよびレジスタなどにも適用可能である。ＣＰＵのキャッシュメモリおよびレジスタなどにＦＥメモリを組み合わせることで、Ｎｏｆｆ−ＣＰＵ（Ｎｏｍａｌｙ　ｏｆｆ　ＣＰＵ）を実現できる。ＧＰＵのキャッシュメモリおよびレジスタなどにＦＥメモリを組み合わせることで、Ｎｏｆｆ−ＧＰＵ（Ｎｏｍａｌｙ　ｏｆｆ　ＧＰＵ）を実現できる。 Furthermore, the FE memory can also be applied to cache memories and registers of CPUs (Central Processing Units), GPUs (Graphics Processing Units), and the like. By combining the FE memory with the cache memory and registers of the CPU, an off-CPU (Normally off CPU) can be realized. By combining the FE memory with the cache memory, registers, etc. of the GPU, it is possible to realize a Noff-GPU (Normally off GPU).
本実施の形態は、本明細書で示す他の実施の形態などと適宜組み合わせることができる。 This embodiment mode can be combined with other embodiment modes shown in this specification as appropriate.
（実施の形態２）
本実施の形態では、半導体装置１０をメモリセルとして用いた記憶装置３００の構成例について説明する。 (Embodiment 2)
In this embodiment, a configuration example of a memory device 300 using a semiconductor device 10 as a memory cell will be described.
図１５Ａに、本発明の一態様に係る記憶装置３００の構成例を示すブロック図を示す。図１５Ａに示す記憶装置３００は、駆動回路２１と、メモリアレイ２０と、を有する。メモリアレイ２０は、複数の半導体装置１０を有する。図１５Ａでは、メモリアレイ２０がｍ行ｎ列（ｍおよびｎは２以上の整数。）のマトリクス状に配置された複数の半導体装置１０を有する例を示している。 FIG. 15A shows a block diagram illustrating a configuration example of a storage device 300 according to one embodiment of the present invention. The storage device 300 shown in FIG. 15A includes a drive circuit 21 and a memory array 20. Memory array 20 includes a plurality of semiconductor devices 10. FIG. 15A shows an example in which the memory array 20 includes a plurality of semiconductor devices 10 arranged in a matrix of m rows and n columns (m and n are integers of 2 or more).
なお、行と列は互いに直交する方向に延在する。本実施の形態では、Ｙ方向を「行」とし、Ｘ方向を「列」としているが、Ｙ方向を「列」とし、Ｘ方向を「行」としてもよい。 Note that the rows and columns extend in directions perpendicular to each other. In this embodiment, the Y direction is defined as a "row" and the X direction is defined as a "column," but the Y direction may be defined as a "column" and the X direction may be defined as a "row."
図１５Ａでは、１行１列目の半導体装置１０を半導体装置１０［１，１］と示し、ｍ行ｎ列目の半導体装置１０を半導体装置１０［ｍ，ｎ］と示している。また、本実施の形態などでは、任意の行を示す場合にｉ行と記す場合がある。また、任意の列を示す場合にｊ列と記す場合がある。よって、ｉは１以上ｍ以下の整数であり、ｊは１以上ｎ以下の整数である。また、本実施の形態などでは、ｉ行ｊ列目の半導体装置１０を半導体装置１０［ｉ，ｊ］と示している。なお、本実施の形態などにおいて、「ｉ＋α」（αは正または負の整数）と示す場合は、「ｉ＋α」は１を下回らず、ｍを超えない。同様に、「ｊ＋α」と示す場合は、「ｊ＋α」は１を下回らず、ｎを超えない。 In FIG. 15A, the semiconductor device 10 in the first row and first column is shown as a semiconductor device 10[1,1], and the semiconductor device 10 in the mth row and nth column is shown as a semiconductor device 10[m,n]. Further, in this embodiment and the like, when indicating an arbitrary line, it may be written as i line. Furthermore, when indicating an arbitrary column, it may be written as column j. Therefore, i is an integer of 1 or more and m or less, and j is an integer of 1 or more and n or less. Further, in this embodiment and the like, the semiconductor device 10 in the i-th row and j-th column is referred to as a semiconductor device 10[i,j]. Note that in this embodiment and the like, when expressed as "i+α" (α is a positive or negative integer), "i+α" is not less than 1 and does not exceed m. Similarly, in the case of "j+α", "j+α" is not less than 1 and not more than n.
また、メモリアレイ２０は、行方向（Ｙ方向）に延在するｍ本の配線ＷＬと、行方向（Ｙ方向）に延在するｍ本の配線ＰＬと、Ｚ方向に延在するｎ本の配線ＢＬと、を備える。なお、ｎ本の配線ＢＬはＺ方向に延在するが、配線ＷＬおよび配線ＰＬと配線ＢＬの関係をわかりやすくするため、図１５Ａではｎ本の配線ＢＬを列方向（Ｘ方向）に延在して示している。 The memory array 20 also includes m wires WL extending in the row direction (Y direction), m wires PL extending in the row direction (Y direction), and n wires extending in the Z direction. A wiring BL is provided. Note that although the n wires BL extend in the Z direction, in order to make it easier to understand the relationship between the wires WL, the wires PL, and the wires BL, in FIG. 15A, the n wires BL extend in the column direction (X direction). It is shown as follows.
本実施の形態などでは、１本目（１行目）に設けられた配線ＷＬを配線ＷＬ［１］と示し、ｍ本目（ｍ行目）に設けられた配線ＷＬを配線ＷＬ［ｍ］と示す。同様に、１本目（１行目）に設けられた配線ＰＬを配線ＰＬ［１］と示し、ｍ本目（ｍ行目）に設けられた配線ＰＬを配線ＰＬ［ｍ］と示す。同様に、１本目（１列目）に設けられた配線ＢＬを配線ＢＬ［１］と示し、ｎ本目（ｎ列目）に設けられた配線ＢＬを配線ＢＬ［ｎ］と示す。 In this embodiment and the like, the wiring WL provided in the first (first row) is referred to as wiring WL[1], and the wiring WL provided in m-th (m-th row) is referred to as wiring WL[m]. . Similarly, the first wiring PL (first row) is designated as wiring PL[1], and the mth wiring PL (mth row) is designated as wiring PL[m]. Similarly, the wiring BL provided in the first (first column) is referred to as wiring BL[1], and the wiring BL provided in the nth (nth column) is referred to as wiring BL[n].
ｉ行目に設けられた複数の半導体装置１０は、ｉ行目の配線ＷＬ（配線ＷＬ［ｉ］）とｉ行目の配線ＰＬ（配線ＰＬ［ｉ］）に電気的に接続される。ｊ列目に設けられた複数の半導体装置１０は、ｊ列目の配線ＢＬ（配線ＢＬ［ｊ］）と電気的に接続される。 The plurality of semiconductor devices 10 provided in the i-th row are electrically connected to the i-th wiring WL (wiring WL[i]) and the i-th wiring PL (wiring PL[i]). The plurality of semiconductor devices 10 provided in the j-th column are electrically connected to the wiring BL (wiring BL[j]) in the j-th column.
駆動回路２１は、ＰＳＷ２２（パワースイッチ）、ＰＳＷ２３、および周辺回路３１を有する。周辺回路３１は、周辺回路４１、コントロール回路３２（Ｃｏｎｔｒｏｌ　Ｃｉｒｃｕｉｔ）、および電圧生成回路３３を有する。 The drive circuit 21 includes a PSW 22 (power switch), a PSW 23, and a peripheral circuit 31. The peripheral circuit 31 includes a peripheral circuit 41, a control circuit 32, and a voltage generation circuit 33.
記憶装置３００において、各回路、各信号および各電圧は、必要に応じて、適宜取捨することができる。あるいは、他の回路または他の信号を追加してもよい。信号ＢＷ、信号ＣＥ、信号ＧＷ、信号ＣＬＫ、信号ＷＡＫＥ、信号ＡＤＤＲ、信号ＷＤＡ、信号ＰＯＮ１、信号ＰＯＮ２は外部からの入力信号であり、信号ＲＤＡは外部への出力信号である。信号ＣＬＫはクロック信号である。 In the storage device 300, each circuit, each signal, and each voltage can be removed or discarded as necessary. Alternatively, other circuits or other signals may be added. Signal BW, signal CE, signal GW, signal CLK, signal WAKE, signal ADDR, signal WDA, signal PON1, and signal PON2 are input signals from the outside, and signal RDA is an output signal to the outside. Signal CLK is a clock signal.
また、信号ＢＷ、信号ＣＥ、および信号ＧＷは制御信号である。信号ＣＥはチップイネーブル信号であり、信号ＧＷはグローバル書き込みイネーブル信号であり、信号ＢＷはバイト書き込みイネーブル信号である。信号ＡＤＤＲはアドレス信号である。信号ＷＤＡは書き込みデータであり、信号ＲＤＡは読み出しデータである。信号ＰＯＮ１、信号ＰＯＮ２は、パワーゲーティング制御用信号である。なお、信号ＰＯＮ１、信号ＰＯＮ２は、コントロール回路３２で生成してもよい。 Further, the signal BW, the signal CE, and the signal GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signal PON1 and signal PON2 are power gating control signals. Note that the signal PON1 and the signal PON2 may be generated by the control circuit 32.
コントロール回路３２は、記憶装置３００の動作全般を制御する機能を有するロジック回路である。例えば、コントロール回路は、信号ＣＥ、信号ＧＷおよび信号ＢＷを論理演算して、記憶装置３００の動作モード（例えば、書き込み動作、読み出し動作）を決定する。または、コントロール回路３２は、この動作モードが実行されるように、周辺回路４１の制御信号を生成する。 The control circuit 32 is a logic circuit that has a function of controlling the overall operation of the storage device 300. For example, the control circuit performs a logical operation on the signal CE, the signal GW, and the signal BW to determine the operation mode (eg, write operation, read operation) of the storage device 300. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.
電圧生成回路３３は電圧を生成する機能を有する。信号ＷＡＫＥは、信号ＣＬＫの電圧生成回路３３への入力を制御する機能を有する。例えば、信号ＷＡＫＥにＨレベルの信号が与えられると、信号ＣＬＫが電圧生成回路３３へ入力され、電圧生成回路３３は電圧を生成する。 The voltage generation circuit 33 has a function of generating voltage. The signal WAKE has a function of controlling input of the signal CLK to the voltage generation circuit 33. For example, when an H level signal is applied to the signal WAKE, the signal CLK is input to the voltage generation circuit 33, and the voltage generation circuit 33 generates a voltage.
周辺回路４１は、半導体装置１０に対するデータの書き込みおよび読み出しをするための回路である。周辺回路４１は、行デコーダ４２（Ｒｏｗ　Ｄｅｃｏｄｅｒ）、列デコーダ４４（Ｃｏｌｕｍｎ　Ｄｅｃｏｄｅｒ）、行ドライバ４３（Ｒｏｗ　Ｄｒｉｖｅｒ）、列ドライバ４５（Ｃｏｌｕｍｎ　Ｄｒｉｖｅｒ）、入力回路４７（Ｉｎｐｕｔ　Ｃｉｒ．）、出力回路４８（Ｏｕｔｐｕｔ　Ｃｉｒ．）、センスアンプ４６（Ｓｅｎｓｅ　Ａｍｐｌｉｆｉｅｒ）を有する。 The peripheral circuit 41 is a circuit for writing and reading data to and from the semiconductor device 10. The peripheral circuit 41 includes a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, and an output circuit 48 ( It has an Output Cir.) and a sense amplifier 46 (Sense Amplifier).
行デコーダ４２および列デコーダ４４は、信号ＡＤＤＲをデコードする機能を有する。行デコーダ４２は、アクセスする行を指定するための回路であり、列デコーダ４４は、アクセスする列を指定するための回路である。行ドライバ４３は、行デコーダ４２が指定する配線ＷＬを選択する機能を有する。列ドライバ４５は、データを半導体装置１０に書き込む機能、半導体装置１０からデータを読み出す機能、読み出したデータを保持する機能等を有する。 Row decoder 42 and column decoder 44 have the function of decoding signal ADDR. The row decoder 42 is a circuit for specifying a row to be accessed, and the column decoder 44 is a circuit for specifying a column to be accessed. The row driver 43 has a function of selecting the wiring WL specified by the row decoder 42. The column driver 45 has a function of writing data into the semiconductor device 10, a function of reading data from the semiconductor device 10, a function of holding the read data, and the like.
入力回路４７は、信号ＷＤＡを保持する機能を有する。入力回路４７が保持するデータは、列ドライバ４５に出力される。入力回路４７の出力データが、半導体装置１０に書き込むデータ（Ｄｉｎ）である。列ドライバ４５が半導体装置１０から読み出したデータ（Ｄｏｕｔ）は、出力回路４８に出力される。出力回路４８は、Ｄｏｕｔを保持する機能を有する。また、出力回路４８は、Ｄｏｕｔを記憶装置３００の外部に出力する機能を有する。出力回路４８から出力されるデータが信号ＲＤＡである。 Input circuit 47 has a function of holding signal WDA. The data held by the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is the data (Din) to be written into the semiconductor device 10. The data (Dout) read from the semiconductor device 10 by the column driver 45 is output to the output circuit 48. The output circuit 48 has a function of holding Dout. Further, the output circuit 48 has a function of outputting Dout to the outside of the storage device 300. The data output from the output circuit 48 is the signal RDA.
ＰＳＷ２２は周辺回路３１へのＶＤＤの供給を制御する機能を有する。ＰＳＷ２３は、行ドライバ４３へのＶＨＭの供給を制御する機能を有する。ここでは、記憶装置３００の高電源電圧がＶＤＤであり、低電源電圧はＧＮＤ（接地電位）である。また、ＶＨＭは、ワード線を高レベルにするために用いられる高電源電圧であり、ＶＤＤよりも高い。信号ＰＯＮ１によってＰＳＷ２２のオン・オフが制御され、信号ＰＯＮ２によってＰＳＷ２３のオン・オフが制御される。図１５Ａでは、周辺回路３１において、ＶＤＤが供給される電源ドメインの数を１としているが、複数にすることもできる。この場合、各電源ドメインに対してパワースイッチを設ければよい。 The PSW 22 has a function of controlling the supply of VDD to the peripheral circuit 31. The PSW 23 has a function of controlling the supply of VHM to the row driver 43. Here, the high power supply voltage of the storage device 300 is VDD, and the low power supply voltage is GND (ground potential). Further, VHM is a high power supply voltage used to bring the word line to a high level, and is higher than VDD. The signal PON1 controls the on/off of the PSW22, and the signal PON2 controls the on/off of the PSW23. In FIG. 15A, in the peripheral circuit 31, the number of power domains to which VDD is supplied is one, but the number may be plural. In this case, a power switch may be provided for each power domain.
駆動回路２１とメモリアレイ２０は同一平面上に設けてもよい。また、図１５Ｂに示すように、駆動回路２１を含む層の直上にメモリアレイ２０を含む層を重ねて設けてもよい。駆動回路２１とメモリアレイ２０を重ねて設けることで、駆動回路２１とメモリアレイ２０の間の信号伝搬距離を短くすることができる。よって、駆動回路２１とメモリアレイ２０の間の抵抗および寄生容量が低減され、消費電力および信号遅延の低減が実現できる。また、記憶装置３００の小型化が実現できる。 The drive circuit 21 and the memory array 20 may be provided on the same plane. Furthermore, as shown in FIG. 15B, a layer containing the memory array 20 may be provided directly above the layer containing the drive circuit 21. By overlapping the drive circuit 21 and the memory array 20, the signal propagation distance between the drive circuit 21 and the memory array 20 can be shortened. Therefore, resistance and parasitic capacitance between drive circuit 21 and memory array 20 are reduced, and power consumption and signal delay can be reduced. Furthermore, the storage device 300 can be made smaller.
また、図１５Ｂでは駆動回路２１上にメモリアレイ２０を１層重ねて設けているが、駆動回路２１上に複数層のメモリアレイ２０を重ねて設けてもよい。図１５Ｃに、駆動回路２１上にｋ層（ｋは２以上の整数）のメモリアレイ２０を重ねて設ける例を示す。図１５Ｃなどでは、１層目に設けられたメモリアレイ２０をメモリアレイ２０［１］と示し、２層目に設けられたメモリアレイ２０をメモリアレイ２０［２］と示し、ｋ層目に設けられたメモリアレイ２０をメモリアレイ２０［ｋ］と示している。 Further, in FIG. 15B, one layer of the memory array 20 is provided on the drive circuit 21, but a plurality of layers of memory arrays 20 may be provided on the drive circuit 21. FIG. 15C shows an example in which k-layer (k is an integer of 2 or more) memory arrays 20 are stacked on the drive circuit 21. In FIG. 15C and the like, the memory array 20 provided in the first layer is indicated as memory array 20[1], the memory array 20 provided in the second layer is indicated as memory array 20[2], and the memory array 20 provided in the kth layer is indicated as memory array 20[2]. The memory array 20 thus obtained is designated as memory array 20[k].
図１６Ａに、記憶装置３００の構成例を説明する模式図を示す。図１６Ａに示す記憶装置３００は、駆動回路２１上に設けられた６層のメモリアレイ２０を有する。前述したように、図１６Ａなどでは、３層目に設けられたメモリアレイ２０をメモリアレイ２０［３］と示し、４層目に設けられたメモリアレイ２０をメモリアレイ２０［４］と示し、５層目に設けられたメモリアレイ２０をメモリアレイ２０［５］と示し、６層目に設けられたメモリアレイ２０をメモリアレイ２０［６］と示している。 FIG. 16A shows a schematic diagram illustrating a configuration example of the storage device 300. A memory device 300 shown in FIG. 16A has a six-layer memory array 20 provided on a drive circuit 21. As described above, in FIG. 16A and the like, the memory array 20 provided in the third layer is indicated as memory array 20[3], the memory array 20 provided in the fourth layer is indicated as memory array 20[4], The memory array 20 provided in the fifth layer is indicated as memory array 20[5], and the memory array 20 provided in the sixth layer is indicated as memory array 20[6].
各層のメモリアレイ２０は、それぞれがマトリクス状に配置された複数の半導体装置１０と、Ｙ方向に延在する配線ＷＬおよび配線ＰＬを有する。なお、図面を見やすくするため、１層から５層目のメモリアレイ２０それぞれが有する配線ＷＬおよび配線ＰＬの記載を省略している。 The memory array 20 in each layer includes a plurality of semiconductor devices 10 arranged in a matrix, and a wiring WL and a wiring PL extending in the Y direction. Note that in order to make the drawing easier to read, the wiring WL and wiring PL included in each of the first to fifth memory arrays 20 are omitted.
また、図１６Ａに示す記憶装置３００は、Ｚ方向に延在する複数の配線ＢＬを有する。配線ＢＬは６層のメモリアレイ２０それぞれを通して形成され、駆動回路２１と電気的に接続する。Ｚ方向から見ると、複数の配線ＢＬはマトリクス状に配置されている。 Furthermore, the storage device 300 shown in FIG. 16A has a plurality of wirings BL extending in the Z direction. The wiring BL is formed through each of the six layers of memory arrays 20 and electrically connected to the drive circuit 21. When viewed from the Z direction, the plurality of wirings BL are arranged in a matrix.
配線ＢＬをＺ方向に延在させて駆動回路２１と電気的に接続することで、配線ＢＬをＸ方向またはＹ方向に延在させた場合よりも、半導体装置１０と駆動回路２１の接続距離を短くすることができる。よって、半導体装置１０と駆動回路２１の信号伝搬距離が短くなるため、記憶装置の動作速度を高めることができる。また、配線ＢＬに付帯する寄生容量が低減されるため、消費電力が低減できる。 By extending the wiring BL in the Z direction and electrically connecting it to the drive circuit 21, the connection distance between the semiconductor device 10 and the drive circuit 21 can be made shorter than when the wiring BL is extended in the X or Y direction. Can be shortened. Therefore, since the signal propagation distance between the semiconductor device 10 and the drive circuit 21 is shortened, the operating speed of the memory device can be increased. Furthermore, since the parasitic capacitance attached to the wiring BL is reduced, power consumption can be reduced.
また、各層のメモリアレイ２０それぞれにおいて、メモリアレイ２０が有する複数の半導体装置１０の１つは、複数の配線ＢＬの１つと電気的に接続される。よって、図１６Ａに示す記憶装置３００において、１つの配線ＢＬには、各層のメモリアレイ２０から１つずつ、合計６個の半導体装置１０が電気的に接続される。 Furthermore, in each of the memory arrays 20 in each layer, one of the plurality of semiconductor devices 10 included in the memory array 20 is electrically connected to one of the plurality of wirings BL. Therefore, in the memory device 300 shown in FIG. 16A, a total of six semiconductor devices 10, one from each layer of the memory array 20, are electrically connected to one wiring BL.
１つの配線ＢＬに複数のメモリセル（半導体装置１０）が電気的に接続される構成を「メモリストリング」ともいう。よって、図１６Ａに示す記憶装置３００は、複数のメモリストリングを含んで構成されていると言える。 A configuration in which a plurality of memory cells (semiconductor devices 10) are electrically connected to one wiring BL is also referred to as a "memory string." Therefore, it can be said that the storage device 300 shown in FIG. 16A is configured to include a plurality of memory strings.
図１６Ｂに、図１６Ａに示す記憶装置３００が有するメモリストリングの模式図を示す。なお、図面を見やすくするため、図１６Ｂに示すメモリストリングの模式図では、半導体装置１０と電気的に接続する配線ＷＬおよび配線ＰＬの記載を省略している。また、図１６Ｂにメモリストリングの等価回路の一部を付記している。 FIG. 16B shows a schematic diagram of a memory string included in the storage device 300 shown in FIG. 16A. Note that in order to make the drawing easier to read, the wiring WL and wiring PL electrically connected to the semiconductor device 10 are omitted in the schematic diagram of the memory string shown in FIG. 16B. Further, a part of the equivalent circuit of the memory string is added to FIG. 16B.
図１７Ａに、記憶装置３００の構成例を説明する模式図を示す。図１７Ａに示す記憶装置３００は、図１６Ａに示す記憶装置３００の変形例である。よって、説明の繰り返しを少なくするため、主に図１６Ａに示す記憶装置３００と異なる点について説明する。 FIG. 17A shows a schematic diagram illustrating a configuration example of the storage device 300. The storage device 300 shown in FIG. 17A is a modification of the storage device 300 shown in FIG. 16A. Therefore, in order to reduce the repetition of explanation, mainly the points different from the storage device 300 shown in FIG. 16A will be explained.
図１７Ａに示す記憶装置３００では、各層のメモリアレイ２０それぞれにおいて、メモリアレイ２０が有する複数の半導体装置１０のうち２つが、複数の配線ＢＬの１つと電気的に接続される点が、図１６Ａに示す記憶装置３００と異なる。すなわち、１つの配線ＢＬに合計１２個の半導体装置１０が電気的に接続される。 In the memory device 300 shown in FIG. 17A, in each of the memory arrays 20 in each layer, two of the plurality of semiconductor devices 10 included in the memory array 20 are electrically connected to one of the plurality of wirings BL. This is different from the storage device 300 shown in FIG. That is, a total of 12 semiconductor devices 10 are electrically connected to one wiring BL.
図１７Ｂに、図１７Ａに示す記憶装置３００が有するメモリストリングの模式図を示す。また、図１７Ｂにメモリストリングの等価回路の一部を付記している。 FIG. 17B shows a schematic diagram of a memory string included in the storage device 300 shown in FIG. 17A. Further, a part of the equivalent circuit of the memory string is added to FIG. 17B.
図１７Ａに示す記憶装置３００では、図１６Ａに示す記憶装置３００よりも配線ＢＬの数を低減できる。よって、記憶装置３００の占有面積が低減される。 In the storage device 300 shown in FIG. 17A, the number of wirings BL can be reduced more than in the storage device 300 shown in FIG. 16A. Therefore, the area occupied by the storage device 300 is reduced.
また、本発明の一態様に係る半導体装置１０はＦＥメモリであり、電力供給が停止しても書き込まれた情報を長期間保持できる。また、ＤＲＡＭで必要なリフレッシュ動作が不要であるため、消費電力の少ない記憶装置３００が実現できる。 Further, the semiconductor device 10 according to one embodiment of the present invention is an FE memory, and can retain written information for a long period of time even if power supply is stopped. Furthermore, since the refresh operation required in DRAM is not required, a storage device 300 with low power consumption can be realized.
［半導体装置の構成例］
本発明の一態様に係る記憶装置３００の断面構成例を図１８に示す。図１８に示す記憶装置３００は、駆動回路２１の上方にｋ層のメモリアレイ２０を有する。図１８では、ｋ層のメモリアレイ２０として、図１１および図１７に示した構成を例示している。説明の繰り返しを減らすため、ここでのｋ層のメモリアレイ２０の説明は省略する。 [Example of configuration of semiconductor device]
FIG. 18 shows an example of a cross-sectional configuration of a storage device 300 according to one embodiment of the present invention. A memory device 300 shown in FIG. 18 has a k-layer memory array 20 above a drive circuit 21. In FIG. 18, the configuration shown in FIGS. 11 and 17 is illustrated as the k-layer memory array 20. In order to reduce repetition of explanation, explanation of the k-layer memory array 20 will be omitted here.
また、図１８では、駆動回路２１が有するトランジスタ４００を例示している。トランジスタ４００は、基板３１１上に設けられ、ゲートとして機能する導電層３１６、ゲート絶縁体として機能する絶縁層３１５、基板３１１の一部からなる半導体領域３１３、およびソース領域またはドレイン領域として機能する低抵抗領域３１４ａ、および低抵抗領域３１４ｂを有する。トランジスタ４００は、ｐチャネル型のトランジスタ、あるいはｎチャネル型のトランジスタのいずれでもよい。基板３１１としては、例えば単結晶シリコン基板を用いることができる。 Further, FIG. 18 illustrates a transistor 400 included in the drive circuit 21. The transistor 400 is provided over a substrate 311 and includes a conductive layer 316 that functions as a gate, an insulating layer 315 that functions as a gate insulator, a semiconductor region 313 that is a part of the substrate 311, and a low layer that functions as a source region or a drain region. It has a resistance region 314a and a low resistance region 314b. The transistor 400 may be either a p-channel transistor or an n-channel transistor. As the substrate 311, for example, a single crystal silicon substrate can be used.
ここで、図１８に示すトランジスタ４００はチャネルが形成される半導体領域３１３（基板３１１の一部）が凸形状を有する。また、半導体領域３１３の側面および上面を、絶縁層３１５を介して、導電層３１６が覆うように設けられている。なお、導電層３１６は仕事関数を調整する材料を用いてもよい。このようなトランジスタ４００は半導体基板の凸部を利用していることからＦＩＮ型トランジスタとも呼ばれる。なお、凸部の上部に接して、凸部を形成するためのマスクとして機能する絶縁体を有していてもよい。また、ここでは半導体基板の一部を加工して凸部を形成する場合を示したが、ＳＯＩ（Ｓｉｌｉｃｏｎ　ｏｎ　Ｉｎｓｕｌａｔｏｒ）基板を加工して凸形状を有する半導体膜を形成してもよい。 Here, in the transistor 400 shown in FIG. 18, a semiconductor region 313 (a part of the substrate 311) in which a channel is formed has a convex shape. Furthermore, a conductive layer 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulating layer 315 interposed therebetween. Note that the conductive layer 316 may be formed using a material that adjusts the work function. Such a transistor 400 is also called a FIN type transistor because it utilizes a convex portion of a semiconductor substrate. Note that an insulator may be provided in contact with the upper portion of the convex portion to function as a mask for forming the convex portion. Furthermore, although a case is shown in which a convex portion is formed by processing a part of a semiconductor substrate, a semiconductor film having a convex shape may be formed by processing an SOI (Silicon on Insulator) substrate.
なお、図１８に示すトランジスタ４００は一例であり、その構造に限定されず、回路構成または駆動方法に応じて適切なトランジスタを用いればよい。 Note that the transistor 400 illustrated in FIG. 18 is an example, and the structure is not limited, and an appropriate transistor may be used depending on the circuit configuration or driving method.
各構造体の間には、層間膜、配線、およびプラグ等が設けられた配線層が設けられていてもよい。また、配線層は、設計に応じて複数層設けることができる。また、本明細書等において、配線と、配線と電気的に接続するプラグとが一体物であってもよい。すなわち、導電体の一部が配線として機能する場合、および導電体の一部がプラグとして機能する場合もある。 A wiring layer including an interlayer film, wiring, plug, etc. may be provided between each structure. Further, a plurality of wiring layers can be provided depending on the design. Further, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.
例えば、トランジスタ４００上には、層間膜として、絶縁層３２０、絶縁層３２２、絶縁層３２４、および絶縁層３２６が順に積層して設けられている。また、絶縁層３２０、絶縁層３２２、絶縁層３２４、および絶縁層３２６には導電層１５２と電気的に接続する導電層３２８、および導電層３３０などが埋め込まれている。なお、導電層３２８、および導電層３３０はコンタクトプラグまたは配線として機能する。 For example, over the transistor 400, an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are sequentially stacked and provided as interlayer films. Further, a conductive layer 328, a conductive layer 330, and the like that are electrically connected to the conductive layer 152 are embedded in the insulating layer 320, the insulating layer 322, the insulating layer 324, and the insulating layer 326. Note that the conductive layer 328 and the conductive layer 330 function as a contact plug or a wiring.
また、層間膜として機能する絶縁体は、その下方の凹凸形状を被覆する平坦化膜として機能してもよい。例えば、絶縁層３２２の上面は、平坦性を高めるためにＣＭＰ処理等を行なってもよい。 Furthermore, the insulator that functions as an interlayer film may function as a flattening film that covers the uneven shape below it. For example, the upper surface of the insulating layer 322 may be subjected to CMP treatment or the like to improve flatness.
絶縁層３２６および導電層３３０上に、配線層を設けてもよい。例えば、図１８において、絶縁層３２６および導電層３３０上に、絶縁層３５０、絶縁層３５２、及び絶縁層３５４が順に積層して設けられている。絶縁層３５０、絶縁層３５２、及び絶縁層３５４には、導電層３５６が形成されている。導電層３５６は、コンタクトプラグまたは配線として機能する。導電層３５６は導電層１５２と電気的に接続される。 A wiring layer may be provided over the insulating layer 326 and the conductive layer 330. For example, in FIG. 18, an insulating layer 350, an insulating layer 352, and an insulating layer 354 are sequentially stacked on an insulating layer 326 and a conductive layer 330. A conductive layer 356 is formed on the insulating layer 350, the insulating layer 352, and the insulating layer 354. The conductive layer 356 functions as a contact plug or a wiring. Conductive layer 356 is electrically connected to conductive layer 152.
本実施の形態は、本明細書で示す他の実施の形態などと適宜組み合わせることができる。 This embodiment mode can be combined with other embodiment modes shown in this specification as appropriate.
（実施の形態３）
本実施の形態では、上記の実施の形態で説明したＯＳトランジスタに用いることができる金属酸化物（以下、酸化物半導体ともいう。）について説明する。 (Embodiment 3)
This embodiment mode describes a metal oxide (hereinafter also referred to as an oxide semiconductor) that can be used for the OS transistor described in the above embodiment mode.
ＯＳトランジスタに用いる金属酸化物は、少なくともインジウムまたは亜鉛を有することが好ましく、インジウムおよび亜鉛を有することがより好ましい。例えば、金属酸化物は、インジウムと、Ｍ（Ｍは、ガリウム、アルミニウム、イットリウム、スズ、シリコン、ホウ素、銅、バナジウム、ベリリウム、チタン、鉄、ニッケル、ゲルマニウム、ジルコニウム、モリブデン、ランタン、セリウム、ネオジム、ハフニウム、タンタル、タングステン、マグネシウム、およびコバルトから選ばれた一種または複数種）と、亜鉛と、を有することが好ましい。特に、Ｍは、ガリウム、アルミニウム、イットリウム、アンチモン、およびスズから選ばれた一種または複数種であることが好ましく、ガリウムがより好ましい。 The metal oxide used in the OS transistor preferably contains at least indium or zinc, more preferably indium and zinc. For example, metal oxides include indium and M (M is gallium, aluminum, yttrium, tin, silicon, boron, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium). , hafnium, tantalum, tungsten, magnesium, and cobalt) and zinc. In particular, M is preferably one or more selected from gallium, aluminum, yttrium, antimony, and tin, with gallium being more preferred.
金属酸化物は、スパッタリング法、有機金属化学気相成長（ＭＯＣＶＤ：Ｍｅｔａｌ　Ｏｒｇａｎｉｃ　Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）法などの化学気相成長（ＣＶＤ：Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）法、または、原子層堆積（ＡＬＤ：Ａｔｏｍｉｃ　Ｌａｙｅｒ　Ｄｅｐｏｓｉｔｉｏｎ）法などにより形成することができる。 Metal oxides can be produced by chemical vapor deposition (CVD) methods such as sputtering, metal organic chemical vapor deposition (MOCVD), or atomic layer deposition (AL). D: Atomic Layer Deposition ) method.
以降では、金属酸化物の一例として、インジウム（Ｉｎ）、ガリウム（Ｇａ）、および亜鉛（Ｚｎ）を含む酸化物について説明する。なお、インジウム（Ｉｎ）、ガリウム（Ｇａ）、および亜鉛（Ｚｎ）を含む酸化物を、Ｉｎ−Ｇａ−Ｚｎ酸化物と呼ぶ場合がある。 Hereinafter, oxides containing indium (In), gallium (Ga), and zinc (Zn) will be described as examples of metal oxides. Note that an oxide containing indium (In), gallium (Ga), and zinc (Zn) may be referred to as an In-Ga-Zn oxide.
＜結晶構造の分類＞
酸化物半導体の結晶構造としては、アモルファス（ｃｏｍｐｌｅｔｅｌｙ　ａｍｏｒｐｈｏｕｓを含む）、ＣＡＡＣ（ｃ−ａｘｉｓ−ａｌｉｇｎｅｄ　ｃｒｙｓｔａｌｌｉｎｅ）、ｎｃ（ｎａｎｏｃｒｙｓｔａｌｌｉｎｅ）、ＣＡＣ（ｃｌｏｕｄ−ａｌｉｇｎｅｄ　ｃｏｍｐｏｓｉｔｅ）、単結晶（ｓｉｎｇｌｅ　ｃｒｙｓｔａｌ）、および多結晶（ｐｏｌｙ　ｃｒｙｓｔａｌ）等が挙げられる。 <Crystal structure classification>
The crystal structures of oxide semiconductors include amorphous (including completely amorphous), CAAC (c-axis-aligned crystalline), nc (nanocrystalline), CAC (cloud-aligned composite), and single crystal ( single crystal), and polycrystalline (poly crystal), etc.
なお、膜または基板の結晶構造は、Ｘ線回折（ＸＲＤ：Ｘ−Ｒａｙ　Ｄｉｆｆｒａｃｔｉｏｎ）スペクトルを用いて評価することができる。例えば、ＧＩＸＤ（Ｇｒａｚｉｎｇ−Ｉｎｃｉｄｅｎｃｅ　ＸＲＤ）測定で得られるＸＲＤスペクトルを用いて評価することができる。なお、ＧＩＸＤ法は、薄膜法またはＳｅｅｍａｎｎ−Ｂｏｈｌｉｎ法ともいう。また、以下では、ＧＩＸＤ測定で得られるＸＲＤスペクトルを、単に、ＸＲＤスペクトルと記す場合がある。 Note that the crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. For example, it can be evaluated using an XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement. Note that the GIXD method is also referred to as a thin film method or Seemann-Bohlin method. Moreover, below, the XRD spectrum obtained by GIXD measurement may be simply referred to as an XRD spectrum.
例えば、石英ガラス基板では、ＸＲＤスペクトルのピークの形状がほぼ左右対称である。一方で、結晶構造を有するＩｎ−Ｇａ−Ｚｎ酸化物膜では、ＸＲＤスペクトルのピークの形状が左右非対称である。ＸＲＤスペクトルのピークの形状が左右非対称であることは、膜中または基板中の結晶の存在を明示している。別言すると、ＸＲＤスペクトルのピークの形状で左右対称でないと、膜または基板は非晶質状態であるとは言えない。 For example, in the case of a quartz glass substrate, the shape of the peak in the XRD spectrum is approximately symmetrical. On the other hand, in an In-Ga-Zn oxide film having a crystal structure, the peak shape of the XRD spectrum is asymmetrical. The fact that the peak shape of the XRD spectrum is asymmetrical indicates the presence of crystals in the film or substrate. In other words, if the shape of the peak in the XRD spectrum is not bilaterally symmetrical, the film or substrate cannot be said to be in an amorphous state.
また、膜または基板の結晶構造は、極微電子線回折法（ＮＢＥＤ：Ｎａｎｏ　Ｂｅａｍ　Ｅｌｅｃｔｒｏｎ　Ｄｉｆｆｒａｃｔｉｏｎ）によって観察される回折パターン（極微電子線回折パターンともいう）にて評価することができる。例えば、石英ガラス基板の回折パターンでは、ハローが観察され、石英ガラスは、非晶質状態であることが確認できる。また、室温成膜したＩｎ−Ｇａ−Ｚｎ酸化物膜の回折パターンでは、ハローではなく、スポット状のパターンが観察される。このため、室温成膜したＩｎ−Ｇａ−Ｚｎ酸化物は、単結晶または多結晶でもなく、非晶質状態でもない、中間状態であり、非晶質状態であると結論することはできないと推定される。 Further, the crystal structure of a film or substrate can be evaluated based on a diffraction pattern (also referred to as a nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). For example, a halo is observed in the diffraction pattern of a quartz glass substrate, confirming that the quartz glass is in an amorphous state. Moreover, in the diffraction pattern of the In-Ga-Zn oxide film formed at room temperature, a spot-like pattern is observed instead of a halo. Therefore, it is assumed that the In-Ga-Zn oxide film formed at room temperature is neither single crystal nor polycrystalline, nor is it in an amorphous state, but in an intermediate state, and it cannot be concluded that it is in an amorphous state. be done.
〔酸化物半導体の構造〕
なお、酸化物半導体は、構造に着目した場合、上記とは異なる分類となる場合がある。例えば、酸化物半導体は、単結晶酸化物半導体と、それ以外の非単結晶酸化物半導体と、に分けられる。非単結晶酸化物半導体として、例えば、上述のＣＡＡＣ−ＯＳ、およびｎｃ−ＯＳがある。また、非単結晶酸化物半導体には、多結晶酸化物半導体、擬似非晶質酸化物半導体（ａ−ｌｉｋｅ　ＯＳ：ａｍｏｒｐｈｏｕｓ−ｌｉｋｅ　ｏｘｉｄｅ　ｓｅｍｉｃｏｎｄｕｃｔｏｒ）、非晶質酸化物半導体、等が含まれる。 [Structure of oxide semiconductor]
Note that when focusing on the structure, oxide semiconductors may be classified into a different classification from the above. For example, oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Further, non-single crystal oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS), amorphous oxide semiconductors, and the like.
ここで、上述のＣＡＡＣ−ＯＳ、ｎｃ−ＯＳ、およびａ−ｌｉｋｅ　ＯＳの詳細について、説明を行う。 Here, details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be explained.
［ＣＡＡＣ−ＯＳ］
ＣＡＡＣ−ＯＳは、複数の結晶領域を有し、当該複数の結晶領域はｃ軸が特定の方向に配向している酸化物半導体である。なお、特定の方向とは、ＣＡＡＣ−ＯＳ膜の厚さ方向、ＣＡＡＣ−ＯＳ膜の被形成面の法線方向、またはＣＡＡＣ−ＯＳ膜の表面の法線方向である。また、結晶領域とは、原子配列に周期性を有する領域である。なお、原子配列を格子配列とみなすと、結晶領域とは、格子配列の揃った領域でもある。さらに、ＣＡＡＣ−ＯＳは、ａ−ｂ面方向において複数の結晶領域が連結する領域を有し、当該領域は歪みを有する場合がある。なお、歪みとは、複数の結晶領域が連結する領域において、格子配列の揃った領域と、別の格子配列の揃った領域と、の間で格子配列の向きが変化している箇所を指す。つまり、ＣＡＡＣ−ＯＳは、ｃ軸配向し、ａ−ｂ面方向には明らかな配向をしていない酸化物半導体である。 [CAAC-OS]
CAAC-OS is an oxide semiconductor that has a plurality of crystal regions, and the c-axes of the plurality of crystal regions are oriented in a specific direction. Note that the specific direction is the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. Further, a crystal region is a region having periodicity in atomic arrangement. Note that if the atomic arrangement is regarded as a lattice arrangement, a crystal region is also a region with a uniform lattice arrangement. Further, the CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and this region may have distortion. Note that distortion refers to a region where a plurality of crystal regions are connected, where the direction of the lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement. In other words, CAAC-OS is an oxide semiconductor that has c-axis orientation and no obvious orientation in the a-b plane direction.
なお、上記複数の結晶領域のそれぞれは、１つまたは複数の微小な結晶（最大径が１０ｎｍ未満である結晶）で構成される。結晶領域が１つの微小な結晶で構成されている場合、当該結晶領域の最大径は１０ｎｍ未満となる。また、結晶領域が多数の微小な結晶で構成されている場合、当該結晶領域の最大径は、数十ｎｍ程度となる場合がある。 Note that each of the plurality of crystal regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When the crystal region is composed of one minute crystal, the maximum diameter of the crystal region is less than 10 nm. Further, when the crystal region is composed of many minute crystals, the maximum diameter of the crystal region may be about several tens of nanometers.
また、Ｉｎ−Ｇａ−Ｚｎ酸化物において、ＣＡＡＣ−ＯＳは、インジウム（Ｉｎ）、および酸素を有する層（以下、Ｉｎ層）と、ガリウム（Ｇａ）、亜鉛（Ｚｎ）、および酸素を有する層（以下、（Ｇａ，Ｚｎ）層）とが積層した、層状の結晶構造（層状構造ともいう）を有する傾向がある。なお、インジウムとガリウムは、互いに置換可能である。よって、（Ｇａ，Ｚｎ）層にはインジウムが含まれる場合がある。また、Ｉｎ層にはガリウムが含まれる場合がある。なお、Ｉｎ層には亜鉛が含まれる場合もある。当該層状構造は、例えば、高分解能ＴＥＭ（Ｔｒａｎｓｍｉｓｓｉｏｎ　Ｅｌｅｃｔｒｏｎ　Ｍｉｃｒｏｓｃｏｐｅ）像において、格子像として観察される。 In addition, in In-Ga-Zn oxide, CAAC-OS consists of a layer containing indium (In) and oxygen (hereinafter referred to as In layer), and a layer containing gallium (Ga), zinc (Zn), and oxygen (hereinafter referred to as In layer). Hereinafter, it tends to have a layered crystal structure (also referred to as a layered structure) in which (Ga, Zn) layers are laminated. Note that indium and gallium can be substituted for each other. Therefore, the (Ga, Zn) layer may contain indium. Further, the In layer may contain gallium. Note that the In layer may contain zinc. The layered structure is observed, for example, as a lattice image in a high-resolution TEM (Transmission Electron Microscope) image.
ＣＡＡＣ−ＯＳ膜に対し、例えば、ＸＲＤ装置を用いて構造解析を行うと、θ／２θスキャンを用いたＯｕｔ−ｏｆ−ｐｌａｎｅ　ＸＲＤ測定では、ｃ軸配向を示すピークが２θ＝３１度またはその近傍に検出される。なお、ｃ軸配向を示すピークの位置（２θの値）は、ＣＡＡＣ−ＯＳを構成する金属元素の種類、組成等により変動する場合がある。 For example, when structural analysis is performed on a CAAC-OS film using an XRD device, an out-of-plane XRD measurement using a θ/2θ scan shows that the peak indicating the c-axis orientation is at or near 2θ = 31 degrees. detected. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type, composition, etc. of the metal element constituting the CAAC-OS.
また、例えば、ＣＡＡＣ−ＯＳ膜の電子線回折パターンにおいて、複数の輝点（スポット）が観測される。なお、あるスポットと別のスポットとは、試料を透過した入射電子線のスポット（ダイレクトスポットともいう。）を対称中心として、点対称の位置に観測される。 Further, for example, a plurality of bright points (spots) are observed in the electron diffraction pattern of the CAAC-OS film. Note that a certain spot and another spot are observed at points symmetrical positions with the spot of the incident electron beam transmitted through the sample (also referred to as a direct spot) as the center of symmetry.
上記特定の方向から結晶領域を観察した場合、当該結晶領域内の格子配列は、六方格子を基本とするが、単位格子は正六角形とは限らず、非正六角形である場合がある。また、上記歪みにおいて、五角形、七角形等の格子配列を有する場合がある。なお、ＣＡＡＣ−ＯＳにおいて、歪み近傍においても、明確な結晶粒界（グレインバウンダリー）を確認することはできない。即ち、格子配列の歪みによって、結晶粒界の形成が抑制されていることがわかる。これは、ＣＡＡＣ−ＯＳが、ａ−ｂ面方向において酸素原子の配列が稠密でないこと、金属原子が置換することで原子間の結合距離が変化すること、などによって、歪みを許容することができるためと考えられる。 When a crystal region is observed from the above-mentioned specific direction, the lattice arrangement within the crystal region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon but may be a non-regular hexagon. Further, the above distortion may have a pentagonal, heptagonal, etc. lattice arrangement. Note that in CAAC-OS, clear grain boundaries cannot be confirmed even in the vicinity of strain. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction, the bond distance between atoms changes due to substitution of metal atoms, etc. It is thought that this is because of this.
なお、明確な結晶粒界が確認される結晶構造は、いわゆる多結晶と呼ばれる。結晶粒界は、再結合中心となり、キャリアが捕獲されトランジスタのオン電流の低下、電界効果移動度の低下等を引き起こす可能性が高い。よって、明確な結晶粒界が確認されないＣＡＡＣ−ＯＳは、トランジスタの半導体層に好適な結晶構造を有する結晶性の酸化物の一つである。なお、ＣＡＡＣ−ＯＳを構成するには、Ｚｎを有する構成が好ましい。例えば、Ｉｎ−Ｚｎ酸化物、およびＩｎ−Ｇａ−Ｚｎ酸化物は、Ｉｎ酸化物よりも結晶粒界の発生を抑制できるため好適である。 Note that a crystal structure in which clear grain boundaries are confirmed is called polycrystalline. The crystal grain boundaries become centers of recombination, and carriers are likely to be captured, resulting in a decrease in the on-current of the transistor, a decrease in field effect mobility, and the like. Therefore, CAAC-OS, in which clear grain boundaries are not confirmed, is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. Note that in order to configure the CAAC-OS, a configuration including Zn is preferable. For example, In--Zn oxide and In--Ga--Zn oxide are more suitable than In oxide because they can suppress the generation of grain boundaries.
ＣＡＡＣ−ＯＳは、結晶性が高く、明確な結晶粒界が確認されない酸化物半導体である。よって、ＣＡＡＣ−ＯＳは、結晶粒界に起因する電子移動度の低下が起こりにくいといえる。また、酸化物半導体の結晶性は不純物の混入および／または欠陥の生成等によって低下する場合があるため、ＣＡＡＣ−ＯＳは不純物および欠陥（酸素欠損等）の少ない酸化物半導体ともいえる。従って、ＣＡＡＣ−ＯＳを有する酸化物半導体は、物理的性質が安定する。そのため、ＣＡＡＣ−ＯＳを有する酸化物半導体は熱に強く、信頼性が高い。また、ＣＡＡＣ−ＯＳは、製造工程における高い温度（所謂サーマルバジェット）に対しても安定である。したがって、ＯＳトランジスタにＣＡＡＣ−ＯＳを用いると、製造工程の自由度を広げることが可能となる。 CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, it can be said that in CAAC-OS, reduction in electron mobility due to grain boundaries is less likely to occur. Further, since the crystallinity of an oxide semiconductor may be reduced due to the incorporation of impurities and/or the generation of defects, CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the oxide semiconductor having CAAC-OS has stable physical properties. Therefore, an oxide semiconductor including a CAAC-OS is resistant to heat and has high reliability. Furthermore, CAAC-OS is stable even at high temperatures (so-called thermal budget) during the manufacturing process. Therefore, if CAAC-OS is used for the OS transistor, the degree of freedom in the manufacturing process can be expanded.
［ｎｃ−ＯＳ］
ｎｃ−ＯＳは、微小な領域（例えば、１ｎｍ以上１０ｎｍ以下の領域、特に１ｎｍ以上３ｎｍ以下の領域）において原子配列に周期性を有する。別言すると、ｎｃ−ＯＳは、微小な結晶を有する。なお、当該微小な結晶の大きさは、例えば、１ｎｍ以上１０ｎｍ以下、特に１ｎｍ以上３ｎｍ以下であることから、当該微小な結晶をナノ結晶ともいう。また、ｎｃ−ＯＳは、異なるナノ結晶間で結晶方位に規則性が見られない。そのため、膜全体で配向性が見られない。したがって、ｎｃ−ＯＳは、分析方法によっては、ａ−ｌｉｋｅ　ＯＳおよび非晶質酸化物半導体と区別が付かない場合がある。例えば、ｎｃ−ＯＳ膜に対し、ＸＲＤ装置を用いて構造解析を行うと、θ／２θスキャンを用いたＯｕｔ−ｏｆ−ｐｌａｎｅ　ＸＲＤ測定では、結晶性を示すピークが検出されない。また、ｎｃ−ＯＳ膜に対し、ナノ結晶よりも大きいプローブ径（例えば５０ｎｍ以上）の電子線を用いる電子線回折（制限視野電子線回折ともいう。）を行うと、ハローパターンのような回折パターンが観測される。一方、ｎｃ−ＯＳ膜に対し、ナノ結晶の大きさと近いかナノ結晶より小さいプローブ径（例えば１ｎｍ以上３０ｎｍ以下）の電子線を用いる電子線回折（ナノビーム電子線回折ともいう。）を行うと、ダイレクトスポットを中心とするリング状の領域内に複数のスポットが観測される電子線回折パターンが取得される場合がある。 [nc-OS]
The nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In other words, the nc-OS has minute crystals. In addition, since the size of the microcrystal is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the microcrystal is also referred to as a nanocrystal. Further, in nc-OS, no regularity is observed in crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be indistinguishable from a-like OS and amorphous oxide semiconductor. For example, when an nc-OS film is subjected to structural analysis using an XRD device, no peak indicating crystallinity is detected in out-of-plane XRD measurement using a θ/2θ scan. Furthermore, when electron diffraction (also called selected area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystals (for example, 50 nm or more) is performed on the nc-OS film, a halo-like diffraction pattern is observed. is observed. On the other hand, when an nc-OS film is subjected to electron beam diffraction (also referred to as nanobeam electron diffraction) using an electron beam with a probe diameter that is close to the size of a nanocrystal or smaller than a nanocrystal (for example, from 1 nm to 30 nm), An electron diffraction pattern in which a plurality of spots are observed within a ring-shaped region centered on a direct spot may be obtained.
［ａ−ｌｉｋｅ　ＯＳ］
ａ−ｌｉｋｅ　ＯＳは、ｎｃ−ＯＳと非晶質酸化物半導体との間の構造を有する酸化物半導体である。ａ−ｌｉｋｅ　ＯＳは、鬆または低密度領域を有する。即ち、ａ−ｌｉｋｅ　ＯＳは、ｎｃ−ＯＳおよびＣＡＡＣ−ＯＳと比べて、結晶性が低い。また、ａ−ｌｉｋｅ　ＯＳは、ｎｃ−ＯＳおよびＣＡＡＣ−ＯＳと比べて、膜中の水素濃度が高い。 [a-like OS]
The a-like OS is an oxide semiconductor having a structure between that of an nc-OS and an amorphous oxide semiconductor. A-like OS has holes or low density areas. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and the CAAC-OS.
［酸化物半導体の構成］
次に、上述のＣＡＣ−ＯＳの詳細について、説明を行う。なお、ＣＡＣ−ＯＳは材料構成に関する。 [Structure of oxide semiconductor]
Next, details of the above-mentioned CAC-OS will be explained. Note that CAC-OS relates to material composition.
［ＣＡＣ−ＯＳ］
ＣＡＣ−ＯＳとは、例えば、金属酸化物を構成する元素が、０．５ｎｍ以上１０ｎｍ以下、好ましくは、１ｎｍ以上３ｎｍ以下、またはその近傍のサイズで偏在した材料の一構成である。なお、以下では、金属酸化物において、一つまたは複数の金属元素が偏在し、該金属元素を有する領域が、０．５ｎｍ以上１０ｎｍ以下、好ましくは、１ｎｍ以上３ｎｍ以下、またはその近傍のサイズで混合した状態をモザイク状、またはパッチ状ともいう。 [CAC-OS]
CAC-OS is, for example, a structure of a material in which elements constituting a metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof. In addition, in the following, in the metal oxide, one or more metal elements are unevenly distributed, and the region having the metal element has a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or a size in the vicinity thereof. The mixed state is also called a mosaic or a patch.
さらに、ＣＡＣ−ＯＳとは、第１の領域と、第２の領域と、に材料が分離することでモザイク状となり、当該第１の領域が、膜中に分布した構成（以下、クラウド状ともいう。）である。つまり、ＣＡＣ−ＯＳは、当該第１の領域と、当該第２の領域とが、混合している構成を有する複合金属酸化物である。 Furthermore, CAC-OS has a structure in which the material is separated into a first region and a second region, resulting in a mosaic shape, and the first region is distributed throughout the film (hereinafter also referred to as cloud shape). ). That is, CAC-OS is a composite metal oxide having a configuration in which the first region and the second region are mixed.
ここで、Ｉｎ−Ｇａ−Ｚｎ酸化物におけるＣＡＣ−ＯＳを構成する金属元素に対するＩｎ、Ｇａ、およびＺｎの原子数比のそれぞれを、［Ｉｎ］、［Ｇａ］、および［Ｚｎ］と表記する。例えば、Ｉｎ−Ｇａ−Ｚｎ酸化物におけるＣＡＣ−ＯＳにおいて、第１の領域は、［Ｉｎ］が、ＣＡＣ−ＯＳ膜の組成における［Ｉｎ］よりも大きい領域である。また、第２の領域は、［Ｇａ］が、ＣＡＣ−ＯＳ膜の組成における［Ｇａ］よりも大きい領域である。または、例えば、第１の領域は、［Ｉｎ］が、第２の領域における［Ｉｎ］よりも大きく、且つ、［Ｇａ］が、第２の領域における［Ｇａ］よりも小さい領域である。また、第２の領域は、［Ｇａ］が、第１の領域における［Ｇａ］よりも大きく、且つ、［Ｉｎ］が、第１の領域における［Ｉｎ］よりも小さい領域である。 Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are expressed as [In], [Ga], and [Zn], respectively. For example, in a CAC-OS made of In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. Further, the second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Or, for example, in the first region, [In] is larger than [In] in the second region, and [Ga] is smaller than [Ga] in the second region. Further, the second region is a region in which [Ga] is larger than [Ga] in the first region, and [In] is smaller than [In] in the first region.
具体的には、上記第１の領域は、インジウム酸化物、インジウム亜鉛酸化物等が主成分である領域である。また、上記第２の領域は、ガリウム酸化物、ガリウム亜鉛酸化物等が主成分である領域である。つまり、上記第１の領域を、Ｉｎを主成分とする領域と言い換えることができる。また、上記第２の領域を、Ｇａを主成分とする領域と言い換えることができる。 Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. Further, the second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region containing In as a main component. Further, the second region can be rephrased as a region containing Ga as a main component.
なお、上記第１の領域と、上記第２の領域とは、明確な境界が観察できない場合がある。 Note that a clear boundary may not be observed between the first region and the second region.
また、Ｉｎ−Ｇａ−Ｚｎ酸化物におけるＣＡＣ−ＯＳとは、Ｉｎ、Ｇａ、Ｚｎ、およびＯを含む材料構成において、一部にＧａを主成分とする領域と、一部にＩｎを主成分とする領域とが、それぞれモザイク状であり、これらの領域がランダムに存在している構成をいう。よって、ＣＡＣ−ＯＳは、金属元素が不均一に分布した構造を有していると推測される。 In addition, CAC-OS in In-Ga-Zn oxide is a material composition containing In, Ga, Zn, and O, with a region mainly composed of Ga and a region mainly composed of In. Each area has a mosaic shape, and these areas exist randomly. Therefore, it is presumed that CAC-OS has a structure in which metal elements are unevenly distributed.
ＣＡＣ−ＯＳは、例えば基板を意図的に加熱しない条件で、スパッタリング法により形成することができる。また、ＣＡＣ−ＯＳをスパッタリング法で形成する場合、成膜ガスとして、不活性ガス（代表的にはアルゴン）、酸素ガス、および窒素ガスの中から選ばれたいずれか一つまたは複数を用いればよい。また、成膜時の成膜ガスの総流量に対する酸素ガスの流量比は低いほど好ましい。例えば、成膜時の成膜ガスの総流量に対する酸素ガスの流量比を０％以上３０％未満、好ましくは０％以上１０％以下とする。 The CAC-OS can be formed, for example, by sputtering without intentionally heating the substrate. In addition, when forming the CAC-OS by sputtering, one or more selected from inert gas (typically argon), oxygen gas, and nitrogen gas may be used as the film-forming gas. good. Furthermore, the lower the flow rate ratio of oxygen gas to the total flow rate of film-forming gas during film formation, the more preferable it is. For example, the flow rate ratio of oxygen gas to the total flow rate of film forming gas during film formation is set to 0% or more and less than 30%, preferably 0% or more and 10% or less.
また、例えば、Ｉｎ−Ｇａ−Ｚｎ酸化物におけるＣＡＣ−ＯＳでは、エネルギー分散型Ｘ線分光法（ＥＤＸ：Ｅｎｅｒｇｙ　Ｄｉｓｐｅｒｓｉｖｅ　Ｘ−ｒａｙ　ｓｐｅｃｔｒｏｓｃｏｐｙ）を用いて取得したＥＤＸマッピングにより、Ｉｎを主成分とする領域（第１の領域）と、Ｇａを主成分とする領域（第２の領域）とが、偏在し、混合している構造を有することが確認できる。 In addition, for example, in CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) reveals regions mainly composed of In. It can be confirmed that the structure has a structure in which the (first region) and the region (second region) whose main component is Ga are unevenly distributed and mixed.
ここで、第１の領域は、第２の領域と比較して、導電性が高い領域である。つまり、第１の領域を、キャリアが流れることにより、金属酸化物としての導電性が発現する。従って、第１の領域が、金属酸化物中にクラウド状に分布することで、高い電界効果移動度（μ）が実現できる。 Here, the first region is a region with higher conductivity than the second region. In other words, carriers flow through the first region, thereby exhibiting conductivity as a metal oxide. Therefore, by distributing the first region in a cloud shape in the metal oxide, high field effect mobility (μ) can be achieved.
一方、第２の領域は、第１の領域と比較して、絶縁性が高い領域である。つまり、第２の領域が、金属酸化物中に分布することで、リーク電流を抑制することができる。 On the other hand, the second region is a region with higher insulation than the first region. That is, by distributing the second region in the metal oxide, leakage current can be suppressed.
したがって、ＣＡＣ−ＯＳをトランジスタに用いる場合、第１の領域に起因する導電性と、第２の領域に起因する絶縁性とが、相補的に作用することにより、スイッチングさせる機能（Ｏｎ／Ｏｆｆさせる機能）をＣＡＣ−ＯＳに付与することができる。つまり、ＣＡＣ−ＯＳとは、材料の一部では導電性の機能と、材料の一部では絶縁性の機能とを有し、材料の全体では半導体としての機能を有する。導電性の機能と絶縁性の機能とを分離させることで、双方の機能を最大限に高めることができる。よって、ＣＡＣ−ＯＳをトランジスタに用いることで、高いオン電流（Ｉｏｎ）、高い電界効果移動度（μ）、および良好なスイッチング動作を実現することができる。 Therefore, when CAC-OS is used in a transistor, the conductivity caused by the first region and the insulation caused by the second region act complementary to each other, thereby providing a switching function (on/off). functions) can be added to CAC-OS. In other words, in CAC-OS, a part of the material has a conductive function, a part of the material has an insulating function, and the entire material has a semiconductor function. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, high on-current (I on ), high field-effect mobility (μ), and good switching operation can be achieved.
また、ＣＡＣ−ＯＳを用いたトランジスタは、信頼性が高い。従って、ＣＡＣ−ＯＳは、表示装置をはじめとするさまざまな半導体装置に最適である。 Furthermore, transistors using CAC-OS have high reliability. Therefore, CAC-OS is optimal for various semiconductor devices including display devices.
酸化物半導体は、多様な構造をとり、それぞれが異なる特性を有する。本発明の一態様の酸化物半導体は、非晶質酸化物半導体、多結晶酸化物半導体、ａ−ｌｉｋｅ　ＯＳ、ＣＡＣ−ＯＳ、ｎｃ−ＯＳ、ＣＡＡＣ−ＯＳのうち、二種以上を有していてもよい。 Oxide semiconductors have a variety of structures, each with different properties. The oxide semiconductor of one embodiment of the present invention includes two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS. It's okay.
＜ＯＳトランジスタ＞
本発明の一態様の金属酸化物（酸化物半導体）をトランジスタに用いることで、高い電界効果移動度のトランジスタを実現できる。また、信頼性の高いトランジスタを実現できる。また、微細化または高集積化されたトランジスタを実現できる。例えば、チャネル長が２ｎｍ以上３０ｎｍ以下のトランジスタを作製しうる。 <OS transistor>
By using the metal oxide (oxide semiconductor) of one embodiment of the present invention for a transistor, a transistor with high field-effect mobility can be achieved. Furthermore, a highly reliable transistor can be realized. Further, it is possible to realize miniaturized or highly integrated transistors. For example, a transistor with a channel length of 2 nm or more and 30 nm or less can be manufactured.
トランジスタのチャネル形成領域には、キャリア濃度の低い酸化物半導体を用いることが好ましい。例えば、酸化物半導体のチャネル形成領域のキャリア濃度は１×１０１８ｃｍ−３以下、好ましくは１×１０１７ｃｍ−３以下、より好ましくは１×１０１５ｃｍ−３以下、より好ましくは１×１０１３ｃｍ−３以下、より好ましくは１×１０１１ｃｍ−３以下、さらに好ましくは１×１０１０ｃｍ−３未満であり、１×１０−９ｃｍ−３以上である。なお、酸化物半導体膜のキャリア濃度を低くする場合においては、酸化物半導体膜中の不純物濃度を低くし、欠陥準位密度を低くすればよい。本明細書等において、不純物濃度が低く、欠陥準位密度の低いことを高純度真性または実質的に高純度真性と言う。なお、キャリア濃度の低い酸化物半導体を、高純度真性または実質的に高純度真性な酸化物半導体と呼ぶ場合がある。 It is preferable to use an oxide semiconductor with a low carrier concentration for a channel formation region of a transistor. For example, the carrier concentration in the channel formation region of the oxide semiconductor is 1×10 18 cm −3 or less, preferably 1×10 17 cm −3 or less, more preferably 1×10 15 cm −3 or less, more preferably 1× It is 1013 cm -3 or less, more preferably 1x1011 cm -3 or less, even more preferably less than 1x1010 cm- 3 , and 1x10-9 cm- 3 or more. Note that in the case of lowering the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be lowered to lower the defect level density. In this specification and the like, low impurity concentration and low defect level density are referred to as high purity intrinsic or substantially high purity intrinsic. Note that an oxide semiconductor with a low carrier concentration is sometimes referred to as a high-purity intrinsic oxide semiconductor or a substantially high-purity intrinsic oxide semiconductor.
また、高純度真性または実質的に高純度真性である酸化物半導体膜は、欠陥準位密度が低いため、トラップ準位密度も低くなる場合がある。 Further, since a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has a low defect level density, the trap level density may also be low.
また、酸化物半導体のトラップ準位に捕獲された電荷は、消失するまでに要する時間が長く、あたかも固定電荷のように振る舞うことがある。そのため、トラップ準位密度の高い酸化物半導体にチャネル形成領域が形成されるトランジスタは、電気特性が不安定となる場合がある。 In addition, charges captured in trap levels of an oxide semiconductor may take a long time to disappear, and may behave as if they were fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap level density may have unstable electrical characteristics.
従って、トランジスタの電気特性を安定にするためには、酸化物半導体中の不純物濃度を低減することが有効である。また、酸化物半導体中の不純物濃度を低減するためには、近接する膜中の不純物濃度も低減することが好ましい。不純物としては、水素、炭素、窒素などが挙げられる。なお、酸化物半導体中の不純物とは、例えば、酸化物半導体を構成する主成分以外をいう。例えば、濃度が０．１ａｔｏｍｉｃ％未満の元素は不純物といえる。 Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Further, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in an adjacent film. Examples of impurities include hydrogen, carbon, and nitrogen. Note that the impurity in the oxide semiconductor refers to, for example, a substance other than the main component that constitutes the oxide semiconductor. For example, an element having a concentration of less than 0.1 atomic% can be considered an impurity.
また、酸化物半導体のバンドギャップは、シリコンのバンドギャップ（代表的には１．１ｅＶ）よりも大きいことが好ましく、好ましくは２ｅＶ以上、より好ましくは２．５ｅＶ以上、さらに好ましくは３．０ｅＶ以上である。シリコンよりも、バンドギャップの大きい酸化物半導体を用いることで、トランジスタのオフ電流（Ｉｏｆｆとも呼称する）を低減できる。 Further, the band gap of the oxide semiconductor is preferably larger than the band gap of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and even more preferably 3.0 eV or more. It is. By using an oxide semiconductor having a larger band gap than silicon, the off-state current (also referred to as Ioff) of the transistor can be reduced.
また、Ｓｉトランジスタ（チャネルが形成される半導体層にシリコンを用いたトランジスタ）では、トランジスタの微細化が進むにつれて、短チャネル効果（ショートチャネル効果：Ｓｈｏｒｔ　Ｃｈａｎｎｅｌ　Ｅｆｆｅｃｔ：ＳＣＥともいう）が発現する。そのため、Ｓｉトランジスタでは、微細化が困難となる。短チャネル効果が発現する要因の一つとして、シリコンのバンドギャップが小さいことが挙げられる。一方、ＯＳトランジスタは、バンドギャップの大きい半導体材料である、酸化物半導体を用いるため、短チャネル効果の抑制を図ることができる。別言すると、ＯＳトランジスタは、短チャネル効果がない、または短チャネル効果が極めて少ないトランジスタである。 Further, in Si transistors (transistors in which silicon is used as a semiconductor layer in which a channel is formed), as transistors become smaller, a short channel effect (also referred to as SCE) occurs. Therefore, it is difficult to miniaturize Si transistors. One of the reasons for the short channel effect is that silicon has a small band gap. On the other hand, since an OS transistor uses an oxide semiconductor, which is a semiconductor material with a large band gap, short channel effects can be suppressed. In other words, an OS transistor is a transistor that has no short channel effect or has very little short channel effect.
なお、短チャネル効果とは、トランジスタの微細化（チャネル長の縮小）に伴って顕在化する電気特性の劣化である。短チャネル効果の具体例としては、しきい値電圧の低下、サブスレッショルドスイング値（Ｓ値と表記することがある）の増大、漏れ電流の増大などがある。ここで、Ｓ値とは、ドレイン電圧一定にてドレイン電流を１桁変化させるサブスレッショルド領域でのゲート電圧の変化量をいう。 Note that the short channel effect is a deterioration in electrical characteristics that becomes apparent as transistors become smaller (reduction in channel length). Specific examples of short channel effects include a decrease in threshold voltage, an increase in subthreshold swing value (sometimes referred to as S value), and an increase in leakage current. Here, the S value refers to the amount of change in gate voltage in a subthreshold region that causes a drain current to change by one order of magnitude with a constant drain voltage.
また、短チャネル効果に対する耐性の指標として、特性長（Ｃｈａｒａｃｔｅｒｉｓｔｉｃ　Ｌｅｎｇｔｈ）が広く用いられている。特性長とは、チャネル形成領域のポテンシャルの曲がりやすさの指標である。特性長が小さいほどポテンシャルが急峻に立ち上がるため、短チャネル効果に強いといえる。 Further, characteristic length is widely used as an index of resistance to short channel effects. The characteristic length is an index of the bendability of the potential in the channel forming region. The smaller the characteristic length, the more steeply the potential rises, so it can be said to be resistant to short channel effects.
ＯＳトランジスタは蓄積型のトランジスタであり、Ｓｉトランジスタは反転型のトランジスタである。したがって、Ｓｉトランジスタと比較して、ＯＳトランジスタは、ソース領域−チャネル形成領域間の特性長、及びドレイン領域−チャネル形成領域間の特性長が小さい。したがって、ＯＳトランジスタは、Ｓｉトランジスタよりも短チャネル効果に強い。すなわち、チャネル長の短いトランジスタを作製したい場合においては、ＯＳトランジスタは、Ｓｉトランジスタよりも好適である。 The OS transistor is an accumulation type transistor, and the Si transistor is an inversion type transistor. Therefore, compared to a Si transistor, an OS transistor has a smaller characteristic length between the source region and the channel forming region and a smaller characteristic length between the drain region and the channel forming region. Therefore, OS transistors are more resistant to short channel effects than Si transistors. That is, when it is desired to manufacture a transistor with a short channel length, an OS transistor is more suitable than a Si transistor.
チャネル形成領域がｉ型または実質的にｉ型となるまで、酸化物半導体のキャリア濃度を下げた場合においても、短チャネルのトランジスタではＣｏｎｄｕｃｔｉｏｎ−Ｂａｎｄ−Ｌｏｗｅｒｉｎｇ（ＣＢＬ）効果により、チャネル形成領域の伝導帯下端が下がるため、ソース領域またはドレイン領域と、チャネル形成領域との間の伝導帯下端のエネルギー差は、０．１ｅＶ以上０．２ｅＶ以下まで小さくなる可能性がある。これにより、ＯＳトランジスタは、チャネル形成領域がｎ−型の領域となり、ソース領域及びドレイン領域がｎ＋型の領域となる、ｎ＋／ｎ−／ｎ＋の蓄積型ｊｕｎｃｔｉｏｎ−ｌｅｓｓトランジスタ構造、または、ｎ＋／ｎ−／ｎ＋の蓄積型ｎｏｎ−ｊｕｎｃｔｉｏｎトランジスタ構造と、捉えることもできる。 Even when the carrier concentration of the oxide semiconductor is lowered until the channel formation region becomes i-type or substantially i-type, conduction in the channel formation region decreases due to the conduction-band-lowering (CBL) effect in short-channel transistors. Since the lower end of the conduction band is lowered, the energy difference at the lower end of the conduction band between the source region or the drain region and the channel formation region may be reduced to 0.1 eV or more and 0.2 eV or less. As a result, the OS transistor has an n + /n- / n + accumulation type junction-less transistor structure, in which the channel forming region becomes an n - type region and the source and drain regions become n + -type regions, or , n + /n − /n + storage type non-junction transistor structure.
ＯＳトランジスタを、上記の構造とすることで、半導体装置を微細化または高集積化しても良好な電気特性を有することができる。例えば、ＯＳトランジスタのチャネル長又はゲート長が、２０ｎｍ以下、１５ｎｍ以下、１０ｎｍ以下、７ｎｍ以下、または６ｎｍ以下であって、１ｎｍ以上、３ｎｍ以上、または５ｎｍ以上であっても、良好な電気特性を得ることができる。一方で、Ｓｉトランジスタは、短チャネル効果が発現するため、２０ｎｍ以下、または１５ｎｍ以下のゲート長とすることが困難な場合がある。したがって、ＯＳトランジスタは、Ｓｉトランジスタと比較してチャネル長の短いトランジスタに好適に用いることができる。なお、ゲート長とは、トランジスタ動作時にキャリアがチャネル形成領域内部を移動する方向における、ゲート電極の長さである。 By making the OS transistor have the above structure, it is possible to have good electrical characteristics even if the semiconductor device is miniaturized or highly integrated. For example, even if the channel length or gate length of an OS transistor is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less, and it is 1 nm or more, 3 nm or more, or 5 nm or more, good electrical characteristics can be obtained. Obtainable. On the other hand, since a short channel effect occurs in a Si transistor, it may be difficult to set the gate length to 20 nm or less or 15 nm or less. Therefore, the OS transistor can be suitably used as a transistor having a shorter channel length than a Si transistor. Note that the gate length is the length of the gate electrode in the direction in which carriers move inside the channel formation region during transistor operation.
また、ＯＳトランジスタを微細化することで、トランジスタの高周波特性を向上させることができる。具体的には、トランジスタの遮断周波数を向上させることができる。ＯＳトランジスタのゲート長が上記範囲のいずれかである場合、トランジスタの遮断周波数を、例えば室温環境下で、５０ＧＨｚ以上、好ましくは１００ＧＨｚ以上、さらに好ましくは１５０ＧＨｚ以上とすることができる。 Further, by miniaturizing the OS transistor, the high frequency characteristics of the transistor can be improved. Specifically, the cutoff frequency of the transistor can be improved. When the gate length of the OS transistor is within any of the above ranges, the cutoff frequency of the transistor can be set to 50 GHz or more, preferably 100 GHz or more, more preferably 150 GHz or more, for example in a room temperature environment.
以上の説明の通り、ＯＳトランジスタは、Ｓｉトランジスタと比較し、オフ電流が小さいこと、チャネル長の短いトランジスタの作製が可能なこと、といった優れた効果を有する。 As described above, OS transistors have excellent effects compared to Si transistors, such as a smaller off-state current and the ability to manufacture a transistor with a short channel length.
＜ＯＳ中の不純物＞
ここで、金属酸化物（酸化物半導体）中における各不純物の影響について説明する。 <Impurities in the OS>
Here, the influence of each impurity in the metal oxide (oxide semiconductor) will be explained.
酸化物半導体において、第１４族元素の一つであるシリコンまたは炭素が含まれると、酸化物半導体において欠陥準位が形成される。このため、ＳＩＭＳにより得られる酸化物半導体のチャネル形成領域における炭素の濃度は、１×１０２０ａｔｏｍｓ／ｃｍ３以下、好ましくは５×１０１９ａｔｏｍｓ／ｃｍ３以下、より好ましくは３×１０１９ａｔｏｍｓ／ｃｍ３以下、より好ましくは１×１０１９ａｔｏｍｓ／ｃｍ３以下、より好ましくは３×１０１８ａｔｏｍｓ／ｃｍ３以下、さらに好ましくは１×１０１８ａｔｏｍｓ／ｃｍ３以下とする。また、ＳＩＭＳにより得られる酸化物半導体のチャネル形成領域におけるシリコンの濃度は、１×１０２０ａｔｏｍｓ／ｃｍ３以下、好ましくは５×１０１９ａｔｏｍｓ／ｃｍ３以下、より好ましくは３×１０１９ａｔｏｍｓ／ｃｍ３以下、より好ましくは１×１０１９ａｔｏｍｓ／ｃｍ３以下、より好ましくは３×１０１８ａｔｏｍｓ／ｃｍ３以下、さらに好ましくは１×１０１８ａｔｏｍｓ／ｃｍ３以下とする。 When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 20 atoms/cm 3 or less, preferably 5×10 19 atoms/cm 3 or less, more preferably 3×10 19 atoms /cm 3 or less, more preferably 1×10 19 atoms/cm 3 or less, more preferably 3×10 18 atoms/cm 3 or less, even more preferably 1×10 18 atoms/cm 3 or less. Further, the silicon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 20 atoms/cm 3 or less, preferably 5×10 19 atoms/cm 3 or less, and more preferably 3×10 19 atoms/cm 3 or less. cm 3 or less, more preferably 1×10 19 atoms/cm 3 or less, more preferably 3×10 18 atoms/cm 3 or less, even more preferably 1×10 18 atoms/cm 3 or less.
また、酸化物半導体において、窒素が含まれると、キャリアである電子が生じ、キャリア濃度が増加し、ｎ型化しやすい。この結果、窒素が含まれている酸化物半導体を半導体に用いたトランジスタはノーマリーオン特性となりやすい。または、酸化物半導体において、窒素が含まれると、トラップ準位が形成される場合がある。この結果、トランジスタの電気特性が不安定となる場合がある。このため、ＳＩＭＳにより得られる酸化物半導体のチャネル形成領域における窒素濃度は、１×１０２０ａｔｏｍｓ／ｃｍ３以下、好ましくは５×１０１９ａｔｏｍｓ／ｃｍ３以下、より好ましくは１×１０１９ａｔｏｍｓ／ｃｍ３以下、より好ましくは５×１０１８ａｔｏｍｓ／ｃｍ３以下、より好ましくは１×１０１８ａｔｏｍｓ／ｃｍ３以下、さらに好ましくは５×１０１７ａｔｏｍｓ／ｃｍ３以下とする。 Further, when nitrogen is contained in an oxide semiconductor, electrons as carriers are generated, the carrier concentration increases, and the semiconductor becomes n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when an oxide semiconductor contains nitrogen, a trap level may be formed in some cases. As a result, the electrical characteristics of the transistor may become unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 20 atoms/cm 3 or less, preferably 5×10 19 atoms/cm 3 or less, and more preferably 1×10 19 atoms/cm 3 or less. cm 3 or less, more preferably 5×10 18 atoms/cm 3 or less, more preferably 1×10 18 atoms/cm 3 or less, still more preferably 5×10 17 atoms/cm 3 or less.
また、酸化物半導体に含まれる水素は、金属原子と結合する酸素と反応して水になるため、酸素欠損を形成する場合がある。該酸素欠損に水素が入ることで、キャリアである電子が生成される場合がある。また、水素の一部が金属原子と結合する酸素と結合して、キャリアである電子を生成することがある。従って、水素が含まれている酸化物半導体を用いたトランジスタはノーマリーオン特性となりやすい。このため、酸化物半導体のチャネル形成領域における中の水素はできる限り低減されていることが好ましい。具体的には、ＳＩＭＳにより得られる酸化物半導体のチャネル形成領域における水素濃度は、１×１０２０ａｔｏｍｓ／ｃｍ３未満、好ましくは５×１０１９ａｔｏｍｓ／ｃｍ３未満、より好ましくは１×１０１９ａｔｏｍｓ／ｃｍ３未満、より好ましくは５×１０１８ａｔｏｍｓ／ｃｍ３未満、さらに好ましくは１×１０１８ａｔｏｍｓ／ｃｍ３未満とする。 Furthermore, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to become water, which may result in the formation of oxygen vacancies. When hydrogen enters the oxygen vacancies, electrons, which are carriers, may be generated. Further, a portion of hydrogen may combine with oxygen that is bonded to a metal atom to generate electrons, which are carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. Therefore, it is preferable that hydrogen in the channel formation region of the oxide semiconductor be reduced as much as possible. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is less than 1×10 20 atoms/cm 3 , preferably less than 5×10 19 atoms/cm 3 , more preferably 1×10 19 atoms/cm 3 , more preferably less than 5×10 18 atoms/cm 3 , even more preferably less than 1×10 18 atoms/cm 3 .
また、酸化物半導体にアルカリ金属またはアルカリ土類金属が含まれると、欠陥準位を形成し、キャリアを生成する場合がある。従って、アルカリ金属またはアルカリ土類金属が含まれている酸化物半導体を用いたトランジスタはノーマリーオン特性となりやすい。このため、ＳＩＭＳにより得られる酸化物半導体のチャネル形成領域中のアルカリ金属またはアルカリ土類金属の濃度を、１×１０１８ａｔｏｍｓ／ｃｍ３以下、好ましくは２×１０１６ａｔｏｍｓ／ｃｍ３以下にする。 Further, when an alkali metal or an alkaline earth metal is contained in the oxide semiconductor, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have normally-on characteristics. Therefore, the concentration of alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms/cm 3 or less, preferably 2×10 16 atoms/cm 3 or less. .
不純物が十分に低減された酸化物半導体をトランジスタのチャネル形成領域に用いることで、安定した電気特性を付与することができる。 By using an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be provided.
本実施の形態は、本明細書で示す他の実施の形態などと適宜組み合わせることができる。 This embodiment mode can be combined with other embodiment modes shown in this specification as appropriate.
（実施の形態４）
本実施の形態では、図１９Ａおよび図１９Ｂを用いて、本発明の半導体装置が実装されたチップ１２００の一例を示す。チップ１２００には、複数の回路（システム）が実装されている。このように、複数の回路（システム）を一つのチップに集積する技術を、システムオンチップ（Ｓｙｓｔｅｍ　ｏｎ　Ｃｈｉｐ：ＳｏＣ）と呼ぶ場合がある。 (Embodiment 4)
In this embodiment, an example of a chip 1200 on which a semiconductor device of the present invention is mounted is shown using FIGS. 19A and 19B. A plurality of circuits (systems) are mounted on the chip 1200. The technology of integrating a plurality of circuits (systems) onto one chip in this way is sometimes called system on chip (SoC).
　図１９Ａに示すように、チップ１２００は、ＣＰＵ１２１１、ＧＰＵ１２１２、一または複数のアナログ演算部１２１３、一または複数のメモリコントローラ１２１４、一または複数のインターフェース１２１５、一または複数のネットワーク回路１２１６等を有する。 As shown in FIG. 19A, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog calculation units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.
チップ１２００には、バンプ（図示しない）が設けられ、図１９Ｂに示すように、パッケージ基板１２０１の第１の面と接続する。また、パッケージ基板１２０１の第１の面の裏面には、複数のバンプ１２０２が設けられており、マザーボード１２０３と接続する。 The chip 1200 is provided with bumps (not shown) and is connected to the first surface of the package substrate 1201, as shown in FIG. 19B. Furthermore, a plurality of bumps 1202 are provided on the back surface of the first surface of the package substrate 1201 and are connected to a motherboard 1203.
マザーボード１２０３には、記憶装置１２２１、フラッシュメモリ１２２２等の記憶装置が設けられていてもよい。例えば、記憶装置１２２１に半導体装置１０を用いることができる。また、例えば、フラッシュメモリ１２２２に替えて半導体装置１０を用いてもよい。 The motherboard 1203 may be provided with storage devices such as a storage device 1221 and a flash memory 1222. For example, the semiconductor device 10 can be used as the storage device 1221. Further, for example, the semiconductor device 10 may be used instead of the flash memory 1222.
ＣＰＵ１２１１は、複数のＣＰＵコアを有することが好ましい。また、ＧＰＵ１２１２は、複数のＧＰＵコアを有することが好ましい。また、ＣＰＵ１２１１、およびＧＰＵ１２１２は、それぞれ一時的にデータを格納するメモリを有していてもよい。または、ＣＰＵ１２１１、およびＧＰＵ１２１２に共通のメモリが、チップ１２００に設けられていてもよい。該メモリには、半導体装置１０を用いることができる。また、ＧＰＵ１２１２は、多数のデータの並列計算に適しており、画像処理または積和演算に用いることができる。ＧＰＵ１２１２に、酸化物半導体を用いた画像処理回路または、積和演算回路を設けることで、画像処理、および積和演算を低消費電力で実行することが可能になる。 Preferably, the CPU 1211 has multiple CPU cores. Further, it is preferable that the GPU 1212 has a plurality of GPU cores. Further, the CPU 1211 and the GPU 1212 may each have a memory that temporarily stores data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200. The semiconductor device 10 can be used for the memory. Further, the GPU 1212 is suitable for parallel calculation of a large amount of data, and can be used for image processing or product-sum calculation. By providing the GPU 1212 with an image processing circuit using an oxide semiconductor or a product-sum calculation circuit, image processing and product-sum calculation can be performed with low power consumption.
また、ＣＰＵ１２１１、およびＧＰＵ１２１２が同一チップに設けられていることで、ＣＰＵ１２１１とＧＰＵ１２１２の間の配線を短くすることができ、ＣＰＵ１２１１からＧＰＵ１２１２へのデータ転送、ＣＰＵ１２１１、およびＧＰＵ１２１２が有するメモリ間のデータ転送、およびＧＰＵ１２１２での演算後に、ＧＰＵ１２１２からＣＰＵ１２１１への演算結果の転送を高速に行うことができる。 In addition, since the CPU 1211 and the GPU 1212 are provided on the same chip, the wiring between the CPU 1211 and the GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212 and between the memory of the CPU 1211 and the GPU 1212 is possible. , and after the calculation by the GPU 1212, the calculation result can be transferred from the GPU 1212 to the CPU 1211 at high speed.
アナログ演算部１２１３はＡ／Ｄ（アナログ／デジタル）変換回路、およびＤ／Ａ（デジタル／アナログ）変換回路の一、または両方を有する。また、アナログ演算部１２１３に上記積和演算回路を設けてもよい。 The analog calculation unit 1213 has one or both of an A/D (analog/digital) conversion circuit and a D/A (digital/analog) conversion circuit. Further, the analog calculation section 1213 may be provided with the above product-sum calculation circuit.
メモリコントローラ１２１４は、記憶装置１２２１のコントローラとして機能する回路、およびフラッシュメモリ１２２２のインターフェースとして機能する回路を有する。 The memory controller 1214 includes a circuit that functions as a controller for the storage device 1221 and a circuit that functions as an interface for the flash memory 1222.
インターフェース１２１５は、表示装置、スピーカー、マイクロフォン、カメラ、コントローラなどの外部接続機器とのインターフェース回路を有する。コントローラとは、マウス、キーボード、ゲーム用コントローラなどを含む。このようなインターフェースとして、ＵＳＢ（Ｕｎｉｖｅｒｓａｌ　Ｓｅｒｉａｌ　Ｂｕｓ）、ＨＤＭＩ（登録商標）（Ｈｉｇｈ−Ｄｅｆｉｎｉｔｉｏｎ　Ｍｕｌｔｉｍｅｄｉａ　Ｉｎｔｅｒｆａｃｅ）などを用いることができる。 The interface 1215 has an interface circuit with externally connected devices such as a display device, speaker, microphone, camera, and controller. Controllers include mice, keyboards, game controllers, and the like. As such an interface, USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used.
ネットワーク回路１２１６は、ＬＡＮ（Ｌｏｃａｌ　Ａｒｅａ　Ｎｅｔｗｏｒｋ）などのネットワーク回路を有する。また、ネットワークセキュリティー用の回路を有してもよい。 The network circuit 1216 includes a network circuit such as a LAN (Local Area Network). It may also include a circuit for network security.
チップ１２００には、上記回路（システム）を同一の製造プロセスで形成することが可能である。そのため、チップ１２００に必要な回路の数が増えても、製造プロセスを増やす必要が無く、チップ１２００を低コストで作製することができる。 The above circuit (system) can be formed on the chip 1200 using the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.
ＧＰＵ１２１２を有するチップ１２００が設けられたパッケージ基板１２０１、記憶装置１２２１、およびフラッシュメモリ１２２２が設けられたマザーボード１２０３は、ＧＰＵモジュール１２０４と呼ぶことができる。 A package substrate 1201 provided with a chip 1200 having a GPU 1212, a motherboard 1203 provided with a storage device 1221, and a flash memory 1222 can be called a GPU module 1204.
ＧＰＵモジュール１２０４は、ＳｏＣ技術を用いたチップ１２００を有しているため、そのサイズを小さくすることができる。また、画像処理に優れていることから、スマートフォン、タブレット端末、ラップトップＰＣ、携帯型（持ち出し可能な）ゲーム機などの携帯型電子機器に用いることが好適である。また、ＧＰＵ１２１２を用いた積和演算回路により、ディープニューラルネットワーク（ＤＮＮ）、畳み込みニューラルネットワーク（ＣＮＮ）、再帰型ニューラルネットワーク（ＲＮＮ）、自己符号化器、深層ボルツマンマシン（ＤＢＭ）、深層信念ネットワーク（ＤＢＮ）などの手法を実行することができるため、チップ１２００をＡＩチップ、またはＧＰＵモジュール１２０４をＡＩシステムモジュールとして用いることができる。 Since the GPU module 1204 includes a chip 1200 using SoC technology, its size can be reduced. Furthermore, since it is excellent in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (portable) game machines. In addition, a product-sum calculation circuit using the GPU 1212 can be used to create deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks ( DBN), etc., the chip 1200 can be used as an AI chip or the GPU module 1204 can be used as an AI system module.
本実施の形態は、本明細書で示す他の実施の形態などと適宜組み合わせることができる。 This embodiment mode can be combined with other embodiment modes shown in this specification as appropriate.
（実施の形態５）
本実施の形態では、上記実施の形態に示す半導体装置などが組み込まれた電子部品の一例を示す。 (Embodiment 5)
This embodiment mode shows an example of an electronic component incorporating the semiconductor device described in the above embodiment mode.
＜電子部品＞
図２０Ａに電子部品７００および電子部品７００が実装された基板（実装基板７０４）の斜視図を示す。図２０Ａに示す電子部品７００は、モールド７１１内に記憶装置７２０を有している。図２０Ａは、電子部品７００の内部を示すために、一部を省略している。電子部品７００は、モールド７１１の外側にランド７１２を有する。ランド７１２は電極パッド７１３と電気的に接続され、電極パッド７１３は記憶装置７２０とワイヤ７１４によって電気的に接続されている。電子部品７００は、例えばプリント基板７０２に実装される。このような電子部品が複数組み合わされて、それぞれがプリント基板７０２上で電気的に接続されることで実装基板７０４が完成する。 <Electronic parts>
FIG. 20A shows a perspective view of an electronic component 700 and a board (mounted board 704) on which the electronic component 700 is mounted. The electronic component 700 shown in FIG. 20A includes a storage device 720 within a mold 711. In FIG. 20A, a part is omitted to show the inside of the electronic component 700. The electronic component 700 has a land 712 on the outside of the mold 711. Land 712 is electrically connected to electrode pad 713, and electrode pad 713 is electrically connected to memory device 720 by wire 714. The electronic component 700 is mounted on a printed circuit board 702, for example. A mounting board 704 is completed by combining a plurality of such electronic components and electrically connecting them on the printed circuit board 702.
　記憶装置７２０は、駆動回路層７２１と、記憶回路層７２２と、を有する。記憶装置７２０に本発明の一態様に係る記憶装置３００を用いることができる。よって、駆動回路層７２１は駆動回路２１を含む層ということができる。また、記憶回路層７２２に単層または複数層のメモリアレイ２０を用いることができる。よって、駆動回路層７２１はメモリアレイ２０を含む層ということができる。 The memory device 720 includes a drive circuit layer 721 and a memory circuit layer 722. The storage device 300 according to one embodiment of the present invention can be used as the storage device 720. Therefore, the drive circuit layer 721 can be said to be a layer including the drive circuit 21. Furthermore, a single-layer or multi-layer memory array 20 can be used for the memory circuit layer 722. Therefore, the drive circuit layer 721 can be said to be a layer that includes the memory array 20.
図２０Ｂに電子部品７３０の斜視図を示す。電子部品７３０は、ＳｉＰ（Ｓｙｓｔｅｍ　ｉｎ　ｐａｃｋａｇｅ）またはＭＣＭ（Ｍｕｌｔｉ　Ｃｈｉｐ　Ｍｏｄｕｌｅ）の一例である。電子部品７３０は、パッケージ基板７３２（プリント基板）上にインターポーザ７３１が設けられ、インターポーザ７３１上に半導体装置７３５、および複数の記憶装置７２０が設けられている。 FIG. 20B shows a perspective view of the electronic component 730. The electronic component 730 is an example of a SiP (System in package) or an MCM (Multi Chip Module). In the electronic component 730, an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of storage devices 720 are provided on the interposer 731.
電子部品７３０では、記憶装置７２０を広帯域メモリ（ＨＢＭ：Ｈｉｇｈ　Ｂａｎｄｗｉｄｔｈ　Ｍｅｍｏｒｙ）として用いる例を示している。また、半導体装置７３５は、ＣＰＵ、ＧＰＵ、ＦＰＧＡなどの集積回路（半導体装置）を用いることができる。 In the electronic component 730, an example is shown in which the storage device 720 is used as a high bandwidth memory (HBM). Further, as the semiconductor device 735, an integrated circuit (semiconductor device) such as a CPU, GPU, or FPGA can be used.
パッケージ基板７３２は、セラミックス基板、プラスチック基板、ガラスエポキシ基板などを用いることができる。インターポーザ７３１は、シリコンインターポーザ、樹脂インターポーザなどを用いることができる。 As the package substrate 732, a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used. As the interposer 731, a silicon interposer, a resin interposer, or the like can be used.
インターポーザ７３１は、複数の配線を有し、端子ピッチの異なる複数の集積回路を電気的に接続する機能を有する。複数の配線は、単層または多層で設けられる。また、インターポーザ７３１は、インターポーザ７３１上に設けられた集積回路をパッケージ基板７３２に設けられた電極と電気的に接続する機能を有する。これらのことから、インターポーザを「再配線基板」または「中間基板」と呼ぶ場合がある。また、インターポーザ７３１に貫通電極を設けて、当該貫通電極を用いて集積回路とパッケージ基板７３２を電気的に接続する場合もある。また、シリコンインターポーザでは、貫通電極として、ＴＳＶ（Ｔｈｒｏｕｇｈ　Ｓｉｌｉｃｏｎ　Ｖｉａ）を用いることも出来る。 The interposer 731 has a plurality of wiring lines and has a function of electrically connecting a plurality of integrated circuits having different terminal pitches. The plurality of wirings are provided in a single layer or in multiple layers. Further, the interposer 731 has a function of electrically connecting the integrated circuit provided on the interposer 731 to the electrodes provided on the package substrate 732. For these reasons, interposers are sometimes called "rewiring boards" or "intermediate boards." Further, in some cases, a through electrode is provided in the interposer 731, and the integrated circuit and the package substrate 732 are electrically connected using the through electrode. Further, in the silicon interposer, TSV (Through Silicon Via) can also be used as the through electrode.
インターポーザ７３１としてシリコンインターポーザを用いることが好ましい。シリコンインターポーザでは能動素子を設ける必要が無いため、集積回路よりも低コストで作製することができる。一方で、シリコンインターポーザの配線形成は半導体プロセスで行なうことができるため、樹脂インターポーザでは難しい微細配線の形成が容易である。 It is preferable to use a silicon interposer as the interposer 731. Since silicon interposers do not require active elements, they can be manufactured at lower cost than integrated circuits. On the other hand, since wiring formation in a silicon interposer can be performed by a semiconductor process, it is easy to form fine wiring, which is difficult to do with a resin interposer.
ＨＢＭでは、広いメモリバンド幅を実現するために多くの配線を接続する必要がある。このため、ＨＢＭを実装するインターポーザには、微細かつ高密度の配線形成が求められる。よって、ＨＢＭを実装するインターポーザには、シリコンインターポーザを用いることが好ましい。 In HBM, it is necessary to connect many wires to realize a wide memory bandwidth. For this reason, an interposer mounting an HBM is required to form fine and high-density wiring. Therefore, it is preferable to use a silicon interposer as the interposer for mounting the HBM.
また、シリコンインターポーザを用いたＳｉＰ、ＭＣＭなどでは、集積回路とインターポーザ間の膨張係数の違いによる信頼性の低下が生じにくい。また、シリコンインターポーザは表面の平坦性が高いため、シリコンインターポーザ上に設ける集積回路とシリコンインターポーザ間の接続不良が生じにくい。特に、インターポーザ上に複数の集積回路を横に並べて配置する２．５Ｄパッケージ（２．５次元実装）では、シリコンインターポーザを用いることが好ましい。 Further, in SiP, MCM, etc. using a silicon interposer, reliability is less likely to deteriorate due to a difference in expansion coefficient between the integrated circuit and the interposer. Furthermore, since the silicon interposer has a highly flat surface, poor connection between the integrated circuit provided on the silicon interposer and the silicon interposer is less likely to occur. In particular, it is preferable to use a silicon interposer in a 2.5D package (2.5-dimensional packaging) in which a plurality of integrated circuits are arranged side by side on an interposer.
また、電子部品７３０と重ねてヒートシンク（放熱板）を設けてもよい。ヒートシンクを設ける場合は、インターポーザ７３１上に設ける集積回路の高さを揃えることが好ましい。例えば、本実施の形態に示す電子部品７３０では、記憶装置７２０と半導体装置７３５の高さを揃えることが好ましい。 Further, a heat sink (heat sink) may be provided to overlap the electronic component 730. When a heat sink is provided, it is preferable that the heights of the integrated circuits provided on the interposer 731 are the same. For example, in the electronic component 730 shown in this embodiment, it is preferable that the storage device 720 and the semiconductor device 735 have the same height.
電子部品７３０を他の基板に実装するため、パッケージ基板７３２の底部に電極７３３を設けてもよい。図２０Ｂでは、電極７３３を半田ボールで形成する例を示している。パッケージ基板７３２の底部に半田ボールをマトリクス状に設けることで、ＢＧＡ（Ｂａｌｌ　Ｇｒｉｄ　Ａｒｒａｙ）実装を実現できる。また、電極７３３を導電性のピンで形成してもよい。パッケージ基板７３２の底部に導電性のピンをマトリクス状に設けることで、ＰＧＡ（Ｐｉｎ　Ｇｒｉｄ　Ａｒｒａｙ）実装を実現できる。 In order to mount the electronic component 730 on another substrate, an electrode 733 may be provided at the bottom of the package substrate 732. FIG. 20B shows an example in which the electrode 733 is formed with a solder ball. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be realized. Further, the electrode 733 may be formed of a conductive pin. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be realized.
電子部品７３０は、ＢＧＡおよびＰＧＡに限らず様々な実装方法を用いて他の基板に実装することができる。例えば、ＳＰＧＡ（Ｓｔａｇｇｅｒｅｄ　Ｐｉｎ　Ｇｒｉｄ　Ａｒｒａｙ）、ＬＧＡ（Ｌａｎｄ　Ｇｒｉｄ　Ａｒｒａｙ）、ＱＦＰ（Ｑｕａｄ　Ｆｌａｔ　Ｐａｃｋａｇｅ）、ＱＦＪ（Ｑｕａｄ　Ｆｌａｔ　Ｊ−ｌｅａｄｅｄ　ｐａｃｋａｇｅ）、またはＱＦＮ（Ｑｕａｄ　Ｆｌａｔ　Ｎｏｎ−ｌｅａｄｅｄ　ｐａｃｋａｇｅ）などの実装方法を用いることができる。 The electronic component 730 can be mounted on other boards using various mounting methods, not limited to BGA and PGA. For example, SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded pack) use a mounting method such as QFN (Quad Flat Non-leaded package) be able to.
本実施の形態は、本明細書で示す他の実施の形態などと適宜組み合わせることができる。 This embodiment mode can be combined with other embodiment modes shown in this specification as appropriate.
（実施の形態６）
本実施の形態では、本発明の一態様に係る半導体装置の応用例について説明する。 (Embodiment 6)
In this embodiment, an application example of a semiconductor device according to one embodiment of the present invention will be described.
本発明の一態様に係る半導体装置は、例えば、各種電子機器（例えば、情報端末、コンピュータ、スマートフォン、電子書籍端末、デジタルスチルカメラ、ビデオカメラ、録画再生装置、ナビゲーションシステム、ゲーム機など）の記憶装置に適用できる。また、イメージセンサ、ＩｏＴ（Ｉｎｔｅｒｎｅｔ　ｏｆ　Ｔｈｉｎｇｓ）、ヘルスケア関連機器などに用いることもできる。なお、ここで、コンピュータとは、タブレット型のコンピュータ、ノート型のコンピュータ、デスクトップ型のコンピュータの他、サーバシステムのような大型のコンピュータを含むものである。 The semiconductor device according to one embodiment of the present invention is, for example, a memory device for various electronic devices (for example, an information terminal, a computer, a smartphone, an electronic book terminal, a digital still camera, a video camera, a recording/playback device, a navigation system, a game console, etc.). Applicable to equipment. Moreover, it can also be used for image sensors, IoT (Internet of Things), healthcare-related equipment, and the like. Note that the term "computer" as used herein includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system.
本発明の一態様に係る半導体装置を有する電子機器の一例について説明する。なお、図２１Ａ乃至図２１Ｊ、図２２Ａ乃至図２２Ｅには、当該半導体装置を有する電子部品７００または電子部品７３０が各電子機器に含まれている様子を図示している。 An example of an electronic device including a semiconductor device according to one embodiment of the present invention will be described. Note that FIGS. 21A to 21J and 22A to 22E illustrate how each electronic device includes an electronic component 700 or an electronic component 730 having the semiconductor device.
［携帯電話］
図２１Ａに示す情報端末５５００は、情報端末の一種である携帯電話（スマートフォン）である。情報端末５５００は、筐体５５１０と、表示部５５１１と、を有しており、入力用インターフェースとして、タッチパネルが表示部５５１１に備えられ、ボタンが筐体５５１０に備えられている。 [mobile phone]
Information terminal 5500 shown in FIG. 21A is a mobile phone (smartphone) that is a type of information terminal. The information terminal 5500 includes a housing 5510 and a display section 5511. As an input interface, the display section 5511 is equipped with a touch panel, and the housing 5510 is equipped with buttons.
情報端末５５００は、本発明の一態様に係る半導体装置を適用することで、アプリケーションの実行時に生成される一時的なファイル（例えば、ウェブブラウザの使用時のキャッシュなど）を保持することができる。 By applying the semiconductor device according to one embodiment of the present invention, the information terminal 5500 can hold temporary files that are generated when an application is executed (for example, a cache when a web browser is used).
［ウェアラブル端末］
また、図２１Ｂには、ウェアラブル端末の一例である情報端末５９００が図示されている。情報端末５９００は、筐体５９０１、表示部５９０２、操作スイッチ５９０３、操作スイッチ５９０４、バンド５９０５などを有する。 [Wearable device]
Further, FIG. 21B illustrates an information terminal 5900 that is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display portion 5902, an operation switch 5903, an operation switch 5904, a band 5905, and the like.
ウェアラブル端末は、先述した情報端末５５００と同様に、本発明の一態様に係る半導体装置を適用することで、アプリケーションの実行時に生成される一時的なファイルを保持することができる。 Similar to the information terminal 5500 described above, the wearable terminal can hold temporary files generated when an application is executed by applying a semiconductor device according to one embodiment of the present invention.
［情報端末］
また、図２１Ｃには、デスクトップ型情報端末５３００が図示されている。デスクトップ型情報端末５３００は、情報端末の本体５３０１と、表示部５３０２と、キーボード５３０３と、を有する。 [Information terminal]
Furthermore, a desktop information terminal 5300 is illustrated in FIG. 21C. The desktop information terminal 5300 includes an information terminal main body 5301, a display section 5302, and a keyboard 5303.
デスクトップ型情報端末５３００は、先述した情報端末５５００と同様に、本発明の一態様に係る半導体装置を適用することで、アプリケーションの実行時に生成される一時的なファイルを保持することができる。 Similar to the information terminal 5500 described above, the desktop information terminal 5300 can hold temporary files generated when an application is executed by applying a semiconductor device according to one embodiment of the present invention.
なお、上述では、電子機器としてスマートフォン、ウェアラブル端末、デスクトップ用情報端末を例として、それぞれ図２１Ａ乃至図２１Ｃに図示したが、スマートフォン、ウェアラブル端末、デスクトップ用情報端末以外の情報端末を適用することができる。スマートフォン、ウェアラブル端末、デスクトップ用情報端末以外の情報端末としては、例えば、ＰＤＡ（Ｐｅｒｓｏｎａｌ　Ｄｉｇｉｔａｌ　Ａｓｓｉｓｔａｎｔ）、ノート型情報端末、ワークステーションなどが挙げられる。 Note that in the above description, a smartphone, a wearable terminal, and a desktop information terminal are shown as examples of electronic devices in FIGS. 21A to 21C, but information terminals other than smartphones, wearable terminals, and desktop information terminals may also be applied. can. Examples of information terminals other than smartphones, wearable terminals, and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, and workstations.
［電化製品］
また、図２１Ｄには、電化製品の一例として電気冷凍冷蔵庫５８００が図示されている。電気冷凍冷蔵庫５８００は、筐体５８０１、冷蔵室用扉５８０２、冷凍室用扉５８０３等を有する。例えば、電気冷凍冷蔵庫５８００は、ＩｏＴ（Ｉｎｔｅｒｎｅｔ　ｏｆ　Ｔｈｉｎｇｓ）に対応した電気冷凍冷蔵庫である。 [electric appliances]
Further, FIG. 21D shows an electric refrigerator-freezer 5800 as an example of an electrical appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like. For example, the electric refrigerator-freezer 5800 is an electric refrigerator-freezer that is compatible with IoT (Internet of Things).
電気冷凍冷蔵庫５８００に本発明の一態様に係る半導体装置を適用することができる。電気冷凍冷蔵庫５８００は、電気冷凍冷蔵庫５８００に保存されている食材、その食材の消費期限などの情報を、インターネットなどを通じて、情報端末などに送受信することができる。電気冷凍冷蔵庫５８００は、当該情報を送信する際に生成される一時的なファイルを、当該半導体装置に保持することができる。 A semiconductor device according to one embodiment of the present invention can be applied to an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 can send and receive information such as the foods stored in the electric refrigerator-freezer 5800 and the expiration date of the foods to an information terminal or the like via the Internet or the like. The electric refrigerator-freezer 5800 can hold a temporary file generated when transmitting the information in the semiconductor device.
本一例では、電化製品として電気冷凍冷蔵庫について説明したが、その他の電化製品としては、例えば、掃除機、電子レンジ、電気オーブン、炊飯器、湯沸かし器、ＩＨ調理器、ウォーターサーバ、エアーコンディショナーを含む冷暖房器具、洗濯機、乾燥機、オーディオビジュアル機器などが挙げられる。 In this example, an electric refrigerator-freezer was explained as an electric appliance, but other electric appliances include air conditioners including vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cookers, water servers, and air conditioners. Examples include appliances, washing machines, dryers, and audio-visual equipment.
［ゲーム機］
また、図２１Ｅには、ゲーム機の一例である携帯ゲーム機５２００が図示されている。携帯ゲーム機５２００は、筐体５２０１、表示部５２０２、ボタン５２０３等を有する。 [game machine]
Further, FIG. 21E shows a portable game machine 5200, which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.
更に、図２１Ｆには、ゲーム機の一例である据え置き型ゲーム機７５００が図示されている。据え置き型ゲーム機７５００は、本体７５２０と、コントローラ７５２２を有する。なお、本体７５２０には、無線または有線によってコントローラ７５２２を接続することができる。また、図２１Ｆには示していないが、コントローラ７５２２は、ゲームの画像を表示する表示部、ボタン以外の入力インターフェースとなる、タッチパネル、スティック、回転式つまみ、またはスライド式つまみなどを備えることができる。また、コントローラ７５２２は、図２１Ｆに示す形状に限定されず、ゲームのジャンルに応じて、コントローラ７５２２の形状を様々に変更してもよい。例えば、ＦＰＳ（Ｆｉｒｓｔ　Ｐｅｒｓｏｎ　Ｓｈｏｏｔｅｒ）などのシューティングゲームでは、トリガーをボタンとし、銃を模した形状のコントローラを用いることができる。また、例えば、音楽ゲームなどでは、楽器、音楽機器などを模した形状のコントローラを用いることができる。更に、据え置き型ゲーム機は、コントローラを使わず、代わりにカメラ、深度センサ、マイクロフォンなどを備えて、ゲームプレイヤーのジェスチャー、または音声によって操作する形式としてもよい。 Further, FIG. 21F shows a stationary game machine 7500, which is an example of a game machine. Stationary game machine 7500 includes a main body 7520 and a controller 7522. Note that a controller 7522 can be connected to the main body 7520 wirelessly or by wire. Although not shown in FIG. 21F, the controller 7522 can include a touch panel, a stick, a rotary knob, a sliding knob, or the like that serves as an input interface other than a display unit that displays game images, buttons, or the like. . Furthermore, the shape of the controller 7522 is not limited to the shape shown in FIG. 21F, and the shape of the controller 7522 may be changed in various ways depending on the genre of the game. For example, in a shooting game such as FPS (First Person Shooter), a trigger can be a button and a controller shaped like a gun can be used. Furthermore, for example, in a music game, a controller shaped like a musical instrument, music device, etc. can be used. Furthermore, the stationary game machine may not use a controller, but instead may be equipped with a camera, a depth sensor, a microphone, etc., and be operated by the game player's gestures or voice.
また、上述したゲーム機の映像は、テレビジョン装置、パーソナルコンピュータ用ディスプレイ、ゲーム用ディスプレイ、ヘッドマウントディスプレイなどの表示装置によって、出力することができる。 Further, the video of the game machine described above can be output by a display device such as a television device, a display for a personal computer, a display for a game, a head-mounted display, or the like.
携帯ゲーム機５２００または据え置き型ゲーム機７５００に上記実施の形態で説明した半導体装置を適用することによって、低消費電力の携帯ゲーム機５２００または低消費電力の据え置き型ゲーム機７５００を実現することができる。また、低消費電力により、回路からの発熱を低減することができるため、発熱によるその回路自体、周辺回路、およびモジュールへの影響を少なくすることができる。 By applying the semiconductor device described in the above embodiment to the portable game machine 5200 or the stationary game machine 7500, the portable game machine 5200 or the stationary game machine 7500 with low power consumption can be realized. . Furthermore, low power consumption makes it possible to reduce heat generation from the circuit, thereby reducing the effect of heat generation on the circuit itself, peripheral circuits, and modules.
更に、携帯ゲーム機５２００または据え置き型ゲーム機７５００に上記実施の形態で説明した半導体装置を適用することによって、ゲームの実行中に発生する演算に必要な一時ファイルなどの保持をおこなうことができる。 Furthermore, by applying the semiconductor device described in the above embodiment to the portable game machine 5200 or the stationary game machine 7500, temporary files and the like required for calculations that occur during game execution can be held.
ゲーム機の一例として図２１Ｅに携帯ゲーム機を示す。また、図２１Ｆに家庭用の据え置き型ゲーム機を示す。なお、本発明の一態様の電子機器はこれに限定されない。本発明の一態様の電子機器としては、例えば、娯楽施設（ゲームセンター、遊園地など）に設置されるアーケードゲーム機、スポーツ施設に設置されるバッティング練習用の投球マシンなどが挙げられる。 A portable game machine is shown in FIG. 21E as an example of a game machine. Further, FIG. 21F shows a home-use stationary game machine. Note that the electronic device of one embodiment of the present invention is not limited to this. Examples of electronic devices according to one embodiment of the present invention include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.), pitching machines for batting practice installed in sports facilities, and the like.
［移動体］
上記実施の形態で説明した半導体装置は、移動体である自動車、および自動車の運転席周辺に適用することができる。 [Mobile object]
The semiconductor device described in the above embodiments can be applied to an automobile, which is a moving object, and to the vicinity of the driver's seat of the automobile.
図２１Ｇには移動体の一例である自動車５７００が図示されている。 FIG. 21G shows an automobile 5700 that is an example of a moving object.
自動車５７００の運転席周辺には、スピードメーター、タコメーター、走行距離、燃料計、ギア状態、エアコンの設定などを表示することで、様々な情報を提供するインストゥルメントパネルが備えられている。また、運転席周辺には、それらの情報を示す表示装置が備えられていてもよい。 The 5700 car is equipped with an instrument panel near the driver's seat that provides a variety of information by displaying speedometer, tachometer, mileage, fuel gauge, gear status, air conditioner settings, etc. Further, a display device showing such information may be provided around the driver's seat.
特に当該表示装置には、自動車５７００に設けられた撮像装置（図示しない。）からの映像を映し出すことによって、ピラーなどで遮られた視界、運転席の死角などを補うことができ、安全性を高めることができる。すなわち、自動車５７００の外側に設けられた撮像装置からの画像を表示することによって、死角を補い、安全性を高めることができる。 In particular, by projecting images from an imaging device (not shown) installed in the vehicle 5700 on the display device, it is possible to compensate for the visibility obstructed by pillars, blind spots in the driver's seat, etc., and improve safety. can be increased. That is, by displaying an image from an imaging device provided outside the automobile 5700, blind spots can be compensated for and safety can be improved.
上記実施の形態で説明した半導体装置は、情報を一時的に保持することができるため、例えば、当該半導体装置を、自動車５７００の自動運転、道路案内、危険予測などを行うシステムなどにおける、必要な一時的な情報の保持に用いることができる。当該表示装置には、道路案内、危険予測などの一時的な情報を表示する構成としてもよい。また、自動車５７００に備え付けられたドライビングレコーダの映像を保持する構成としてもよい。 Since the semiconductor device described in the above embodiment mode can temporarily hold information, the semiconductor device can be used, for example, in a system that performs automatic driving of the automobile 5700, road guidance, danger prediction, etc. It can be used to temporarily hold information. The display device may be configured to display temporary information such as road guidance and danger prediction. Alternatively, a configuration may be adopted in which images from a driving recorder installed in the automobile 5700 are held.
なお、上述では、移動体の一例として自動車について説明しているが、移動体は自動車に限定されない。例えば、移動体としては、電車、モノレール、船、飛行体（ヘリコプター、無人航空機（ドローン）、飛行機、ロケット）なども挙げることができる。 Note that although a car is described above as an example of a moving body, the moving body is not limited to a car. For example, examples of moving objects include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets).
［カメラ］
上記実施の形態で説明した半導体装置は、カメラに適用することができる。 [camera]
The semiconductor device described in the above embodiment can be applied to a camera.
図２１Ｈには、撮像装置の一例であるデジタルカメラ６２４０が図示されている。デジタルカメラ６２４０は、筐体６２４１、表示部６２４２、操作スイッチ６２４３、シャッターボタン６２４４等を有し、また、デジタルカメラ６２４０には、着脱可能なレンズ６２４６が取り付けられている。なお、ここではデジタルカメラ６２４０を、レンズ６２４６を筐体６２４１から取り外して交換することが可能な構成としたが、レンズ６２４６と筐体６２４１とが一体となっていてもよい。また、デジタルカメラ６２４０は、ストロボ装置、ビューファインダー等を別途装着することができる構成としてもよい。 FIG. 21H illustrates a digital camera 6240 that is an example of an imaging device. The digital camera 6240 includes a housing 6241, a display section 6242, an operation switch 6243, a shutter button 6244, and the like, and a detachable lens 6246 is attached to the digital camera 6240. Note that although the digital camera 6240 is configured here so that the lens 6246 can be removed from the housing 6241 and replaced, the lens 6246 and the housing 6241 may be integrated. Further, the digital camera 6240 may have a configuration in which a strobe device, a viewfinder, etc. can be separately attached.
デジタルカメラ６２４０に上記実施の形態で説明した半導体装置を適用することによって、低消費電力のデジタルカメラ６２４０を実現することができる。また、低消費電力により、回路からの発熱を低減することができるため、発熱によるその回路自体、周辺回路、およびモジュールへの影響を少なくすることができる。 By applying the semiconductor device described in the above embodiment to the digital camera 6240, the digital camera 6240 with low power consumption can be realized. Furthermore, low power consumption makes it possible to reduce heat generation from the circuit, thereby reducing the effect of heat generation on the circuit itself, peripheral circuits, and modules.
［ビデオカメラ］
上記実施の形態で説明した半導体装置は、ビデオカメラに適用することができる。 [Video camera]
The semiconductor device described in the above embodiment can be applied to a video camera.
図２１Ｉには、撮像装置の一例であるビデオカメラ６３００が図示されている。ビデオカメラ６３００は、第１筐体６３０１、第２筐体６３０２、表示部６３０３、操作スイッチ６３０４、レンズ６３０５、接続部６３０６等を有する。操作スイッチ６３０４およびレンズ６３０５は第１筐体６３０１に設けられており、表示部６３０３は第２筐体６３０２に設けられている。そして、第１筐体６３０１と第２筐体６３０２とは、接続部６３０６により接続されており、第１筐体６３０１と第２筐体６３０２の間の角度は、接続部６３０６により変更が可能である。表示部６３０３における映像を、接続部６３０６における第１筐体６３０１と第２筐体６３０２との間の角度に従って切り替える構成としてもよい。 FIG. 21I illustrates a video camera 6300, which is an example of an imaging device. The video camera 6300 includes a first housing 6301, a second housing 6302, a display portion 6303, an operation switch 6304, a lens 6305, a connecting portion 6306, and the like. The operation switch 6304 and the lens 6305 are provided in the first casing 6301, and the display portion 6303 is provided in the second casing 6302. The first casing 6301 and the second casing 6302 are connected by a connecting part 6306, and the angle between the first casing 6301 and the second casing 6302 can be changed by the connecting part 6306. be. The image on the display section 6303 may be switched according to the angle between the first casing 6301 and the second casing 6302 at the connection section 6306.
ビデオカメラ６３００で撮影した映像を記録する際、データの記録形式に応じたエンコードを行う必要がある。上述した半導体装置を利用することによって、ビデオカメラ６３００は、エンコードの際に発生する一時的なファイルの保持を行うことができる。 When recording video captured by the video camera 6300, it is necessary to perform encoding according to the data recording format. By using the semiconductor device described above, the video camera 6300 can hold temporary files generated during encoding.
［ＩＣＤ］
上記実施の形態で説明した半導体装置は、植え込み型除細動器（ＩＣＤ）に適用することができる。 [ICD]
The semiconductor device described in the above embodiments can be applied to an implantable cardioverter defibrillator (ICD).
図２１Ｊは、ＩＣＤの一例を示す断面模式図である。ＩＣＤ本体５４００は、バッテリー５４０１と、電子部品７００と、レギュレータと、制御回路と、アンテナ５４０４と、右心房へのワイヤ５４０２、右心室へのワイヤ５４０３とを少なくとも有している。 FIG. 21J is a schematic cross-sectional view showing an example of an ICD. The ICD main body 5400 includes at least a battery 5401, an electronic component 700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.
ＩＣＤ本体５４００は手術により体内に設置され、二本のワイヤは、人体の鎖骨下静脈５４０５および上大静脈５４０６を通過させて一方のワイヤ先端が右心室、もう一方のワイヤ先端が右心房に設置されるようにする。 The ICD main body 5400 is surgically installed in the body, and the two wires are passed through the subclavian vein 5405 and the superior vena cava 5406, and the tip of one wire is placed in the right ventricle and the tip of the other wire is placed in the right atrium. to be done.
ＩＣＤ本体５４００は、ペースメーカとしての機能を有し、心拍数が規定の範囲から外れた場合に心臓に対してペーシングを行う。また、ペーシングによって心拍数が改善しない場合（速い心室頻拍、心室細動など）、電気ショックによる治療が行われる。 The ICD main body 5400 has a function as a pacemaker, and paces the heart when the heart rate falls outside of a specified range. In addition, if the heart rate does not improve with pacing (such as rapid ventricular tachycardia or ventricular fibrillation), electric shock treatment is performed.
ＩＣＤ本体５４００は、ペーシングおよび電気ショックを適切に行うため、心拍数を常に監視する必要がある。そのため、ＩＣＤ本体５４００は、心拍数を検知するためのセンサを有する。また、ＩＣＤ本体５４００は、当該センサなどによって取得した心拍数のデータ、ペーシングによる治療を行った回数、時間などを電子部品７００に記憶することができる。 The ICD main body 5400 needs to constantly monitor heart rate in order to properly perform pacing and electric shock. Therefore, ICD main body 5400 has a sensor for detecting heart rate. Further, the ICD main body 5400 can store heart rate data acquired by the sensor, the number of times pacing treatment has been performed, time, etc. in the electronic component 700.
また、アンテナ５４０４で電力が受信でき、その電力はバッテリー５４０１に充電される。また、ＩＣＤ本体５４００は複数のバッテリーを有することにより、安全性を高くすることができる。具体的には、ＩＣＤ本体５４００の一部のバッテリーが使えなくなったとしても残りのバッテリーが機能させることができるため、補助電源としても機能する。 Further, power can be received by the antenna 5404, and the battery 5401 is charged with the power. Further, the ICD main body 5400 can have higher safety by having a plurality of batteries. Specifically, even if some of the batteries in the ICD main body 5400 become unusable, the remaining batteries can function, so it also functions as an auxiliary power source.
また、電力を受信できるアンテナ５４０４とは別に、生理信号を送信できるアンテナを有していてもよく、例えば、脈拍、呼吸数、心拍数、体温などの生理信号を外部のモニタ装置で確認できるような心臓活動を監視するシステムを構成してもよい。 Furthermore, in addition to the antenna 5404 that can receive power, it may have an antenna that can transmit physiological signals. A system may be configured to monitor cardiac activity.
［ＰＣ用の拡張デバイス］
上記実施の形態で説明した半導体装置は、ＰＣ（Ｐｅｒｓｏｎａｌ　Ｃｏｍｐｕｔｅｒ）などの計算機、情報端末用の拡張デバイスに適用することができる。 [Expansion device for PC]
The semiconductor device described in the above embodiments can be applied to computers such as PCs (Personal Computers) and expansion devices for information terminals.
図２２Ａは、当該拡張デバイスの一例として、持ち運びのできる、情報の記憶が可能なチップが搭載された、ＰＣに外付けする拡張デバイス６１００を示している。拡張デバイス６１００は、例えば、ＵＳＢ（Ｕｎｉｖｅｒｓａｌ　Ｓｅｒｉａｌ　Ｂｕｓ）などでＰＣに接続することで、当該チップによる情報の記憶を行うことができる。なお、図２２Ａは、持ち運びが可能な形態の拡張デバイス６１００を図示しているが、本発明の一態様に係る拡張デバイスは、これに限定されず、例えば、冷却用ファンなどを搭載した比較的大きい形態の拡張デバイスとしてもよい。 FIG. 22A shows, as an example of the expansion device, an expansion device 6100 that is portable and equipped with a chip that can store information and is externally attached to a PC. The expansion device 6100 can store information using the chip by connecting it to a PC via, for example, a USB (Universal Serial Bus). Note that although FIG. 22A illustrates a portable expansion device 6100, the expansion device according to one embodiment of the present invention is not limited to this, and for example, a relatively portable expansion device equipped with a cooling fan or the like. It may also be a large form expansion device.
拡張デバイス６１００は、筐体６１０１、キャップ６１０２、ＵＳＢコネクタ６１０３および基板６１０４を有する。基板６１０４は、筐体６１０１に収納されている。基板６１０４には、上記実施の形態で説明した半導体装置などを駆動する回路が設けられている。例えば、基板６１０４には、電子部品７００、コントローラチップ６１０６が取り付けられている。ＵＳＢコネクタ６１０３は、外部装置と接続するためのインターフェースとして機能する。 Expansion device 6100 includes a housing 6101, a cap 6102, a USB connector 6103, and a board 6104. A board 6104 is housed in a housing 6101. A circuit for driving the semiconductor device described in the above embodiment mode or the like is provided on the substrate 6104. For example, an electronic component 700 and a controller chip 6106 are attached to the board 6104. The USB connector 6103 functions as an interface for connecting to an external device.
［ＳＤカード］
上記実施の形態で説明した半導体装置は、情報端末、デジタルカメラなどの電子機器に取り付けが可能なＳＤカードに適用することができる。 [SD card]
The semiconductor device described in the above embodiments can be applied to an SD card that can be attached to electronic devices such as information terminals and digital cameras.
図２２ＢはＳＤカードの外観の模式図であり、図２２Ｃは、ＳＤカードの内部構造の模式図である。ＳＤカード５１１０は、筐体５１１１、コネクタ５１１２および基板５１１３を有する。コネクタ５１１２が外部装置と接続するためのインターフェースとして機能する。基板５１１３は筐体５１１１に収納されている。基板５１１３には、半導体装置および半導体装置を駆動する回路が設けられている。例えば、基板５１１３には、電子部品７００、コントローラチップ５１１５が取り付けられている。なお、電子部品７００とコントローラチップ５１１５とのそれぞれの回路構成は、上述の記載に限定せず、状況に応じて、適宜回路構成を変更してもよい。例えば、電子部品に備えられている書き込み回路、ロードライバ、読み出し回路などは、電子部品７００でなく、コントローラチップ５１１５に組み込んだ構成としてもよい。 FIG. 22B is a schematic diagram of the external appearance of the SD card, and FIG. 22C is a schematic diagram of the internal structure of the SD card. The SD card 5110 has a housing 5111, a connector 5112, and a board 5113. A connector 5112 functions as an interface for connecting to an external device. The board 5113 is housed in a housing 5111. The substrate 5113 is provided with a semiconductor device and a circuit for driving the semiconductor device. For example, an electronic component 700 and a controller chip 5115 are attached to the board 5113. Note that the circuit configurations of the electronic component 700 and the controller chip 5115 are not limited to those described above, and the circuit configurations may be changed as appropriate depending on the situation. For example, a write circuit, a row driver, a read circuit, etc. included in the electronic component may be incorporated into the controller chip 5115 instead of the electronic component 700.
基板５１１３の裏面側にも電子部品７００を設けることで、ＳＤカード５１１０の容量を増やすことができる。また、無線通信機能を備えた無線チップを基板５１１３に設けてもよい。これによって、外部装置とＳＤカード５１１０との間で無線通信を行うことができ、電子部品７００のデータの読み出し、書き込みが可能となる。 By providing the electronic component 700 also on the back side of the board 5113, the capacity of the SD card 5110 can be increased. Further, a wireless chip having a wireless communication function may be provided on the substrate 5113. Thereby, wireless communication can be performed between the external device and the SD card 5110, and data can be read from and written to the electronic component 700.
［ＳＳＤ］
上記実施の形態で説明した半導体装置は、情報端末など電子機器に取り付けが可能なＳＳＤ（Ｓｏｌｉｄ　Ｓｔａｔｅ　Ｄｒｉｖｅ）に適用することができる。 [SSD]
The semiconductor device described in the above embodiment can be applied to an SSD (Solid State Drive) that can be attached to an electronic device such as an information terminal.
図２２ＤはＳＳＤの外観の模式図であり、図２２Ｅは、ＳＳＤの内部構造の模式図である。ＳＳＤ５１５０は、筐体５１５１、コネクタ５１５２および基板５１５３を有する。コネクタ５１５２が外部装置と接続するためのインターフェースとして機能する。基板５１５３は筐体５１５１に収納されている。基板５１５３には、記憶装置および記憶装置を駆動する回路が設けられている。例えば、基板５１５３には、電子部品７００、メモリチップ５１５５、コントローラチップ５１５６が取り付けられている。基板５１５３の裏面側にも電子部品７００を設けることで、ＳＳＤ５１５０の容量を増やすことができる。メモリチップ５１５５にはワークメモリが組み込まれている。例えば、メモリチップ５１５５には、ＤＲＡＭチップを用いればよい。コントローラチップ５１５６には、プロセッサ、ＥＣＣ回路などが組み込まれている。なお、電子部品７００と、メモリチップ５１５５と、コントローラチップ５１１５と、のそれぞれの回路構成は、上述の記載に限定せず、状況に応じて、適宜回路構成を変更してもよい。例えば、コントローラチップ５１５６にも、ワークメモリとして機能するメモリを設けてもよい。 FIG. 22D is a schematic diagram of the external appearance of the SSD, and FIG. 22E is a schematic diagram of the internal structure of the SSD. The SSD 5150 includes a housing 5151, a connector 5152, and a board 5153. A connector 5152 functions as an interface for connecting to an external device. The board 5153 is housed in a housing 5151. The substrate 5153 is provided with a memory device and a circuit that drives the memory device. For example, an electronic component 700, a memory chip 5155, and a controller chip 5156 are attached to the board 5153. By providing the electronic component 700 also on the back side of the substrate 5153, the capacity of the SSD 5150 can be increased. A work memory is incorporated in the memory chip 5155. For example, a DRAM chip may be used as the memory chip 5155. The controller chip 5156 incorporates a processor, an ECC circuit, and the like. Note that the circuit configurations of the electronic component 700, the memory chip 5155, and the controller chip 5115 are not limited to those described above, and the circuit configurations may be changed as appropriate depending on the situation. For example, the controller chip 5156 may also be provided with a memory that functions as a work memory.
［計算機］
図２３Ａに示す計算機５６００は、主に科学技術計算に利用される大型の計算機（スーパーコンピュータ）の例である。科学技術計算では、膨大な演算を高速に処理する必要があるため、消費電力が高く、チップの発熱が大きい。例えば、計算機５６００を複数有するデータセンターでは、使用されるデジタルデータ量が非常に膨大になる。具体的には、世界のデジタルデータ量は、１０２４（ｙｏｔｔａ（ヨタ））バイト、または１０３０（ｑｕｅｔｔａ（クエタ））バイトを超えると予想されている。 [calculator]
A computer 5600 shown in FIG. 23A is an example of a large computer (supercomputer) mainly used for scientific and technical calculations. Scientific and technical calculations require high-speed processing of huge amounts of calculations, which consumes a lot of power and generates a lot of heat from the chip. For example, in a data center having a plurality of computers 5600, the amount of digital data used becomes extremely large. Specifically, the amount of digital data in the world is expected to exceed 10 24 (yotta) bytes or 10 30 (quetta) bytes.
計算機５６００に本発明の一態様の半導体装置を適用することによって、低消費電力のスーパーコンピュータを実現することができる。また、低消費電力により、回路からの発熱を低減することができるため、発熱によるその回路自体、周辺回路、およびモジュールへの影響を少なくすることができる。また、本発明の一態様の半導体装置を用いることで、低消費電力のスーパーコンピュータの実現が可能となる。これにより、世界のデジタルデータ量を低減し、地球温暖化対策にも大きな貢献ができると期待される。 By applying the semiconductor device of one embodiment of the present invention to the computer 5600, a supercomputer with low power consumption can be realized. Furthermore, low power consumption makes it possible to reduce heat generation from the circuit, thereby reducing the effect of heat generation on the circuit itself, peripheral circuits, and modules. Furthermore, by using the semiconductor device of one embodiment of the present invention, a supercomputer with low power consumption can be realized. This is expected to reduce the amount of digital data in the world and make a major contribution to global warming countermeasures.
計算機５６００には、ラック５６１０にラックマウント型の計算機５６２０が複数格納されている。計算機５６２０は、例えば、図２３Ｂに示す斜視図の構成とすることができる。図２３Ｂにおいて、計算機５６２０は、マザーボード５６３０を有し、マザーボード５６３０は、複数のスロット５６３１、複数の接続端子を有する。スロット５６３１には、ＰＣカード５６２１が挿されている。加えて、ＰＣカード５６２１は、接続端子５６２３、接続端子５６２４、接続端子５６２５を有し、それぞれ、マザーボード５６３０に接続されている。 In the computer 5600, a plurality of rack-mounted computers 5620 are stored in a rack 5610. The computer 5620 can have, for example, the configuration shown in the perspective view shown in FIG. 23B. In FIG. 23B, a computer 5620 has a motherboard 5630, and the motherboard 5630 has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has a connection terminal 5623, a connection terminal 5624, and a connection terminal 5625, each of which is connected to the motherboard 5630.
図２３Ｃに示すＰＣカード５６２１は、ＣＰＵ、ＧＰＵ、記憶装置などを備えた処理ボードの一例である。ＰＣカード５６２１は、ボード５６２２を有する。また、ボード５６２２は、接続端子５６２３と、接続端子５６２４と、接続端子５６２５と、半導体装置５６２６と、半導体装置５６２７と、半導体装置５６２８と、接続端子５６２９と、を有する。なお、図２３Ｃには、半導体装置５６２６、半導体装置５６２７、および半導体装置５６２８以外の半導体装置を図示しているが、それらの半導体装置については、以下に記載する半導体装置５６２６、半導体装置５６２７、および半導体装置５６２８の説明を参考にすればよい。 A PC card 5621 shown in FIG. 23C is an example of a processing board that includes a CPU, a GPU, a storage device, and the like. PC card 5621 has a board 5622. Further, the board 5622 includes a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that although semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 are illustrated in FIG. The description of the semiconductor device 5628 may be referred to.
接続端子５６２９は、マザーボード５６３０のスロット５６３１に挿すことができる形状を有しており、接続端子５６２９は、ＰＣカード５６２１とマザーボード５６３０とを接続するためのインターフェースとして機能する。接続端子５６２９の規格としては、例えば、ＰＣＩｅなどが挙げられる。 The connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. Examples of the standard of the connection terminal 5629 include PCIe.
接続端子５６２３、接続端子５６２４、接続端子５６２５は、例えば、ＰＣカード５６２１に対して電力供給、信号入力などを行うためのインターフェースとすることができる。また、例えば、ＰＣカード５６２１によって計算された信号の出力などを行うためのインターフェースとすることができる。接続端子５６２３、接続端子５６２４、接続端子５６２５のそれぞれの規格としては、例えば、ＵＳＢ（Ｕｎｉｖｅｒｓａｌ　Ｓｅｒｉａｌ　Ｂｕｓ）、ＳＡＴＡ（Ｓｅｒｉａｌ　ＡＴＡ）、ＳＣＳＩ（Ｓｍａｌｌ　Ｃｏｍｐｕｔｅｒ　Ｓｙｓｔｅｍ　Ｉｎｔｅｒｆａｃｅ）などが挙げられる。また、接続端子５６２３、接続端子５６２４、接続端子５６２５から映像信号を出力する場合、それぞれの規格としては、ＨＤＭＩ（登録商標）などが挙げられる。 The connection terminal 5623, the connection terminal 5624, and the connection terminal 5625 can be used as an interface for supplying power, inputting signals, etc. to the PC card 5621, for example. Further, for example, it can be used as an interface for outputting a signal calculated by the PC card 5621. The respective standards of the connection terminal 5623, connection terminal 5624, and connection terminal 5625 include, for example, USB (Universal Serial Bus), SATA (Serial ATA), SCSI (Small Computer System Interface), etc. Can be mentioned. Furthermore, when outputting video signals from the connection terminals 5623, 5624, and 5625, the respective standards include HDMI (registered trademark).
半導体装置５６２６は、信号の入出力を行う端子（図示しない。）を有しており、当該端子をボード５６２２が備えるソケット（図示しない。）に対して差し込むことで、半導体装置５６２６とボード５６２２を電気的に接続することができる。 The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and by inserting the terminal into a socket (not shown) provided on the board 5622, the semiconductor device 5626 and the board 5622 can be connected. Can be electrically connected.
半導体装置５６２７は、複数の端子を有しており、当該端子をボード５６２２が備える配線に対して、例えば、リフロー方式のはんだ付けを行うことで、半導体装置５６２７とボード５６２２を電気的に接続することができる。半導体装置５６２７としては、例えば、ＦＰＧＡ（Ｆｉｅｌｄ　Ｐｒｏｇｒａｍｍａｂｌｅ　Ｇａｔｅ　Ａｒｒａｙ）、ＧＰＵ、ＣＰＵなどが挙げられる。半導体装置５６２７として、例えば、電子部品７３０を用いることができる。 The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 and the board 5622 are electrically connected by, for example, reflow soldering the terminals to wiring provided on the board 5622. be able to. Examples of the semiconductor device 5627 include an FPGA (Field Programmable Gate Array), a GPU, and a CPU. For example, an electronic component 730 can be used as the semiconductor device 5627.
半導体装置５６２８は、複数の端子を有しており、当該端子をボード５６２２が備える配線に対して、例えば、リフロー方式のはんだ付けを行うことで、半導体装置５６２８とボード５６２２を電気的に接続することができる。半導体装置５６２８としては、例えば、記憶装置などが挙げられる。半導体装置５６２８として、例えば、電子部品７００を用いることができる。 The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 are electrically connected by, for example, reflow soldering the terminals to wiring provided on the board 5622. be able to. Examples of the semiconductor device 5628 include a storage device. For example, the electronic component 700 can be used as the semiconductor device 5628.
計算機５６００は並列計算機としても機能できる。計算機５６００を並列計算機として用いることで、例えば、人工知能の学習、および推論に必要な大規模の計算を行うことができる。 Computer 5600 can also function as a parallel computer. By using the computer 5600 as a parallel computer, for example, large-scale calculations required for artificial intelligence learning and inference can be performed.
上記の各種電子機器などに、本発明の一態様の半導体装置を用いることにより、電子機器の小型化、および低消費電力化を図ることができる。また、本発明の一態様の半導体装置は消費電力が少ないため、回路からの発熱を低減することができる。よって、当該発熱によるその回路自体、周辺回路、およびモジュールへの悪影響を低減できる。また、本発明の一態様の半導体装置を用いることにより、高温環境下においても動作が安定した電子機器を実現できる。よって、電子機器の信頼性を高めることができる。 By using the semiconductor device of one embodiment of the present invention in the various electronic devices described above, the electronic devices can be made smaller and have lower power consumption. Further, since the semiconductor device of one embodiment of the present invention consumes less power, heat generated from the circuit can be reduced. Therefore, the adverse effect of the heat generation on the circuit itself, peripheral circuits, and module can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, an electronic device that operates stably even in a high-temperature environment can be achieved. Therefore, the reliability of electronic equipment can be improved.
本実施の形態は、本明細書で示す他の実施の形態などと適宜組み合わせることができる。 This embodiment mode can be combined with other embodiment modes shown in this specification as appropriate.
（実施の形態７）
本発明の一態様の半導体装置は、ＯＳトランジスタを含む。当該ＯＳトランジスタは、放射線照射による電気特性の変動が小さい。つまり放射線に対する耐性が高いため、放射線が入射しうる環境において好適に用いることができる。例えば、ＯＳトランジスタは、宇宙空間にて使用する場合に好適に用いることができる。本実施の形態においては、本発明の一態様の半導体装置を宇宙用機器に適用する場合の具体例について、図２４を用いて説明する。 (Embodiment 7)
A semiconductor device of one embodiment of the present invention includes an OS transistor. The OS transistor has small variations in electrical characteristics due to radiation irradiation. In other words, since it has high resistance to radiation, it can be suitably used in environments where radiation may be incident. For example, OS transistors can be suitably used when used in outer space. In this embodiment, a specific example in which a semiconductor device of one embodiment of the present invention is applied to space equipment will be described with reference to FIG.
図２４には、宇宙用機器の一例として、人工衛星６８００を示している。人工衛星６８００は、機体６８０１と、ソーラーパネル６８０２と、アンテナ６８０３と、二次電池６８０５と、制御装置６８０７と、を有する。なお、図２４においては、宇宙空間に惑星６８０４を例示している。なお、宇宙空間とは、例えば、高度１００ｋｍ以上を指すが、本明細書に記載の宇宙空間は、熱圏、中間圏、及び成層圏を含んでもよい。 FIG. 24 shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 includes a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that in FIG. 24, a planet 6804 is illustrated in outer space. Note that outer space refers to, for example, an altitude of 100 km or more, but outer space described in this specification may include the thermosphere, mesosphere, and stratosphere.
また、宇宙空間は、地上に比べて１００倍以上、放射線量の高い環境である。なお、放射線として、例えば、Ｘ線、及びガンマ線に代表される電磁波（電磁放射線）、並びにアルファ線、ベータ線、中性子線、陽子線、重イオン線、中間子線などに代表される粒子放射線が挙げられる。 Furthermore, outer space is an environment with more than 100 times higher radiation levels than on the ground. Examples of radiation include electromagnetic waves (electromagnetic radiation) represented by X-rays and gamma rays, and particle radiation represented by alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, meson rays, etc. It will be done.
ソーラーパネル６８０２に太陽光が照射されることにより、人工衛星６８００が動作するために必要な電力が生成される。しかしながら、例えばソーラーパネルに太陽光が照射されない状況、またはソーラーパネルに照射される太陽光の光量が少ない状況では、生成される電力が少なくなる。よって、人工衛星６８００が動作するために必要な電力が生成されない可能性がある。生成される電力が少ない状況下であっても人工衛星６８００を動作させるために、人工衛星６８００に二次電池６８０５を設けるとよい。なお、ソーラーパネルは、太陽電池モジュールと呼ばれる場合がある。 By irradiating the solar panel 6802 with sunlight, electric power necessary for the operation of the artificial satellite 6800 is generated. However, for example, in a situation where the solar panel is not irradiated with sunlight, or in a situation where the amount of sunlight irradiated onto the solar panel is small, less electric power is generated. Therefore, the power necessary for satellite 6800 to operate may not be generated. In order to operate the artificial satellite 6800 even in a situation where generated power is small, it is preferable to provide the artificial satellite 6800 with a secondary battery 6805. Note that the solar panel is sometimes called a solar cell module.
人工衛星６８００は、信号を生成することができる。当該信号は、アンテナ６８０３を介して送信され、たとえば地上に設けられた受信機、または他の人工衛星が当該信号を受信することができる。人工衛星６８００が送信した信号を受信することにより、当該信号を受信した受信機の位置を測定することができる。以上より、人工衛星６８００は、衛星測位システムを構成することができる。 Satellite 6800 can generate signals. The signal is transmitted via antenna 6803 and can be received by, for example, a ground-based receiver or other satellite. By receiving the signal transmitted by the artificial satellite 6800, the position of the receiver that received the signal can be measured. As described above, the artificial satellite 6800 can constitute a satellite positioning system.
また、制御装置６８０７は、人工衛星６８００を制御する機能を有する。制御装置６８０７としては、例えば、ＣＰＵ、ＧＰＵ、及び記憶装置の中から選ばれるいずれか一または複数を用いて構成される。なお、制御装置６８０７には、本発明の一態様であるＯＳトランジスタを含む半導体装置を用いると好適である。ＯＳトランジスタは、Ｓｉトランジスタと比較し、放射線照射による電気特性の変動が小さい。つまり放射線が入射しうる環境においても信頼性が高く、好適に用いることができる。 Further, the control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using one or more selected from, for example, a CPU, a GPU, and a storage device. Note that a semiconductor device including an OS transistor, which is one embodiment of the present invention, is preferably used for the control device 6807. Compared to Si transistors, OS transistors have smaller fluctuations in electrical characteristics due to radiation irradiation. In other words, it is highly reliable and can be suitably used even in environments where radiation may be incident.
また、人工衛星６８００は、センサを有する構成とすることができる。たとえば、可視光センサを有する構成とすることにより、人工衛星６８００は、地上に設けられている物体に当たって反射された太陽光を検出する機能を有することができる。または、熱赤外センサを有する構成とすることにより、人工衛星６８００は、地表から放出される熱赤外線を検出する機能を有することができる。以上より、人工衛星６８００は、たとえば地球観測衛星としての機能を有することができる。 Furthermore, the artificial satellite 6800 can be configured to include a sensor. For example, by having a configuration including a visible light sensor, the artificial satellite 6800 can have a function of detecting sunlight reflected by hitting an object provided on the ground. Alternatively, by having a configuration including a thermal infrared sensor, the artificial satellite 6800 can have a function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can have the function of, for example, an earth observation satellite.
なお、本実施の形態においては、宇宙用機器の一例として、人工衛星について例示したがこれに限定されない。例えば、本発明の一態様の半導体装置は、宇宙船、宇宙カプセル、宇宙探査機などの宇宙用機器に好適に用いることができる。 Note that in this embodiment, an artificial satellite is illustrated as an example of space equipment, but the present invention is not limited to this. For example, the semiconductor device of one embodiment of the present invention can be suitably used for space equipment such as a spacecraft, a space capsule, and a space probe.
本実施の形態は、本明細書で示す他の実施の形態などと適宜組み合わせることができる。 This embodiment mode can be combined with other embodiment modes shown in this specification as appropriate.
１００：トランジスタ、１１０：容量素子、１５１：導電層、１５２：導電層、１５３：絶縁層、１５４：絶縁層、１５５：導電層、１５７：絶縁層、１５８：絶縁層、１５９：絶縁層、１６１：導電層、１６２：開口、１６３：半導体層 100: Transistor, 110: Capacitive element, 151: Conductive layer, 152: Conductive layer, 153: Insulating layer, 154: Insulating layer, 155: Conductive layer, 157: Insulating layer, 158: Insulating layer, 159: Insulating layer, 161 : Conductive layer, 162: Opening, 163: Semiconductor layer

Claims (19)

  1. 　容量素子と、前記容量素子上のトランジスタとを有し、
    　前記容量素子は、
    　第１導電層と、前記第１導電層上の第１絶縁層と、前記第１絶縁層上の第２導電層と、を有し、
    　前記トランジスタは、
    　前記第２導電層上の第２絶縁層と、前記第２絶縁層上の第３導電層と、
    　前記第２絶縁層および前記第３導電層に設けられた開口と、
    　前記開口を覆う半導体層と、前記半導体層上の第３絶縁層と、前記第３絶縁層上の第４導電層と、を有し、
    　前記開口は前記第２導電層と重なり、
    　前記第１絶縁層は強誘電体を含む半導体装置。     comprising a capacitive element and a transistor on the capacitive element,
    The capacitive element is
    a first conductive layer, a first insulating layer on the first conductive layer, and a second conductive layer on the first insulating layer,
    The transistor is
    a second insulating layer on the second conductive layer; a third conductive layer on the second insulating layer;
    an opening provided in the second insulating layer and the third conductive layer;
    a semiconductor layer covering the opening, a third insulating layer on the semiconductor layer, and a fourth conductive layer on the third insulating layer,
    the opening overlaps the second conductive layer,
    A semiconductor device in which the first insulating layer includes a ferroelectric material.
  2. 　請求項１において、
    　前記開口における前記第２絶縁層の側面と、前記第２絶縁層の底面のなす角度が、４５度以上９０度以下である半導体装置。     In claim 1,
    A semiconductor device in which an angle between a side surface of the second insulating layer in the opening and a bottom surface of the second insulating layer is 45 degrees or more and 90 degrees or less.
  3. 　請求項１または請求項２において、
    　１５０℃の環境温度下において、メモリ保持期間が１０日以上である半導体装置。     In claim 1 or claim 2,
    A semiconductor device whose memory retention period is 10 days or more at an environmental temperature of 150°C.
  4. 　請求項１または請求項２において、
    　前記第２絶縁層は、第４絶縁層と、前記第４絶縁層上の第５絶縁層と、前記第５絶縁層上の第６絶縁層と、を有し、
    　前記第４絶縁層と前記第６絶縁層のそれぞれは、窒素およびシリコンを有し、
    　前記第５絶縁層は、酸素およびシリコンを有する半導体装置。     In claim 1 or claim 2,
    The second insulating layer includes a fourth insulating layer, a fifth insulating layer on the fourth insulating layer, and a sixth insulating layer on the fifth insulating layer,
    Each of the fourth insulating layer and the sixth insulating layer contains nitrogen and silicon,
    A semiconductor device in which the fifth insulating layer includes oxygen and silicon.
  5. 　請求項４において、
    　前記第４絶縁層と前記第６絶縁層のそれぞれは、水素を有する半導体装置。     In claim 4,
    A semiconductor device in which each of the fourth insulating layer and the sixth insulating layer includes hydrogen.
  6. 　請求項１または請求項２において、
    　前記半導体層は、酸化物半導体を含む半導体装置。     In claim 1 or claim 2,
    A semiconductor device in which the semiconductor layer includes an oxide semiconductor.
  7. 　請求項１または請求項２において、
    　前記第１絶縁層は、ハフニウム、ジルコニウム、および酸素を含む半導体装置。     In claim 1 or claim 2,
    A semiconductor device in which the first insulating layer contains hafnium, zirconium, and oxygen.
  8. 　請求項１または請求項２において、
    　前記第１導電層および前記第２導電層は、チタンおよび窒素を含む半導体装置。     In claim 1 or claim 2,
    A semiconductor device in which the first conductive layer and the second conductive layer contain titanium and nitrogen.
  9. 　請求項１または請求項２において、
    　前記第４導電層は前記トランジスタのゲート電極として機能し、
    　前記第３導電層は前記トランジスタのソース電極またはドレイン電極の一方として機能し、
    　前記第２導電層は前記トランジスタのソース電極またはドレイン電極の他方として機能する半導体装置。     In claim 1 or claim 2,
    The fourth conductive layer functions as a gate electrode of the transistor,
    The third conductive layer functions as one of a source electrode or a drain electrode of the transistor,
    In the semiconductor device, the second conductive layer functions as the other of a source electrode and a drain electrode of the transistor.
  10. 　積層された複数の層と、
    　前記複数の層を貫通する第１電極と、を有し、
    　前記複数の層のそれぞれは、
    　容量素子と、前記容量素子上のトランジスタとを有し、
    　前記容量素子は、
    　第１導電層と、前記第１導電層上の第１絶縁層と、前記第１絶縁層上の第２導電層と、を有し、
    　前記トランジスタは、
    　前記第２導電層上の第２絶縁層と、前記第２絶縁層上の第３導電層と、
    　前記第２絶縁層および前記第３導電層に設けられた開口と、
    　前記開口を覆う半導体層と、前記半導体層上の第３絶縁層と、前記第３絶縁層上の第４導電層と、を有し、
    　前記開口は前記第２導電層と重なり、
    　前記第１絶縁層は強誘電体を含み、
    　前記第３導電層は前記第１電極と電気的に接続する半導体装置。     multiple laminated layers;
    a first electrode penetrating the plurality of layers;
    Each of the plurality of layers is
    comprising a capacitive element and a transistor on the capacitive element,
    The capacitive element is
    a first conductive layer, a first insulating layer on the first conductive layer, and a second conductive layer on the first insulating layer,
    The transistor is
    a second insulating layer on the second conductive layer; a third conductive layer on the second insulating layer;
    an opening provided in the second insulating layer and the third conductive layer;
    a semiconductor layer covering the opening, a third insulating layer on the semiconductor layer, and a fourth conductive layer on the third insulating layer,
    the opening overlaps the second conductive layer,
    the first insulating layer includes a ferroelectric material,
    A semiconductor device in which the third conductive layer is electrically connected to the first electrode.
  11. 　請求項１０において、
    　前記開口における前記第２絶縁層の側面と、前記第２絶縁層の底面のなす角度が、４５度以上９０度以下である半導体装置。     In claim 10,
    A semiconductor device in which an angle between a side surface of the second insulating layer in the opening and a bottom surface of the second insulating layer is 45 degrees or more and 90 degrees or less.
  12. 　請求項１０または請求項１１において、
    　１５０℃の環境温度下において、メモリ保持期間が１０日以上である半導体装置。     In claim 10 or claim 11,
    A semiconductor device whose memory retention period is 10 days or more at an environmental temperature of 150°C.
  13. 　請求項１０または請求項１１において、
    　前記第１電極は、複数の導電層を含む半導体装置。     In claim 10 or claim 11,
    A semiconductor device in which the first electrode includes a plurality of conductive layers.
  14. 　請求項１０または請求項１１において、
    　前記第２絶縁層は、第４絶縁層と、前記第４絶縁層上の第５絶縁層と、前記第５絶縁層上の第６絶縁層と、を有し、
    　前記第４絶縁層と前記第６絶縁層のそれぞれは、窒素およびシリコンを有し、
    　前記第５絶縁層は、酸素およびシリコンを有する半導体装置。     In claim 10 or claim 11,
    The second insulating layer includes a fourth insulating layer, a fifth insulating layer on the fourth insulating layer, and a sixth insulating layer on the fifth insulating layer,
    Each of the fourth insulating layer and the sixth insulating layer contains nitrogen and silicon,
    A semiconductor device in which the fifth insulating layer includes oxygen and silicon.
  15. 　請求項１４において、
    　前記第４絶縁層と前記第６絶縁層のそれぞれは、水素を有する半導体装置。     In claim 14,
    A semiconductor device in which each of the fourth insulating layer and the sixth insulating layer includes hydrogen.
  16. 　請求項１０または請求項１１において、
    　前記半導体層は、酸化物半導体を含む半導体装置。     In claim 10 or claim 11,
    A semiconductor device in which the semiconductor layer includes an oxide semiconductor.
  17. 　請求項１０または請求項１１において、
    　前記第１絶縁層は、ハフニウム、ジルコニウム、および酸素を含む半導体装置。     In claim 10 or claim 11,
    A semiconductor device in which the first insulating layer contains hafnium, zirconium, and oxygen.
  18. 　請求項１０または請求項１１において、
    　前記第１導電層および前記第２導電層は、チタンおよび窒素を含む半導体装置。     In claim 10 or claim 11,
    A semiconductor device in which the first conductive layer and the second conductive layer contain titanium and nitrogen.
  19. 　請求項１０または請求項１１において、
    　前記第４導電層は前記トランジスタのゲート電極として機能し、
    　前記第３導電層は前記トランジスタのソース電極またはドレイン電極の一方として機能し、
    　前記第２導電層は前記トランジスタのソース電極またはドレイン電極の他方として機能する半導体装置。     In claim 10 or claim 11,
    The fourth conductive layer functions as a gate electrode of the transistor,
    The third conductive layer functions as one of a source electrode or a drain electrode of the transistor,
    In the semiconductor device, the second conductive layer functions as the other of a source electrode and a drain electrode of the transistor.
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JP2016149552A (en) * 2015-02-11 2016-08-18 株式会社半導体エネルギー研究所 Semiconductor device, and manufacturing method for the same
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JP2016131253A (en) * 2011-03-03 2016-07-21 株式会社半導体エネルギー研究所 Semiconductor device
JP2016149552A (en) * 2015-02-11 2016-08-18 株式会社半導体エネルギー研究所 Semiconductor device, and manufacturing method for the same
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