WO2024031737A1 - 半导体结构及其形成方法、存储器 - Google Patents

半导体结构及其形成方法、存储器 Download PDF

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Publication number
WO2024031737A1
WO2024031737A1 PCT/CN2022/113007 CN2022113007W WO2024031737A1 WO 2024031737 A1 WO2024031737 A1 WO 2024031737A1 CN 2022113007 W CN2022113007 W CN 2022113007W WO 2024031737 A1 WO2024031737 A1 WO 2024031737A1
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Prior art keywords
chip unit
chip
substrate
conductive
chipset
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PCT/CN2022/113007
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English (en)
French (fr)
Inventor
吕开敏
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长鑫存储技术有限公司
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Publication of WO2024031737A1 publication Critical patent/WO2024031737A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads

Definitions

  • the present disclosure relates to the field of semiconductor technology, and specifically, to a semiconductor structure, a method of forming the same, and a memory.
  • Memory is widely used in mobile devices such as mobile phones and tablet computers due to its advantages such as small size, high degree of integration, and fast transmission speed.
  • it is usually necessary to stack multiple chip units together and connect each chip unit to an external circuit through wires.
  • the leads connected to different chip units are of different lengths, which can easily cause delays.
  • the present disclosure provides a semiconductor structure, a method of forming the same, and a memory, which can avoid signal delays and improve product yield.
  • a semiconductor structure including:
  • Substrate including external circuitry
  • a chipset is provided on one side of the substrate and includes a plurality of chip units spaced apart in a direction perpendicular to the substrate, and each of the chip units is electrically connected to each other;
  • a conductive structure is provided on at least one surface of the chip unit
  • One end of the lead is connected to the conductive structure, and the other end extends to the outside of the chip unit and is connected to the external circuit.
  • a method for forming a semiconductor structure including:
  • the substrate including external circuitry
  • a chipset is formed on one side of the substrate, and the chipset includes a plurality of chip units spaced apart in a direction perpendicular to the substrate, and each of the chip units is electrically connected to each other;
  • a lead is formed, one end of the lead is connected to the conductive structure, and the other end extends to the outside of the chip unit and is connected to the external circuit.
  • a memory including the semiconductor structure described in any one of the above.
  • Figure 1 is a schematic diagram of a semiconductor structure in the related art
  • Figure 2 is a schematic diagram of a semiconductor structure in the related art
  • Figure 3 is a schematic diagram of a semiconductor structure in an embodiment of the present disclosure.
  • Figure 4 is a schematic diagram of a conductive structure in an embodiment of the present disclosure.
  • Figure 5 is a schematic diagram of a connection part in an embodiment of the present disclosure.
  • Figure 6 is a schematic diagram of a connection part in an embodiment of the present disclosure.
  • Figure 7 is a schematic diagram of an insulating filling layer in an embodiment of the present disclosure.
  • FIG. 8 is a flowchart of a method of forming a semiconductor structure in an embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments.
  • the same reference numerals in the drawings indicate the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • a common memory mainly includes a substrate 100 and a chip unit 200 disposed on the substrate 100.
  • multiple chip units 200 are usually stacked.
  • each chip unit 200 needs to connect the chip unit 200 with the external circuit 110 in the substrate 100 through its corresponding lead 300, so as to transmit the data in the chip unit 200 to the external circuit. 110 in.
  • the leads 300 connected thereto have different lengths, which easily causes signal delays.
  • signal delays are usually avoided by winding inside the chip unit 200 or by performing winding compensation externally. However, this will increase the size of the memory and easily cause signal interference during wiring. At the same time, it is not conducive to stacking more chip units 200, resulting in lower device integration and lower storage capacity.
  • Figure 3 shows a schematic diagram of the semiconductor structure in the embodiment of the present disclosure.
  • the semiconductor structure may include a substrate 1, a chipset 2, and a conductive structure. 3 and lead 4, where:
  • the substrate 1 may include an external circuit 11;
  • the chipset 2 can be disposed on one side of the substrate 1 and includes a plurality of chip units 21 spaced apart in a direction perpendicular to the substrate 1, and each chip unit 21 can be electrically connected to each other;
  • the conductive structure 3 can be provided at least on the surface of a chip unit 21;
  • One end of the lead 4 is connected to the conductive structure 3 , and the other end extends to the outside of the chip unit 21 and is connected to the external circuit 11 .
  • the semiconductor structure of the present disclosure can stack multiple chip units 21 in the vertical direction, which helps to increase storage capacity.
  • data in multiple different chip units 21 can be transmitted to the same chip unit 21.
  • the lead 4 is connected to the conductive structure 3, and the data in the conductive structure 3 can be connected through the conductive structure. 3.
  • signals from multiple chip units 21 in the chipset 2 can be simultaneously transmitted to the external circuit 11 through one lead 4, thus avoiding signal transmission delays from different chip units 21 in the same chipset 2.
  • each chip unit 21 is spaced apart in a direction perpendicular to the substrate 1, space can be left for the leads 4, thereby avoiding the need for lead wires. 4 fracture, which can improve product yield.
  • the substrate 1 can have a flat plate structure, which can be rectangular, circular, elliptical, polygonal or irregular in shape, and its material can be a semiconductor material, for example, its material can be silicon, but It is not limited to silicon or other semiconductor materials, and the shape and material of the substrate 1 are not specifically limited here.
  • the substrate 1 may include a central area and a peripheral area, the central area and the peripheral area may be adjacently distributed, the peripheral area may surround the periphery of the central area, the central area may be used to form the chipset 2 , and the peripheral area may be used to form the external circuit 11 .
  • the central area can be a circular area, a rectangular area or an irregular graphic area. Of course, it can also be an area of other shapes, which is not specifically limited here.
  • the peripheral area can be an annular area and can surround the outer periphery of the central area. It can be a circular annular area, a rectangular annular area or annular areas of other shapes, which are not listed here.
  • the chipset 2 can be disposed on one side of the substrate 1, and the chipset 2 can be used in integrated circuits. For example, it can be used in dynamic random access memory (DRAM, Dynamic Random Access Memory) or static random access memory (static In random access memory (SRAM), in order to achieve low driving voltage, the size of the DRAM or SRAM needs to be reduced as much as possible.
  • the chip unit 21 is the core component of the DRAM or SRAM. In order to reduce the size of the DRAM or SRAM while ensuring the storage capacity , multiple chip units 21 can be stacked in a direction perpendicular to the substrate 1 to form a chipset 2. For example, the number of chip units 21 in the chipset 2 can be 2, 3, 4, or 5. , 6 or 7, of course, it can also be other quantities, there is no special limit here.
  • each chip unit 21 in the chipset 2 can be electrically connected to each other, which facilitates the mutual transmission of data in multiple chip units 21 and thus facilitates the integration of multiple different chip units 21
  • the data in the chip unit 21 is transmitted to the same chip unit 21, so that the electrical signals in each chip unit 21 in the chipset 2 can be simultaneously transmitted to the leads 4 through the conductive structure 3, and then the chip unit 21 and the external circuit 11 can be connected through the leads 4. connection for signal transmission.
  • each chip unit 21 in the chipset 2 can be spaced apart in a direction perpendicular to the substrate 1 to leave room for the subsequently formed leads 4 to avoid breakage of the leads 4 , which can improve product yield.
  • each chip unit 21 may be equally spaced in a direction perpendicular to the substrate 1 .
  • two adjacent chip units 21 may be spaced apart by a preset distance.
  • the spacing between the chip units 21 may not be completely equal.
  • the spacing between at least two chip units 21 among the plurality of chip units 21 is not equal to the spacing between other two adjacent chip units 21 . .
  • the preset distance may be 10um-150um.
  • the preset distance may be 10um, 40um, 70um, 100um, 130um or 150um.
  • the preset distance may also be other values. I won’t list them all here.
  • the chip unit 21 may have a sheet-like structure, and its shape may be rectangular, circular, elliptical or irregular, which is not specifically limited here.
  • the thickness of each chip unit 21 may be the same or different, and is not specifically limited here.
  • the thickness of the chip unit 21 may be 40um-80um. For example, it may be 40um, 50um, 60um, 70um or 80um. Of course, it can also be other thicknesses, which are not listed here.
  • each chip unit 21 in the chipset 2 may have the same thickness.
  • the thickness of each chip unit 21 may be 50 ⁇ m, or the thickness of each chip unit 21 may be 50 ⁇ m. 60um, or the thickness of each chip unit 21 can be 70um; of course, each chip unit 21 can also have other thicknesses, which are not listed here.
  • the chip unit 21 may include a wafer and a circuit module disposed on the surface of the wafer, and the chipset 2 may include two chip units 21 .
  • the two chip units may be 21 are respectively defined as a first chip unit 211 and a second chip unit 212.
  • the second chip unit 212 may be located on a side of the first chip unit 211 away from the substrate 1, and the first chip unit 211 and the second chip unit 212 may be mirror images.
  • the arrangement, that is, the first chip unit 211 and the second chip unit 212 are exactly the same, and the circuit module of the first chip unit 211 can be arranged opposite to the circuit module of the second chip unit 212.
  • the conductive structure 3 can be disposed on the surface of at least one chip unit 21.
  • the conductive structure 3 can be disposed on the surface of any chip unit 21 in the chipset 2, and can be connected with the circuit module on the surface of the chip unit 21. Through contact connection, the circuit module of the chip unit 21 can be electrically drawn out through the conductive structure 3 , so that the data signal in the chip unit 21 can be transmitted to the external circuit 11 through the conductive structure 31 .
  • the conductive structure 3 can be disposed on the surface of the chip unit 21 closest to the substrate 1 in the chipset 2.
  • the length of the leads 4 subsequently connected to the conductive structure 3 can be shortened to the greatest extent, thereby shortening the chip unit 21.
  • the signal transmission time of the signal in the circuit 11 is transmitted to the external circuit 11, which helps to improve the signal transmission efficiency; at the same time, it can also save the materials required for making the lead 4 and reduce the manufacturing cost.
  • the chipset 2 includes a first chip unit 211 and a second chip unit 212 arranged in a mirror image, and the second chip unit 212 may be located on a side of the first chip unit 211 away from the substrate 1 , the conductive structure 3 may It is provided on the surface of the first chip unit 211 close to the second chip unit 212 .
  • conductive structures 3 can be formed on the surface of each chip unit 21, and the conductive structures 3 of each chip unit 21 are in contact with the chip.
  • the circuit modules of unit 21 are contact-connected.
  • the subsequently formed leads 4 can be connected to the conductive structure 3 on the surface of any chip unit 21 .
  • the conductive structure 3 may include a wiring layer 31, a connection pad 32 and a first conductive bump 33, wherein:
  • the wiring layer 31 can be provided on the surface of the chip unit 21 . It can be a film formed on the surface of the chip unit 21 , or it can be a coating formed on the surface of the chip unit 21 .
  • the specific form of the wiring layer 31 is not particularly limited here.
  • the material of the wiring layer 31 can be a conductive material, for example, the material can be a metal or other conductive material, and can be formed on the chip unit 21 by vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition or atomic layer deposition.
  • the wiring layer 31 is formed on the surface. Of course, the wiring layer 31 can also be formed by other methods.
  • the formation method of the wiring layer 31 is not particularly limited here.
  • connection pad 32 can be disposed on the surface of the chip unit 21 , and the connection pad 32 can be made of conductive material, for example, the material can be gold, silver, copper, aluminum or tungsten.
  • the connection pads 32 may be bonding pads formed on the surface of the chip unit 21 , and may be connected to the wiring layer 31 by soldering; in other embodiments of the present disclosure, the connection pads 32 may be a thin film formed on the surface of the chip unit 21 , or may be a coating formed on the surface of the chip unit 21 .
  • the specific form of the connection pad 32 is not particularly limited here. It can be formed by vacuum evaporation or magnetron sputtering.
  • the connection pads 32 are formed on the surface of the chip unit 21 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. Of course, the connection pads 32 can also be formed by other methods, and the formation method of the connection pads 32 is not particularly limited here.
  • connection pad 32 can be provided on the side of the wiring layer 31 close to the edge of the chip unit 21. And it can be in contact with the side of the wiring layer 31 close to the edge of the chip unit 21 .
  • the first conductive bump 33 can be disposed on the surface of the chip unit 21 , and its orthographic projection on the substrate 1 does not overlap with the orthographic projection of the connection pad 32 on the substrate 1 .
  • the first conductive bumps 33 can be in contact with the circuit module of the chip unit 21.
  • the first conductive bumps 33 can also be in contact with the wiring layer 31.
  • the first conductive bumps 33 can be used to connect the circuit modules of the chip unit 21 to each other.
  • the data signal is transmitted to the connection pad 32 through the wiring layer 31, so that the data signal is subsequently transmitted to the external circuit 11 through the lead 4 connected to the connection pad 32.
  • the first conductive bump 33 may be made of conductive material, for example, the material may be gold, silver, copper, aluminum or tungsten.
  • the first conductive bump 33 may be a soldering pad formed on the surface of the chip unit 21, and may be connected to the wiring layer 31 and the external circuit 11 of the chip unit 21 by soldering; in In other embodiments of the present disclosure, the first conductive bumps 33 may be a film formed on the surface of the chip unit 21 , or may be a coating formed on the surface of the chip unit 21 .
  • the first conductive bumps 33 are not used here. The specific form is specially limited.
  • the first conductive bumps 33 can be formed on the surface of the chip unit 21 by vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition or atomic layer deposition. Of course, the first conductive bumps 33 can also be formed by The first conductive bumps 33 may be formed by other methods, and the method of forming the first conductive bumps 33 is not particularly limited here.
  • the surfaces of the first chip unit 211 and the second chip unit 212 may both be provided with conductive structures 3 , that is, the surfaces of the first chip unit 211 and the second chip unit 212 may be provided with wirings. layer 31, connection pad 32 and first conductive bump 33.
  • the first conductive bump 33 on the surface of the second chip unit 212 can be the second conductive bump 34.
  • the second conductive bump 34 can be The second chip unit 212 is close to the surface of the first chip unit 211 and is arranged opposite to the first conductive bumps 33 of the first chip unit 211 .
  • the structures of the first chip unit 211 and the second chip unit 212 can be kept consistent, that is, the structures of the first chip unit 211 and the second chip unit 212 can be made consistent.
  • the unit 211 and the second chip unit 212 are arranged as mirror images, the first conductive bumps 33 on the surface of the first chip unit 211 and the second conductive bumps 34 on the surface of the second chip unit 212 are relatively distributed.
  • the first chip unit The wiring layer 31 on the surface of 211 and the wiring layer 31 on the surface of the second chip unit 212 are arranged oppositely, and the connection pads 32 on the surface of the first chip unit 211 and the connection pads 32 on the surface of the second chip unit 212 are also arranged oppositely.
  • One end of the lead 4 can be connected to the conductive structure 3 , and the other end can extend to the outside of the chip unit 21 and be connected to the external circuit 11 on the substrate 1 .
  • the lead 4 can be in contact with the connection pad 32 , and the data signal in the chip unit 21 can be transmitted to the external circuit 11 through the lead 4 , the connection pad 32 , the wiring layer 31 and the first conductive bump 33 .
  • the two ends of the lead 4 can be connected to the conductive structure 3 and the external circuit 11 on the substrate 1 respectively by welding.
  • one end of the lead 4 can be connected to the conductive structure 3
  • the connection pads 32 are welded together, and at the same time, the other end is welded to the external circuit 11 .
  • the lead 4 can be connected to the conductive structure 3 on the surface of one chip unit 21 in the chipset 2. Since each chip unit 21 in the chipset 2 is electrically connected, multiple chip units 21 in the chipset 2 can be connected. The data in different chip units 21 is transmitted to the same chip unit 21.
  • the lead 4 is connected to the conductive structure 3 on the surface of the chip unit 21, and the electrical signal in the chip unit 21 can be transmitted to the lead 4 through the conductive structure 3. , and then connect the chip unit 21 with the external circuit 11 through the lead 4 to realize signal transmission.
  • signals from multiple chip units 21 in the chipset 2 can be simultaneously transmitted to the external circuit 11 through one wire 4 , thereby avoiding signal transmission delays in different chip units 21 in the same chipset 2 .
  • the lead 4 can be made of conductive material.
  • it can be a metal material.
  • it can be gold, silver, copper, aluminum and other metals. It can also be an alloy composed of two or more of the above materials.
  • it can also be It can be other metals with good electrical conductivity, and is not specifically limited here.
  • the lead 4 can also be made of other materials, for example, it can also be made of non-metallic materials such as polysilicon, which will not be listed here.
  • the chipset 2 of the present disclosure may further include a connection part 5 , which may be provided between two adjacent chip units 21 and may be connected to the adjacent chip unit 21
  • the first conductive bumps 33 on the surface are in contact connection.
  • the connection portion 5 may be located between the first conductive bump 33 and the second conductive bump 34, and may be connected with the first conductive bump.
  • the point 33 and the second conductive bump 34 are in contact connection.
  • the connecting portion 5 can be connected to the second conductive bumps 34 on the surface of the second chip unit 212 by soldering, and then the first conductive bumps 33 on the surface of the first chip unit 211 and the connecting portion 5 can be soldered together. .
  • connection part 5 may be made of conductive material.
  • the material may be tin, lead, silver, copper, nickel, zinc, bismuth, indium, gold, cadmium, germanium, silicon, etc.
  • the shape of the solder material composed of one or more than two materials can be hemispherical, spherical, elliptical, cylindrical, square, etc. (as shown in Figures 5 and 6), and can be connected through the first conductive bump 33.
  • the portion 5 and the second conductive bump 34 electrically connect the first chip unit 211 and the second chip unit 212 .
  • a “sandwich” structure composed of the above-mentioned first conductive bumps 33, connecting portions 5, and second conductive bumps 34 is provided between two adjacent chip units 21, so that the two adjacent chips can
  • the "sandwich” structure between the units 21 electrically connects two adjacent chip units 21 in the chipset.
  • the first conductive bumps 33 and the connecting portion 5 can be provided on the surface of the first chip unit 211 where the circuit module is installed, and only the second conductive bumps can be provided on the surface of the second chip unit 212 where the circuit module is installed.
  • the second conductive bumps 34 and the connecting portion 5 are provided on the surface of the second chip unit 212 where the circuit module is provided, and only the first conductive bumps 33 are provided on the surface of the first chip unit 211 where the circuit module is provided.
  • the conductive structures 3 can be respectively provided on two adjacent chip units 21.
  • the first conductive bumps 33 and the connecting portions 5 are provided on the first chip unit 211
  • the first conductive bumps 33 and the connecting portions 5 are provided on the second chip unit 211.
  • 212 is provided with the connecting portion 5 and the second conductive bump 34.
  • the first conductive bump 33 and the connecting portion 5 on the first chip unit 211 and the connecting portion 5 and the second conductive bump 34 on the second chip unit 212 are at The orthographic projection on the substrate 1 has no overlap, and the first chip unit 211 and the second chip unit 212 can be electrically connected through the two connection portions 5 between the first chip unit 211 and the second chip unit 212 .
  • the conductive structures 3 can be respectively provided on two adjacent chip units 21 , for example, staggered distribution of first conductive bumps 33 can be provided on the first chip unit 211 and the second chip unit 212 respectively. and second conductive bumps 34.
  • the first chip unit 211 and the second chip unit 212 can be directly electrically connected through the first conductive bumps 33 and the second conductive bumps 34.
  • the first conductive bumps 33 , the connection portions 5 and the second conductive bumps 34 may separate adjacent chip units 21 by a preset distance.
  • the chipset 2 includes a third
  • the first conductive bump 33, the connecting portion 5 and the second conductive bump 34 can separate the first chip unit 211 and the second chip unit 212 by a preset distance.
  • the preset distance may be greater than the longitudinal spacing required for bending the lead 4 , and one end of the lead 4 connected to the connection pad 32 may be bent at a preset distance separated by the first chip unit 211 and the second chip unit 212 . Folding can avoid breakage of lead 4 and improve product yield.
  • the semiconductor structure of the present disclosure may further include an insulating filling layer 6 , through which the adjacent chip units 21 can be insulated and isolated to avoid each other. Signal crosstalk or coupling occurs between chip units 21 .
  • the material of the insulating filling layer 6 can be insulating glue or encapsulating glue, which can isolate external water and oxygen through the insulating filling layer 6 and prevent external water and oxygen from entering the inside of the chip unit 21, thereby preventing external water and oxygen from entering the chip unit 21. Preventing water and oxygen from corroding the internal structure of the chip unit 21 can extend the service life of the chip unit 21 .
  • the insulating filling layer 6 can fill the gap between adjacent chip units 21 , and the gap between two adjacent chip units 21 can be supported by the insulating filling layer 6 , while , it can also balance the stress between two adjacent chip units 21, reduce the possibility of each chip unit 21 being broken by external force, and improve product yield.
  • the insulating filling layer 6 in the chipset 2 may be a thick layer, and each chip unit 21 may be buried in the insulating filling layer 6 .
  • an insulating filling layer 6 can be formed on the surface of the structure formed by the substrate 1 and the chipset 2 .
  • the insulating filling layer 6 can fill the gaps between the chip units 21 and connect each chip unit 21 The side walls of the chip are covered inside, thereby achieving all-round isolation and protection of each chip unit 21.
  • the insulating filling layer 6 may include a plurality of insulating layers distributed at intervals, and the number of insulating layers may match the number of gaps between each chip unit 21 .
  • the number of insulating layers can be one less than the number of chip units 21.
  • Each insulating layer can be distributed between two adjacent chip units 21 in one-to-one correspondence.
  • the thickness of the insulating layer can be the same as that between adjacent chip units 21.
  • the spacing between adjacent chip units 21 is equal, that is, the insulating layer can fill the gaps between adjacent chip units 21 .
  • each insulating layer and each chip set 2 After the structure composed of each insulating layer and each chip set 2 is fixed on the substrate 1, the surface of the structure composed of each insulating layer, each chip set 2 and the substrate 1 can be further filled. Insulating material, and then each chipset 2 is buried in the insulating material.
  • the insulating material can form the insulating filling layer 6 together with each insulating layer.
  • the materials of the insulating material and the insulating layer can be the same or different, and are not specifically limited here. .
  • the material of the insulating material and the insulating layer can both be insulating glue or encapsulating glue; or, the material of any one of the insulating material and the insulating layer can be insulating glue, and the material of the other can be encapsulating glue.
  • the number of chipsets 2 may be multiple, and the plurality of chipsets 2 may be stacked and distributed in a direction perpendicular to the substrate 1.
  • the number of chipsets 2 can be 2, 3, 4, 5, 6 or 7. Of course, it can also be other numbers, which are not specifically limited here.
  • the number of chip units 21 in different chipsets 2 may be equal.
  • the number of chip units 21 in each chipset 2 may be two; or, each chipset may The number of chip units 21 in each chipset 2 may be 3, or the number of chip units 21 in each chipset 2 may be 3.
  • the number of chip units 21 in each chipset 2 may also be 3. Other values are not listed here.
  • the number of chip units 21 in different chipsets 2 may not be equal.
  • the number of chip units 21 in some chipsets 2 in each chipset 2 is 2, and in others The number of chip units 21 in the chipset 2 is 3; for another example, the number of chip units 21 in some chipsets 2 in each chipset 2 is 3, and the number of chip units 21 in other chipsets 2 is 4; of course, the number of chip units 21 in each chipset 2 can also be other values, which will not be listed here.
  • each chipset 2 can be insulated from each other to avoid crosstalk between data in different chipsets 2 .
  • Each chipset 2 has a corresponding conductive structure 3 and leads 4 , and data in different chipsets 2 can be transmitted to the external circuit 11 through different leads 4 .
  • the semiconductor structure of the present disclosure may also include a plurality of packaging layers 8 .
  • Each packaging layer 8 may be disposed between each chipset 2 in one-to-one correspondence and may fill the spaces between each chipset 2 . the gap between.
  • the packaging layer 8 can be used to isolate external water and oxygen, prevent external water and oxygen from entering the inside of the chipset 2, thereby preventing water and oxygen from corroding the internal structure of the chipset 2, and extending the service life of the chipset 2.
  • the material of the encapsulation layer 8 can be insulating non-conductive glue or encapsulation glue. Adjacent chipsets 2 can be insulated and isolated through the encapsulation layer 8 to avoid conflicts between the chipsets 2 . Signal crosstalk or coupling occurs between them.
  • the number of packaging layers 8 may match the number of each chipset 2 .
  • the number of packaging layers 8 may be one less than the number of chipsets 2 .
  • Each packaging layer 8 may be one by one. The corresponding ones are distributed between two adjacent chipsets 2 , and the orthographic projection of the packaging layer 8 on the substrate 1 can at least coincide with the orthographic projection of the chipset 2 on the substrate 1 . It should be noted that each packaging layer 8 can also be connected together to completely cover each chipset 2, thereby achieving all-round packaging of each chipset 2.
  • the semiconductor structure of the present disclosure may further include an adhesive layer 7 , and the adhesive layer 7 may be provided between the substrate 1 and the chipset 2 closest to the substrate 1 .
  • the material of the adhesive layer 7 can be conductive glue, and the chipset 2 closest to the substrate 1 can be pasted on the surface of the substrate 1 through the adhesive layer 7 to prevent the chipset 2 from shaking relative to the substrate 1 .
  • the orthographic projection of the adhesive layer 7 on the substrate 1 does not overlap with the external circuit 11 , that is, the adhesive layer 7 can expose the external circuit 11 to facilitate the connection between the external circuit 11 and the lead 4 .
  • the adhesive layer 7 may be located in the middle area of the substrate 1 , and its orthographic projection on the substrate 1 may coincide with the orthographic projection on the substrate 1 of the chipset 2 closest to the substrate 1 .
  • the embodiment of the present disclosure may also include a plurality of solder balls 9 , which may be disposed on a side of the substrate 1 away from the chipset 2 , and electrical signals in the chip unit 21 may be transmitted to external circuits through the solder balls 9 .
  • Embodiments of the present disclosure also provide a method for forming a semiconductor structure.
  • FIG. 8 shows a flow chart of a method for forming a semiconductor structure of the present disclosure. Referring to FIG. 8 , the forming method may include step S110 to step S140, wherein:
  • Step S110 providing a substrate including an external circuit
  • Step S120 forming a chipset on one side of the substrate.
  • the chipset includes a plurality of chip units spaced apart in a direction perpendicular to the substrate, and each of the chip units is electrically connected to each other;
  • Step S130 forming a conductive structure on at least one surface of the chip unit
  • Step S140 Form a lead. One end of the lead is connected to the conductive structure, and the other end extends to the outside of the chip unit and is connected to the external circuit.
  • the semiconductor structure chip forming method of the present disclosure can stack multiple chip units 21 in a vertical direction, which helps to increase storage capacity.
  • data in multiple different chip units 21 can be transmitted to the same chip unit 21.
  • the lead 4 is connected to the conductive structure 3, and the data in the conductive structure 3 can be connected through the conductive structure. 3.
  • signals from multiple chip units 21 in the chipset 2 can be simultaneously transmitted to the external circuit 11 through one lead 4, thus avoiding signal transmission delays from different chip units 21 in the same chipset 2.
  • each chip unit 21 is spaced apart in a direction perpendicular to the substrate 1, space can be left for the leads 4, thereby avoiding the need for lead wires. 4 fracture, which can improve product yield.
  • step S110 a substrate is provided, and the substrate includes an external circuit.
  • the substrate 1 can have a flat plate structure, which can be rectangular, circular, elliptical, polygonal or irregular in shape, and its material can be a semiconductor material, for example, its material can be silicon, but It is not limited to silicon or other semiconductor materials, and the shape and material of the substrate 1 are not specifically limited here.
  • the substrate 1 may include a central area and a peripheral area, the central area and the peripheral area may be adjacently distributed, the peripheral area may surround the periphery of the central area, the central area may be used to form the chipset 2 , and the peripheral area may be used to form the external circuit 11 .
  • the central area can be a circular area, a rectangular area or an irregular graphic area. Of course, it can also be an area of other shapes, which is not specifically limited here.
  • the peripheral area can be an annular area and can surround the outer periphery of the central area. It can be a circular annular area, a rectangular annular area or annular areas of other shapes, which are not listed here.
  • a chipset is formed on one side of the substrate.
  • the chipset includes a plurality of chip units spaced apart in a direction perpendicular to the substrate. Each chip unit electrical connection between them.
  • the chipset 2 can be disposed on one side of the substrate 1, and the chipset 2 can be used in integrated circuits. For example, it can be used in dynamic random access memory (DRAM, Dynamic Random Access Memory) or static random access memory (static In random access memory (SRAM), in order to achieve low driving voltage, the size of the DRAM or SRAM needs to be reduced as much as possible.
  • the chip unit 21 is the core component of the DRAM or SRAM. In order to reduce the size of the DRAM or SRAM while ensuring the storage capacity , multiple chip units 21 can be stacked in a direction perpendicular to the substrate 1 to form a chipset 2. For example, the number of chip units 21 in the chipset 2 can be 2, 3, 4, or 5. , 6 or 7, of course, it can also be other quantities, there is no special limit here.
  • each chip unit 21 in the chipset 2 can be electrically connected to each other, which facilitates the mutual transmission of data in multiple chip units 21 and thus facilitates the integration of multiple different chip units 21
  • the data in the chip unit 21 is transmitted to the same chip unit 21, so that the electrical signals in each chip unit 21 in the chipset 2 are subsequently transmitted to the leads 4 through the conductive structure 3, and then the chip unit 21 is connected to the external circuit 11 through the leads 4. , to achieve signal transmission.
  • each chip unit 21 in the chipset 2 can be spaced apart in a direction perpendicular to the substrate 1 to leave room for the subsequently formed leads 4 to avoid breakage of the leads 4 , which can improve product yield.
  • each chip unit 21 may be equally spaced in a direction perpendicular to the substrate 1 .
  • two adjacent chip units 21 may be spaced apart by a preset distance.
  • the spacing between the chip units 21 may not be completely equal.
  • the spacing between at least two chip units 21 among the plurality of chip units 21 is not equal to the spacing between other two adjacent chip units 21 . .
  • the preset distance may be 10um-150um.
  • the preset distance may be 10um, 40um, 70um, 100um, 130um or 150um.
  • the preset distance may also be other values. I won’t list them all here.
  • the chip unit 21 may have a sheet-like structure, and its shape may be rectangular, circular, elliptical or irregular, which is not specifically limited here.
  • the thickness of each chip unit 21 may be the same or different, and is not specifically limited here.
  • the thickness of the chip unit 21 may be 40um-80um. For example, it may be 40um, 50um, 60um, 70um or 80um. Of course, it can also be other thicknesses, which are not listed here.
  • each chip unit 21 in the chipset 2 may have the same thickness.
  • the thickness of each chip unit 21 may be 50 ⁇ m, or the thickness of each chip unit 21 may be 50 ⁇ m. 60um, or the thickness of each chip unit 21 can be 70um; of course, each chip unit 21 can also have other thicknesses, which are not listed here.
  • the chip unit 21 may include a wafer and a circuit module disposed on the surface of the wafer, and the chipset 2 may include two chip units 21 .
  • the two chip units may be 21 are respectively defined as a first chip unit 211 and a second chip unit 212.
  • the second chip unit 212 may be located on a side of the first chip unit 211 away from the substrate 1, and the first chip unit 211 and the second chip unit 212 may be mirror images.
  • the arrangement, that is, the first chip unit 211 and the second chip unit 212 are exactly the same, and the circuit module of the first chip unit 211 can be arranged opposite to the circuit module of the second chip unit 212.
  • a conductive structure is formed on at least one surface of the chip unit.
  • the conductive structure 3 can be disposed on the surface of at least one chip unit 21.
  • the conductive structure 3 can be disposed on the surface of any chip unit 21 in the chipset 2, and can be connected with the circuit module on the surface of the chip unit 21. Through contact connection, the circuit module of the chip unit 21 can be electrically drawn out through the conductive structure 3 , so that the data signal in the chip unit 21 can be transmitted to the external circuit 11 through the conductive structure 31 .
  • the conductive structure 3 can be disposed on the surface of the chip unit 21 closest to the substrate 1 in the chipset 2.
  • the length of the leads 4 subsequently connected to the conductive structure 3 can be shortened to the greatest extent, thereby shortening the chip unit 21.
  • the signal transmission time of the signal in the circuit 11 is transmitted to the external circuit 11, which helps to improve the signal transmission efficiency; at the same time, it can also save the materials required for making the lead 4 and reduce the manufacturing cost.
  • the chipset 2 includes a first chip unit 211 and a second chip unit 212 arranged in a mirror image, and the second chip unit 212 may be located on a side of the first chip unit 211 away from the substrate 1 , the conductive structure 3 may It is provided on the surface of the first chip unit 211 close to the second chip unit 212 .
  • conductive structures 3 can be formed on the surface of each chip unit 21, and the conductive structures 3 of each chip unit 21 are in contact with the chip.
  • the circuit modules of unit 21 are contact-connected.
  • the subsequently formed leads 4 can be connected to the conductive structure 3 of any chip unit 21 .
  • forming the conductive structure 3 on at least the surface of one chip unit 21 may include steps S210 to S230, wherein:
  • Step S210 Form a wiring layer 31 on the surface of at least one chip unit 21.
  • the wiring layer 31 can be provided on the surface of the chip unit 21 . It can be a film formed on the surface of the chip unit 21 , or it can be a coating formed on the surface of the chip unit 21 .
  • the specific form of the wiring layer 31 is not particularly limited here.
  • the material of the wiring layer 31 may be a conductive material, for example, the material may be a metal or other conductive material, and may be deposited on the chip unit 21 through vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition or atomic layer deposition.
  • the wiring layer 31 is formed on the surface. Of course, the wiring layer 31 can also be formed by other methods.
  • the formation method of the wiring layer 31 is not particularly limited here.
  • Step S220 Form a connection pad 32 on the surface of the chip unit 21 on which the wiring layer 31 is formed.
  • the connection pad 32 is connected to the side of the wiring layer 31 close to the edge of the chip unit 21.
  • the lead 4 is in contact with the connection pad 32 .
  • connection pad 32 can be disposed on the surface of the chip unit 21 , and the connection pad 32 can be made of conductive material, for example, the material can be gold, silver, copper, aluminum or tungsten.
  • the connection pads 32 may be solder pads formed on the surface of the chip unit 21 , and may be connected to the wiring layer 31 by soldering; in other embodiments of the present disclosure, the connection pads 32 may be a thin film formed on the surface of the chip unit 21 , or may be a coating formed on the surface of the chip unit 21 .
  • the specific form of the connection pad 32 is not specifically limited here. It can be formed by vacuum evaporation or magnetron sputtering.
  • the connection pads 32 are formed on the surface of the chip unit 21 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. Of course, the connection pads 32 can also be formed by other methods, and the formation method of the connection pads 32 is not specifically limited here.
  • connection pad 32 can be provided on the side of the wiring layer 31 close to the edge of the chip unit 21. And it can be in contact with the side of the wiring layer 31 close to the edge of the chip unit 21 .
  • Step S230 Form first conductive bumps 33 on the surface of the chip unit 21 on which the wiring layer 31 is formed.
  • the first conductive bumps 33 are in contact with the wiring layer 31, and the first conductive bumps 33 are in contact with the wiring layer 31.
  • the orthographic projection of the bump 33 on the substrate 1 does not overlap with the orthographic projection of the connection pad 32 on the substrate 1 .
  • the first conductive bump 33 can be disposed on the surface of the chip unit 21 , and its orthographic projection on the substrate 1 does not overlap with the orthographic projection of the connection pad 32 on the substrate 1 .
  • the first conductive bumps 33 can be in contact with the circuit module of the chip unit 21.
  • the first conductive bumps 33 can also be in contact with the wiring layer 31.
  • the first conductive bumps 33 can be used to connect the circuit modules of the chip unit 21 to each other.
  • the data signal is transmitted to the connection pad 32 through the wiring layer 31, so that the data signal is subsequently transmitted to the external circuit 11 through the lead 4 connected to the connection pad 32.
  • the first conductive bump 33 may be made of conductive material, for example, the material may be gold, silver, copper, aluminum or tungsten.
  • the first conductive bump 33 may be a connection portion 5 formed on the surface of the chip unit 21, which may be connected to the wiring layer 31 and the external circuit 11 of the chip unit 21 by soldering;
  • the first conductive bumps 33 may be a thin film formed on the surface of the chip unit 21 , or may be a coating formed on the surface of the chip unit 21 .
  • the first conductive bumps 33 are not used here. The specific form of 33 is specially limited.
  • the first conductive bumps 33 can be formed on the surface of the chip unit 21 by vacuum evaporation, magnetron sputtering, chemical vapor deposition, physical vapor deposition or atomic layer deposition. Of course, it can also be The first conductive bumps 33 are formed by other methods, and the method of forming the first conductive bumps 33 is not particularly limited here.
  • the formation of the semiconductor structure of the present disclosure may further include:
  • Step S150 forming second conductive bumps 34 on the surface of the second chip unit 212 close to the first chip unit 211 , and the second conductive bumps 34 are arranged opposite to the first conductive bumps 33 .
  • the surfaces of the first chip unit 211 and the second chip unit 212 may both be provided with conductive structures 3 , that is, the surfaces of the first chip unit 211 and the second chip unit 212 may be provided with wirings. layer 31, connection pad 32 and first conductive bump 33.
  • the first conductive bump 33 on the surface of the second chip unit 212 can be the second conductive bump 34.
  • the second conductive bump 34 can be The second chip unit 212 is close to the surface of the first chip unit 211 and is arranged opposite to the first conductive bumps 33 of the first chip unit 211 .
  • the structures of the first chip unit 211 and the second chip unit 212 can be kept consistent, that is, the structures of the first chip unit 211 and the second chip unit 212 can be made consistent.
  • the unit 211 and the second chip unit 212 are arranged as mirror images, the first conductive bumps 33 on the surface of the first chip unit 211 and the second conductive bumps 34 on the surface of the second chip unit 212 are relatively distributed.
  • the first chip unit The wiring layer 31 on the surface of 211 and the wiring layer 31 on the surface of the second chip unit 212 are arranged oppositely, and the connection pads 32 on the surface of the first chip unit 211 and the connection pads 32 on the surface of the second chip unit 212 are also arranged oppositely.
  • the formation method of the second conductive bumps 34 is similar to the formation method of the first conductive bumps 33.
  • the second conductive bumps 34 can be formed with reference to the formation method of the first conductive bumps 33.
  • the second conductive bumps 34 are not used here. The formation process of the conductive bumps 34 will not be described in detail.
  • step S140 a lead is formed, one end of the lead is connected to the conductive structure, and the other end extends to the outside of the chip unit and is connected to the external circuit.
  • One end of the lead 4 can be connected to the conductive structure 3 , and the other end can extend to the outside of the chip unit 21 and be connected to the external circuit 11 on the substrate 1 .
  • the lead 4 can be in contact with the connection pad 32 , and the data signal in the chip unit 21 can be transmitted to the external circuit 11 through the lead 4 , the connection pad 32 , the wiring layer 31 and the first conductive bump 33 .
  • the two ends of the lead 4 can be connected to the conductive structure 3 and the external circuit 11 on the substrate 1 respectively by welding.
  • one end of the lead 4 can be connected to the conductive structure 3
  • the connection pads 32 are welded together, and at the same time, the other end is welded to the external circuit 11 .
  • the lead 4 can be connected to the conductive structure 3 on the surface of one chip unit 21 in the chipset 2. Since each chip unit 21 in the chipset 2 is electrically connected, multiple chip units 21 in the chipset 2 can be connected. The data in different chip units 21 is transmitted to the same chip unit 21.
  • the lead 4 is connected to the conductive structure 3 on the surface of the chip unit 21, and the electrical signal in the chip unit 21 can be transmitted to the lead 4 through the conductive structure 3. , and then connect the chip unit 21 with the external circuit 11 through the lead 4 to realize signal transmission.
  • signals from multiple chip units 21 in the chipset 2 can be simultaneously transmitted to the external circuit 11 through one lead 4 , thus avoiding signal transmission delays of different chip units 21 in the same chipset 2 .
  • the lead 4 can be made of a conductive material.
  • it can be a metal material.
  • it can be a metal such as gold, silver, copper, aluminum, or an alloy composed of two or more of the above materials.
  • it can also be It can be other metals with better electrical conductivity, and is not specifically limited here.
  • the lead 4 can also be made of other materials, for example, it can also be made of non-metallic materials such as polysilicon, which will not be listed here.
  • forming the chipset 2 on one side of the substrate 1 may further include forming a connection part 5 on the surface of the first conductive bump 33 , and the connection part 5 may be provided on two adjacent between the chip units 21 and can be in contact with the first conductive bumps 33 on the surface of the adjacent chip units 21 .
  • the connection portion 5 is located on the first conductive bump 33 on the surface of the first chip unit 211 and the second conductive bump 33 on the surface of the second chip unit 212.
  • the first conductive bump 33 , the connecting portion 5 and the second conductive bump 34 separate the first chip unit 211 and the second chip unit 212 by a preset distance.
  • connection portion 5 may be located between the first conductive bump 33 and the second conductive bump 34, and may be connected with the first conductive bump.
  • the point 33 and the second conductive bump 34 are in contact connection.
  • the connecting portion 5 can be connected to the second conductive bumps 34 on the surface of the second chip unit 212 by soldering, and then the first conductive bumps 33 on the surface of the first chip unit 211 and the connecting portion 5 can be soldered together. .
  • connection part 5 may be made of conductive material.
  • the material may be tin, lead, silver, copper, nickel, zinc, bismuth, indium, gold, cadmium, germanium, silicon, etc.
  • the shape of the solder material composed of one or more than two materials can be hemispherical, spherical, elliptical, cylindrical, square, etc., and can be connected through the first conductive bump 33, the connecting part 5 and the second conductive bump 34.
  • the first chip unit 211 and the second chip unit 212 are electrically connected.
  • the above-mentioned first conductive bumps 33 , connection portions 5 , and second conductive bumps 34 can be disposed between two adjacent chip units 21 .
  • the formed "sandwich” structure can electrically connect two adjacent chip units 21 in the chipset 2 through the "sandwich” structure between the two adjacent chip units 21 .
  • the first conductive bumps 33 and the connecting portion 5 can be provided on the surface of the first chip unit 211 where the circuit module is installed, and only the second conductive bumps can be provided on the surface of the second chip unit 212 where the circuit module is installed.
  • the second conductive bumps 34 and the connecting portion 5 are provided on the surface of the second chip unit 212 where the circuit module is provided, and only the first conductive bumps 33 are provided on the surface of the first chip unit 211 where the circuit module is provided.
  • the conductive structures 3 can be respectively provided on two adjacent chip units 21.
  • the first conductive bumps 33 and the connecting portions 5 are provided on the first chip unit 211
  • the first conductive bumps 33 and the connecting portions 5 are provided on the second chip unit 211.
  • 212 is provided with the connecting portion 5 and the second conductive bump 34.
  • the first conductive bump 33 and the connecting portion 5 on the first chip unit 211 and the connecting portion 5 and the second conductive bump 34 on the second chip unit 212 are at The orthographic projection on the substrate 1 has no overlap, and the first chip unit 211 and the second chip unit 212 can be electrically connected through the two connection portions 5 between the first chip unit 211 and the second chip unit 212 .
  • the conductive structures 3 can be respectively provided on two adjacent chip units 21 , for example, staggered distribution of first conductive bumps 33 can be provided on the first chip unit 211 and the second chip unit 212 respectively. and second conductive bumps 34.
  • the first chip unit 211 and the second chip unit 212 can be directly electrically connected through the first conductive bumps 33 and the second conductive bumps 34.
  • the first conductive bumps 33 , the connection portions 5 and the second conductive bumps 34 may separate adjacent chip units 21 by a preset distance.
  • the chipset 2 includes a third
  • the first conductive bump 33, the connecting portion 5 and the second conductive bump 34 can separate the first chip unit 211 and the second chip unit 212 by a preset distance.
  • the preset distance For setting the distance, reference may be made to the preset distance in the above embodiment, which will not be described again here.
  • the preset distance may be greater than the longitudinal spacing required for bending the lead 4 , and one end of the lead 4 connected to the connection pad 32 may be bent at a preset distance separated by the first chip unit 211 and the second chip unit 212 . Folding can avoid breakage of lead 4 and improve product yield.
  • the method for forming the semiconductor structure of the present disclosure may further include:
  • step S160 an insulating filling layer 6 is formed, and the insulating filling layer 6 fills the gap between the adjacent chip units 21.
  • the insulating filling layer 6 can be disposed between two adjacent chip units 21 .
  • the insulating filling layer 6 can be formed between two adjacent chip units 21 by spin coating or coating.
  • the insulating filling layer 6 insulates and isolates adjacent chip units 21 to avoid signal crosstalk or coupling between the chip units 21 .
  • the material of the insulating filling layer 6 can be insulating glue or encapsulating glue, which can isolate external water and oxygen through the insulating filling layer 6 and prevent external water and oxygen from entering the inside of the chip unit 21, thereby preventing external water and oxygen from entering the chip unit 21. Preventing water and oxygen from corroding the internal structure of the chip unit 21 can extend the service life of the chip unit 21 .
  • the insulating filling layer 6 can fill the gap between adjacent chip units 21 , and the gap between two adjacent chip units 21 can be supported by the insulating filling layer 6 , while , it can also balance the stress between two adjacent chip units 21, reduce the possibility of each chip unit 21 being broken by external force, and improve product yield.
  • the insulating filling layer 6 in the chipset 2 may be a thick layer, and each chip unit 21 may be buried in the insulating filling layer 6 .
  • an insulating filling layer 6 can be formed on the surface of the structure formed by the substrate 1 and the chipset 2 .
  • the insulating filling layer 6 can fill the gaps between the chip units 21 and connect each chip unit 21 The side walls of the chip are covered inside, thereby achieving all-round isolation and protection of each chip unit 21.
  • the insulating filling layer 6 may include a plurality of insulating layers distributed at intervals, and the number of insulating layers may match the number of gaps between each chip unit 21 .
  • the number of insulating layers can be one less than the number of chip units 21.
  • Each insulating layer can be distributed between two adjacent chip units 21 in one-to-one correspondence.
  • the thickness of the insulating layer can be the same as that between adjacent chip units 21.
  • the spacing between adjacent chip units 21 is equal, that is, the insulating layer can fill the gaps between adjacent chip units 21 .
  • each insulating layer and each chip set 2 After the structure composed of each insulating layer and each chip set 2 is fixed on the substrate 1, the surface of the structure composed of each insulating layer, each chip set 2 and the substrate 1 can be further filled. Insulating material, and then each chipset 2 is buried in the insulating material.
  • the insulating material can form the insulating filling layer 6 together with each insulating layer.
  • the materials of the insulating material and the insulating layer can be the same or different, and are not specifically limited here. .
  • the material of the insulating material and the insulating layer can both be insulating glue or encapsulating glue; or, the material of any one of the insulating material and the insulating layer can be insulating glue, and the material of the other can be encapsulating glue.
  • the number of chipsets 2 may be multiple, and the plurality of chipsets 2 may be stacked and distributed in a direction perpendicular to the substrate 1.
  • the number of chipsets 2 can be 2, 3, 4, 5, 6 or 7. Of course, it can also be other numbers, which are not specifically limited here.
  • the number of chip units 21 in different chipsets 2 may be equal.
  • the number of chip units 21 in each chipset 2 may be two; or, each chipset may The number of chip units 21 in each chipset 2 may be 3, or the number of chip units 21 in each chipset 2 may be 3.
  • the number of chip units 21 in each chipset 2 may also be 3. Other values are not listed here.
  • the number of chip units 21 in different chipsets 2 may not be equal.
  • the number of chip units 21 in some chipsets 2 in each chipset 2 is 2, and in others The number of chip units 21 in the chipset 2 is 3; for another example, the number of chip units 21 in some chipsets 2 in each chipset 2 is 3, and the number of chip units 21 in other chipsets 2 is 4; of course, the number of chip units 21 in each chipset 2 can also be other values, which will not be listed here.
  • each chipset 2 can be insulated from each other to avoid crosstalk between data in different chipsets 2 .
  • Each chipset 2 has a corresponding conductive structure 3 and leads 4 , and data in different chipsets 2 can be transmitted to the external circuit 11 through different leads 4 .
  • the method of forming the semiconductor structure of the present disclosure may further include:
  • step S170 a plurality of packaging layers 8 are formed.
  • Each of the packaging layers 8 can be disposed between the chipsets 2 in one-to-one correspondence, and can fill the gaps between the chipsets 2.
  • the material of the encapsulation layer 8 can be insulating non-conductive glue or encapsulation glue, and the encapsulation layer can be formed between two adjacent chipsets 2 by spin coating or coating. 8.
  • the adjacent chipsets 2 can be insulated and isolated through the packaging layer 8 to avoid signal crosstalk or coupling between the chipsets 2; at the same time, the packaging layer 8 can also be used to isolate external water and oxygen to prevent external water and oxygen. Enter the inside of the chipset 2 to prevent water and oxygen from corroding the internal structure of the chipset 2, thereby extending the service life of the chipset 2.
  • the number of packaging layers 8 may match the number of each chipset 2 .
  • the number of packaging layers 8 may be one less than the number of chipsets 2 .
  • Each packaging layer 8 may be one by one. The corresponding ones are distributed between two adjacent chipsets 2 , and the orthographic projection of the packaging layer 8 on the substrate 1 can at least coincide with the orthographic projection of the chipset 2 on the substrate 1 . It should be noted that each packaging layer 8 can also be connected together to completely cover each chipset 2, thereby achieving all-round packaging of each chipset 2.
  • the semiconductor structure of the present disclosure may further include:
  • step S180 an adhesive layer 7 is formed between the substrate 1 and the chipset 2 closest to the substrate 1.
  • the material of the adhesive layer 7 can be conductive glue, and the chipset 2 closest to the substrate 1 can be pasted on the surface of the substrate 1 through the adhesive layer 7 to prevent the chipset 2 from shaking relative to the substrate 1 .
  • the orthographic projection of the adhesive layer 7 on the substrate 1 does not overlap with the external circuit 11 , that is, the adhesive layer 7 can expose the external circuit 11 to facilitate the connection between the external circuit 11 and the lead 4 .
  • the adhesive layer 7 may be located in the middle area of the substrate 1 , and its orthographic projection on the substrate 1 may coincide with the orthographic projection on the substrate 1 of the chipset 2 closest to the substrate 1 .
  • the embodiment of the present disclosure may also include a plurality of solder balls 9 , which may be disposed on a side of the substrate 1 away from the chipset 2 , and electrical signals in the chip unit 21 may be transmitted to external circuits through the solder balls 9 .
  • Embodiments of the present disclosure also provide a memory, which may include the semiconductor structure in any of the above embodiments.
  • a memory which may include the semiconductor structure in any of the above embodiments.
  • the specific details, formation process and beneficial effects have been described in detail in the corresponding semiconductor structure and the method of forming the semiconductor structure. , which will not be described again here.
  • the memory can be dynamic random access memory (Dynamic Random Access Memory, DRAM), static random access memory (static random access memory, SRAM), etc.
  • DRAM Dynamic Random Access Memory
  • SRAM static random access memory
  • other storage devices may also be used, which are not listed here.

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Abstract

一种半导体结构及其形成方法、存储器；属于半导体技术领域。所述半导体结构包括衬底（1）、芯片组（2）、导电结构（3）及引线（4），其中：衬底包括外接电路（11）；芯片组（2）设于衬底（1）的一侧，且包括多个沿垂直于衬底的方向间隔分布的芯片单元（21），各芯片单元（21）之间电性连接；导电结构（3）至少设于一芯片单元（21）的表面；引线（4）一端与导电结构（3）连接，另一端延伸至芯片单元（21）外侧，并与外接电路（11）连接。所述半导体结构可避免信号延时，提高产品良率。

Description

半导体结构及其形成方法、存储器
交叉引用
本公开要求于2022年8月12日提交的申请号为202210970472.4名称为“半导体结构及其形成方法、存储器”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体技术领域，具体而言，涉及一种半导体结构及其形成方法、存储器。
背景技术
存储器因具有体积小、集成化程度高及传输速度快等优点，被广泛应用于手机、平板电脑等移动设备中。为了提高存储器的存储容量，通常需要将多个芯片单元叠加在一起，并通过引线将各芯片单元与外部电路相连接。但是，不同的芯片单元连接的引线长短不一，易产生延时。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
有鉴于此，本公开提供一种半导体结构及其形成方法、存储器，可避免信号延时，提高产品良率。
根据本公开的一个方面，提供一种半导体结构，包括：
衬底，包括外接电路；
芯片组，设于所述衬底的一侧，且包括多个沿垂直于所述衬底的方向间隔分布的芯片单元，各所述芯片单元之间电性连接；
导电结构，至少设于一所述芯片单元的表面；
引线，一端与所述导电结构连接，另一端延伸至所述芯片单元外侧，并与所述外接电路连接。
根据本公开的一个方面，提供一种半导体结构的形成方法，包括：
提供衬底，所述衬底包括外接电路；
在所述衬底的一侧形成芯片组，所述芯片组包括多个沿垂直于所述衬底的方向间隔分布的芯片单元，各所述芯片单元之间电性连接；
在至少设于一所述芯片单元的表面形成导电结构；
形成引线，所述引线的一端与所述导电结构连接，另一端延伸至所述芯片单元外侧，并与所述外接电路连接。
根据本公开的一个方面，提供一种存储器，包括上述任意一项所述 的半导体结构。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中一半导体结构的示意图；
图2为相关技术中一半导体结构的示意图；
图3为本公开的一实施方式中半导体结构的示意图；
图4为本公开实施方式中导电结构的示意图；
图5为本公开一实施方式中连接部的示意图；
图6为本公开一实施方式中连接部的示意图；
图7为本公开一实施方式中绝缘填充层的示意图；
图8为本公开实施方式中半导体结构的形成方法的流程图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
在相关技术中，如图1及图2所示，常见的存储器主要包括衬底100 及设置于衬底100上的芯片单元200，为了保证存储器的存储容量，通常将多个芯片单元200叠层设置于衬底100上，每个芯片单元200都需要通过与之对应的引线300将芯片单元200与衬底100中的外接电路110连接在一起，以便将芯片单元200中的数据传输至外接电路110中。然而，由于各芯片单元200的高度不同，致使与其连接的引线300的长短不一，易产生信号延时。目前，通常通过在芯片单元200内部进行绕线或者外部进行绕线补偿的方式避免信号延时。但是，这样会导致存储器的体积增大，且绕线时易产生信号干扰。同时，不利于更多芯片单元200的堆叠，致使器件集成度和存储容量较低。
基于此，本公开实施方式提供了一种半导体结构，图3示出了本公开实施方式中半导体结构的示意图，参见图3所示，该半导体结构可包括衬底1、芯片组2、导电结构3及引线4，其中：
衬底1可包括外接电路11；
芯片组2可设于衬底1的一侧，且包括多个沿垂直于衬底1的方向间隔分布的芯片单元21，各芯片单元21之间可电性连接；
导电结构3可至少设于一芯片单元21的表面；
引线4，一端与导电结构3连接，另一端延伸至芯片单元21外侧，并与外接电路11连接。
本公开的半导体结构，可将多个芯片单元21沿竖直方向堆叠设置，有助于提高存储容量。在此过程中，通过将各芯片单元21电性连接，进而可将多个不同的芯片单元21中的数据传输至同一个芯片单元21中，将引线4与导电结构3连接，可通过导电结构3将芯片单元21中的电信号传递至引线4，进而通过引线4将芯片单元21与外接电路11连接，实现信号传输。在此过程中，可通过一根引线4将芯片组2中的多个芯片单元21中的信号同时传输至外接电路11，避免了同一芯片组2中的不同芯片单元21的信号传输延时，同时，还可避免绕线，有助于缩小器件体积，避免信号干扰；此外，由于各芯片单元21沿垂直于衬底1的方向间隔分布，可为引线4留出容置空间，进而避免引线4断裂，可提高产品良率。
下面对本公开的半导体结构的具体细节进行详细说明：
如图4-图6所示，衬底1可呈平板结构，其可为矩形、圆形、椭圆形、多边形或不规则图形，其材料可以是半导体材料，例如，其材料可为硅，但是不限于硅或其他半导体材料，在此不对衬底1的形状及材料做特殊限定。
衬底1可包括中心区及外围区，中心区与外围区可邻接分布，外围区可环绕于中心区的外周，中心区可用于形成芯片组2，外围区可用于形成外接电路11。举例而言，中心区可为圆形区域、矩形区域或不规则图形区域，当然，也可以是其他形状的区域，在此不做特殊限定。外围区可为环形区域，并可环绕于中心区的外周，其可以是圆环区域、矩形 环区域或其他形状的环形区域，在此不再一一列举。
芯片组2可设于衬底1一侧，该芯片组2可用于集成电路中，举例而言，其可用于动态随机存取存储器(DRAM，Dynamic Random Access Memory)或静态随机存取存储器(static random access memory，SRAM)中，为了实现低的驱动电压，需尽可能减小DRAM或SRAM的尺寸，芯片单元21是DRAM或SRAM的核心部件，为了在保证存储容量的同时减小DRAM或SRAM尺寸，可将多个芯片单元21沿垂直与衬底1的方向堆叠设置，以形成芯片组2，举例而言，芯片组2中芯片单元21的数量可以是2个、3个、4个、5个、6个或7个，当然，还可以是其他数量，在此不做特殊限定。
在本公开的一些实施方式中，芯片组2中的各芯片单元21之间均可电性连接，有助于多个芯片单元21中的数据互相传输，进而便于将多个不同的芯片单元21中的数据传输至同一个芯片单元21中，便于后续通过导电结构3将芯片组2中的各芯片单元21中的电信号同时传递至引线4，进而通过引线4将芯片单元21与外接电路11连接，以实现信号传输。
在本公开的一些实施方式中，芯片组2中的各芯片单元21均可沿垂直于衬底1的方向间隔分布，以便于为后续形成的引线4留出容置空间，进而避免引线4断裂，可提高产品良率。举例而言，各芯片单元21可沿垂直于衬底1的方向等间距间隔分布，例如，相邻两个芯片单元21之间可间隔开预设距离。当然，各芯片单元21之间的间距也可不完全相等，例如，多个芯片单元21中至少有两个芯片单元21之间的间距与其他的相邻两个芯片单元21之间的间距不相等。
在本公开的一些实施方式中，预设距离可为10um～150um，举例而言，预设距离可为10um、40um、70um、100um、130um或150um，当然，预设距离还可以是其他数值，在此不再一一列举。
在本公开的一种示例性实施方式中，芯片单元21可呈片状结构，其形状可以是矩形、圆形、椭圆形或不规则图形，在此不做特殊限定。各芯片单元21的厚度可以相同，也可以不同，在此不做特殊限定。芯片单元21的厚度可以是40um～80um，举例而言，其可以是40um、50um、60um、70um或80um，当然，也可以是其他厚度，在此不再一一列举。
在本公开的一些实施方式中，芯片组2中的各芯片单元21可具有相同的厚度，举例而言，各芯片单元21的厚度均可为50um，或者，各芯片单元21的厚度均可为60um，又或者，各芯片单元21的厚度均可为70um；当然，各芯片单元21也均可为其他厚度，在此不再一一列举。
在本公开的一种示例性实施方式中，芯片单元21可包括晶圆及设于晶圆表面的电路模块，芯片组2可包括两个芯片单元21，为了便于区分，可将两个芯片单元21分别定义为第一芯片单元211和第二芯片单元212，第二芯片单元212可位于第一芯片单元211远离衬底1的一侧，且第一芯片单元211和第二芯片单元212可镜像设置，即：第一芯片单元211 和第二芯片单元212完全相同，第一芯片单元211的电路模块可与第二芯片单元212电路模块相对设置。
导电结构3可设于至少一个芯片单元21的表面，举例而言，导电结构3可设于芯片组2中的任一一个芯片单元21的表面，并可与该芯片单元21表面的电路模块接触连接，可通过导电结构3将芯片单元21的电路模块电学引出，以便于通过导电结构31将芯片单元21中的数据信号传输至外接电路11。
优选的，导电结构3可设于芯片组2中最靠近衬底1的芯片单元21的表面，此时，可最大程度的缩短后续与导电结构3连接的引线4的长度，进而缩短芯片单元21中的信号向外接电路11传输的信号传输时长，有助于提高信号传输效率；同时，还可节省制作引线4所需的材料，降低制造成本。举例而言，当芯片组2包括镜像设置的第一芯片单元211和第二芯片单元212，且第二芯片单元212可位于第一芯片单元211远离衬底1的一侧时，导电结构3可设于第一芯片单元211靠近第二芯片单元212的表面。
在本公开的一些实施方式中，在芯片单元21的大批量生产过程中，为了工艺方便，可在每一个芯片单元21的表面均形成导电结构3，各芯片单元21的导电结构3均与芯片单元21的电路模块接触连接。在芯片组2中，可使后续形成的引线4与任一一个芯片单元21表面的导电结构3连接。
在本公开的一种示例性实施方式中，导电结构3可包括布线层31、连接垫32和第一导电凸点33，其中：
布线层31可设于芯片单元21的表面，其可以是形成于芯片单元21表面的薄膜，也可以是形成于芯片单元21表面的涂层，在此不对布线层31的具体形式做特殊限定。布线层31的材料可为导电材料，例如，其材料可为金属或其他导电材料，可通过真空蒸镀、磁控溅射、化学气相沉积、物理气相沉积或原子层沉积等方式在芯片单元21的表面形成布线层31，当然，也可通过其他方式形成布线层31，在此不对布线层31的形成方式做特殊限定。
连接垫32可设于芯片单元21的表面，连接垫32可由导电材料制成，例如，其材料可为金、银、铜、铝或钨等。在本公开的一些实施方式中，连接垫32可以是形成于芯片单元21的表面的焊垫，可通过焊接的方式将其与布线层31连接；在本公开的另一些实施方式中，连接垫32可以是形成于芯片单元21的表面的薄膜，也可以是形成于芯片单元21的表面的涂层，在此不对连接垫32的具体形式做特殊限定，可通过真空蒸镀、磁控溅射、化学气相沉积、物理气相沉积或原子层沉积等方式在芯片单元21的表面形成连接垫32，当然，也可通过其他方式形成连接垫32，在此不对连接垫32的形成方式做特殊限定。
需要说明的是，为了便于将连接垫32与后续形成的引线4连接，避 免引线4在芯片单元21内部绕线，可将连接垫32设于布线层31靠近芯片单元21的边缘的一侧，并可使其与布线层31靠近芯片单元21的边缘的一侧接触连接。
第一导电凸点33可设于芯片单元21的表面，且其在衬底1上的正投影与连接垫32在衬底1上的正投影无交叠。第一导电凸点33可与芯片单元21的电路模块接触连接，同时，第一导电凸点33还可与布线层31接触连接，可通过第一导电凸点33将芯片单元21的电路模块中的数据信号通过布线层31传输至连接垫32，以便于后续通过与连接垫32连接的引线4将数据信号传输至外接电路11。
在本公开的一些实施方式中，第一导电凸点33可由导电材料制成，例如，其材料可为金、银、铜、铝或钨等。在本公开的一些实施方式中，第一导电凸点33可以是形成于芯片单元21表面的焊垫，可通过焊接的方式将其与布线层31及芯片单元21的外接电路11接触连接；在本公开的另一些实施方式中，第一导电凸点33可以是形成于芯片单元21的表面的薄膜，也可以是形成于芯片单元21的表面的涂层，在此不对第一导电凸点33的具体形式做特殊限定，可通过真空蒸镀、磁控溅射、化学气相沉积、物理气相沉积或原子层沉积等方式在芯片单元21的表面形成第一导电凸点33，当然，也可通过其他方式形成第一导电凸点33，在此不对第一导电凸点33的形成方式做特殊限定。
在本公开的一些实施方式中，第一芯片单元211和第二芯片单元212的表面均可设有导电结构3，即，第一芯片单元211和第二芯片单元212的表面均可设有布线层31、连接垫32以及第一导电凸点33，为了便于区分，可将第二芯片单元212表面的第一导电凸点33即为第二导电凸点34，第二导电凸点34可设于第二芯片单元212靠近第一芯片单元211的表面，并与第一芯片单元211的第一导电凸点33相对设置。与此同时，为了便于后续装配，在第一芯片单元211和第二芯片单元212的制程过程中，可使第一芯片单元211和第二芯片单元212的结构保持一致，即，在第一芯片单元211和第二芯片单元212镜像设置时，第一芯片单元211表面的第一导电凸点33与第二芯片单元212表面的第二导电凸点34相对分布，与此同时，第一芯片单元211表面的布线层31与第二芯片单元212表面的布线层31相对设分布，第一芯片单元211表面的连接垫32与第二芯片单元212表面的连接垫32也相对设分布。
引线4的一端可与导电结构3连接，另一端可延伸至芯片单元21外侧，并可与衬底1上的外接电路11连接。举例而言，引线4可与连接垫32接触连接，可通过引线4、连接垫32、布线层31及第一导电凸点33将芯片单元21中的数据信号传输至外接电路11。在本公开的一些实施方式中，可通过焊接的方式将引线4的两端分别与导电结构3及衬底1上的外接电路11连接在一起，例如，可将引线4的一端与导电结构3的连接垫32焊接在一起，同时，将其另一端与外接电路11焊接在一起。
在本公开的一些实施方式中，引线4可与芯片组2中的一个芯片单元21表面的导电结构3连接，由于芯片组2中的各芯片单元21之间均电连接，进而可将多个不同的芯片单元21中的数据传输至同一个芯片单元21中，将引线4与该芯片单元21表面的导电结构3连接，可通过导电结构3将该芯片单元21中的电信号传递至引线4，进而通过引线4将芯片单元21与外接电路11连接，实现信号传输。在此过程中，可通过一根引线4将芯片组2中的多个芯片单元21中的信号同时传输至外接电路11，避免了同一芯片组2中的不同芯片单元21的信号传输延时。
引线4可由导电材料构成，举例而言，其可以是金属材料，例如，其可以是金、银、铜、铝等金属，也可以是上述两种或两种以上材料组成的合金，当然，还可以是其他导电性能较好的金属，在此不做特殊限定。当然，引线4还可以是其他材料，例如，还可以是多晶硅等非金属材料，在此不再一一列举。
在本公开的一种示例性实施方式中，本公开的芯片组2还可包括连接部5，连接部5可设于相邻两个芯片单元21之间，并可与相邻的芯片单元21表面的第一导电凸点33接触连接。举例而言，当芯片组2包括第一芯片单元211和第二芯片单元212时，连接部5可位于第一导电凸点33和第二导电凸点34之间，并可与第一导电凸点33及第二导电凸点34接触连接。可通过焊接的方式将连接部5与第二芯片单元212表面的第二导电凸点34连接在一起，随后，将第一芯片单元211表面的第一导电凸点33与连接部5焊接在一起。
在本公开的一些实施方式中，连接部5可由导电材料制成，举例而言，其材料可为锡、铅、银、铜、镍、锌、铋、铟、金、镉、锗、硅等一种或两种以上材料组成的焊锡材料，其形状可以是半球形、球形、椭圆球形、圆柱形、方形等(如图5及图6所示)，可通过第一导电凸点33、连接部5及第二导电凸点34将第一芯片单元211与第二芯片单元212电性连接。
需要说明的是，相邻的两个芯片单元21之间设有如上述第一导电凸点33、连接部5、第二导电凸点34组成的“三明治”结构，可通过相邻的两个芯片单元21之间的“三明治”结构将芯片组中的相邻的两个芯片单元21电性连接。
举例而言，可在第一芯片单元211中设有电路模块的表面设置第一导电凸点33、连接部5，在第二芯片单元212中设有电路模块的表面仅设置第二导电凸点34。或者，在第二芯片单元212中设有电路模块的表面设置第二导电凸点34、连接部5，在第一芯片单元211中设有电路模块的表面仅设置第一导电凸点33。
或者，需要说明的是，可在相邻的两个芯片单元21上分别设置导电结构3，例如，在第一芯片单元211上设置第一导电凸点33及连接部5，在第二芯片单元212上设置连接部5及第二导电凸点34，第一芯片单元 211上的第一导电凸点33及连接部5与第二芯片单元212上的连接部5及第二导电凸点34在衬底1上的正投影无交叠，可通过第一芯片单元211和第二芯片单元212之间的两个连接部5将第一芯片单元211及第二芯片单元212电性连接。
或者，需要说明的是，可在相邻的两个芯片单元21上分别设置导电结构3，例如，在第一芯片单元211和第二芯片单元212上分别设置错位分布的第一导电凸点33和第二导电凸点34，可通过第一导电凸点33和第二导电凸点34直接将第一芯片单元211和第二芯片单元212电性连接。
在本公开的一些实施方式中，第一导电凸点33、连接部5及第二导电凸点34可将相邻的芯片单元21间隔开预设距离，举例而言，当芯片组2包括第一芯片单元211和第二芯片单元212时，第一导电凸点33、连接部5及第二导电凸点34可将第一芯片单元211和第二芯片单元212间隔开预设距离，该预设距离可参考上述实施方式中的预设距离，此处不再赘述。需要说明的是，预设距离可大于引线4弯折所需的纵向间距，引线4与连接垫32连接的一端可在第一芯片单元211和第二芯片单元212间隔开的预设距离处弯折，可避免引线4断裂，提高产品良率。
在本公开的一种示例性实施方式中，如图3所示，本公开的半导体结构还可包括绝缘填充层6，可通过绝缘填充层6对相邻的芯片单元21进行绝缘隔离，避免各芯片单元21之间发生信号串扰或耦合。
在本公开的一种示例性实施方式中，绝缘填充层6的材料可为绝缘胶或封装胶，可通过绝缘填充层6隔绝外界水、氧，防止外界水、氧进入芯片单元21内部，进而避免水、氧侵蚀芯片单元21的内部结构，可延长芯片单元21的使用寿命。
在本公开的一些实施方式中，绝缘填充层6可填满相邻的芯片单元21之间的间隙，可通过绝缘填充层6对相邻的两个芯片单元21之间的空隙进行支撑，同时，还可平衡相邻两个芯片单元21之间的应力，可减小各芯片单元21受外力作用而断裂的可能性，可提高产品良率。
在本公开的一些实施方式中，如图7所示，芯片组2中的绝缘填充层6可为厚厚的一层，各芯片单元21可埋入该绝缘填充层6内，举例而言，可在形成芯片组2后，在衬底1与芯片组2共同构成的结构的表面形成绝缘填充层6，绝缘填充层6可填满各芯片单元21之间的间隙，并将各芯片单元21的侧壁包覆在内，进而可实现对各芯片单元21的全方位隔绝保护。
在本公开的另一些实施方式中，绝缘填充层6可包括多个间隔分布的绝缘层，绝缘层的数量可与各芯片单元21之间的间隙的数量相匹配，举例而言，在同一芯片组2中，绝缘层的数量可比芯片单元21的数量少1，各绝缘层可一一对应的分布于相邻两个芯片单元21之间，绝缘层的厚度可与相邻的芯片单元21之间的间距相等，即绝缘层可填满相邻的芯 片单元21之间的间隙。
需要说明的是，将各绝缘层、各芯片组2共同构成的结构的固定在衬底1上后，还可在各绝缘层、各芯片组2及衬底1共同构成的结构的表面继续填充绝缘材料，进而将各芯片组2埋藏于绝缘材料内，该绝缘材料可与各绝缘层共同构成绝缘填充层6，绝缘材料与绝缘层的材料可以相同，也可以不同，在此不做特殊限定。举例而言，绝缘材料和绝缘层的材料均可为绝缘胶或封装胶；或者，绝缘材料和绝缘层的材料中任一一个的材料为绝缘胶，另一个的材料为封装胶。
在本公开的一种示例性实施方式中，为了进一步增大存储容量，芯片组2的数量可为多个，多个芯片组2可沿垂直于衬底1的方向层叠分布，举例而言，芯片组2的数量可以是2个、3个、4个、5个、6个或7个，当然，还可以是其他数量，在此不做特殊限定。
在本公开的一些实施方式中，不同的芯片组2中的芯片单元21的数量可以相等，举例而言，各芯片组2中的芯片单元21的数量可均为2个；或者，各芯片组2中的芯片单元21的数量可均为3个，又或者，各芯片组2中的芯片单元21的数量可均为3个，当然，各芯片组2中的芯片单元21的数量也可为其他数值，在此不再一一列举。
在本公开的另一些实施方式中，不同的芯片组2中的芯片单元21的数量可以不相等，例如，各芯片组2中一些芯片组2中的芯片单元21的数量为2个，另一些芯片组2中的芯片单元21的数量为3个；又如，各芯片组2中一些芯片组2中的芯片单元21的数量为3个，另一些芯片组2中的芯片单元21的数量为4个；当然，各芯片组2中的芯片单元21的数量也可为其他数值，在此不再一一列举。
在本公开的一些实施方式中，各芯片组2之间均可绝缘设置，可避免不同芯片组2中的数据之间出现串扰。每个芯片组2均具有与之对应的导电结构3和引线4，进而可通过不同的引线4将不同的芯片组2中的数据传输至外接电路11。
在本公开的一些实施方式中，本公开的半导体结构还可包括多个封装层8，各封装层8可一一对应的设置于各芯片组2之间，并可填满各芯片组2之间的间隙。可通过封装层8隔绝外界水、氧，防止外界水、氧进入芯片组2内部，进而避免水、氧侵蚀芯片组2的内部结构，可延长芯片组2的使用寿命。
在本公开的一种示例性实施方式中，封装层8的材料可为绝缘的非导电胶或封装胶，可通过封装层8对相邻的芯片组2进行绝缘隔离，避免各芯片组2之间发生信号串扰或耦合。
在本公开的一些实施方式中，封装层8的数量可与各芯片组2的数量相匹配，举例而言，封装层8的数量可比芯片组2的数量少1，各封装层8可一一对应的分布于相邻两个芯片组2之间，且封装层8在衬底1上的正投影可至少与芯片组2在衬底1上的正投影重合。需要说明的 是，各封装层8还可连接在一起，进而将各芯片组2完全包覆在内，进而可实现对各芯片组2的全方位封装。
在本公开的一种示例性实施方式中，本公开的半导体结构还可包括粘接层7，粘接层7可设于衬底1与最靠近衬底1的芯片组2之间。粘接层7的材料可为导电胶，可通过粘接层7将最靠近衬底1的芯片组2粘贴在衬底1表面，以防止芯片组2相对于衬底1晃动。需要说明的是，粘接层7在衬底1上的正投影与外接电路11无交叠，即：粘接层7可露出外接电路11，以便于将外接电路11与引线4连接。举例而言，粘接层7可位于衬底1的中间区域，且其在衬底1上的正投影可与最靠近衬底1的芯片组2在衬底1上的正投影相互重合。
本公开实施方式还可以包括多个锡球9，锡球9可设于衬底1远离芯片组2的一侧，可通过锡球9将芯片单元21中的电信号传输至外部电路。
本公开实施方式还提供一种半导体结构的形成方法，图8示出了本公开的半导体结构的形成方法的流程图，参见图8所示，该形成方法可以包括步骤S110-步骤S140，其中：
步骤S110，提供衬底，所述衬底包括外接电路；
步骤S120，在所述衬底的一侧形成芯片组，所述芯片组包括多个沿垂直于所述衬底的方向间隔分布的芯片单元，各所述芯片单元之间电性连接；
步骤S130，在至少设于一所述芯片单元的表面形成导电结构；
步骤S140，形成引线，所述引线的一端与所述导电结构连接，另一端延伸至所述芯片单元外侧，并与所述外接电路连接。
本公开的半导体结构烦人形成方法，可将多个芯片单元21沿竖直方向堆叠设置，有助于提高存储容量。在此过程中，通过将各芯片单元21电性连接，进而可将多个不同的芯片单元21中的数据传输至同一个芯片单元21中，将引线4与导电结构3连接，可通过导电结构3将芯片单元21中的电信号传递至引线4，进而通过引线4将芯片单元21与外接电路11连接，实现信号传输。在此过程中，可通过一根引线4将芯片组2中的多个芯片单元21中的信号同时传输至外接电路11，避免了同一芯片组2中的不同芯片单元21的信号传输延时，同时，还可避免绕线，有助于缩小器件体积，避免信号干扰；此外，由于各芯片单元21沿垂直于衬底1的方向间隔分布，可为引线4留出容置空间，进而避免引线4断裂，可提高产品良率。
下面对本公开实施方式半导体结构的形成方法的具体细节做详细说明：
如图8所示，在步骤S110中，提供衬底，所述衬底包括外接电路。
如图4-图6所示，衬底1可呈平板结构，其可为矩形、圆形、椭圆形、多边形或不规则图形，其材料可以是半导体材料，例如，其材料可 为硅，但是不限于硅或其他半导体材料，在此不对衬底1的形状及材料做特殊限定。
衬底1可包括中心区及外围区，中心区与外围区可邻接分布，外围区可环绕于中心区的外周，中心区可用于形成芯片组2，外围区可用于形成外接电路11。举例而言，中心区可为圆形区域、矩形区域或不规则图形区域，当然，也可以是其他形状的区域，在此不做特殊限定。外围区可为环形区域，并可环绕于中心区的外周，其可以是圆环区域、矩形环区域或其他形状的环形区域，在此不再一一列举。
如图8所示，在步骤S120中，在所述衬底的一侧形成芯片组，所述芯片组包括多个沿垂直于所述衬底的方向间隔分布的芯片单元，各所述芯片单元之间电性连接。
芯片组2可设于衬底1一侧，该芯片组2可用于集成电路中，举例而言，其可用于动态随机存取存储器(DRAM，Dynamic Random Access Memory)或静态随机存取存储器(static random access memory，SRAM)中，为了实现低的驱动电压，需尽可能减小DRAM或SRAM的尺寸，芯片单元21是DRAM或SRAM的核心部件，为了在保证存储容量的同时减小DRAM或SRAM尺寸，可将多个芯片单元21沿垂直与衬底1的方向堆叠设置，以形成芯片组2，举例而言，芯片组2中芯片单元21的数量可以是2个、3个、4个、5个、6个或7个，当然，还可以是其他数量，在此不做特殊限定。
在本公开的一些实施方式中，芯片组2中的各芯片单元21之间均可电性连接，有助于多个芯片单元21中的数据互相传输，进而便于将多个不同的芯片单元21中的数据传输至同一个芯片单元21中，便于后续通过导电结构3将芯片组2中的各芯片单元21中的电信号传递至引线4，进而通过引线4将芯片单元21与外接电路11连接，以实现信号传输。
在本公开的一些实施方式中，芯片组2中的各芯片单元21均可沿垂直于衬底1的方向间隔分布，以便于为后续形成的引线4留出容置空间，进而避免引线4断裂，可提高产品良率。举例而言，各芯片单元21可沿垂直于衬底1的方向等间距间隔分布，例如，相邻两个芯片单元21之间可间隔开预设距离。当然，各芯片单元21之间的间距也可不完全相等，例如，多个芯片单元21中至少有两个芯片单元21之间的间距与其他的相邻两个芯片单元21之间的间距不相等。
在本公开的一些实施方式中，预设距离可为10um～150um，举例而言，预设距离可为10um、40um、70um、100um、130um或150um，当然，预设距离还可以是其他数值，在此不再一一列举。
在本公开的一种示例性实施方式中，芯片单元21可呈片状结构，其形状可以是矩形、圆形、椭圆形或不规则图形，在此不做特殊限定。各芯片单元21的厚度可以相同，也可以不同，在此不做特殊限定。芯片单元21的厚度可以是40um～80um，举例而言，其可以是40um、50um、 60um、70um或80um，当然，也可以是其他厚度，在此不再一一列举。
在本公开的一些实施方式中，芯片组2中的各芯片单元21可具有相同的厚度，举例而言，各芯片单元21的厚度均可为50um，或者，各芯片单元21的厚度均可为60um，又或者，各芯片单元21的厚度均可为70um；当然，各芯片单元21也均可为其他厚度，在此不再一一列举。
在本公开的一种示例性实施方式中，芯片单元21可包括晶圆及设于晶圆表面的电路模块，芯片组2可包括两个芯片单元21，为了便于区分，可将两个芯片单元21分别定义为第一芯片单元211和第二芯片单元212，第二芯片单元212可位于第一芯片单元211远离衬底1的一侧，且第一芯片单元211和第二芯片单元212可镜像设置，即：第一芯片单元211和第二芯片单元212完全相同，第一芯片单元211的电路模块可与第二芯片单元212电路模块相对设置。
如图8所示，在步骤S130中，在至少设于一所述芯片单元的表面形成导电结构。
导电结构3可设于至少一个芯片单元21的表面，举例而言，导电结构3可设于芯片组2中的任一一个芯片单元21的表面，并可与该芯片单元21表面的电路模块接触连接，可通过导电结构3将芯片单元21的电路模块电学引出，以便于通过导电结构31将芯片单元21中的数据信号传输至外接电路11。
优选的，导电结构3可设于芯片组2中最靠近衬底1的芯片单元21的表面，此时，可最大程度的缩短后续与导电结构3连接的引线4的长度，进而缩短芯片单元21中的信号向外接电路11传输的信号传输时长，有助于提高信号传输效率；同时，还可节省制作引线4所需的材料，降低制造成本。举例而言，当芯片组2包括镜像设置的第一芯片单元211和第二芯片单元212，且第二芯片单元212可位于第一芯片单元211远离衬底1的一侧时，导电结构3可设于第一芯片单元211靠近第二芯片单元212的表面。
在本公开的一些实施方式中，在芯片单元21的大批量生产过程中，为了工艺方便，可在每一个芯片单元21的表面均形成导电结构3，各芯片单元21的导电结构3均与芯片单元21的电路模块接触连接。在芯片组2中，可使后续形成的引线4与任一一个芯片单元21的导电结构3连接。
在本公开的一种示例性实施方式中，在至少设于一芯片单元21的表面形成导电结构3(即步骤S130)可包括步骤S210-步骤S230，其中：
步骤S210，在至少一所述芯片单元21的表面形成布线层31。
布线层31可设于芯片单元21的表面，其可以是形成于芯片单元21表面的薄膜，也可以是形成于芯片单元21表面的涂层，在此不对布线层31的具体形式做特殊限定。布线层31的材料可为导电材料，例如，其材料可为金属或其他导电材料，可通过真空蒸镀、磁控溅射、化学气相 沉积、物理气相沉积或原子层沉积等方式在芯片单元21的表面形成布线层31，当然，也可通过其他方式形成布线层31，在此不对布线层31的形成方式做特殊限定。
步骤S220，在形成有所述布线层31的所述芯片单元21的表面形成连接垫32，所述连接垫32与所述布线层31靠近所述芯片单元21的边缘的一侧连接，所述引线4与所述连接垫32接触连接。
连接垫32可设于芯片单元21的表面，连接垫32可由导电材料制成，例如，其材料可为金、银、铜、铝或钨等。在本公开的一些实施方式中，连接垫32可以是形成于芯片单元21的表面的焊垫，可通过焊接的方式将其与布线层31连接；在本公开的另一些实施方式中，连接垫32可以是形成于芯片单元21的表面的薄膜，也可以是形成于芯片单元21的表面的涂层，在此不对连接垫32的具体形式做特殊限定，可通过真空蒸镀、磁控溅射、化学气相沉积、物理气相沉积或原子层沉积等方式在芯片单元21的表面形成连接垫32，当然，也可通过其他方式形成连接垫32，在此不对连接垫32的形成方式做特殊限定。
需要说明的是，为了便于将连接垫32与后续形成的引线4连接，避免引线4在芯片单元21内部绕线，可将连接垫32设于布线层31靠近芯片单元21的边缘的一侧，并可使其与布线层31靠近芯片单元21的边缘的一侧接触连接。
步骤S230，在形成有所述布线层31的所述芯片单元21的表面形成第一导电凸点33，所述第一导电凸点33与所述布线层31接触连接，且所述第一导电凸点33在所述衬底1上的正投影与所述连接垫32在所述衬底1上的正投影无交叠。
第一导电凸点33可设于芯片单元21的表面，且其在衬底1上的正投影与连接垫32在衬底1上的正投影无交叠。第一导电凸点33可与芯片单元21的电路模块接触连接，同时，第一导电凸点33还可与布线层31接触连接，可通过第一导电凸点33将芯片单元21的电路模块中的数据信号通过布线层31传输至连接垫32，以便于后续通过与连接垫32连接的引线4将数据信号传输至外接电路11。
在本公开的一些实施方式中，第一导电凸点33可由导电材料制成，例如，其材料可为金、银、铜、铝或钨等。在本公开的一些实施方式中，第一导电凸点33可以是形成于芯片单元21表面的连接部5，可通过焊接的方式将其与布线层31及芯片单元21的外接电路11接触连接；在本公开的另一些实施方式中，第一导电凸点33可以是形成于芯片单元21的表面的薄膜，也可以是形成于芯片单元21的表面的涂层，在此不对第一导电凸点33的具体形式做特殊限定，可通过真空蒸镀、磁控溅射、化学气相沉积、物理气相沉积或原子层沉积等方式在芯片单元21的表面形成第一导电凸点33，当然，也可通过其他方式形成第一导电凸点33，在此不对第一导电凸点33的形成方式做特殊限定。
在本公开的一些实施方式中，本公开的半导体结构的形成还可包括：
步骤S150，在所述第二芯片单元212靠近所述第一芯片单元211的表面形成第二导电凸点34，所述第二导电凸点34与所述第一导电凸点33相对设置。
在本公开的一些实施方式中，第一芯片单元211和第二芯片单元212的表面均可设有导电结构3，即，第一芯片单元211和第二芯片单元212的表面均可设有布线层31、连接垫32以及第一导电凸点33，为了便于区分，可将第二芯片单元212表面的第一导电凸点33即为第二导电凸点34，第二导电凸点34可设于第二芯片单元212靠近第一芯片单元211的表面，并与第一芯片单元211的第一导电凸点33相对设置。与此同时，为了便于后续装配，在第一芯片单元211和第二芯片单元212的制程过程中，可使第一芯片单元211和第二芯片单元212的结构保持一致，即，在第一芯片单元211和第二芯片单元212镜像设置时，第一芯片单元211表面的第一导电凸点33与第二芯片单元212表面的第二导电凸点34相对分布，与此同时，第一芯片单元211表面的布线层31与第二芯片单元212表面的布线层31相对设分布，第一芯片单元211表面的连接垫32与第二芯片单元212表面的连接垫32也相对设分布。
需要说明的是，第二导电凸点34的形成方式与第一导电凸点33的形成方式类似，可参考第一导电凸点33的形成方式形成第二导电凸点34，此处不对第二导电凸点34的形成过程进行赘述。
如图8所示，在步骤S140中，形成引线，所述引线的一端与所述导电结构连接，另一端延伸至所述芯片单元外侧，并与所述外接电路连接。
引线4的一端可与导电结构3连接，另一端可延伸至芯片单元21外侧，并可与衬底1上的外接电路11连接。举例而言，引线4可与连接垫32接触连接，可通过引线4、连接垫32、布线层31及第一导电凸点33将芯片单元21中的数据信号传输至外接电路11。在本公开的一些实施方式中，可通过焊接的方式将引线4的两端分别与导电结构3及衬底1上的外接电路11连接在一起，例如，可将引线4的一端与导电结构3的连接垫32焊接在一起，同时，将其另一端与外接电路11焊接在一起。
在本公开的一些实施方式中，引线4可与芯片组2中的一个芯片单元21表面的导电结构3连接，由于芯片组2中的各芯片单元21之间均电连接，进而可将多个不同的芯片单元21中的数据传输至同一个芯片单元21中，将引线4与该芯片单元21表面的导电结构3连接，可通过导电结构3将该芯片单元21中的电信号传递至引线4，进而通过引线4将芯片单元21与外接电路11连接，实现信号传输。在此过程中，可通过一根引线4将芯片组2中的多个芯片单元21中的信号同时传输至外接电路11，避免了同一芯片组2中的不同芯片单元21的信号传输延时。
引线4可由导电材料构成，举例而言，其可以是金属材料，例如，其可以是金、银、铜、铝等金属，也可以是上述两种或两种以上材料组 成的合金，当然，还可以是其他导电性能较好的金属，在此不做特殊限定。当然，引线4还可以是其他材料，例如，还可以是多晶硅等非金属材料，在此不再一一列举。
在本公开的一种示例性实施方式中，在衬底1的一侧形成芯片组2还可包括在第一导电凸点33的表面形成连接部5，连接部5可设于相邻两个芯片单元21之间，并可与相邻的芯片单元21表面的第一导电凸点33接触连接。举例而言，当芯片组2包括第一芯片单元211和第二芯片单元212时，连接部5位于第一芯片单元211表面的第一导电凸点33和第二芯片单元212表面的第二导电凸点34之间，第一导电凸点33、连接部5及第二导电凸点34将第一芯片单元211和第二芯片单元212间隔开预设距离。
举例而言，当芯片组2包括第一芯片单元211和第二芯片单元212时，连接部5可位于第一导电凸点33和第二导电凸点34之间，并可与第一导电凸点33及第二导电凸点34接触连接。可通过焊接的方式将连接部5与第二芯片单元212表面的第二导电凸点34连接在一起，随后，将第一芯片单元211表面的第一导电凸点33与连接部5焊接在一起。
在本公开的一些实施方式中，连接部5可由导电材料制成，举例而言，其材料可为锡、铅、银、铜、镍、锌、铋、铟、金、镉、锗、硅等一种或两种以上材料组成的焊锡材料，其形状可以是半球形、球形、椭圆球形、圆柱形、方形等，可通过第一导电凸点33、连接部5及第二导电凸点34将第一芯片单元211与第二芯片单元212电性连接。
需要说明的是，当芯片组2中包括多个芯片单元21时，相邻的两个芯片单元21之间均可设有如上述第一导电凸点33、连接部5、第二导电凸点34组成的“三明治”结构，可通过相邻的两个芯片单元21之间的“三明治”结构将芯片组2中的相邻的两个芯片单元21电性连接。
举例而言，可在第一芯片单元211中设有电路模块的表面设置第一导电凸点33、连接部5，在第二芯片单元212中设有电路模块的表面仅设置第二导电凸点34。或者，在第二芯片单元212中设有电路模块的表面设置第二导电凸点34、连接部5，在第一芯片单元211中设有电路模块的表面仅设置第一导电凸点33。
或者，需要说明的是，可在相邻的两个芯片单元21上分别设置导电结构3，例如，在第一芯片单元211上设置第一导电凸点33及连接部5，在第二芯片单元212上设置连接部5及第二导电凸点34，第一芯片单元211上的第一导电凸点33及连接部5与第二芯片单元212上的连接部5及第二导电凸点34在衬底1上的正投影无交叠，可通过第一芯片单元211和第二芯片单元212之间的两个连接部5将第一芯片单元211及第二芯片单元212电性连接。
或者，需要说明的是，可在相邻的两个芯片单元21上分别设置导电结构3，例如，在第一芯片单元211和第二芯片单元212上分别设置错 位分布的第一导电凸点33和第二导电凸点34，可通过第一导电凸点33和第二导电凸点34直接将第一芯片单元211和第二芯片单元212电性连接。
在本公开的一些实施方式中，第一导电凸点33、连接部5及第二导电凸点34可将相邻的芯片单元21间隔开预设距离，举例而言，当芯片组2包括第一芯片单元211和第二芯片单元212时，第一导电凸点33、连接部5及第二导电凸点34可将第一芯片单元211和第二芯片单元212间隔开预设距离，该预设距离可参考上述实施方式中的预设距离，此处不再赘述。需要说明的是，预设距离可大于引线4弯折所需的纵向间距，引线4与连接垫32连接的一端可在第一芯片单元211和第二芯片单元212间隔开的预设距离处弯折，可避免引线4断裂，提高产品良率。
在本公开的一种示例性实施方式中，本公开的半导体结构的形成方法还可包括：
步骤S160，形成绝缘填充层6，所述绝缘填充层6填满相邻的所述芯片单元21之间的间隙。
如图3所示，绝缘填充层6可设于相邻两个芯片单元21之间，可采用旋涂或涂布等方式在相邻两个芯片单元21之间形成绝缘填充层6，可通过绝缘填充层6对相邻的芯片单元21进行绝缘隔离，避免各芯片单元21之间发生信号串扰或耦合。
在本公开的一种示例性实施方式中，绝缘填充层6的材料可为绝缘胶或封装胶，可通过绝缘填充层6隔绝外界水、氧，防止外界水、氧进入芯片单元21内部，进而避免水、氧侵蚀芯片单元21的内部结构，可延长芯片单元21的使用寿命。
在本公开的一些实施方式中，绝缘填充层6可填满相邻的芯片单元21之间的间隙，可通过绝缘填充层6对相邻的两个芯片单元21之间的空隙进行支撑，同时，还可平衡相邻两个芯片单元21之间的应力，可减小各芯片单元21受外力作用而断裂的可能性，可提高产品良率。
在本公开的一些实施方式中，如图7所示，芯片组2中的绝缘填充层6可为厚厚的一层，各芯片单元21可埋入该绝缘填充层6内，举例而言，可在形成芯片组2后，在衬底1与芯片组2共同构成的结构的表面形成绝缘填充层6，绝缘填充层6可填满各芯片单元21之间的间隙，并将各芯片单元21的侧壁包覆在内，进而可实现对各芯片单元21的全方位隔绝保护。
在本公开的另一些实施方式中，绝缘填充层6可包括多个间隔分布的绝缘层，绝缘层的数量可与各芯片单元21之间的间隙的数量相匹配，举例而言，在同一芯片组2中，绝缘层的数量可比芯片单元21的数量少1，各绝缘层可一一对应的分布于相邻两个芯片单元21之间，绝缘层的厚度可与相邻的芯片单元21之间的间距相等，即绝缘层可填满相邻的芯片单元21之间的间隙。
需要说明的是，将各绝缘层、各芯片组2共同构成的结构的固定在衬底1上后，还可在各绝缘层、各芯片组2及衬底1共同构成的结构的表面继续填充绝缘材料，进而将各芯片组2埋藏于绝缘材料内，该绝缘材料可与各绝缘层共同构成绝缘填充层6，绝缘材料与绝缘层的材料可以相同，也可以不同，在此不做特殊限定。举例而言，绝缘材料和绝缘层的材料均可为绝缘胶或封装胶；或者，绝缘材料和绝缘层的材料中任一一个的材料为绝缘胶，另一个的材料为封装胶。
在本公开的一种示例性实施方式中，为了进一步增大存储容量，芯片组2的数量可为多个，多个芯片组2可沿垂直于衬底1的方向层叠分布，举例而言，芯片组2的数量可以是2个、3个、4个、5个、6个或7个，当然，还可以是其他数量，在此不做特殊限定。
在本公开的一些实施方式中，不同的芯片组2中的芯片单元21的数量可以相等，举例而言，各芯片组2中的芯片单元21的数量可均为2个；或者，各芯片组2中的芯片单元21的数量可均为3个，又或者，各芯片组2中的芯片单元21的数量可均为3个，当然，各芯片组2中的芯片单元21的数量也可为其他数值，在此不再一一列举。
在本公开的另一些实施方式中，不同的芯片组2中的芯片单元21的数量可以不相等，例如，各芯片组2中一些芯片组2中的芯片单元21的数量为2个，另一些芯片组2中的芯片单元21的数量为3个；又如，各芯片组2中一些芯片组2中的芯片单元21的数量为3个，另一些芯片组2中的芯片单元21的数量为4个；当然，各芯片组2中的芯片单元21的数量也可为其他数值，在此不再一一列举。
在本公开的一些实施方式中，各芯片组2之间均可绝缘设置，可避免不同芯片组2中的数据之间出现串扰。每个芯片组2均具有与之对应的导电结构3和引线4，进而可通过不同的引线4将不同的芯片组2中的数据传输至外接电路11。
在本公开的一些实施方式中，本公开的半导体结构的形成方法还可包括：
步骤S170，形成多个封装层8，各所述封装层8可一一对应的设置于各所述芯片组2之间，并可填满各所述芯片组2之间的间隙。
在本公开的一种示例性实施方式中，封装层8的材料可为绝缘的非导电胶或封装胶，可采用旋涂或涂布等方式在相邻两个芯片组2之间形成封装层8，可通过封装层8对相邻的芯片组2进行绝缘隔离，避免各芯片组2之间发生信号串扰或耦合；同时，还可通过封装层8隔绝外界水、氧，防止外界水、氧进入芯片组2内部，进而避免水、氧侵蚀芯片组2的内部结构，可延长芯片组2的使用寿命。
在本公开的一些实施方式中，封装层8的数量可与各芯片组2的数量相匹配，举例而言，封装层8的数量可比芯片组2的数量少1，各封装层8可一一对应的分布于相邻两个芯片组2之间，且封装层8在衬底 1上的正投影可至少与芯片组2在衬底1上的正投影重合。需要说明的是，各封装层8还可连接在一起，进而将各芯片组2完全包覆在内，进而可实现对各芯片组2的全方位封装。
在本公开的一种示例性实施方式中，本公开的半导体结构还可包括：
步骤S180，在所述衬底1与最靠近所述衬底1的所述芯片组2之间形成粘接层7。
粘接层7的材料可为导电胶，可通过粘接层7将最靠近衬底1的芯片组2粘贴在衬底1表面，以防止芯片组2相对于衬底1晃动。需要说明的是，粘接层7在衬底1上的正投影与外接电路11无交叠，即：粘接层7可露出外接电路11，以便于将外接电路11与引线4连接。举例而言，粘接层7可位于衬底1的中间区域，且其在衬底1上的正投影可与最靠近衬底1的芯片组2在衬底1上的正投影相互重合。
本公开实施方式还可以包括多个锡球9，锡球9可设于衬底1远离芯片组2的一侧，可通过锡球9将芯片单元21中的电信号传输至外部电路。
需要说明的是，尽管在附图中以特定顺序描述了本公开中半导体结构的形成方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
本公开实施方式还提供一种存储器，该存储器可包括上述任一实施方式中的半导体结构，其具体细节、形成工艺以及有益效果已经在对应的半导体结构及半导体结构的形成方法中进行了详细说明，此处不再赘述。
举例而言，该存储器可以是动态随机存取存储器(Dynamic Random Access Memory，DRAM)、静态随机存取存储器(static random access memory，SRAM)等。当然，还可以是其它存储装置，在此不再一一列举。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (19)

  1. 一种半导体结构，其中，包括：
    衬底，包括外接电路；
    芯片组，设于所述衬底的一侧，且包括多个沿垂直于所述衬底的方向间隔分布的芯片单元，各所述芯片单元之间电性连接；
    导电结构，至少设于一所述芯片单元的表面；
    引线，一端与所述导电结构连接，另一端延伸至所述芯片单元外侧，并与所述外接电路连接。
  2. 根据权利要求1所述的半导体结构，其中，所述导电结构包括：
    布线层，设于所述芯片单元的表面；
    连接垫，设于所述芯片单元的表面，且与所述布线层靠近所述芯片单元的边缘的一侧连接，所述引线与所述连接垫接触连接；
    第一导电凸点，设于所述芯片单元的表面，且与所述布线层接触连接，所述第一导电凸点在所述衬底上的正投影与所述连接垫在所述衬底上的正投影无交叠。
  3. 根据权利要求2所述的半导体结构，其中，所述导电结构位于所述芯片组中最靠近所述衬底的所述芯片单元的表面。
  4. 根据权利要求2所述的半导体结构，其中，所述芯片组包括镜像设置的第一芯片单元和第二芯片单元，所述第二芯片单元位于所述第一芯片单元远离所述衬底的一侧，所述导电结构设于所述第一芯片单元靠近所述第二芯片单元的表面。
  5. 根据权利要求4所述的半导体结构，其中，所述第二芯片单元靠近所述第一芯片单元的表面设有第二导电凸点，所述第二导电凸点与所述第一导电凸点相对设置，所述芯片组还包括：
    连接部，位于所述第一导电凸点和所述第二导电凸点之间，所述第一导电凸点、所述连接部及所述第二导电凸点将所述第一芯片单元和所述第二芯片单元间隔开预设距离。
  6. 根据权利要求1所述的半导体结构，其中，所述半导体结构还包括：
    绝缘填充层，填满相邻的所述芯片单元之间的间隙。
  7. 根据权利要求1所述的半导体结构，其中，所述芯片组的数量为多个，多个所述芯片组沿垂直于所述衬底的方向层叠分布，且各所述芯片组之间均绝缘设置；每个所述芯片组均具有与之对应的所述导电结构和所述引线。
  8. 根据权利要求7所述的半导体结构，其中，所述半导体结构还包括：
    粘接层，设于所述衬底与最靠近所述衬底的所述芯片组之间。
  9. 根据权利要求7所述的半导体结构，其中，所述半导体结构还包括：
    多个封装层，各所述封装层一一对应的设置于各所述芯片组之间，并填满各所述芯片组之间的间隙。
  10. 一种半导体结构的形成方法，其中，包括：
    提供衬底，所述衬底包括外接电路；
    在所述衬底的一侧形成芯片组，所述芯片组包括多个沿垂直于所述衬底的方向间隔分布的芯片单元，各所述芯片单元之间电性连接；
    在至少设于一所述芯片单元的表面形成导电结构；
    形成引线，所述引线的一端与所述导电结构连接，另一端延伸至所述芯片单元外侧，并与所述外接电路连接。
  11. 根据权利要求10所述的形成方法，其中，所述在至少设于一所述芯片单元的表面形成导电结构，包括：
    在至少一所述芯片单元的表面形成布线层；
    在形成有所述布线层的所述芯片单元的表面形成连接垫，所述连接垫与所述布线层靠近所述芯片单元的边缘的一侧连接，所述引线与所述连接垫接触连接；
    在形成有所述布线层的所述芯片单元的表面形成第一导电凸点，所述第一导电凸点与所述布线层接触连接，且所述第一导电凸点在所述衬底上的正投影与所述连接垫在所述衬底上的正投影无交叠。
  12. 根据权利要求11所述的形成方法，其中，所述导电结构形成于所述芯片组中最靠近所述衬底的所述芯片单元的表面。
  13. 根据权利要求11所述的形成方法，其中，所述芯片组包括镜像设置的第一芯片单元和第二芯片单元，所述第二芯片单元形成于所述第一芯片单元远离所述衬底的一侧，所述导电结构形成于所述第一芯片单元靠近所述第二芯片单元的表面。
  14. 根据权利要求13所述的形成方法，其中，所述形成方法还包括：
    在所述第二芯片单元靠近所述第一芯片单元的表面形成第二导电凸点，所述第二导电凸点与所述第一导电凸点相对设置；
    所述在所述衬底的一侧形成芯片组还包括：
    在所述第一导电凸点的表面形成连接部，所述连接部位于所述第一导电凸点和所述第二导电凸点之间，所述第一导电凸点、所述连接部及所述第二导电凸点将所述第一芯片单元和所述第二芯片单元间隔开预设距离。
  15. 根据权利要求10所述的形成方法，其中，所述形成方法还包括：
    形成绝缘填充层，所述绝缘填充层填满相邻的所述芯片单元之间的间隙。
  16. 根据权利要求10所述的形成方法，其中，所述芯片组的数量为多个，多个所述芯片组沿垂直于所述衬底的方向层叠分布，且各所述芯片组之间均绝缘设置；每个所述芯片组均具有与之对应的所述导电结构和所述引线。
  17. 根据权利要求16所述的形成方法，其中，所述形成方法还包括：
    在所述衬底与最靠近所述衬底的所述芯片组之间形成粘接层。
  18. 根据权利要求16所述的形成方法，其中，所述形成方法还包括：
    形成多个封装层，各所述封装层一一对应的设置于各所述芯片组之间，并填满各所述芯片组之间的间隙。
  19. 一种存储器，其中，包括权利要求1-9任一项所述的半导体结构。
PCT/CN2022/113007 2022-08-12 2022-08-17 半导体结构及其形成方法、存储器 WO2024031737A1 (zh)

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US20120273940A1 (en) * 2011-04-29 2012-11-01 Hynix Semiconductor Inc. Semiconductor apparatus and method for fabricating the same
CN112908969A (zh) * 2019-12-04 2021-06-04 长鑫存储技术有限公司 半导体器件、封装结构及封装结构的制备方法
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