WO2024027377A1 - 一种数模转换器、数模转换电路和电子设备 - Google Patents

一种数模转换器、数模转换电路和电子设备 Download PDF

Info

Publication number
WO2024027377A1
WO2024027377A1 PCT/CN2023/102946 CN2023102946W WO2024027377A1 WO 2024027377 A1 WO2024027377 A1 WO 2024027377A1 CN 2023102946 W CN2023102946 W CN 2023102946W WO 2024027377 A1 WO2024027377 A1 WO 2024027377A1
Authority
WO
WIPO (PCT)
Prior art keywords
digital signal
resistor
code bits
digital
resistance
Prior art date
Application number
PCT/CN2023/102946
Other languages
English (en)
French (fr)
Inventor
弋才敏
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Publication of WO2024027377A1 publication Critical patent/WO2024027377A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters

Definitions

  • the present application relates to the technical field of digital signal processing chips, and in particular to a digital-to-analog converter, a digital-to-analog conversion circuit and an electronic device.
  • Digital-to-analog converter as a device that converts digital signals into analog voltage signals, plays an indispensable role in today's electronic device field.
  • Common digital-to-analog converters include current steering digital-to-analog converter (IDAC) and resistor digital-to-analog converter (RDAC).
  • IDAC current steering digital-to-analog converter
  • RDAC resistor digital-to-analog converter
  • resistive digital-to-analog converters in processing scenarios with high speed requirements, it is often necessary to reduce the output impedance by reducing the resistance value of the resistor, thereby increasing the signal processing rate.
  • Using a resistor with a smaller resistance will increase the impact of the on-resistance of the over-current switch in the resistive digital-to-analog converter on the linearity of the digital-to-analog converter. If the effect of on-resistance on the linearity of the digital-to-analog converter is reduced by increasing the size of the over-current switch, a larger parasitic capacitance will be generated by increasing the size of the over-current switch. Therefore, in existing applications, it is difficult for resistive digital-to-analog converters to ensure high speed and high accuracy at the same time.
  • Embodiments of the present application provide a digital-to-analog converter, a digital-to-analog conversion circuit, and an electronic device, which enable the resistive digital-to-analog converter to have high speed and high accuracy.
  • a digital-to-analog converter in a first aspect, includes a first voltage terminal, a second voltage terminal, a control unit, and a first conversion unit.
  • the first conversion unit includes N first switches, N The first resistor; the first voltage terminal is used to input the first voltage; the second voltage terminal is used to input the second voltage; the control unit is used to receive the first digital signal, the first digital signal includes N code bits, and the Nth code bit One switch corresponds to one, and the control unit controls the N first switches respectively according to the N code bits of the first digital signal, so that the first end of the first resistor corresponding to the N first switches is coupled to the first voltage end or the second voltage terminal; the second terminals of the N first resistors are coupled to the first coupling point; the first coupling point is used to output a first analog signal corresponding to N code bits of the first digital signal.
  • the N first resistors respectively correspond to different code bits of the N code bits of the input first digital signal, so that the first voltage or the second voltage of the input first resistor corresponds to the first digital signal.
  • the value of N code points In this embodiment of the present application, N first resistors are equivalently connected in parallel by coupling the second end of the first resistor to the first coupling point. At this time, all the first resistors can be equivalently connected in parallel.
  • the output impedance Rout of the first conversion unit R 3 /2 N
  • R 3 is the highest code bit among the N code bits of the first digital signal.
  • the corresponding resistance value of the first resistor It can be seen that at this time, the output impedance of the first conversion unit is very small and has a constant value.
  • the first resistor can be a resistor with a larger resistance without reducing the resistance of the resistor, a stable and very small output impedance is obtained without using a larger resistance. High-precision and high-speed digital-to-analog conversion can be achieved with a small-sized overcurrent switch.
  • the first digital signal further includes E code bits, and the E code bits of the first digital signal are lower than the N code bits of a digital signal;
  • the digital-to-analog converter also includes a resistor voltage dividing unit and a second conversion unit; the second conversion unit includes N second switches and N second resistors; the control unit is also used according to the first
  • the digital signal generates a second digital signal;
  • the second digital signal includes N code bits, which correspond to the N second switches one-to-one, and the control unit controls the N second switches respectively according to the N code bits of the second digital signal, so that
  • the first terminals of the second resistors corresponding to the N second switches are coupled to the first voltage terminal or the second voltage terminal;
  • the second terminals of the N second resistors are coupled to the second coupling point;
  • the second coupling point is used to Output a second analog signal corresponding to the second digital signal;
  • the value of the second digital signal is greater than the value of the first digital signal;
  • a second digital signal is also generated.
  • the second digital signal also includes N code bits, and the value of the N code bits of the second digital signal is greater than the value of the N code bits of the first digital signal.
  • the first conversion unit generates a first analog signal corresponding to the N code bits of the first digital signal
  • the second conversion unit generates a second analog signal corresponding to the N code bits of the second digital signal.
  • the first analog signal is output to the first input end of the resistor voltage dividing unit through the first coupling point; the second analog signal is output to the second input end of the resistor voltage dividing unit through the second coupling point.
  • the third coupling point serves as the output end of the digital-to-analog converter and outputs a third analog signal.
  • the third analog signal is used to express the N code bits of the first digital signal in the high code bit section and the first digital signal in the low code bit section.
  • the E code bits are combined into the corresponding analog signal after the digital signal of the multi-code bit segment.
  • the E code bits of the first digital signal are used as digital signals in the low code bit section, and are used to control the resistance values of the first resistance module and the second resistance module. When the value of the E code bits of the first digital signal is lower, the output third analog signal is closer to the first analog signal. When the value of the E code bits of the first digital signal is higher, the output third analog signal is closer to the second analog signal.
  • the resistor voltage dividing unit specifically includes an output selection switch and E third resistors; one end of the E third resistors connected in series serves as the first input end and the first coupling point of the resistor voltage dividing unit. Coupling, the other end of the E third resistors connected in series serves as the second input end of the resistor voltage dividing unit and is coupled to the second coupling point; the control unit is used to output the The selection input end of the selection switch is coupled to a third coupling point.
  • the third coupling point is the first end or the second end of one of the E third resistors.
  • the distance between the third coupling point and the first coupling point is The sum of the resistance values of all the third resistors corresponds to the value of the E code bits of the first digital signal.
  • the E third resistors there is a third resistance coupling point between two adjacent third resistors, then the E third resistors have E-1 third resistance coupling points, and they are connected in series.
  • the E third resistors there is an endpoint at the beginning and end that is not connected to other third resistors. Then, by adding E-1 third resistance coupling points to the first and last two endpoints, E endpoints can be obtained. According to the value of the E code bits of the first digital signal, one of the E endpoints is used as the third endpoint. coupling point.
  • the third coupling point is closer to the first coupling point, and conversely, the third coupling point is closer to the second coupling point.
  • the coupling position of the output selection switch that is, the position of the third coupling point
  • the number of third resistors between the second coupling point and the third coupling point is reduced, thereby reducing the number of third coupling points located at the second coupling point.
  • the resistance of the second resistance module between the first coupling point and the third coupling point is increased, and the resistance of the first resistance module between the first coupling point and the third coupling point is increased.
  • the digital-to-analog converter further includes a first bridge resistor; the output end of the first conversion unit is coupled to the first input end of the resistor voltage dividing unit through the first bridge resistor.
  • the equivalent resistance of the first conversion unit is added to the equivalent resistance of the second conversion unit and the resistance of the first bridge resistor.
  • the sum of the values is equal to the resistance of a third resistor.
  • the digital-to-analog converter further includes a second bridge resistor; the output end of the second conversion unit is coupled to the second end of the second resistance module through the second bridge resistor.
  • the resistance obtained by adding the equivalent resistance of the first conversion unit to the equivalent resistance of the second conversion unit and the resistance of the second bridge resistor is The sum of the values is equal to the resistance of a third resistor.
  • the equivalent resistance of the first conversion unit and the second conversion unit can be appropriately increased or decreased, and thus the resistance of the first resistor and the second resistor can be better set.
  • the digital-to-analog converter includes a second bridge resistor
  • the sum of the equivalent resistance of the first conversion unit plus the equivalent resistance of the second conversion unit, the resistance of the first bridge resistor, and the resistance of the second bridge resistor is equal to the resistance of a third resistor.
  • the E code bits of the first digital signal are thermometer codes; the resistance values of the E third resistors are equal.
  • each code bit of the thermometer code corresponds to a third resistor, and the resistance values of the third resistors are equal.
  • the superposition of the resistance values of the third resistor corresponds to the superposition of different values.
  • the resistance values of the third resistors under the thermometer code are all equal, which can reduce the deviation of the analog signal output from excessive voltage or current when the third resistors with different resistance values output different voltages or currents as analog signals. Produces greater interference to the overall analog signal.
  • the N code bits of the second digital signal are thermometer codes; the resistance values of the N second resistors are equal.
  • the resistance values of the second resistors under the thermometer code are all equal, which can reduce the problem of excessive voltage or current output when the second resistors with different resistance values output different voltages or currents as analog signals.
  • the deviation of the analog signal is too large, causing greater interference to the overall analog signal.
  • the N code bits of the second digital signal are binary codes; among the N second resistors, two second resistors corresponding to adjacent code bits among the N code bits of the second digital signal Between them, the resistance value of the second resistor corresponding to the lower code bit of the adjacent code bits among the N code bits of the second digital signal is corresponding to the higher code bit of the adjacent code bits among the N code bits of the second digital signal. twice the resistance of the second resistor.
  • a binary code is used as the N code bits of the second digital signal, and the number of corresponding second resistors is smaller than that of the thermometer code, which is suitable for applications with lower accuracy requirements and a smaller number of resistors. Scenes.
  • the first digital signal further includes M code bits; the M code bits of the first digital signal are higher than the E code bits of the first digital signal and lower than the N code bits of the first digital signal. code bit; the first conversion unit also includes a first segmentation unit; the second conversion unit also includes a second segmentation unit; the output end and the first coupling point of the first segmentation unit are coupled to the first input of the resistor voltage dividing unit terminal; the output terminal and the second coupling point of the second conversion unit are coupled to the second input terminal of the resistor voltage dividing unit; the control unit is also used to control the first segmentation unit to the resistor voltage dividing unit according to the M code bits of the first digital signal.
  • the first input end of the compression unit outputs a fourth analog signal corresponding to the M code bits of the first digital signal; generates M code bits of the second digital signal; the M code bits of the second digital signal are lower than the second N code bits of the digital signal; according to the M code bits of the second digital signal, the second segmentation unit is controlled to output the fifth code bit corresponding to the M code bits of the second digital signal to the second input end of the resistor voltage dividing unit. analog signal.
  • a digital signal including multiple bits there is a digital signal including multiple bits.
  • the digital signal including multiple bits is segmented into N code bits of the first digital signal of the high code bit segment and the low code bit segment.
  • the M code bits of the first digital signal are input into the first segmentation unit of the parallel resistance segmentation circuit through the M code bits of the first digital signal, so that the output of the first segmentation unit is consistent with the low code bit segment.
  • the fourth analog signal corresponding to the M code bits of the first digital signal is output from the first coupling point through the cooperation of the first switch and the first resistor, corresponding to the N code bits of the first digital signal in the high code bit section.
  • the sum of the first analog signal, the first analog signal and the fourth analog signal is used to express the analog signal corresponding to the digital signal including a plurality of bits.
  • a second segmentation unit is correspondingly set in the second conversion unit.
  • the N code bits of the second digital signal correspond to the N code bit values of the first digital signal, but the second digital signal
  • the value of the M code bits is greater than the value of the M code bits of the first digital signal.
  • the first segmentation unit and the second segmentation unit are parallel resistance segmentation units; the parallel resistance segmentation unit includes M code bits corresponding to the first digital signal or the second digital signal.
  • the M fourth switches and M fourth resistors correspond one to one to the M code bits; the control unit is used to respectively control the M fourth switches according to the M code bits of the first digital signal or the M code bits of the second digital signal.
  • the fourth resistor corresponding to the M fourth switches is coupled to the first voltage end or the second voltage end; the second end of the M fourth resistors is coupled to the fourth coupling point; the fourth The coupling point is used to output a fourth analog signal corresponding to the M code bits of the first digital signal or a fifth analog signal corresponding to the M code bits of the second digital signal.
  • a parallel resistor segmentation unit is implemented by equivalently connecting multiple fourth resistors in parallel, which can ensure that the equivalent resistance and output impedance of the entire circuit remain constant.
  • the parallel resistor segment unit further includes a third bridge resistor; a fourth coupling point is coupled to the first end of the third bridge resistor; and the second end of the third bridge resistor serves as a parallel resistor segment. The output of the segment unit.
  • the equivalent resistance of the parallel resistor segment circuit needs to be the resistance of the first resistor corresponding to the lowest bit of the N code bits of the first digital signal. Therefore, after segmenting multi-bit digital signals, it is necessary to adjust the parallel resistor Corresponding relationship between the resistance values of the fourth resistor in the segmented circuit and the first resistor in the first conversion unit.
  • the equivalent resistance of the parallel resistor segment circuit is much smaller than the resistance of the fourth resistor corresponding to the highest code bit of the fourth digital signal (the fourth resistor with the smallest resistance under the binary code), and the parallel resistor
  • the equivalent resistance of the segmented circuit needs to be equal to the resistance of the first resistor corresponding to the lowest code bit of the N code bits of the first digital signal (in binary notation, it is the resistance of the largest first resistor).
  • the fourth resistor needs to have a larger resistance (especially when the fourth digital signal is a binary code, the resistance of the fourth resistor corresponding to the lowest bit of the fourth digital signal needs to be very large) .
  • the equivalent resistance of the parallel-connected resistor segment circuit is the sum of the equivalent resistances of the parallel-connected fourth resistor.
  • the equivalent resistance of the parallel resistor segmented circuit is the sum of the equivalent resistances of the parallel fourth resistors plus the resistance of the third bridge resistor. Therefore, by setting the third bridge resistor, there is no need to set a fourth resistor with an excessively large resistance during the segmentation process, which increases the possibility of realizing the solution.
  • the resistance between the fourth resistor and the first resistor is The setting of the corresponding relationship is also more flexible, and can be adaptively adjusted by adjusting the resistance value of the third bridge resistor.
  • the M code bits of the first digital signal or the M code bits of the second digital signal are binary codes; among the M fourth resistors, corresponding to the M code bits of the first digital signal Or between two fourth resistors of adjacent code bits among the M code bits of the second digital signal, corresponding to the M code bits of the first digital signal or the adjacent code bits among the M code bits of the second digital signal.
  • the resistance value of the fourth resistor of the lower code bit is corresponding to the resistance value of the fourth resistor of the higher code bit of adjacent code bits among the M code bits of the first digital signal or the M code bits of the second digital signal.
  • a binary code is used as the fourth digital signal, and the number of corresponding fourth resistors is smaller than that of the thermometer code, which is suitable for scenarios with lower accuracy requirements and a smaller number of resistors.
  • the M code bits of the first digital signal or the M code bits of the second digital signal are thermometer codes; the resistance values of the M fourth resistors are equal.
  • the resistance values of the fourth resistors under the thermometer code are all equal, which can reduce the simulation of excessive voltage or current output when the fourth resistors with different resistance values output different voltages or currents as analog signals.
  • the signal deviation is too large, causing greater interference to the overall analog signal.
  • the second conversion unit further includes a fifth resistor; the first terminal of the fifth resistor is coupled to the first voltage terminal to input the first voltage or to the second voltage terminal to input the second voltage; The second end of the fifth resistor is used for coupling to the first coupling point; the resistance of the fifth resistor is equal to the resistance of the resistor corresponding to the lowest code bit of the second digital signal.
  • the embodiment of the present application can be used to better express the analog signal output by the digital-to-analog conversion, and can carry out the indicated value.
  • the second conversion unit further includes a fifth switch; a first end of the fifth resistor is coupled to the fifth switch; and the control unit is used to control the first end of the fifth resistor to be coupled to the fifth switch through the fifth switch.
  • the first voltage terminal or the first terminal controlling the fifth resistor is coupled to the second voltage terminal through the fifth switch.
  • control unit controls the fifth switch to adjust the input of the first resistor, which is a high voltage, or the second voltage, which is a low voltage, to the fifth resistor.
  • the N code bits of the first digital signal are binary codes; among the N first resistors, two first bits corresponding to adjacent code bits among the N code bits of the first digital signal are Between the resistors, the resistance of the first resistor corresponding to the lower code bit of the adjacent code bits among the N code bits of the first digital signal is the resistance value of the first resistor corresponding to the higher of the adjacent code bits among the N code bits of the first digital signal. Twice the resistance of the first resistor of the code bit.
  • a binary code is used as the N code bits of the first digital signal, and the number of corresponding first resistors is smaller than that of the thermometer code. It is suitable for applications with lower accuracy requirements and a smaller number of resistors. Scenes.
  • the N code bits of the first digital signal are thermometer codes; the resistance values of the N first resistors are equal.
  • the resistance values of the first resistors under the thermometer codes are all equal, which can reduce the problem of excessive voltage or current output when the first resistors with different resistance values output different voltages or currents as analog signals.
  • the deviation of the analog signal is too large, causing greater interference to the overall analog signal.
  • the first conversion unit further includes a sixth resistor; the first terminal of the sixth resistor is coupled to the first voltage terminal to input the first voltage or to the second voltage terminal to input the second voltage; The resistance of the sixth resistor is equal to the resistance of the resistor corresponding to the lowest code bit of the first digital signal.
  • the sixth resistor by setting the sixth resistor, it can be used to better express the analog signal output by the digital-to-analog conversion, and can Carry out the value indicated by the output analog signal.
  • the first conversion unit further includes a sixth switch; a first end of the sixth resistor is coupled to the sixth switch; and the control unit is used to control the first end of the sixth resistor to be coupled to the sixth switch through the sixth switch.
  • the first voltage terminal or the first terminal controlling the sixth resistor is coupled to the second voltage terminal through the sixth switch.
  • control unit controls the sixth switch to adjust the input of the first resistor, which is a high voltage, or the second voltage, which is a low voltage, to the sixth resistor.
  • a digital-to-analog conversion circuit including a resistive digital-to-analog converter and a driving amplifier as described in the first aspect; the driving amplifier is coupled to the output end of the resistive digital-to-analog converter; the resistive digital-to-analog conversion circuit The converter is used to input digital signals and generate analog signals to be output to the driving amplifier. The driving amplifier is used to amplify the analog signals.
  • an electronic device in a third aspect, includes a resistive digital-to-analog converter as described in the first aspect or a digital-to-analog conversion circuit as described in the second aspect; the resistive digital-to-analog converter or the digital-to-analog conversion circuit is used for Generates an analog signal based on the input digital signal.
  • Figure 1 is a schematic structural diagram of a digital-to-analog converter provided by an embodiment of the present application
  • Figure 2 is a schematic structural diagram of another digital-to-analog converter provided by an embodiment of the present application.
  • Figure 3 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • Figure 4 is a schematic structural diagram of another electronic device provided by an embodiment of the present application.
  • Figure 5 is a schematic structural diagram of a digital-to-analog converter provided by an embodiment of the present application.
  • Figure 6 is a schematic structural diagram of a first switch provided by an embodiment of the present application.
  • Figure 7 is a schematic structural diagram of another digital-to-analog converter provided by an embodiment of the present application.
  • Figure 8 is a schematic structural diagram of another digital-to-analog converter provided by an embodiment of the present application.
  • Figure 9 is a schematic structural diagram of another digital-to-analog converter provided by an embodiment of the present application.
  • Figure 10 is a schematic structural diagram of a resistor voltage dividing unit provided by an embodiment of the present application.
  • Figure 11 is a schematic structural diagram of a digital-to-analog converter provided by an embodiment of the present application.
  • Figure 12 is a schematic structural diagram of a parallel resistance segmentation unit provided by an embodiment of the present application.
  • Figure 13 is a schematic structural diagram of another parallel resistance segmented unit provided by an embodiment of the present application.
  • Figure 14 is a schematic structural diagram of another parallel resistance segmented unit provided by an embodiment of the present application.
  • Figure 15 is a schematic structural diagram of a second conversion unit provided by an embodiment of the present application.
  • Coupled and “connection” involved in the embodiments of this application should be understood in a broad sense. For example, they may refer to a physical direct connection, or they may refer to an indirect connection realized through electronic devices, such as resistance, inductance, capacitance or other electronic devices.
  • the connection implemented by the device.
  • Digital-to-analog converter as a device that converts digital signals into analog voltage signals, plays an indispensable role in today's electronic device field.
  • Common digital-to-analog converters include current steering digital-to-analog converter (IDAC) and digital-to-analog converter (resistor digital-to-analog converter, RDAC).
  • IDAC current steering digital-to-analog converter
  • RDAC resistor digital-to-analog converter
  • current-mode digital-to-analog converters are often used.
  • digital-to-analog converters are difficult to apply in high-speed and high-precision processing scenarios.
  • the embodiment of the present application provides a digital-to-analog converter, as shown in Figure 1.
  • the digital-to-analog converter 1 divides the voltage by dividing the resistance into segments, and finally realizes the corresponding processing of the digital signal containing multiple bits.
  • Analog signals provide high-precision feedback.
  • this embodiment requires adding multiple registers 11, which increases device cost and area.
  • the embodiment of the present application also provides a digital-to-analog converter.
  • the digital-to-analog converter 1 includes two high-stage series units 14 and one low-stage series unit 15 .
  • a digital signal including a plurality of bits is segmented into a high-segment digital signal including a high-code segment and a low-segment digital signal including a low-code segment.
  • Each high-stage series unit 14 includes a plurality of high-stage resistors 12 corresponding to the bits of the high-stage digital signal.
  • the input terminal of one of the high-stage series units 14 is used to input positive voltage, and the input terminal of the other high-stage series unit 14 is used to input negative voltage.
  • the low-stage series unit 15 includes a plurality of series-connected low-stage resistors 13 , and the two ends of the series-connected plurality of low-stage resistors 13 are respectively coupled to the output terminals of the two high-stage series units 14 . According to the value of the low-stage digital signal, the first end or the second end of a certain low-stage resistor 13 among the plurality of low-stage resistors 13 is selected as a coupling point to output an analog signal.
  • the embodiment of the present application realizes that after the high-stage series unit 14 outputs the analog signal corresponding to the high-stage digital signal to the low-stage series unit 15, the low-stage series unit 15 then outputs an analog signal that combines the low-stage digital signal and the high-stage digital signal.
  • the analog signal corresponding to the digital signal can be added to the high-stage series unit 14 and the low-stage series unit 15 to select different numbers and resistance values of the high-stage resistors 12 and low-stage resistors 13 to output analog signals.
  • an embodiment of the present application provides an electronic device.
  • the electronic device 2 includes a digital-to-analog converter 3 .
  • the electronic device 2 includes a digital-to-analog conversion circuit, and the digital-to-analog conversion circuit includes a digital-to-analog converter 3 and a driving amplifier 4 .
  • the digital-to-analog converter 3 or the digital-to-analog conversion circuit is used to generate an analog signal according to the input digital signal.
  • the electronic device 2 may be a sigma selta modulator (SDM), a successive approximation register (SAR), a sensor, a digital graphics processor, an audio processor, etc.
  • SDM selta modulator
  • SAR successive approximation register
  • sensor a digital graphics processor
  • audio processor etc.
  • the digital-to-analog converter 3 includes a first voltage terminal, a second voltage terminal, a control unit 30 and a first conversion unit 31 .
  • the first voltage terminal is used to provide a first voltage
  • the second voltage terminal is used to provide a second voltage
  • the control unit 30 is used to input a first digital signal, the first digital signal includes N code bits
  • the first conversion unit 31 It includes N first switches 311 and N first resistors 312 that correspond one-to-one to the N code bits of the first digital signal; as shown in Figure 6, the first terminals of the N first switches 311 are used to input the first voltage, the second terminals of the N first switches 311 are used to input the second voltage; the third terminal of each first switch 311 is coupled to the first terminal of the corresponding first resistor 312; the receiver of each first switch 311
  • the control terminal is used to input one of the N code bits of the first digital signal, so as to be controlled by the first digital signal to conduct the first end of the first switch 311 and the third end of the first
  • the second ends of the N first resistors 312 are coupled to the first coupling point 314 ; the first coupling point 314 serves as the output terminal of the first conversion unit 31 for outputting N values corresponding to the first digital signal.
  • the first analog signal corresponding to code bits.
  • all the first resistors 312 are respectively corresponding to one of the N code bits of the first digital signal, and then the first voltage or the second voltage is selected to be input according to the value of the code bit, and then The second terminals of all first resistors 312 are coupled to the first coupling point 314 as output terminals.
  • the first analog signal corresponding to N code bits of the first digital signal is output through the first coupling point 314.
  • all the first resistors 312 can be equivalently connected in parallel. Regardless of whether the corresponding first resistor inputs the first voltage or the second voltage, it must provide a resistance value for the entire first conversion unit 31.
  • the equivalent resistance R 1 of the first conversion unit 31 is the equivalent resistance of all the first resistors 312 connected in parallel, which is smaller than the resistance of the first resistors 312 and has a constant resistance value.
  • the output impedance Rout of the first conversion unit 31 R 2 /2, where R 2 is the N codes of the first digital signal.
  • the output impedance of the first conversion unit 31 is constant and is smaller than the resistance value of the first resistor 312 .
  • the output impedance Rout of the first conversion unit 31 R 3 /2 N
  • R 3 is when the N code bits of the first digital signal are the thermometer code.
  • the resistance value of the first resistor 312 corresponding to the highest code bit. It can be seen that when the N code bits of the first digital signal are fixed as thermometer codes, the output impedance of the first conversion unit 31 is smaller than when the N code bits of the first digital signal are binary codes, and when the N code bits of the first digital signal are fixed as binary codes, the output impedance of the first conversion unit 31 is smaller.
  • the resistance of resistor 312 is constant, the equivalent impedance is also constant.
  • the output impedance of the digital-to-analog converter 3 can be reduced to a very small value, and there is no need to greatly reduce the resistance of the first resistor 312 during the implementation process.
  • a resistor with a conventional resistance is used as the first resistor.
  • Resistor 312 can obtain a stable and very small output impedance. High-precision and high-speed digital-to-analog conversion can be achieved without using a larger-sized overcurrent switch.
  • the N code bits of the first digital signal are binary codes.
  • the N code bits of the first digital signal can be expressed as xxxx, the first voltage is a high voltage, and the second voltage is a low voltage.
  • N is the number of bits of the binary code, which is 4.
  • the controlled terminals of the four first switches 311 respectively correspond to the 0-bit, 1-bit, 2-bit and 3-bit input of the first digital signal.
  • the first terminal and the third terminal of the first switch 311 are turned on to output a first voltage that is a high voltage to the first resistor 312; when the value of the corresponding bit is high, When it is low, the second terminal and the third terminal of the first switch 311 are turned on to output a second voltage that is a low voltage to the first resistor 312 .
  • the different voltage values of the first voltage and the second voltage correspond to the corresponding value of each bit being 0 or 1.
  • a certain bit is 1, it means that the value is high, then use The first voltage that is a high voltage represents the value.
  • a certain bit is 0, it represents that the value is low, and the second voltage that is a low voltage represents the value.
  • different bits represent different number sizes. Take 1000, 0100, 0010, 0001 as an example. 1 of 1000 is a 3-bit value, which represents the decimal number 8. 0100 is a 2-bit value, and Represents the decimal number 4.
  • 0010 is the value of 1 bit, which represents the decimal number 2.
  • 0001 is the value of the 0 bit, which represents the decimal number 1.
  • the value of the high bit is twice the value of the low bit. Therefore, there are multiple first resistors 312 representing different bits. According to the level of the corresponding bit, different resistance values can be assigned to the first resistor 312 corresponding to different bits. The higher the bit, the lower the resistance of the first resistor 312. When the same voltage is input ( (such as the first voltage), the lower the resistance of the first resistor 312, the less it divides the first voltage, so that a higher voltage value can be output to correspond to a higher bit value.
  • the resistance of the first resistor 312 with the lower bit is the higher bit. bit twice the resistance of the first resistor 312 .
  • the N code bits of the first digital signal are thermometer codes.
  • the resistance values of the N first resistors 312 are equal.
  • thermometer code 2 n -1
  • n the number of bits of the binary code.
  • Table 1 taking the input of a 3-bit first digital signal as an example, the first digital signal is a binary code, that is, the first digital signal can be expressed as xxx, the first voltage is a high voltage, and the second voltage is a low voltage.
  • n is the number of bits of the binary code, which is 3.
  • a total of 8 different values from the numerical value 0 (10) to the numerical value 7 (10) in the decimal system can be expressed through the first digital signal of 3 bits.
  • the code bits of the thermometer code correspond to 7 bits, that is, the N code bits of the first digital signal are 7 code bits.
  • the value of the number N of the first resistor 312 corresponds to the code bit of the thermometer code, which is 7.
  • the controlled terminals of the seven first switches 311 respectively correspond to 1 of the 7 code bits of the input first digital signal.
  • the code bit reaches code bit 7, when the value of the corresponding bit is 1, the first terminal and the third terminal of the first switch 311 are turned on to input a first voltage that is a high voltage to the first resistor 312; when When the value of the corresponding bit is 0, the second terminal and the third terminal of the first switch 311 are turned on to input a second voltage that is a low voltage to the first resistor 312 .
  • the values corresponding to the 7 code bits are all 0, that is, the controlled terminals of the seven first switches 311 are turned on and the corresponding first switches 311 are turned on.
  • the second terminal and the third terminal are used to input a second voltage that is a low voltage to the seven first resistors 312 .
  • the controlled end of the first switch 311 corresponding to 1 code bit turns on the first end and the third end of the corresponding first switch 311,
  • the first voltage that is a high voltage is input to the first resistor 312 corresponding to 1 code bit, and the controlled end of the first switch 311 corresponding to the remaining 6 code bits is turned on to the second end and the third end of the corresponding first switch 311.
  • the input of the first resistor 312 corresponding to the 1 code bit and the 2 code bit is a high voltage first voltage
  • the 3 code bit to 7 The input of the first resistor 312 corresponding to the code bit is a low voltage second voltage.
  • the seven first resistors 312 all input a high first voltage.
  • thermometer codes when a binary code is used to control the switch to output the corresponding analog signal, since the resistance value of the resistor corresponding to each bit of the binary code is different, the resistance value of the resistor corresponding to the high bit bit is smaller. If it is small, the output voltage or current will be large. If the resistance of the low-bit resistor is too large, the output voltage or current will be small. When outputting completely different voltages or currents as analog signals, larger analogs will produce greater interference errors at the output, thus affecting the overall accuracy, in the form of thermometer codes.
  • the code bit of each thermometer code actually corresponds to the decimal value 1, so the resistance value of the resistor corresponding to the code bit of each thermometer code is equal, which can reduce the occurrence of such interference errors.
  • the number of the first resistors 312 can be doubled, and the first switches 311 can be modified into twice the number of single-pole single-throw switches.
  • Half of the first resistors 312 input the first voltage through the corresponding single-pole single-throw switch, and the other half of the first resistor 312 inputs the second voltage through the corresponding single-pole single throw switch; each of the first resistors 312 inputs the first voltage.
  • the first resistors 312 respectively correspond to one code bit among the N code bits of the first digital signal; each first resistor 312 inputting the second voltage also corresponds to one code bit among the N code bits of the first digital signal respectively;
  • One of the N code bits of a digital signal controls the corresponding first resistor 312 for inputting the first voltage and the corresponding first resistor 312 for inputting the second voltage, one of the two first resistors 312 in total. Coupled to first coupling point 314.
  • the principle of using the single-pole single-throw switch in this embodiment is essentially the same as the principle of using the first switch 311 .
  • a segmented approach may be used to implement high-speed and high-precision digital-to-analog processing in the case of a digital signal with a large number of bits. Convert.
  • a segmentation method is: input a first digital signal including multiple code bits, and segment the first digital signal into N code bits in the high bit segment and E code bits in the low bit segment. .
  • a second digital signal corresponding to the N code bits of the high-order segment of the first digital signal is also generated.
  • the second digital signal includes N code bits, and the value ratio of the N code bits of the second digital signal is The value of N code bits of the first digital signal is large.
  • the digital-to-analog converter 3 also includes a second conversion unit 32 and a resistor voltage dividing unit 33 .
  • the resistor voltage dividing unit 33 includes a first resistor module 331 and a second resistor module 332; the first end of the first resistor module 331 and the output end of the first conversion unit 31 (ie, the first coupling point 314) Coupling, the second end of the first resistance module 331 and the first end of the second resistance module 332 are coupled to the third coupling point 333; the second end of the second resistance module 332 is coupled to the output end of the second conversion unit 32;
  • the three coupling points 333 serve as the output terminals of the digital-to-analog converter 3 .
  • the second conversion unit 32 includes N second switches 321, N second resistors 322 and a second segment unit 323; the first terminals of the N second switches 321 are used to input the first voltage, The second terminals of the N second switches 321 are used to input the second voltage; the third terminal of each second switch 321 is coupled to the first terminal of the corresponding second resistor 322; the controlled terminal of each second switch 321 Used to input one of the N code bits of the second digital signal to conduct the first end of the second switch 321 and the third end of the second switch 321 under the control of the second digital signal, or to conduct the third end of the second switch 321 under the control of the second digital signal.
  • the control of the two digital signals connects the second end of the second switch 321 to the third end of the second switch 321; the first end of the second segment unit 323 is used to input the first voltage or the second voltage; the Nth The second end of the two resistors 322 is coupled to the second coupling point 324; the second coupling point 324 serves as the output terminal of the second conversion unit 32 and is used to output a second analog signal corresponding to N code bits of the second digital signal.
  • the first digital signal including multiple code bits is segmented into N code bits of the first digital signal located in the high code bit section and E of the first digital signal located in the low code bit section. code bits, and at the same time, a second digital signal is also generated.
  • the second digital signal includes N code bits, and the value of the N code bits of the second digital signal is greater than the value of the N code bits of the first digital signal.
  • the value is large (for example, the N code bits of the first digital signal have a value of 13(10), and the N code bits of the second digital signal have a value of 14(10)).
  • the first conversion unit 31 generates a first analog signal corresponding to the N code bits of the first digital signal
  • the second conversion unit 32 generates a second analog signal corresponding to the N code bits of the second digital signal.
  • the first analog signal is output to the first resistance module 331 through the first coupling point 314; the second analog signal is output to the second resistance module 332 through the second coupling point 324.
  • the third coupling point 333 serves as the output end of the digital-to-analog converter 3 to output a third analog signal.
  • the third analog signal is used to express the N code bits of the first digital signal in the high code bit section and the first number in the low code bit section.
  • the E code bits of the signal are combined into the first digital signal of multiple code bits.
  • the corresponding analog signal (for example, if the first digital signal is a binary signal 1010 1011, it can be segmented into 1010 in the high code bit segment (corresponding to the N code bits of the first digital signal) and 1011 in the low code bit segment (corresponding to the N code bits of the first digital signal).
  • E code bits of a digital signal at this time N is 4 and E is 4).
  • the E code bits of the first digital signal are used as the digital signal in the low code bit segment, and are used to control the resistance values of the first resistance module 331 and the second resistance module 332 .
  • the resistance value of the E code bits of the first digital signal is lower, the resistance value of the second resistance module 332 is higher, and the resistance value of the first resistance module 331 is lower.
  • the output third analog signal is closer to to the first analog signal.
  • the resistance value of the second resistance module 332 is lower, and the resistance value of the first resistance module 331 is higher. At this time, the output third analog signal is closer to to the second analog signal.
  • the value of the N code bits of the second digital signal is one greater than the value of the N code bits of the first digital signal.
  • the difference between the N code bits of the second digital signal and the N code bits of the first digital signal represents the E code bits of the first digital signal.
  • the value range of Adding 1 corresponds to the lowest code bit value among the N code bits of the first digital signal being 1.
  • the value of the N code bits of the second digital signal is set to be 1 greater than the value of the N code bits of the first digital signal, so that the third analog signal can be better used to indicate the value of the first digital signal.
  • the value of the first digital signal obtained by combining N code bits and E code bits of the first digital signal.
  • the value of the N code bits of the second digital signal is greater than the value of the N code bits of the first digital signal by a value other than 1, by adjusting the resistance of the first resistance module 331 and the second resistance module 332
  • the corresponding relationship between the value and the resistance value of the first resistor 312 and the second resistor 322 can also be obtained by using a third analog signal to indicate the N code bits of the first digital signal and the E code bits of the first digital signal. The value of the first digital signal.
  • the N code bits of the second digital signal are binary codes.
  • the resistance value of the second resistor 322 of the low bit bit is the high bit bit. bit twice the resistance of the second resistor 322 .
  • the resistance of the second segmentation unit 323 is equal to the resistance of the second resistor 322 corresponding to the lowest bit among the N code bits of the second digital signal.
  • the N code bits of the second digital signal are thermometer codes.
  • the resistance values of the N second resistors 322 are equal.
  • the resistance of the second segmentation unit 323 is equal to the resistance of the second resistor 322 .
  • the description of the relevant technical effects of the second segmentation unit 323 and the second resistor 322 in the second conversion unit 32 may refer to the above-mentioned N of the first digital signal.
  • the code bits are related descriptions of the binary code and the thermometer code, which will not be described again.
  • the resistor voltage dividing unit 33 specifically includes an output selection switch 334 and E third resistors 330 ; one end of the E third resistors 330 connected in series is coupled to the first coupling point 314 , the other end is coupled to the second coupling point 324; the selection input end of the output selection switch 334 is used to couple E code bits controlled by the first digital signal to the third resistor 330 of one of the E third resistors 330.
  • One end or the second end, and the coupling point between the selection input end of the output selection switch 334 and the first end or the second end of a third resistor 330 serves as the third coupling point 333; the third coupling point 333 and the first coupling point 314
  • the third resistor 330 between them is used to form the first resistance module 331
  • the third resistor 330 between the third coupling point 333 and the second coupling point 324 is used to form the second resistance module 332 .
  • the output third analog signal is closer to the second analog signal. Then, by adjusting the selection input terminal of the output selection switch 334 The coupling position, that is, the position of the third coupling point 333, reduces the number of the third resistor 330 between the second coupling point 324 and the third coupling point 333, thereby reducing the The resistance of the second resistance module 332 between them is increased, and the resistance of the first resistance module 331 between the first coupling point 314 and the third coupling point 333 is increased.
  • the value of the number E of the third resistor 330 is 2 n -1, where n is the E code bits of the first digital signal. The number of bits in binary code. And the resistance value of each third resistor 330 is equal.
  • the E code bits of the first digital signal are thermometer codes
  • taking the thermometer code corresponding to a four-bit binary code in which the low code bit segment of the first digital signal is an example 15 code points, ranging from code point 1 to code point 15 respectively.
  • the third coupling point 333 coincides with the first coupling point 314, that is, the second resistance module 332 includes 15 third resistors 330, and the first resistance module 331 includes zero third resistors 330 .
  • the second analog signal and the first analog signal are connected in parallel and output from the third coupling point 333.
  • the first analog signal is output from the first coupling point 314 of the first conversion unit 31, it does not need to pass through any third resistor 330.
  • the voltage is divided, and the second analog signal is output from the second coupling point 324 of the second conversion unit 32, passes through 15 third resistors 330, and then is output to the third coupling point 333.
  • the final output third analog signal is equal to the first The value of the analog signal.
  • the value of the third analog signal is 15 (10)
  • the third coupling point 333 coincides with the second coupling point 324.
  • the second analog signal can be output without going through the voltage division of the third resistor 330. to the third coupling point 333, and the first analog signal needs to pass through 15 third resistors 330 before it can be output to the third coupling point 333.
  • the value of the output third analog signal is equal to the second analog signal.
  • the digital-to-analog converter 3 further includes a first bridge resistor 34 , and the output end of the first conversion unit 31 (ie, the first coupling point 314 ) is coupled through the first bridge resistor 34 to the first end of the first resistor module 331 .
  • the digital-to-analog converter 3 further includes a second bridge resistor 35 , and the output end of the second conversion unit 32 (ie, the second coupling point 324 ) is coupled through the second bridge resistor 35 to the second end of the second resistor module.
  • the equivalent resistance of the first conversion unit 31 is added to the equivalent resistance of the second conversion unit 32 and the resistance of the first bridge resistor 34 .
  • the sum of the obtained resistance values is equal to the resistance value of a third resistor 330 .
  • the equivalent resistance of the first conversion unit 31 and the second conversion unit 32 can be appropriately increased or decreased, and thus the first resistor 312 and the second resistor can be better set. 322 resistance.
  • the equivalent resistance of the first conversion unit 31 is added to the equivalent resistance of the second conversion unit 32 and the resistance of the second bridge resistor 35.
  • the sum of the resistance values is equal to the resistance value of a third resistor 330 .
  • the equivalent resistance of the first conversion unit 31 and the second conversion unit 32 can be appropriately increased or decreased, and thus the first resistor 312 and the second resistor can be better set. 322 resistance.
  • the digital-to-analog converter 3 includes the second bridge resistor 35
  • the equivalent resistance of the first conversion unit 31 plus the equivalent resistance of the second conversion unit 32 and the resistance of the first bridge resistor 34 The sum of the resistances obtained by connecting the two bridge resistors 35 is equal to the resistance of a third resistor 330 .
  • the equivalent resistance values of the first conversion unit 31 and the second conversion unit 32 can be appropriately increased or decreased, thereby better setting the first conversion unit 31 and the second conversion unit 32.
  • the sum of the equivalent resistance of the first conversion unit 31 and the resistance of the first bridge resistor 34 may be equal to the sum of the equivalent resistance of the second conversion unit 32 and the resistance of the second bridge resistor 35 .
  • the equivalent resistance of the first conversion unit 31 may be equal to the equivalent resistance of the second conversion unit 32 , and the equivalent resistance of the first conversion unit 31 may not be equal to that of the second conversion unit 32 . Equivalent resistance.
  • the equivalent resistance or resistance value of the first conversion unit 31 , the second conversion unit 32 , the first bridge resistor 34 and the second bridge resistor 35 is not limited. Completely equal, partially equal or completely unequal, it only needs to be satisfied that the equivalent resistance value or the sum of the resistance values of the four is equal to the resistance value of a third resistor 330.
  • the first conversion unit 31 further includes a fifth resistor 315; the resistance of the fifth resistor 315 is equal to the resistance value corresponding to the lowest code bit of the first digital signal.
  • the first terminal of the fifth resistor 315 is fixedly coupled to the first voltage terminal for inputting the first voltage, or the first terminal of the fifth resistor 315 is fixedly coupled to the second voltage terminal for inputting the second voltage;
  • the second end is coupled to first coupling point 314 .
  • the first digital signal includes N code bits, and the N code bits are thermometer codes, N first resistors 312 are included. Each first resistor 312 corresponds to outputting a voltage. According to the different values of the N code bits of the first digital signal at the first coupling point 312, the output voltage is output when the code bit corresponding to the first resistor 312 is 1. Taking the value of one voltage as 1/N as an example, the first coupling point 312 can output voltages with values of 0/N, 1/N, 2/N, ..., N/N. And after setting a fifth resistor 315.
  • the fifth resistor 315 When the fifth resistor 315 is fixedly coupled to the second voltage terminal, the fifth resistor 315 has a fixed output value of 0/(N+1), and the first coupling point 312 can output a voltage of 0/(N+1). , 1/(N+1), 2/(N+1),..., N/(N+1) voltages can be used to express binary numbers 0 to N, and at this time, it is more conducive to the first conversion unit 31 for carry calculation.
  • the fifth resistor 315 when the fifth resistor 315 is fixedly coupled at the At one voltage terminal, the fifth resistor 315 has a fixed output value of 1/(N+1), while the first coupling point 312 can output a voltage of 1/(N+1), 2/(N+1), ..., the voltage of (N+1)/(N+1) can be used to express the binary numbers 1 to N+1.
  • the resistance of the fifth resistor 315 is the resistance of the first resistor 312 corresponding to the lowest code bit among the N code bits of the first digital signal.
  • the first conversion unit 31 further includes a fifth switch 316 .
  • the first end of the fifth resistor 315 is coupled to the fifth switch 316; the control unit 30 is used to control the first end of the fifth resistor 315 to be coupled to the first voltage end or control through the fifth switch 316.
  • the first terminal of the fifth resistor 315 is coupled to the second voltage terminal through the fifth switch 316 .
  • control unit 30 controls the fifth switch 315 to couple the first terminal of the fifth resistor 315 to the first voltage terminal or the second voltage terminal, so as to realize the first conversion unit 31 to represent the value.
  • the second conversion unit 32 also includes a sixth resistor 325; the resistance of the sixth resistor 325 is equal to the lowest code bit among the N code bits of the second digital signal. resistance value.
  • the first terminal of the sixth resistor 325 is fixedly coupled to the first voltage terminal for inputting the first voltage, or the first terminal of the sixth resistor 325 is fixedly coupled to the second voltage terminal for inputting the second voltage;
  • the second end is coupled to second coupling point 324.
  • the second conversion unit 32 further includes a sixth switch 326 .
  • the first end of the sixth resistor 325 is coupled to the sixth switch 326; the control unit 30 is used to control the first end of the sixth resistor 325 to be coupled to the first voltage end or control through the sixth switch 326.
  • the first terminal of the sixth resistor 325 is coupled to the second voltage terminal through the sixth switch 326 .
  • digital-to-analog conversion is performed on a set of digital signals including multiple values that continuously increase by 1.
  • each digital signal in the group of digital signals is segmented into N code bits of the first digital signal in the high code bit section and E code bits of the first digital signal in the low code bit section. code point.
  • the E code bits of the first digital signal in the low code bit segment are input into the resistor voltage dividing unit to control the resistance values of the first resistor module 331 and the second resistor module 332 .
  • the 3-bit digital signal 010(2) is segmented into a high code bit segment (i.e. N code bits of the first digital signal ) and the 3-bit digital signal 011(2) of the low code bit segment (ie, the E code bits of the first digital signal), input the 3-bit digital signal 010(2) of the high code bit segment to the first conversion unit 31, a 3-bit digital signal 011(2) (that is, N code bits of the second digital signal) that is 1 larger than the value of the 3-bit digital signal 010(2) in the high code bit segment is generated and input to In the second conversion unit 32, the 3-bit digital signal 011(2) of the low code bit section is then input to the resistor voltage dividing unit 33.
  • a high code bit segment i.e. N code bits of the first digital signal
  • the 3-bit digital signal 011(2) of the low code bit segment ie.e. the E code bits of the first digital signal
  • digital-to-analog conversion on a digital signal of 1 for example, when performing digital-to-analog conversion on a digital signal with a value of 010 011(2)-010 111(2), it is only necessary to change the first digital signal in the input resistor voltage dividing unit 33
  • the value of E code bits is enough, that is, the value of 011(2) is gradually increased by 1 until it is 111(2).
  • the E code bits of the first digital signal reach 111(2), there are the following two ways to continue the digital-to-analog conversion of the first digital signal whose subsequent value is increased by 1:
  • Method 1 Add 1 to the value of the N code bits of the first digital signal input to the first conversion unit 31, and add 1 to the value of the N code bits of the second digital signal input to the second conversion unit 32. , and re-couple the output selection switch 334 in the resistor voltage dividing unit 33 to the coupling point representing the lowest value, that is, the third coupling point 333 is close to the first coupling point 314 . Then continue to add 1 to the values of the E code bits of the first digital signal in the input resistor voltage dividing unit 33 in sequence, so as to perform digital analog processing on multiple digital signals in which the consecutive values in a group of digital signals are added by 1. Convert.
  • Method 2 Add 2 to the value of N code bits of the first digital signal input into the first conversion unit 31 .
  • the N code bits of the second digital signal input into the second conversion unit 32 are used as the high code bit section of the digital signal to be converted to digital-to-analog, and then the low code bit section of the digital signal to be subjected to digital to analog conversion is used.
  • the E code bits are used as the E code bits of the first digital signal to control the output selection switch 334 to gradually move the third coupling point 333 from a position close to the second coupling point 324 of the second conversion unit 32 to the first coupling point 314 .
  • the E code bits representing the first digital signal have reached the highest count and cannot take a larger value.
  • the code bits are again used as the high code bit section of the digital signal to be converted to digital to analog, and the values of the E code bits of the low code bit section of the first digital signal to be subjected to digital to analog conversion continue to be increased by one one after another to express the Digital-to-analog conversion of a digital signal whose value gradually increases by 1.
  • the third coupling point 333 gradually approaches the second coupling point 324 from the first coupling point 314 .
  • the N code bits of the first digital signal and the N code bits of the second digital signal are alternately used as the high code bit segment of the digital signal for digital-to-analog conversion.
  • the equivalent resistance of the first conversion unit 31 is equal to the equivalent resistance of the second conversion unit 32 and equal to the resistance of the third resistor 330 .
  • method 2 is better at achieving differential nonlinearity (DNL) when implementing digital-to-analog conversion.
  • DNL differential nonlinearity
  • the sum of the equivalent resistance of the first conversion unit 31 and the resistance of the first bridge resistor 34 is equal to the second conversion unit 32
  • the second method is better for realizing differential nonlinearity (DNL) during digital-to-analog conversion. .
  • the fifth resistor 315 of the first conversion unit 31 and/or the sixth resistor 325 of the second conversion unit 32 can be a fixed input.
  • the first voltage is a high voltage to realize the numerical expression of 1(10) to 16(10), or the second voltage is fixed and input is a low voltage to realize the expression of 0(0) to 15(10).
  • the control unit 30 can be used to control the fifth switch 316 or the sixth switch 326 to switch the voltage input to the fifth resistor 315 or the sixth resistor 325 to be first voltage or second voltage.
  • N code bits of the first digital signal input to the first conversion unit 31 are used as the high code bit segment of the digital signal for digital-to-analog conversion. If both the first conversion unit 31 and the second conversion unit 32 can express a 4-bit digital signal, then when the value of the N code bits of the first digital signal is 15 (10), if the resistor voltage dividing unit 33 When the value reaches the maximum, it is necessary to carry to the higher code segment.
  • the first conversion unit 31 can adjust the voltage input to the fifth resistor 315 to the first voltage to achieve 16(10) Value expression, but the second conversion unit 32 cannot realize the expression of 17(10) for the N code bits of the second digital signal.
  • the second conversion unit 32 When the voltage input to the sixth resistor 325 is switched from the second voltage to the first voltage, the second conversion unit 32 can input N code bits of the second digital signal with a value of 16(10). At this time, the second digital signal is The N code bits are used as the high code bit segment of the digital signal for digital-to-analog conversion, thereby enabling continued digital-to-analog conversion of subsequent digital signals.
  • another segmentation method is to segment a digital signal including multiple bits into N code bits of the first digital signal in the high code bit segment and N code bits of the first digital signal in the low code bit segment. M code points.
  • a first segmentation unit 313 is provided in the first conversion unit.
  • the first segmentation unit 313 is configured as a parallel resistance segmentation unit.
  • the parallel resistance segmentation unit 5 includes M fourth switches 51 and M fourth resistors 52;
  • the first terminals of the M fourth switches 51 are used to input the first voltage, and the second terminals of the M fourth switches 51 are used to input the second voltage; the third terminal of each fourth switch 51 is coupled to the corresponding fourth The first end of the resistor 52; the controlled end of each fourth switch 51 is used to input one of the M code bits of the first digital signal, so as to be controlled by the M code bits of the first digital signal.
  • the first end of the fourth switch 51 is connected to the third end of the fourth switch 51, or the second end of the fourth switch 51 is connected to the third end of the fourth switch 51 under the control of M code bits of the first digital signal.
  • the second ends of the M fourth resistors 52 are coupled to the fourth coupling point 54;
  • the fourth coupling point 54 serves as the output end of the parallel resistor segment unit 5 and is coupled to the first coupling point 314 for transmitting to the first
  • the coupling point 314 outputs a fourth analog signal corresponding to M code bits of the first digital signal;
  • the first coupling point 314 serves as the output end of the digital-to-analog converter 3 and is used to output the first analog signal and the fourth analog signal.
  • the first digital signal including multiple bits there is a first digital signal including multiple bits
  • the first digital signal including multiple bits is segmented into N code bits and
  • the M code bits of the first digital signal in the low code bit segment are input into the first segmentation unit 313 of the parallel resistance segmentation unit 5, so that the first segmentation unit 313 outputs a fourth analog signal corresponding to the M code bits of the first digital signal in the low code bit section, and outputs it from the first coupling point 314 through the cooperation of the first switch 311 and the first resistor 312 as shown in Figure 5 N with the first digital signal of the high code bit segment
  • the first analog signal corresponding to the code bit The first analog signal corresponding to the code bit.
  • the sum of the first analog signal and the fourth analog signal output by the first coupling point 314 is used to express the analog signal corresponding to the first digital signal including multiple bits. .
  • the M code bits of the first digital signal are binary codes.
  • the number of the fourth resistors 52 is equal to the number of bits of the M code bits of the first digital signal.
  • the resistance of the fourth resistor 52 of the low bit is twice the resistance of the fourth resistor 52 of the high bit.
  • the resistance of the fifth resistor 315 is the resistance of the resistor corresponding to the lowest bit of the first digital signal.
  • the lowest bit of the first digital signal is the lowest bit among the M bits of the first digital signal. Therefore, at this time, the resistance of the fifth resistor 315 is equal to the resistance of the fourth resistor 52 corresponding to the lowest bit among the M bits of the first digital signal.
  • the M code bits of the first digital signal are thermometer codes.
  • the number M of the fourth resistor 52 is equal to 2 n -1, where n is the value when the M code bits of the first digital signal are binary codes. corresponding bit. And the resistance values of the M fourth resistors 52 are equal.
  • the resistance of the fifth resistor 315 is equal to the resistance of the fourth resistor 52 .
  • the resistance of the fifth resistor 315 is still equal to the resistance of the fourth resistor 52 corresponding to the lowest bit among the M bits of the first digital signal, but the resistances of the fourth resistors 52 at this time are all equal.
  • the equivalent resistance of the first segmentation unit 313 is equal to the lowest code bit among the N code bits of the first digital signal.
  • the corresponding resistance value of the first resistor 312. (That is, when the N code bits of the first digital signal are binary signals, the equivalent resistance of the first segmentation unit 313 needs to be equal to the resistance of the first resistor 312 with the largest resistance; when the N bits of the first digital signal When the code bit is a thermometer code, the equivalent resistance of the first segment unit 313 needs to be equal to the resistance of the first resistor 312).
  • the equivalent resistance value of the first segmentation unit 313 and the fifth resistor 315 is equal to the lowest code bit among the N code bits of the first digital signal.
  • the parallel resistance segmentation unit 5 may also include a third segmentation unit 53 .
  • the M code bits of the first digital signal may also be segmented to obtain the M code bits located at the first digital signal.
  • a fifth digital signal in a high code bit segment among the M code bits of a digital signal and a sixth digital signal located in a low code bit segment among the M code bits of the first digital signal.
  • the fifth digital signal of the high code bit section is converted to digital-to-analog through the fourth resistor 52, and the third segmentation unit 53 shown in Figure 12 is set as a parallel resistor divider as shown in Figure 12.
  • the structure of the segment unit 5 uses the structure of the parallel resistor segment unit 5 to perform digital-to-analog conversion on the sixth digital signal in the low code bit segment, and finally obtains an analog signal corresponding to the M code bits of the first digital signal.
  • N code bits N is 4 of the first digital signal of 4 bits in the high code bit segment and 6 bits of the low code bit segment.
  • M code bits M is 6 of the first digital signal are input into the digital-to-analog converter 3 shown in Figure 5, and the first resistor 312 of the digital-to-analog converter 3 shown in Figure 5 is used to pair the 4-bit first N code bits of a digital signal (N is 4) are subjected to digital-to-analog conversion.
  • the first segmentation unit 313 in Figure 5 is set to the structure of the parallel resistor segmentation unit 5 as shown in Figure 12.
  • the 6-bit M code bits of the first digital signal (M is 6) are input into the first segmentation unit 313 of the parallel resistor segmentation unit 5 structure for digital-to-analog conversion. Further, when processing the M code bits (M is 6) of the 6-bit first digital signal, the M code bits (M is 6) of the 6-bit first digital signal can be further segmented. For example, they are the fifth digital signal of 2 bits in the high code bit segment and the sixth digital signal of the 4 bit bit segment. The 2-bit fifth digital signal is input into the fourth resistor 52 of the parallel resistor segmentation unit 5 for digital-to-analog conversion.
  • the third segmentation unit 53 in the parallel resistance segmentation unit 5 shown in Figure 12 is set to the structure shown in Figure 12, and the low code bits are processed by the third segmentation unit 53.
  • the sixth digital signal of the segment undergoes digital-to-analog conversion.
  • reference numeral 51' represents the structure of the fourth switch 51 in the parallel-type resistance segmentation unit 5 shown in Figure 12
  • reference numeral 52' represents the structure of the fourth switch 51 in the parallel-type resistance segmentation unit 5 shown in Figure 12.
  • the fourth resistor 52 The structure of the fourth resistor 52; the reference numeral 53' represents the structure of the third segment unit 53 in the parallel resistor segment unit 5 shown in Figure 12; the reference numeral 55' represents the parallel resistor segment unit 5 shown in Figure 14
  • the segmented low code bit segment is passed through the parallel resistor segmenting unit 5
  • the digital signals in low-code bit segments can also be segmented, thereby achieving high-speed and high-precision digital-to-analog conversion of digital signals with more bits.
  • the fifth resistor 315 when the fifth resistor 315 is not set, between the parallel resistance segmentation units 5 corresponding to two adjacent code bit segments, the low code bit
  • the equivalent resistance value of the parallel resistance segmentation unit 5 of the segment is equal to the lowest code bit among the M code bits of the parallel resistance segmentation unit 5 of the input high code bit segment.
  • the parallel resistance segmentation unit 5 in the high code bit segment The corresponding resistance value of the fourth resistor 52 in the segment unit.
  • the equivalent resistance of the parallel resistance segmentation unit 5 of the low code bit segment and the fifth resistor 315 is The value is equal to the lowest code bit among the M code bits of the parallel-connected resistance segmentation unit 5 of the input high-code bit segment. In the parallel-connected resistance segmentation unit of the high-code bit segment, the resistance of the corresponding fourth resistor 52 value.
  • the parallel resistance segmentation unit 5 further includes a third bridge resistor 55 ; the fourth coupling point 54 is coupled to the first coupling point 314 through the third bridge resistor 55 .
  • the equivalent resistance value of the parallel resistance segmentation unit 5 when there is only one parallel resistance segmentation unit 5, the equivalent resistance value of the parallel resistance segmentation unit 5 needs to be the highest code bit among the N code bits of the first digital signal.
  • the corresponding resistance value of the first resistor 312. Therefore, after segmenting the multi-bit first digital signal into N code bits and M code bits, it is necessary to adjust the fourth resistor 52 in the parallel resistor segmenting unit 5 and the first resistor in the first conversion unit 31.
  • the equivalent resistance value of the parallel resistor segmentation unit 5 needs to be equal to the resistance value of the first resistor 312 corresponding to the lowest code bit among the N code bits of the first digital signal (in binary system: The maximum resistance of the first resistor 312).
  • the fourth resistor 52 needs to have a larger resistance value (especially when the M code bits of the first digital signal are binary codes, the lowest code bit among the M code bits of the first digital signal is The corresponding resistance of the fourth resistor 52 needs to be very large).
  • the equivalent resistance of the parallel-type resistor segment unit 5 is the sum of the equivalent resistances of the parallel-connected fourth resistor 52 and the parallel-type adjustment resistor 53 .
  • the equivalent resistance of the parallel resistance segment unit 5 is the sum of the equivalent resistances of the equivalent parallel fourth resistor 52 and the fifth resistor 315 plus the third bridge resistor. 55 resistance. Therefore, by setting the third bridge resistor 55, there is no need to set the fourth resistor 52 with an excessively large resistance during the segmentation process, which increases the possibility of realizing the solution.
  • the fourth resistor 52 and the first resistor 312 are The setting of the corresponding relationship between resistance values is also more flexible, and can be adaptively adjusted by adjusting the resistance value of the third bridge resistor 55 .
  • the unit 5 is also provided with a third segment unit 53.
  • the structure of the third segment unit 53 is similar to that of the parallel resistance segment unit 5.
  • the equivalent resistance values of the third segmentation unit 53 and the fifth resistor 315 corresponding to the sixth digital signal in the low code bit section need to be equal to the parallel resistance segment corresponding to the fifth digital signal in the high code bit section.
  • the resistance value of the fourth resistor 52 in unit 5 corresponding to the lowest code bit of the fifth digital signal needs to be reduced at this time the resistance value of the resistor 52' in the third segmentation unit 53.
  • the third segmentation unit 53 is also provided with a third bridge resistor 55, then the equivalent resistance of the third segmentation unit 53 and the fifth resistor 315 corresponding to the sixth digital signal of the low code bit segment is set to The sum of the resistance values of the third bridge resistors 55 in the third segmentation unit 53 is equal to the lowest code bit of the parallel resistor segment unit 5 corresponding to the fifth digital signal in the high code bit segment.
  • the resistance of the fourth resistor 52, and the resistance of the resistor 52' in the third segment unit 53 does not need to be reduced at this time to meet the implementation of the solution. Therefore, when performing multiple segmentation of digital signals, it is necessary to set up a structure of multiple parallel resistor segmentation units 5 as shown in FIG. 12 in the manner described in FIGS.
  • the third bridge resistor 55 is not provided in the parallel resistance segmentation unit 5, then when the digital signal is divided into multiple segments, the requirements for the fourth resistor 52 in the parallel resistance segmentation unit 5 of each segment are: It is very strict and represents the lower segment of the parallel resistance segmentation unit 5, the higher the resistance value of the fourth resistor 52 it is set. Without setting the third bridge resistor 55, its implementation is more difficult. of.
  • the third bridge resistor 55 is set in the plurality of parallel resistor segmentation units 5, by adjusting the value of the third bridge resistor 55, the fourth resistor 52 does not need to have an excessive resistance value, and the process is completed. Signal segmentation for more segments of digital signals.
  • the equivalent resistance corresponding to each segment of the digital signal is constant, and due to its equivalent parallel structure, the equivalent impedance of each segment output is fixed.
  • the output end of the digital-to-analog converter 3 is always the first coupling point 314, and the output impedance at the first coupling point 314 is the output impedance of the digital-to-analog converter 3, which is a fixed value. And is much smaller than the resistance of the first resistor 312. In this implementation mode, the output end of the digital-to-analog converter 3 can be directly connected to the load.
  • the driving amplifier 4 coupled to the output end of the digital-to-analog converter 3 can be Trans-impedance amplifier (TIA).
  • TIA Trans-impedance amplifier
  • the second conversion unit 32 in the second conversion unit 32 in the digital-to-analog converter 3 shown in Figures 7, 8, 9, 10, and 11 is used.
  • the segment unit 323 may also be configured as a parallel resistor segment unit 5 as shown in Figures 12, 13, and 14 above, to segment the second digital signal and perform digital-to-analog conversion respectively.
  • reference numeral 51' represents the structure of the fourth switch 51 in the parallel-type resistance segmentation unit 5 shown in Figure 12
  • reference numeral 52' represents the structure of the fourth switch 51 in the parallel-type resistance segmentation unit 5 shown in Figure 12.
  • the structure of the four resistors 52; reference numeral 53' represents the structure of the third segment unit 53 in the parallel resistor segment unit 5 shown in Figure 12.
  • the description of the second segmentation unit 323 being configured as a parallel resistor segmentation unit 5 may refer to the above-mentioned description of the first segmentation unit 313 being configured as a parallel resistor segmentation unit 5, so no Again.
  • the embodiment of the present application includes the digital-to-analog converter 3 with the structure shown in Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, Figure 10, Figure 11, Figure 12, Figure 13, Figure 14, and Figure 15, While reducing the equivalent impedance of the digital-to-analog converter 3, there is no need to reduce the resistance of the resistor, thereby avoiding the impact of the on-resistance of the over-current switch on the linearity of the digital-to-analog conversion due to the reduction in the resistance of the resistor. Influence. Since the input first voltage or second voltage is a constant voltage, there is no need to use a large-sized switch as the over-current switch.
  • the digital-to-analog converter 3 shown in Figure 13 and Figure 14 because the resistance of the digital-to-analog converter 3 is constant, its output end can be directly loaded with a load (such as a coupled transimpedance amplifier, etc.), and the op amp input point is Virtual location makes it easier to achieve high linearity design.
  • the output impedance of the digital-to-analog converter 3 shown in Figure 12, Figure 13, and Figure 14 is very small, and its output noise is only 4KT*Rout, where K is Boltzmann's constant, T is the absolute temperature, and Rout is the output impedance of digital-to-analog converter 3. Even if a current-mode digital-to-analog converter wants to achieve the same noise level, it still needs to set up 1 to 2 larger off-chip capacitors.
  • the disclosed devices, circuits, and devices can be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of unit modules is only a logical function division.
  • there may be other division methods for example, multiple modules or components may be combined. Either it can be integrated into another device, or some features can be ignored, or not implemented.
  • the coupling or direct coupling or communication connection between each other shown or discussed may be through some interfaces, indirect coupling or communication connection of devices or modules, which may be in electrical, mechanical or other forms.
  • modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located on one device, or they may be distributed to multiple devices. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional module in each embodiment of the present application can be integrated in one device, or each module can exist physically alone, or two or more modules can be integrated in one device.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

本申请实施例提出了一种数模转换器、数模转换电路和电子设备；用于数字信号处理领域。该数模转换器包括并联的第一电阻、第一开关。本申请实施例通过将第一开关和第一电阻与数字信号的各个码位相对应。并通过第一开关输入代表码位不同取值的第一电压或第二电压，并通过第一开关的受控端根据数字信号对应码位的取值将第一电压或第二电压通过所第一开关的第三端输出至第一电阻。所有第一电阻的第二端耦合至第一耦合点，向第一耦合点输出数字信号的各码位所对应的模拟信号。本申请实施例提供的数模转换器的输出阻抗较低且阻值恒定，实现了数模转换器在高速率及高精度下的应用。

Description

一种数模转换器、数模转换电路和电子设备
本申请要求于2022年08月03日提交国家知识产权局、申请号为202210930195.4，申请名称为“一种数模转换器、数模转换电路和电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及数字信号处理芯片技术领域，尤其涉及一种数模转换器、数模转换电路和电子设备。
背景技术
数模转换器(digital-to-analog converter，DAC)作为将数字信号转换为模拟电压信号的器件，在如今的电子器件领域具有不可或缺的作用。常见的数模转换器包括电流型数模转换器(current steering digital-to-analog converter，IDAC)和电阻型数模转换器(resistor digital-to-analog converter，RDAC)。随着芯片的高速发展，对数字信号的处理速率和处理精度的要求也越来越高。在对数字信号有着高速率高精度的处理要求的处理场景中，常常采用电流型数模转换器。
而对于电阻型数模转换器而言，在高速率要求的处理场景中，往往需要通过减小电阻的阻值来减小输出阻抗，从而增加信号处理的速率。而使用更小阻值的电阻又将增加电阻型数模转换器中的过电流开关的导通阻抗对数模转换器的线性度的影响。若通过增大过电流开关的尺寸来降低导通阻抗对数模转换器的线性度的影响，又会因增加过电流开关的尺寸而产生更大的寄生电容。故在现有的应用中，电阻型数模转换器难以实现保证高速率的同时还具有高精度。
发明内容
本申请实施例提供一种数模转换器、数模转换电路和电子设备，实现了让电阻型数模转换器具有高速率的同时还具有高精度。
为达到上述目的，本申请的实施例采用如下技术方案：
第一方面，提供了一种数模转换器，该数模转换器包括第一电压端、第二电压端、控制单元和第一转换单元，第一转换单元包括N个第一开关、N个第一电阻；第一电压端用于输入第一电压；第二电压端用于输入第二电压；控制单元用于接收第一数字信号，第一数字信号包括N个码位，与N个第一开关一一对应，控制单元根据第一数字信号的N个码位分别控制N个第一开关，使得与N个第一开关对应的第一电阻的第一端被耦合至第一电压端或第二电压端；N个第一电阻的第二端被耦合至第一耦合点；第一耦合点用于输出与第一数字信号的N个码位对应的第一模拟信号。
在本申请实施例中，通过N个第一电阻分别对应输入的第一数字信号的N个码位的不同码位，以输入第一电阻的第一电压或第二电压对应第一数字信号的N个码位的取值。本申请实施例通过将第一电阻的第二端耦合至第一耦合点的方式，实现了将N个第一电阻等效并联。此时，所有的第一电阻都可等效为并联的连接方式，不论对应的第一电阻输入的是第一电压还是第二电压，其都要为整个第一转换单元提供电阻值，故而第一转换单元的等效阻值R1为所有第一电阻等效并联后的阻值，其小于第一电阻的阻值，且为恒定的电阻值。进而，在第一数字信号的N个码位为固定输入的二进制码时，第一转换单元的输出阻抗Rout＝R2/2，其中R2为第一数字信号的N个码位中的最高码位所对应的第一电阻的阻值。在第一数字信号的N个码位为固定输入的温度计码时，第一转换单元的输出阻抗Rout＝R3/2N，R3为第一数字信号的N个码位中的最高码位所对应的第一电阻的阻值。可以看出，此时第一转换单元的输出阻抗很小，且为恒定值。而在本申请实施例的应用下，在第一电阻可以采用较大阻值的电阻，而无需减小电阻的阻值的情况下，得到了稳定且非常小的输出阻抗，在避免使用较大尺寸的过电流开关的情况下，即可实现高精度且高速率的数模转换。
在一种可能的实施方式中，第一数字信号还包括E个码位，第一数字信号的E个码位低于第 一数字信号的N个码位；数模转换器还包括电阻分压单元和第二转换单元；第二转换单元包括N个第二开关、N个第二电阻；控制单元还用于根据第一数字信号生成第二数字信号；第二数字信号包括N个码位，与N个第二开关一一对应，控制单元根据第二数字信号的N个码位分别控制N个第二开关，使得与N个第二开关对应的第二电阻的第一端被耦合至第一电压端或第二电压端；N个第二电阻的第二端被耦合至第二耦合点；第二耦合点用于输出与第二数字信号对应的第二模拟信号；第二数字信号的取值比第一数字信号的取值大；电阻分压单元的第一输入端耦合至第一耦合点，用于输入第一模拟信号，电阻分压单元的第二输入端耦合至第二耦合点，用于输入第二模拟信号；控制单元用于根据第一数字信号的E个码位控制电阻分压单元的输出端输出与第一数字信号的N个码位和第一数字信号的E个码位之和对应的第三模拟信号。
在本申请实施例中，通过将包括多个比特位的数字信号分段为高码位段的第一数字信号的N个码位和低码位段的第一数字信号的E个码位，同时，还生成了一个第二数字信号，该第二数字信号同样包括N个码位，且第二数字信号的N个码位的取值比第一数字信号的N个码位的取值大。通过第一转换单元生成第一数字信号的N个码位对应的第一模拟信号，通过第二转换单元生成第二数字信号的N个码位对应的第二模拟信号。第一模拟信号通过第一耦合点输出至电阻分压单元的第一输入端；第二模拟信号通过第二耦合点输出至电阻分压单元的第二输入端。第三耦合点作为数模转换器的输出端输出第三模拟信号，第三模拟信号用于表达高码位段的第一数字信号的N个码位和低码位段的第一数字信号的E个码位组合为多码位段的数字信号后所对应的模拟信号。第一数字信号的E个码位作为低码位段的数字信号，用于控制第一电阻模块和第二电阻模块的阻值。当第一数字信号的E个码位的取值越低，则输出的第三模拟信号更趋近于第一模拟信号。当第一数字信号的E个码位的取值越高，则输出的第三模拟信号更趋近于第二模拟信号。
在一种可能的实施方式中，电阻分压单元具体包括输出选择开关和E个第三电阻；串联后的E个第三电阻的一端作为电阻分压单元的第一输入端与第一耦合点耦合，串联后的E个第三电阻的另一端作为电阻分压单元的第二输入端与第二耦合点耦合；控制单元用于根据第一数字信号的E个码位的取值，将输出选择开关的选择输入端耦合至第三耦合点，第三耦合点为E个第三电阻中的一个第三电阻的第一端或第二端，第三耦合点与第一耦合点之间的所有第三电阻的阻值之和与第一数字信号的E个码位的取值对应。
在本申请实施例中，E个第三电阻中，相邻两个第三电阻之间有一个第三电阻耦合点，则E个第三电阻有E-1个第三电阻耦合点，且串联的E个第三电阻中，首尾各有一个未连接其他第三电阻的端点。则以E-1个第三电阻耦合点加上首尾的两个端点，可以得到E个端点，根据第一数字信号的E个码位的取值，以该E个端点中的一个作为第三耦合点。当第一数字信号的E个码位的取值越小，则第三耦合点越靠近第一耦合点，反之，第三耦合点越靠近第二耦合点。在本申请实施例中，通过调整输出选择开关的耦合位置，即第三耦合点的位置，使得第二耦合点和第三耦合点之间的第三电阻的数量减少，从而降低位于第二耦合点和第三耦合点之间的第二电阻模块的阻值，并增加位于第一耦合点和第三耦合点之间的第一电阻模块的阻值。当第一数字信号的E个码位的取值越高，则输出的第三模拟信号更趋近于第二模拟信号。
在一种可能的实施方式中，数模转换器还包括第一桥接电阻；第一转换单元的输出端通过第一桥接电阻耦合至电阻分压单元的第一输入端。
在本申请实施例中，当数模转换器包括第一桥接电阻时，第一转换单元的等效阻值加上第二转换单元的等效阻值以及第一桥接电阻的阻值得到的阻值之和等于一个第三电阻的阻值。此时，通过调整第一桥接电阻的阻值，可以适当增加或减少第一转换单元和第二转换单元的等效阻值，进而可以更好地设置第一电阻和第二电阻的阻值。
在一种可能的实施方式中，数模转换器还包括第二桥接电阻；第二转换单元的输出端通过第二桥接电阻耦合至第二电阻模块的第二端。
在本申请实施例中，当数模转换器包括第二桥接电阻时，第一转换单元的等效阻值加上第二转换单元的等效阻值以及第二桥接电阻的阻值得到的阻值之和等于一个第三电阻的阻值。此时，通过调整第二桥接电阻的阻值，可以适当增加或减少第一转换单元和第二转换单元的等效阻值，进而可以更好地设置第一电阻和第二电阻的阻值。同样的，当数模转换器包括第二桥接电阻时， 第一转换单元的等效阻值加上第二转换单元的等效阻值以及第一桥接电阻的阻值、第二桥接电阻的阻值得到的阻值之和等于一个第三电阻的阻值。此时，通过调整第一桥接电阻和第二桥接电阻的阻值，可以适当增加或减少第一转换单元和第二转换单元的等效阻值，进而可以更好地设置第一电阻和第二电阻的阻值。
在一种可能的实施方式中，第一数字信号的E个码位为温度计码；E个第三电阻的阻值相等。
在本申请实施例中，温度计码的每个码位对应一个第三电阻，且第三电阻的阻值相等。通过第三电阻的阻值的叠加时对应不同数值的叠加。在温度计码下的第三电阻阻值都相等，可以减少在不同的阻值的第三电阻输出不同的电压或电流作为模拟信号时，过大的电压或电流输出的模拟信号的偏差过大，对整体的模拟信号产生较大的干扰。
在一种可能的实施方式中，第二数字信号的N个码位为温度计码；N个第二电阻的阻值相等。
在本申请实施例中，温度计码下的第二电阻的阻值都相等，可以减少在不同的阻值的第二电阻输出不同的电压或电流作为模拟信号时，过大的电压或电流输出的模拟信号的偏差过大，对整体的模拟信号产生较大的干扰。
在一种可能的实施方式中，第二数字信号的N个码位为二进制码；N个第二电阻中，对应第二数字信号的N个码位中相邻码位的两个第二电阻之间，对应第二数字信号的N个码位中相邻码位的较低码位的第二电阻的阻值为对应第二数字信号N个码位中相邻码位的较高码位的第二电阻的阻值的两倍。
在本申请实施例中，使用二进制码作为第二数字信号的N个码位，其对应的第二电阻的数量相对于温度计码更少，适用于精度要求较低，且要求电阻数量较少的场景。
在一种可能的实施方式中，第一数字信号还包括M个码位；第一数字信号的M个码位高于第一数字信号的E个码位且低于第一数字信号的N个码位；第一转换单元还包括第一分段单元；第二转换单元还包括第二分段单元；第一分段单元的输出端与第一耦合点耦合至电阻分压单元的第一输入端；第二转换单元的输出端与第二耦合点耦合至电阻分压单元的第二输入端；控制单元还用于根据第一数字信号的M个码位控制第一分段单元向电阻分压单元的第一输入端输出与第一数字信号的M个码位所对应的第四模拟信号；生成第二数字信号的M个码位；第二数字信号的M个码位低于第二数字信号的N个码位；根据第二数字信号的M个码位控制第二分段单元向电阻分压单元的第二输入端输出与第二数字信号的M个码位所对应的第五模拟信号。
在本申请实施例中，例如有一个包括多个比特位的数字信号，将该包括多比特位的数字信号分段为高码位段的第一数字信号的N个码位和低码位段的第一数字信号的M个码位，通过第一数字信号的M个码位输入为并联型电阻分段电路的第一分段单元中，从而由第一分段单元输出与低码位段的第一数字信号的M个码位对应的第四模拟信号，通过第一开关和第一电阻配合，从第一耦合点处输出与高码位段的第一数字信号的N个码位对应的第一模拟信号，第一模拟信号和第四模拟信号之和，即用于表达该包括多个比特位的数字信号所对应的模拟信号。同时，适应性的，在第二转换单元中对应设置第二分段单元，此时第二数字信号的N个码位与第一数字信号的N个码位取值对应，但第二数字信号的M个码位的取值比第一数字信号的M个码位的取值大。
在一种可能的实施方式中，第一分段单元和第二分段单元为并联型电阻分段单元；并联型电阻分段单元包括与第一数字信号的M个码位或第二数字信号的M个码位一一对应的M个第四开关、M个第四电阻；控制单元用于根据第一数字信号的M个码位或第二数字信号的M个码位分别控制M个第四开关，使得与M个第四开关对应的第四电阻的第一端被耦合至第一电压端或第二电压端；M个第四电阻的第二端耦合至第四耦合点；第四耦合点用于输出与第一数字信号的M个码位所对应的第四模拟信号或与第二数字信号的M个码位所对应的第五模拟信号。
在本申请实施例中，通过多个第四电阻等效并联的方式实现并联型电阻分段单元，可以保证整体电路的等效阻值和输出阻抗保持恒定。
在一种可能的实施方式中，并联型电阻分段单元还包括第三桥接电阻；第四耦合点耦合至第三桥接电阻的第一端；第三桥接电阻的第二端作为并联型电阻分段单元的输出端。
在本申请实施例中，并联型电阻分段电路的等效阻值需要为第一数字信号的N个码位的最低比特位所对应的第一电阻的阻值。故在对多比特位的数字信号进行分段后，需要调整并联型电阻 分段电路中的第四电阻和第一转换单元中的第一电阻的阻值对应关系。因为并联型电阻分段电路的等效阻值远远小于第四数字信号的最高码位对应的第四电阻的阻值(在二进制码下为阻值最小的第四电阻)，而并联型电阻分段电路的等效阻值又需要等于第一数字信号的N个码位的最低码位所对应的第一电阻的阻值(在二进制下为最大的第一电阻的阻值)。在这种情况下，需要第四电阻具有较大的阻值(尤其是在第四数字信号为二进制码时，第四数字信号的最低比特位所对应的第四电阻的阻值需要非常大)。在设置第三桥接电阻之前，并联型电阻分段电路的等效阻值为并联的第四电阻的等效电阻之和。而当设置了第三桥接电阻后，并联型电阻分段电路的等效阻值为并联的第四电阻的等效电阻之和再加上第三桥接电阻的阻值。故通过设置第三桥接电阻，可以在分段的过程中，无需设置过大阻值的第四电阻，增加了方案的实现可能性，同时，对第四电阻和第一电阻之间的阻值对应关系的设置也更加灵活，可以通过调整第三桥接电阻的阻值进行适应性调整。
在一种可能的实施方式中，第一数字信号的M个码位或第二数字信号的M个码位为二进制码；在M个第四电阻中，对应第一数字信号的M个码位或第二数字信号的M个码位中相邻码位的两个第四电阻之间，对应第一数字信号的M个码位或第二数字信号的M个码位中相邻码位的较低码位的第四电阻的阻值为对应第一数字信号的M个码位或第二数字信号的M个码位中相邻码位的较高码位的第四电阻的阻值的两倍。
在本申请实施例中，使用二进制码作为第四数字信号，其对应的第四电阻的数量相对于温度计码更少，适用于精度要求较低，且要求电阻数量较少的场景。
在一种可能的实施方式中，第一数字信号的M个码位或第二数字信号的M个码位为温度计码；M个第四电阻的阻值相等。
本申请实施例中，温度计码下的第四电阻的阻值都相等，可以减少在不同的阻值的第四电阻输出不同的电压或电流作为模拟信号时，过大的电压或电流输出的模拟信号的偏差过大，对整体的模拟信号产生较大的干扰。
在一种可能的实施方式中，第二转换单元还包括第五电阻；第五电阻的第一端耦合至第一电压端以输入第一电压或耦合至第二电压端以输入第二电压；第五电阻的第二端用于耦合至第一耦合点；第五电阻的阻值等于与第二数字信号的最低码位所对应的电阻的阻值。
本申请实施例通过设置第五电阻，可用于更好地表达数模转换输出的模拟信号，且可以对指示的数值进行进位。
在一种可能的实施方式中，第二转换单元还包括第五开关；第五电阻的第一端与第五开关耦合；控制单元用于控制第五电阻的第一端通过第五开关耦合至第一电压端或控制第五电阻的第一端通过第五开关耦合至第二电压端。
本申请实施例通过控制单元控制第五开关，以调整向第五电阻输入为高电压的第一电阻或者为低电压的第二电压。
在一种可能的实施方式中，第一数字信号的N个码位为二进制码；在N个第一电阻中，对应第一数字信号的N个码位中相邻码位的两个第一电阻之间，对应第一数字信号的N个码位中相邻码位的较低码位的第一电阻的阻值为对应第一数字信号的N个码位中相邻码位的较高码位的第一电阻的阻值的两倍。
在本申请实施例中，使用二进制码作为第一数字信号的N个码位，其对应的第一电阻的数量相对于温度计码更少，适用于精度要求较低，且要求电阻数量较少的场景。
在一种可能的实施方式中，第一数字信号的N个码位为温度计码；N个第一电阻的阻值相等。
在本申请实施例中，温度计码下的第一电阻的阻值都相等，可以减少在不同的阻值的第一电阻输出不同的电压或电流作为模拟信号时，过大的电压或电流输出的模拟信号的偏差过大，对整体的模拟信号产生较大的干扰。
在一种可能的实施方式中，第一转换单元还包括第六电阻；第六电阻的第一端耦合至第一电压端以输入第一电压或耦合至第二电压端以输入第二电压；第六电阻的阻值等于与第一数字信号的最低码位所对应的电阻的阻值。
在本申请实施例中，通过设置第六电阻，可用于更好地表达数模转换输出的模拟信号，且可 以对输出的模拟信号所指示的数值进行进位。
在一种可能的实施方式中，第一转换单元还包括第六开关；第六电阻的第一端与第六开关耦合；控制单元用于控制第六电阻的第一端通过第六开关耦合至第一电压端或控制第六电阻的第一端通过第六开关耦合至第二电压端。
本申请实施例通过控制单元控制第六开关，以调整向第六电阻输入为高电压的第一电阻或者为低电压的第二电压。
第二方面，提供了一种数模转换电路，包括如第一方面所记载的电阻型数模转换器和驱动放大器；驱动放大器耦合至电阻型数模转换器的输出端；电阻型数模转换器用于输入数字信号，并生成模拟信号输出至驱动放大器，驱动放大器用于对模拟信号进行放大。
第三方面，一种电子设备，包括如上第一方面所记载的电阻型数模转换器或包括如上第二方面所记载的数模转换电路；电阻型数模转换器或数模转换电路用于根据输入的数字信号生成模拟信号。
关于第二方面和第三方面的技术效果的描述可参考上述第一方面的相关描述。
附图说明
图1为本申请实施例提供的一种数模转换器的结构示意图；
图2为本申请实施例提供的又一种数模转换器的结构示意图；
图3为本申请实施例提供的一种电子设备的结构示意图；
图4为本申请实施例提供的又一种电子设备的结构示意图；
图5为本申请实施例提供的一种数模转换器的结构示意图；
图6为本申请实施例提供的一种第一开关的结构示意图；
图7为本申请实施例提供的又一种数模转换器的结构示意图；
图8为本申请实施例提供的又一种数模转换器的结构示意图；
图9为本申请实施例提供的又一种数模转换器的结构示意图；
图10为本申请实施例提供的一种电阻分压单元的结构示意图；
图11为本申请实施例提供的有一种数模转换器的结构示意图；
图12为本申请实施例提供的一种并联型电阻分段单元的结构示意图；
图13为本申请实施例提供的又一种并联型电阻分段单元的结构示意图；
图14为本申请实施例提供的又一种并联型电阻分段单元的结构示意图；
图15为本申请实施例提供的一种第二转换单元的结构示意图。
具体实施方式
需要说明的是，本申请实施例涉及的术语“第一”、“第二”等仅用于区分同一类型特征的目的，不能理解为用于指示相对重要性、数量、顺序等。
本申请实施例涉及的术语“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
本申请实施例涉及的术语“耦合”、“连接”应做广义理解，例如，可以指物理上的直接连接，也可以指通过电子器件实现的间接连接，例如通过电阻、电感、电容或其他电子器件实现的连接。
首先对本申请实施例的一些基础概念进行解释说明：
数模转换器(digital-to-analog converter，DAC)作为将数字信号转换为模拟电压信号的器件，在如今的电子器件领域具有不可或缺的作用。常见的数模转换器包括电流型数模转换器(current steering digital-to-analog converter，IDAC)和数模转换器(resistor digital-to-analog converter，RDAC)。随着芯片的高速发展，对数字信号的处理速率和处理精度的要求也越来越高。在对数字信号有着高速率高精度的处理要求的处理场景中，常常采用电流型数模转换器，而数模转换器则难以应用于高速率和高精度的处理场景中。
本申请实施例提供了一种数模转换器，如图1所示，该数模转换器1通过将电阻分段进行分压的方式，最终实现对包含多个比特位的数字信号所对应的模拟信号进行高精度的反馈。但该实施例需要增加多个缓存器11，增加了器件成本和面积。
本申请实施例还提供了一种数模转换器，如图2所示，该数模转换器1包括两个高段串联单元14和一个低段串联单元15。将一个包括多个比特位的数字信号分段为包括高码位段的高段数字信号和包括低码位段的低段数字信号。每个高段串联单元14中包括与高段数字信号的比特位对应的多个高段电阻12。其中一个高段串联单元14的输入端用于输入正电压，另一个高段串联单元14的输入端用于输入负电压。低段串联单元15中包括多个串联的低段电阻13，且串联后的多个低段电阻13的两端分别与两个高段串联单元14的输出端对应耦合。通过低段数字信号的取值对应选择多个低段电阻13中的某一个低段电阻13的第一端或第二端作为耦合点以输出模拟信号。
本申请实施例实现了在通过高段串联单元14输出与高段数字信号对应的模拟信号至低段串联单元15后，再通过低段串联单元15输出结合低段数字信号和高段数字信号的数字信号所对应的模拟信号。但在高段串联单元14和低段串联单元15中需要增加过电流开关以选择不同数量及阻值的高段电阻12和低段电阻13以输出模拟信号。而对于电阻型的数模转换器1而言，在高速率要求的处理场景中，往往需要通过减小高段电阻12和低段电阻13的阻值来减小输出阻抗，从而增加信号处理的速率。而使用更小阻值的电阻又将增加电阻型的数模转换器1中的过电流开关的导通阻抗对数模转换器1的线性度的影响。若通过增大过电流开关的尺寸来降低过电流开关的导通阻抗对数模转换器1的线性度的影响，又会因增加过电流开关的尺寸而产生更大的寄生电容。故在实际的应用中，数模转换器难以实现保证高速率的同时还具有高精度。
本申请实施例提供了一种电子设备，如图3所示，该电子设备2包括数模转换器3。或者，如图4所示，该电子设备2包括数模转换电路，该数模转换电路包括数模转换器3和驱动放大器4。该数模转换器3或该数模转换电路用于根据输入的数字信号生成模拟信号。
示例性地，该电子设备2可以为三角积分调变器(sigma selta modulator，SDM)、逐次求近寄存器(successive approximation register，SAR)、传感器、数字图形处理器、音频处理器等。
如图5所示，数模转换器3包括第一电压端、第二电压端、控制单元30和第一转换单元31。第一电压端用于提供第一电压；第二电压端用于提供第二电压；控制单元30用于输入第一数字信号，该第一数字信号包括N个码位；该第一转换单元31包括与第一数字信号的N个码位一一对应的N个第一开关311、N个第一电阻312；如图6所示，N个第一开关311的第一端用于输入第一电压，N个第一开关311的第二端用于输入第二电压；每个第一开关311的第三端耦合至对应的第一电阻312的第一端；每个第一开关311的受控端用于输入第一数字信号的N个码位中的一个码位，以受第一数字信号的控制将第一开关311的第一端与第一开关311的第三端导通，或受第一数字信号的控制将第一开关311的第二端与第一开关311的第三端导通。如图5所示，N个第一电阻312的第二端被耦合至第一耦合点314；第一耦合点314作为第一转换单元31的输出端，用于输出与第一数字信号的N个码位相对应的第一模拟信号。
在本申请实施例中，通过将所有的第一电阻312分别对应第一数字信号的N个码位中的一个码位，再根据码位的取值选择输入第一电压或第二电压，然后所有的第一电阻312的第二端作为输出端耦合至第一耦合点314。通过第一耦合点314输出与第一数字信号的N个码位对应的第一模拟信号。此时，所有的第一电阻312都可等效为并联的连接方式，不论对应的第一电阻输入的是第一电压还是第二电压，其都要为整个第一转换单元31提供电阻值，故而第一转换单元31的等效阻值R1为所有第一电阻312等效并联后的阻值，其小于第一电阻312的阻值，且为恒定的电阻值。示例性地，当输入的第一数字信号的N个码位为固定的二进制码时，第一转换单元31的输出阻抗Rout＝R2/2，其中R2为第一数字信号的N个码位中的最高码位所对应的第一电阻312的阻值。在第一数字信号的N个码位中的最高码位所对应的第一电阻312的阻值恒定的情况下，第一转换单元31的输出阻抗恒定，且其小于第一电阻312的阻值。在输入的第一数字信号的N个码位固定为温度计码时，第一转换单元31的输出阻抗Rout＝R3/2N，R3为第一数字信号的N个码位为温度计码时的最高码位所对应的第一电阻312的阻值。可以看出，在第一数字信号的N个码位固定为温度计码时，第一转换单元31的输出阻抗相比于第一数字信号的N个码位为二进制码时更小，且在第一电阻312的阻值恒定的情况下，等效阻抗也为恒定值。而在本申请实施例的应用下，可以实现数模转换器3的输出阻抗降低到非常小，且在实现过程中无需大大降低第一电阻312的阻值，采用常规阻值的电阻作为第一电阻312即可得到了稳定且非常小的输出阻抗，在避 免使用较大尺寸的过电流开关的情况下，即可实现高精度且高速率的数模转换。
在一些可能的实施方式中，第一数字信号的N个码位为二进制码。
示例性地，以第一数字信号包括四个码位的二进制码为例，即第一数字信号的N个码位可表示为xxxx，第一电压为高电压，第二电压为低电压。此时，N为二进制码的比特位数，即为4。4个第一开关311的受控端分别对应输入第一数字信号的0比特位、1比特位、2比特位和3比特位，当对应的比特位的取值为高时，导通第一开关311的第一端和第三端，以向第一电阻312输出为高电压的第一电压；当对应的比特位的取值为低时，导通第一开关311的第二端和第三端，以向第一电阻312输出为低电压的第二电压。
在本申请实施例中，通过第一电压和第二电压的不同电压值来对应各比特位为0或1的相应取值，当某一比特位为1时，代表取值为高，则用为高电压的第一电压代表该取值，当某一比特位为0时，代表取值为低，则用为低电压的第二电压代表该取值。同时，不同比特位代表着不同的数字大小，以1000、0100、0010、0001为例，1000的1为3比特位的取值，其代表十进制数8。0100为2比特位的取值，其代表十进制数4。0010为1比特位的取值，其代表十进制数2。0001为0比特位的取值，其代表十进制数1。可以看出，在二进制码的情况下，相邻两个比特位中，高比特位的取值为低比特位的取值的两倍。故对于多个代表不同比特位的第一电阻312。根据其对应的比特位的高低，可以为不同比特位对应的第一电阻312赋予不同的阻值，越高的比特位对应的第一电阻312的阻值越低，当输入同样的电压时(如第一电压)，阻值越低的第一电阻312对第一电压分压越少，从而可以输出更高电压值来对应更高比特位的取值。
示例性地，当第一数字信号的N个码位为二进制码时，相邻两个比特位所对应的两个第一电阻312中，低比特位的第一电阻312的阻值为高比特位的第一电阻312的阻值的两倍。
在一些可能的实施方式中，第一数字信号的N个码位为温度计码。
示例性地，N个第一电阻312的阻值相等。
示例性地，温度计码与二进制码之间的转换关系为：温度计码的位宽＝2n-1，其中n为二进制码的比特位数。如下表1所示，以输入3比特的第一数字信号为例，第一数字信号为二进制码，即第一数字信号可表示为xxx，第一电压为高电压，第二电压为低电压。此时，n为二进制码的比特位数，即为3，可通过3个比特位的第一数字信号表达十进制下的数值0(10)到数值7(10)共8个不同取值。而温度计码的码位对应为7位，即第一数字信号的N个码位为7个码位。此时第一电阻312的数量N的取值对应的是温度计码的码位，即为7。7个第一开关311的受控端分别对应输入第一数字信号的7个码位中的1码位到7码位，当对应的比特位的取值为1时，导通第一开关311的第一端和第三端，以向第一电阻312输入为高电压的第一电压；当对应的比特位的取值为0时，导通第一开关311的第二端和第三端，以向第一电阻312输入为低电压的第二电压。当第一数字信号的7个码位的取值为0(10)时，7个码位对应的值都为0，即7个第一开关311的受控端导通对应的第一开关311的第二端和第三端，以向7个第一电阻312输入为低电压的第二电压。当第一数字信号的7个码位的取值为1(10)时，1码位对应的第一开关311的受控端导通对应的第一开关311的第一端和第三端，以向1码位对应的第一电阻312输入为高电压的第一电压，其余6个码位对应的第一开关311的受控端导通对应的第一开关311的第二端和第三端，以向2码位到7码位的6个第一电阻312输入为低电压的第二电压。同理，当第一数字信号的7个码位的取值为2(10)时，1码位和2码位对应的第一电阻312输入为高电压的第一电压，3码位到7码位对应的第一电阻312输入为低电压的第二电压。当第一数字信号的7个码位的取值为7(10)时，7个第一电阻312都输入为高电压的第一电压。
表1 3比特位的二进制码和温度计码对比表

在本申请实施例中，当采用二进制码控制开关来实现输出对应的模拟信号时，因二进制码的每个比特位所对应的电阻的阻值不同，高比特位所对应的电阻的阻值较小，输出的电压或电流较大，低比特位的电阻的阻值过大，输出的电压或电流较小。在输出完全不同的电压或电流作为模拟信号时，较大的模拟在输出时会产生更大的干扰误差，从而影响整体的精确度，而在采用温度计码的形式下。每个温度计码的码位实质上对应着十进制下的数值1，故每个温度计码的码位所对应的电阻阻值相等，可以减少此类干扰误差的产生。
示例性地，如图5所示的第一转换单元31中，还可以将第一电阻312的个数改为两倍，并将第一开关311修改为两倍数量的单刀单掷开关，双倍的第一电阻312中的一半第一电阻312通过对应的单刀单掷开关输入第一电压，另一半第一电阻312通过对应的单刀单掷开关输入第二电压；每个输入第一电压的第一电阻312分别对应第一数字信号的N个码位中的一个码位；每个输入第二电压的第一电阻312同样分别对应第一数字信号N个码位中的一个码位；第一数字信号的N个码位中一个码位控制对应的输入第一电压的第一电阻312和对应的输入第二电压的第一电阻312共两个第一电阻312中的一个第一电阻312耦合至第一耦合点314。本实施例中的采用单刀单掷开关的实现方式本质上的原理与采用第一开关311的原理一致。
在一些可能的实施方式中，当第一数字信号的比特位较多时，可采用分段的方式来实现在具有较多个比特位的数字信号的情况下，实现高速率和高精度的数模转换。
可选地，一种分段方式为：输入一段包括多个码位的第一数字信号，将该第一数字信号分段为在高位段的N个码位和在低位段的E个码位。同时，还生成一个与第一数字信号的高位段的N个码位对应的第二数字信号，该第二数字信号包括N个码位，且第二数字信号的N个码位的取值比第一数字信号的N个码位的取值大。如图7所示，数模转换器3还包括第二转换单元32和电阻分压单元33。如图8所示，电阻分压单元33包括第一电阻模块331、第二电阻模块332；第一电阻模块331的第一端与第一转换单元31的输出端(即第一耦合点314)耦合，第一电阻模块331的第二端与第二电阻模块332的第一端耦合至第三耦合点333；第二电阻模块332的第二端与第二转换单元32的输出端耦合；第三耦合点333作为数模转换器3的输出端。
如图9所示，第二转换单元32包括N个第二开关321、N个第二电阻322和第二分段单元323；N个第二开关321的第一端用于输入第一电压，N个第二开关321的第二端用于输入第二电压；每个第二开关321的第三端耦合至对应的第二电阻322的第一端；每个第二开关321的受控端用于输入第二数字信号的N个码位中的一个码位，以受第二数字信号的控制将第二开关321的第一端与第二开关321的第三端导通，或受第二数字信号的控制将第二开关321的第二端与第二开关321的第三端导通；第二分段单元323的第一端用于输入第一电压或第二电压；N个第二电阻322的第二端耦合至第二耦合点324；第二耦合点324作为第二转换单元32的输出端，用于输出与第二数字信号的N个码位对应的第二模拟信号。
在本申请实施例中，通过将包括多个码位的第一数字信号分段为位于高码位段的第一数字信号的N个码位和位于低码位段的第一数字信号的E个码位，同时，还生成了一个第二数字信号，该第二数字信号包括N个码位，且第二数字信号的N个码位的取值比第一数字信号的N个码位的取值大(例如第一数字信号的N个码位取值为13(10)，第二数字信号的N个码位取值为14(10))。通过第一转换单元31生成第一数字信号的N个码位对应的第一模拟信号，通过第二转换单元32生成第二数字信号的N个码位对应的第二模拟信号。第一模拟信号通过第一耦合点314输出至第一电阻模块331；第二模拟信号通过第二耦合点324输出至第二电阻模块332。第三耦合点333作为数模转换器3的输出端输出第三模拟信号，第三模拟信号用于表达高码位段的第一数字信号的N个码位和低码位段的第一数字信号的E个码位组合为多个码位的第一数字信号后所对 应的模拟信号(例如，第一数字信号为二进制信号1010 1011，则可以分段为高码位段的1010(对应第一数字信号的N个码位)和低码位段的1011(对应第一数字信号的E个码位)，此时N为4，E为4)。第一数字信号的E个码位作为低码位段的数字信号，用于控制第一电阻模块331和第二电阻模块332的阻值。当第一数字信号的E个码位的取值越低，则第二电阻模块332的阻值越高，第一电阻模块331的阻值越低，此时输出的第三模拟信号更趋近于第一模拟信号。当第一数字信号的E个码位的取值越高，则第二电阻模块332的阻值越低，第一电阻模块331的阻值越高，此时输出的第三模拟信号更趋近于第二模拟信号。
示例性地，第二数字信号的N个码位的取值比第一数字信号的N个码位的取值大1。
在本申请实施例中，第二数字信号的N个码位的取值与第一数字信号的N个码位的取值之间的差值，即可代表第一数字信号的E个码位的取值范围，当第一数字信号的N个码位和第一数字信号的E个码位之间为连续的码位时，则第一数字信号的E个码位取到最大值后，再加1即对应为第一数字信号的N个码位中的最低码位值为1。此时，将第二数字信号的N个码位的取值设置为比第一数字信号的N个码位的取值大1，可以更好地用第三模拟信号来指示第一数字信号的N个码位和第一数字信号的E个码位结合得到的第一数字信号的取值。但当第二数字信号的N个码位的取值比第一数字信号的N个码位的取值大不为1的值时，通过调整第一电阻模块331和第二电阻模块332的阻值与第一电阻312和第二电阻322之间的阻值对应关系，也可以实现通过第三模拟信号来指示第一数字信号的N个码位和第一数字信号的E个码位结合得到的第一数字信号的取值。
在一些可能的实施方式中，第二数字信号的N个码位为二进制码。
示例性地，当第二数字信号的N个码位为二进制码时，相邻两个比特位所对应的两个第二电阻322中，低比特位的第二电阻322的阻值为高比特位的第二电阻322的阻值的两倍。
示例性地，第二分段单元323的阻值等于第二数字信号的N个码位中的最低比特位所对应的第二电阻322的阻值。
在一些可能的实施方式中，第二数字信号的N个码位为温度计码。
示例性地，当第二数字信号的N个码位为温度计码时，N个第二电阻322的阻值相等。
示例性地，当第二数字信号的N个码位为温度计码时，第二分段单元323的阻值等于第二电阻322的阻值。
关于第二数字信号的N个码位为二进制码和温度计码时，第二转换单元32中关于第二分段单元323、第二电阻322的相关技术效果描述可参考上述第一数字信号的N个码位为二进制码和温度计码的相关描述，不再赘述。
在一些可能的实施方式中，如图10所示，电阻分压单元33具体包括输出选择开关334和E个第三电阻330；E个第三电阻330串联后的一端与第一耦合点314耦合，另一端与第二耦合点324耦合；输出选择开关334的选择输入端用于受控于第一数字信号的E个码位耦合至E个第三电阻330中的一个第三电阻330的第一端或第二端，且输出选择开关334的选择输入端与一个第三电阻330的第一端或第二端的耦合点作为第三耦合点333；第三耦合点333与第一耦合点314之间的第三电阻330用于构成第一电阻模块331，第三耦合点333与第二耦合点324之间的第三电阻330用于构成第二电阻模块332。
在本申请实施例中，当第一数字信号的E个码位的取值越高，则输出的第三模拟信号更趋近于第二模拟信号，那么通过调整输出选择开关334的选择输入端的耦合位置，即第三耦合点333的位置，使得第二耦合点324和第三耦合点333之间的第三电阻330的数量减少，从而降低位于第二耦合点324和第三耦合点333之间的第二电阻模块332的阻值，并增加位于第一耦合点314和第三耦合点333之间的第一电阻模块331的阻值。
示例性地，当第一数字信号的E个码位为温度计码时，第三电阻330的个数E的取值为2n-1，此处n为第一数字信号的E个码位为二进制码时的比特位数。且每个第三电阻330的阻值相等。
在本申请实施例中，当第一数字信号的E个码位为温度计码时，以第一数字信号的低码位段为四比特位的二进制码所对应的温度计码为例，则需要15个码位，分别为1码位到15码位。当 第一数字信号的E个码位的取值为0(10)时，第三耦合点333与第一耦合点314重合，即第二电阻模块332包括15个第三电阻330，第一电阻模块331包括0个第三电阻330。此时，第二模拟信号和第一模拟信号并联后从第三耦合点333输出，但第一模拟信号从第一转换单元31的第一耦合点314输出后，无需经过任何第三电阻330的分压，而第二模拟信号从第二转换单元32的第二耦合点324输出后，经过15个第三电阻330，再输出至第三耦合点333，最终输出的第三模拟信号等于第一模拟信号的值。同理，当第三模拟信号的取值为15(10)时，第三耦合点333与第二耦合点324重合，此时，第二模拟信号无需经过第三电阻330的分压即可输出至第三耦合点333，而第一模拟信号需要经过15个第三电阻330后方能输出至第三耦合点333，此时输出的第三模拟信号的值等于第二模拟信号。
示例性地，在第二数字信号的N个码位的取值比第一数字信号的N个码位的取值大1的情况下，在本申请实施例中，在如图7、图8、图9和图10所示的数模转换器3中，第一转换单元31的等效阻值加上第二转换单元32的等效阻值之和，需要等于一个第三电阻330的阻值。
在一些可能的实施方式中，如图11所示，数模转换器3还包括第一桥接电阻34，第一转换单元31的输出端(即第一耦合点314)通过第一桥接电阻34耦合至第一电阻模块331的第一端。
在一些可能的实施方式中，如图11所示，数模转换器3还包括第二桥接电阻35，第二转换单元32的输出端(即第二耦合点324)通过第二桥接电阻35耦合至第二电阻模块的第二端。
在本申请实施例中，当数模转换器3包括第一桥接电阻34时，第一转换单元31的等效阻值加上第二转换单元32的等效阻值以及第一桥接电阻34的阻值得到的阻值之和等于一个第三电阻330的阻值。此时，通过调整第一桥接电阻34的阻值，可以适当增加或减少第一转换单元31和第二转换单元32的等效阻值，进而可以更好地设置第一电阻312和第二电阻322的阻值。
同理，当数模转换器3包括第二桥接电阻35时，第一转换单元31的等效阻值加上第二转换单元32的等效阻值以及第二桥接电阻35的阻值得到的阻值之和等于一个第三电阻330的阻值。此时，通过调整第二桥接电阻35的阻值，可以适当增加或减少第一转换单元31和第二转换单元32的等效阻值，进而可以更好地设置第一电阻312和第二电阻322的阻值。
同样的，当数模转换器3包括第二桥接电阻35时，第一转换单元31的等效阻值加上第二转换单元32的等效阻值以及第一桥接电阻34的阻值、第二桥接电阻35的阻值得到的阻值之和等于一个第三电阻330的阻值。此时，通过调整第一桥接电阻34和第二桥接电阻35的阻值，可以适当增加或减少第一转换单元31和第二转换单元32的等效阻值，进而可以更好地设置第一电阻312和第二电阻322的阻值。
示例性地，第一转换单元31的等效阻值与第一桥接电阻34的阻值之和可以等于第二转换单元32的等效阻值与第二桥接电阻35的阻值之和。可选地，此时，第一转换单元31的等效阻值可以等于第二转换单元32的等效阻值，第一转换单元31的等效阻值也可以不等于第二转换单元32的等效阻值。
在本申请实施例中，对第一转换单元31、第二转换单元32、第一桥接电阻34和第二桥接电阻35各自的等效阻值或阻值并不加以限定，四者之间可以完全相等，部分相等或者完全不等，只需要满足四者的等效阻值或阻值之和等于一个第三电阻330的阻值即可。
在一些可能的实施方式中，如图5所示，第一转换单元31还包括第五电阻315；第五电阻315的阻值等于第一数字信号的最低码位所对应的电阻值。第五电阻315的第一端固定耦合至第一电压端用于输入第一电压，或者第五电阻315的第一端固定耦合至第二电压端用于输入第二电压；第五电阻315的第二端耦合至第一耦合点314。
示例性地，以第一数字信号包括N个码位，N个码位为温度计码为例，则包括N个第一电阻312。每个第一电阻312对应输出一路电压，则第一耦合点312处根据第一数字信号的N个码位的取值不同，以一个第一电阻312对应的码位取值为1时输出的一路电压的值为1/N为例，则第一耦合点312处可以输出值为0/N、1/N、2/N、…、N/N的电压。而当设置一个第五电阻315后。当第五电阻315固定耦合在第二电压端时，第五电阻315固定输出值为0/(N+1)的电压，而第一耦合点312处可以输出值为0/(N+1)、1/(N+1)、2/(N+1)、…、N/(N+1)的电压，可用于表达二进制的数字0到N，且此时，更有利于第一转换单元31进行进位计算。而当第五电阻315固定耦合在第 一电压端时，第五电阻315固定输出值为1/(N+1)的电压，而第一耦合点312处可以输出值为1/(N+1)、2/(N+1)、…、(N+1)/(N+1)的电压，可用于表达二进制的数字1到N+1。此时第五电阻315的阻值为第一数字信号的N个码位中的最低码位对应的第一电阻312的阻值。
在一些可能的实施方式中，如图5所示，第一转换单元31还包括第五开关316。第五电阻315的第一端与第五开关316耦合；所述控制单元30用于控制所述第五电阻315的第一端通过所述第五开关316耦合至所述第一电压端或控制所述第五电阻315的第一端通过所述第五开关316耦合至所述第二电压端。
在本申请实施例中，通过控制单元30控制第五开关315将第五电阻315的第一端耦合至第一电压端或第二电压端，以实现第一转换单元31表示值。
在一些可能的实施方式中，如图9所示，第二转换单元32还包括第六电阻325；第六电阻325的阻值等于第二数字信号的N个码位中的最低码位所对应的电阻值。第六电阻325的第一端固定耦合至第一电压端用于输入第一电压，或者第六电阻325的第一端固定耦合至第二电压端用于输入第二电压；第六电阻325的第二端耦合至第二耦合点324。
在一些可能的实施方式中，如图9所示，第二转换单元32还包括第六开关326。第六电阻325的第一端与第六开关326耦合；所述控制单元30用于控制所述第六电阻325的第一端通过所述第六开关326耦合至所述第一电压端或控制所述第六电阻325的第一端通过所述第六开关326耦合至所述第二电压端。
本申请实施例关于第六电阻315和第六开关326的技术效果的描述可参考上述关于第五电阻315和第五开关325的相关描述，故不再赘述。
在一些可能的实施方式中，对包括多个取值连续增加1的一组数字信号进行数模转换。
示例性地，对包括多个取值连续加1的一组数字信号(例如取值为010 011(2)、010 100(2)、010 101(2)、010 110(2)、….、111 111(2))，对该一组数字信号中的每一个数字信号，分段为高码位段的第一数字信号的N个码位和低码位段的第一数字信号的E个码位。将低码位段的第一数字信号的E个码位输入电阻分压单元，以控制第一电阻模块331和第二电阻模块332的阻值。如图10所示，以一个六比特位的数字信号010 011(2)为例，分段为高码位段的3比特位数字信号010(2)(即第一数字信号的N个码位)和低码位段的3比特位数字信号011(2)(即第一数字信号的E个码位)，将高码位段的3比特位数字信号010(2)输入到第一转换单元31中，再生成一个比高码位段的3比特位数字信号010(2)的取值大1的3比特位数字信号011(2)(即第二数字信号的N个码位)输入到第二转换单元32中，然后将低码位段的3比特位数字信号011(2)输入到电阻分压单元33中，此时第一数字信号的E个码位作为低码位段，为3比特位数字信号，则有23-1＝7个第三电阻330，可用于表达000(2)-111(2)共8种取值，故在对一组包括多个取值连续增加1的数字信号进行数模转换时，例如对取值为010 011(2)-010 111(2)的数字信号进行数模转换时，只需要更改输入电阻分压单元33中的第一数字信号的E个码位的取值即可，即对011(2)的取值逐渐增加1，直至为111(2)。而当第一数字信号的E个码位达到111(2)后，有以下两种方式继续进行后续取值加1的第一数字信号的数模转换：
方式一：将输入第一转换单元31中的第一数字信号的N个码位的取值加1，将输入第二转换单元32中的第二数字信号的N个码位的取值加1，并将电阻分压单元33中的输出选择开关334重新耦合至代表最低值的耦合点，即第三耦合点333靠近第一耦合点314。然后再继续依次将输入电阻分压单元33中的第一数字信号的E个码位的取值加1，以分别对一组数字信号中的连续取值加1的多个数字信号进行数模转换。
方式二：将输入第一转换单元31中的第一数字信号的N个码位的取值加2。此时以第二转换单元32中输入的第二数字信号的N个码位作为将要进行数模转换的数字信号的高码位段，然后以将要进行数模转换的数字信号的低码位段的E个码位作为第一数字信号的E个码位来控制输出选择开关334将第三耦合点333从靠近第二转换单元32的第二耦合点324的位置逐渐靠近第一耦合点314。当第三耦合点333与第一耦合点314重合或者与第一桥接电阻34的输出端耦合时，代表第一数字信号的E个码位已经计数达到最高位，无法再取更大的值。此时，将输入第二转换单元32的第二数字信号的N个码位的取值加2，以输入第一转换单元31的第一数字信号的N个 码位重新作为将要进行数模转换的数字信号的高码位段，将将要进行数模转换的第一数字信号的低码位段的E个码位的取值继续逐次加一，以表达对取值逐渐加1的数字信号的数模转换。此时，第三耦合点333从第一耦合点314逐渐靠近第二耦合点324。以此类推，以第一数字信号的N个码位和第二数字信号的N个码位交替作为进行数模转换的数字信号的高码位段。在使用方式二的处理时，在如图9所示的结构中，第一转换单元31的等效阻值等于第二转换单元32的等效阻值，并等于第三电阻330的阻值的一半时，方式二在实现数模转换时的微分非线性(differential nonlinearity，DNL)较佳。在如图11所示包括第一桥接电阻34和第二桥接电阻35的结构中，第一转换单元31的等效阻值和第一桥接电阻34的阻值之和，等于第二转换单元32的等效阻值和第二桥接电阻34的阻值之和，并等于第三电阻330的阻值的一半时，方式二在实现数模转换时的微分非线性(differential nonlinearity，DNL)较佳。
在本申请实施例中，上述方式一的方法，每次作为低码位段的第一数字信号的E个码位的取值达到最高，需要向高码位段进位时，需要同时改变输入的第一数字信号的N个码位的取值、第二数字信号的N个码位的取值，还需要调整输出选择开关334的选择输入端的耦合点。而采用方式二的方式时，每次从电阻分压单元33的第一数字信号的E个码位进位到高码位段时，只需要改变第一数字信号的N个码位或第二数字信号的N个码位中的一个的取值即可，操作更加方便快捷。
示例性地，如图5、图9所示，以输入四比特位的数据信号为例，第一转换单元31的第五电阻315和/或第二转换单元32的第六电阻325可以固定输入为高电压的第一电压以实现1(10)到16(10)的数值表达，或者固定输入为低电压的第二电压以实现0(0)到15(10)的表达。当需要改变输入第一转换单元31或第二转换单元32的取值时，可以通过控制单元30来控制第五开关316或第六开关326切换输入第五电阻315或第六电阻325的电压为第一电压或第二电压。例如，以输入第一转换单元31的第一数字信号的N个码位作为进行数模转换的数字信号的高码位段。若第一转换单元31和第二转换单元32都可以表达4比特位的数字信号，则当第一数字信号的N个码位的取值为15(10)时，若电阻分压单元33的取值达到最大，需要向高码位段进位，而在上述方式一的实施例中，第一转换单元31可以通过调整输入第五电阻315的电压为第一电压，以实现16(10)的取值表达，但第二转换单元32却无法实现对第二数字信号的N个码位进行17(10)的表达，此时，采用上述方式二的实施例时，将第二转换单元32中输入第六电阻325的电压从第二电压切换为第一电压，则第二转换单元32可以输入取值为16(10)的第二数字信号的N个码位，此时以第二数字信号的N个码位作为进行数模转换的数字信号的高码位段，从而实现继续进行后续数字信号的数模转换。
可选地，另一种分段方式为：将一段包括多个比特位的数字信号分段为高码位段的第一数字信号的N个码位和低码位段的第一数字信号的M个码位。如图5所示，在第一转换单元中设置第一分段单元313。第一分段单元313设置为并联型电阻分段单元。如图12所示，该并联型电阻分段单元5包括M个第四开关51、M个第四电阻52；
M个第四开关51的第一端用于输入第一电压，M个第四开关51的第二端用于输入第二电压；每个第四开关51的第三端耦合至对应的第四电阻52的第一端；每个第四开关51的受控端用于输入第一数字信号的M个码位中的一个码位，以受第一数字信号的M个码位的控制将第四开关51的第一端与第四开关51的第三端导通，或受第一数字信号的M个码位的控制将第四开关51的第二端与第四开关51的第三端导通；M个第四电阻52的第二端耦合至第四耦合点54；第四耦合点54作为并联型电阻分段单元5的输出端耦合至第一耦合点314，用于向第一耦合点314输出与第一数字信号的M个码位对应的第四模拟信号；第一耦合点314作为数模转换器3的输出端，用于输出包括第一模拟信号和第四模拟信号。
在本申请实施例中，例如有一个包括多个比特位的第一数字信号，将该包括多比特位的第一数字信号分段为高码位段的第一数字信号的N个码位和低码位段的第一数字信号的M个码位，将第一数字信号的M个码位输入为并联型电阻分段单元5的第一分段单元313中，从而由第一分段单元313输出与低码位段的第一数字信号的M个码位对应的第四模拟信号，通过如图5所示的第一开关311和第一电阻312配合，从第一耦合点314处输出与高码位段的第一数字信号的N个 码位对应的第一模拟信号，此时，第一耦合点314输出的第一模拟信号和第四模拟信号之和，即用于表达包括多个比特位的第一数字信号所对应的模拟信号。
在一些可能的实施方式中，第一数字信号的M个码位为二进制码。
示例性地，当第一数字信号的M个码位为二进制码时，第四电阻52的数量等于第一数字信号的M个码位的比特位数。相邻两个比特位所对应的两个第四电阻52中，低比特位的第四电阻52的阻值为高比特位的第四电阻52的阻值的两倍。
示例性地，第五电阻315的阻值为第一数字信号的最低位所对应的电阻的阻值。此时，第一数字信号的最低位为第一数字信号的M个比特位中的最低位。故此时第五电阻315的阻值为等于第一数字信号的M个比特位中的最低比特位所对应的第四电阻52的阻值。
在一些可能的实施方式中，第一数字信号的M个码位为温度计码。
示例性地，当第一数字信号的M个码位为温度计码时，第四电阻52的数量M等于2n-1，其中，n为第一数字信号的M个码位为二进制码时所对应的比特位。且M个第四电阻52的阻值相等。
示例性地，当第一数字信号的M个码位为温度计码时，第五电阻315的阻值等于第四电阻52的阻值。此时第五电阻315的阻值依然等于第一数字信号的M个比特位中的最低位所对应的第四电阻52的阻值，但此时的第四电阻52的阻值都相等。
在本申请实施例中，关于图12所示的并联型电阻分段单元5的相关技术原理及技术效果描述可参考上述关于第一转换单元31和第二转换单元32的相关描述，不再赘述。
在一些可能的实施方式中，在第一转换单元31不包括第五电阻315时，第一分段单元313的等效阻值等于第一数字信号的N个码位中的最低码位位所对应的第一电阻312的阻值。(即当第一数字信号的N个码位为二进制信号时，第一分段单元313的等效阻值需要等于阻值最大的第一电阻312的阻值；当第一数字信号的N个码位为温度计码时，第一分段单元313的等效阻值需要等于第一电阻312的阻值)。在第一转换单元31包括第五电阻315时，第一分段单元313与第五电阻315的的等效阻值，等于第一数字信号的N个码位中的最低码位位所对应的第一电阻312的阻值。
在一些可能的实施方式中，如图12所示，并联型电阻分段单元5中还可以包括第三分段单元53。在通过并联型电阻分段单元5对分段后得到的第一数字信号的M个码位进行数模转换时，还可以可对第一数字信号的M个码位进行分段，得到位于第一数字信号的M个码位中的高码位段的第五数字信号和位于第一数字信号的M个码位中的低码位段的第六数字信号。如图13所示，通过第四电阻52对高码位段的第五数字信号进行数模转换，而将图12所示的第三分段单元53设置为图12所示的并联型电阻分段单元5的结构，以并联型电阻分段单元5结构对低码位段的第六数字信号进行数模转换，最终得到关于第一数字信号的M个码位对应的模拟信号。
示例性地，对于一个10比特位的数字信号，可以分段为高码位段的4比特位的第一数字信号的N个码位(N为4)和低码位段的6比特位的第一数字信号的M个码位(M为6)输入如图5所示的数模转换器3中，通过图5所示的数模转换器3的第一电阻312对4比特位的第一数字信号的N个码位(N为4)进行数模转换，将图5中的第一分段单元313设置为如图12所示的并联型电阻分段单元5的结构，将6比特位的第一数字信号的M个码位(M为6)输入该并联型电阻分段单元5结构的第一分段单元313中进行数模转换。进一步地，在对6比特位的第一数字信号的M个码位(M为6)进行处理时，可将6比特位的第一数字信号的M个码位(M为6)再分段为例如高码位段的2比特位的第五数字信号和4码位段的第六数字信号。将2比特位的第五数字信号输入并联型电阻分段单元5的第四电阻52中进行数模转换。同时，如图13所示，将如图12所示的并联型电阻分段单元5中的第三分段单元53设置为图12所示的结构，通过第三分段单元53对低码位段的第六数字信号进行数模转换。在图13中，附图标记51’代表图12所示并联型电阻分段单元5中的第四开关51的结构；附图标记52’代表图12所示并联型电阻分段单元5中的第四电阻52的结构；附图标记53’代表图12所示的并联型电阻分段单元5中的第三分段单元53的结构；附图标记55’代表图14所述的并联型分段单元5中的第三桥接电阻55的结构。在本申请实施例中，理论上，对于分段后的数字信号，在通过并联型电阻分段单元5对分段后的低码位段 的数字信号进行数模转换时，还可以对低码位段的数字信号再进行分段，从而实现更多比特位下的数字信号的高速率和高精度的数模转换。
示例性地，因对输入的第一数字信号进行了分段，故当未设置第五电阻315时，相邻两个码位段所对应的并联型电阻分段单元5之间，低码位段的并联型电阻分段单元5的等效阻值，等于输入高码位段的并联型电阻分段单元5的M个码位中的最低码位，在高码位段的并联型电阻分段单元中，所对应的第四电阻52的阻值。当设置了第五电阻315时，相邻两个码位段所对应的并联型电阻分段单元5之间，低码位段的并联型电阻分段单元5与第五电阻315的等效阻值，等于输入高码位段的并联型电阻分段单元5的M个码位中的最低码位，在高码位段的并联型电阻分段单元中，所对应的第四电阻52的阻值。
在一些可能的实施方式中，如图14所示，并联型电阻分段单元5还包括第三桥接电阻55；第四耦合点54通过第三桥接电阻55耦合至第一耦合点314。
在本申请实施例中，在只有一个并联型电阻分段单元5时，该并联型电阻分段单元5的等效阻值需要为第一数字信号的N个码位中的最码位位所对应的第一电阻312的阻值。故在对多比特位的第一数字信号分段为N个码位和M个码位后，需要调整并联型电阻分段单元5中的第四电阻52和第一转换单元31中的第一电阻312的阻值对应关系。因为并联型电阻分段单元5的等效阻值远远小于第一数字信号的M个码位中的最高码位对应的第四电阻52的阻值(在二进制码下为阻值最小的第四电阻52)，而并联型电阻分段单元5的等效阻值又需要等于第一数字信号的N个码位中的最低码位所对应的第一电阻312的阻值(在二进制下为最大的第一电阻312的阻值)。在这种情况下，需要第四电阻52具有较大的阻值(尤其是在第一数字信号的M个码位为二进制码时，第一数字信号的M个码位中的最低码位所对应的第四电阻52的阻值需要非常大)。在设置第三桥接电阻55之前，考虑第五电阻315的情况下，并联型电阻分段单元5的等效阻值为并联的第四电阻52和并联型调整电阻53的等效电阻之和。而当设置了第三桥接电阻55后，并联型电阻分段单元5的等效阻值为等效并联的第四电阻52和第五电阻315的等效电阻之和再加上第三桥接电阻55的阻值。故通过设置第三桥接电阻55，可以在分段的过程中，无需设置过大阻值的第四电阻52，增加了方案的实现可能性，同时，对第四电阻52和第一电阻312之间的阻值对应关系的设置也更加灵活，可以通过调整第三桥接电阻55的阻值进行适应性调整。当对第一数字信号的M个码位还进行分段时，例如分段为高码位段的第五数字信号和低码位段的第六数字信号，此时，在并联型电阻分段单元5中还设置有第三分段单元53，第三分段单元53的结构与并联型电阻分段单元5的结构类似。此时，低码位段的第六数字信号所对应的第三分段单元53与第五电阻315的等效阻值需要等于高码位段的第五数字信号所对应的并联型电阻分段单元5中对应第五数字信号的最低码位的第四电阻52的阻值，此时需要减少第三分段单元53中的电阻52’的阻值。而若第三分段单元53中也设置有第三桥接电阻55，则低码位段的第六数字信号所对应的第三分段单元53与第五电阻315的等效阻值与设置在第三分段单元53中的第三桥接电阻55的阻值之和，等于高码位段的第五数字信号所对应的并联型电阻分段单元5中对应第五数字信号的最低码位的第四电阻52的阻值，此时第三分段单元53中的电阻52’的阻值无需减小，即可满足方案实现。故在对数字信号进行多个分段时，需要如上图12、图13所描述的方式，设置多个如图12所示的并联型电阻分段单元5的结构。若并联型电阻分段单元5中并未设置第三桥接电阻55，则在将数字信号分为多段的情况下，对每一段的并联型电阻分段单元5中的第四电阻52的要求是非常严格的，且代表越低段的并联型电阻分段单元5，其设置的第四电阻52的阻值也会越高，在不设置第三桥接电阻55的情况下，其实现是较为困难的。而当设置的多个并联型电阻分段单元5中都设置了第三桥接电阻55后，通过调整第三桥接电阻55的值，实现不需要过大阻值的第四电阻52，即可完成对数字信号更多段的信号分段。除此以外，不论分段多少，每一段数字信号所对应的等效阻值都是恒定的，且由于其等效并联的结构，每一段输出的等效阻抗都是固定的。在分为多段数字信号的情况下，数模转换器3的输出端始终为第一耦合点314，第一耦合点314处的输出阻抗即为数模转换器3的输出阻抗，其为固定值且远远小于第一电阻312的阻值，在这种实现方式下，该数模转换器3的输出端可以直接搭接负载，而在传统的电阻型的数模转换器中，因输入的数字信号的取值不同，每次搭接的电阻的阻值也在变化，输出阻抗过大且阻值不恒定，往往难以 在输出端直接搭载负载，而是需要增加后级驱动器件等。在实现如图4所示的电子设备2时，当应用如图12、图13、图14所示的数模转换器3时，该数模转换器3的输出端耦合的驱动放大器4可以为跨阻放大器(trans-impedance amplifier，TIA)。
在一些可能的实施方式，如图15所示，上述实施例如图7、图8、图9和图10、图11所示的数模转换器3中的第二转换单元32中的第二分段单元323也可以设置为如上图12、图13、图14所示的并联型电阻分段单元5，以对第二数字信号分段后分别进行数模转换。图15中，附图标记51’代表图12所示并联型电阻分段单元5中的第四开关51的结构；附图标记52’代表图12所示并联型电阻分段单元5中的第四电阻52的结构；附图标记53’代表图12所示的并联型电阻分段单元5中的第三分段单元53的结构。
在本申请实施例中，关于第二分段单元323设置为并联型电阻分段单元5的描述可参考上述关于第一分段单元313设置为并联型电阻分段单元5的相关描述，故不再赘述。
本申请实施例通过包括上述如图5、图6、图7、图8、图9、图10、图11、图12、图13、图14、图15所示结构的数模转换器3，减少了数模转换器3的等效阻抗的同时还不需要减小电阻的阻值，进而避免了过电流开关的导通阻抗因电阻的阻值的减小而对数模转换的线性度的影响。因输入的第一电压或第二电压为恒定电压，故无需使用大尺寸的开关作为过电流开关，使用小尺寸的开关作为过电流开关，还避免了引入更多寄生电容的问题，同时后驱动的线性度也更加高。除此以外，现有的数模转换器的输出端均无法直接带负载，需要设计宽电压输入范围的同相放大器件，甚至是在输入端设置轨到轨的运算放大器，而在使用如图12、图13、图14所示的数模转换器3时，因该数模转换器3的阻值恒定，其输出端可直接带负载(例如耦合跨阻放大器等)，且运放输入点为虚地点，其更加容易实现高线性度设计。除此以外，如图12、图13、图14所示的数模转换器3的输出阻抗很小，其输出噪声只有4KT*Rout，其中K为玻尔兹曼常数，T为绝对温度，Rout为数模转换器3的输出阻抗。而即便是电流型数模转换器想要达到相同的噪声水平，也需要额外设置1到2个较大的片外电容。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的模块及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和模块的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的器件、电路、设备，可以通过其它的方式实现。例如，以上所描述的设备实施例仅仅是示意性的，例如，所述单元模块的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个模块或组件可以结合或者可以集成到另一个设备，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，设备或模块的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的模块可以是或者也可以不是物理上分开的，作为模块显示的部件可以是或者也可以不是物理模块，即可以位于一个设备，或者也可以分布到多个设备上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能模块可以集成在一个设备中，也可以是各个模块单独物理存在，也可以两个或两个以上模块集成在一个设备中。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (21)

  1. 一种数模转换器，其特征在于，包括第一电压端、第二电压端、控制单元和第一转换单元，所述第一转换单元包括N个第一开关、N个第一电阻；
    所述第一电压端用于输入第一电压；
    所述第二电压端用于输入第二电压；
    所述控制单元用于接收第一数字信号，所述第一数字信号包括N个码位，与所述N个第一开关一一对应，所述控制单元根据所述第一数字信号的N个码位分别控制所述N个第一开关，使得与所述N个第一开关对应的第一电阻的第一端被耦合至所述第一电压端或所述第二电压端；所述N个第一电阻的第二端被耦合至第一耦合点；所述第一耦合点用于输出与所述第一数字信号的N个码位对应的第一模拟信号。
  2. 根据权利要求1所述的一种数模转换器，其特征在于，所述第一数字信号还包括E个码位，所述第一数字信号的E个码位低于所述第一数字信号的N个码位；所述数模转换器还包括电阻分压单元和第二转换单元；所述第二转换单元包括N个第二开关、N个第二电阻；
    所述控制单元还用于根据所述第一数字信号生成第二数字信号；所述第二数字信号包括N个码位，与所述N个第二开关一一对应，所述控制单元根据所述第二数字信号的N个码位分别控制所述N个第二开关，使得与所述N个第二开关对应的第二电阻的第一端被耦合至所述第一电压端或所述第二电压端；所述N个第二电阻的第二端被耦合至第二耦合点；所述第二耦合点用于输出与所述第二数字信号对应的第二模拟信号；所述第二数字信号的取值比所述第一数字信号的取值大；
    所述电阻分压单元的第一输入端耦合至所述第一耦合点，用于输入所述第一模拟信号，所述电阻分压单元的第二输入端耦合至所述第二耦合点，用于输入所述第二模拟信号；所述控制单元用于根据所述第一数字信号的E个码位控制所述电阻分压单元的输出端输出与所述第一数字信号的N个码位和所述第一数字信号的E个码位之和对应的第三模拟信号。
  3. 根据权利要求2所述的数模转换器，其特征在于，所述电阻分压单元具体包括输出选择开关和E个第三电阻；串联后的所述E个第三电阻的一端作为所述电阻分压单元的第一输入端与所述第一耦合点耦合，串联后的所述E个第三电阻的另一端作为所述电阻分压单元的第二输入端与所述第二耦合点耦合；
    所述控制单元用于根据所述第一数字信号的E个码位的取值，将所述输出选择开关的选择输入端耦合至第三耦合点，所述第三耦合点为所述E个第三电阻中的一个第三电阻的第一端或第二端，所述第三耦合点与所述第一耦合点之间的所有所述第三电阻的阻值之和与所述第一数字信号的E个码位的取值对应。
  4. 根据权利要求2或3所述的数模转换器，其特征在于，所述数模转换器还包括第一桥接电阻；所述第一转换单元的输出端通过所述第一桥接电阻耦合至所述电阻分压单元的第一输入端。
  5. 根据权利要求2-4任一项所述的数模转换器，其特征在于，所述数模转换器还包括第二桥接电阻；所述第二转换单元的输出端通过所述第二桥接电阻耦合至所述第二电阻模块的第二端。
  6. 根据权利要求5所述的数模转换器，其特征在于，所述第一数字信号的E个码位为温度计码；所述E个第三电阻的阻值相等。
  7. 根据权利要求2-6任一项所述的数模转换器，其特征在于，所述第二数字信号的N个码位为温度计码；所述N个第二电阻的阻值相等。
  8. 根据权利要求2-6任一项所述的数模转换器，其特征在于，所述第二数字信号的N个码位为二进制码；所述N个所述第二电阻中，对应所述第二数字信号的N个码位中相邻码位的两个所述第二电阻之间，对应所述第二数字信号的N个码位中相邻码位的较低码位的所述第二电阻的阻值为对应所述第二数字信号的N个码位中相邻码位的较高码位的所述第二电阻的阻值的两倍。
  9. 根据权利要求2-8任一项所述的数模转换器，其特征在于，所述第一数字信号还包括M个码位；所述第一数字信号的M个码位高于所述第一数字信号的E个码位且低于所述第一数字信号的N个码位；所述第一转换单元还包括第一分段单元；所述第二转换单元还包括第二分段单元；所述第一分段单元的输出端与所述第一耦合点耦合至所述电阻分压单元的第一输入端；所述第二 转换单元的输出端与所述第二耦合点耦合至所述电阻分压单元的第二输入端；
    所述控制单元还用于根据所述第一数字信号的M个码位控制所述第一分段单元向所述电阻分压单元的第一输入端输出与所述第一数字信号的M个码位所对应的第四模拟信号；生成第二数字信号的M个码位；所述第二数字信号的M个码位低于所述第二数字信号的N个码位；根据所述第二数字信号的M个码位控制所述第二分段单元向所述电阻分压单元的第二输入端输出与所述第二数字信号的M个码位所对应的第五模拟信号。
  10. 根据权利要求9所述的数模转换器，其特征在于，所述第一分段单元和所述第二分段单元为并联型电阻分段单元；所述并联型电阻分段单元包括与所述第一数字信号的M个码位或所述第二数字信号的M个码位一一对应的M个第四开关、M个第四电阻；
    所述控制单元用于根据所述第一数字信号的M个码位或所述第二数字信号的M个码位分别控制所述M个第四开关，使得与所述M个第四开关对应的第四电阻的第一端被耦合至所述第一电压端或所述第二电压端；所述M个第四电阻的第二端耦合至第四耦合点；所述第四耦合点用于输出与所述第一数字信号的M个码位所对应的第四模拟信号或与所述第二数字信号的M个码位所对应的第五模拟信号。
  11. 根据权利要求10所述的数模转换器，其特征在于，所述并联型电阻分段单元还包括第三桥接电阻；所述第四耦合点耦合至所述第三桥接电阻的第一端；所述第三桥接电阻的第二端作为所述并联型电阻分段单元的输出端。
  12. 根据权利要求10或11所述的数模转换器，其特征在于，所述第一数字信号的M个码位或所述第二数字信号的M个码位为二进制码；在所述M个第四电阻中，对应所述第一数字信号的M个码位或所述第二数字信号的M个码位中相邻码位的两个所述第四电阻之间，对应所述第一数字信号的M个码位或所述第二数字信号的M个码位中相邻码位的较低码位的所述第四电阻的阻值为对应所述第一数字信号的M个码位或所述第二数字信号的M个码位中相邻码位的较高码位的所述第四电阻的阻值的两倍。
  13. 根据权利要求10或11所述的数模转换器，其特征在于，所述第一数字信号的M个码位或所述第二数字信号的M个码位为温度计码；所述M个第四电阻的阻值相等。
  14. 根据权利要求2-13任一项所述的数模转换器，其特征在于，所述第二转换单元还包括第五电阻；所述第五电阻的第一端耦合至所述第一电压端以输入所述第一电压或耦合至所述第二电压端以输入所述第二电压；所述第五电阻的第二端用于耦合至所述第一耦合点；所述第五电阻的阻值等于与所述第二数字信号的最低码位所对应的电阻的阻值。
  15. 根据权利要求14所述的数模转换器，其特征在于，所述第二转换单元还包括第五开关；所述第五电阻的第一端与所述第五开关耦合；所述控制单元用于控制所述第五电阻的第一端通过所述第五开关耦合至所述第一电压端或控制所述第五电阻的第一端通过所述第五开关耦合至所述第二电压端。
  16. 根据权利要求1-15任一项所述的数模转换器，其特征在于，所述第一数字信号的N个码位为二进制码；在所述N个第一电阻中，对应所述第一数字信号的N个码位中相邻码位的两个所述第一电阻之间，对应所述第一数字信号的N个码位中相邻码位的较低码位的所述第一电阻的阻值为对应所述第一数字信号的N个码位中相邻码位的较高码位的所述第一电阻的阻值的两倍。
  17. 根据权利要求1-15任一项所述的数模转换器，其特征在于，所述第一数字信号的N个码位为温度计码；所述N个第一电阻的阻值相等。
  18. 根据权利要求1-17任一项所述的数模转换器，其特征在于，所述第一转换单元还包括第六电阻；所述第六电阻的第一端耦合至所述第一电压端以输入所述第一电压或耦合至所述第二电压端以输入所述第二电压；所述第六电阻的阻值等于与所述第一数字信号的最低码位所对应的电阻的阻值。
  19. 根据权利要求18所述的数模转换器，其特征在于，所述第一转换单元还包括第六开关；所述第六电阻的第一端与所述第六开关耦合；所述控制单元用于控制所述第六电阻的第一端通过所述第六开关耦合至所述第一电压端或控制所述第六电阻的第一端通过所述第六开关耦合至所述第二电压端。
  20. 一种数模转换电路，其特征在于，包括如权利要求1-19任一项所述的数模转换器和驱动放大器；所述驱动放大器耦合至所述数模转换器的输出端；所述数模转换器用于输入数字信号，并生成模拟信号输出至所述驱动放大器，所述驱动放大器用于对所述模拟信号进行放大。
  21. 一种电子设备，其特征在于，包括如权利要求1-19任一项所述的数模转换器或包括如权利要求20所述的数模转换电路；所述数模转换器或所述数模转换电路用于根据输入的数字信号生成模拟信号。
PCT/CN2023/102946 2022-08-03 2023-06-27 一种数模转换器、数模转换电路和电子设备 WO2024027377A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210930195.4A CN117560011A (zh) 2022-08-03 2022-08-03 一种数模转换器、数模转换电路和电子设备
CN202210930195.4 2022-08-03

Publications (1)

Publication Number Publication Date
WO2024027377A1 true WO2024027377A1 (zh) 2024-02-08

Family

ID=89821003

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/102946 WO2024027377A1 (zh) 2022-08-03 2023-06-27 一种数模转换器、数模转换电路和电子设备

Country Status (2)

Country Link
CN (1) CN117560011A (zh)
WO (1) WO2024027377A1 (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110557123A (zh) * 2018-06-04 2019-12-10 恩智浦美国有限公司 分段式电阻型数模转换器
CN112583410A (zh) * 2019-09-27 2021-03-30 恩智浦美国有限公司 分段式数模转换器
CN114531157A (zh) * 2022-02-22 2022-05-24 成都利普芯微电子有限公司 数模转换电路、数模转换方法以及显示驱动芯片

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110557123A (zh) * 2018-06-04 2019-12-10 恩智浦美国有限公司 分段式电阻型数模转换器
CN112583410A (zh) * 2019-09-27 2021-03-30 恩智浦美国有限公司 分段式数模转换器
CN114531157A (zh) * 2022-02-22 2022-05-24 成都利普芯微电子有限公司 数模转换电路、数模转换方法以及显示驱动芯片

Also Published As

Publication number Publication date
CN117560011A (zh) 2024-02-13

Similar Documents

Publication Publication Date Title
JP3253901B2 (ja) デジタル／アナログ変換器
US11133818B2 (en) Interpolation digital-to-analog converter (DAC)
US9118346B2 (en) Complementary switches in current switching digital to analog converters
US8963757B2 (en) D/A converter including higher-order resistor string
JPS6225295B2 (zh)
WO2021258949A1 (zh) 一种基于混合编码的电流舵型数模转换器
KR100550102B1 (ko) 전류셀 구동 방식의 디지털-아날로그 변환기
JP2014521253A (ja) 重み付き抵抗素子を有するデジタルアナログ変換器回路
CN106664096B (zh) 混合数/模转换系统
WO2024027377A1 (zh) 一种数模转换器、数模转换电路和电子设备
TWI792438B (zh) 訊號轉換裝置、動態元件匹配電路與動態元件匹配方法
US20210143784A1 (en) Digitally controlled variable gain amplifier
CN115208406A (zh) 混合型数字模拟转换电路、芯片及转换方法
CN108702158B (zh) 数模转换器和数模转换方法
CN109586726B (zh) 分段式数模转换器
JPH06132828A (ja) Ｄ／ａ変換装置
RU74022U1 (ru) Устройство нелинейного цифроаналогового преобразования сигнала
CN220067405U (zh) 数模转换装置和信号处理设备
CN112865793A (zh) 数模转换器的校准转换方法
JP4513970B2 (ja) 多チャンネルデジタルアナログ変換器
Tan et al. The design of 8-bit CMOS digital to analog converter
CN116032288A (zh) 一种多位并行二进制的原/补码dac转换装置
US11005493B2 (en) Digital-to-analog conversion circuit
CN114095021A (zh) 一种电阻型数模转换器的电阻失配的校准方法及电路
JPH05327510A (ja) 電圧加算方式ｄ／ａコンバータ

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23849087

Country of ref document: EP

Kind code of ref document: A1