WO2024011985A1 - 半导体结构的制造方法 - Google Patents

半导体结构的制造方法 Download PDF

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Publication number
WO2024011985A1
WO2024011985A1 PCT/CN2023/089535 CN2023089535W WO2024011985A1 WO 2024011985 A1 WO2024011985 A1 WO 2024011985A1 CN 2023089535 W CN2023089535 W CN 2023089535W WO 2024011985 A1 WO2024011985 A1 WO 2024011985A1
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Prior art keywords
layer
word line
region
active
area
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PCT/CN2023/089535
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English (en)
French (fr)
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WO2024011985A9 (zh
Inventor
窦涛
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US18/547,151 priority Critical patent/US12575389B2/en
Publication of WO2024011985A1 publication Critical patent/WO2024011985A1/zh
Publication of WO2024011985A9 publication Critical patent/WO2024011985A9/zh
Anticipated expiration legal-status Critical
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures

Definitions

  • Embodiments of the present disclosure belong to the field of semiconductors, and specifically relate to a method of manufacturing a semiconductor structure.
  • DRAM Dynamic Random Access Memory
  • 3D stacked DRAM is a structure in which multi-layer transistors are stacked on a substrate. Its integration level is high, which is beneficial to reducing the cost per unit area. However, the performance of 3D stacked DRAM still needs to be improved.
  • Embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, which is at least beneficial to improving the performance of 3D stacked DRAM.
  • the embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, wherein the semiconductor structure includes a transistor region, and the transistor region includes first source and drain regions and words arranged in a first direction. line region, the manufacturing method includes: providing a substrate, forming a plurality of spaced-apart active layers on the substrate, the active layer of the transistor region including a plurality of active structures arranged in a second direction, The second direction is perpendicular to the first direction; multiple dummy word line structures are formed in the first source and drain region and the word line region, and the dummy word line structures cover the active structure in the same layer on the surface; a first isolation layer is formed between adjacent dummy word line structures to form a first isolation layer, the first isolation layer and the dummy word line structure are alternately arranged in a third direction, and the third The direction is perpendicular to the surface of the substrate; remove the dummy word line structure; form an initial dielectric layer on the surface of the
  • a dummy word line structure covering the same active layer is formed, and the spatial position occupied by the dummy word line structure is the spatial position occupied by the initial word line formed subsequently; in A first isolation layer is formed between adjacent dummy word line structures. After that, the dummy word line structure is removed, and an initial word line is formed in the first isolation layer. That is, the first isolation layer can regulate the shape of the initial word line, thereby avoiding the problem of disconnection of the same word line or interconnection of adjacent word lines. In addition, it is beneficial to improve the performance of the semiconductor structure. In addition, the first source and drain regions can increase the process window for forming the dummy word line structure, the first isolation layer, and the initial word line, thereby facilitating process manufacturing.
  • Figure 1 shows a schematic diagram of a semiconductor structure
  • 2-46 show schematic structural diagrams corresponding to each step in a method for manufacturing a semiconductor structure.
  • Embodiments of the present disclosure provide a semiconductor structure.
  • the manufacturing method includes: forming a dummy word line structure covering the same layer of active structures, forming a first isolation layer between adjacent dummy word line structures, and thereafter removing the dummy word line.
  • the structure exposes the active structure and forms a word line covering the same layer of active structure. That is, the spatial position occupied by the dummy word line structure is the spatial position occupied by the word line.
  • the first isolation layer is a mold for forming the word line, which can standardize the shape of the word line, thereby avoiding word gaps between adjacent active structures.
  • the line is disconnected; in addition, the first isolation layer has been formed before forming the word line. Under the isolation effect of the first dielectric layer, interconnection of the upper and lower word lines can be avoided.
  • the first source and drain regions can also be used to increase the process window, thereby facilitating process manufacturing.
  • FIGS. 2 to 46 an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure.
  • the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, in order to facilitate description and clearly illustrate the steps of the semiconductor structure manufacturing method, FIG. 2 to FIG. 46 are partial structural schematic diagrams of the semiconductor structure.
  • FIG. 2 shows a top view of the finally formed semiconductor structure. To be more intuitive, only part of the structure of the semiconductor structure is shown in the top view.
  • the semiconductor structure has a first direction X, a second direction Y, and a third direction Z (refer to FIG. 3 ).
  • the first direction X and the second direction Y are parallel to the surface of the substrate 1 and perpendicular to each other, and the third direction Z is perpendicular to the surface of the substrate 1 .
  • the semiconductor structure includes a transistor region A, a first source-drain region A2 and a word line region A1 arranged sequentially in the first direction X.
  • the semiconductor structure further includes a step region B.
  • the step region B and the word line region A1 are arranged in the second direction Y and are connected to each other.
  • Figure 3 is a cross-sectional view in the d-d1 direction shown in Figure 2;
  • Figure 4 is a cross-sectional view in the e-e1 direction, f-f1 direction and h-h1 direction shown in Figure 2;
  • Figure 5 is a cross-sectional view in the e-e1 direction, f-f1 direction and h-h1 direction shown in Figure 2;
  • the cross-sectional view in the g-g1 direction is shown.
  • a substrate 1 is provided, and a plurality of alternately arranged active layers 20 and sacrificial layers 31 are formed on the substrate 1 .
  • the active layer 20 and the sacrificial layer 31 are located on the substrate 1 in the transistor region A and the step region B.
  • the active layer 20 and the sacrificial layer 31 are formed through an epitaxial growth process.
  • the active layer 20 and the substrate 1 may be made of the same material, for example, both may be silicon layers.
  • the material of the sacrificial layer 31 may be silicon germanium.
  • a protective layer 30 may also be formed on the surface of the active layer 20 .
  • silicon oxide is deposited on the surface of the active layer 20 as the protective layer 30 .
  • the protective layer 30 can protect the active layer 20 during the subsequent etching process. surface.
  • Figure 6 is a cross-sectional view in the d-d1 direction shown in Figure 2
  • Figure 7 is a cross-sectional view in the f-f1 direction and h-h1 direction shown in Figure 2.
  • a second isolation layer 321 is formed in the transistor area A, and the second isolation layer 321 penetrates the active layer 20 and the sacrificial layer 31, and connects the transistor
  • the active layer 20 of area A is divided into a plurality of active structures 2 .
  • the active layer 20 and the sacrificial layer 31 are patterned to remove portions of the active layer 20 and the sacrificial layer 31 to form a plurality of trenches extending in the first direction X; an insulating material is deposited in the trenches as the second isolation layer 321.
  • the material of the second isolation layer 321 may be the same as the material of the protective layer 30 , for example, both are silicon oxide.
  • the edge isolation layer 322 may also be formed in the step region B while the second isolation layer 321 is formed.
  • FIG. 8 is a cross-sectional view in the g-g1 direction shown in FIG. 2; the step area B includes a first area B1 and a second area B2, and the first area B1 and the word line area A1 Opposite, and part of the side of the first region B1 is connected to the word line region A1, and the second region B2 surrounds the side of the first region B1 that is not connected to the word line region A1.
  • the second region B2 can be used to increase the size of the first region B1. Process window for area B1.
  • the shape of the first area B1 is a rectangle, one side of the first area B1 is connected to the word line area A1, and the second area B2 surrounds the other three sides of the first area B1.
  • the edge isolation layer 322 is located in the second area B2 of the step area B.
  • the sacrificial layer 31 and the active layer 20 located in the second area B2 are removed, and thereafter, the edge isolation layer 322 is deposited in the second area B2.
  • Figure 9 is a cross-sectional view in the d-d1 direction shown in Figure 2
  • Figure 10 is a cross-sectional view in the e-e1 direction shown in Figure 2
  • Figure 11 is a cross-sectional view in the h-h1 direction shown in Figure 2
  • a support structure 4 is formed.
  • a dry etching process is used to remove part of the second isolation layer 321 and part of the sacrificial layer 31 to form a plurality of trenches, and silicon nitride is deposited in the trenches to serve as the support structure 4 .
  • a chemical mechanical polishing process is used for planarization.
  • the support structure 4 is located on a side of the word line region A1 away from the step region B, and this support structure 4 penetrates the second isolation layer 321 .
  • This support structure 4 can be used to define the word line region. A1 is far away from the boundary of step area B.
  • the support structure 4 can also be located on the side of the step area B facing the word line area A1, and this support structure 4 can be used to support the active layer 20 of the step area B.
  • the support structure 4 is located at least on a side of the word line region A1 facing away from the first source and drain region A2 , and the support structure 4 here covers the active structure 2 . That is, the support structure 4 here is a mesh structure, and the active structure 2 penetrates the support structure 4 .
  • the support structure 4 can also be located on a side of the anti-leakage area A4 away from the word line area A1, and the support structure 4 here covers the active structure 2.
  • a frame structure 42 surrounding the step area B may also be formed.
  • the frame structure 42 penetrates the edge isolation layer 322 (refer to FIG. 8 ), and is formed on the word line.
  • the frame structure 42 also covers the active layer 20. That is, the frame structure 42 is used to define the edge of the step area B and can isolate the step area B from other areas within the semiconductor structure. It should be noted that the farther the distance between the frame structure 42 located at the edge of the second area B2 and the first area B1 is, the larger the process window of the first area B1 will be.
  • the width of the step region B is greater than the width of the word line region A1. Since the active layer 20 in the first region B1 will be removed subsequently, the larger width of the step region B can increase the process window for removing the active layer 20, thereby facilitating process manufacturing.
  • Figure 12 is a cross-sectional view in the d-d1 direction shown in Figure 2
  • Figure 13 is a cross-sectional view in the e-e1 direction shown in Figure 2
  • Figure 14 is a f- shown in Figure 2
  • the cross-sectional view in the h-h1 direction has not changed.
  • the second isolation layer 321 and the sacrificial layer 31 of the transistor area A are removed to expose the active parts of the transistor area A. Source layer 20.
  • edge isolation layer 322 and the sacrificial layer 31 in the step area B can also be removed, that is, the edge isolation layer 322 in the second area B2 and the sacrificial layer in the first area B1 can be removed. 31 to expose the active layer 20 in the step area B.
  • a wet etching process is used to remove the second isolation layer 321, the sacrificial layer 31 and the edge isolation layer 322.
  • the support structure 4 can support the active layer 20 when the above structure is removed.
  • a first filling layer 331 is formed in the transistor area A.
  • the first filling layer 331 covers the active layer 20 and the support structure 4. That is, the first filling layer 331 occupies the original sacrificial layer of the transistor area A. 31 and the space of the second isolation layer 321.
  • Figure 15 is a cross-sectional view along the g-g1 direction shown in Figure 2. While forming the first filling layer 331, multiple second filling layers 332 can also be formed in the step area B.
  • the second filling layer 332 are alternately arranged with the active layer 20 . Specifically, the second filling layer 332 is alternately arranged with the active layer 20 of the first region B1, and the second filling layer 332 is also filled in the second region B2.
  • a chemical vapor deposition process is used to fill the transistor area A and the step area B with silicon oxide as the first filling layer 331 and the second filling layer 332, and thereafter, a chemical mechanical polishing process is used for planarization.
  • Figure 16 is a cross-sectional view in the d-d1 direction shown in Figure 2
  • Figure 17 is a cross-sectional view in the e-e1 direction shown in Figure 2
  • Figure 18 is a f- shown in Figure 2
  • the first filling layer 331 located in the first source-drain region A2 and the word line region A1 is removed, thereby exposing the active structure 2 of the first source-drain region A2 and the word line region A1.
  • the main reason for removing the first filling layer 331 of the first source and drain region A2 is that the first source and drain region A2 can be used to increase the process window of the word line region A1 to facilitate the subsequent formation of the dummy word line structure 6 , the first isolation layer 5, the initial word line 620 and the initial dielectric layer 610.
  • the process window is enlarged, the production efficiency is improved, and it is conducive to improving the quality of each film layer, thereby improving the performance of the semiconductor structure.
  • the active layer 20 of the transistor region A includes a plurality of active structures 2 arranged in the second direction Y, and the word The active structure 2 in the line region A1 and the first source and drain region A2 is exposed to facilitate subsequent formation of the dummy word line structure 6 .
  • the above steps are only exemplary, and the embodiments of the present disclosure are not limited thereto.
  • only the second isolation layer 321 and the sacrificial layer 31 in the word line region A1 and the first source and drain region A2 may be removed. . Since the sacrificial layer 31 in other areas has not been removed, there is no need to form the first filling layer 331 and the second filling layer 332.
  • Figure 19 is a cross-sectional view in the d-d1 direction shown in Figure 2.
  • Figure 20 is a cross-sectional view in the e-e1 direction shown in Figure 2.
  • Figure 21 is a cross-sectional view in the f-f1 direction shown in Figure 2.
  • Reference 19-21 multiple dummy word line structures 6 are formed in the first source and drain region A2 and the word line region A1, and the dummy word line structures 6 cover the surface of the active structure 2 of the same layer.
  • silicon oxide is deposited on the surface of the active layer 20 through an atomic layer deposition process to serve as the dummy word line structure 6 .
  • the atomic layer deposition process deposits substances in the form of single atomic films layer by layer on the surface of the active structure 2.
  • the chemical reaction of the new layer of atomic film is directly related to the previous layer, so , the film layer has better uniformity and density, which is beneficial to improving the morphology of the dummy word line structure 6 .
  • the spatial position where the dummy word line structure 6 is located is the spatial position where the subsequently formed word line 62 is located. Therefore, the appearance of the subsequently formed word line 62 can also be improved.
  • a chemical vapor deposition process may also be used to form the dummy word line structure 6 .
  • the first source and drain region A2 can be used to increase the process window, that is, to increase the reactive gas entering the word line region A1, thereby allowing the reactive gas to be in the word line region A1.
  • the deposition degree on the surface of the active structure 2 is relatively consistent to improve the morphology of the dummy word line structure 6 .
  • an initial first isolation layer 50 is formed.
  • the initial first isolation layer 50 is located in the first source and drain region A2 and the word line region A1, and covers the end surface of the dummy word line structure 6 facing away from the word line region A1. , and is located between adjacent dummy word line structures 6 . That is to say, a reverse filling process is used to form the initial first isolation layer 50 as an isolation structure between the upper and lower word lines 62 formed subsequently.
  • silicon oxycarbonitride is deposited in the word line region A1 and the first source and drain region A2 through an atomic layer deposition process as the initial first isolation layer 50 .
  • the atomic layer deposition process can improve the density and uniformity of the initial first isolation layer 50, which is beneficial to improving the isolation effect, and can also improve the morphology of the subsequently formed word line 62.
  • the initial first isolation layer 50 may also be formed through a chemical vapor deposition process.
  • the material of the support structure 4 is different from the material of the initial first isolation layer 50 .
  • the main reason is that part of the initial first isolation layer 50 will be removed later to form the first isolation layer 5 .
  • the materials of the two are different.
  • the initial selective etching ratio between the first isolation layer 50 and the support structure 4 is greater than 2.
  • Figure 22 is a cross-sectional view in the d-d1 direction shown in Figure 2.
  • Figure 23 is a cross-sectional view in the e-e1 direction shown in Figure 2.
  • Figure 24 is a cross-sectional view in the f-f1 direction shown in Figure 2.
  • Reference 22 to 24 the initial first isolation layer 50 located at the end surface of the dummy word line structure 6 facing away from the word line region A1 is removed, and the remaining initial first isolation layer 50 serves as the first isolation layer 5 .
  • the first isolation layer 5 and the dummy word line structure 6 are alternately arranged in the third direction Z, and the third direction Z is perpendicular to the surface of the substrate 1 .
  • a dry etching process is used to remove the initial first isolation layer 50 located on the end surface of the dummy word line structure 6 .
  • the dummy word line structure 6 is removed.
  • a wet etching process is used to remove the dummy word line structure 6 , thereby exposing the gap between adjacent first isolation layers 5 .
  • Figure 25 is a cross-sectional view in the d-d1 direction shown in Figure 2.
  • Figure 26 is a cross-sectional view in the e-e1 direction shown in Figure 2.
  • Figure 27 is a cross-sectional view in the f-f1 direction shown in Figure 2.
  • an initial dielectric layer 610 is formed on the surface of the active structure 2 in the first source-drain region A2 and the word line region A1; for example, silicon oxide is grown on the surface of the active structure 2 through an in-situ water vapor generation process. as the initial dielectric layer 610.
  • an initial word line 620 is formed on the surface of the initial dielectric layer 610 , and the initial word line 620 covers the active structure 2 .
  • a film layer such as titanium nitride or tantalum nitride is formed on the surface of the initial dielectric layer 610 through an atomic layer deposition process as the initial word line barrier layer 6210.
  • the initial word line barrier layer 6210 can prevent atomic diffusion between the subsequently formed initial word line filling layer 6220 and the first isolation layer 5, thereby ensuring that the initial word line filling layer 6220 has a low resistance.
  • an initial word line filling layer 6220 is formed between adjacent first isolation layers 5.
  • the initial word line filling layer 6220 also covers the initial word line blocking layer 6210, and the initial word line filling layer 6220 covers The active structure 2 covering the same layer, the initial word line blocking layer 6210 and the initial word line filling layer 6220 constitute the initial word line 620.
  • a low-resistance metal such as titanium, tungsten or molybdenum is deposited between adjacent first isolation layers 5 as the initial word line filling layer 6220. Low-resistance metal is beneficial to reducing the power consumption of the semiconductor structure, and is also beneficial to shortening the delay time, thereby increasing the operating speed of the semiconductor structure.
  • initial dielectric layer 610 and the initial word line 620 are still located on the side of the first source and drain region A2 facing away from the word line region A1.
  • the initial word line 620 and the initial dielectric layer at this position will be removed subsequently. 610.
  • Figure 28 is a cross-sectional view in the d-d1 direction shown in Figure 2.
  • Figure 29 is a cross-sectional view in the e-e1 direction shown in Figure 2.
  • the top surface of the first isolation layer 5 is removed.
  • Initial word line 620 and initial dielectric layer 610 are removed through a chemical mechanical polishing process to expose the top surface of the first isolation layer 5 .
  • the initial word line 620 and the initial dielectric layer 610 located on the side of the first source and drain region A2 facing away from the word line region A1 are etched, thereby exposing the end surface of the active structure 2 .
  • Figure 30 is a cross-sectional view along the f-f1 direction shown in Figure 2.
  • a plurality of first trenches 501 are formed in the first source and drain region A2.
  • the first trenches 501 extend along the third direction Z.
  • the direction Z is perpendicular to the surface of the substrate 1; the first trench 501 penetrates the first isolation layer 5, the initial word line 620 and the initial dielectric layer 610.
  • a dry etching process is used to remove the first isolation layer 5 , the initial word line 620 and the initial dielectric layer 610 located between adjacent active structures 2 along the third direction Z, thereby exposing the active structure 2 in the third direction Z.
  • Two directions Y Arranged side walls.
  • FIG. 31 is a cross-sectional view along the f-f1 direction shown in FIG. 2.
  • a first insulating layer 511 filling the first trench 501 is formed.
  • silicon nitride is deposited in the first trench 501 as the first insulating layer 511 .
  • a chemical mechanical polishing process is used for planarization.
  • Figure 32 is a cross-sectional view in the e-e1 direction shown in Figure 2.
  • Figure 33 is a cross-sectional view in the f-f1 direction shown in Figure 2.
  • the remaining initial characters in the first source and drain region A2 are removed.
  • line 620 and the initial dielectric layer 610; the remaining initial dielectric layer 610 constitutes the dielectric layer 61; the remaining initial word line 620 constitutes the word line 62.
  • the first insulating layer 511 is formed, the first insulating layer 511, the active structure 2 and the first isolation layer 5 form a small hole 502.
  • the initial word line 620 and the initial word line 620 located in the small hole 502 are etched.
  • the dielectric layer 610 thereby shortening the lengths of the initial word line 620 and the initial dielectric layer 610 in the first direction X. Since the area of the small hole 502 is small, it is easy to control the length of the initial word line 620 and the initial dielectric layer 610 that are removed, thereby avoiding the removal of the initial word line 620 and the initial dielectric layer 610 in the word line area A1. In this way, It is beneficial to improve the performance of semiconductor structures.
  • the initial word line 620 and the initial dielectric layer 610 located in the first source and drain region A2 can be removed, thereby forming the word line 62 and the dielectric layer 61.
  • the dielectric layer 61 is located on the surface of the active structure 2 in the word line area A1.
  • the word line 62 covers the active structure 2 of the same layer in the word line area A1 and covers the dielectric layer 61.
  • an etching step may also be used to remove the initial dielectric layer 610 and the initial word line 620 of the first source and drain region A2.
  • Figure 34 is a cross-sectional view along the e-e1 direction shown in Figure 2.
  • Figure 35 is a cross-sectional view along the f-f1 direction shown in Figure 2.
  • a second insulation is formed in the first source and drain region A2.
  • Layer 512, the second insulating layer 512 is located on the upper and lower sides of the active structure 2 and between the adjacent first insulating layer 511, and also covers the first isolation layer 5; the first insulating layer 511 and the second insulating layer 512 constitute an insulating layer. 51.
  • the second insulating layer 512 is located in the small hole 502 surrounded by the first insulating layer 511, the active structure 2 and the first isolation layer 5, and covers the sidewall of the first source and drain region A2 away from the word line region A1.
  • silicon carbonitride oxycarbon is deposited in the first source and drain region A2 as the second insulating layer 512 .
  • the material of the second insulation layer 512 may be the same as the material of the first isolation layer 5 .
  • the insulating layer 51 can be formed in the first source and drain region A2 based on the two steps shown in FIG. 31 and FIG. 34-35 .
  • the insulating layer 51 is located between adjacent active structures 2 and covers the first isolation layer 5 .
  • Using two steps to form the insulating layer 51 is beneficial to increasing the density of the insulating layer 51 , thereby improving the isolation effect of the insulating layer 51 .
  • a deposition step may be used to form the insulating layer 51 after removing the initial dielectric layer 610 and the initial word line 620 of the first source and drain region A2.
  • the manufacturing method also includes: heavily doping the active structure 2 of the first source and drain region A2.
  • the type of doping ions in the first source and drain region A2 may be opposite to the type of doping ions in the word line region A1.
  • Figure 36 is a cross-sectional view in the d-d1 direction shown in Figure 2
  • Figure 37 is a cross-sectional view in the g-g1 direction shown in Figure 2.
  • the step area B is patterned to form A plurality of steps 21 include the active layer 20 and the second filling layer 332 located below it.
  • a dry etching process is used to remove part of the active layer 20 and part of the second filling layer 332 , and the remaining active layer 20 and the second filling layer 332 serve as steps 21 .
  • Figure 38 is a cross-sectional view in the d-d1 direction shown in Figure 2
  • Figure 39 is a cross-sectional view in the g-g1 direction shown in Figure 2.
  • the first covering layer 34 covering the steps is formed.
  • the material of the first covering layer 34 may be the same as the material of the second filling layer 332 , for example, silicon oxide is deposited on the steps as the first covering layer 34 .
  • Figure 40 is a cross-sectional view in the d-d1 direction shown in Figure 2
  • Figure 41 is a cross-sectional view in the g-g1 direction shown in Figure 2.
  • the second A second trench 632 is formed in area B2
  • the second trenches 632 are located on opposite sides of the active layer 20 arranged in the first direction
  • the purpose of forming the second trench 632 is to expose the active layer 20 so that the etchant can enter under the first covering layer 34 through the second trench 632 to react with the active layer 20 , and finally Active layer 20 is removed.
  • the position of the stepped filling groove 631 is the position of the original active layer 20 .
  • the dielectric layer 61 connected to the active layer 20 can be removed through the step filling trench 631, that is, the junction between the word line area A1 and the step area B can be removed.
  • the dielectric layer 61 allows the subsequently filled word line connection layer 63 to directly contact the word line 62, thereby increasing the contact area and reducing the contact resistance.
  • the active layer 20 located in the step area B and word line area A1 can be removed based on the steps shown in FIGS. 36 to 41 .
  • the advantage of using two steps to remove the active layer 20 is that the length of the active layer 20 in the second direction Y can be shortened, thereby reducing residues generated by etching the active layer 20 .
  • the length of the second filling layer 332 in the second direction Y is also shortened accordingly, which can avoid the second filling layer 332 from tilting or collapsing due to loss of support after the active layer 20 is removed. question.
  • Figure 42 is a cross-sectional view in the d-d1 direction shown in Figure 2
  • Figure 43 is a cross-sectional view in the g-g1 direction shown in Figure 2.
  • the material of the initial word line connection layer 633 may be a low-resistance metal, such as copper, tungsten, molybdenum or aluminum, etc.
  • Figure 44 is a cross-sectional view along the g-g1 direction shown in Figure 2.
  • the initial word line connection layer 633 located in the second trench 632 is removed, and the initial word line located in the step filling trench 631 (refer to Figure 41)
  • the line connection layer 633 serves as the word line connection layer 63, and the word line connection layer 63 is also located between adjacent second filling layers 332.
  • the word line connection layer 63 is electrically connected to the word line 62 .
  • the word line connection layer 63 in the step area B replaces the active layer 20 as the contact structure of the word line 62.
  • the resistance of the word line connection layer 63 is smaller than that of the active layer 20, which can improve the operation of the semiconductor structure. speed, reducing the power consumption of semiconductor structures.
  • a larger opening can be formed at the junction of the step area B and the word line area A1, thereby increasing the contact area between the word line 62 and the word line connection layer 63, thereby reducing the contact resistance. .
  • a third isolation layer 35 is formed within the second trench 632 (refer to FIG. 41 ).
  • the third isolation layer 35 may be made of the same material as the first covering layer 34 and the second filling layer 332 , such as silicon dioxide.
  • the connecting pillars 64 correspond to the steps one by one and penetrate the first covering layer 34 located on the word line 62 so that the connecting pillars 64 are connected to the word line 62 .
  • a second covering layer 36 is formed on the first covering layer 34, and a contact hole is formed penetrating the first covering layer 34 and the second covering layer 36.
  • the contact hole corresponds to the word line connection layer 63 of the step area B in a one-to-one manner. , and expose the top surface of the word line connection layer 63 .
  • Conductive material is deposited within the contact holes to serve as connection posts 64 .
  • the transistor region A also includes an anti-leakage region A4 and a second source-drain region A5; the anti-leakage region A4 is located between the second source-drain region A5 and the word line region A1; in the first direction
  • the width of the leakage region A4 is greater than the width of the second source-drain region A5; the active structure 2 of the anti-leakage region A4 is lightly doped; the active structure 2 of the second source-drain region A5 is heavily doped.
  • the purpose of lightly doping the anti-leakage region A4 is to slowly change the potential, reduce the transition probability, and then reduce the gate-induced drain leakage current GIDL (gate-induced drain leakage), thereby improving the reliability of the semiconductor structure.
  • the doping type of the second source and drain region A5 may be the same as the doping type of the anti-leakage region A4 and the first source and drain region A2.
  • the transistor region A may also include a bit line region A3, and the bit line region A3 is connected to the first source and drain region A2.
  • a bit line 7 extending along the third direction Z may be formed in the bit line area A3, and the bit line 7 is connected to the multi-layer active structure 2.
  • the semiconductor structure may further include a capacitor region C.
  • the capacitor region C is connected to the second source-drain region A5 .
  • a plurality of stacked capacitors may be formed in the capacitor region C.
  • the dummy word line structure 6 is first formed on the surface of the active structure 2; after the first isolation layer 5 is formed, the dummy word line structure 6 is removed, thereby obtaining a mold for forming the word line 62; The first isolation layer 5 is filled with conductive material to form word lines 62, thereby avoiding the problem of disconnection of word lines 62 on the same layer or interconnection of upper and lower word lines 62.
  • the active layer 20 of the step region B is removed, the opening at the interface between the word line region A1 and the step region B is larger, thereby avoiding the problem of the word line 62 being disconnected at the interface between the two regions.
  • removing the first filling layer 331 of the first source and drain region A2 can increase the process window of the word line region A1.
  • the first insulating layer 511 is formed, and the first insulating layer 511, the active structure 2 and the first isolation layer 5 can surround the small hole 502, which can facilitate controlling the length of the removed initial word line 620. In this way, it is beneficial to improve the performance of the semiconductor structure.
  • the method of forming the first isolation layer 5 includes an atomic layer deposition process, and the method of forming the dummy word line structure includes an atomic layer deposition process, it can be ensured that the finally formed word line 62 has a better morphology.

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Abstract

公开了一种半导体结构的制造方法。半导体结构包括晶体管区，晶体管区包括第一源漏区和字线区。该制造方法包括在基底上形成有源层，晶体管区的有源层包括多个有源结构。在第一源漏区和字线区形成包覆同一层有源结构的伪字线结构。形成与伪字线结构在第三方向上交替设置的第一隔离层。去除伪字线结构。在第一源漏区和字线区的有源结构的表面形成初始介质层。在初始介质层表面形成初始字线。去除位于第一源漏区的初始字线和初始介质层。

Description

半导体结构的制造方法
交叉引用
本申请引用于2022年7月12日递交的名称为“半导体结构的制造方法”的第202210822648.1号中国专利申请，其通过引用被全部并入本申请。
技术领域
本公开实施例属于半导体领域，具体涉及一种半导体结构的制造方法。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是一种半导体存储器，主要的作用原理是利用电容内存储电荷的多寡来代表其存储的一个二进制比特是1还是0。
3D堆叠式DRAM是一种在基底上堆叠多层晶体管的结构，其集成度较高，有利于降低单位面积的成本。然而3D堆叠式DRAM的性能还有待提升。
发明内容
本公开实施例提供一种半导体结构的制造方法，至少有利于提高3D堆叠式DRAM的性能。
根据本公开一些实施例，本公开实施例一方面提供一种半导体结构的制造方法，其中，所述半导体结构包括晶体管区，所述晶体管区包括在第一方向排列的第一源漏区和字线区，所述制造方法包括：提供基底，在所述基底上形成多层间隔设置的有源层，所述晶体管区的所述有源层包括多个在第二方向排列的有源结构，所述第二方向垂直于所述第一方向；在所述第一源漏区和所述字线区形成多个伪字线结构，所述伪字线结构包覆同一层所述有源结构的表面；在相邻所述伪字线结构之间形成第一隔离层，形成第一隔离层，所述第一隔离层与所述伪字线结构在第三方向上交替设置，所述第三方向垂直于所述基底表面；去除所述伪字线结构；在所述第一源漏区和所述字线区的所述有源结构的表面形成初始介质层；在所述初始介质层表面形成初始字线，且所述初始字线包覆所述有源结构；去除位于所述第一源漏区的所述初始字线和初始介质层；剩余的所述初始介质层构成介质层；剩余的所述初始字线构成字线，所述字线包覆所述字线区的同一层的所述有源结构；在所述第一源漏区形成绝缘层，所述绝缘层位于相邻所述有源结构之间，并覆盖所述第一隔离层。
本公开实施例提供的技术方案至少具有以下优点：形成包覆同一层有源层的伪字线结构，伪字线结构所占据的空间位置为后续形成的初始字线所占据的空间位置；在相邻伪字线结构之间形成第一隔离层，此后，去除伪字线结构，并在第一隔离层内形成初始字线。即第一隔离层能够规范初始字线的形状，从而避免同一字线发生断开，或相邻字线发生互连的问题。此外，从而有利于提高半导体结构的性能。此外，第一源漏区能够增大形成伪字线结构、第一隔离层、初始字线的工艺窗口，从而便于工艺制造。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了一种半导体结构的示意图；
图2-图46示出了一种半导体结构的制造方法中各步骤对应的结构示意图。
具体实施方式
背景技术可知，3D堆叠式DRAM的性能还有待提升。参考图1，经分析发现，主要原因在于：在基底100上形成多层有源结构200后，通常直接沉积导电材料以形成包覆同一层的多个有源结构200的字线600；然而，导电材料在不同位置的沉积程度不同，从而可能发生错误的互连或断开。比如，在第一位置L1，即有源结构200的边缘处，字线600的厚度较小，并且可能发生断开现象。在第二位置L2，由于上下空间连通，因此，上下层相邻的字线600容易发生互连。因此，半导体结构的性能有待提升。
本公开实施例提供一种半导体结构，制造方法包括：形成包覆同一层有源结构的伪字线结构，并在相邻伪字线结构之间形成第一隔离层，此后，去除伪字线结构以露出有源结构，形成包覆同一层有源结构的字线。即，伪字线结构所占据的空间位置即为字线所占据的空间位置，第一隔离层为形成字线的模子，能够规范字线的形状，从而避免相邻有源结构之间的字线发生断开；此外，第一隔离层在形成字线之前已经形成，在第一介质层隔离作用下，可以避免上下层的字线发生互联。此外，第一源漏区还可用于增大工艺窗口，进而便于工艺制造。
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开实施例而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开实施例所要求保护的技术方案。
如图2-图46所示，本公开一实施例提供一种半导体结构的制造方法，以下将结合附图对本申请一实施例提供的半导体结构的制造方法进行详细说明。需要说明的是，为了便于描述以及清晰地示意出半导体结构制作方法的步骤，图2至图46均为半导体结构的局部结构示意图。
参考图2，图2示出了最终形成的半导体结构的俯视图，为更加直观，俯视图中仅示出了半导体结构中的部分结构。首先，需要说明的是，半导体结构内具有第一方向X、第二方向Y和第三方向Z(参考图3)。第一方向X和第二方向Y与基底1表面平行且二者相互垂直，第三方向Z垂直于基底1表面。
半导体结构包括晶体管区A，晶体管区A在第一方向X依次排列的第一源漏区A2和字线区A1。在一些实施例中，半导体结构还包括台阶区B，台阶区B与字线区A1在第二方向Y排列，且二者相接。
图3为图2所示的d-d1方向上的剖面图；图4为图2所示的e-e1方向、f-f1方向和h-h1方向上的剖面图；图5为图2所示的g-g1方向上的剖面图。参考图3-图5，提供基底1，在基底1上形成多层交替设置的有源层20和牺牲层31。在一些实施例中，有源层20和牺牲层31位于晶体管区A和台阶区B的基底1上。
示例地，通过外延生长工艺形成有源层20和牺牲层31。此外，有源层20与基底1的材料可以相同，比如二者可以均为硅层。牺牲层31的材料可以为硅锗。
此外，还可以在有源层20的表面形成保护层30。示例地，在有源层20的表面沉积氧化硅以作为保护层30。保护层30能够在后续刻蚀过程中保护有源层20的 表面。
参考图6-图7，图6为图2所示的d-d1方向上的剖面图，图7为图2所示的f-f1方向和h-h1方向上的剖面图，在本步骤中，半导体结构在e-e1方向上的剖面未发生变化，可参考图4；在晶体管区A形成第二隔离层321，第二隔离层321穿透有源层20和牺牲层31，并将晶体管区A的有源层20分割为多个有源结构2。
示例地，对有源层20和牺牲层31进行图形化处理，以去除部分有源层20和牺牲层31，以形成在第一方向X延伸的多个沟槽；在沟槽中沉积绝缘材料以作为第二隔离层321。第二隔离层321的材料可以与保护层30的材料相同，比如二者均为氧化硅。
在一些实施例中，还可以在形成第二隔离层321的同时，在台阶区B形成边缘隔离层322。具体地，参考图2和图8，图8为图2所示的g-g1方向上的剖面图；台阶区B包括第一区B1和第二区B2，第一区B1与字线区A1正对，且第一区B1的部分侧面与字线区A1相接，第二区B2环绕第一区B1未与字线区A1相接的侧面，第二区B2可以用于增大第一区B1的工艺窗口。示例地，第一区B1的形状为矩形，第一区B1的一个侧面与字线区A1相接，第二区B2环绕第一区B1的其他三个侧面。边缘隔离层322位于台阶区B的第二区B2。
示例地，去除位于第二区B2的牺牲层31和有源层20，此后，在第二区B2沉积边缘隔离层322。
图9为图2所示的d-d1方向上的剖面图，图10为图2所示的e-e1方向的剖面图，图11为图2所示的h-h1方向上的剖面图；参考图9-图11，形成支撑结构4。示例地，采用干法刻蚀工艺去除部分第二隔离层321和部分牺牲层31，以形成多个沟槽，在沟槽中沉积氮化硅以作为支撑结构4。沉积氮化硅之后，采用化学机械研磨工艺进行平坦化处理。
参考图9，在一些实施例中，支撑结构4位于字线区A1远离台阶区B的一侧，且此支撑结构4穿透第二隔离层321，此支撑结构4可以用于定义字线区A1远离台阶区B的边界。支撑结构4还可以位于台阶区B朝向字线区A1的一侧，此支撑结构4可以用于支撑台阶区B的有源层20。
参考图10-图11，在另一些实施例中，支撑结构4至少位于字线区A1背向第一源漏区A2的一侧，且此处的支撑结构4包覆有源结构2。即此处的支撑结构4为网状结构，有源结构2穿透支撑结构4。此外，支撑结构4还可以位于防漏电区A4远离字线区A1的一侧，且此处的支撑结构4包覆有源结构2。
在另一些实施例中，参考图2，在形成支撑结构4的同时，还可以形成环绕台阶区B的框架结构42，框架结构42穿透边缘隔离层322(参考图8)，且在字线区A1与第一区B1的相接处，框架结构42还包覆有源层20。即，框架结构42用于定义台阶区B的边缘，且能够将台阶区B与半导体结构内的其他区域相隔离。需要说明的是，位于第二区B2边缘的框架结构42与第一区B1的距离越远，则第一区B1的工艺窗口越大。
在一些实施例中，参考图2，在第一方向X上，台阶区B的宽度大于字线区A1的宽度。由于后续将去除第一区B1的有源层20，因此，台阶区B较大的宽度能够增大去除有源层20的工艺窗口，从而便于工艺制造。
参考图12-图14，图12为图2所示的d-d1方向上的剖面图，图13为图2所示的e-e1方向的剖面图，图14为图2所示的f-f1方向的剖面图，在本步骤中，h-h1方向上的剖面图未发生变化，可参考图11；去除晶体管区A的第二隔离层321和牺牲层31，以露出晶体管区A的有源层20。此外，还可以去除台阶区B的边缘隔离层322和牺牲层31，即去除第二区B2的边缘隔离层322和第一区B1的牺牲层 31，以露出台阶区B的有源层20。
示例地，采用湿法刻蚀工艺去除第二隔离层321、牺牲层31和边缘隔离层322。支撑结构4能够在去除上述结构时，对有源层20起到支撑作用。
继续参考图12-图14，在晶体管区A形成第一填充层331，第一填充层331覆盖有源层20和支撑结构4，即第一填充层331占据了晶体管区A原有的牺牲层31和第二隔离层321的空间。
参考图15，图15为图2所示的g-g1方向的剖面图，在形成第一填充层331的同时，还可以在台阶区B形成多层第二填充层332，第二填充层332与有源层20交替设置。具体地，第二填充层332与第一区B1的有源层20交替设置，且第二填充层332还填充于第二区B2。
示例地，采用化学气相沉积工艺在晶体管区A和台阶区B填充氧化硅以作为第一填充层331和第二填充层332，此后，采用化学机械研磨工艺进行平坦化处理。
参考图16-图18，图16为图2所示的d-d1方向上的剖面图，图17为图2所示的e-e1方向的剖面图，图18为图2所示的f-f1方向的剖面图，去除位于第一源漏区A2和字线区A1的第一填充层331，从而露出第一源漏区A2和字线区A1的有源结构2。
需要说明的是，去除第一源漏区A2的第一填充层331的主要原因在于：第一源漏区A2可以用于增大字线区A1的工艺窗口，以便于后续形成伪字线结构6、第一隔离层5、初始字线620和初始介质层610。工艺窗口增大，生产效率提高，且有利于提高各膜层的质量，从而提高半导体结构的性能。
至此，基于图3-图18，可以在基底1上形成多层间隔设置的有源层20，晶体管区A的有源层20包括多个在第二方向Y排列的有源结构2，且字线区A1和第一源漏区A2内的有源结构2被露出，以便于后续形成伪字线结构6。上述步骤仅为示例性说明，本公开实施例不限于此，比如，在形成支撑结构4后，可以只去除字线区A1和第一源漏区A2内的第二隔离层321和牺牲层31。由于其他区域内的牺牲层31并未并去除，因而无需再形成第一填充层331和第二填充层332。
图19为图2所示的d-d1方向上的剖面图，图20为图2所示的e-e1方向的剖面图，图21为图2所示的f-f1方向的剖面图，参考图19-图21，在第一源漏区A2和字线区A1形成多个伪字线结构6，伪字线结构6包覆同一层有源结构2的表面。
示例地，通过原子层沉积工艺在有源层20的表面沉积氧化硅以作为伪字线结构6。原子层沉积工艺将物质以单原子膜形式一层一层的镀在有源结构2表面，在原子层沉积过程中，新一层原子膜的化学反应是直接与之前一层相关联的，因此，膜层的均一性、致密度更好，从而有利于改善伪字线结构6的形貌。伪字线结构6所在的空间位置即为后续形成的字线62所在的空间位置，因此，还可以改善后续形成的字线62的形貌。在另一些实施例中，也可以采用化学气相沉积工艺形成伪字线结构6。
需要说明的是，由于第一源漏区A2的第一填充层331被去除，第一源漏区A2可用于增大工艺窗口，即增加进入字线区A1的反应气体，进而使得反应气体在有源结构2表面的沉积程度相对一致，以改善伪字线结构6的形貌。
继续参考图19-图21，形成初始第一隔离层50，初始第一隔离层50位于第一源漏区A2和字线区A1，且覆盖伪字线结构6背向字线区A1的端面，并位于相邻伪字线结构6之间。也就是说，采用反向填充工艺形成初始第一隔离层50以作为后续形成的上下层字线62之间的隔离结构。
示例地，通过原子层沉积工艺在字线区A1和第一源漏区A2沉积碳氮氧硅以作为初始第一隔离层50。原子层沉积工艺能够提高初始第一隔离层50的致密度和均一性，从而有利于提高隔离效果，还能够改善后续形成的字线62的形貌。在另一些实施例中，还可以通过化学气相沉积工艺形成初始第一隔离层50。
在一些实施例中，支撑结构4的材料与初始第一隔离层50的材料不同。主要原因在于，后续将去除部分初始第一隔离层50，以形成第一隔离层5。在去除部分初始第一隔离层50时，为避免将支撑结构4也去除，因此，二者的材料不同。示例地，初始第一隔离层50与支撑结构4的选择刻蚀比大于2。
图22为图2所示的d-d1方向上的剖面图，图23为图2所示的e-e1方向的剖面图，图24为图2所示的f-f1方向的剖面图，参考图22-图24，去除位于伪字线结构6背向字线区A1的端面的初始第一隔离层50，剩余的初始第一隔离层50作为第一隔离层5。第一隔离层5与伪字线结构6在第三方向Z上交替设置，第三方向Z垂直于基底1表面。
示例地，采用干法刻蚀工艺以去除位于伪字线结构6端面的初始第一隔离层50。
继续参考图22-图24，去除伪字线结构6。示例地，采用湿法刻蚀工艺去除伪字线结构6，从而露出相邻第一隔离层5之间的间隙。
图25为图2所示的d-d1方向上的剖面图，图26为图2所示的e-e1方向的剖面图，图27为图2所示的f-f1方向的剖面图，参考图25-图27，在第一源漏区A2和字线区A1的有源结构2的表面形成初始介质层610；示例地，通过原位水汽生成工艺在有源结构2的表面生长氧化硅以作为初始介质层610。
继续参考图25-图27，在初始介质层610表面形成初始字线620，且初始字线620包覆有源结构2。具体地，通过原子层沉积工艺在初始介质层610的表面形成氮化钛或氮化钽等膜层以作为初始字线阻挡层6210。初始字线阻挡层6210能够避免后续形成的初始字线填充层6220与第一隔离层5发生原子扩散，从而保证初始字线填充层6220具有较低电阻。
继续参考图25-图27，形成位于相邻第一隔离层5之间的初始字线填充层6220，初始字线填充层6220还覆盖初始字线阻挡层6210，且初始字线填充层6220包覆同一层的有源结构2，初始字线阻挡层6210和初始字线填充层6220构成初始字线620。示例地，在相邻第一隔离层5之间沉积钛、钨或钼等低电阻金属作为初始字线填充层6220。低电阻的金属有利于降低半导体结构的功耗，还有利于缩短延迟时间，从而提高半导体结构的运行速率。
参考图26，需要说明的是，初始介质层610和初始字线620还位于第一源漏区A2背向字线区A1的一侧，后续将去除此位置的初始字线620和初始介质层610。
图28为图2所示的d-d1方向上的剖面图，图29为图2所示的e-e1方向的剖面图，参考图28-图29，去除位于第一隔离层5顶面的初始字线620和初始介质层610。具体地，可通过化学机械研磨工艺去除顶面的初始字线620和初始介质层610，以露出第一隔离层5的顶面。
参考图29，刻蚀位于第一源漏区A2背向字线区A1的一侧的初始字线620和初始介质层610，从而露出有源结构2的端面。
图30为图2所示的f-f1方向的剖面图，参考图30，在第一源漏区A2形成多个第一沟槽501，第一沟槽501沿第三方向Z延伸，第三方向Z垂直于基底1表面；第一沟槽501穿透第一隔离层5、初始字线620和初始介质层610。
示例地，采用干法刻蚀工艺沿着第三方向Z去除位于相邻有源结构2之间的第一隔离层5、初始字线620和初始介质层610，从而露出有源结构2在第二方向Y 排列的侧壁。
图31为图2所示的f-f1方向的剖面图，参考图31，形成填充第一沟槽501的第一绝缘层511。示例地，在第一沟槽501中沉积氮化硅以作为第一绝缘层511。此后，采用化学机械研磨工艺进行平坦化处理。
图32为图2所示的e-e1方向的剖面图，图33为图2所示的f-f1方向的剖面图，参考图32-图33，去除第一源漏区A2剩余的初始字线620和初始介质层610；剩余的初始介质层610构成介质层61；剩余的初始字线620构成字线62。换言之，在形成第一绝缘层511后，第一绝缘层511与有源结构2以及第一隔离层5围成小孔502，此后，刻蚀位于该小孔502内的初始字线620和初始介质层610，从而缩短初始字线620和初始介质层610在第一方向X上的长度。由于小孔502的面积较小，因此，能够便于控制去除的初始字线620和初始介质层610的长度，从而避免将字线区A1的初始字线620和初始介质层610也去除，如此，有利于提高半导体结构的性能。
至此，基于图28-图30和图32-图33所示的工艺步骤，可以去除位于第一源漏区A2的初始字线620和初始介质层610，从而形成字线62和介质层61。介质层61位于字线区A1的有源结构2的表面，字线62包覆字线区A1的同一层的有源结构2，且覆盖介质层61。上述步骤为示例性说明，而不限于此。在另一些实施例中，还可以采用一道刻蚀步骤以去除第一源漏区A2的初始介质层610和初始字线620。
图34为图2所示的e-e1方向的剖面图，图35为图2所示的f-f1方向的剖面图，参考图34-图35，在第一源漏区A2形成第二绝缘层512，第二绝缘层512位于有源结构2的上下两侧以及相邻第一绝缘层511之间，还覆盖第一隔离层5；第一绝缘层511和第二绝缘层512构成绝缘层51。换言之，第二绝缘层512位于第一绝缘层511、有源结构2以及第一隔离层5围成的小孔502内，并覆盖第一源漏区A2远离字线区A1的侧壁。
示例地，在第一源漏区A2沉积碳氮氧硅以作为第二绝缘层512。第二绝缘层512的材料可以与第一隔离层5的材料相同。
至此，基于图31和图34-图35所示的两个步骤可以在第一源漏区A2形成绝缘层51，绝缘层51位于相邻有源结构2之间，并覆盖第一隔离层5。采用两次步骤形成绝缘层51，有利于提升绝缘层51的致密度，从而提高绝缘层51的隔离效果。在另一些实施例中，在去除第一源漏区A2的初始介质层610和初始字线620后，可以采用一道沉积步骤形成绝缘层51。
需要说明的是，在形成第二绝缘层512前，制造方法还包括：对第一源漏区A2的有源结构2进行重掺杂处理。示例地，第一源漏区A2的掺杂离子的类型可以与字线区A1的掺杂离子的类型相反。
图36为图2所示的d-d1方向的剖面图，图37为图2所示的g-g1方向的剖面图，参考图36-图37，对台阶区B进行图形化处理，以形成多个台阶21，台阶21包括有源层20以及位于其下方的第二填充层332。
示例地，采用干法刻蚀工艺去除部分有源层20和部分第二填充层332，剩余的有源层20和第二填充层332作为台阶21。
图38为图2所示的d-d1方向的剖面图，图39为图2所示的g-g1方向的剖面图，参考图38-图39，形成覆盖台阶的第一覆盖层34。示例地，第一覆盖层34的材料可以与第二填充层332的材料相同，比如，在台阶上沉积氧化硅以作为第一覆盖层34。
图40为图2所示的d-d1方向的剖面图，图41为图2所示的g-g1方向的剖面图，参考图40-图41，形成第一覆盖层34后，在第二区B2内形成第二沟槽632， 第二沟槽632位于有源层20在第一方向X上排列的相对两侧，并露出有源层20的侧壁；去除第一区B1的有源层20，以形成台阶填充槽631。
也就是说，形成第二沟槽632的目的在于：露出有源层20，使得刻蚀剂可以通过第二沟槽632进入第一覆盖层34的下方，从而与有源层20进行反应，最终去除有源层20。台阶填充槽631的位置为原有源层20的位置。
在另一些实施例中，去除有源层20形成台阶填充槽631后，可以通过台阶填充槽631去除与有源层20连接的介质层61，即，去除字线区A1与台阶区B交界处的介质层61，从而使得后续填充的字线连接层63可以与字线62直接接触，增加接触面积，降低接触电阻。
至此，基于图36-图41所示的步骤可以去除位于台阶区B字线区A1的有源层20。需要说明的是，采用两道步骤以去除有源层20的好处在于：可以缩短有源层20在第二方向Y上的长度，进而能够减少刻蚀有源层20所产生的残留物。此外，在形成台阶21时，第二填充层332在第二方向Y上的长度也相应缩短，能够避免后续在去除有源层20后，第二填充层332因失去支撑而发生倾斜或坍塌的问题。
图42为图2所示的d-d1方向的剖面图，图43为图2所示的g-g1方向的剖面图，参考图42-图43，在台阶填充槽631以及第二沟槽632内形成初始字线连接层633。初始字线连接层633的材料可以为低电阻金属，比如铜、钨、钼或铝等等。
参考图44，图44为图2所示的g-g1方向的剖面图，去除位于第二沟槽632内的初始字线连接层633，位于台阶填充槽631(参考图41)内的初始字线连接层633作为字线连接层63，字线连接层63还位于相邻第二填充层332之间。字线连接层63与字线62电连接。
需要说明的是，台阶区B的字线连接层63替代有源层20作为字线62的接触结构，字线连接层63的电阻比有源层20的电阻更小，能够提高半导体结构的运行速率，降低半导体结构的功耗。此外，有源层20被去除，则在台阶区B与字线区A1的交界处可以形成一个较大的开口，从而可以增加字线62和字线连接层63的接触面积，进而降低接触电阻。
继续参考图44，在第二沟槽632(参考图41)内形成第三隔离层35。第三隔离层35的材料可以与第一覆盖层34和第二填充层332的材料相同，比如均为二氧化硅。
参考图45-图46，形成多个连接柱64，连接柱64与台阶一一对应，并穿透位于字线62上的第一覆盖层34，以使连接柱64与字线62连接。
示例地，在第一覆盖层34上形成第二覆盖层36，形成穿透第一覆盖层34和第二覆盖层36的接触孔，接触孔与台阶区B的字线连接层63一一对应，且露出字线连接层63的顶面。在接触孔内沉积导电材料以作为连接柱64。
此外，参考图2，晶体管区A还包括防漏电区A4和第二源漏区A5；防漏电区A4位于第二源漏区A5与字线区A1之间；在第一方向X上，防漏电区A4的宽度大于第二源漏区A5的宽度；对防漏电区A4的有源结构2进行轻掺杂处理；对第二源漏区A5的有源结构2进行重掺杂处理。
具体地，对防漏电区A4进行轻掺杂处理的目的在于：使电势缓变，降低跃迁几率，进而降低栅诱导漏极泄漏电流GIDL(gate-induced drain leakage)，从而提升半导体结构的可靠性。第二源漏区A5的掺杂类型可以与防漏电区A4和第一源漏区A2的掺杂类型相同。
此外，参考图2，晶体管区A还可以包括位线区A3，位线区A3与第一源漏区A2相连。位线区A3内可形成沿第三方向Z延伸的位线7，位线7与多层的有源结构2相连。
此外，参考图2，半导体结构还可以包括电容区C，电容区C与第二源漏区A5相连，电容区C内可形成多个堆叠设置的电容。
综上所述，本公开实施例先在有源结构2的表面形成伪字线结构6；形成第一隔离层5后，再去除伪字线结构6，从而获得形成字线62的模子；在第一隔离层5内填充导电材料可形成字线62，从而可以避免同一层字线62发生断开，或上下层字线62发生互连的问题。此外，由于去除了台阶区B的有源层20，字线区A1和台阶区B交界处的开口较大，从而可以避免字线62在两个区域的交界处发生断开的问题。此外，去除第一源漏区A2的第一填充层331，可增大字线区A1的工艺窗口。此外，形成第一绝缘层511，第一绝缘层511、有源结构2和第一隔离层5可围成小孔502，能够便于控制去除的初始字线620的长度。如此，有利于提高半导体结构的性能。此外，由于形成第一隔离层5的方法包括原子层沉积工艺，形成伪字线结构的方法包括原子层沉积工艺，从而可以保证最终形成的字线62具有较好的形貌。

Claims (15)

  1. 一种半导体结构的制造方法，其特征在于，所述半导体结构包括晶体管区(A)，所述晶体管区(A)包括在第一方向(X)排列的第一源漏区(A2)和字线区(A1)，所述制造方法包括：
    提供基底(1)，在所述基底(1)上形成多层间隔设置的有源层(20)，所述晶体管区(A)的所述有源层(20)包括多个在第二方向(Y)排列的有源结构(2)，所述第二方向(Y)垂直于所述第一方向(X)；
    在所述第一源漏区(A2)和所述字线区(A1)形成多个伪字线结构(6)，所述伪字线结构(6)包覆同一层所述有源结构(2)的表面；
    形成第一隔离层(5)，所述第一隔离层(5)与所述伪字线结构(6)在第三方向(Z)上交替设置，所述第三方向(Z)垂直于所述基底(1)表面；
    去除所述伪字线结构(6)；
    在所述第一源漏区(A2)和所述字线区(A1)的所述有源结构(2)的表面形成初始介质层(610)；
    在所述初始介质层(610)表面形成初始字线(620)，且所述初始字线(620)包覆所述有源结构(2)；
    去除位于所述第一源漏区(A2)的所述初始字线(620)和初始介质层(610)；剩余的所述初始介质层(610)构成介质层(61)；剩余的所述初始字线(620)构成字线(62)，所述字线(62)包覆所述字线区(A1)的同一层的所述有源结构(2)；
    在所述第一源漏区(A2)形成绝缘层(51)，所述绝缘层(51)位于相邻所述有源结构(2)之间，并覆盖所述第一隔离层(5)。
  2. 根据权利要求1所述的半导体结构的制造方法，其特征在于，去除位于所述第一源漏区(A2)的所述初始字线(620)和初始介质层(610)，以及在所述第一源漏区(A2)形成所述绝缘层(51)，包括：
    在所述第一源漏区(A2)形成多个第一沟槽(501)，所述第一沟槽(501)沿第三方向(Z)延伸，所述第三方向(Z)垂直于所述基底(1)表面；所述第一沟槽(501)穿透所述第一隔离层(5)、所述初始字线(620)和所述初始介质层(610)；
    形成填充所述第一沟槽(501)的第一绝缘层(511)；
    形成所述第一绝缘层(511)后，去除所述第一源漏区(A2)剩余的所述初始字线(620)和所述初始介质层(610)；
    在所述第一源漏区(A2)形成第二绝缘层(512)，所述第二绝缘层(512)位于所述有源结构(2)的上下两侧以及相邻所述第一绝缘层(511)之间，还覆盖所述第一隔离层(5)；所述第一绝缘层(511)和所述第二绝缘层(512)构成所述绝缘层(51)。
  3. 根据权利要求2所述的半导体结构的制造方法，其特征在于，所述初始介质层(610)和所述初始字线(620)还位于所述第一源漏区(A2)背向所述字线区(A1)的一侧；
    在形成所述第一沟槽(501)前，还包括：刻蚀位于所述第一源漏区(A2)背向所述字线区(A1)的一侧的所述初始字线(620)和所述初始介质层(610)。
  4. 根据权利要求2或3所述的半导体结构的制造方法，其特征在于，在形成所述第二绝缘层(512)前，还包括：
    对所述第一源漏区(A2)的所述有源结构(2)进行重掺杂处理。
  5. 根据权利要求1-4中任一项所述的半导体结构的制造方法，其特征在于，所述形成多层间隔设置的有源层(20)的步骤包括：
    在所述基底(1)上形成多层交替设置的牺牲层(31)和所述有源层(20)；
    在所述晶体管区(A)形成第二隔离层(321)，所述第二隔离层(321)穿透所述有源层(20)和所述牺牲层(31)，并将所述晶体管区(A)的所述有源层(20)分割为多个所述有 源结构(2)；
    形成所述第二隔离层(321)后，还包括：
    形成支撑结构(4)，所述支撑结构(4)至少位于所述字线区(A1)背向所述第一源漏区(A2)的一侧，且所述支撑结构(4)包覆所述有源结构(2)；
    形成所述支撑结构(4)后，去除所述第二隔离层(321)和所述牺牲层(31)；
    在所述晶体管区(A)形成第一填充层(331)，所述第一填充层(331)覆盖所述有源层(20)和所述支撑结构(4)；
    在形成所述伪字线结构(6)前，还包括：去除位于所述第一源漏区(A2)和所述字线区(A1)的所述第一填充层(331)。
  6. 根据权利要求5所述的半导体结构的制造方法，其特征在于，所述支撑结构(4)的材料与所述第一隔离层(5)的材料不同。
  7. 根据权利要求1-6中任一项所述的半导体结构的制造方法，其特征在于，所述半导体结构还包括：台阶区(B)，所述台阶区(B)与所述字线区(A1)在所述第二方向(Y)排列，且二者相接；
    所述制造方法还包括：在所述台阶区(B)形成多层第二填充层(332)，所述第二填充层(332)与所述有源层(20)交替设置；
    去除位于所述台阶区(B)的所述有源层(20)；
    在相邻所述第二填充层(332)之间形成字线连接层(63)，所述字线连接层(63)与所述字线(62)电连接。
  8. 根据权利要求7所述的半导体结构的制造方法，其特征在于，
    所述台阶区(B)包括第一区(B1)和第二区(B2)，所述第一区(B1)与所述字线区(A1)正对，且所述第一区(B1)的部分侧面与所述字线区(A1)相接，所述第二区(B2)环绕所述第一区(B1)未与所述字线区(A1)相接的侧面；
    在形成所述第二填充层(332)前，还包括：
    在所述台阶区(B)的所述基底(1)上形成多层牺牲层(31)，所述牺牲层(31)与所述有源层(20)交替设置；
    去除位于所述第二区(B2)的所述牺牲层(31)和所述有源层(20)；
    在所述第二区(B2)形成边缘隔离层(322)；
    形成环绕所述台阶区(B)的框架结构，所述框架结构(42)穿透所述边缘隔离层(322)，且在所述台阶区(B)与所述第一区(B1)的相接处，所述框架结构(42)还包覆所述有源层(20)；
    去除所述边缘隔离层(322)和位于所述第一区(B1)的所述牺牲层(31)；
    形成所述第二填充层(332)，所述第二填充层(332)与所述第一区(B1)的所述有源层(20)交替设置。
  9. 根据权利要求7或8所述的半导体结构的制造方法，其特征在于，
    在所述第一方向(X)上，所述台阶区(B)的宽度大于所述字线区(A1)的宽度。
  10. 根据权利要求8所述的半导体结构的制造方法，其特征在于，形成所述字线连接层(63)的步骤包括：
    对所述台阶区(B)进行图形化处理，以形成多个台阶(21)，所述台阶(21)包括有源层(20)以及位于其下方的第二填充层(332)；在所述字线区(A1)指向所述台阶区(B)的方向上，所述台阶(21)的高度依次降低；
    形成覆盖所述台阶(21)的第一覆盖层(34)；
    形成所述第一覆盖层(34)后，在所述第二区(B2)内形成第二沟槽(632)，所述第二沟槽(632)位于所述有源层(20)在所述第一方向(X)上排列的相对两侧，并露出有源层(20)的侧壁；
    去除所述第一区(B1)的所述有源层(20)，以形成台阶填充槽(631)；
    在所述台阶填充槽(631)以及所述第二沟槽(632)内形成初始字线连接层(633)；
    去除位于所述第二沟槽(632)内的初始字线连接层(633)，位于所述台阶填充槽(631)内的所述初始字线连接层(633)作为所述字线连接层(63)；
    在所述第二沟槽(632)内形成第三隔离层(35)。
  11. 根据权利要求10所述的半导体结构的制造方法，其特征在于，还包括：
    形成多个连接柱(64)，所述连接柱(64)与所述台阶(21)一一对应，并穿透位于所述字线(62)上的所述第一覆盖层(34)，以使所述连接柱(64)与所述字线(62)连接。
  12. 根据权利要求1-11中任一项所述的半导体结构的制造方法，其特征在于，形成所述第一隔离层(5)包括：
    形成初始第一隔离层(50)，所述初始第一隔离层(50)位于所述第一源漏区(A2)和所述字线区(A1)，且覆盖所述伪字线结构(6)背向所述字线区(A1)的端面，并位于相邻所述伪字线结构(6)之间；
    去除位于所述端面的所述初始第一隔离层(50)，剩余的所述初始第一隔离层(50)作为所述第一隔离层(5)。
  13. 根据权利要求1-12中任一项所述的半导体结构的制造方法，其特征在于，所述晶体管区(A)还包括防漏电区(A4)和第二源漏区(A5)；所述防漏电区(A4)位于所述第二源漏区(A5)与所述字线区(A1)之间；在所述第一方向(X)上，所述防漏电区(A4)的宽度大于所述第二源漏区(A5)的宽度；
    对所述防漏电区(A4)的所述有源结构(2)进行轻掺杂处理；
    对所述第二源漏区(A5)的所述有源结构(2)进行重掺杂处理。
  14. 根据权利要求1-13中任一项所述的半导体结构的制造方法，其特征在于，形成所述伪字线结构(6)的方法包括：原子层沉积工艺。
  15. 根据权利要求1-14中任一项所述的半导体结构的制造方法，其特征在于，形成所述第一隔离层(5)的方法包括：原子层沉积工艺。
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