WO2024007440A1 - 高密度3d堆叠扇出型封装结构及其制造方法 - Google Patents

高密度3d堆叠扇出型封装结构及其制造方法 Download PDF

Info

Publication number
WO2024007440A1
WO2024007440A1 PCT/CN2022/116559 CN2022116559W WO2024007440A1 WO 2024007440 A1 WO2024007440 A1 WO 2024007440A1 CN 2022116559 W CN2022116559 W CN 2022116559W WO 2024007440 A1 WO2024007440 A1 WO 2024007440A1
Authority
WO
WIPO (PCT)
Prior art keywords
density
layer
packaging structure
out packaging
active device
Prior art date
Application number
PCT/CN2022/116559
Other languages
English (en)
French (fr)
Inventor
肖智轶
马书英
刘苏
Original Assignee
华天科技（昆山）电子有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华天科技（昆山）电子有限公司 filed Critical 华天科技（昆山）电子有限公司
Publication of WO2024007440A1 publication Critical patent/WO2024007440A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

Definitions

  • This application belongs to the field of chip packaging technology, and specifically relates to a high-density 3D stacked fan-out packaging structure and its manufacturing method.
  • this application provides a high-density 3D stacked fan-out packaging structure and a manufacturing method thereof.
  • the first aspect of this application provides a high-density 3D stacked fan-out packaging structure.
  • the high-density 3D stacked fan-out packaging structure includes at least one active device, at least one high-density interconnection module and several passive chips.
  • the high-density interconnection module between the active device and the passive chip realizes 3D in the vertical direction. interconnected.
  • the high-density 3D stacked fan-out packaging structure also includes a metal wiring layer.
  • the metal wiring layer is formed at the conductive via holes of the high-density interconnect module, and the passive chip is attached to the metal on the wiring layer.
  • the passive chip is electrically interconnected with the conductive via via a metal wiring layer.
  • the high-density 3D stacked fan-out packaging structure further includes a protective layer, and the metal wiring layer and the passive chip are plastically sealed in the protective layer.
  • the high-density 3D stacked fan-out packaging structure further includes a first passivation layer, a first rewiring layer, a second passivation layer, a second rewiring layer and a metal pad.
  • a first passivation layer is formed on the upper surface of the active device and the high-density interconnection module.
  • a first rewiring layer is formed on the first passivation layer.
  • a second passivation layer is formed on the first rewiring layer.
  • the second passivation layer A second rewiring layer is formed on the second rewiring layer, a metal pad is provided on the second rewiring layer, and tin balls are soldered on the metal pad.
  • the first passivation layer is provided with a first opening for electrical interconnection of the active device and a second opening for external interconnection with the high-density interconnection module, and the first rewiring A layer is formed at least at the first opening and the second opening, and a second passivation layer and a plurality of openings are formed on the first redistribution layer.
  • the active device and the high-density interconnection module are arranged in the same plane and at intervals, and an active device is arranged between adjacent high-density interconnection modules.
  • the soldering of the active device The pad is located on the side of the active device away from the passive chip.
  • all high-density interconnection modules come from the same base body, and the base body is made of silicon base, glass or insulating high-temperature resistant resin.
  • the high-density 3D stacked fan-out packaging structure further includes a carrier board.
  • the carrier board includes a plurality of main grooves arranged at intervals, wherein auxiliary grooves are arranged between adjacent main grooves, active devices are arranged in the main grooves, and high-density interconnection modules are arranged in the auxiliary grooves.
  • the main groove and the auxiliary groove respectively penetrate the carrier plate.
  • the second aspect of this application provides a method for manufacturing a high-density 3D stacked fan-out packaging structure, which method includes:
  • a carrier board is thinned to a specified thickness, and at least one main groove and at least one auxiliary groove are formed on the carrier board.
  • the active device is buried in the main groove, and the side of the active device away from the soldering pad is set toward the bottom of the main groove.
  • the high-density interconnection module is buried in the auxiliary groove.
  • the active device and the high-density interconnection module are respectively It is fixed in the main groove and auxiliary groove through the adhesive film layer.
  • a first passivation layer is formed on the side facing the opening of the main groove.
  • the first passivation layer is provided with a first opening for electrical interconnection with the active device and a second opening for external interconnection of the high-density interconnection module.
  • the first opening exposes the soldering pads of the active devices
  • the second opening exposes the copper pillars of the high-density interconnection module.
  • Line build-up is performed on the side of the first passivation layer facing away from the carrier board to form a first intermediate structure.
  • a temporary bonding film layer is formed on the side of the first intermediate structure facing away from the carrier plate.
  • the upper carrier plate is disposed on the side of the temporary bonding film layer facing away from the carrier plate, and the upper carrier plate and the first intermediate structure are connected through the temporary bonding film layer.
  • the carrier board On the side of the first intermediate structure facing away from the upper carrier board, grind the carrier board flat to expose the conductive via holes of the high-density interconnection module, and then make a metal wiring layer where there are conductive via holes on the flat structure. , and then attach the passive chip to the metal wiring layer through flip chip, so that the active device and the passive chip realize 3D interconnection in the vertical direction through the high-density interconnection module to form a second intermediate structure.
  • the second intermediate structure is plastic-sealed to form a protective layer.
  • the temporary bonding film layer and the temporary bonding structure of the upper board are released, the metal pad is exposed, and solder balls are soldered on it for external signal conduction.
  • the carrier plate is made of silicon wafer, glass, metal alloy or composite material.
  • the steps of forming a high-density interconnection module include: forming an array of mask openings on an entire substrate, etching high-density through holes, and then etching high-density through holes on the sides of the through holes.
  • the wall forms an oxide barrier layer, the through holes are plugged by electroplating, the base body is turned over, the copper pillars on the back are exposed by grinding, and cut into pieces to obtain at least one independent high-density interconnection module.
  • performing circuit layering on the side of the first passivation layer facing away from the carrier board includes: forming a first rewiring layer on the side of the first passivation layer facing away from the carrier board, Then, a second passivation layer and several openings are formed on the first redistribution layer; a second passivation layer is formed on the side of the second passivation layer away from the first redistribution layer in the same or different manner as the first redistribution layer. a redistribution layer, and a metal pad is formed on a side of the second redistribution layer facing away from the second redistribution layer; the second passivation layer includes at least one opening.
  • the temporary bonding film layer is a photolytic or thermally detachable bonding film or temporary bonding glue
  • the upper plate is made of glass, silicon-based, metal alloy or composite material.
  • the method before thinning a carrier board to a specified thickness, the method further includes temporarily bonding the carrier board and the support sheet together through a first adhesive layer. After performing circuit layering on the side of the first passivation layer facing away from the carrier board, and before forming a temporary bonding film layer on the side of the first intermediate structure facing away from the carrier board, the method further includes releasing the first bonding layer. Temporary bonding structure of layers and support sheets. Wherein, at least one main groove and at least one auxiliary groove penetrate the carrier plate.
  • the main groove of the main chip and the smaller auxiliary groove next to it can be etched out in one step, which can avoid two etchings, especially to avoid bringing the bonding structure into the etching machine to etch through holes. risks arising from the time. At the same time, reducing one etching can greatly shorten the production cycle of the product.
  • High-density interconnection modules come from the same substrate (such as silicon base, etc.). Good interconnection modules can be selected and buried in auxiliary grooves, avoiding the risks involved in etching through holes and ensuring the through-hole portion of the reorganized wafer. yield rate.
  • the high-density interconnection module is made separately and can form a dense and stable barrier layer on the side wall of the through hole under high temperature conditions. There is no need to consider that the temporary bonding material is not resistant to high temperatures.
  • High-density interconnection modules can work alone to form high-density through holes according to design requirements to meet design requirements for higher I/O density.
  • Figure 1 is an intermediate structural schematic diagram of at least one embodiment of the present application.
  • Figure 2 is a schematic diagram of an intermediate structure of at least one embodiment of the present application.
  • Figure 3 is a schematic diagram of an intermediate structure of at least one embodiment of the present application.
  • Figure 4 is an intermediate structural schematic diagram of at least one embodiment of the present application.
  • Figure 5 is a schematic diagram of an intermediate structure of at least one embodiment of the present application.
  • Figure 6 is a schematic diagram of an intermediate structure of at least one embodiment of the present application.
  • Figure 7 is a schematic diagram of an intermediate structure of at least one embodiment of the present application.
  • Figure 8 is a schematic diagram of an intermediate structure of at least one embodiment of the present application.
  • Figure 9 is a schematic diagram of an intermediate structure of at least one embodiment of the present application.
  • Figure 10 is a schematic diagram of an intermediate structure of at least one embodiment of the present application.
  • Figure 11 is a schematic diagram of an intermediate structure of at least one embodiment of the present application.
  • Figure 12 is a schematic diagram of an intermediate structure of at least one embodiment of the present application.
  • Figure 13 is a schematic diagram of an intermediate structure of at least one embodiment of the present application.
  • silicon-based fan-out packaging As an example.
  • silicon-based grooves and through-silicon vias cannot be formed through one-step etching.
  • silicon groove etching is performed first, and then the backside silicon is etched after completing the front-side packaging of the embedded chip.
  • the etching of through holes is a typical via last process.
  • the two-step etching cannot be performed at the same time, and usually the dry etching rate is slow, which undoubtedly increases the process cycle and cost;
  • the etching process When etching through silicon holes, it is necessary to enter the etching machine with a temporary bonding structure on the front side, which may face the problem of poor heat dissipation during etching, and is risky during mass production;
  • oxide needs to be added to the side wall Barrier layer, usually the oxide layer can form a dense and stable film under high temperature conditions, but temporary bonding materials usually do not have high temperature resistance properties, which results in the limitation that the oxide layer film can only be deposited under lower temperature conditions. This is not conducive to improving the coverage of deep hole deposition; fourth, deep hole etching with a bonding structure requires bearing the yield loss caused by the fluctuation of the etching machine.
  • the packaging structure includes a protective layer 1200, a metal wiring layer 1000, a passive chip 1100, an active device 200, The high-density interconnect module 300, the first passivation layer 400, the first rewiring layer 500, the second passivation layer 600, the second rewiring layer 700 and the metal pad 710.
  • the active devices 200 and the high-density interconnection modules 300 are arranged at intervals.
  • An active device 200 is arranged between two adjacent high-density interconnection modules 300.
  • a first passivation layer 400 is formed on the device 200 and the high-density interconnection module 300.
  • the first passivation layer 400 has a first opening 410 for electrical interconnection of the active device 200 and a first opening 410 for external interconnection of the high-density interconnection module 300.
  • the second opening 420, the first redistribution layer 500 is formed at least at the first opening 410 and the second opening 420, a second passivation layer 600 is formed on the first redistribution layer 500, and several passivation layers 600 are provided in the second passivation layer 600.
  • a second rewiring layer 700 is formed on the second passivation layer 600, a metal pad 710 is provided on the second rewiring layer 700, and the solder ball 1300 is soldered on the metal pad 710.
  • the first redistribution layer 500 is electrically connected to the second redistribution layer 700 through the opening in the second passivation layer 600 .
  • a high-density 3D stacked fan-out packaging structure While etching the main groove 110 for burying the main chip, auxiliary grooves 120 of smaller or equivalent size are simultaneously etched around it. At the same time as the main chip is inserted, a separately designed and produced high-density interconnect module 300 is simultaneously embedded in the auxiliary groove 120.
  • the high-density interconnect module 300 is filled with high-density through holes and filled with metal to achieve vertical Directional interconnection.
  • the front side of the high-density interconnection module 300 faces the first passivation layer 400, and then the high-density interconnection module 300 is used to perform build-up wiring as needed to form the metal pad 710. At this point, the front side is covered with a temporary bonding film. layer of protection.
  • the wafer Turn the wafer over, with the back side facing up, and expose the high-density interconnection module 300 by grinding. Then use the high-density interconnection module 300 to make a line rewiring layer as needed, and attach multiple passive chips 1100 to the rewiring layer through patching. At the layer contact point, the passive chip 1100 and the front main chip are interconnected in the vertical direction. Finally, the passive chip 1100 is protected by filling and plastic sealing in sequence, the wafer is flipped again, the temporary bonding is released, the balls are planted, and the cutting is completed to complete the final packaging.
  • At least one embodiment of the present disclosure provides a manufacturing method of a high-density 3D stacked fan-out packaging structure, which method includes the following steps 110 to 180 .
  • Step 110 As shown in Figure 1, a carrier plate 100 is thinned to a specified thickness. Several main grooves 110 and several auxiliary grooves are formed on the carrier plate 100 by etching methods such as dry etching, mechanical processing, and 3D printing.
  • the groove 120 and the carrier plate 100 are made of silicon wafer, glass, metal alloy, composite materials and other materials.
  • Step 120 As shown in Figure 2, bury the active device 200 in the main groove 110 with the soldering pad 210 of the active device 200 facing upward. Bury the high-density interconnect module 300 in the auxiliary groove 120. The active device 200 and the high-density interconnection module 300 are respectively pasted with adhesive film layers on their bottoms, which are used to be fixed in the main groove 110 and the auxiliary groove 120 respectively.
  • the formation steps of the high-density interconnection module 300 include: first, forming an array of mask openings on a whole silicon base, glass or insulating high-temperature-resistant resin substrate, and then dry etching, high-precision machining or high-precision 3D printing technology and other methods are used to etch high-density through holes; then vacuum coating technology is used to form an oxide barrier layer on the side walls of the through holes, and then the through holes are plugged with electroplating, the silicon base is turned over, and the back side is polished by grinding The copper pillars are exposed; finally, the silicon base is cut to obtain at least one independent high-density interconnection module 300, as shown in Figure 3.
  • Step 130 As shown in Figure 4, the first passivation layer 400 is formed on the semi-finished product obtained in step 120, that is, the first passivation layer 400 is formed on the upper surface of the carrier board 100 in which the active device 200 and the high-density interconnection module 300 are embedded.
  • the first passivation layer 400 has a first opening 410 for electrical interconnection of the active device 200 and a second opening 420 for external interconnection of the high-density interconnection module 300.
  • the first opening 410 exposes the solder joints of the active device 200.
  • the pad 210 and the second opening 420 expose the copper pillars of the high-density interconnection module 300 .
  • the first passivation layer 400 can be a vacuum pressed film.
  • the first opening 410 and the second opening 420 can be opened through exposure through a mask. If it is a non-photosensitive dry film, it can be opened by laser ablation or mechanical drilling. The first opening 410 and the second opening 420 are formed in a manner.
  • the first passivation layer 400 can also be formed by spin-coating liquid photoresist, and the first opening 410 and the second opening 420 are also formed by exposure.
  • Step 140 As shown in Figure 5, add circuit layers on the semi-finished product obtained in step 130.
  • adding layers to the line includes: forming the first rewiring layer 500 using methods such as electroplating, physical vapor deposition, chemical plating, etc.; secondly, forming the second passivation layer 600 and several openings on the first rewiring layer 500; Third, the second redistribution layer 700 is formed in the same or different manner as the first redistribution layer 500; finally, the metal pad 710 is formed in the same manner.
  • the specific number of rewiring layers depends on the design requirements of the actual product.
  • the second passivation layer 600 may be a pressure-sensitive or non-photosensitive dry film, and the corresponding openings may be formed by mask exposure, laser ablation, etc.
  • the second passivation layer 600 may also be formed by spin coating or spraying liquid photoresist. , the opening formation method is mask exposure.
  • Step 150 As shown in Figure 6, a temporary bonding film layer 800 is formed on the basis of the semi-finished product obtained in step 140.
  • the upper loading plate 900 is disposed on the temporary bonding film layer 800.
  • the upper loading plate 900 and steps are implemented through the temporary bonding film layer 800.
  • 140 Temporary bonding of the resulting semi-finished product.
  • the temporary bonding film layer 800 can be a photolytic or thermally detached bonding film, temporary bonding glue, etc.
  • the upper board 900 can be made of glass, silicon-based, metal alloy, composite materials, etc. according to the type of the temporary bonding film layer 800 .
  • Step 160 As shown in Figure 7, turn over the semi-finished product structure obtained in step 150, and smooth the carrier plate 100 by grinding to expose the conductive through holes of the high-density interconnection module 300, and then there are conductive through holes on the smoothed structure.
  • the metal wiring layer 1000 refer to the formation method of the first rewiring layer 500 in step 140, which will not be described again here.
  • the passive chip 1100 is attached to the metal wiring layer 1000 through a flip-chip method. At this point, the active device 200 and the passive chip 1100 realize 3D interconnection in the vertical direction through the high-density interconnection module 300 .
  • Step 170 As shown in Figure 8, the semi-finished product structure obtained in step 160 is plastic-sealed to form a protective layer 1200.
  • Step 180 As shown in Figure 9, release the temporary bonding structure of the temporary bonding film layer 800 and the upper board 900, expose the metal pad 710, and solder the solder ball 1300 thereon for external signal conduction.
  • At least one embodiment of the present disclosure provides a manufacturing method of a high-density 3D stacked fan-out packaging structure, including the following steps 210 to 250.
  • Step 210 As shown in Figure 10, prepare a carrier plate 100, grind it to a specified thickness, and temporarily bond the carrier plate 100 and a support sheet 3000 together through the first adhesive layer 2000.
  • the main groove 110 for burying the active device 200 and the auxiliary groove 120 for burying the high-density interconnect module 300 are produced through dry etching, 3D printing, mechanical processing, etc.
  • the groove 120 is penetrating, that is, the first adhesive layer 2000 is exposed.
  • Step 220 As shown in Figure 11, bury the active device 200 in the main groove 110 with the soldering pad 210 of the active device 200 facing upward. Bury the high-density interconnection module 300 in the auxiliary groove 120.
  • the high-density interconnection module 300 The formation method is the same as step 120 in the above embodiment, and will not be described again here.
  • Step 230 As shown in Figure 12, add layers to the front circuit. This step is the same as step 130 and step 140 in the above embodiment, and is implemented according to actual product requirements.
  • Step 240 As shown in Figure 13, release the temporary bonding structure of the first adhesive layer 2000 and the support sheet 3000, and use the second adhesive layer 7000 and the carrier sheet 8000 to protect the front structure of Figure 12 through temporary bonding means. Then the wafer is flipped, and the exposed high-density interconnection module 300 is used to form a metal wiring layer 1000 as needed, and then the passive chip 1100 is mounted on the metal wiring layer 1000 to realize 3D interconnection between the active device 200 and the passive chip 1100.
  • Step 250 The subsequent process is the same as step 170 and step 180 in the above embodiment, and the packaging structure is finally obtained, as shown in Figure 9, which will not be described again here.
  • Parts or structures not specifically described in this application can adopt existing technology or existing products, and will not be described in detail here.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

本申请公开了一种高密度3D堆叠扇出型封装结构及其制造方法，该封装结构包括若干个有源器件、若干个高密度互联模块和若干个无源芯片，有源器件和无源芯片之间通过高密度互联模块实现垂直方向上的3D互联。本申请中，埋主芯片的主凹槽和旁边的尺寸较小的辅助凹槽可一步刻蚀，避免两次刻蚀，特别是避免了带着键合结构进刻蚀机刻通孔时带来的风险，大幅度缩短产品的生产周期；高密度互联模块来自于同一片基体，单独作业，可按照设计需求形成高密度的通孔，满足更高I/O密度的设计需求，而且保证重组晶圆中通孔部分的良率，同时可在高温条件下在通孔侧壁形成致密稳定的阻挡层，无需考虑临时键合材料不耐高温的情况。

Description

高密度3D堆叠扇出型封装结构及其制造方法
本申请要求于2022年07月08日递交的中国专利申请第202210801507.1号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本申请属于芯片封装技术领域，具体涉及一种高密度3D堆叠扇出型封装结构及其制造方法。
背景技术
随着前道制程工艺节点的下探接近物理极限，在单颗芯片上实现完备的电路系统集成越来越困难，集中体现在流片良率的下滑和成本的上升。在后摩尔时代，通过先进的中道封装工艺实现异质系统化集成是更为高效的解决方案。其中，三维立体堆叠则突破了芯片封装的空间限制，几乎是多芯片异质集成的必选之项。
各类通孔是该技术的关键所在。现有结构通孔密度设计有限，无法满足更多芯片的三维互联，特别是多有源器件和多无源器件的垂直组合。
发明内容
为解决现有技术中存在的技术问题，本申请提供一种高密度3D堆叠扇出型封装结构及其制造方法。
为实现上述目的，达到上述技术效果，本申请第一方面提供一种高密度3D堆叠扇出型封装结构。
该高密度3D堆叠扇出型封装结构包括至少一个有源器件、至少一个高密度互联模块和若干个无源芯片，有源器件和无源芯片之间通过高密度互联模块实现垂直方向上的3D互联。
在本申请第一方面的至少一个实施方式中，该高密度3D堆叠扇出型封 装结构还包括金属布线层，高密度互联模块的导电通孔处形成有金属布线层，无源芯片贴于金属布线层上。
在本申请第一方面的至少一个实施方式中，无源芯片通过金属布线层与导电通孔电气互联。
在本申请第一方面的至少一个实施方式中，该高密度3D堆叠扇出型封装结构还包括保护层，金属布线层和无源芯片塑封于保护层内。
在本申请第一方面的至少一个实施方式中，该高密度3D堆叠扇出型封装结构还包括第一钝化层、第一重布线层、第二钝化层、第二重布线层和金属焊盘。有源器件和高密度互联模块上表面形成第一钝化层，第一钝化层上形成有第一重布线层，第一重布线层上形成有第二钝化层，第二钝化层上形成有第二重布线层，第二重布线层上设置金属焊盘，金属焊盘上焊接锡球。
在本申请第一方面的至少一个实施方式中，第一钝化层上设置有用于有源器件电气互联的第一开口和用于与高密度互联模块对外互联的第二开口，第一重布线层至少形成在第一开口和第二开口处，第一重布线层上形成有第二钝化层和若干个开口。
在本申请第一方面的至少一个实施方式中，有源器件和高密度互联模块在同一平面内且间隔设置，相邻的高密度互联模块之间设置有一个有源器件，有源器件的焊垫位于有源器件远离无源芯片的一侧。
在本申请第一方面的至少一个实施方式中，所有高密度互联模块来自同一基体，基体采用硅基、玻璃或绝缘耐高温树脂。
在本申请第一方面的至少一个实施方式中，该高密度3D堆叠扇出型封装结构还包括载板。该载板包括间隔设置的多个主凹槽，其中相邻主凹槽之间设置有辅凹槽，有源器件设置在主凹槽中，高密度互联模块设置在辅凹槽中。
在本申请第一方面的至少一个实施方式中，主凹槽和辅凹槽分别贯穿载板。
本申请第二方面提供一种高密度3D堆叠扇出型封装结构的制造方法，该方法包括：
将一载板减薄至指定厚度，载板上形成至少一个主凹槽和至少一个辅凹 槽。在主凹槽内埋入有源器件，有源器件的背离焊垫的一侧朝向主凹槽的底部设置，在辅凹槽内埋入高密度互联模块，有源器件和高密度互联模块分别通过粘结膜层固定在主凹槽和辅凹槽内。在朝向主凹槽的开口的一侧形成第一钝化层，第一钝化层上设置有用于与有源器件电气互联的第一开口和用于实现高密度互联模块对外互联的第二开口，第一开口露出有源器件的焊垫，第二开口露出高密度互联模块的铜柱。在第一钝化层背离载板的一侧进行线路增层，以形成第一中间结构。在第一中间结构背离载板的一侧形成一层临时键合膜层，上载板设置于临时键合膜层背离载板的一侧，且通过临时键合膜层实现上载板和第一中间结构的临时键合。在第一中间结构背离上载板的一侧，通过研磨的方式将载板磨平，使高密度互联模块的导电通孔露出来，然后在磨平结构上有导电通孔的地方制作金属布线层，然后通过覆晶的方式，将无源芯片贴到金属布线层上，以使得有源器件和无源芯片通过高密度互联模块实现了垂直方向上的3D互联，以形成第二中间结构。对第二中间结构进行塑封，形成保护层。解除临时键合膜层和上载板的临时键合结构，将金属焊盘暴露出来，并在其上焊接锡球，用于对外信号导通。
在本申请第二方面的至少一个实施方式中，载板采用硅片、玻璃、金属合金或复合材料制成。
在本申请第二方面的至少一个实施方式中，高密度互联模块的形成步骤包括：在一整片基体上形成阵列的掩膜开口，刻蚀出高密度的通孔，然后在通孔的侧壁形成氧化物阻挡层，将通孔用电镀的方法塞实，翻转基体，通过研磨将背面的铜柱露出，并切割成单，得到至少一个独立的高密度互联模块。
在本申请第二方面的至少一个实施方式中，在第一钝化层背离载板的一侧进行线路增层包括：在第一钝化层背离载板的一侧形成第一重布线层，然后在第一重布线层上形成第二钝化层和若干个开口；用相同或不同于形成第一重布线层的方式在第二钝化层背离第一重布线层的一侧形成第二重布线层，以及在第二重布线层背离第二重布线层的一侧形成金属焊盘；第二钝化层中包括至少一个开口。
在本申请第二方面的至少一个实施方式中，临时键合膜层为光解或热拆的键合膜或临时键合胶，上载板为玻璃、硅基、金属合金或复合材料。
在本申请第二方面的至少一个实施方式中，在将一载板减薄至指定厚度前，该方法还包括通过第一粘结层将载板和支撑片临时键合在一起。在在第一钝化层背离载板的一侧进行线路增层后，且在第一中间结构背离载板的一侧形成一层临时键合膜层前，该方法还包括解除第一粘结层和支撑片的临时键合结构。其中，至少一个主凹槽和至少一个辅凹槽贯穿载板。
与现有技术相比，本申请的有益效果为：
1.埋主芯片的主凹槽和旁边的尺寸较小的辅助凹槽可以一步刻蚀出来，这样可以避免两次刻蚀，特别是避免了带着键合结构进刻蚀机刻蚀通孔时带来的风险。同时，减少一次刻蚀可以大幅度缩短产品的生产周期。
2.高密度互联模块来自于同一片基体(如硅基等)，可以筛选出好的互联模块埋入辅凹槽，避免了刻蚀通孔时存在的风险，保证重组晶圆中通孔部分的良率。
3.高密度互联模块是单独做的，可以在高温条件下在通孔侧壁形成致密稳定的阻挡层，无需考虑临时键合材料不耐高温的情况。
4.高密度互联模块单独作业，就可以按照设计需求形成高密度的通孔，满足更高I/O密度的设计需求。
附图说明
图1为本申请的至少一个的实施例的中间结构示意图。
图2为本申请的至少一个实施例的中间结构示意图。
图3为本申请的至少一个实施例的中间结构示意图。
图4为本申请的至少一个实施例的中间结构示意图。
图5为本申请的至少一个实施例的中间结构示意图。
图6为本申请的至少一个实施例的中间结构示意图。
图7为本申请的至少一个实施例的中间结构示意图。
图8为本申请的至少一个实施例的中间结构示意图。
图9为本申请的至少一个实施例的中间结构示意图。
图10为本申请的至少一个实施例的中间结构示意图。
图11为本申请的至少一个实施例的中间结构示意图。
图12为本申请的至少一个实施例的中间结构示意图。
图13为本申请的至少一个实施例的中间结构示意图。
具体实施方式
下面对本申请进行详细阐述，以使本申请的优点和特征能更易于被本领域技术人员理解，从而对本申请的保护范围做出更为清楚明确的界定。
以下给出一个或多个方面的简要概述以提供对这些方面的基本理解。此概述不是所有构想到的方面的详尽综览，并且既非旨在指认出所有方面的关键性或决定性要素亦非试图界定任何或所有方面的范围。其唯一的目的是要以简化形式给出一个或多个方面的一些概念以为稍后给出的更加详细的描述之序。
在本申请的描述中，需要理解的是，术语“上”、“下”、“前”、“后”、“左”、“右”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
目前对于硅基扇出或者玻璃基扇出平台技术，要实现三维堆叠互联，必须解决TSV/TGV的相关问题。以硅基扇出封装为例，通常情况下，硅基凹槽和硅通孔无法通过一步刻蚀形成，一般是先进行硅凹槽刻蚀，完成埋入芯片的正面封装后再进行背面硅通孔的刻蚀，是典型的via last工艺，这样的做法有以下问题：首先是两步刻蚀无法同时进行，通常干法刻蚀速率慢，这无疑增加了制程周期和成本；其次，刻蚀硅通孔时需要带着正面的临时键合结构进刻蚀机，这可能面临刻蚀散热不好的问题，大批量生产时有风险；第三，TSV形成后需要在侧壁增加氧化物阻挡层，通常氧化层在高温条件下才能形成致密的、稳定的薄膜，但是临时键合材料通常都不具备耐高温的特性，这就导致限制了只能在较低温条件下沉积氧化层薄膜，这不利于提高深孔沉积的覆盖率；第四，带着键合结构进行深孔刻蚀，需要承担刻蚀机波动带来的良率损失。
如图1-9所示，本申请至少一个实施例提供一种高密度3D堆叠扇出型封装结构，该封装结构包括保护层1200、金属布线层1000、无源芯片1100、有源器件200、高密度互联模块300、第一钝化层400、第一重布线层500、第二钝化层 600、第二重布线层700和金属焊盘710。
有源器件200和高密度互联模块300分别设置有若干个，有源器件200和高密度互联模块300间隔设置，相邻两个高密度互联模块300之间设置有一个有源器件200，有源器件200和高密度互联模块300上形成第一钝化层400，第一钝化层400上开有用于有源器件200电气互联的第一开口410和用于实现高密度互联模块300对外互联的第二开口420，第一重布线层500至少形成于第一开口410和第二开口420处，第一重布线层500上形成有第二钝化层600，第二钝化层600中设置若干个开口，第二钝化层600上形成有第二重布线层700，第二重布线层700上设置金属焊盘710，金属焊盘710上焊接锡球1300。第一重布线层500通过第二钝化层600中的开口与第二重布线层700电连接。
一种高密度3D堆叠扇出型封装结构，在刻蚀用于埋入主芯片的主凹槽110的同时，在其周围同步刻蚀出尺寸更小或尺寸相当的辅凹槽120，在埋入主芯片的同时，同步在辅凹槽120中埋入单独设计并制作的高密度互联模块300，该高密度互联模块300内部布满高密度的通孔，并用金属填实，用于实现垂直方向上的互联。高密度互联模块300的正面朝向第一钝化层400，然后高密度互联模块300的正面按需要利用高密度互联模块300进行增层布线至形成金属焊盘710，至此，正面用临时键合膜层保护起来。翻转晶圆，背面朝上，通过研磨将高密度互联模块300暴露出来，然后利用高密度互联模块300按需制作线路重布线层，将多个无源芯片1100通过贴片的方式贴在重布线层接触点上，实现无源芯片1100和正面主芯片垂直方向上的互联。最后依次通过填充、塑封将无源芯片1100保护起来，再次翻转晶圆，解除临时键合，植球，切割，完成最终的封装。
本公开至少一个实施例提供一种高密度3D堆叠扇出型封装结构的制造方法，该方法包括以下步骤110至步骤180。
步骤110：如图1所示，将一载板100减薄至指定厚度，载板100上通过干法刻蚀、机械加工、3D打印等刻蚀方法形成若干个主凹槽110和若干个辅凹槽120，载板100采用硅片、玻璃、金属合金以及复合材料等材料。
步骤120：如图2所示，在主凹槽110内埋入有源器件200，有源器件200的焊垫210朝上，在辅凹槽120内埋入高密度互联模块300，有源器件200和高密度互联模块300的下方分别贴有粘接膜层，分别用于固定在主凹槽110和辅凹 槽120内。
其中，高密度互联模块300的形成步骤包括：首先，在一整片硅基、玻璃或绝缘耐高温树脂等基体上形成阵列的掩膜开口，通过干法刻蚀、高精度机械加工或者高精度3D打印技术等方式刻蚀出高密度的通孔；然后通过真空镀膜技术在通孔的侧壁形成氧化物阻挡层，接着将通孔用电镀的方法塞实，翻转硅基，通过研磨将背面的铜柱露出；最后，切割硅基，得到至少一个独立的高密度互联模块300，如图3所示。
步骤130：如图4，在步骤120所得半成品上形成第一钝化层400，也即在埋入有源器件200和高密度互联模块300的载板100上表面形成第一钝化层400，第一钝化层400上开有用于有源器件200电气互联的第一开口410和用于实现高密度互联模块300对外互联的第二开口420，第一开口410处露出有源器件200的焊垫210，第二开口420处露出高密度互联模块300的铜柱。第一钝化层400可以是真空压膜，若是感光干膜，可以通过曝掩膜曝光打开第一开口410和第二开口420，若是非感光干膜，则可以通过激光烧蚀或机械钻孔的方式形成第一开口410和第二开口420。第一钝化层400也可以是旋涂液态光刻胶形成，第一开口410和第二开口420也是采用曝光的方式形成。
步骤140：如图5，在步骤130所得半成品上进行线路增层。
具体地，进行线路增层包括：采用电镀、物理气相沉积、化学镀等方法形成第一重布线层500；其次，在第一重布线层500上形成第二钝化层600和若干个开口；第三，用相同或不同于形成第一重布线层500的方式形成第二重布线层700；最后，用相同的方式形成金属焊盘710。具体的重布线层数取决于实际产品的设计要求。其中，第二钝化层600可以是压感光或非感光干膜，对应开口形成方式是掩膜曝光和激光烧蚀等，第二钝化层600也可以是旋涂或喷涂液态光刻胶形成，开口形成方式是掩膜曝光。
步骤150：如图6，在步骤140所得半成品基础上形成一层临时键合膜层800，上载板900设置于临时键合膜层800上，通过临时键合膜层800实现上载板900和步骤140所得半成品的临时键合。临时键合膜层800可以是光解或热拆的键合膜、临时键合胶等，上载板900根据临时键合膜层800的种类可以选用玻璃、硅基、金属合金以及复合材料等。
步骤160：如图7，将步骤150所得半成品结构翻转过来，通过研磨的方式将载板100磨平，使高密度互联模块300的导电通孔露出来，然后在磨平结构上有导电通孔的地方制作金属布线层1000，参考步骤140的第一重布线层500的形成方式，这里不再赘述。然后通过覆晶的方式，将无源芯片1100贴到金属布线层1000上，至此，有源器件200和无源芯片1100通过高密度互联模块300实现了垂直方向上的3D互联。
步骤170：如图8，对步骤160所得半成品结构进行塑封，形成保护层1200。
步骤180：如图9，解除临时键合膜层800和上载板900的临时键合结构，将金属焊盘710暴露出来，并在其上焊接锡球1300，用于对外信号导通。
如图9-13所示，本公开至少一个实施例提供一种高密度3D堆叠扇出型封装结构的制造方法，包括以下步骤210-步骤250。
步骤210：如图10，准备一载板100，将其研磨至指定厚度，并通过第一粘结层2000将载板100和一支撑片3000临时键合在一起。通过干法刻蚀、3D打印、机械加工等方式制作出用于埋入有源器件200的主凹槽110和用于埋入高密度互联模块300的辅凹槽120，主凹槽110和辅凹槽120是贯穿的，即第一粘结层2000是暴露出来的。
步骤220：如图11，在主凹槽110内埋入有源器件200，有源器件200的焊垫210朝上，在辅凹槽120内埋入高密度互联模块300，高密度互联模块300的形成方法同上述实施例中步骤120，这里不再赘述。
步骤230：如图12，进行正面线路增层，该步骤与上述实施例中步骤130和步骤140相同，按实际产品需求实现。
步骤240：如图13，解除第一粘结层2000和支撑片3000的临时键合结构，并使用第二粘结层7000和载片8000将图12的正面结构通过临时键合手段保护起来，然后翻转晶圆，利用暴露的高密度互联模块300按需形成金属布线层1000，再将无源芯片1100贴片到金属布线层1000上，实现有源器件200和无源芯片1100的3D互联。
步骤250：后续制程与上述实施例中的步骤170和步骤180相同，最终得到封装结构，如图9所示，这里不再赘述。
余同上述实施例。
本申请未具体描述的部分或结构采用现有技术或现有产品即可，在此不做赘述。
以上所述仅为本申请的实施例，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (16)

  1. 一种高密度3D堆叠扇出型封装结构，其特征在于，包括至少一个有源器件、至少一个高密度互联模块和至少一个无源芯片，所述有源器件和所述无源芯片之间通过所述高密度互联模块实现垂直方向上的3D互联。
  2. 根据权利要求1所述的高密度3D堆叠扇出型封装结构，其特征在于，还包括：
    金属布线层，所述高密度互联模块的导电通孔处形成有所述金属布线层，所述无源芯片贴于所述金属布线层上。
  3. 根据权利要求2所述的高密度3D堆叠扇出型封装结构，其特征在于，所述无源芯片通过所述金属布线层与所述导电通孔电气互联。
  4. 根据权利要求2或3所述的高密度3D堆叠扇出型封装结构，其特征在于，还包括：
    保护层，所述金属布线层和所述无源芯片塑封于所述保护层内。
  5. 根据权利要求1-4中任一项所述的一种高密度3D堆叠扇出型封装结构，其特征在于，还包括：第一钝化层、第一重布线层、第二钝化层、第二重布线层和金属焊盘，所述有源器件和高密度互联模块上表面形成有第一钝化层，所述第一钝化层上形成有第一重布线层，所述第一重布线层上形成有第二钝化层，所述第二钝化层上形成有第二重布线层，所述第二重布线层上设置金属焊盘，所述金属焊盘上焊接锡球。
  6. 根据权利要求5所述的高密度3D堆叠扇出型封装结构，其特征在于，所述第一钝化层上设置有用于与所述有源器件电气互联的第一开口和用于与所述高密度互联模块电气互联的第二开口，所述第一重布线层至少形成在所述第一开口和所述第二开口处，所述第一重布线层上形成有第二钝化层和若干个开口。
  7. 根据权利要求1-6中任一项所述的高密度3D堆叠扇出型封装结构，其特征在于，所述有源器件和所述高密度互联模块在同一平面内且间隔设置，相邻的高密度互联模块之间设置有一个所述有源器件，所述有源器件的焊垫位于所述有源器件远离所述无源芯片的一侧。
  8. 根据权利要求1-7中任一项所述的高密度3D堆叠扇出型封装结构， 其特征在于，还包括：
    载板，包括间隔设置的多个主凹槽，其中相邻所述主凹槽之间设置有辅凹槽，所述有源器件设置在所述主凹槽中，所述高密度互联模块设置在所述辅凹槽中。
  9. 根据权利要求8所述的高密度3D堆叠扇出型封装结构，其特征在于，
    所述主凹槽和所述辅凹槽分别贯穿所述载板。
  10. 根据权利要求1-9中任一项所述的高密度3D堆叠扇出型封装结构，其特征在于，所述至少一个高密度互联模块包括多个高密度互联模块，所述多个高密度互联模块来自同一基体，所述基体采用硅基、玻璃或绝缘耐高温树脂制成。
  11. 一种高密度3D堆叠扇出型封装结构的制造方法，其特征在于，包括：
    将一载板减薄至指定厚度，所述载板上形成至少一个主凹槽和至少一个辅凹槽；
    在所述主凹槽内埋入有源器件，所述有源器件的背离焊垫的一侧朝向所述主凹槽的底部设置，在所述辅凹槽内埋入高密度互联模块，所述有源器件和所述高密度互联模块分别通过粘接膜层固定在所述主凹槽和所述辅凹槽内；
    在朝向所述主凹槽的开口的一侧形成第一钝化层，所述第一钝化层上设置有用于与所述有源器件电气互联的第一开口和用于与所述高密度互联模块电气互联的第二开口，所述第一开口露出所述有源器件的焊垫，所述第二开口露出所述高密度互联模块的铜柱；
    在所述第一钝化层背离所述载板的一侧进行线路增层，以形成第一中间结构；
    在所述第一中间结构背离所述载板的一侧形成一层临时键合膜层，上载板设置于所述临时键合膜层背离所述载板的一侧，且通过所述临时键合膜层实现所述上载板和第一中间结构的临时键合；
    在所述第一中间结构背离所述上载板的一侧，通过研磨的方式将载板磨平，使所述高密度互联模块的导电通孔露出来，然后在磨平结构上有导电通 孔的地方制作金属布线层，然后通过覆晶的方式，将无源芯片贴到所述金属布线层上，以使得所述有源器件和所述无源芯片通过高密度互联模块实现垂直方向上的3D互联，以形成第二中间结构；
    对所述第二中间结构进行塑封，以形成保护层；以及
    解除所述临时键合膜层和所述上载板的临时键合结构，将金属焊盘暴露出来，并在其上焊接锡球，用于对外信号导通。
  12. 根据权利要求11所述的高密度3D堆叠扇出型封装结构的制造方法，其特征在于，所述载板采用硅片、玻璃、金属合金或复合材料制成。
  13. 根据权利要求11或12所述的一种高密度3D堆叠扇出型封装结构的制造方法，其特征在于，所述高密度互联模块的形成步骤包括：
    在一整片基体上形成阵列的掩膜开口，刻蚀出高密度的通孔，然后在所述通孔的侧壁形成氧化物阻挡层，将所述通孔用电镀的方法塞实，翻转基体，通过研磨将背面的铜柱露出，并切割基体，得到至少一个独立的高密度互联模块。
  14. 根据权利要求11-13中任一项所述的高密度3D堆叠扇出型封装结构的制造方法，其特征在于，所述在所述第一钝化层背离所述载板的一侧进行线路增层包括：
    在所述第一钝化层背离所述载板的一侧形成第一重布线层，然后在第一重布线层上形成第二钝化层；用相同或不同于形成第一重布线层的方式在所述第二钝化层背离所述第一重布线层的一侧形成第二重布线层，以及在所述第二重布线层背离所述第二重布线层的一侧形成金属焊盘；所述第二钝化层中包括至少一个开口。
  15. 根据权利要求11-14中任一项所述的高密度3D堆叠扇出型封装结构的制造方法，其特征在于，所述临时键合膜层为光解或热拆的键合膜或临时键合胶，所述上载板为玻璃、硅基、金属合金或复合材料。
  16. 根据权利要求11-15中任一项所述的高密度3D堆叠扇出型封装结构的制造方法，其特征在于，在所述将一载板减薄至指定厚度前，所述方法还包括：
    通过第一粘结层将所述载板和支撑片临时键合在一起；以及
    在所述在所述第一钝化层背离所述载板的一侧进行线路增层后，且在所述第一中间结构背离所述载板的一侧形成一层临时键合膜层前，所述方法还包括：
    解除所述第一粘结层和所述支撑片的临时键合结构；
    其中，所述至少一个主凹槽和所述至少一个辅凹槽贯穿所述载板。
PCT/CN2022/116559 2022-07-08 2022-09-01 高密度3d堆叠扇出型封装结构及其制造方法 WO2024007440A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210801507.1A CN115101514A (zh) 2022-07-08 2022-07-08 一种高密度3d堆叠扇出型封装结构及其制造工艺
CN202210801507.1 2022-07-08

Publications (1)

Publication Number Publication Date
WO2024007440A1 true WO2024007440A1 (zh) 2024-01-11

Family

ID=83296421

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/116559 WO2024007440A1 (zh) 2022-07-08 2022-09-01 高密度3d堆叠扇出型封装结构及其制造方法

Country Status (2)

Country Link
CN (1) CN115101514A (zh)
WO (1) WO2024007440A1 (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105575913A (zh) * 2016-02-23 2016-05-11 华天科技（昆山）电子有限公司 埋入硅基板扇出型3d封装结构
CN107634049A (zh) * 2017-09-15 2018-01-26 中国电子科技集团公司第五十八研究所 Fc芯片系统堆叠扇出封装结构及其制备方法
US20210123729A1 (en) * 2019-10-24 2021-04-29 International Business Machines Corporation Non-destructive bond line thickness measurement of thermal interface material on silicon packages
CN113725153A (zh) * 2021-08-31 2021-11-30 中国电子科技集团公司第五十八研究所 多层多芯片扇出型三维集成封装方法及结构

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105575913A (zh) * 2016-02-23 2016-05-11 华天科技（昆山）电子有限公司 埋入硅基板扇出型3d封装结构
CN107634049A (zh) * 2017-09-15 2018-01-26 中国电子科技集团公司第五十八研究所 Fc芯片系统堆叠扇出封装结构及其制备方法
US20210123729A1 (en) * 2019-10-24 2021-04-29 International Business Machines Corporation Non-destructive bond line thickness measurement of thermal interface material on silicon packages
CN113725153A (zh) * 2021-08-31 2021-11-30 中国电子科技集团公司第五十八研究所 多层多芯片扇出型三维集成封装方法及结构

Also Published As

Publication number Publication date
CN115101514A (zh) 2022-09-23

Similar Documents

Publication Publication Date Title
TWI692838B (zh) 半導體封裝及其形成方法
US11164754B2 (en) Fan-out packages and methods of forming the same
US10867897B2 (en) PoP device
KR102329567B1 (ko) 반도체 패키지 및 그를 형성하는 방법
TWI640045B (zh) 半導體裝置及製造方法
TWI764032B (zh) 天線整合式封裝結構及其製造方法
WO2019179184A1 (zh) 一种封装结构及其制作方法、电子设备
US9111947B2 (en) Chip arrangement with a recessed chip housing region and a method for manufacturing the same
KR102383912B1 (ko) 팬-아웃 패키지 및 그 형성 방법
KR20120052171A (ko) 반도체 패키지 및 반도체 소자 패키징 방법
WO2022012538A1 (zh) 多芯片3d封装结构及其制作方法
TW201533869A (zh) 半導體元件及其製作方法
TW202209598A (zh) 半導體系統封裝及其製造方法
TW202401709A (zh) 接合組裝
JP2022023830A (ja) 半導体パッケージにおける放熱及びその形成方法
WO2024007440A1 (zh) 高密度3d堆叠扇出型封装结构及其制造方法
WO2022095695A1 (zh) Mcm封装结构及其制作方法
CN115579324A (zh) 中介层结构及其制作方法
CN115527972A (zh) 高密度互联三维集成器件封装结构及其制造方法
TW202230541A (zh) 封裝及其製作方法
TWI611530B (zh) 具有散熱座之散熱增益型面朝面半導體組體及製作方法
TWI821476B (zh) 半導體裝置及其製造方法
CN114914196B (zh) 基于芯粒概念的局部中介层2.5d扇出封装结构及工艺
WO2024022273A1 (zh) 扇出型系统级封装结构及其制作方法
TWI739650B (zh) 具有近零接合線厚度之三維堆疊半導體總成

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22950002

Country of ref document: EP

Kind code of ref document: A1