WO2024000494A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2024000494A1
WO2024000494A1 PCT/CN2022/103082 CN2022103082W WO2024000494A1 WO 2024000494 A1 WO2024000494 A1 WO 2024000494A1 CN 2022103082 W CN2022103082 W CN 2022103082W WO 2024000494 A1 WO2024000494 A1 WO 2024000494A1
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Prior art keywords
electrode
source
substrate
layer pattern
active layer
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PCT/CN2022/103082
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English (en)
French (fr)
Inventor
王东方
刘威
胡合合
王利忠
宁策
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京东方科技集团股份有限公司
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Priority to PCT/CN2022/103082 priority Critical patent/WO2024000494A1/zh
Priority to CN202280002049.3A priority patent/CN117730413A/zh
Publication of WO2024000494A1 publication Critical patent/WO2024000494A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present disclosure relates to but is not limited to the field of display technology, and specifically relates to a display substrate, a preparation method thereof, and a display device.
  • low-temperature polysilicon thin film transistors (English: Low Temperature Poly-Silicon Thin Film Transistor; abbreviation: LTPS TFT) and oxide (Oxide) thin film transistors have attracted much attention in the display industry, and each has its own advantages.
  • Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging.
  • Indium gallium zinc oxide (In-Ga-Zn-Oxide, IGZO) thin film transistor i.e. IGZO-TFT
  • IGZO-TFT Indium gallium zinc oxide
  • IGZO-TFT Indium gallium zinc oxide
  • IGZO-TFT Indium gallium zinc oxide
  • IGZO-TFT Indium gallium zinc oxide
  • IGZO-TFT Indium gallium zinc oxide
  • IGZO-TFT Indium gallium zinc oxide
  • IGZO-TFT Indium gallium zinc oxide
  • IGZO-TFT Indium gallium zinc oxide
  • the parasitic capacitance in the extension direction of the data line has become the most important factor restricting the increase in pixel density and refresh rate of the display panel.
  • the size and current of the transistors in the pixel circuit are key factors affecting the capacitance and power consumption of the drive circuit.
  • the present disclosure provides a display substrate, including: a substrate and at least one transistor disposed on the substrate; the transistor includes:
  • An active layer pattern is provided on the substrate
  • a first source and drain electrode is provided on the substrate, and the first source and drain electrode is electrically connected to the active layer pattern;
  • a first gate electrode is provided on the side of the active layer pattern away from the substrate.
  • the first gate electrode and the active layer pattern overlap in the orthographic projection of the substrate and do not contact each other. ;
  • a second source-drain electrode is provided on the side of the active layer pattern away from the substrate.
  • the second source-drain electrode includes a first sub-electrode and a second sub-electrode connected to each other.
  • the second sub-electrode is located on The first sub-electrode is close to the side of the first gate electrode, the first sub-electrode is electrically connected to the active layer pattern, the second sub-electrode and the active layer pattern are on the substrate
  • the orthographic projections overlap and do not touch each other.
  • the second source-drain electrode further includes a third sub-electrode, the third sub-electrode is located on a side of the first sub-electrode away from the first gate electrode, and the third sub-electrode
  • the orthographic projection of the electrode and the active layer pattern on the substrate overlaps and does not contact each other.
  • the first sub-electrode and the second sub-electrode are integrally formed.
  • the first source-drain electrode includes a fourth sub-electrode and a fifth sub-electrode connected to each other, and the fifth sub-electrode is located on a side of the fourth sub-electrode away from the first gate electrode.
  • the fourth sub-electrode is electrically connected to the active layer pattern, the fifth sub-electrode and the active layer pattern overlap in the orthographic projection of the substrate, and do not contact each other.
  • the transistor further includes a first insulating layer located between the active layer pattern and the first gate electrode, the first insulating layer connecting the active layer pattern to the first gate electrode.
  • the source layer pattern covers the first source-drain electrode, the first gate electrode and the second source-drain electrode and are located on the side of the first insulating layer away from the substrate.
  • a first via hole and a second via hole are provided, the first source and drain electrode is electrically connected to the active layer pattern through the first via hole, and the second source and drain electrode passes through the second via hole. electrically connected to the active layer pattern.
  • the transistor further includes a first insulating layer, the first insulating layer includes at least one insulating layer pattern, the insulating layer pattern covers part of the active layer pattern, and the insulating layer pattern There is a non-overlapping area with the orthographic projection of at least part of the active layer pattern on the substrate, and the first source and drain electrodes, the first gate electrode and the second source and drain electrode are all located on the third An insulating layer is away from the side of the substrate, and the first source and drain electrodes and the second source and drain electrodes are electrically connected to non-overlapping areas of the active layer pattern respectively.
  • a pixel electrode is further provided on a side of the transistor away from the substrate, and the pixel electrode is integrally formed with the second source and drain electrode.
  • the first source and drain electrodes are integrally formed with the active layer pattern.
  • a signal line is further included, and the signal line is electrically connected to the first source and drain electrode.
  • the signal line is located between the first source and drain electrode and the substrate, and the display substrate further includes a buffer layer, the buffer layer is located between the signal line and the active Between the layer patterns, a third via hole is provided in the buffer layer, and the first source and drain electrode is electrically connected to the signal line through the third via hole.
  • the first source-drain electrode is integrally formed with the active layer pattern, the signal line is in electrical contact with the first source-drain electrode, and the signal line is located on the first source-drain electrode. Very close to the side of the substrate, or the signal line is located on the side of the first source and drain electrode away from the substrate.
  • the active layer pattern is made of an oxide semiconductor.
  • the transistor is configured as a transistor in a gate drive circuit.
  • the present disclosure also provides a display device, including the aforementioned display substrate bracket.
  • the present disclosure also provides a method for preparing a display substrate, including:
  • first source and drain electrode on the substrate so that at least part of the first source and drain electrode is electrically connected to the active layer pattern
  • a first gate electrode is formed on the side of the active layer pattern away from the substrate, so that the first gate electrode and the active layer pattern overlap in the orthographic projection of the substrate and do not contact each other. ;
  • a second source-drain electrode is formed on the side of the active layer pattern away from the substrate.
  • the second source-drain electrode includes a first sub-electrode and a second sub-electrode connected to each other.
  • the second sub-electrode is located on the side of the active layer pattern away from the substrate.
  • the first sub-electrode is close to the side of the first gate electrode, the first sub-electrode is electrically connected to the active layer pattern, and the second sub-electrode and the active layer pattern are on the side of the substrate. Orthographic projections overlap and do not touch each other.
  • Figure 1a is a schematic structural diagram of a transistor in a display substrate according to an embodiment of the present disclosure
  • Figure 1b is a cross-sectional view of a display substrate according to an embodiment of the present disclosure
  • Figure 2 shows circuit symbols of transistors in a substrate according to an embodiment of the present disclosure
  • Figure 3a is an equivalent circuit diagram 1 of a transistor in a display substrate according to an embodiment of the present disclosure
  • Figure 3b is an equivalent circuit diagram 2 of the transistor in the display substrate according to the embodiment of the present disclosure.
  • Figure 4a is a graph 1 showing the drain-source current of the transistor in the substrate when charging according to an embodiment of the present disclosure
  • Figure 4b is a graph 1 showing the drain-source current of the transistor in the substrate during discharge according to an embodiment of the present disclosure
  • Figure 4c is a second graph showing the drain-source current of the transistor in the substrate when charging according to an embodiment of the present disclosure
  • Figure 4d is a second graph showing a graph of the drain-source current of the transistor in the substrate during discharge according to an embodiment of the present disclosure
  • Figure 5 is a graph showing the drain-source current of the transistor in the substrate when the transistor in the related technology is under voltage
  • Figure 6 is a cross-sectional view of a transistor in a related art display substrate
  • Figure 7a is a schematic diagram 2 showing the structure of a transistor in a substrate according to an embodiment of the present disclosure
  • Figure 7b is a second cross-sectional view of a display substrate according to an embodiment of the present disclosure.
  • Figure 8a is a schematic diagram 3 showing the structure of a transistor in a substrate according to an embodiment of the present disclosure
  • Figure 8b is a third cross-sectional view of the display substrate according to the embodiment of the present disclosure.
  • Figure 9a is a schematic diagram 4 showing the structure of a transistor in a substrate according to an embodiment of the present disclosure
  • Figure 9b is a cross-sectional view 4 of a display substrate according to an embodiment of the present disclosure.
  • Figure 10 is a cross-sectional view of a display substrate according to an embodiment of the present disclosure.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • a transistor refers to an element including at least three terminals: a first gate electrode, a second source-drain electrode, and a first source-drain electrode.
  • the transistor has a second source-drain electrode (second source-drain electrode terminal, drain region, or second source-drain electrode) and a first source-drain electrode (first source-drain electrode terminal, source region, or first source-drain electrode).
  • second source-drain electrode second source-drain electrode terminal, drain region, or second source-drain electrode
  • first source-drain electrode terminal, source region, or first source-drain electrode first source-drain electrode terminal, source region, or first source-drain electrode.
  • channel region refers to the region through which current mainly flows.
  • the first electrode may be a second source-drain electrode and the second electrode may be a first source-drain electrode, or the first electrode may be a first source-drain electrode and the second electrode may be a second source-drain electrode.
  • the functions of the "first source-drain electrode” and the “second source-drain electrode” may be interchanged with each other. Therefore, in this specification, the "first source-drain electrode” and the “second source-drain electrode” may be interchanged with each other.
  • electrical connection includes a case where constituent elements are connected together through an element having some electrical effect.
  • component having some electrical function There is no particular limitation on the “component having some electrical function” as long as it can transmit and receive electrical signals between the connected components.
  • elements having some electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.
  • parallel refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it also includes a state in which the angle is -5° or more and 5° or less.
  • vertical refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes an angle of 85° or more and 95° or less.
  • film and “layer” may be interchanged.
  • conductive layer may sometimes be replaced by “conductive film.”
  • insulating film may sometimes be replaced by “insulating layer”.
  • FIG. 5 is a graph showing the drain-source current of the transistor in the substrate when the transistor in the related art substrate is under voltage.
  • the horizontal axis is the voltage Vg of the first gate electrode (unit: volt)
  • the vertical axis is the current Ids between the drain and the source (unit: ampere).
  • the curve of the current between the drain and the source before the transistor fails is a
  • the curve of the current between the drain and the source after the transistor fails is b.
  • Transistor failure occurs due to device degradation due to high voltage and current density.
  • An embodiment of the present disclosure provides a display substrate, including: a substrate and at least one transistor provided on the substrate; the transistor includes:
  • An active layer pattern is provided on the substrate
  • An active layer pattern is provided on the substrate
  • a first source and drain electrode is provided on the substrate, and the first source and drain electrode is electrically connected to the active layer pattern;
  • a first gate electrode is provided on the side of the active layer pattern away from the substrate.
  • the first gate electrode and the active layer pattern overlap in the orthographic projection of the substrate and do not contact each other. ;
  • a second source-drain electrode is provided on the side of the active layer pattern away from the substrate.
  • the second source-drain electrode includes a first sub-electrode and a second sub-electrode connected to each other.
  • the second sub-electrode is located on The first sub-electrode is close to the side of the first gate electrode, the first sub-electrode is electrically connected to the active layer pattern, the second sub-electrode and the active layer pattern are on the substrate
  • the orthographic projections overlap and do not touch each other.
  • Embodiments of the present disclosure show that the substrate is electrically connected to the active layer pattern through the first sub-electrode of the second source-drain electrode, and the second sub-electrode of the second source-drain electrode and the active layer pattern overlap in the orthographic projection of the substrate and are not in contact with each other.
  • the first sub-electrode of the second source-drain electrode can be configured as the source-drain electrode
  • the second sub-electrode of the second source-drain electrode can be configured as the second gate electrode.
  • the first sub-electrode and the second sub-electrode in the second source-drain electrode can be The sub-electrodes are configured as source and drain electrodes, thereby enabling the transistor to form a single-gate structure and speeding up charging.
  • FIG. 1 a is a schematic structural diagram of a transistor in a display substrate according to an embodiment of the present disclosure
  • FIG. 1 b is a cross-sectional view of a display substrate according to an embodiment of the present disclosure.
  • Figure 1b is a cross-sectional view of A-A' in Figure 1a.
  • the display substrate of the embodiment of the present disclosure may include a substrate 101 and at least one transistor 100 disposed on the substrate 101 .
  • the transistor 100 includes a buffer layer 1, a semiconductor layer, a first insulating layer 6, a conductive layer and a second insulating layer 7 provided on a substrate 101; the semiconductor layer includes an active layer pattern 2; the conductive layer includes a first source and drain electrode 3, The second source and drain electrodes 4 and the first gate electrode 5 .
  • the first source and drain electrodes 3 , the second source and drain electrodes 4 and the first gate electrode 5 all extend along the second direction (for example, direction Y).
  • the source and drain electrodes 4 and the first gate electrode 5 are arranged at intervals along the first direction (for example, direction X), and the first gate electrode 5 is located between the first source and drain electrode 3 and the second source and drain electrode 4 .
  • the first direction is different from the second direction. For example, the first direction is perpendicular to the second direction.
  • the transistor 100 may be an oxide (Oxide) thin film transistor, and the active layer in the transistor may be made of an oxide semiconductor material.
  • the active layer in the transistor may be made of indium gallium zinc oxide (IGZO).
  • the transistor 100 may be used as a transistor in a gate drive circuit, an input circuit, an operating voltage circuit, and the like.
  • the first gate electrode 5 and the active layer pattern 2 overlap in the orthographic projection of the substrate 101 , and the first gate electrode 5 and the active layer pattern 2 pass through the first
  • the insulating layers 6 are separated from each other and do not contact each other.
  • a first via hole 61 and a second via hole 62 are provided in the first insulating layer 6 , and the first source and drain electrode 3 is connected to the first via hole 61 through the first via hole 61 .
  • the source layer pattern 2 is electrically connected, and the second source and drain electrode 4 includes a first sub-electrode 41 and a second sub-electrode 42 that are connected to each other.
  • the second sub-electrode 42 is located on the side of the first sub-electrode 41 close to the first gate electrode 5; the second sub-electrode 42 overlaps with the active layer pattern 2 in the orthographic projection of the substrate 101, and the second sub-electrode 42 overlaps with the active layer pattern 2.
  • the source layer patterns 2 are separated from each other by the first insulating layer 6 and do not contact each other.
  • the first sub-electrode 41 is electrically connected to the active layer pattern 2 through the second via hole 62 .
  • the first insulation layer 6 may also be called a gate insulation (GI) layer.
  • first sub-electrode 41 and the second sub-electrode 42 can be integrally formed to form a film structure, and the first sub-electrode 41 and the second sub-electrode 42 can be prepared using the same material through the same preparation process. become.
  • the second source-drain electrode 4 further includes a third sub-electrode 43 , and the third sub-electrode 43 is located on the side of the first sub-electrode 41 away from the first gate electrode 5 .
  • the third sub-electrode 43 and the active layer pattern 2 overlap in the orthographic projection of the substrate 101, and are separated from each other by the first insulating layer 6 and do not contact each other.
  • the first source-drain electrode 3 includes a fourth sub-electrode 31 and a fifth sub-electrode 32 connected to each other.
  • the fifth sub-electrode 32 is located away from the fourth sub-electrode 31 .
  • the fourth sub-electrode 31 is electrically connected to the active layer pattern 2.
  • the fifth sub-electrode 32 and the active layer pattern 2 overlap in the orthographic projection of the substrate 101, and pass through the first insulating layer. 6 Separate from each other and do not touch each other.
  • the fourth sub-electrode 31 and the fifth sub-electrode 32 can be integrally formed to form a film structure, and the fourth sub-electrode 31 and the fifth sub-electrode 32 can be made of the same material through the same preparation process.
  • FIG. 2 shows circuit symbols of transistors in a substrate according to an embodiment of the present disclosure.
  • G is a gate electrode
  • S is a source electrode
  • D is a drain electrode.
  • Vg-Vs gate-source voltage
  • the transistor is turned off, and at this time there is a leakage current I off between the drain and the source.
  • the gate-source voltage Vgs is lower than the threshold voltage Vth, the transistor operates, the source voltage is higher than the drain voltage, and holes flow as carriers from the source through the channel region to the drain.
  • FIG. 3a is the first equivalent circuit diagram of the transistor in the display substrate according to the embodiment of the present disclosure
  • FIG. 3b is the second equivalent circuit diagram of the transistor in the display substrate according to the embodiment of the present disclosure.
  • the embodiment of the present disclosure shows that when the transistor in the substrate is discharging, a high potential voltage Vg can be applied to the first gate electrode 5 of the transistor, and a high potential voltage Vg can be applied to the second source of the transistor.
  • a high-potential voltage Vd is applied to the drain electrode 4, and a low-potential voltage Vs is applied to the first source-drain electrode 3 of the transistor, so that the first sub-electrode 41 of the second source-drain electrode 4 is configured as a source-drain electrode, causing the second source-drain electrode to drain.
  • the second sub-electrode 42 in electrode 4 is configured as a second gate electrode, thereby allowing the transistor to form a double-gate structure; the embodiment of the present disclosure shows that when the transistor in the substrate is charging, a high potential voltage can be applied to the first gate electrode 5 of the transistor Vg, a low potential voltage Vd can be applied to the second source-drain electrode 4 of the transistor, and a high-potential voltage Vs can be applied to the first source-drain electrode 3 of the transistor, so that the first sub-electrode 41 and the second sub-electrode 41 in the second source-drain electrode 4
  • the sub-electrodes 42 are configured as source and drain electrodes, so that the transistor forms a single-gate structure.
  • the embodiment of the present disclosure shows that the calculation formula of the current Ids between the drain and the source of the transistor in the substrate when discharging is:
  • the embodiment of the present disclosure shows that the calculation formula of the current Ids between the drain and the source of the transistor in the substrate when charging is:
  • Vm is a relevant variable, related to the specific transistor design, and can be calculated specifically through the above formula;
  • W 1 is the length of the first gate electrode 5 in the first direction (for example, direction X);
  • L 1 is the first gate electrode 5 is the length in the second direction (for example, direction Y);
  • Vth 1 is the threshold voltage of the first gate electrode 5;
  • W 2 is the length of the second gate electrode in the first direction (for example, direction X);
  • L 2 is the The length of the second gate electrode in the second direction (for example, direction Y);
  • Vth 2 is the threshold voltage of the second gate electrode.
  • FIG. 4a is a graph 1 showing the drain-source current of the transistor in the substrate when charging according to an embodiment of the disclosure
  • FIG. 4b is a graph 1 showing the drain-source current of the transistor in the substrate during discharge according to an embodiment of the disclosure.
  • Figures 4a and 4b are both drain-source current curves using the equivalent circuit shown in Figure 3a.
  • the horizontal axis is the voltage Vg of the first gate electrode (unit: volt)
  • the vertical axis is the current Ids between the drain and the source (unit: ampere).
  • the embodiment of the present disclosure shows that when the transistor in the substrate is charged, the transistor forms a single gate structure, and the open-state current Ion changes greatly.
  • the embodiment of the present disclosure shows that when the transistor in the substrate is discharging, the transistor forms a double-gate structure, which can effectively control the open-state current Ion and avoid the impact of high current density on the transistor.
  • the substrate can accelerate the charging speed during charging and effectively reduce the leakage current I off during discharging.
  • Embodiments of the present disclosure show that if the turn-on voltage of the substrate is adjusted to above 0.5V, the transistor can achieve reverse turn-off.
  • Figure 4c is a second graph showing the current between the drain and source of the transistor in the substrate when charging according to an embodiment of the present disclosure
  • Figure 4d is a second graph showing the current between the drain and source of the transistor in the substrate when discharging according to an embodiment of the present disclosure.
  • Figure 4c and Figure 4d are both graphs of the drain-source current using the equivalent circuit shown in Figure 3b.
  • the horizontal axis is the voltage Vg of the first gate electrode (unit: volt)
  • the vertical axis is the current Ids between the drain and the source (unit: ampere).
  • the embodiment of the present disclosure shows that when the transistor in the substrate is charging, the transistor forms a single gate structure, and the open-state current Ion changes greatly.
  • the embodiment of the present disclosure shows that when the transistor in the substrate is discharging, the transistor forms a double-gate structure, which can effectively control the open-state current Ion and avoid the impact of high current density on the transistor.
  • the substrate can accelerate the charging speed during charging and effectively reduce the leakage current I off during discharging.
  • FIG. 6 is a cross-sectional view of a transistor in a related art display substrate.
  • the transistor in the relevant display substrate can adopt a double-gate structure.
  • the transistor includes an active layer pattern 2, a first source-drain electrode 3, a first gate electrode 5, a second gate electrode, and an active layer pattern 2 arranged sequentially on a substrate 101.
  • the first gate electrode 5 and the second gate electrode 8 are disconnected and insulated from each other. Both the first gate electrode 5 and the second gate electrode 8 overlap with the orthographic projection of the active layer pattern 2 on the substrate 101.
  • the first source leakage current Both the electrode 3 and the second source and drain electrode 4 are electrically connected to the active layer pattern 2 .
  • the display substrate of the embodiment of the present disclosure uses the second sub-electrode as the second gate electrode so that the second sub-electrode is located on the side of the first sub-electrode close to the gate electrode.
  • the present disclosure implements The example shows that the substrate eliminates the distance between the second gate electrode and the second source-drain electrode. By controlling the distance between the second sub-electrode and the first gate electrode, the resistance of the active layer pattern conductor is adjusted to achieve the threshold voltage. Vth adjustment.
  • Figure 7a is a second structural schematic diagram of a transistor in a display substrate according to an embodiment of the present disclosure
  • Figure 7b is a second cross-sectional view of the display substrate according to an embodiment of the present disclosure.
  • Fig. 7b is a cross-sectional view of B-B' in Fig. 7a.
  • the transistor 100 in the display substrate of the embodiment of the present disclosure includes a buffer layer 1 disposed on a substrate 101, a semiconductor layer, a third An insulating layer 6 , a conductive layer and a second insulating layer 7 ;
  • the semiconductor layer includes the active layer pattern 2 ;
  • the conductive layer includes the first source-drain electrode 3 , the second source-drain electrode 4 and the first gate electrode 5 .
  • the first insulating layer 6 is provided with a first via hole 61 and a second via hole 62.
  • the first source and drain electrode 3 is electrically connected to the active layer pattern 2 through the first via hole 61.
  • the second source and drain electrode 4 includes interconnected The first sub-electrode 41, the second sub-electrode 42 and the third sub-electrode 43.
  • the first sub-electrode 41 is electrically connected to the active layer pattern 2 through the second via hole 62 .
  • the second sub-electrode 42 is located on the side of the first sub-electrode 41 close to the first gate electrode 5; the third sub-electrode 43 is located on the side of the first sub-electrode 41 away from the first gate electrode 5; the second sub-electrode 42 and the third sub-electrode 43 overlap with the orthographic projection of the active layer pattern 2 on the substrate 101, and the second sub-electrode 42 and the third sub-electrode 43 are separated from the active layer pattern 2 by the first insulating layer 6 and are not mutually exclusive. touch.
  • Figure 8a is a schematic diagram 3 of the structure of a transistor in a display substrate according to an embodiment of the disclosure
  • Figure 8b is a cross-sectional view 3 of the display substrate according to an embodiment of the disclosure.
  • Figure 8b is a cross-sectional view of C-C' in Figure 8a.
  • the transistor 100 in the display substrate of the embodiment of the present disclosure includes a buffer layer 1 disposed on a substrate 101, a semiconductor layer, a third An insulating layer 6 , a conductive layer and a second insulating layer 7 ;
  • the semiconductor layer includes the active layer pattern 2 ;
  • the conductive layer includes the first source-drain electrode 3 , the second source-drain electrode 4 and the first gate electrode 5 .
  • the first insulating layer 6 is provided with a first via hole 61 and a second via hole 62.
  • the first source and drain electrode 3 includes a fourth sub-electrode 31 and a fifth sub-electrode 32 connected to each other.
  • the fifth sub-electrode 32 is located on the fourth
  • the sub-electrode 31 is on the side away from the first gate electrode 5, the fourth sub-electrode 31 is electrically connected to the active layer pattern 2, the fifth sub-electrode 32 and the active layer pattern 2 overlap in the orthographic projection of the substrate 101, and through
  • the first insulating layers 6 are separated from each other and do not contact each other.
  • the second source and drain electrode 4 includes a first sub-electrode 41 and a second sub-electrode 42 that are connected to each other.
  • the first sub-electrode 41 is electrically connected to the active layer pattern 2 through the second via hole 62 .
  • the second sub-electrode 42 is located on the side of the first sub-electrode 41 close to the first gate electrode 5; the second sub-electrode 4 overlaps with the active layer pattern 2 in the orthographic projection of the substrate 101, and the second sub-electrode 42 overlaps with the active layer pattern 2.
  • the source layer patterns 2 are separated from each other by the first insulating layer 6 and do not contact each other.
  • Figure 9a is a schematic diagram 4 of the structure of a transistor in a display substrate according to an embodiment of the disclosure
  • Figure 9b is a cross-sectional view 4 of the display substrate according to an embodiment of the disclosure.
  • Fig. 9b is a cross-sectional view of D-D' in Fig. 9a.
  • the transistor 100 in the display substrate of the embodiment of the present disclosure includes a buffer layer 1 disposed on a substrate 101, a semiconductor layer, a third An insulating layer 6 , a conductive layer and a second insulating layer 7 ;
  • the semiconductor layer includes the active layer pattern 2 ;
  • the conductive layer includes the first source-drain electrode 3 , the second source-drain electrode 4 and the first gate electrode 5 .
  • a first via hole 61 and a second via hole 62 are provided in the first insulating layer 6 , and the first source and drain electrode 3 is electrically connected to the active layer pattern 2 through the first via hole 61 .
  • the second source and drain electrode 4 includes a first sub-electrode 41 and a second sub-electrode 42 that are connected to each other.
  • the first sub-electrode 41 is electrically connected to the active layer pattern 2 through the second via hole 62 , and the second sub-electrode 42 is located on the first
  • the sub-electrode 41 is close to the side of the first gate electrode 5, the second sub-electrode 42 and the active layer pattern 2 overlap in the orthographic projection of the substrate 101, and the second sub-electrode 42 and the active layer pattern 2 are separated by the first insulation Layers 6 are separated from each other and do not touch each other.
  • the display substrate of the present disclosure may be an LCD display substrate, a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate.
  • Figure 10 is a cross-sectional view of a display substrate according to an embodiment of the present disclosure.
  • the substrate includes: a substrate 101 and a first conductive layer, a buffer layer 1 , a semiconductor layer, and a first insulating layer 6 sequentially provided on the substrate 101 , the second conductive layer, the third insulating layer 9, the third conductive layer, the second insulating layer 7, the planarization layer 10, the fourth conductive layer, the fourth insulating layer 11 and the fifth conductive layer.
  • the substrate 101 may be made of transparent material, such as glass or quartz.
  • a first conductive layer is provided on the substrate 101 .
  • the first conductive layer includes a signal line 20 and a light-shielding layer 21 .
  • the signal line 20 may be a data signal line and is connected to the first source.
  • the drain electrode 3 is electrically connected, and the signal line 20 is used to provide a driving signal to the first source and drain electrode 3; the orthographic projection of the light-shielding layer 21 and the active layer pattern 2 on the substrate 101 overlaps, and the light-shielding layer 21 is used to block light.
  • the materials of the signal line 20 and the light-shielding layer 21 can adopt a laminated structure of molybdenum (Mo), aluminum (Al) and aluminum (Al), or a laminated structure of molybdenum-niobium alloy (MoNb) and copper (Cu), Or a laminated structure of molybdenum niobium alloy (MTD) and copper (Cu), or a laminated structure of molybdenum niobium alloy (MoNb), copper (Cu) and molybdenum niobium alloy (MTD), the signal line 20 and the light shielding layer 21
  • the thickness can be 1000 ⁇ 10000A.
  • the buffer layer 1 is provided on the side of the first conductive layer away from the substrate 101 and covers the signal line 20 and the light-shielding layer 21 .
  • a third via hole is provided in the buffer layer 1 50.
  • the first source and drain electrode 3 is electrically connected to the signal line 20 through the third via hole 50.
  • the material of the buffer layer 1 may be silicon oxide compound (SiOx), or a stacked structure of silicon nitride compound (SiNx) and oxygen silicon compound (SiOx).
  • the thickness of the buffer layer 1 may be 100 nm to 700 nm.
  • the semiconductor layer is disposed on the side of the buffer layer 1 away from the substrate 101 .
  • the semiconductor layer includes an active layer pattern 2 , and the thickness of the active layer pattern 2 may be 10 nm to 80 nm.
  • the first insulating layer 6 is disposed on the side of the semiconductor layer away from the substrate 101 and covers the active layer pattern 2 , and a first via hole is disposed in the first insulating layer 6 61 and the second via hole 62, the material of the first insulating layer 6 can be silicon oxide compound (SiOx), and the thickness of the first insulating layer 6 can be 600A to 2000A.
  • the first via hole 61 and the third via hole 50 in the buffer layer 1 can be prepared through the same preparation process.
  • the second conductive layer is disposed on the side of the first insulating layer 6 away from the substrate 101 .
  • the second conductive layer includes a first gate electrode 5 .
  • the first gate electrode 5 is connected to the active
  • the orthographic projection of the layer pattern 2 on the substrate 101 overlaps, and the first gate electrode 5 and the active layer pattern 2 are separated from each other by the first insulating layer 6 and do not contact each other; the material of the first gate electrode 5 can be molybdenum.
  • the third insulating layer 9 is disposed on the side of the second conductive layer away from the substrate 101 and covers the first gate electrode 5 .
  • the material of the third insulating layer 9 can be silicon.
  • the thickness of the third insulating layer 9 may be 200 nm to 400 nm.
  • the third conductive layer is provided on the side of the third insulating layer 9 away from the substrate 101, and the third conductive layer includes the first source and drain electrode 3 and the second source and drain electrode 4,
  • the first source and drain electrode 3 is electrically connected to the active layer pattern 2 through the first via hole 61;
  • the second source and drain electrode 4 includes a first sub-electrode 41, a second sub-electrode 42 and a third sub-electrode 43 that are connected to each other.
  • the second sub-electrode 42 is located on the side of the first sub-electrode 41 close to the first gate electrode 5, and the third sub-electrode 43 is located on the side of the first sub-electrode 41 away from the first gate electrode 5; the second sub-electrode 42 and the third sub-electrode 43 Both of them overlap with the orthographic projection of the active layer pattern 2 on the substrate 101, and the second sub-electrode 42 and the third sub-electrode 43 are mutually connected with the active layer pattern 2 through the first insulating layer 6 and the third insulating layer 9.
  • the first sub-electrode 41 is electrically connected to the active layer pattern 2 through the second via hole 62;
  • the materials of the first source-drain electrode 3 and the second source-drain electrode 4 can be molybdenum (Mo), A laminated structure of aluminum (Al) and aluminum (Al), or a laminated structure of molybdenum niobium alloy (MoNb) and copper (Cu), or a laminated structure of molybdenum niobium alloy (MTD) and copper (Cu),
  • the thickness of the first source-drain electrode 3 and the second source-drain electrode 4 may be 1000-10000A.
  • the first source and drain electrode 3, the second source and drain electrode 4, the first gate electrode 5 and the active layer pattern 2 constitute a transistor.
  • the second insulating layer 7 is disposed on the side of the third conductive layer away from the substrate 101 and covers the first source-drain electrode 3 and the second source-drain electrode 4 .
  • the material of the insulating layer 7 can be silicon oxide compound (SiOx), or a stacked structure of silicon nitride compound (SiNx) and oxygen silicon compound (SiOx).
  • the thickness of the second insulating layer 7 can be 200 nm to 400 nm.
  • the planarization layer 10 is provided on the side of the second insulating layer 7 away from the substrate 101 .
  • the material of the planarization layer 10 can be an organic material, and the thickness of the planarization layer 10 can be 2um ⁇ 3um.
  • the fourth conductive layer is disposed on the side of the planarization layer 10 away from the substrate 101 .
  • the fourth conductive layer includes a common electrode 30 .
  • the material of the common electrode 30 can be indium gallium zinc oxide. (IGZO) or indium zinc oxide (IZO), the thickness of the common electrode 30 may be 400A ⁇ 1000A.
  • the fourth insulating layer 11 is disposed on the side of the fourth conductive layer away from the substrate 101 and covers the common electrode 30 .
  • the material of the fourth insulating layer 11 can be a silicon oxide compound. (SiOx), or a stacked structure of silicon nitride compound (SiNx) and oxygen silicon compound (SiOx), the thickness of the fourth insulating layer 11 may be 1000A to 3000A.
  • the fifth conductive layer is disposed on the side of the fourth insulating layer 11 away from the substrate 101 .
  • the fifth conductive layer includes the pixel electrode 40 , the second insulating layer 7 , and the planarization layer 10
  • a fourth via hole 60 is provided in the fourth insulating layer 11 and the pixel electrode 40 is electrically connected to the second source and drain electrode 4 through the fourth via hole 60.
  • the material of the pixel electrode 40 can be indium tin oxide (ITO) or oxide. Indium zinc (IZO), the thickness of the pixel electrode 40 may be 40 nm to 135 nm.
  • embodiments of the present disclosure show that the first insulating layer in the substrate includes at least one insulating layer pattern, the insulating layer pattern covers part of the active layer pattern, and the insulating layer pattern does not cover part of the active layer pattern, that is, the insulating layer pattern and At least part of the active layer pattern has a non-overlapping area in the orthographic projection of the substrate, exposing at least part of the active layer pattern.
  • the first source-drain electrode, the first gate electrode and the second source-drain electrode are all located away from the first insulating layer.
  • the first sub-electrodes of the first source-drain electrode and the second source-drain electrode are electrically connected to non-overlapping areas of the active layer pattern respectively.
  • the edge areas on both sides of the insulating layer pattern and the active layer pattern have non-overlapping areas in the orthographic projection of the substrate, exposing the edge areas on both sides of the active layer pattern, and the first source-drain electrode and the second source-drain electrode
  • the first sub-electrodes are electrically connected to the edge areas on both sides of the active layer pattern respectively; the preparation process of the display substrate of the present disclosure reduces the preparation process of forming the first via hole and the second via hole in the first insulating layer, simplifying The preparation process reduces production costs.
  • the first gate electrode and the first source and drain electrode in the display substrate of the present disclosure can be made of the same material through the same preparation process; the second source and drain electrode can be integrally formed with the pixel electrode, and the second source and drain electrode can be integrally formed with the pixel electrode.
  • the source and drain electrodes and the pixel electrodes can be made of the same material through the same preparation process; thereby simplifying the preparation process of the display substrate of the present disclosure and reducing the production cost.
  • the embodiments of the present disclosure show that the first source and drain electrodes in the substrate can be integrally formed with the active layer pattern to form a film structure.
  • the first source and drain electrodes and the active layer pattern can be made of the same material and pass through the same layer.
  • Preparation process; the second source drain electrode can be integrally formed with the pixel electrode, and the second source drain electrode and the pixel electrode can be made of the same material through the same preparation process; thereby simplifying the preparation process of the display substrate of the present disclosure, Reduced production costs.
  • embodiments of the present disclosure show that the first insulating layer in the substrate includes at least one insulating layer pattern, the insulating layer pattern covers part of the active layer pattern, and the insulating layer pattern does not cover part of the active layer pattern, that is, the insulating layer pattern and There is a non-overlapping area in the orthographic projection of at least part of the active layer pattern on the substrate, exposing at least part of the active layer pattern.
  • the first source-drain electrode, the first gate electrode and the second source-drain electrode are all located on the side of the first insulating layer away from the substrate.
  • the first sub-electrodes of the first source-drain electrode and the second source-drain electrode are respectively connected with the active layer pattern.
  • the non-overlapping areas are electrically connected.
  • the first gate electrode and the first source and drain electrode can be made of the same material through the same preparation process; the second source and drain electrode can be integrally formed with the pixel electrode, and the second source and drain electrode and the pixel electrode can be made of the same material and made of the same process. It is prepared by the preparation process; thereby simplifying the preparation process of the display substrate of the present disclosure and reducing the production cost.
  • embodiments of the present disclosure show that the first insulating layer in the substrate includes at least one insulating layer pattern, the insulating layer pattern covers part of the active layer pattern, and the insulating layer pattern does not cover part of the active layer pattern, that is, the insulating layer pattern and At least part of the active layer pattern has a non-overlapping area in the orthographic projection of the substrate, exposing at least part of the active layer pattern.
  • the first source-drain electrode, the first gate electrode and the second source-drain electrode are all located away from the first insulating layer.
  • the first source and drain electrodes can be integrally formed with the active layer pattern to form a film structure, and the first source and drain electrodes and the active layer pattern can be made of the same material through the same preparation process;
  • the second The source and drain electrodes can be integrally formed with the pixel electrodes, and the second source and drain electrodes and the pixel electrodes can be made of the same material through the same preparation process; thereby simplifying the preparation process of the display substrate of the present disclosure and reducing production costs.
  • the embodiments of the present disclosure show that the buffer layer can be eliminated in the substrate.
  • the embodiments of the present disclosure show that the first source and drain electrodes in the substrate can be integrally formed with the active layer pattern to form a film structure.
  • the first source and drain electrodes The same material as the active layer pattern can be prepared through the same preparation process; the signal line is located on the side of the first source and drain electrode close to the substrate, and the signal line can be in electrical contact with the first source and drain electrode; the second source and drain electrode is The pixel electrodes can be made of the same material through the same preparation process.
  • the preparation process of the display substrate in the embodiment of the present disclosure is: first forming a signal line on the substrate, and then forming a semiconductor film on the signal line, so that the semiconductor film forms an integrated first source and drain electrode and an active layer pattern, and the third A source and drain electrode is located on the side of the signal line away from the substrate, and the first source and drain electrode is in electrical contact with the signal line. Finally, a first insulating layer is formed on the side of the first source and drain electrode and the active layer pattern away from the substrate. An insulating layer forms a first gate electrode and an integrally formed second source-drain electrode and pixel electrode on a side away from the substrate. The second source-drain electrode is electrically connected to the active layer pattern. This simplifies the preparation process of the display substrate of the present disclosure and reduces the production cost.
  • the embodiments of the present disclosure show that the buffer layer can be eliminated in the substrate.
  • the embodiments of the present disclosure show that the first source and drain electrodes in the substrate can be integrally formed with the active layer pattern to form a film structure.
  • the first source and drain electrodes can be made of the same material through the same preparation process; the signal line is located on the side of the first source and drain electrode away from the substrate, and the signal line can be in electrical contact with the first source and drain electrode; the second source and drain electrode is The pixel electrodes can be made of the same material through the same preparation process.
  • the embodiment of the present disclosure shows that the preparation process of the substrate is as follows: first forming a semiconductor film on the substrate, so that the semiconductor film forms an integrated first source and drain electrode and an active layer pattern, and then placing the first source and drain electrode on the side away from the substrate. Form a signal line and electrically contact the signal line with the first source and drain electrode. Finally, form a first insulating layer on the side of the signal line away from the substrate, and form a first gate electrode on the side of the first insulating layer away from the substrate. The second source-drain electrode and the pixel electrode are formed, and the second source-drain electrode is electrically connected to the active layer pattern. This simplifies the preparation process of the display substrate of the present disclosure and reduces the production cost.
  • the embodiment of the present disclosure shows that the substrate electrically contacts the signal line and the first source-drain electrode, thereby reducing the capacitance between the signal line and the first source-drain electrode, ensuring the stability of the transistor operation and reducing power consumption.
  • the present disclosure also provides a method for preparing a display substrate, including:
  • first source and drain electrode on the substrate so that at least part of the first source and drain electrode is electrically connected to the active layer pattern
  • a first gate electrode is formed on the side of the active layer pattern away from the substrate, so that the first gate electrode and the active layer pattern overlap in the orthographic projection of the substrate and do not contact each other. ;
  • a second source-drain electrode is formed on the side of the active layer pattern away from the substrate.
  • the second source-drain electrode includes a first sub-electrode and a second sub-electrode connected to each other.
  • the second sub-electrode is located on the side of the active layer pattern away from the substrate.
  • the first sub-electrode is close to the side of the first gate electrode, the first sub-electrode is electrically connected to the active layer pattern, and the second sub-electrode and the active layer pattern are on the side of the substrate. Orthographic projections overlap and do not touch each other.
  • the present disclosure also provides a display device, including the display substrate of the foregoing exemplary embodiment.
  • the display device can be any product or component with a display function such as a mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame or navigator.

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Abstract

一种显示基板及其制备方法、显示装置，显示基板包括：衬底（101）以及设置在衬底（101）上的至少一个晶体管（100）；晶体管（100）包括：有源层图案（2），设置在衬底（101）上；第一源漏电极（3），设置在衬底（101）上，第一源漏电极（3）与有源层图案（2）电连接；第一栅电极（5），设置在有源层图案（2）远离衬底（101）一侧，第一栅电极（5）和有源层图案（2）在衬底（101）的正投影存在交叠，且互不接触；第二源漏电极（4），设置在有源层图案（2）远离衬底（101）一侧，第二源漏电极（4）包括互相连接的第一子电极（41）和第二子电极（42），第二子电极（42）位于第一子电极（41）靠近第一栅电极（5）一侧，第一子电极（41）与有源层图案（2）电连接，第二子电极（42）和有源层图案（2）在衬底（101）的正投影存在交叠，且互不接触。

Description

显示基板及其制备方法、显示装置 技术领域
本公开涉及但不限于显示技术领域，具体涉及一种显示基板及其制备方法、显示装置。
背景技术
近年来，低温多晶硅薄膜晶体管(英文：Low Temperature Poly-Silicon Thin Film Transistor；简称：LTPS TFT)和氧化物(Oxide)薄膜晶体管在显示行业备受关注，各具优势，不分伯仲。低温多晶硅薄膜晶体管具有迁移率高、充电快的优势。铟镓锌氧化物(In-Ga-Zn-Oxide，IGZO)薄膜晶体管(即IGZO-TFT)，由于其有源层(IGZO)具有较高的载流子迁移率，以及较高的热学性能、化学稳定性，成为人们的研究热点。制备高性能、高稳定性的IGZO薄膜晶体管成为各厂商研究的重点和难点。
随着产品像素密度和刷新率的提高，数据线延伸方向的寄生电容成为制约显示面板像素密度升高和刷新率提升的最重要的因素。同时，像素电路中晶体管的尺寸和电流是影响驱动电路电容和功耗的关键因素。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开提供了一种显示基板，包括：衬底以及设置在所述衬底上的至少一个晶体管；所述晶体管包括：
有源层图案，设置在所述衬底上；
第一源漏电极，设置在所述衬底上，所述第一源漏电极与所述有源层图案电连接；
第一栅电极，设置在所述有源层图案远离所述衬底一侧，所述第一栅电极和所述有源层图案在所述衬底的正投影存在交叠，且互不接触；
第二源漏电极，设置在所述有源层图案远离所述衬底一侧，所述第二源漏电极包括互相连接的第一子电极和第二子电极，所述第二子电极位于所述第一子电极靠近所述第一栅电极一侧，所述第一子电极与所述有源层图案电连接，所述第二子电极和所述有源层图案在所述衬底的正投影存在交叠，且互不接触。
在示例性实施例中，所述第二源漏电极还包括第三子电极，所述第三子电极位于所述第一子电极远离所述第一栅电极一侧，且所述第三子电极和所述有源层图案在所述衬底的正投影存在交叠，且互不接触。
在示例性实施例中，所述第一子电极和所述第二子电极一体成型。
在示例性实施例中，所述第一源漏电极包括互相连接的第四子电极和第五子电极，所述第五子电极位于所述第四子电极远离所述第一栅电极一侧，所述第四子电极与所述有源层图案电连接，所述第五子电极和所述有源层图案在所述衬底的正投影存在交叠，且互不接触。
在示例性实施例中，所述晶体管还包括第一绝缘层，所述第一绝缘层位于所述有源层图案与所述第一栅电极之间，所述第一绝缘层将所述有源层图案覆盖，所述第一源漏电极、所述第一栅电极和所述第二源漏电极均位于所述第一绝缘层远离所述衬底一侧，所述第一绝缘层中设置有第一过孔和第二过孔，所述第一源漏电极通过所述第一过孔与所述有源层图案电连接，所述第二源漏电极通过所述第二过孔与所述有源层图案电连接。
在示例性实施例中，所述晶体管还包括第一绝缘层，所述第一绝缘层包括至少一个绝缘层图案，所述绝缘层图案覆盖部分所述有源层图案，且所述绝缘层图案与至少部分所述有源层图案在所述衬底的正投影存在不交叠区域，所述第一源漏电极、所述第一栅电极和所述第二源漏电极均位于所述第一绝缘层远离所述衬底一侧，所述第一源漏电极和所述第二源漏电极分别与所述有源层图案的不交叠区域电连接。
在示例性实施例中，还包括设置在所述晶体管远离所述衬底一侧的像素 电极，所述像素电极与所述第二源漏电极一体成型。
在示例性实施例中，所述第一源漏电极与所述有源层图案一体成型。
在示例性实施例中，还包括信号线，所述信号线与所述第一源漏电极电连接。
在示例性实施例中，所述信号线位于所述第一源漏电极与所述衬底之间，所述显示基板还包括缓冲层，所述缓冲层位于所述信号线与所述有源层图案之间，所述缓冲层中设置有第三过孔，所述第一源漏电极通过所述第三过孔与所述信号线电连接。
在示例性实施例中，所述第一源漏电极与所述有源层图案一体成型，所述信号线与所述第一源漏电极电接触，所述信号线位于所述第一源漏电极靠近所述衬底一侧，或者，所述信号线位于所述第一源漏电极远离所述衬底一侧。
在示例性实施例中，所述有源层图案的材料采用氧化物半导体。
在示例性实施例中，所述晶体管被配置为栅极驱动电路中的晶体管。
另一方面，本公开还提供了一种显示装置，包括前述的显示基板括。
另一方面，本公开还提供了一种显示基板的制备方法，包括：
在衬底上形成有源层图案；
在衬底上形成第一源漏电极，使至少部分所述第一源漏电极与所述有源层图案电连接；
在所述有源层图案远离所述衬底一侧形成第一栅电极，使所述第一栅电极和所述有源层图案在所述衬底的正投影存在交叠，且互不接触；
在所述有源层图案远离所述衬底一侧形成第二源漏电极，所述第二源漏电极包括互相连接的第一子电极和第二子电极，所述第二子电极位于所述第一子电极靠近所述第一栅电极一侧，所述第一子电极与所述有源层图案电连接，所述第二子电极和所述有源层图案在所述衬底的正投影存在交叠且互不接触。
在阅读并理解了附图和详细描述后，可以明白其它方面。
附图说明
附图用来提供对本申请技术方案的理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本申请的技术方案，并不构成对本申请技术方案的限制。
图1a为本公开实施例显示基板中晶体管的结构示意图一；
图1b为本公开实施例显示基板的剖视图一；
图2为本公开实施例显示基板中晶体管的电路符号；
图3a为本公开实施例显示基板中晶体管的等效电路图一；
图3b为本公开实施例显示基板中晶体管的等效电路图二；
图4a为本公开实施例显示基板中晶体管在充电时漏源极间电流的曲线图一；
图4b为本公开实施例显示基板中晶体管在放电时漏源极间电流的曲线图一；
图4c为本公开实施例显示基板中晶体管在充电时漏源极间电流的曲线图二；
图4d为本公开实施例显示基板中晶体管在放电时漏源极间电流的曲线图的曲线图二；
图5为相关技术显示基板中晶体管在电压下时漏源极间电流的曲线图；
图6为相关技术显示基板中晶体管的剖视图；
图7a为本公开实施例显示基板中晶体管的结构示意图二；
图7b为本公开实施例显示基板的剖视图二；
图8a为本公开实施例显示基板中晶体管的结构示意图三；
图8b为本公开实施例显示基板的剖视图三；
图9a为本公开实施例显示基板中晶体管的结构示意图四；
图9b为本公开实施例显示基板的剖视图四；
图10为本公开实施例显示基板的剖视图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括第一栅电极、第二源漏电极以及第一源漏电极这三个端子的元件。晶体管在第二源漏电极(第二源漏电极端子、漏区域或第二源漏电极)与第一源漏电极(第一源漏电极端子、源区域或第一源漏电极)之间具有沟道区域，并且电流能够流过第二源漏电极、沟道区域以及第一源漏电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为第二源漏电极、第二极可以为第一源漏电极，或者第一极可以为第一源漏电极、第二极可以为第二源漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“第一源漏电极”及“第二源漏电极”的功能有时互相调换。因此，在本说明书中，“第一源漏电极”和“第二源漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图5为相关技术显示基板中晶体管在电压下时漏源极间电流的曲线图。经本公开发明人的研究发现，晶体管在电压下容易发生晶体管负飘或DGS，导致驱动电路失效。图5中横轴为第一栅电极的电压Vg(单位：伏)，纵轴为漏源极间的电流Ids(单位：安)。如图5所示，晶体管失效前漏源极 间电流的曲线为a，晶体管失效后漏源极间电流的曲线为b。晶体管失效的原因为高压和高电流密度导致器件衰减。
本公开实施例提供了一种显示基板，包括：衬底以及设置在所述衬底上的至少一个晶体管；所述晶体管包括：
有源层图案，设置在所述衬底上；
有源层图案，设置在所述衬底上；
第一源漏电极，设置在所述衬底上，所述第一源漏电极与所述有源层图案电连接；
第一栅电极，设置在所述有源层图案远离所述衬底一侧，所述第一栅电极和所述有源层图案在所述衬底的正投影存在交叠，且互不接触；
第二源漏电极，设置在所述有源层图案远离所述衬底一侧，所述第二源漏电极包括互相连接的第一子电极和第二子电极，所述第二子电极位于所述第一子电极靠近所述第一栅电极一侧，所述第一子电极与所述有源层图案电连接，所述第二子电极和所述有源层图案在所述衬底的正投影存在交叠，且互不接触。
本公开实施例显示基板通过第二源漏电极的第一子电极与有源层图案电连接，第二源漏电极的第二子电极和有源层图案在衬底的正投影存在交叠且互不接触，一方面，在晶体管放电时，可以使第二源漏电极中的第一子电极被配置为源漏电极，第二源漏电极中的第二子电极被配置为第二栅电极，进而使晶体管形成双栅结构，有效降低漏电流I off，避免高电流密度对晶体管的冲击；另一方面，在晶体管充电时，可以使第二源漏电极中的第一子电极和第二子电极均被配置为源漏电极，进而使晶体管形成单栅结构，加快充电速度。
图1a为本公开实施例显示基板中晶体管的结构示意图一；图1b为本公开实施例显示基板的剖视图一。其中，图1b为图1a中A-A’的剖视图。在示例性实施例中，如图1a和图1b所示，在垂直于显示基板的方向上，本公开实施例显示基板可以包括衬底101以及设置在衬底101上的至少一个晶体管100，晶体管100包括设置在衬底101上的缓冲层1、半导体层、第一绝缘层 6、导电层以及第二绝缘层7；半导体层包括有源层图案2；导电层包括第一源漏电极3、第二源漏电极4以及第一栅电极5。在平行于显示基板的方向上，第一源漏电极3、第二源漏电极4以及第一栅电极5均沿着第二方向(例如方向Y)延伸，第一源漏电极3、第二源漏电极4以及第一栅电极5沿着第一方向(例如方向X)间隔排布，第一栅电极5位于第一源漏电极3和第二源漏电极4之间。其中，第一方向与第二方向不同，示例的，第一方向与第二方向垂直。
在示例性实施例中，晶体管100可以为氧化物(Oxide)薄膜晶体管，晶体管中的有源层为氧化物半导体材质，例如，晶体管中的有源层可以为铟镓锌氧化物(IGZO)。
在示例性实施例中，晶体管100可以作为栅极驱动电路、输入电路和工作电压电路等电路中的晶体管。
在示例性实施例中，如图1b所示，第一栅电极5与有源层图案2在衬底101的正投影存在交叠，且第一栅电极5与有源层图案2通过第一绝缘层6相互隔开，互不接触。
在示例性实施例中，如图1a和图1b所示，第一绝缘层6中设置有第一过孔61和第二过孔62，第一源漏电极3通过第一过孔61与有源层图案2电连接，第二源漏电极4包括互相连接的第一子电极41和第二子电极42。第二子电极42位于第一子电极41靠近第一栅电极5一侧；第二子电极42与有源层图案2在衬底101的正投影存在交叠，且第二子电极42与有源层图案2通过第一绝缘层6相互隔开，互不接触。第一子电极41通过第二过孔62与有源层图案2电连接。其中，第一绝缘层6还可以称为栅绝缘(GI)层。
在示例性实施例中，第一子电极41和第二子电极42可以一体成型，形成一层膜结构，第一子电极41和第二子电极42可以采用相同的材料通过同一制备工艺制备而成。
在示例性实施例中，如图1a和图1b所示，第二源漏电极4还包括第三子电极43，第三子电极43位于第一子电极41远离第一栅电极5一侧，且第三子电极43和有源层图案2在衬底101的正投影存在交叠，且通过第一绝缘 层6相互隔开，互不接触。
在示例性实施例中，如图1a和图1b所示，第一源漏电极3包括互相连接的第四子电极31和第五子电极32，第五子电极32位于第四子电极31远离第一栅电极5一侧，第四子电极31与有源层图案2电连接，第五子电极32和有源层图案2在衬底101的正投影存在交叠，且通过第一绝缘层6相互隔开，互不接触。其中，第四子电极31和第五子电极32可以一体成型，形成一层膜结构，第四子电极31和第五子电极32可以采用相同的材料通过同一制备工艺制备而成。
图2为本公开实施例显示基板中晶体管的电路符号。在示例性实施例中，如图2所示，G为栅极，S为源极，D为漏极。当栅源电压Vgs(即，Vg-Vs)的值大于阈值电压Vth时，晶体管截止，此时在漏源之间存在漏电流I off。当栅源电压Vgs低于阈值电压Vth时，晶体管工作，源极电压高于漏极电压，空穴作为载流子从源极通过沟道区域流向漏极。
图3a为本公开实施例显示基板中晶体管的等效电路图一；图3b为本公开实施例显示基板中晶体管的等效电路图二。在示例性实施例中，如图3a和图3b所示，本公开实施例显示基板中晶体管在放电时，可以在晶体管的第一栅电极5施加高电位电压Vg，可以在晶体管的第二源漏电极4施加高电位电压Vd，在晶体管的第一源漏电极3施加低电位电压Vs，使第二源漏电极4中的第一子电极41被配置为源漏电极，使第二源漏电极4中的第二子电极42被配置为第二栅电极，进而使晶体管形成双栅结构；本公开实施例显示基板中晶体管在充电时，可以在晶体管的第一栅电极5施加高电位电压Vg，可以在晶体管的第二源漏电极4施加低电位电压Vd，在晶体管的第一源漏电极3施加高电位电压Vs，使第二源漏电极4中的第一子电极41和第二子电极42均被配置为源漏电极，进而使晶体管形成单栅结构。
在示例性实施例中，本公开实施例显示基板中晶体管在放电时漏源极间的电流Ids的计算公式为：
Ids＝μ×CoxW 1/L 1×[(0-Vth 1)×Vm-1/2×Vm 2]＝μ×CoxW 2/L 2×[(Vgs-Vm)×(Vd-Vm)-1/2×(Vd-Vm) 2]
在示例性实施例中，本公开实施例显示基板中晶体管在充电时漏源极间的电流Ids的计算公式为：
Ids＝μ×CoxW 1/L 1×[(Vd-Vm-Vth 1)×(Vd-Vm)-1/2(Vd-Vm) 2]＝μ×Cox×W 2/L 2×[(Vgs-Vth 2)×Vm-1/2×Vm 2]
其中，Vm为相关变量，和具体的晶体管设计相关，通过上述公式，可以具体计算；W 1为第一栅电极5在第一方向(例如方向X)上的长度；L 1为第一栅电极5在第二方向(例如方向Y)上的长度；Vth 1为第一栅电极5的阈值电压；W 2为第二栅电极在第一方向(例如方向X)上的长度；L 2为第二栅电极在第二方向(例如方向Y)上的长度；Vth 2为第二栅电极的阈值电压。
图4a为本公开实施例显示基板中晶体管在充电时漏源极间电流的曲线图一；图4b为本公开实施例显示基板中晶体管在放电时漏源极间电流的曲线图一。其中，图4a和图4b均为采用图3a所示等效电路的漏源极间的电流曲线图。图4a和图4b中横轴为第一栅电极的电压Vg(单位：伏)，纵轴为漏源极间的电流Ids(单位：安)。如图4a所示，本公开实施例显示基板中晶体管在充电时，晶体管形成单栅结构，开态电流Ion变化较大。如图4b所示，本公开实施例显示基板中晶体管在放电时，晶体管形成双栅结构，可以有效的控制开态电流Ion，避免高电流密度对晶体管的冲击。本公开实施例显示基板能够在充电时，加快充电速度；在放电时，有效降低漏电流I off。本公开实施例显示基板若将开启电压调整到0.5V以上，晶体管可以实现反向关断。
图4c为本公开实施例显示基板中晶体管在充电时漏源极间电流的曲线图二；图4d为本公开实施例显示基板中晶体管在放电时漏源极间电流的曲线图的曲线图二。其中，图4c和图4d均为采用图3b所示等效电路的漏源极间电流的曲线图。图4c和图4d中横轴为第一栅电极的电压Vg(单位：伏)，纵轴为漏源极间的电流Ids(单位：安)。如图4c所示，本公开实施例显示基板中晶体管在充电时，晶体管形成单栅结构，开态电流Ion变化较大。如图4d所示，本公开实施例显示基板中晶体管在放电时，晶体管形成双栅结构，可以有效的控制开态电流Ion，避免高电流密度对晶体管的冲击。本公开实施例显示基板能够在充电时，加快充电速度；在放电时，有效降低漏电 流I off。
图6为相关技术显示基板中晶体管的剖视图。如图6所示，相关显示基板中晶体管可以采用双栅结构，该晶体管包括依次设置在衬底101上的有源层图案2以及第一源漏电极3、第一栅电极5、第二栅电极8、第二源漏电极4。第一栅电极5和第二栅电极8相互断开且绝缘，第一栅电极5和第二栅电极8均与有源层图案2在衬底101的正投影存在交叠，第一源漏电极3和第二源漏电极4均与有源层图案2电连接。
本公开实施例显示基板通过将第二子电极作为第二栅电极，使第二子电极位于第一子电极靠近栅极一侧，相对于相关技术显示基板中晶体管的双栅结构，本公开实施例显示基板消除了第二栅电极与第二源漏电极之间的距离，通过控制第二子电极与第一栅电极之间的距离，调整有源层图案导体化的电阻，实现对阈值电压Vth的调整。
图7a为本公开实施例显示基板中晶体管的结构示意图二；图7b为本公开实施例显示基板的剖视图二。其中，图7b为图7a中B-B’的剖视图。在示例性实施例中，如图7a和图7b所示，在垂直于显示基板的方向上，本公开实施例显示基板中晶体管100包括设置在衬底101上的缓冲层1、半导体层、第一绝缘层6、导电层以及第二绝缘层7；半导体层包括有源层图案2；导电层包括第一源漏电极3、第二源漏电极4以及第一栅电极5。第一栅电极5与有源层图案2在衬底101的正投影存在交叠，且第一栅电极5与有源层图案2通过第一绝缘层6相互隔开，互不接触。第一绝缘层6中设置有第一过孔61和第二过孔62，第一源漏电极3通过第一过孔61与有源层图案2电连接，第二源漏电极4包括互相连接的第一子电极41、第二子电极42和第三子电极43。第一子电极41通过第二过孔62与有源层图案2电连接。第二子电极42位于第一子电极41靠近第一栅电极5一侧；第三子电极43位于第一子电极41远离第一栅电极5一侧；第二子电极42和第三子电极43均与有源层图案2在衬底101的正投影存在交叠，且第二子电极42和第三子电极43均与有源层图案2通过第一绝缘层6相互隔开，互不接触。
图8a为本公开实施例显示基板中晶体管的结构示意图三；图8b为本公开实施例显示基板的剖视图三。其中，图8b为图8a中C-C’的剖视图。在示 例性实施例中，如图8a和图8b所示，在垂直于显示基板的方向上，本公开实施例显示基板中晶体管100包括设置在衬底101上的缓冲层1、半导体层、第一绝缘层6、导电层以及第二绝缘层7；半导体层包括有源层图案2；导电层包括第一源漏电极3、第二源漏电极4以及第一栅电极5。第一栅电极5与有源层图案2在衬底101的正投影存在交叠，且第一栅电极5与有源层图案2通过第一绝缘层6相互隔开，互不接触。第一绝缘层6中设置有第一过孔61和第二过孔62，第一源漏电极3包括互相连接的第四子电极31和第五子电极32，第五子电极32位于第四子电极31远离第一栅电极5一侧，第四子电极31与有源层图案2电连接，第五子电极32和有源层图案2在衬底101的正投影存在交叠，且通过第一绝缘层6相互隔开，互不接触。第二源漏电极4包括互相连接的第一子电极41和第二子电极42。第一子电极41通过第二过孔62与有源层图案2电连接。第二子电极42位于第一子电极41靠近第一栅电极5一侧；第二子电极4与有源层图案2在衬底101的正投影存在交叠，且第二子电极42与有源层图案2通过第一绝缘层6相互隔开，互不接触。
图9a为本公开实施例显示基板中晶体管的结构示意图四；图9b为本公开实施例显示基板的剖视图四。其中，图9b为图9a中D-D’的剖视图。在示例性实施例中，如图9a和图9b所示，在垂直于显示基板的方向上，本公开实施例显示基板中晶体管100包括设置在衬底101上的缓冲层1、半导体层、第一绝缘层6、导电层以及第二绝缘层7；半导体层包括有源层图案2；导电层包括第一源漏电极3、第二源漏电极4以及第一栅电极5。第一栅电极5与有源层图案2在衬底101的正投影存在交叠，且第一栅电极5与有源层图案2通过第一绝缘层6相互隔开，互不接触。第一绝缘层6中设置有第一过孔61和第二过孔62，第一源漏电极3通过第一过孔61与有源层图案2电连接。第二源漏电极4包括互相连接的第一子电极41和第二子电极42，第一子电极41通过第二过孔62与有源层图案2电连接，第二子电极42位于第一子电极41靠近第一栅电极5一侧，第二子电极42与有源层图案2在衬底101的正投影存在交叠，且第二子电极42与有源层图案2通过第一绝缘层6相互隔开，互不接触。
在示例性实施例中，本公开实施例显示基板可以为LCD显示基板、柔性 OLED显示基板、QLED显示基板、Micro-LED显示基板、或者Mini-LED显示基板。
图10为本公开实施例显示基板的剖视图。以本公开实施例显示基板为LCD显示基板为例。在示例性实施例中，如图10所示，本公开实施例显示基板包括：衬底101以及依次设置在衬底101上的第一导电层、缓冲层1、半导体层、第一绝缘层6、第二导电层、第三绝缘层9、第三导电层、第二绝缘层7、平坦化层10、第四导电层、第四绝缘层11以及第五导电层。
在示例性实施例中，如图10所示，衬底101可以采用透明材料，例如玻璃或石英。
在示例性实施例中，如图10所示，第一导电层设置在衬底101上，第一导电层包括信号线20和遮光层21，信号线20可以为数据信号线，与第一源漏电极3电连接，信号线20用于向第一源漏电极3提供驱动信号；遮光层21与有源层图案2在衬底101上的正投影具有交叠，遮光层21用于遮挡光线；信号线20和遮光层21的材料均可以采用钼(Mo)、铝(Al)和铝(Al)的叠层结构，或者，钼铌合金(MoNb)和铜(Cu)的叠层结构，或者，钼铌合金(MTD)和铜(Cu)的叠层结构，或者，钼铌合金(MoNb)、铜(Cu)和钼铌合金(MTD)的叠层结构，信号线20和遮光层21的厚度可以为1000～10000A。
在示例性实施例中，如图10所示，缓冲层1设置在第一导电层远离衬底101一侧，并将信号线20和遮光层21覆盖，缓冲层1中设置有第三过孔50，第一源漏电极3通过第三过孔50与信号线20电连接。缓冲层1的材料可以采用硅氧化合物(SiOx)，或者，硅氮化合物(SiNx)和氧硅化合物(SiOx)的叠层结构，缓冲层1的厚度可以为100nm～700nm。
在示例性实施例中，如图10所示，半导体层设置在缓冲层1远离衬底101一侧，半导体层包括有源层图案2，有源层图案2的厚度可以为10nm～80nm。
在示例性实施例中，如图10所示，第一绝缘层6设置在半导体层远离衬底101一侧，并将有源层图案2覆盖，第一绝缘层6中设置有第一过孔61 和第二过孔62，第一绝缘层6的材料可以采用硅氧化合物(SiOx)，第一绝缘层6的厚度可以为600A～2000A。其中，第一过孔61可以与缓冲层1中的第三过孔50通过同一制备工艺制备而成。
在示例性实施例中，如图10所示，第二导电层设置在第一绝缘层6远离衬底101一侧，第二导电层包括第一栅电极5，第一栅电极5与有源层图案2在衬底101的正投影存在交叠，且第一栅电极5与有源层图案2通过第一绝缘层6相互隔开，互不接触；第一栅电极5的材料可以采用钼铌合金(MoNb)和铜(Cu)的叠层结构，或者，钼铌合金(MTD)和铜(Cu)的叠层结构，或者，钼铌合金(MoNb)、铜(Cu)和钼铌合金(MTD)的叠层结构；第一栅电极5的厚度可以为200nm～1200nm。
在示例性实施例中，如图10所示，第三绝缘层9设置在第二导电层远离衬底101一侧，并将第一栅电极5覆盖，第三绝缘层9的材料可以采用硅氧化合物(SiOx)，或者，硅氮化合物(SiNx)和氧硅化合物(SiOx)的叠层结构，第三绝缘层9的厚度可以为200nm～400nm。
在示例性实施例中，如图10所示，第三导电层设置在第三绝缘层9远离衬底101一侧，第三导电层包括第一源漏电极3和第二源漏电极4，第一源漏电极3通过第一过孔61与有源层图案2电连接；第二源漏电极4包括互相连接的第一子电极41、第二子电极42和第三子电极43，第二子电极42位于第一子电极41靠近第一栅电极5一侧，第三子电极43位于第一子电极41远离第一栅电极5一侧；第二子电极42和第三子电极43均与有源层图案2在衬底101的正投影存在交叠，且第二子电极42和第三子电极43均与有源层图案2通过第一绝缘层6和第三绝缘层9相互隔开，互不接触；第一子电极41通过第二过孔62与有源层图案2电连接；第一源漏电极3以及第二源漏电极4的材料均可以采用钼(Mo)、铝(Al)和铝(Al)的叠层结构，或者，钼铌合金(MoNb)和铜(Cu)的叠层结构，或者，钼铌合金(MTD)和铜(Cu)的叠层结构，或者，钼铌合金(MoNb)、铜(Cu)和钼铌合金(MTD)的叠层结构，第一源漏电极3和第二源漏电极4的厚度可以为1000～10000A。其中，第一源漏电极3、第二源漏电极4、第一栅极5和有源层图案2构成晶体管。
在示例性实施例中，如图10所示，第二绝缘层7设置在第三导电层远离衬底101一侧，并将第一源漏电极3和第二源漏电极4覆盖，第二绝缘层7的材料可以采用硅氧化合物(SiOx)，或者，硅氮化合物(SiNx)和氧硅化合物(SiOx)的叠层结构，第二绝缘层7的厚度可以为200nm～400nm。
在示例性实施例中，如图10所示，平坦化层10设置在第二绝缘层7远离衬底101一侧，平坦化层10的材料可以采用有机材质，平坦化层10的厚度可以为2um～3um。
在示例性实施例中，如图10所示，第四导电层设置在平坦化层10远离衬底101一侧，第四导电层包括公共电极30，公共电极30的材料可以采用铟镓锌氧化物(IGZO)或氧化铟锌(IZO)，公共电极30的厚度可以为400A～1000A。
在示例性实施例中，如图10所示，第四绝缘层11设置在第四导电层远离衬底101一侧，并将公共电极30覆盖，第四绝缘层11的材料可以采用硅氧化合物(SiOx)，或者，硅氮化合物(SiNx)和氧硅化合物(SiOx)的叠层结构，第四绝缘层11的厚度可以为1000A～3000A。
在示例性实施例中，如图10所示，第五导电层设置在第四绝缘层11远离衬底101一侧，第五导电层包括像素电极40，第二绝缘层7、平坦化层10和第四绝缘层11中均设置有第四过孔60，像素电极40通过第四过孔60与第二源漏电极4电连接，像素电极40的材料可以采用氧化铟锡(ITO)或氧化铟锌(IZO)，像素电极40的厚度可以为40nm～135nm。
在一些实施例中，本公开实施例显示基板中第一绝缘层包括至少一个绝缘层图案，绝缘层图案覆盖部分有源层图案，绝缘层图案没有覆盖部分有源层图案，即绝缘层图案与至少部分有源层图案在衬底的正投影存在不交叠区域，将至少部分有源层图案暴露，第一源漏电极、第一栅电极和第二源漏电极均位于第一绝缘层远离衬底一侧，第一源漏电极和第二源漏电极的第一子电极分别与有源层图案的不交叠区域电连接。例如，绝缘层图案与有源层图案两侧的边缘区域在衬底的正投影存在不交叠区域，将有源层图案两侧的边缘区域暴露，第一源漏电极和第二源漏电极的第一子电极分别与有源层图案两侧的边缘区域电连接；使本公开显示基板的制备过程减少在第一绝缘层中 形成第一过孔和第二过孔的制备工艺，简化了制备工艺，降低了生产成本。
在一些实施例中，本公开实施例显示基板中第一栅电极可以与第一源漏电极采用相同的材料通过同一制备工艺制备而成；第二源漏电极可以与像素电极一体成型，第二源漏电极与像素电极可以采用相同的材料通过同一制备工艺制备而成；从而简化了本公开显示基板的制备工艺，降低了生产成本。
在一些实施例中，本公开实施例显示基板中第一源漏电极可以与有源层图案一体成型，形成一层膜结构，第一源漏电极与有源层图案可以采用相同的材料通过同一制备工艺制备而成；第二源漏电极可以与像素电极一体成型，第二源漏电极与像素电极可以采用相同的材料通过同一制备工艺制备而成；从而简化了本公开显示基板的制备工艺，降低了生产成本。
在一些实施例中，本公开实施例显示基板中第一绝缘层包括至少一个绝缘层图案，绝缘层图案覆盖部分有源层图案，绝缘层图案没有覆盖部分有源层图案，即绝缘层图案与至少部分有源层图案在衬底的正投影存在不交叠区域，将至少部分有源层图案暴露。第一源漏电极、第一栅电极和第二源漏电极均位于第一绝缘层远离衬底一侧，第一源漏电极和第二源漏电极的第一子电极分别与有源层图案的不交叠区域电连接。第一栅电极可以与第一源漏电极采用相同的材料通过同一制备工艺制备而成；第二源漏电极可以与像素电极一体成型，第二源漏电极与像素电极可以采用相同的材料通过同一制备工艺制备而成；从而简化了本公开显示基板的制备工艺，降低了生产成本。
在一些实施例中，本公开实施例显示基板中第一绝缘层包括至少一个绝缘层图案，绝缘层图案覆盖部分有源层图案，绝缘层图案没有覆盖部分有源层图案，即绝缘层图案与至少部分有源层图案在衬底的正投影存在不交叠区域，将至少部分有源层图案暴露，第一源漏电极、第一栅电极和第二源漏电极均位于第一绝缘层远离衬底一侧；第一源漏电极可以与有源层图案一体成型，形成一层膜结构，第一源漏电极与有源层图案可以采用相同的材料通过同一制备工艺制备而成；第二源漏电极可以与像素电极一体成型，第二源漏电极与像素电极可以采用相同的材料通过同一制备工艺制备而成；从而简化了本公开显示基板的制备工艺，降低了生产成本。
在一些实施例中，本公开实施例显示基板中可以取消缓冲层，本公开实 施例显示基板中第一源漏电极可以与有源层图案一体成型，形成一层膜结构，第一源漏电极与有源层图案可以采用相同的材料通过同一制备工艺制备而成；信号线位于第一源漏电极靠近衬底一侧，信号线可以与第一源漏电极电接触；第二源漏电极与像素电极可以采用相同的材料通过同一制备工艺制备而成。本公开实施例显示基板的制备过程为：先在衬底上形成信号线，然后在信号线上形成半导体薄膜，使半导体薄膜形成一体成型的第一源漏电极和有源层图案，并使第一源漏电极位于信号线远离衬底一侧，第一源漏电极与信号线电接触，最后，在第一源漏电极和有源层图案远离衬底一侧形成第一绝缘层、在第一绝缘层远离衬底一侧形成第一栅极以及一体成型的第二源漏电极和像素电极，第二源漏电极与有源层图案电连接。从而简化了本公开显示基板的制备工艺，降低了生产成本。
在一些实施例中，本公开实施例显示基板中可以取消缓冲层，本公开实施例显示基板中第一源漏电极可以与有源层图案一体成型，形成一层膜结构，第一源漏电极与有源层图案可以采用相同的材料通过同一制备工艺制备而成；信号线位于第一源漏电极远离衬底一侧，信号线可以与第一源漏电极电接触；第二源漏电极与像素电极可以采用相同的材料通过同一制备工艺制备而成。本公开实施例显示基板的制备过程为：先在衬底上形成半导体薄膜，使半导体薄膜形成一体成型的第一源漏电极和有源层图案，然后在第一源漏电极远离衬底一侧形成信号线，并使信号线与第一源漏电极电接触，最后，在信号线远离衬底一侧形成第一绝缘层、在第一绝缘层远离衬底一侧形成第一栅极以及一体成型的第二源漏电极和像素电极，第二源漏电极与有源层图案电连接。从而简化了本公开显示基板的制备工艺，降低了生产成本。
本公开实施例显示基板通过将信号线与第一源漏电极电接触，降低了信号线与第一源漏电极电之间的电容，保证晶体管工作的稳定性，降低功耗。
本公开还提供了一种显示基板的制备方法，包括：
在衬底上形成有源层图案；
在衬底上形成第一源漏电极，使至少部分所述第一源漏电极与所述有源层图案电连接；
在所述有源层图案远离所述衬底一侧形成第一栅电极，使所述第一栅电极和所述有源层图案在所述衬底的正投影存在交叠，且互不接触；
在所述有源层图案远离所述衬底一侧形成第二源漏电极，所述第二源漏电极包括互相连接的第一子电极和第二子电极，所述第二子电极位于所述第一子电极靠近所述第一栅电极一侧，所述第一子电极与所述有源层图案电连接，所述第二子电极和所述有源层图案在所述衬底的正投影存在交叠且互不接触。
本公开还提供了一种显示装置，包括前述示例性实施例的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本发明。任何所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (15)

  1. 一种显示基板，包括：衬底以及设置在所述衬底上的至少一个晶体管；所述晶体管包括：
    有源层图案，设置在所述衬底上；
    第一源漏电极，设置在所述衬底上，所述第一源漏电极与所述有源层图案电连接；
    第一栅电极，设置在所述有源层图案远离所述衬底一侧，所述第一栅电极和所述有源层图案在所述衬底的正投影存在交叠，且互不接触；
    第二源漏电极，设置在所述有源层图案远离所述衬底一侧，所述第二源漏电极包括互相连接的第一子电极和第二子电极，所述第二子电极位于所述第一子电极靠近所述第一栅电极一侧，所述第一子电极与所述有源层图案电连接，所述第二子电极和所述有源层图案在所述衬底的正投影存在交叠，且互不接触。
  2. 根据权利要求1所述的显示基板，其中，所述第二源漏电极还包括第三子电极，所述第三子电极位于所述第一子电极远离所述第一栅电极一侧，且所述第三子电极和所述有源层图案在所述衬底的正投影存在交叠，且互不接触。
  3. 根据权利要求1所述的显示基板，其中，所述第一子电极和所述第二子电极一体成型。
  4. 根据权利要求1所述的显示基板，其中，所述第一源漏电极包括互相连接的第四子电极和第五子电极，所述第五子电极位于所述第四子电极远离所述第一栅电极一侧，所述第四子电极与所述有源层图案电连接，所述第五子电极和所述有源层图案在所述衬底的正投影存在交叠，且互不接触。
  5. 根据权利要求1至4任一所述的显示基板，其中，所述晶体管还包括第一绝缘层，所述第一绝缘层位于所述有源层图案与所述第一栅电极之间，所述第一绝缘层将所述有源层图案覆盖，所述第一源漏电极、所述第一栅电极和所述第二源漏电极均位于所述第一绝缘层远离所述衬底一侧，所述第一 绝缘层中设置有第一过孔和第二过孔，所述第一源漏电极通过所述第一过孔与所述有源层图案电连接，所述第二源漏电极通过所述第二过孔与所述有源层图案电连接。
  6. 根据权利要求1至4任一所述的显示基板，其中，所述晶体管还包括第一绝缘层，所述第一绝缘层包括至少一个绝缘层图案，所述绝缘层图案覆盖部分所述有源层图案，且所述绝缘层图案与至少部分所述有源层图案在所述衬底的正投影存在不交叠区域，所述第一源漏电极、所述第一栅电极和所述第二源漏电极均位于所述第一绝缘层远离所述衬底一侧，所述第一源漏电极和所述第二源漏电极分别与所述有源层图案的不交叠区域电连接。
  7. 根据权利要求1至4任一所述的显示基板，还包括设置在所述晶体管远离所述衬底一侧的像素电极，所述像素电极与所述第二源漏电极一体成型。
  8. 根据权利要求1至4任一所述的显示基板，其中，所述第一源漏电极与所述有源层图案一体成型。
  9. 根据权利要求1至8任一所述的显示基板，还包括信号线，所述信号线与所述第一源漏电极电连接。
  10. 根据权利要求9所述的显示基板，其中，所述信号线位于所述第一源漏电极与所述衬底之间，所述显示基板还包括缓冲层，所述缓冲层位于所述信号线与所述有源层图案之间，所述缓冲层中设置有第三过孔，所述第一源漏电极通过所述第三过孔与所述信号线电连接。
  11. 根据权利要求9所述的显示基板，其中，所述第一源漏电极与所述有源层图案一体成型，所述信号线与所述第一源漏电极电接触，所述信号线位于所述第一源漏电极靠近所述衬底一侧，或者，所述信号线位于所述第一源漏电极远离所述衬底一侧。
  12. 根据权利要求1至11任一所述的显示基板，其中，所述有源层图案的材料采用氧化物半导体。
  13. 根据权利要求1至11任一所述的显示基板，其中，所述晶体管被配置为栅极驱动电路中的晶体管。
  14. 一种显示装置，包括权利要求1至13任一所述的显示基板。
  15. 一种显示基板的制备方法，包括：
    在衬底上形成有源层图案；
    在衬底上形成第一源漏电极，使至少部分所述第一源漏电极与所述有源层图案电连接；
    在所述有源层图案远离所述衬底一侧形成第一栅电极，使所述第一栅电极和所述有源层图案在所述衬底的正投影存在交叠，且互不接触；
    在所述有源层图案远离所述衬底一侧形成第二源漏电极，所述第二源漏电极包括互相连接的第一子电极和第二子电极，所述第二子电极位于所述第一子电极靠近所述第一栅电极一侧，所述第一子电极与所述有源层图案电连接，所述第二子电极和所述有源层图案在所述衬底的正投影存在交叠且互不接触。
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