WO2023283973A1 - 半导体结构的制作方法 - Google Patents

半导体结构的制作方法 Download PDF

Info

Publication number
WO2023283973A1
WO2023283973A1 PCT/CN2021/107202 CN2021107202W WO2023283973A1 WO 2023283973 A1 WO2023283973 A1 WO 2023283973A1 CN 2021107202 W CN2021107202 W CN 2021107202W WO 2023283973 A1 WO2023283973 A1 WO 2023283973A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
layer
protective layer
forming
manufacturing
Prior art date
Application number
PCT/CN2021/107202
Other languages
English (en)
French (fr)
Inventor
吴潮
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/447,191 priority Critical patent/US20230011347A1/en
Publication of WO2023283973A1 publication Critical patent/WO2023283973A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

Definitions

  • the embodiments of the present application relate to but are not limited to a method for fabricating a semiconductor structure.
  • STI shallow trench isolation
  • STI structures typically deposit silicon nitride on a semiconductor substrate and then form a patterned hard mask. A trench is formed by etching the substrate outside the shielded area of the hard mask, and an isolation structure is formed by filling the trench with oxide.
  • Divot edge notch
  • an embodiment of the present application provides a method for fabricating a semiconductor structure, including:
  • Patterned etching is performed on the semiconductor substrate to form a recessed area
  • FIG. 1 is a flowchart of a manufacturing method of a semiconductor structure according to an embodiment of the present application
  • FIG. 2 is a schematic diagram of forming a recessed region on a semiconductor substrate in a method for manufacturing a semiconductor structure according to an embodiment of the present application;
  • FIG. 3 is a schematic diagram of a first protective layer and an isolation structure in a method for fabricating a semiconductor structure according to an embodiment of the present application;
  • FIG. 4 is a schematic diagram of forming a second protective layer in a recessed region in a method for manufacturing a semiconductor structure according to an embodiment of the present application;
  • FIG. 5 is a schematic diagram of forming a first protective layer when there is a second protective layer in the recessed region in a method for fabricating a semiconductor structure according to an embodiment of the present application;
  • FIG. 6 is a schematic diagram of forming an isolation structure when the surface of the substrate has a first protection layer in a method for fabricating a semiconductor structure according to an embodiment of the present application.
  • DRAM Dynamic Random Access Memory, dynamic random access memory
  • FRAM Feroelectric Random Access Memory, ferroelectric random access memory
  • MRAM Magneticoresistive Random Access Memory, magnetic random access memory
  • Sub-Si The underlying silicon (Sub-Si) of the peripheral circuit will be oxidized during the process of active etching (ACTIVE EH) and intermediate multi-step wet etching (WET) and double gate (dual gate) structure. Si is partially oxidized to form Divot.
  • the embodiment of the present application provides a method for manufacturing a semiconductor structure to reduce the above phenomenon.
  • the technical solution of the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments.
  • the embodiment of the present application provides a method for manufacturing a semiconductor structure, as shown in FIG. 1 , the method includes:
  • Step S101 performing patterned etching on the semiconductor substrate to form a recessed area
  • Step S102 forming a first protective layer on the surface of the substrate; wherein, the surface of the substrate is the surface of an unetched area other than the recessed area;
  • Step S103 forming an isolation structure in the recessed region
  • Step S104 removing the first protection layer on the surface of the substrate.
  • a mask or photoresist can be used to cover and protect the area that does not need to be etched, that is, the area of the substrate surface 120, and etch away the area that needs to form a trench, that is, the above-mentioned area.
  • the recessed area 130 can be used to cover and protect the area that does not need to be etched, that is, the area of the substrate surface 120, and etch away the area that needs to form a trench, that is, the above-mentioned area.
  • the isolation structure 140 refers to a structure in which an insulating layer having at least one layer of insulating material isolates two semiconductor substrate regions, such as an STI structure. This structure is widely used in the manufacturing process of submicron semiconductor integrated circuit products.
  • the recessed region 130 is the region used to form the isolation structure 140. Therefore, in order to avoid damage to the edge of the substrate surface 120 and form a Divot during the process of forming the isolation structure, it is proposed in the embodiment of the present application to form a first protective layer 150 .
  • the edge of the above-mentioned substrate surface 120 is protected by the first protective layer 150, which can reduce oxidation during cleaning, etching, etc., thereby reducing Divot, improving product performance, and reducing defective rates in the production process.
  • the above-mentioned first protective layer can be removed by various methods such as cleaning, grinding or etching, so as to complete the manufacturing process of the isolation structure.
  • the forming the first protective layer on the surface of the substrate includes:
  • oxidation treatment is performed on the surface of the substrate to form the first protective layer.
  • the above-mentioned first protective layer needs to cover the surface of the substrate outside the recessed area. Therefore, before forming the first protective layer, a second protective layer can be formed in the recessed area so that the first protective layer will not cover the recessed area.
  • the method for forming the first protection layer may be to oxidize the surface of the substrate to change the film quality of the silicon crystal on the surface of the substrate, thereby forming an oxide film as the first protection layer.
  • Forming the above-mentioned first protection layer by means of oxidation has a simple process and is easy to implement.
  • forming the second protection layer 210 in the recessed region 130 includes:
  • the mask layer 211 is etched to expose the substrate surface 120 , wherein the remaining mask layer 211 is the second protective layer 210 in the recessed region 130 .
  • the mask layer formed on the semiconductor substrate can cover the entire semiconductor substrate, so that the recessed area and the substrate surface outside the recessed area are all covered.
  • the mask layer can be a spin-on hard-mask layer (SOH, Spin-on Hard-mask), or photoresist or the like.
  • the mask layer is thinned by etching, so that the substrate surface outside the recessed area is exposed.
  • the etching method may use a liquid or gas that has a corrosive effect on the mask layer, so that the mask layer is etched to a certain thickness.
  • the exposed substrate surface may be slightly higher than the remaining mask layer in the recessed area, that is, the second protective layer, or may be on the same plane as the surface of the second protective layer.
  • the first protective layer in the embodiment of the present application can be formed on the exposed surface of the substrate. Forming the first protective layer and other methods can oxidize the exposed substrate surface, so that the silicon on the substrate surface is oxidized to form a silicon oxide film; it is also possible to cover an oxide film on the substrate surface by depositing an oxide, thereby Form the first protective layer.
  • the area where the first protective layer needs to be formed can be exposed through the second protective layer, and the recessed area can be covered, so that the subsequent formation of the first protective layer on the surface of the substrate is facilitated without affecting the film quality of the recessed area.
  • the exposed surface of the substrate is higher than the remaining surface of the mask layer.
  • the surface of the remaining second protection layer 210 after etching away the mask layer 211 is lower than the exposed substrate surface 120 .
  • the above-mentioned first protective layer 150 can be formed by utilizing the raised portion of the substrate surface for oxidation treatment.
  • the thickness of the first protective layer formed after the oxidation treatment may be equal to the above-mentioned thickness of the substrate surface above the second protective layer, or may be slightly higher or slightly lower than the thickness of the substrate surface above the second protective layer.
  • the thickness is not limited here, as long as the first protective layer can uniformly cover the surface of the substrate.
  • the height of the exposed substrate surface relative to the remaining surface of the mask layer is 0.1 nm to 5 nm. For example, 1 nanometer, 3 nanometers, 3.5 nanometers or 5 nanometers, etc. In practical applications, parameters can be set according to product requirements or equipment capabilities.
  • the oxidation treatment on the surface of the substrate to form the first protective layer includes:
  • the above method of forming the first protective layer includes oxidizing the surface of the substrate to form an oxide film as the first protective layer.
  • the way of oxidation treatment can utilize RTO, that is, rapid thermal oxidation treatment.
  • the surface of the substrate can be rapidly oxidized by heating in an oxygen-enriched environment to form a dense silicon dioxide film, that is, the above-mentioned first oxygen-enriched layer.
  • CVD technology can also be used to deposit oxygen ions and (O2Plasma, oxygen plasma) on the surface of the substrate, so that it can quickly react with the silicon on the surface of the substrate to form a silicon dioxide film, that is, the second oxygen-rich layer mentioned above.
  • oxygen ions and (O2Plasma, oxygen plasma) on the surface of the substrate, so that it can quickly react with the silicon on the surface of the substrate to form a silicon dioxide film, that is, the second oxygen-rich layer mentioned above.
  • forming the isolation structure 140 in the recessed region 130 includes:
  • a first oxide layer 310, a silicon nitride layer 320 and a second oxide layer 330 are sequentially deposited on the patterned etched semiconductor substrate 110; wherein the second oxide layer 330 covers the substrate surface 120 and said recessed area 130;
  • the first oxide layer 310, the second oxide layer 330 and the silicon nitride layer 320 above the substrate surface 120 are removed through the first cleaning process, so that the first protective layer 150 of the substrate surface 120 is exposed; wherein, the The first oxide layer 310 , the silicon nitride layer 320 and the second oxide layer 330 in the recessed region 130 constitute the isolation structure.
  • the second protective layer in the recessed area can be removed, and then the above isolation structure is formed in the recessed area.
  • the above-mentioned isolation structure may be a shallow trench isolation structure composed of three layers of insulating materials: a first oxide layer, a silicon nitride layer, and a second oxide layer.
  • the first oxide layer and the second silicon oxide may be silicon oxide or other oxides.
  • the first oxide layer and the silicon nitride layer may be a thin film uniformly covering the inner surface of the recessed area, and may also cover the first protective layer during film formation.
  • the second oxide layer can fill the entire recessed area and cover the first protection layer, thereby forming a three-layer isolation structure in the recessed area and on the sidewall of the recess.
  • the first oxide layer, the silicon nitride layer and the second oxide layer covering the first protection layer can be removed through the first cleaning process.
  • the first protective layer on the surface of the substrate is exposed, and the isolation structure in the recessed area is retained. In this way, the entire process of forming the isolation structure will not affect the substrate surface covered by the first protective layer, thereby reducing Divot generated at the edge of the junction between the substrate surface and the recessed region.
  • the first cleaning process may be a physical cleaning method of grinding, or a chemical cleaning method of cleaning with a corrosive solution or gas.
  • the first oxide layer, the silicon nitride layer, and the second oxide layer are etched away by using an acidic solution, thereby exposing the first protection layer.
  • the removing the first protective layer on the surface of the substrate includes:
  • the first protection layer on the surface of the substrate is removed through a second cleaning process.
  • the first protective layer can be removed to expose the substrate surface again, so that other structures, such as transistor structures, can be formed using the substrate surface.
  • the second cleaning process can be a peripheral surface cleaning (Peri Clean) process for the peripheral circuit area, which cleans the entire peripheral area of the semiconductor substrate to remove the first protective layer on the substrate surface outside the recessed area.
  • Peri Clean a peripheral surface cleaning
  • the second cleaning process includes:
  • a weak acid solution may be used to remove only the first protective layer.
  • the weak acid solution includes:
  • Hydrofluoric acid solution with a concentration less than or equal to 1/500.
  • the disclosed devices and methods may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division.
  • the coupling, or direct coupling, or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical or other forms of.
  • the units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed to multiple network units; Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application can be integrated into one processing unit, or each unit can be used as a single unit, or two or more units can be integrated into one unit; the above-mentioned integration
  • the unit can be realized in the form of hardware or in the form of hardware plus software functional unit.
  • the embodiment of the present application provides a method for manufacturing a semiconductor structure, and the method is applied to the industrial production of semiconductor products.
  • the first protective layer is formed on the surface of the substrate, and then the isolation structure is formed in the recessed area after etching, and the first protective layer is removed after the isolation structure is formed.
  • the risk of Divot at the edge of the isolation structure can be reduced through the protection of the first protective layer, and the product performance can be improved.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Element Separation (AREA)

Abstract

本申请实施例公开了一种半导体结构的制作方法，包括：在半导体衬底上进行图形化刻蚀，形成凹陷区域；在衬底表面形成第一保护层；其中，所述衬底表面为所述凹陷区域以外未被刻蚀的区域表面；在所述凹陷区域内形成隔离结构；去除所述衬底表面的所述第一保护层。

Description

半导体结构的制作方法
相关申请的交叉引用
本申请基于申请号为202110784653.3、申请日为2021年07月12日、申请名称为“半导体结构的制作方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请实施例涉及但不限于一种半导体结构的制作方法。
背景技术
在半导体器件的制造技术中，浅槽隔离(Shallow Trench Isolation，STI)技术被广泛应用。STI结构通常在半导体衬底上沉积氮化硅，然后形成具有图案的硬掩膜。通过在硬掩膜的遮挡区域以外刻蚀衬底形成沟槽，并在沟槽中填入氧化物形成隔离结构。然而，在外围电路以及阵列区域等位置形成STI的过程中容易产生凹陷形状的缺陷，称为Divot(边缘缺口)，进而造成产品失效或者产生漏电影响产品性能。
发明内容
有鉴于此，本申请实施例提供一种半导体结构的制作方法，包括：
在半导体衬底上进行图形化刻蚀，形成凹陷区域；
在衬底表面形成第一保护层；其中，所述衬底表面为所述凹陷区域以外未被刻蚀的区域表面；
在所述凹陷区域内形成隔离结构；
去除所述衬底表面的所述第一保护层。
附图说明
图1为本申请实施例的一种半导体结构的制作方法流程图；
图2为本申请实施例的一种半导体结构的制作方法中在半导体衬底上形成凹陷区域的示意图；
图3为本申请实施例的一种半导体结构的制作方法中第一保护层以及隔离结构的示意图；
图4为本申请实施例的一种半导体结构的制作方法中在凹陷区域内形成第二保护层的示意图；
图5为本申请实施例的一种半导体结构的制作方法中在凹陷区域中具有第二保护层时形成第一保护层的示意图；
图6为本申请实施例的一种半导体结构的制作方法中在衬底表面具有第一保护层时形成隔离结构的示意图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
本申请技术方案可以应用于DRAM(Dynamic Random Access Memory，动态随机存储器)、FRAM(Ferroelectric Random Access Memory，铁电随机存储器)或者MRAM(Magnetoresistive Random Access Memory，磁性随机存储器)等存储器产品或者其他半导体器件的外围电路中。
外围电路的底层硅(Sub-Si)从活性刻蚀(ACTIVE EH)后经过中间多步湿法刻蚀(WET)及双栅极(dual gate)结构的制程中会进行氧化反应，使得边缘的Si被部分氧化形成Divot。
本申请实施例提供一半导体结构的制作方法，以减少上述现象。下面结合附图和实施例对本申请的技术方案进一步详细阐述。
本申请实施例提供一种半导体结构的制作方法，如图1所示，该方法包括：
步骤S101、在半导体衬底上进行图形化刻蚀，形成凹陷区域；
步骤S102、在衬底表面形成第一保护层；其中，所述衬底表面为所述凹陷区域以外未被刻蚀的区域表面；
步骤S103、在所述凹陷区域内形成隔离结构；
步骤S104、去除所述衬底表面的所述第一保护层。
在本申请实施例中，如图2所示，在利用晶圆制作半导体器件时，可以对其中至少部分表面的半导体衬底110进行图形化刻蚀。图形化刻蚀的过程中，可以采用掩膜或者光刻胶等覆盖并保护不需要被刻蚀掉的区域即上述衬底表面120的区域，并刻蚀掉需要形成沟槽的区域，即上述凹陷区域130。
如图3所示，隔离结构140是指具有至少一层绝缘材料的绝缘层隔离两个半导体衬底区域的结构，例如STI结构。这种结构被广泛应用于亚微米的半导体集成电路产品的制造工艺中。
凹陷区域130即用于形成隔离结构140的区域，因此，为了避免形成隔离结构的过程中，对衬底表面120的边缘造成损伤，形成Divot，本申请实施例中提出在衬底表面形成第一保护层150。
在凹陷区域130内形成上述隔离结构140的过程中，可能需要各种清洗、刻蚀等过程。上述衬底表面120的边缘在第一保护层150的保护下，可以减少在这些清洗、刻蚀等过程中被氧化的现象，进而减少Divot，提升产品性能，降低生产过程中的不良率。
当完成隔离结构的制程后，可以通过清洗、研磨或者刻蚀等各种方式去除上述第一 保护层，从而完成隔离结构的制程。
在一些实施例中，所述在所述衬底表面形成第一保护层，包括：
在所述凹陷区域内形成第二保护层；
通过所述第二保护层的隔离，在衬底表面进行氧化处理，形成所述第一保护层。
上述第一保护层需要覆盖凹陷区域以外的衬底表面，因此，在形成第一保护层之前，可以在凹陷区域内形成第二保护层，使得第一保护层不会覆盖到凹陷区域中。
在本申请实施例中，形成第一保护层的方法可以通过对衬底表面进行氧化处理，使得衬底表面的硅晶体的膜质改变，从而形成氧化膜作为上述第一保护层。通过氧化的方式形成上述第一保护层，工艺简单且易于实现。
在一些实施例中，如图4所述，所述在所述凹陷区域130内形成第二保护层210，包括：
在所述图形化刻蚀后的半导体衬底110上形成掩膜层211；
刻蚀所述掩膜层211使所述衬底表面120裸露，其中，保留的所述掩膜层211为所述凹陷区域130内的第二保护层210。
在半导体衬底上形成的掩膜层可以覆盖整个半导体衬底，使得凹陷区域以及凹陷区域以外的衬底表面均被覆盖。掩膜层可以为旋涂硬掩膜层(SOH，Spin-on Hard-mask)，或者光刻胶等等。
然后再通过刻蚀的方法对掩膜层进行减薄，使得凹陷区域以外的衬底表面裸露出来。该刻蚀的方法可以使用对掩膜层具有腐蚀作用的液体或者气体，使得掩膜层被腐蚀掉一定的厚度。
裸露出的衬底表面可以略高于凹陷区域内剩余的掩膜层即第二保护层，也可以与第二保护层的表面位于同一平面。这样，可以在裸露出的衬底表面形成本申请实施例中的第一保护层。形成第一保护层等方式可以对裸露的衬底表面进行氧化处理，使得衬底表面的硅被氧化形成氧化硅薄膜；也可以在衬底表面通过沉积氧化物的方式覆盖一层氧化膜，从而形成第一保护层。
这样，就可以通过第二保护层使得需要形成第一保护层的区域显露出来，并遮挡住凹陷区域，从而便于后续在衬底表面形成第一保护层且不影响凹陷区域的膜质。
在一些实施例中，所述刻蚀所述掩膜层使所述衬底表面裸露后，裸露的所述衬底表面高于保留的所述掩膜层的表面。
如图5所示，刻蚀掉掩膜层211后保留的第二保护层210的表面低于裸露出的衬底表面120。这样，可以利用衬底表面高出的部分进行氧化处理，形成上述第一保护层150。
需要说明的是，氧化处理后形成的第一保护层的厚度可以等于上述衬底表面高出第二保护层的厚度，也可以略高于或者略低于衬底表面高出第二保护层的厚度，这里不做限定，只要第一保护层能够均匀覆盖衬底表面即可。
在一些实施例中，所述裸露的衬底表面相对于保留的所述掩膜层表面高度为0.1纳米至5纳米。例如，1纳米、3纳米、3.5纳米或者5纳米等。在实际应用中，可以根据产品需求或者设备能力来设定参数。
在一些实施例中，所述在衬底表面进行氧化处理，形成所述第一保护层，包括：
对所述衬底表面进行RTO处理形成第一富氧层；或者
通过CVD在所述衬底表面沉积第二富氧层；其中，所述第一富氧层或所述第二富氧层为所述第一保护层。
上述形成第一保护层的方式包括对衬底表面进行氧化处理，形成氧化薄膜作为第一保护层。这里，氧化处理的方式可以利用RTO，即快速热氧化处理。示例性地，可以在富氧环境下通过加热升温使得衬底表面被快速氧化，形成致密的二氧化硅薄膜，即上述第一富氧层。
此外，还可以利用CVD技术，将氧离子与(O2Plasma，氧等离子体)沉积在衬底表面，使其与衬底表面的硅快速反应形成二氧化硅薄膜，即上述第二富氧层。
在一些实施例中，如图6所示，所述在所述凹陷区域130内形成隔离结构140，包括：
在所述图形化刻蚀后的半导体衬底110上依次沉积第一氧化层310、氮化硅层320以及第二氧化层330；其中，所述第二氧化层330覆盖所述衬底表面120和所述凹陷区域130；
通过第一清洗流程去除所述衬底表面120上方的第一氧化层310、第二氧化层330以及氮化硅层320，使所述衬底表面120的第一保护层150裸露；其中，所述凹陷区域130内的所述第一氧化层310、所述氮化硅层320以及所述第二氧化层330构成所述隔离结构。
在形成第一保护层后，可以去除凹陷区域内的第二保护层，然后在凹陷区域内形成上述隔离结构。
在本申请实施例中，上述隔离结构可以为由第一氧化层、氮化硅层以及第二氧化层这三层绝缘材料构成的浅槽隔离结构。其中，第一氧化层和第二氧化硅可以为氧化硅，也可以为其他氧化物。
第一氧化层和氮化硅层可以是一层均匀覆盖凹陷区域内表面的薄膜，在成膜的过程中，也可以覆盖到第一保护层上。第二氧化层可以填充整个凹陷区域并覆盖至第一保护层上，从而在凹陷区域内以及凹陷侧壁上形成三层的隔离结构。
然后可以通过第一清洗流程去除覆盖在第一保护层上第一氧化层、氮化硅层以及第二氧化层。裸露出衬底表面的第一保护层，保留凹陷区域内的隔离结构。这样，形成隔离结构的整个过程都不会影响被第一保护层覆盖的衬底表面，从而减少衬底表面与凹陷区域交界的边缘位置产生的Divot。
需要说明的是，第一清洗流程可以为研磨的物理清洗方式，也可以为利用腐蚀性溶液或者气体进行清洗的化学清洗方式。例如，利用酸性溶液使上述第一氧化层、氮化硅层以及第二氧化层被腐蚀掉，从而裸露出上述第一保护层。
在一些实施例中，所述去除所述衬底表面的所述第一保护层，包括：
通过第二清洗流程去除所述衬底表面的所述第一保护层。
在凹陷区域内形成隔离结构后，可以去除第一保护层，重新使得衬底表面裸露出来，以便利用衬底表面形成其他结构，如晶体管结构等。
第二清洗流程可以为针对外围电路区域的外围表面清洗(Peri Clean)流程，针对半 导体衬底的外围区域整体进行清洗，去除凹陷区域以外的衬底表面的第一保护层。
在一些实施例中，所述第二清洗流程，包括：
使用弱酸溶液，对所述衬底表面进行清洗。
为了减少上述第二清洗流程对衬底表面的损伤，可以采用弱酸溶液，仅去除第一保护层。
在一些实施例中，所述弱酸溶液，包括：
浓度小于或等于1/500的氢氟酸溶液。
这样，可以减少对隔离结构的损伤，保证外围电路的电性性能。
应理解，说明书通篇中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本申请的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。上述本申请实施例序号仅仅为了描述，不代表实施例的优劣。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
在本申请所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过其它的方式实现。以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的各组成部分相互之间的耦合、或直接耦合、或通信连接可以是通过一些接口，设备或单元的间接耦合或通信连接，可以是电性的、机械的或其它形式的。
上述作为分离部件说明的单元可以是、或也可以不是物理上分开的，作为单元显示的部件可以是、或也可以不是物理单元；既可以位于一个地方，也可以分布到多个网络单元上；可以根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。
另外，在本申请各实施例中的各功能单元可以全部集成在一个处理单元中，也可以是各单元分别单独作为一个单元，也可以两个或两个以上单元集成在一个单元中；上述集成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。
以上所述，仅为本申请的实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。
工业实用性
本申请是实施例提供一种半导体结构的制作方法，该方法应用于半导体产品的工业生产。通过本申请实施例的技术方案，通过在衬底表面形成第一保护层，再在刻蚀后的 凹陷区域内形成隔离结构，在形成隔离结构后再去除第一保护层。如此，可以在形成隔离结构的过程中，通过第一保护层的保护，减少隔离结构边缘位置产生Divot的风险，提升产品性能。

Claims (10)

  1. 一种半导体结构的制作方法，包括：
    在半导体衬底上进行图形化刻蚀，形成凹陷区域；
    在衬底表面形成第一保护层；其中，所述衬底表面为所述凹陷区域以外未被刻蚀的区域表面；
    在所述凹陷区域内形成隔离结构；
    去除所述衬底表面的所述第一保护层。
  2. 根据权利要求1所述的制作方法，其中，所述在所述衬底表面形成第一保护层，包括：
    在所述凹陷区域内形成第二保护层；
    通过所述第二保护层的隔离，在衬底表面进行氧化处理，形成所述第一保护层。
  3. 根据权利要求2所述的制作方法，其中，所述在所述凹陷区域内形成第二保护层，包括：
    在所述图形化刻蚀后的半导体衬底上形成掩膜层；
    刻蚀所述掩膜层使所述衬底表面裸露，其中，保留的所述掩膜层为所述凹陷区域内的第二保护层。
  4. 根据权利要求3所述的制作方法，其中，所述刻蚀所述掩膜层使所述衬底表面裸露后，裸露的所述衬底表面高于保留的所述掩膜层的表面。
  5. 根据权利要求4所述的制作方法，其中，所述裸露的衬底表面相对于保留的所述掩膜层表面高度为0.1纳米至5纳米。
  6. 根据权利要求2所述的制作方法，其中，所述在衬底表面进行氧化处理，形成所述第一保护层，包括：
    对所述衬底表面进行快速热氧化RTO处理形成第一富氧层；或者
    通过化学气相沉积CVD在所述衬底表面沉积第二富氧层；其中，所述第一富氧层或所述第二富氧层为所述第一保护层。
  7. 根据权利要求1至6任一所述的制作方法，其中，所述在所述凹陷区域内形成隔离结构，包括：
    在所述图形化刻蚀后的半导体衬底上依次沉积第一氧化层、氮化硅层以及第二氧化层；其中，所述第二氧化层覆盖所述衬底表面和所述凹陷区域；
    通过第一清洗流程去除所述衬底表面上方的第一氧化层、第二氧化层以及氮化硅层，使所述衬底表面的第一保护层裸露；其中，所述凹陷区域内的所述第一氧化层、所述氮化硅层以及所述第二氧化层构成所述隔离结构。
  8. 根据权利要求1所述的制作方法，其中，所述去除所述衬底表面的所述第一保护层，包括：
    通过第二清洗流程去除所述衬底表面的所述第一保护层。
  9. 根据权利要求8所述的制作方法，其中，所述第二清洗流程，包括：
    使用弱酸溶液，对所述衬底表面进行清洗。
  10. 根据权利要求9所述的制作方法，其中，所述弱酸溶液，包括：
    浓度小于或等于1/500的氢氟酸溶液。
PCT/CN2021/107202 2021-07-12 2021-07-19 半导体结构的制作方法 WO2023283973A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/447,191 US20230011347A1 (en) 2021-07-12 2021-09-08 Manufacturing method for semiconductor structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110784653.3A CN113594085B (zh) 2021-07-12 2021-07-12 半导体结构的制作方法
CN202110784653.3 2021-07-12

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/447,191 Continuation US20230011347A1 (en) 2021-07-12 2021-09-08 Manufacturing method for semiconductor structure

Publications (1)

Publication Number Publication Date
WO2023283973A1 true WO2023283973A1 (zh) 2023-01-19

Family

ID=78246909

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/107202 WO2023283973A1 (zh) 2021-07-12 2021-07-19 半导体结构的制作方法

Country Status (2)

Country Link
CN (1) CN113594085B (zh)
WO (1) WO2023283973A1 (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030201473A1 (en) * 2002-04-24 2003-10-30 Hsien-Wen Liu Method of fabricating shallow trench isolation
CN104347473A (zh) * 2013-08-05 2015-02-11 中芯国际集成电路制造(北京)有限公司 浅沟槽隔离结构及其形成方法
CN105655285A (zh) * 2014-12-02 2016-06-08 中芯国际集成电路制造(上海)有限公司 沟槽隔离结构及其形成方法
CN109524345A (zh) * 2018-10-19 2019-03-26 武汉新芯集成电路制造有限公司 浅沟槽隔离结构及其制造方法和半导体器件
CN110911342A (zh) * 2018-09-14 2020-03-24 长鑫存储技术有限公司 浅沟槽隔离结构及其制备方法
CN112234024A (zh) * 2020-11-18 2021-01-15 华虹半导体(无锡)有限公司 浅沟槽隔离结构的顶角圆化方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100449318B1 (ko) * 2001-12-20 2004-09-18 동부전자 주식회사 반도체 장치의 소자 분리막 형성방법
US8227318B2 (en) * 2009-11-19 2012-07-24 International Business Machines Corporation Integration of multiple gate oxides with shallow trench isolation methods to minimize divot formation
US20130122684A1 (en) * 2011-11-10 2013-05-16 Teng-Chun Hsuan Semiconductor process for removing oxide layer

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030201473A1 (en) * 2002-04-24 2003-10-30 Hsien-Wen Liu Method of fabricating shallow trench isolation
CN104347473A (zh) * 2013-08-05 2015-02-11 中芯国际集成电路制造(北京)有限公司 浅沟槽隔离结构及其形成方法
CN105655285A (zh) * 2014-12-02 2016-06-08 中芯国际集成电路制造(上海)有限公司 沟槽隔离结构及其形成方法
CN110911342A (zh) * 2018-09-14 2020-03-24 长鑫存储技术有限公司 浅沟槽隔离结构及其制备方法
CN109524345A (zh) * 2018-10-19 2019-03-26 武汉新芯集成电路制造有限公司 浅沟槽隔离结构及其制造方法和半导体器件
CN112234024A (zh) * 2020-11-18 2021-01-15 华虹半导体(无锡)有限公司 浅沟槽隔离结构的顶角圆化方法

Also Published As

Publication number Publication date
CN113594085A (zh) 2021-11-02
CN113594085B (zh) 2023-10-03

Similar Documents

Publication Publication Date Title
US6787421B2 (en) Method for forming a dual gate oxide device using a metal oxide and resulting device
US20180233579A1 (en) Gate cut integration and related device
US6130168A (en) Using ONO as hard mask to reduce STI oxide loss on low voltage device in flash or EPROM process
KR20010015288A (ko) 폴리실리콘 마스크와 화학적 기계적 폴리싱(ｃｍｐ)평탄화를 이용하여 서로 다른 두께를 갖는 2개의 게이트유전체를 제조하기 위한 방법
JPH0438853A (ja) コンタクト構造の形成方法
JP2003158264A (ja) 金属ゲートｃｍｏｓおよびその製造方法
JP5226863B2 (ja) ２重ハードマスク層を使用したｃｍｏｓイメージセンサの製造方法
WO2023283973A1 (zh) 半导体结构的制作方法
TWI793949B (zh) 半導體結構及其製備方法
US6184116B1 (en) Method to fabricate the MOS gate
US20230011347A1 (en) Manufacturing method for semiconductor structure
JP2002373935A (ja) トレンチ素子分離方法
WO2022033126A1 (zh) 一种半导体器件及其制备方法
US6784056B2 (en) Flash memory cell process using a hardmask
JPH11176929A (ja) 化学気相蒸着による第２パッド酸化膜を用いた半導体装置の素子分離方法
TWI840771B (zh) 處理半導體基板之方法及半導體結構
US20220230881A1 (en) Active region array formation method
WO2023060754A1 (zh) 一种半导体结构及半导体结构制作方法
US6667210B2 (en) Flash memory cell process using a hardmask
JPH0778999A (ja) 半導体装置の製造方法
US20200203221A1 (en) Semiconductor structure and method of processing the same
US8524603B1 (en) Fabricating method for semiconductor device
KR20000067350A (ko) 실리콘 질화막의 크랙 방지를 위한 커패시터 형성 방법
CN116454026A (zh) 改善厚栅氧化层残留的方法
TW202303757A (zh) 半導體基板上之邊緣保護

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21949753

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE