WO2023248630A1 - 出力帰還回路、リニア電源 - Google Patents

出力帰還回路、リニア電源 Download PDF

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Publication number
WO2023248630A1
WO2023248630A1 PCT/JP2023/017276 JP2023017276W WO2023248630A1 WO 2023248630 A1 WO2023248630 A1 WO 2023248630A1 JP 2023017276 W JP2023017276 W JP 2023017276W WO 2023248630 A1 WO2023248630 A1 WO 2023248630A1
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Prior art keywords
output
voltage
transistor
amplifier
feedback circuit
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2023/017276
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English (en)
French (fr)
Japanese (ja)
Inventor
信 安坂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
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Rohm Co Ltd
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Publication date
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Priority to JP2024528373A priority Critical patent/JPWO2023248630A1/ja
Publication of WO2023248630A1 publication Critical patent/WO2023248630A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current 
    • G05F1/46—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
    • G05F1/56—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices

Definitions

  • the present disclosure relates to an output feedback circuit and a linear power supply using the same.
  • the output feedback circuit is built into a linear power supply that generates a desired output voltage from an input voltage (for example, see Patent Document 1).
  • the output feedback circuit disclosed herein is configured to generate an error signal that is in phase with the output voltage depending on the difference between the output voltage or a corresponding feedback voltage and a predetermined reference voltage.
  • an error amplifier configured to generate a drive signal for an output transistor by amplifying the error signal, and an amplifier configured to transmit the error signal from an output end of the error amplifier to an input end of the amplifier.
  • a shield wiring that is laid adjacent to and parallel to the signal wiring and is configured to receive the output voltage or a voltage in phase with the output voltage.
  • FIG. 1 is a diagram showing a comparative example of a linear power supply.
  • FIG. 2 is a diagram showing a first embodiment of the linear power supply.
  • FIG. 3 is a diagram showing an example of the configuration of an error amplifier and an amplifier.
  • FIG. 4 is a diagram showing a planar layout of signal wiring and shield wiring.
  • FIG. 5 is a diagram showing parasitic capacitance between wirings.
  • FIG. 6 is a diagram showing parasitic capacitance in the linear power supply of the first embodiment.
  • FIG. 7 is a diagram showing a second embodiment of the linear power supply.
  • FIG. 8 is a diagram showing parasitic capacitance in the linear power supply according to the second embodiment.
  • FIG. 9 is a diagram showing the behavior of the output voltage when the output current suddenly changes.
  • FIG. 9 is a diagram showing the behavior of the output voltage when the output current suddenly changes.
  • FIG. 10 is a diagram showing a third embodiment of the linear power supply.
  • FIG. 11 is a diagram showing parasitic capacitance in the linear power supply of the third embodiment.
  • FIG. 12 is a diagram showing a fourth embodiment of the linear power supply.
  • FIG. 13 is a diagram showing a fifth embodiment of the linear power supply.
  • FIG. 14 is a diagram showing a sixth embodiment of the linear power supply.
  • the linear power supply 1 of this comparative example generates a desired output voltage Vout from the input voltage Vin and supplies it to the load 2 connected to the output terminal OUT.
  • the linear power supply 1 may be an LDO [low drop out] regulator.
  • the linear power supply 1 includes an output transistor M0, an error amplifier 10, an amplifier 20, and a feedback voltage generation circuit 30. Note that some or all of these components may be integrated into a semiconductor device.
  • the output transistor M0 is connected between the application end of the input voltage Vin and the application end of the output voltage Vout.
  • the output transistor M0 may be, for example, a PMOSFET [P-channel type metal oxide semiconductor field effect transistor].
  • the source of the output transistor M0 is connected to the application terminal of the input voltage Vin
  • the drain of the output transistor M0 is connected to the application terminal of the output voltage Vout.
  • the error amplifier 10 generates an error signal S0 according to the difference between the feedback voltage Vfb input to the non-inverting input terminal (+) and the reference voltage Vref input to the inverting input terminal (-).
  • the reference voltage Vref may be a constant voltage that is not easily affected by the input voltage Vin and ambient temperature.
  • the error signal S0 decreases when the feedback voltage Vfb is lower than the reference voltage Vref, and increases when the feedback voltage Vfb is higher than the reference voltage Vref. That is, the error signal S0 decreases when the output voltage Vout is lower than the target value, and increases when the output voltage Vout is higher than the target value. In this way, the error amplifier 10 generates the error signal S0 that is in phase with the output voltage Vout according to the difference between the feedback voltage Vfb and the reference voltage Vref.
  • error signal S0 is transmitted from the output end of the error amplifier 10 to the input end of the amplifier 20 via the signal line L1.
  • the amplifier 20 generates a drive signal G0 for the output transistor M0 by amplifying the error signal S0, and outputs it to the gate of the output transistor M0.
  • the amplifier 20 may be a non-inverting output type (so-called buffer) that generates a drive signal G0 of the same polarity (same logic level) as the error signal S0. .
  • the gain of the error amplifier 10 is not very high. Therefore, an amplifier 20 for amplifying the error signal S0 is often provided after the error amplifier 10.
  • the feedback voltage generation circuit 30 includes resistors 31 and 32 connected in series between the output terminal OUT and the ground terminal, and divides the output voltage Vout to generate the feedback voltage Vfb. Note that the feedback voltage generation circuit 30 may be omitted and the output voltage Vout may be directly input to the error amplifier 10.
  • the error amplifier 10, the amplifier 20, and the feedback voltage generation circuit 30 form an output feedback circuit X for controlling the drive of the output transistor M0 so that the feedback voltage Vfb matches the reference voltage Vref. are doing.
  • the error amplifier 10 operates in response to the bias current Ib1 generated by the current source 11.
  • the bias current Ib1 of the error amplifier 10 will also be reduced. Reducing the bias current Ib1 of the error amplifier 10 increases the output impedance of the error amplifier 10, making the error signal S0 more susceptible to noise and the like. As a result, there is a possibility that the linear power supply 1 may malfunction or the stability of the output voltage Vout may be impaired.
  • FIG. 2 is a diagram showing a first embodiment of the linear power supply.
  • the linear power supply 1 of the first embodiment is based on the above-mentioned comparative example (FIG. 1), but further includes a shield wiring L2.
  • the shield wiring L2 is laid adjacent to and parallel to the signal wiring L1, as shown by the dashed line in the figure.
  • a plurality of shield wirings L2 may be laid in the same wiring layer as the shield wiring L2 so as to sandwich the signal wiring L1 in a two-dimensional manner.
  • a plurality of shield wirings L2 may be laid in the wiring layer immediately above and directly below the wiring layer in which the signal wiring L1 is laid, so as to three-dimensionally sandwich the signal wiring L1.
  • the shield wiring L2 is connected to a stable potential node (for example, a ground terminal) via a low-impedance conductive path.
  • FIG. 3 is a diagram showing an example of the configuration of the error amplifier 10 and the amplifier 20.
  • the error amplifier 10 includes transistors 12 and 13 (for example, PMOSFET) and transistors 14 and 15 (for example, NMOSFET [N-channel type MOSFET]).
  • the amplifier 20 of this configuration example includes a current source 21 and a transistor 22 (for example, an NMOSFET).
  • the current source 11 is connected between the application terminal of the input voltage Vin and the sources of each of the transistors 12 and 13, and generates a bias current Ib1.
  • the gate of the transistor 12 is connected to the application terminal of the feedback voltage Vfb as a non-inverting input terminal (+) of the error amplifier 10.
  • the gate of the transistor 13 is connected as an inverting input terminal (-) of the error amplifier 10 to an application terminal of the reference voltage Vref.
  • the gates of transistors 14 and 15 are both connected to the drain of transistor 14.
  • the drain of transistor 14 is connected to the drain of transistor 12.
  • the sources of transistors 14 and 15 are both connected to a ground terminal.
  • the current source 21 is connected between the application terminal of the input voltage Vin and the drain of the transistor 22, and generates a bias current Ib2.
  • the drain of the transistor 22 is connected to the application terminal of the drive signal G0 as the output terminal of the amplifier 20.
  • the gate of the transistor 22 is connected to the second end of the signal line L1 as an input end of the amplifier 20.
  • the source of transistor 22 is connected to the ground terminal.
  • a shield wiring L2 is laid.
  • the shield wiring L2 is connected to a stable potential node (for example, a ground terminal) via a low impedance conductive path.
  • the linear power supply 1 of the first embodiment With the linear power supply 1 of the first embodiment, noise etc. superimposed from the outside can be released to the shield wiring L2. Therefore, the error signal S0 is less susceptible to noise and the like.
  • FIG. 4 is a diagram showing a planar layout of the signal wiring L1 (solid line) and the shield wiring L2 (broken line) on a semiconductor substrate in which the error amplifier 10 and the amplifier 20 are integrated.
  • symbols D, S, and G in the figure schematically indicate the drain, source, and gate of the transistors 12 to 15 and the transistor 22, respectively.
  • FIG. 5 is a diagram (corresponding to a partially enlarged diagram of the peripheral region of the transistor 22 in FIG. 4 mentioned earlier) showing the parasitic capacitance that accompanies the signal wiring L1 and the shield wiring L2.
  • a parasitic capacitance Cp is attached between the signal wiring L1 and the shield wiring L2 so that the signal wiring L1 and the shield wiring L2 each serve as an electrode.
  • the capacitance value of the parasitic capacitance Cp increases as the parallel running distance of the signal wiring L1 and the shield wiring L2 increases.
  • FIG. 6 is a diagram showing the parasitic capacitance Cp in the linear power supply 1 of the first embodiment. As shown in this figure, when looking at the output feedback circuit Become.
  • FIG. 7 is a diagram showing a second embodiment of the linear power supply.
  • the linear power supply 1 of the second embodiment is based on the first embodiment (FIG. 2) described above, but the shield wiring L2 is connected not to the ground terminal but to the application of the output voltage Vout.
  • FIG. 8 is a diagram showing the parasitic capacitance Cp in the linear power supply 1 of the second embodiment. As shown in this figure, when looking at the output feedback circuit It becomes an accompanying form.
  • the error signal S0 is a voltage signal that is in phase with the output voltage Vout. Therefore, the transient response characteristics of the error amplifier 10 (and by extension, the linear power supply 1) in the high frequency region are improved. Furthermore, since the end to which the output voltage Vout is applied has low impedance, the original shielding effect of the shield wiring L2 is not impaired.
  • FIG. 9 is a diagram showing the behavior of the output voltage Vout when the output current Iout suddenly changes.
  • the solid line indicates the behavior of the second embodiment (denoted as “Vout shield”).
  • the large broken line indicates the behavior of the first embodiment (described as “GND shield”)
  • the small broken line indicates the behavior of the comparative example (described as “no shield”).
  • FIG. 10 is a diagram showing a third embodiment of the linear power supply.
  • the linear power supply 1 of the third embodiment is based on the aforementioned second embodiment (FIG. 7), but the P-channel type output transistor M0 is replaced with an N-channel type output transistor M0'.
  • the drain of the output transistor M0' is connected to the application terminal of the input voltage Vin, and the source of the output transistor M0' is connected to the application terminal of the output voltage Vout.
  • the non-inverting output type amplifier 20 is replaced with an inverting output type amplifier 20' due to the above change. That is, the amplifier 20' generates a drive signal G0' having a polarity opposite to that of the error signal S0 (inverted logic level). Therefore, the higher the error signal S0, the lower the drive signal G0' becomes, and the lower the error signal S0, the higher the drive signal G0' becomes.
  • FIG. 11 is a diagram showing the parasitic capacitance Cp in the linear power supply 1 of the third embodiment. As shown in this figure, when looking at the output feedback circuit It becomes an accompanying form. In this respect, there is no difference from the previously mentioned second embodiment (FIG. 7).
  • the configuration in which the output voltage Vout is applied to the shield wiring L2 can be applied regardless of the channel type of the output transistor.
  • FIG. 12 is a diagram showing a fourth embodiment of the linear power supply.
  • the linear power supply 1 of the fourth embodiment is based on the aforementioned second embodiment (FIG. 7), but further includes a voltage clamp circuit 40.
  • the voltage clamp circuit 40 generates a clamp voltage Vout' that is in phase with the output voltage Vout and applies it to the shield wiring L2.
  • connection destination of the shield wiring L2 is not necessarily limited to the application end of the output voltage Vout, but may be any potential node as long as it is in phase with the output voltage Vout and has low impedance.
  • the AC behavior of the voltage applied to the shield wiring L2 only needs to be in phase with the output voltage Vout, and there is no problem even if the DC level deviates.
  • FIG. 13 is a diagram showing a fifth embodiment of the linear power supply.
  • the linear power supply 1 of the fifth embodiment is based on the fourth embodiment (FIG. 12) described above, but a current source 41 and a transistor 42 (for example, a PMOSFET) are illustrated as components of the voltage clamp circuit 40.
  • a current source 41 and a transistor 42 for example, a PMOSFET
  • the current source 41 is connected between the application terminal of the input voltage Vin and the source of the transistor 42, and generates a bias current Ib3.
  • the drain of the transistor 42 is connected to the ground end.
  • the gate is connected to the application end of the output voltage Vout.
  • the DC level of the clamp voltage Vout is It deviates from the voltage Vout.
  • the AC behavior of the clamp voltage Vout'' is in phase with the output voltage Vout. Therefore, it is possible to improve the transient response characteristics while maintaining the shielding effect.
  • FIG. 14 is a diagram showing a sixth embodiment of the linear power supply.
  • the linear power supply 1 of the sixth embodiment is based on the fourth embodiment (FIG. 12) described above, but a current source 43 and a transistor 44 (for example, NMOSFET) are illustrated as components of the voltage clamp circuit 40.
  • a current source 43 and a transistor 44 for example, NMOSFET
  • the current source 43 is connected between the source of the transistor 44 and the ground terminal, and generates a bias current Ib4.
  • the drain of the transistor 44 is connected to the application terminal of the input voltage Vin.
  • the gate of the transistor 44 is connected to the application terminal of the output voltage Vout.
  • the output feedback circuit disclosed herein is configured to generate an error signal that is in phase with the output voltage depending on the difference between the output voltage or a corresponding feedback voltage and a predetermined reference voltage.
  • an error amplifier configured to generate a drive signal for an output transistor by amplifying the error signal, and an amplifier configured to transmit the error signal from an output end of the error amplifier to an input end of the amplifier.
  • a shield wiring that is laid adjacent to and runs parallel to the signal wiring and is configured to receive the output voltage or a voltage in phase with the output voltage ( (first configuration).
  • the error amplifier operates according to the difference between the output voltage or the feedback voltage input to the non-inverting input terminal and the reference voltage input to the inverting input terminal.
  • a configuration (second configuration) may be used to generate the error signal.
  • the output transistor may be of a P-channel type or a pnp type, and the amplifier may be of a non-inverting output type (third configuration).
  • the output transistor may be of an N-channel type or an npn type, and the amplifier may be of an inverted output type (fourth configuration).
  • the output feedback circuit includes a voltage clamp circuit configured to generate a clamp voltage in phase with the output voltage and apply it to the shield wiring (fifth configuration).
  • the voltage clamp circuit includes a transistor configured such that a gate is connected to the application terminal of the output voltage and a source is connected to the shield wiring ( (6th configuration) may also be used.
  • the transistor is of a P-channel type or a pnp type, and the clamp voltage is higher than the output voltage by an on-threshold voltage of the transistor (seventh configuration). You can.
  • the transistor is of an N-channel type or an npn type, and the clamp voltage is lower than the output voltage by an on-threshold voltage of the transistor (eighth configuration). You can.
  • the output feedback circuit may be configured to include a feedback voltage generation circuit configured to generate the feedback voltage by dividing the output voltage (a ninth configuration). You can.
  • the linear power supply disclosed herein includes the output transistor configured to be connected between an input voltage application end and an output voltage application end, and the output voltage or a configuration (tenth configuration) comprising: an output feedback circuit according to any one of the first to ninth configurations, configured to drive the output transistor so that the feedback voltage matches the reference voltage; has been done.
  • the PMOSFET and NMOSFET may be replaced with a pnp bipolar transistor and an npn bipolar transistor, respectively. In that case, it is sufficient to read the drain, source, and gate in the previous explanation as collector, emitter, and base.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
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  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Semiconductor Integrated Circuits (AREA)
PCT/JP2023/017276 2022-06-20 2023-05-08 出力帰還回路、リニア電源 Ceased WO2023248630A1 (ja)

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JP2022-098797 2022-06-20

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017107551A (ja) * 2015-11-30 2017-06-15 ローム株式会社 電源レギュレータ
JP2018148274A (ja) * 2017-03-01 2018-09-20 株式会社リコー アナログ信号バス駆動回路、及び光電変換装置
JP2020123643A (ja) * 2019-01-30 2020-08-13 ローム株式会社 半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017107551A (ja) * 2015-11-30 2017-06-15 ローム株式会社 電源レギュレータ
JP2018148274A (ja) * 2017-03-01 2018-09-20 株式会社リコー アナログ信号バス駆動回路、及び光電変換装置
JP2020123643A (ja) * 2019-01-30 2020-08-13 ローム株式会社 半導体装置

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