WO2023243451A1 - Dispositif de commande de convertisseur de puissance et procédé de commande - Google Patents

Dispositif de commande de convertisseur de puissance et procédé de commande Download PDF

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Publication number
WO2023243451A1
WO2023243451A1 PCT/JP2023/020695 JP2023020695W WO2023243451A1 WO 2023243451 A1 WO2023243451 A1 WO 2023243451A1 JP 2023020695 W JP2023020695 W JP 2023020695W WO 2023243451 A1 WO2023243451 A1 WO 2023243451A1
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WIPO (PCT)
Prior art keywords
current
power converter
output
gate
semiconductor switching
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PCT/JP2023/020695
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English (en)
Japanese (ja)
Inventor
徹郎 児島
高志 伊君
直樹 栗原
比呂 中山
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株式会社日立製作所
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Publication of WO2023243451A1 publication Critical patent/WO2023243451A1/fr

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode

Definitions

  • the present invention relates to a power converter control device and control method.
  • the output voltage command is normalized with the DC power supply voltage to obtain a modulated wave.
  • the semiconductor switching element is driven by PWM control that outputs a pulse obtained by comparing this modulated wave and a carrier wave.
  • delay elements of detection timing include delay time due to an output current input circuit such as an output current sensor, an LPF circuit for noise removal, and an A/D converter. Furthermore, the operation delay time of the gate circuit that drives the semiconductor switching element and the semiconductor switching element itself can also be seen as the delay time of the detection timing. Therefore, it is necessary to consider both delay times in the same way.
  • Patent Document 1 and Patent Document 2 are known as techniques for accurately detecting the output current with respect to such detection timing delay elements.
  • Patent Document 3 and Patent Document 4 are known as gate circuits for driving a semiconductor switching element including such a plurality of gate terminals. Both technologies achieve low loss by providing a predetermined delay time within the gate circuit and completing the transition between the steady mode and the transient mode during this delay time.
  • Patent Document 1 assumes a delay time of about several ⁇ s, but the technique described in Patent Document 4 causes an operation delay of about 60 ⁇ s.
  • the output current is detected after being delayed by the operation delay time from the timing of the peaks and troughs of the carrier.
  • the operation delay time is as short as several ⁇ s, there is no problem, but if the operation delay time becomes long as in the technique described in Patent Document 4, the output current value detected within the control cycle cannot be used. In that case, the control cycle is carried over to the next control cycle, leading to an increase in dead time and affecting the responsiveness of the current feedback control.
  • the output current can be detected accurately, but the actual operation delay time may vary due to individual variations in semiconductor switching elements, current dependence of the operation delay time, etc. Therefore, errors may occur.
  • Patent Document 2 in order to avoid the influence of such variations in operation delay time, the output current is reduced for a period shorter than the period of peaks and troughs of the carrier, that is, shorter than a half period of the carrier. is sampled multiple times and the average value of these is used for current feedback control.
  • Patent Document 2 does not disclose the specific length of the sampling period and the timing of starting sampling.
  • the sampling period is shorter than the carrier half cycle, if the operation delay time is as short as a few ⁇ s, the sampling period will be symmetrical with respect to the timing of the peaks and troughs of the carrier.
  • the switching ripples are approximately symmetrical (the magnitude is the same but the sign is opposite) centering on the timing of the peak and valley of the carrier. Therefore, the magnitude of the output current can be accurately determined by canceling out the effects of switching ripples.
  • Another object of the present invention is to provide a technique that suppresses dead time and improves the responsiveness of current feedback control.
  • one of the representative power converter control devices of the present invention is a current detection device that detects the output current of a power converter that converts DC power into AC power using a semiconductor switching element.
  • current control means for generating an output voltage command of the power converter through current control based on the output of the current detection means; PWM control means for outputting a gate command for the semiconductor switching element based on the output voltage command;
  • the current detecting means is equipped with a gate driver circuit that generates a gate signal for turning on and off the element with an operation delay from the gate command, and the current detecting means uses the output of the current sensor provided on the output side of the power converter as an input signal, and controls the sampling period.
  • the current integrating section calculates the current integrated value for each integration period, the current controlling means performs current control based on the current integrated value, and the current detecting means, the current controlling means, and the PWM controlling means operate in synchronization. It is something to do.
  • FIG. 1 is a diagram showing an example of an AC motor drive device configured using a power converter control device according to the present invention
  • FIG. 2 is a diagram showing a detailed configuration of a current detection means in the control device shown in FIG. 1.
  • FIG. FIG. 2 is a diagram showing a detailed configuration of rotational coordinate conversion means in the control device shown in FIG. 1.
  • FIG. 2 is a diagram showing a detailed configuration of current control means in the control device shown in FIG. 1.
  • FIG. FIG. 2 is a diagram showing an example of a current waveform when an AC motor is driven using a conventional technique (operation delay time: less than 1 ⁇ s).
  • FIG. 2 is a diagram showing an example of a current waveform when an AC motor is driven using a conventional technique (operation delay time: 60 ⁇ s).
  • FIG. 2 is a diagram showing an example of a current waveform when an AC motor is driven using an embodiment of the present invention (operation delay time: 60 ⁇ s).
  • FIG. 3 is a diagram showing a difference in current waveform of an AC motor depending on whether or not there is an operation delay of a semiconductor switching element. It is a figure which shows the operating waveform of each element which comprises a control apparatus when an AC motor is driven using the control apparatus of the power converter which concerns on this invention.
  • FIG. 1 is a diagram showing an example of an AC motor drive device configured using a power converter control device according to the present invention.
  • a smoothing capacitor 10 that smoothes DC power supplied by a DC voltage source (not shown) and a bridge circuit configured by connecting semiconductor switching elements 11 and 12, 13 and 14, and 15 and 16 in series are connected in parallel. connected to form a power converter.
  • the AC output terminal of this bridge circuit is connected to an AC motor (MOTOR) 18, and a current sensor 17 detects the output current from the AC output terminal to the AC motor (MOTOR) 18.
  • the semiconductor switching elements 11 to 16 have two gate terminals (dual gates), and can switch between a mode for reducing conduction loss and a mode for reducing switching loss using two gate signals.
  • the output currents iu, iv, and iw detected by the current sensor 17 are input to a low-pass filter (LPF) circuit 20 that reduces surge noise and the like. Then, the output of the low-pass filter (LPF) circuit 20 is sampled using the A/D converter 21.
  • LPF low-pass filter
  • the current detection means 22 inputs iuf, ivf, and iwf output from the A/D converter 21 and the trigger signal Trig, and outputs the output current integrated values ius, ivs, iws and the number of integrations N.
  • the rotational coordinate conversion means 23 outputs a trigger signal Trig to the current detection means 22, reads the output current integrated values ius, ivs, iws and the number of integrations N from the A/D converter 21, calculates the output current average value, and calculates the rotational coordinate conversion means 23. Coordinate transformation is performed to output detected current values Id and Iq on the d/q axes.
  • the current control means (ACR) 24 performs current control using the detected current values Id and Iq on the d/q axes, generates a voltage vector, and then performs static coordinate transformation to obtain AC voltage commands vup, vvp, and vwp. Output.
  • the PWM control means 25 inputs the AC voltage commands vup, vvp, and vwp, normalizes them with the DC power supply voltage, compares them with a carrier wave, and performs PWM control to prevent short-circuiting between the upper arm and the lower arm that constitute the power converter.
  • Gate commands (Gpu to Gnw) are output by managing the non-wrapping time and minimum pulse width for prevention.
  • the gate driver (GD) circuit 26 receives gate commands (Gpu to Gnw) and generates first and second gate signals (Gpu1, 2 to Gnw1, 2) that drive the semiconductor switching elements 11 to 16.
  • the time constant of the low-pass filter (LPF) circuit 20 is about several ⁇ s to 10 ⁇ s, and the sampling period of the A/D converter 21 and the current detection means 22 is also about several ⁇ s.
  • the rotational coordinate conversion means 23, the current control means (ACR) 24, and the PWM control means 25 perform processing in the same PWM control period, which varies depending on the carrier frequency, but is generally on the order of several hundred ⁇ s to several ms.
  • the non-wrap time and minimum pulse width in the PWM control means 25 are both about several ⁇ s to 10 ⁇ s.
  • the gate driver (GD) circuit 26 When the gate driver (GD) circuit 26 generates the first and second gate signals from the gate command, a delay of about several ⁇ s to several tens of ⁇ s occurs.
  • the sum of the detection delay time up to the current detection means including the time constant of the low-puff filter (LPF) circuit 20 and the delay time in the gate driver (GD) circuit 26 is the main factor in the operation delay time.
  • the sampling period of the A/D converter 21 must be sufficiently short for the sum of .
  • FIG. 2 is a diagram showing a detailed configuration of the current detection means 22 in the control device 19 shown in FIG.
  • the current detection means 22 is synchronized with the A/D converter 21 and performs calculations at a sampling period of about several ⁇ s, so the processing is executed by hardware such as an integrated circuit such as ASIC or FPGA.
  • the signals input to the current detection means 22 are the output current detection values iuf, ivf, iwf sampled by the A/D converter 21 and the trigger signal Trig.
  • the trigger signal Trig is written every PWM control period by software that executes the rotational coordinate conversion means 23.
  • the write detection circuit 30 turns on the switches 39 to 42 (“set” in FIG. 2) at the timing when the output request is written to the trigger signal Trig, and buffers the contents of the delay elements (Z ⁇ 1 ) 35 to 38. After copying to (buf) 43 to 46, delay elements (Z ⁇ 1 ) 35 to 38 are cleared to zero (“clear” in FIG. 2).
  • Adders 31 to 33 and delay elements (Z ⁇ 1 ) 35 to 37 are used to configure an integration circuit for output current detection values iuf, ivf, and iwf. Furthermore, the adder 34 and the delay element (Z ⁇ 1 ) 38 constitute a counter that counts the number of integrations.
  • the outputs of the buffers (buf) 43 to 46 are output current integrated values ius, ivs, iws and the number of integrations N.
  • FIG. 3 is a diagram showing a detailed configuration of the rotational coordinate conversion means 23 in the control device 19 shown in FIG. 1.
  • the rotational coordinate conversion means 23 executes processing using software in a PWM control period. After writing an output request (request) to the trigger signal Trig only once during the PWM control period, the current detection means 22 is accessed to read the output current integrated values ius, ivs, iws and the number of integrations N.
  • the dividers 50 to 52 use the number of integrations N to obtain the average output current value of each of the output current integrated values ius, ivs, and iws.
  • the rotating coordinate converter 53 uses this output current average value to obtain the d/q axis current detection values Id and Iq.
  • FIG. 4 is a diagram showing a detailed configuration of the current control means (ACR) 24 in the control device 19 shown in FIG. 1.
  • the current control means (ACR) 24 executes processing using software in a PWM control period.
  • the PI controllers 60 and 61 for the d/q axes receive as input the d/q axis current command values Idp and Iqp and the d/q axis current detection values Id and Iq outputted by the rotational coordinate conversion means 23, respectively.
  • current control is performed to determine voltage operation amounts dVd and dVq on the d/q axes.
  • a voltage vector calculator (VECT) 62 inputs the voltage operation amounts dVd and dVq of the d/q axes and obtains voltage commands Vdp and Vqp of the d/q axes.
  • the stationary coordinate converter 63 obtains three-phase AC voltage commands vup, vvp, and vwp from the d/q-axis voltage commands Vdp, Vqp.
  • the present invention allows the sum of the detection delay time up to the current detection means and the operation delay time generated in the gate driver (GD) circuit 26 to be larger than the non-wrap period and minimum pulse width of the semiconductor switching element. Even if the current detection error is large, the current detection error can be reduced.
  • a gate driver (GD) circuit 26 is provided outside the power converter control device 19, and current detection errors can be reduced even when the operation delay time varies from individual to individual and changes slowly depending on temperature conditions and the like. Even if the operation delay time is unknown in the first place, it can be handled.
  • GD gate driver
  • a power converter using a semiconductor switching element having a plurality of gate signals was used as an example of the present invention, but a power converter using a general semiconductor switching element having a single gate signal is also applicable.
  • the gate driver circuits used to drive them are also required to have high breakdown voltages.As a result, the delay time of the insulation circuits that transmit gate signals tends to increase.
  • the embodiment of the present invention is an effective means.
  • FIG. 5 is a diagram showing an example of a current waveform when an AC motor is driven using a conventional technique.
  • the operation delay time of the semiconductor switching element is less than 1 ⁇ s.
  • the d/q-axis current detection values Id and Iq are affected by switching ripples and are approximately vertically symmetrical about the steady value of the d/q-axis current command value shown by the dotted line. It is vibrating.
  • the detected current values Id and Iq on the d/q axes are passed through a low-pass filter of approximately the electrical time constant (primary time constant) of the AC motor.
  • Id and Iq are shown as Id(LPF) and Iq(LPF). Note that the means for generating Id (LPF) and Iq (LPF) are not shown in the drawings because they are outside the scope of the present invention. As far as Id (LPF) and Iq (LPF) are concerned, it can be seen that the current detection values Id and Iq on the d/q axes do not regularly generate detection errors.
  • FIG. 6 is a diagram showing an example of a current waveform when an AC motor is driven using the conventional technology.
  • the operation delay time of the semiconductor switching element is 60 ⁇ s.
  • FIG. 6 unlike the case in FIG. 5, when looking at the q-axis current detection value Iq and Iq (LPF), it can be seen that a detection error has occurred on the q-axis current side. As a result, if current feedback control is enabled, a torque error will occur. On the other hand, it can be seen that no detection error occurs on the d-axis current side.
  • FIG. 7 is a diagram showing an example of a current waveform when an AC motor is driven using an embodiment of the present invention.
  • the operation delay time of the semiconductor switching element is 60 ⁇ s, as in the case of FIG.
  • FIG. 8 is a diagram showing the difference in current waveform of an AC motor depending on whether or not there is an operation delay of the semiconductor switching element.
  • current feedback control is disabled and feedforward control is performed.
  • the period from t1 to t2 has a downward slope, and during this period, pulses are raised in all three phases of UVW.
  • the period from t2 to t3 has an upward slope, and during this period, the pulses of all three phases of UVW fall.
  • the dotted lines are the voltage and current waveforms when there is no operation delay
  • the solid lines are the voltage and current waveforms when the operation delay is 60 ⁇ s. Since the three-phase AC voltages vu, vv, and vw are equally delayed, the detected value (A/D converted value) iuf of the U-phase current is also equally delayed.
  • times t1, t2, and t3 are the beginning of each PWM control cycle, and the output current is detected at these timings.
  • the detected value (A/D conversion value) iuf of the U-phase current the symbols shown in FIG. This is the detected value. Since the time rate of change di/dt of the current is negative, the detected current value appears to be small due to the operation delay.
  • FIG. 9 is a diagram showing operating waveforms of each element constituting the power converter control device according to the present invention when an AC motor is driven.
  • times t1, t2, and t3 indicate the beginning of each PWM control cycle.
  • the rotational coordinate conversion means 23 (FIGS. 1 and 3) writes an output request to the trigger signal Trig for the current detection means 22 (FIGS. 1 and 2).
  • the rising edge of the trigger signal Trig is simply used as an output request.
  • the current detection means 22 (FIGS. 1 and 2) receives a rising edge that is an output request of the trigger signal Trig, it turns on the switches 39 to 42 and transfers the contents of the delay elements 35 to 38 to the buffers 43 to 43. 46, and then clear the delay elements 35 to 38 to zero.
  • the counter shown in FIG. 9 is the output of the delay element 38 shown in FIG. 2, and indicates the number of integrations.
  • the counter value n1 immediately before time t1 is written into the buffer 46 as the number of integrations N, and the value n1 is held until time t2 when the next trigger signal Trig is written.
  • the counter increases from zero at a constant rate and reaches zero again at time t2.
  • the value n2 of the counter immediately before time t2 is written into the buffer 46 as the number of integrations N, and the value n2 is held until time t3.
  • the integrated value (integrator) shown in FIG. 9 is the output of the delay element 35 shown in FIG. 2, and is the integrated value of the U-phase current detection value (A/D conversion value) iuf.
  • the integrated value s1 immediately before time t1 is written into the buffer 43 as the U-phase current integrated value ius, and the value s1 is held until time t2.
  • the integrated value integrates the U-phase current detection value (A/D conversion value) iuf from zero, and becomes zero again at time t2.
  • the integrated value s2 immediately before time t2 is written into the buffer 43 as the U-phase current integrated value ius, and the value s2 is held until time t3 when the next trigger signal Trig is written. Further, although not shown in FIG. 9, the current integrated values of the V phase and W phase are also the same as in the case of the U phase described above.
  • the rotational coordinate conversion means 23 (FIGS. 1 and 3) is executed by software, after executing the dividers 50 to 52 shown in FIG. Find the q-axis current detection values Id and Iq. From this point on, the software uses the previously determined d/q axis current detection values Id and Iq to control the current by the current control means (ACR) 24 (Figs. 1 and 4) and the PWM control means 25 (Fig. 1). PWM control is performed sequentially. However, these series of software processes must be completed within the PWM control period.
  • the current detection means 22 (FIGS. 1 and 2), which performs high-speed sampling and integration, is implemented in hardware.
  • the rotational coordinate conversion means 23 (FIGS. 1 and 3), the current control means (ACR) 24 (FIGS. 1 and 4), the PWM control means 25 (FIG. 1), etc. perform sophisticated calculations that require processing time. Run in software.
  • the current detection means 22 for which high speed and timing are important, in hardware, it is possible to suppress the need to pay attention to timing in software processing. For example, as long as an output request is written to the trigger signal Trig at the beginning of each PWM control cycle, the three-phase current integrated values ius, ivs, iws and the number of integrations N can be set at any timing within the PWM control cycle. All you have to do is read it out.
  • the present invention is particularly useful for control using such a microcomputer.

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Abstract

Afin de réduire une erreur d'une valeur de détection de courant de sortie provoquée par l'influence d'un temps de retard d'un courant de sortie dans un circuit d'entrée et d'un temps de retard de fonctionnement d'un élément de commutation à semi-conducteur, et d'améliorer la réactivité de la commande de rétroaction de courant, la présente invention comprend : un moyen de détection de courant qui détecte un courant de sortie d'un convertisseur de puissance pour convertir une puissance c.c. en puissance c.a. à l'aide d'un élément de commutation à semi-conducteur ; un moyen de commande de courant qui génère une instruction de tension de sortie par l'intermédiaire d'une commande de courant sur la base de la sortie du moyen de détection de courant ; un moyen de commande PWM qui délivre une instruction de grille par rapport à l'élément de commutation à semi-conducteur sur la base de l'instruction de tension de sortie ; et un circuit d'attaque de grille qui génère, avec un retard de fonctionnement, un signal de grille pour commander la marche-arrêt de l'élément de commutation à semi-conducteur à partir de l'instruction de grille. Le moyen de détection de courant comporte une unité d'intégration de courant qui calcule une valeur intégrée de courant dans une période de temps d'intégration pour chaque cycle d'échantillonnage en utilisant une sortie d'un capteur de courant en tant que signal d'entrée. Le moyen de commande de courant effectue une commande de courant sur la base de la valeur intégrée de courant. Le moyen de détection de courant, le moyen de commande de courant et le moyen de commande PWM fonctionnent en synchronisation les uns avec les autres.
PCT/JP2023/020695 2022-06-17 2023-06-02 Dispositif de commande de convertisseur de puissance et procédé de commande WO2023243451A1 (fr)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006238637A (ja) * 2005-02-25 2006-09-07 Toshiba Corp インバータ装置
JP2012110074A (ja) * 2010-11-15 2012-06-07 Toshiba Corp 電流検出装置及びモータ制御装置
JP2017127046A (ja) * 2016-01-12 2017-07-20 三菱電機株式会社 電力変換器制御装置
JP2018113754A (ja) * 2017-01-10 2018-07-19 株式会社デンソー 交流電動機の制御装置
JP2019161720A (ja) * 2018-03-08 2019-09-19 株式会社日立製作所 インバータ装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006238637A (ja) * 2005-02-25 2006-09-07 Toshiba Corp インバータ装置
JP2012110074A (ja) * 2010-11-15 2012-06-07 Toshiba Corp 電流検出装置及びモータ制御装置
JP2017127046A (ja) * 2016-01-12 2017-07-20 三菱電機株式会社 電力変換器制御装置
JP2018113754A (ja) * 2017-01-10 2018-07-19 株式会社デンソー 交流電動機の制御装置
JP2019161720A (ja) * 2018-03-08 2019-09-19 株式会社日立製作所 インバータ装置

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