WO2023243451A1 - Power converter control device and control method - Google Patents

Power converter control device and control method Download PDF

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Publication number
WO2023243451A1
WO2023243451A1 PCT/JP2023/020695 JP2023020695W WO2023243451A1 WO 2023243451 A1 WO2023243451 A1 WO 2023243451A1 JP 2023020695 W JP2023020695 W JP 2023020695W WO 2023243451 A1 WO2023243451 A1 WO 2023243451A1
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current
power converter
output
gate
semiconductor switching
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PCT/JP2023/020695
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French (fr)
Japanese (ja)
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徹郎 児島
高志 伊君
直樹 栗原
比呂 中山
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株式会社日立製作所
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode

Definitions

  • the present invention relates to a power converter control device and control method.
  • the output voltage command is normalized with the DC power supply voltage to obtain a modulated wave.
  • the semiconductor switching element is driven by PWM control that outputs a pulse obtained by comparing this modulated wave and a carrier wave.
  • delay elements of detection timing include delay time due to an output current input circuit such as an output current sensor, an LPF circuit for noise removal, and an A/D converter. Furthermore, the operation delay time of the gate circuit that drives the semiconductor switching element and the semiconductor switching element itself can also be seen as the delay time of the detection timing. Therefore, it is necessary to consider both delay times in the same way.
  • Patent Document 1 and Patent Document 2 are known as techniques for accurately detecting the output current with respect to such detection timing delay elements.
  • Patent Document 3 and Patent Document 4 are known as gate circuits for driving a semiconductor switching element including such a plurality of gate terminals. Both technologies achieve low loss by providing a predetermined delay time within the gate circuit and completing the transition between the steady mode and the transient mode during this delay time.
  • Patent Document 1 assumes a delay time of about several ⁇ s, but the technique described in Patent Document 4 causes an operation delay of about 60 ⁇ s.
  • the output current is detected after being delayed by the operation delay time from the timing of the peaks and troughs of the carrier.
  • the operation delay time is as short as several ⁇ s, there is no problem, but if the operation delay time becomes long as in the technique described in Patent Document 4, the output current value detected within the control cycle cannot be used. In that case, the control cycle is carried over to the next control cycle, leading to an increase in dead time and affecting the responsiveness of the current feedback control.
  • the output current can be detected accurately, but the actual operation delay time may vary due to individual variations in semiconductor switching elements, current dependence of the operation delay time, etc. Therefore, errors may occur.
  • Patent Document 2 in order to avoid the influence of such variations in operation delay time, the output current is reduced for a period shorter than the period of peaks and troughs of the carrier, that is, shorter than a half period of the carrier. is sampled multiple times and the average value of these is used for current feedback control.
  • Patent Document 2 does not disclose the specific length of the sampling period and the timing of starting sampling.
  • the sampling period is shorter than the carrier half cycle, if the operation delay time is as short as a few ⁇ s, the sampling period will be symmetrical with respect to the timing of the peaks and troughs of the carrier.
  • the switching ripples are approximately symmetrical (the magnitude is the same but the sign is opposite) centering on the timing of the peak and valley of the carrier. Therefore, the magnitude of the output current can be accurately determined by canceling out the effects of switching ripples.
  • Another object of the present invention is to provide a technique that suppresses dead time and improves the responsiveness of current feedback control.
  • one of the representative power converter control devices of the present invention is a current detection device that detects the output current of a power converter that converts DC power into AC power using a semiconductor switching element.
  • current control means for generating an output voltage command of the power converter through current control based on the output of the current detection means; PWM control means for outputting a gate command for the semiconductor switching element based on the output voltage command;
  • the current detecting means is equipped with a gate driver circuit that generates a gate signal for turning on and off the element with an operation delay from the gate command, and the current detecting means uses the output of the current sensor provided on the output side of the power converter as an input signal, and controls the sampling period.
  • the current integrating section calculates the current integrated value for each integration period, the current controlling means performs current control based on the current integrated value, and the current detecting means, the current controlling means, and the PWM controlling means operate in synchronization. It is something to do.
  • FIG. 1 is a diagram showing an example of an AC motor drive device configured using a power converter control device according to the present invention
  • FIG. 2 is a diagram showing a detailed configuration of a current detection means in the control device shown in FIG. 1.
  • FIG. FIG. 2 is a diagram showing a detailed configuration of rotational coordinate conversion means in the control device shown in FIG. 1.
  • FIG. 2 is a diagram showing a detailed configuration of current control means in the control device shown in FIG. 1.
  • FIG. FIG. 2 is a diagram showing an example of a current waveform when an AC motor is driven using a conventional technique (operation delay time: less than 1 ⁇ s).
  • FIG. 2 is a diagram showing an example of a current waveform when an AC motor is driven using a conventional technique (operation delay time: 60 ⁇ s).
  • FIG. 2 is a diagram showing an example of a current waveform when an AC motor is driven using an embodiment of the present invention (operation delay time: 60 ⁇ s).
  • FIG. 3 is a diagram showing a difference in current waveform of an AC motor depending on whether or not there is an operation delay of a semiconductor switching element. It is a figure which shows the operating waveform of each element which comprises a control apparatus when an AC motor is driven using the control apparatus of the power converter which concerns on this invention.
  • FIG. 1 is a diagram showing an example of an AC motor drive device configured using a power converter control device according to the present invention.
  • a smoothing capacitor 10 that smoothes DC power supplied by a DC voltage source (not shown) and a bridge circuit configured by connecting semiconductor switching elements 11 and 12, 13 and 14, and 15 and 16 in series are connected in parallel. connected to form a power converter.
  • the AC output terminal of this bridge circuit is connected to an AC motor (MOTOR) 18, and a current sensor 17 detects the output current from the AC output terminal to the AC motor (MOTOR) 18.
  • the semiconductor switching elements 11 to 16 have two gate terminals (dual gates), and can switch between a mode for reducing conduction loss and a mode for reducing switching loss using two gate signals.
  • the output currents iu, iv, and iw detected by the current sensor 17 are input to a low-pass filter (LPF) circuit 20 that reduces surge noise and the like. Then, the output of the low-pass filter (LPF) circuit 20 is sampled using the A/D converter 21.
  • LPF low-pass filter
  • the current detection means 22 inputs iuf, ivf, and iwf output from the A/D converter 21 and the trigger signal Trig, and outputs the output current integrated values ius, ivs, iws and the number of integrations N.
  • the rotational coordinate conversion means 23 outputs a trigger signal Trig to the current detection means 22, reads the output current integrated values ius, ivs, iws and the number of integrations N from the A/D converter 21, calculates the output current average value, and calculates the rotational coordinate conversion means 23. Coordinate transformation is performed to output detected current values Id and Iq on the d/q axes.
  • the current control means (ACR) 24 performs current control using the detected current values Id and Iq on the d/q axes, generates a voltage vector, and then performs static coordinate transformation to obtain AC voltage commands vup, vvp, and vwp. Output.
  • the PWM control means 25 inputs the AC voltage commands vup, vvp, and vwp, normalizes them with the DC power supply voltage, compares them with a carrier wave, and performs PWM control to prevent short-circuiting between the upper arm and the lower arm that constitute the power converter.
  • Gate commands (Gpu to Gnw) are output by managing the non-wrapping time and minimum pulse width for prevention.
  • the gate driver (GD) circuit 26 receives gate commands (Gpu to Gnw) and generates first and second gate signals (Gpu1, 2 to Gnw1, 2) that drive the semiconductor switching elements 11 to 16.
  • the time constant of the low-pass filter (LPF) circuit 20 is about several ⁇ s to 10 ⁇ s, and the sampling period of the A/D converter 21 and the current detection means 22 is also about several ⁇ s.
  • the rotational coordinate conversion means 23, the current control means (ACR) 24, and the PWM control means 25 perform processing in the same PWM control period, which varies depending on the carrier frequency, but is generally on the order of several hundred ⁇ s to several ms.
  • the non-wrap time and minimum pulse width in the PWM control means 25 are both about several ⁇ s to 10 ⁇ s.
  • the gate driver (GD) circuit 26 When the gate driver (GD) circuit 26 generates the first and second gate signals from the gate command, a delay of about several ⁇ s to several tens of ⁇ s occurs.
  • the sum of the detection delay time up to the current detection means including the time constant of the low-puff filter (LPF) circuit 20 and the delay time in the gate driver (GD) circuit 26 is the main factor in the operation delay time.
  • the sampling period of the A/D converter 21 must be sufficiently short for the sum of .
  • FIG. 2 is a diagram showing a detailed configuration of the current detection means 22 in the control device 19 shown in FIG.
  • the current detection means 22 is synchronized with the A/D converter 21 and performs calculations at a sampling period of about several ⁇ s, so the processing is executed by hardware such as an integrated circuit such as ASIC or FPGA.
  • the signals input to the current detection means 22 are the output current detection values iuf, ivf, iwf sampled by the A/D converter 21 and the trigger signal Trig.
  • the trigger signal Trig is written every PWM control period by software that executes the rotational coordinate conversion means 23.
  • the write detection circuit 30 turns on the switches 39 to 42 (“set” in FIG. 2) at the timing when the output request is written to the trigger signal Trig, and buffers the contents of the delay elements (Z ⁇ 1 ) 35 to 38. After copying to (buf) 43 to 46, delay elements (Z ⁇ 1 ) 35 to 38 are cleared to zero (“clear” in FIG. 2).
  • Adders 31 to 33 and delay elements (Z ⁇ 1 ) 35 to 37 are used to configure an integration circuit for output current detection values iuf, ivf, and iwf. Furthermore, the adder 34 and the delay element (Z ⁇ 1 ) 38 constitute a counter that counts the number of integrations.
  • the outputs of the buffers (buf) 43 to 46 are output current integrated values ius, ivs, iws and the number of integrations N.
  • FIG. 3 is a diagram showing a detailed configuration of the rotational coordinate conversion means 23 in the control device 19 shown in FIG. 1.
  • the rotational coordinate conversion means 23 executes processing using software in a PWM control period. After writing an output request (request) to the trigger signal Trig only once during the PWM control period, the current detection means 22 is accessed to read the output current integrated values ius, ivs, iws and the number of integrations N.
  • the dividers 50 to 52 use the number of integrations N to obtain the average output current value of each of the output current integrated values ius, ivs, and iws.
  • the rotating coordinate converter 53 uses this output current average value to obtain the d/q axis current detection values Id and Iq.
  • FIG. 4 is a diagram showing a detailed configuration of the current control means (ACR) 24 in the control device 19 shown in FIG. 1.
  • the current control means (ACR) 24 executes processing using software in a PWM control period.
  • the PI controllers 60 and 61 for the d/q axes receive as input the d/q axis current command values Idp and Iqp and the d/q axis current detection values Id and Iq outputted by the rotational coordinate conversion means 23, respectively.
  • current control is performed to determine voltage operation amounts dVd and dVq on the d/q axes.
  • a voltage vector calculator (VECT) 62 inputs the voltage operation amounts dVd and dVq of the d/q axes and obtains voltage commands Vdp and Vqp of the d/q axes.
  • the stationary coordinate converter 63 obtains three-phase AC voltage commands vup, vvp, and vwp from the d/q-axis voltage commands Vdp, Vqp.
  • the present invention allows the sum of the detection delay time up to the current detection means and the operation delay time generated in the gate driver (GD) circuit 26 to be larger than the non-wrap period and minimum pulse width of the semiconductor switching element. Even if the current detection error is large, the current detection error can be reduced.
  • a gate driver (GD) circuit 26 is provided outside the power converter control device 19, and current detection errors can be reduced even when the operation delay time varies from individual to individual and changes slowly depending on temperature conditions and the like. Even if the operation delay time is unknown in the first place, it can be handled.
  • GD gate driver
  • a power converter using a semiconductor switching element having a plurality of gate signals was used as an example of the present invention, but a power converter using a general semiconductor switching element having a single gate signal is also applicable.
  • the gate driver circuits used to drive them are also required to have high breakdown voltages.As a result, the delay time of the insulation circuits that transmit gate signals tends to increase.
  • the embodiment of the present invention is an effective means.
  • FIG. 5 is a diagram showing an example of a current waveform when an AC motor is driven using a conventional technique.
  • the operation delay time of the semiconductor switching element is less than 1 ⁇ s.
  • the d/q-axis current detection values Id and Iq are affected by switching ripples and are approximately vertically symmetrical about the steady value of the d/q-axis current command value shown by the dotted line. It is vibrating.
  • the detected current values Id and Iq on the d/q axes are passed through a low-pass filter of approximately the electrical time constant (primary time constant) of the AC motor.
  • Id and Iq are shown as Id(LPF) and Iq(LPF). Note that the means for generating Id (LPF) and Iq (LPF) are not shown in the drawings because they are outside the scope of the present invention. As far as Id (LPF) and Iq (LPF) are concerned, it can be seen that the current detection values Id and Iq on the d/q axes do not regularly generate detection errors.
  • FIG. 6 is a diagram showing an example of a current waveform when an AC motor is driven using the conventional technology.
  • the operation delay time of the semiconductor switching element is 60 ⁇ s.
  • FIG. 6 unlike the case in FIG. 5, when looking at the q-axis current detection value Iq and Iq (LPF), it can be seen that a detection error has occurred on the q-axis current side. As a result, if current feedback control is enabled, a torque error will occur. On the other hand, it can be seen that no detection error occurs on the d-axis current side.
  • FIG. 7 is a diagram showing an example of a current waveform when an AC motor is driven using an embodiment of the present invention.
  • the operation delay time of the semiconductor switching element is 60 ⁇ s, as in the case of FIG.
  • FIG. 8 is a diagram showing the difference in current waveform of an AC motor depending on whether or not there is an operation delay of the semiconductor switching element.
  • current feedback control is disabled and feedforward control is performed.
  • the period from t1 to t2 has a downward slope, and during this period, pulses are raised in all three phases of UVW.
  • the period from t2 to t3 has an upward slope, and during this period, the pulses of all three phases of UVW fall.
  • the dotted lines are the voltage and current waveforms when there is no operation delay
  • the solid lines are the voltage and current waveforms when the operation delay is 60 ⁇ s. Since the three-phase AC voltages vu, vv, and vw are equally delayed, the detected value (A/D converted value) iuf of the U-phase current is also equally delayed.
  • times t1, t2, and t3 are the beginning of each PWM control cycle, and the output current is detected at these timings.
  • the detected value (A/D conversion value) iuf of the U-phase current the symbols shown in FIG. This is the detected value. Since the time rate of change di/dt of the current is negative, the detected current value appears to be small due to the operation delay.
  • FIG. 9 is a diagram showing operating waveforms of each element constituting the power converter control device according to the present invention when an AC motor is driven.
  • times t1, t2, and t3 indicate the beginning of each PWM control cycle.
  • the rotational coordinate conversion means 23 (FIGS. 1 and 3) writes an output request to the trigger signal Trig for the current detection means 22 (FIGS. 1 and 2).
  • the rising edge of the trigger signal Trig is simply used as an output request.
  • the current detection means 22 (FIGS. 1 and 2) receives a rising edge that is an output request of the trigger signal Trig, it turns on the switches 39 to 42 and transfers the contents of the delay elements 35 to 38 to the buffers 43 to 43. 46, and then clear the delay elements 35 to 38 to zero.
  • the counter shown in FIG. 9 is the output of the delay element 38 shown in FIG. 2, and indicates the number of integrations.
  • the counter value n1 immediately before time t1 is written into the buffer 46 as the number of integrations N, and the value n1 is held until time t2 when the next trigger signal Trig is written.
  • the counter increases from zero at a constant rate and reaches zero again at time t2.
  • the value n2 of the counter immediately before time t2 is written into the buffer 46 as the number of integrations N, and the value n2 is held until time t3.
  • the integrated value (integrator) shown in FIG. 9 is the output of the delay element 35 shown in FIG. 2, and is the integrated value of the U-phase current detection value (A/D conversion value) iuf.
  • the integrated value s1 immediately before time t1 is written into the buffer 43 as the U-phase current integrated value ius, and the value s1 is held until time t2.
  • the integrated value integrates the U-phase current detection value (A/D conversion value) iuf from zero, and becomes zero again at time t2.
  • the integrated value s2 immediately before time t2 is written into the buffer 43 as the U-phase current integrated value ius, and the value s2 is held until time t3 when the next trigger signal Trig is written. Further, although not shown in FIG. 9, the current integrated values of the V phase and W phase are also the same as in the case of the U phase described above.
  • the rotational coordinate conversion means 23 (FIGS. 1 and 3) is executed by software, after executing the dividers 50 to 52 shown in FIG. Find the q-axis current detection values Id and Iq. From this point on, the software uses the previously determined d/q axis current detection values Id and Iq to control the current by the current control means (ACR) 24 (Figs. 1 and 4) and the PWM control means 25 (Fig. 1). PWM control is performed sequentially. However, these series of software processes must be completed within the PWM control period.
  • the current detection means 22 (FIGS. 1 and 2), which performs high-speed sampling and integration, is implemented in hardware.
  • the rotational coordinate conversion means 23 (FIGS. 1 and 3), the current control means (ACR) 24 (FIGS. 1 and 4), the PWM control means 25 (FIG. 1), etc. perform sophisticated calculations that require processing time. Run in software.
  • the current detection means 22 for which high speed and timing are important, in hardware, it is possible to suppress the need to pay attention to timing in software processing. For example, as long as an output request is written to the trigger signal Trig at the beginning of each PWM control cycle, the three-phase current integrated values ius, ivs, iws and the number of integrations N can be set at any timing within the PWM control cycle. All you have to do is read it out.
  • the present invention is particularly useful for control using such a microcomputer.

Abstract

In order to reduce an error of an output current detection value caused by the influence of a delay time of an output current in an input circuit and an operation delay time of a semiconductor switching element, and to enhance responsiveness of current feedback control, the present invention comprises: a current detection means that detects an output current of a power convertor for converting DC power into AC power by using a semiconductor switching element; a current control means that generates an output voltage command through current control based on the output of the current detection means; a PWM control means that outputs a gate command with respect to the semiconductor switching element on the basis of the output voltage command; and a gate driver circuit that generates, with an operation delay, a gate signal for on-off driving the semiconductor switching element from the gate command. The current detection means has a current integration unit that calculates a current integrated value in an integration time period for each sampling cycle by using an output of a current sensor as an input signal. The current control means performs current control on the basis of the current integrated value. The current detection means, the current control means, and the PWM control means operate in synchronization with one another.

Description

電力変換器の制御装置および制御方法Power converter control device and control method
　本発明は、電力変換器の制御装置および制御方法に関する。 The present invention relates to a power converter control device and control method.
　一般的に、半導体スイッチング素子を用いた電力変換器が、直流電力を交流電力、あるいは交流電力を直流電力に変換する際には、出力電圧指令を直流電源電圧で正規化して変調波を求め、この変調波と搬送波とを比較して求めたパルスを出力するＰＷＭ制御によって半導体スイッチング素子を駆動している。 Generally, when a power converter using semiconductor switching elements converts DC power to AC power or AC power to DC power, the output voltage command is normalized with the DC power supply voltage to obtain a modulated wave. The semiconductor switching element is driven by PWM control that outputs a pulse obtained by comparing this modulated wave and a carrier wave.
　この電力変換器を交流電動機に接続して、交流電動機のトルク制御すなわち電流制御を行う場合、電力変換器の出力電流を正確に把握する必要がある。しかし、電力変換器の出力電流は、スイッチングのたびに激しく増減を繰り返すため（電流の時間変化率ｄｉ／ｄｔが大きいため）、検出のタイミングが僅かに遅れただけで大きな検出誤差が生じ、出力電流を正確に把握することが難しい。そして、出力電流に検出誤差を生じると、トルク精度の低下をもたらすことになる。 When this power converter is connected to an AC motor to perform torque control, that is, current control of the AC motor, it is necessary to accurately grasp the output current of the power converter. However, since the output current of a power converter repeats rapid increases and decreases each time it is switched (because the time rate of change di/dt of the current is large), even a slight delay in the detection timing causes a large detection error, and the output It is difficult to accurately determine the current. If a detection error occurs in the output current, this will result in a decrease in torque accuracy.
　従来、検出タイミングの遅延要素としては、出力電流センサ、ノイズ除去用のＬＰＦ回路、Ａ／Ｄ変換器などの出力電流の入力回路による遅延時間などがある。また、半導体スイッチング素子を駆動するゲート回路や半導体スイッチング素子自体の動作遅延時間も、検出タイミングの遅延時間として見える。そのため、両方の遅延時間については、同様に考慮する必要がある。 Conventionally, delay elements of detection timing include delay time due to an output current input circuit such as an output current sensor, an LPF circuit for noise removal, and an A/D converter. Furthermore, the operation delay time of the gate circuit that drives the semiconductor switching element and the semiconductor switching element itself can also be seen as the delay time of the detection timing. Therefore, it is necessary to consider both delay times in the same way.
　このような検出タイミングの遅延要素に対して、正確に出力電流を検出するための技術として、特許文献１および特許文献２に記載された技術が知られている。 The techniques described in Patent Document 1 and Patent Document 2 are known as techniques for accurately detecting the output current with respect to such detection timing delay elements.
　一方で、近年、半導体スイッチング素子に複数のゲート端子を設けた新しい半導体スイッチング素子が開発されている。この素子では、複数のゲート信号の組み合わせにより、導通状態での導通損失を低減するための定常モードと、導通状態から遮断状態あるいはその逆方向への遷移時のスイッチング損失を低減するための過渡モードを切り替えることにより、従来の半導体スイッチング素子に対して大幅な損失低下を図るものである。 On the other hand, in recent years, new semiconductor switching elements have been developed in which a semiconductor switching element is provided with a plurality of gate terminals. This device uses a combination of multiple gate signals to create a steady mode to reduce conduction loss in the conduction state, and a transient mode to reduce switching loss when transitioning from the conduction state to the cutoff state or vice versa. By switching, the loss can be significantly reduced compared to conventional semiconductor switching elements.
　このような複数のゲート端子を備えた半導体スイッチング素子を駆動するためのゲート回路として、特許文献３および特許文献４に記載された技術が知られている。いずれの技術も、ゲート回路内で所定の遅延時間を設け、この遅延時間の間に定常モードと過渡モード間の遷移を済ませることで低損失化を実現している。 The techniques described in Patent Document 3 and Patent Document 4 are known as gate circuits for driving a semiconductor switching element including such a plurality of gate terminals. Both technologies achieve low loss by providing a predetermined delay time within the gate circuit and completing the transition between the steady mode and the transient mode during this delay time.
特開２０１６－７２９９１号公報Japanese Patent Application Publication No. 2016-72991 特開２０１８－１１３７５４号公報Japanese Patent Application Publication No. 2018-113754 特開２０１５－２０４７２３号公報JP2015-204723A 特開２０１９－１０３２８６号公報JP2019-103286A
　ところが、上記した複数のゲート端子を備えた半導体スイッチング素子およびゲート回路を用いた電力変換器に対して、特許文献１に記載の技術を適用すると、出力電流検出に誤差が生じてしまう。特許文献１に記載の技術では、数μｓ程度の遅延時間を想定しているが、特許文献４に記載の技術では、６０μｓ程度の動作遅延が生じる。 However, if the technique described in Patent Document 1 is applied to a power converter using a semiconductor switching element and a gate circuit having a plurality of gate terminals described above, an error will occur in output current detection. The technique described in Patent Document 1 assumes a delay time of about several μs, but the technique described in Patent Document 4 causes an operation delay of about 60 μs.
　一般に、出力電圧が上昇するにつれてキャリアの山と谷のタイミングの近傍でスイッチングすることが多くなり、キャリアの山と谷のタイミングから動作遅延時間の間にスイッチングを行う場合が生じる。もしもこの場合のスイッチングを行ってしまうと、電圧印加による電流の時間変化率が大きくなるので、出力電流検出誤差そのものが大きくなること、また、一相だけスイッチングした状態であるかあるいは二相スイッチングした状態であるかによって電流変化の方向と大きさが不規則に変わるため、予見が困難であることから、特許文献１に記載の技術では、出力電流検出誤差を補正し切れないことになる。ただし、動作遅延時間が数μｓ程度と短く、半導体スイッチング素子の最小パルス幅よりも短い場合には、このような懸念は生じない。 In general, as the output voltage increases, switching is often performed near the timing of carrier peaks and troughs, and switching may occur between the timing of carrier peaks and troughs and the operation delay time. If switching is performed in this case, the rate of change of current over time due to voltage application will increase, so the output current detection error itself will increase, and if only one phase is switched or two phases are switched. Since the direction and magnitude of current change change irregularly depending on the state, it is difficult to predict, so the technique described in Patent Document 1 cannot fully correct the output current detection error. However, if the operation delay time is as short as several microseconds, which is shorter than the minimum pulse width of the semiconductor switching element, such concerns do not arise.
　一方、特許文献２に記載の第１～４の実施形態は、キャリアの山と谷のタイミングから動作遅延時間分だけ遅らせて出力電流検出を行うものである。しかし、動作遅延時間が数μｓ程度と短ければ問題はないが、特許文献４に記載の技術のように動作遅延時間が長くなると、制御サイクル内で検出した出力電流値を使用することができない。その場合、次の制御サイクルまで持ち越すことになるため、無駄時間の増加に繋がり、電流フィードバック制御の応答性に影響を与える。また、動作遅延時間の見積もりに誤差が無ければ正確に出力電流を検出することができるが、半導体スイッチング素子の個体ばらつきや動作遅延時間の電流依存性等により、実際の動作遅延時間が変動し得るため、誤差を生じる場合がある。 On the other hand, in the first to fourth embodiments described in Patent Document 2, the output current is detected after being delayed by the operation delay time from the timing of the peaks and troughs of the carrier. However, if the operation delay time is as short as several μs, there is no problem, but if the operation delay time becomes long as in the technique described in Patent Document 4, the output current value detected within the control cycle cannot be used. In that case, the control cycle is carried over to the next control cycle, leading to an increase in dead time and affecting the responsiveness of the current feedback control. In addition, if there is no error in the estimation of the operation delay time, the output current can be detected accurately, but the actual operation delay time may vary due to individual variations in semiconductor switching elements, current dependence of the operation delay time, etc. Therefore, errors may occur.
　更に、特許文献２に記載の第５の実施形態は、このような動作遅延時間のばらつきの影響を避けるため、キャリアの山と谷の周期以下、すなわちキャリア半周期よりも短い期間にわたり、出力電流を複数回サンプリングし、これらの平均値を電流フィードバック制御に用いるものである。ここで、特許文献２には、具体的なサンプリング期間の長さおよびサンプリング開始のタイミングが開示されていない。 Furthermore, in the fifth embodiment described in Patent Document 2, in order to avoid the influence of such variations in operation delay time, the output current is reduced for a period shorter than the period of peaks and troughs of the carrier, that is, shorter than a half period of the carrier. is sampled multiple times and the average value of these is used for current feedback control. Here, Patent Document 2 does not disclose the specific length of the sampling period and the timing of starting sampling.
　しかし、図面から察するに、たとえサンプリング期間がキャリア半周期よりも短くても、動作遅延時間が数μｓ程度と短ければ、キャリアの山と谷のタイミングを中心にして左右対称となるようにサンプリング期間を取ることにより、スイッチングリップルは、キャリアの山と谷のタイミングを中心にして概ね左右反対称（大きさは同じで符号が逆）である。そのため、スイッチングリップルの影響を相殺して正確に出力電流の大きさを求めることができる。 However, as can be seen from the drawing, even if the sampling period is shorter than the carrier half cycle, if the operation delay time is as short as a few μs, the sampling period will be symmetrical with respect to the timing of the peaks and troughs of the carrier. As a result, the switching ripples are approximately symmetrical (the magnitude is the same but the sign is opposite) centering on the timing of the peak and valley of the carrier. Therefore, the magnitude of the output current can be accurately determined by canceling out the effects of switching ripples.
　一方、動作遅延時間が長くなると対称とはみなせず、誤差を生じてしまう。また、制御演算をキャリアの山と谷の周期の先頭から開始しようとすると、平均値をただちに使用することができず、キャリア半周期の約１／２だけ待たされることになる。これも無駄時間の増加に繋がり、フィードバック制御の応答性に影響を与える。 On the other hand, if the operation delay time becomes long, it cannot be considered symmetrical and an error will occur. Furthermore, if the control calculation is to be started from the beginning of the cycle of peaks and troughs of the carrier, the average value cannot be used immediately and it will have to wait for about 1/2 of the carrier half cycle. This also leads to an increase in dead time and affects the responsiveness of feedback control.
　そこで、本発明では、電力変換器の制御装置において、電力変換器の出力電流を検出する入力回路での遅延時間や半導体スイッチング素子の動作遅延時間の影響による出力電流検出値の誤差を低減し、また、無駄時間を抑制して電流フィードバック制御の応答性を高める技術を提供することを目的とする。 Therefore, in the present invention, in a power converter control device, the error in the output current detection value due to the influence of the delay time in the input circuit that detects the output current of the power converter and the operation delay time of the semiconductor switching element is reduced, Another object of the present invention is to provide a technique that suppresses dead time and improves the responsiveness of current feedback control.
　上記した課題を解決するため、代表的な本発明の電力変換器の制御装置の一つは、半導体スイッチング素子を用いて直流電力を交流電力に変換する電力変換器の出力電流を検出する電流検出手段と、電流検出手段の出力に基づく電流制御により電力変換器の出力電圧指令を生成する電流制御手段と、出力電圧指令に基づいて半導体スイッチング素子に対するゲート指令を出力するＰＷＭ制御手段と、半導体スイッチング素子をオンオフ駆動するゲート信号をゲート指令から動作遅延を伴って生成するゲートドライバ回路とを備え、電流検出手段は、電力変換器の出力側に設けた電流センサの出力を入力信号として、サンプリング周期毎の積算期間の電流積算値を求める電流積算部を有し、電流制御手段は、電流積算値に基づいて電流制御を行い、電流検出手段と電流制御手段とＰＷＭ制御手段とは同期して動作するものである。 In order to solve the above-mentioned problems, one of the representative power converter control devices of the present invention is a current detection device that detects the output current of a power converter that converts DC power into AC power using a semiconductor switching element. current control means for generating an output voltage command of the power converter through current control based on the output of the current detection means; PWM control means for outputting a gate command for the semiconductor switching element based on the output voltage command; The current detecting means is equipped with a gate driver circuit that generates a gate signal for turning on and off the element with an operation delay from the gate command, and the current detecting means uses the output of the current sensor provided on the output side of the power converter as an input signal, and controls the sampling period. The current integrating section calculates the current integrated value for each integration period, the current controlling means performs current control based on the current integrated value, and the current detecting means, the current controlling means, and the PWM controlling means operate in synchronization. It is something to do.
　本発明によれば、出力電流の入力回路での遅延時間や半導体スイッチング素子の動作遅延時間の影響による出力電流検出値の誤差を低減することができる。また、無駄時間を抑制して電流フィードバック制御の応答性を高めることができる。
　上記した以外の課題、構成および効果は、以下の発明を実施するための形態における説明により明らかにされる。 According to the present invention, it is possible to reduce errors in the detected output current value due to the influence of the delay time of the output current in the input circuit and the operation delay time of the semiconductor switching element. Moreover, the responsiveness of current feedback control can be improved by suppressing dead time.
Problems, configurations, and effects other than those described above will be made clear by the description in the following detailed description.
本発明に係る電力変換器の制御装置を用いて交流電動機の駆動装置を構成した一例を示す図である。1 is a diagram showing an example of an AC motor drive device configured using a power converter control device according to the present invention; FIG. 図１に示す制御装置の中の電流検出手段の詳細な構成を示す図である。2 is a diagram showing a detailed configuration of a current detection means in the control device shown in FIG. 1. FIG. 図１に示す制御装置の中の回転座標変換手段の詳細な構成を示す図である。FIG. 2 is a diagram showing a detailed configuration of rotational coordinate conversion means in the control device shown in FIG. 1. FIG. 図１に示す制御装置の中の電流制御手段の詳細な構成を示す図である。2 is a diagram showing a detailed configuration of current control means in the control device shown in FIG. 1. FIG. 従来技術を用いて交流電動機を駆動した場合の電流波形の一例を示す図（動作遅延時間：１μｓ未満）である。FIG. 2 is a diagram showing an example of a current waveform when an AC motor is driven using a conventional technique (operation delay time: less than 1 μs). 従来技術を用いて交流電動機を駆動した場合の電流波形の一例を示す図（動作遅延時間：６０μｓ）である。FIG. 2 is a diagram showing an example of a current waveform when an AC motor is driven using a conventional technique (operation delay time: 60 μs). 本発明の実施例を用いて交流電動機を駆動した場合の電流波形の一例を示す図（動作遅延時間：６０μｓ）である。FIG. 2 is a diagram showing an example of a current waveform when an AC motor is driven using an embodiment of the present invention (operation delay time: 60 μs). 半導体スイッチング素子の動作遅延の有無による交流電動機の電流波形の差を示す図である。FIG. 3 is a diagram showing a difference in current waveform of an AC motor depending on whether or not there is an operation delay of a semiconductor switching element. 本発明に係る電力変換器の制御装置を用いて交流電動機を駆動した場合の制御装置を構成する各要素の動作波形を示す図である。It is a figure which shows the operating waveform of each element which comprises a control apparatus when an AC motor is driven using the control apparatus of the power converter which concerns on this invention.
　以下、本発明の実施例を、図面を用いて説明する。なお、この実施例により本発明が限定されるものではない。また、図面の記載において、同一部分には同一の符号を付して示している。 Embodiments of the present invention will be described below with reference to the drawings. Note that the present invention is not limited to this example. In addition, in the description of the drawings, the same parts are denoted by the same reference numerals.
　図１は、本発明に係る電力変換器の制御装置を用いて交流電動機の駆動装置を構成した一例を示す図である。
　図示しない直流電圧源が供給する直流電力を平滑化する平滑化コンデンサ１０と、半導体スイッチング素子１１と１２、１３と１４および１５と１６をそれぞれ直列に接続して構成されるブリッジ回路とが並列に接続されて電力変換器を構成する。このブリッジ回路の交流出力端子を交流電動機（ＭＯＴＯＲ）１８に接続し、交流出力端子から交流電動機（ＭＯＴＯＲ）１８への出力電流を電流センサ１７が検出する。 FIG. 1 is a diagram showing an example of an AC motor drive device configured using a power converter control device according to the present invention.
A smoothing capacitor 10 that smoothes DC power supplied by a DC voltage source (not shown) and a bridge circuit configured by connecting semiconductor switching elements 11 and 12, 13 and 14, and 15 and 16 in series are connected in parallel. connected to form a power converter. The AC output terminal of this bridge circuit is connected to an AC motor (MOTOR) 18, and a current sensor 17 detects the output current from the AC output terminal to the AC motor (MOTOR) 18.
　半導体スイッチング素子１１～１６は、２つのゲート端子（デュアルゲート）を持ち、２つのゲート信号を用いて導通損失を低減するモードまたはスイッチング損失を低減するモードを切り替えることができる。 The semiconductor switching elements 11 to 16 have two gate terminals (dual gates), and can switch between a mode for reducing conduction loss and a mode for reducing switching loss using two gate signals.
　電力変換器の制御装置１９（図１の破線で囲まれた部分）では、電流センサ１７が検出した出力電流ｉｕ、ｉｖおよびｉｗを、サージノイズなどを低減するローパスフィルタ（ＬＰＦ）回路２０に入力し、ローパスフィルタ（ＬＰＦ）回路２０の出力をＡ／Ｄ変換器２１を用いてサンプリングする。 In the power converter control device 19 (the part surrounded by the broken line in FIG. 1), the output currents iu, iv, and iw detected by the current sensor 17 are input to a low-pass filter (LPF) circuit 20 that reduces surge noise and the like. Then, the output of the low-pass filter (LPF) circuit 20 is sampled using the A/D converter 21.
　電流検出手段２２は、Ａ／Ｄ変換器２１が出力するｉｕｆ、ｉｖｆおよびｉｗｆと、トリガ信号Ｔｒｉｇとを入力して、出力電流積算値ｉｕｓ、ｉｖｓ、ｉｗｓおよび積算回数Ｎを出力する。 The current detection means 22 inputs iuf, ivf, and iwf output from the A/D converter 21 and the trigger signal Trig, and outputs the output current integrated values ius, ivs, iws and the number of integrations N.
　回転座標変換手段２３は、電流検出手段２２にトリガ信号Ｔｒｉｇを出力し、Ａ／Ｄ変換器２１から出力電流積算値ｉｕｓ、ｉｖｓ、ｉｗｓおよび積算回数Ｎを読み込んで出力電流平均値を求め、回転座標変換を行ってｄ／ｑ軸の電流検出値Ｉｄ、Ｉｑを出力する。 The rotational coordinate conversion means 23 outputs a trigger signal Trig to the current detection means 22, reads the output current integrated values ius, ivs, iws and the number of integrations N from the A/D converter 21, calculates the output current average value, and calculates the rotational coordinate conversion means 23. Coordinate transformation is performed to output detected current values Id and Iq on the d/q axes.
　電流制御手段（ＡＣＲ）２４は、ｄ／ｑ軸の電流検出値Ｉｄ、Ｉｑを用いて電流制御を行い、電圧ベクトルを生成した後、静止座標変換を行って交流電圧指令ｖｕｐ、ｖｖｐおよびｖｗｐを出力する。 The current control means (ACR) 24 performs current control using the detected current values Id and Iq on the d/q axes, generates a voltage vector, and then performs static coordinate transformation to obtain AC voltage commands vup, vvp, and vwp. Output.
　ＰＷＭ制御手段２５は、交流電圧指令ｖｕｐ、ｖｖｐおよびｖｗｐを入力し、直流電源電圧で正規化した後に搬送波と比較してＰＷＭ制御を行い、電力変換器を構成する上アームと下アームとの短絡防止のための非ラップ時間および最小パルス幅の管理を行ってゲート指令（Ｇｐｕ～Ｇｎｗ）を出力する。 The PWM control means 25 inputs the AC voltage commands vup, vvp, and vwp, normalizes them with the DC power supply voltage, compares them with a carrier wave, and performs PWM control to prevent short-circuiting between the upper arm and the lower arm that constitute the power converter. Gate commands (Gpu to Gnw) are output by managing the non-wrapping time and minimum pulse width for prevention.
　ゲートドライバ（ＧＤ）回路２６は、ゲート指令（Ｇｐｕ～Ｇｎｗ）を入力し、半導体スイッチング素子１１～１６を駆動する第１および第２のゲート信号（Ｇｐｕ１，２～Ｇｎｗ１，２）を生成する。 The gate driver (GD) circuit 26 receives gate commands (Gpu to Gnw) and generates first and second gate signals (Gpu1, 2 to Gnw1, 2) that drive the semiconductor switching elements 11 to 16.
　ここで、ローパスフィルタ（ＬＰＦ）回路２０の時定数は数μｓから１０μｓ程度、Ａ／Ｄ変換器２１および電流検出手段２２のサンプリング周期も数μｓ程度、である。 Here, the time constant of the low-pass filter (LPF) circuit 20 is about several μs to 10 μs, and the sampling period of the A/D converter 21 and the current detection means 22 is also about several μs.
　一方、回転座標変換手段２３、電流制御手段（ＡＣＲ）２４およびＰＷＭ制御手段２５は、同一のＰＷＭ制御周期で処理を行い、キャリア周波数によって変わるが、概ね数百μｓから数ｍｓのオーダーである。 On the other hand, the rotational coordinate conversion means 23, the current control means (ACR) 24, and the PWM control means 25 perform processing in the same PWM control period, which varies depending on the carrier frequency, but is generally on the order of several hundred μs to several ms.
　また、ＰＷＭ制御手段２５における非ラップ時間および最小パルス幅は、いずれも数μｓから１０μｓ程度である。ゲートドライバ（ＧＤ）回路２６がゲート指令から第１および第２のゲート信号を生成する際、数μｓから数十μｓ程度の遅延が生じる。 Furthermore, the non-wrap time and minimum pulse width in the PWM control means 25 are both about several μs to 10 μs. When the gate driver (GD) circuit 26 generates the first and second gate signals from the gate command, a delay of about several μs to several tens of μs occurs.
　ここで、ローパフフィルタ（ＬＰＦ）回路２０の時定数を含む電流検出手段までの検出遅延時間およびゲートドライバ（ＧＤ）回路２６での遅延時間の和が、主たる動作遅延時間の要因であり、これらの合計に対して、Ａ／Ｄ変換器２１のサンプリング周期は十分に短くなくてはならない。 Here, the sum of the detection delay time up to the current detection means including the time constant of the low-puff filter (LPF) circuit 20 and the delay time in the gate driver (GD) circuit 26 is the main factor in the operation delay time. The sampling period of the A/D converter 21 must be sufficiently short for the sum of .
　図２は、図１に示す制御装置１９の中の電流検出手段２２の詳細な構成を示す図である。
　電流検出手段２２は、Ａ／Ｄ変換器２１と同期し、数μｓ程度のサンプリング周期で演算するため、ＡＳＩＣやＦＰＧＡなどの集積回路によるハードウェアでもって処理を実行する。電流検出手段２２に入力される信号は、Ａ／Ｄ変換器２１がサンプリングした出力電流検出値ｉｕｆ、ｉｖｆ、ｉｗｆおよびトリガ信号Ｔｒｉｇである。 FIG. 2 is a diagram showing a detailed configuration of the current detection means 22 in the control device 19 shown in FIG.
The current detection means 22 is synchronized with the A/D converter 21 and performs calculations at a sampling period of about several μs, so the processing is executed by hardware such as an integrated circuit such as ASIC or FPGA. The signals input to the current detection means 22 are the output current detection values iuf, ivf, iwf sampled by the A/D converter 21 and the trigger signal Trig.
　トリガ信号Ｔｒｉｇは、回転座標変換手段２３を実行するソフトウェアによって、ＰＷＭ制御周期ごとに書き込まれる。書き込み検出回路３０は、トリガ信号Ｔｒｉｇに出力要求が書き込まれたタイミングで、スイッチ３９～４２をオンにし（図２では、「ｓｅｔ」）、遅延素子（Ｚ－１）３５～３８の内容をバッファ（ｂｕｆ）４３～４６にコピーした後に、遅延素子（Ｚ－１）３５～３８をゼロクリア（図２では、「ｃｌｅａｒ」）する。 The trigger signal Trig is written every PWM control period by software that executes the rotational coordinate conversion means 23. The write detection circuit 30 turns on the switches 39 to 42 (“set” in FIG. 2) at the timing when the output request is written to the trigger signal Trig, and buffers the contents of the delay elements (Z −1 ) 35 to 38. After copying to (buf) 43 to 46, delay elements (Z −1 ) 35 to 38 are cleared to zero (“clear” in FIG. 2).
　加算器３１～３３と遅延素子（Ｚ－１）３５～３７を用いて、出力電流検出値ｉｕｆ、ｉｖｆおよびｉｗｆの積算回路を構成する。また、加算器３４と遅延素子（Ｚ－１）３８を用いて、積算回数をカウントするカウンタを構成する。
　バッファ（ｂｕｆ）４３～４６それぞれの出力が、出力電流積算値ｉｕｓ、ｉｖｓ、ｉｗｓおよび積算回数Ｎとなる。 Adders 31 to 33 and delay elements (Z −1 ) 35 to 37 are used to configure an integration circuit for output current detection values iuf, ivf, and iwf. Furthermore, the adder 34 and the delay element (Z −1 ) 38 constitute a counter that counts the number of integrations.
The outputs of the buffers (buf) 43 to 46 are output current integrated values ius, ivs, iws and the number of integrations N.
　図３は、図１に示す制御装置１９の中の回転座標変換手段２３の詳細な構成を示す図である。
　回転座標変換手段２３は、ＰＷＭ制御周期でソフトウェアにより処理を実行する。ＰＷＭ制御周期中に、トリガ信号Ｔｒｉｇに出力要求（ｒｅｑｕｅｓｔ）を一度だけ書き込んだ後、電流検出手段２２にアクセスして、出力電流積算値ｉｕｓ、ｉｖｓ、ｉｗｓおよび積算回数Ｎを読み込む。 FIG. 3 is a diagram showing a detailed configuration of the rotational coordinate conversion means 23 in the control device 19 shown in FIG. 1. As shown in FIG.
The rotational coordinate conversion means 23 executes processing using software in a PWM control period. After writing an output request (request) to the trigger signal Trig only once during the PWM control period, the current detection means 22 is accessed to read the output current integrated values ius, ivs, iws and the number of integrations N.
　除算器５０～５２は、積算回数Ｎを用いて出力電流積算値ｉｕｓ、ｉｖｓおよびｉｗｓそれぞれの出力電流平均値を求める。
　回転座標変換器５３は、この出力電流平均値を用いてｄ／ｑ軸の電流検出値Ｉｄ、Ｉｑを求める。 The dividers 50 to 52 use the number of integrations N to obtain the average output current value of each of the output current integrated values ius, ivs, and iws.
The rotating coordinate converter 53 uses this output current average value to obtain the d/q axis current detection values Id and Iq.
　図４は、図１に示す制御装置１９の中の電流制御手段（ＡＣＲ）２４の詳細な構成を示す図である。
　電流制御手段（ＡＣＲ）２４は、ＰＷＭ制御周期でソフトウェアにより処理を実行する。ｄ／ｑ軸のＰＩ制御器６０、６１は、ｄ／ｑ軸の電流指令値Ｉｄｐ、Ｉｑｐと、回転座標変換手段２３が出力したｄ／ｑ軸の電流検出値Ｉｄ、Ｉｑとをそれぞれ入力とし、電流制御を行ってｄ／ｑ軸の電圧操作量ｄＶｄ、ｄＶｑを求める。 FIG. 4 is a diagram showing a detailed configuration of the current control means (ACR) 24 in the control device 19 shown in FIG. 1. As shown in FIG.
The current control means (ACR) 24 executes processing using software in a PWM control period. The PI controllers 60 and 61 for the d/q axes receive as input the d/q axis current command values Idp and Iqp and the d/q axis current detection values Id and Iq outputted by the rotational coordinate conversion means 23, respectively. , current control is performed to determine voltage operation amounts dVd and dVq on the d/q axes.
　電圧ベクトル演算器（ＶＥＣＴ）６２は、ｄ／ｑ軸の電圧操作量ｄＶｄ、ｄＶｑを入力して、ｄ／ｑ軸の電圧指令Ｖｄｐ、Ｖｑｐを求める。
　静止座標変換器６３は、ｄ／ｑ軸の電圧指令Ｖｄｐ、Ｖｑｐより三相交流電圧指令ｖｕｐ、ｖｖｐおよびｖｗｐを求める。 A voltage vector calculator (VECT) 62 inputs the voltage operation amounts dVd and dVq of the d/q axes and obtains voltage commands Vdp and Vqp of the d/q axes.
The stationary coordinate converter 63 obtains three-phase AC voltage commands vup, vvp, and vwp from the d/q-axis voltage commands Vdp, Vqp.
　本発明は、以上の構成により、電流検出手段までの検出遅延時間とゲートドライバ（ＧＤ）回路２６で発生する動作遅延時間との和が、半導体スイッチング素子の非ラップ期間や最小パルス幅に対して大きい場合においても、電流検出誤差を低減することができる。 With the above configuration, the present invention allows the sum of the detection delay time up to the current detection means and the operation delay time generated in the gate driver (GD) circuit 26 to be larger than the non-wrap period and minimum pulse width of the semiconductor switching element. Even if the current detection error is large, the current detection error can be reduced.
　また、電力変換器の制御装置１９の外部にゲートドライバ（ＧＤ）回路２６があり、動作遅延時間が個体でばらつき、温度条件などによって緩やかに変動する場合でも、電流検出誤差を低減できる。そもそも動作遅延時間が不明の場合でも、対応可能である。 In addition, a gate driver (GD) circuit 26 is provided outside the power converter control device 19, and current detection errors can be reduced even when the operation delay time varies from individual to individual and changes slowly depending on temperature conditions and the like. Even if the operation delay time is unknown in the first place, it can be handled.
　以上では、本発明の実施例として、複数のゲート信号を有する半導体スイッチング素子を用いた電力変換器を用いたが、単一のゲート信号を有する一般的な半導体スイッチング素子を用いた電力変換器にも適用可能である。特に、半導体スイッチング素子が高耐圧になると、これを駆動するためのゲートドライバ回路にも高耐圧が求められることから、結果として、ゲート信号を伝える絶縁回路の遅延時間が長くなる傾向にあるため、本発明の実施例は有効な手段である。 In the above, a power converter using a semiconductor switching element having a plurality of gate signals was used as an example of the present invention, but a power converter using a general semiconductor switching element having a single gate signal is also applicable. In particular, when semiconductor switching elements have high breakdown voltages, the gate driver circuits used to drive them are also required to have high breakdown voltages.As a result, the delay time of the insulation circuits that transmit gate signals tends to increase. The embodiment of the present invention is an effective means.
　図５は、従来技術を用いて交流電動機を駆動した場合の電流波形の一例を示す図である。ここで、半導体スイッチング素子の動作遅延時間は、１μｓ未満の場合である。
　特許文献１に記載の技術を用いて、ＰＷＭ制御周期の先頭で出力電流をサンプリングし、ＰＷＭ制御周期での移動平均値を求め、これを回転座標変換してｄ／ｑ軸の電流検出値Ｉｄ、Ｉｑを求めた場合に対応する。 FIG. 5 is a diagram showing an example of a current waveform when an AC motor is driven using a conventional technique. Here, the operation delay time of the semiconductor switching element is less than 1 μs.
Using the technology described in Patent Document 1, the output current is sampled at the beginning of the PWM control cycle, a moving average value in the PWM control cycle is obtained, and this is converted into rotational coordinates to obtain the d/q axis current detection value Id. , Iq is calculated.
　なお、電流検出誤差を調べるため、電流フィードバック制御を無効化し、フィードフォワード制御としている。モータ定数などの誤差もないので、ｄ／ｑ軸の電流指令値Ｉｄｐ、Ｉｑｐを比較することにより、電流検出誤差を調べることができる。 In addition, in order to investigate the current detection error, current feedback control was disabled and feedforward control was used. Since there is no error in the motor constant, etc., the current detection error can be investigated by comparing the d/q-axis current command values Idp and Iqp.
　ただし、発生トルクの僅かな差異により加速度が変わってしまうと、図６および図７に示す例と比較するのが難しくなるため、時刻ｔ０まで速度ゼロとし、時刻ｔ０から加速度一定で交流電動機の速度を引き上げるようにした。 However, if the acceleration changes due to a slight difference in the generated torque, it will be difficult to compare with the examples shown in FIGS. I tried to raise it.
　図５に示すとおり、従来技術によるｄ／ｑ軸の電流検出値Ｉｄ、Ｉｑは、スイッチングリップルの影響を受け、点線で示すｄ／ｑ軸の電流指令値の定常値を中心として、概ね上下対称に振動している。ここで、定常的には検出誤差が生じていないことを明示するために、ｄ／ｑ軸の電流検出値Ｉｄ、Ｉｑに交流電動機の電気時定数（一次時定数）程度のローパスフィルタを通したＩｄ、Ｉｑを、Ｉｄ（ＬＰＦ）、Ｉｑ（ＬＰＦ）として示す。なお、Ｉｄ（ＬＰＦ）とＩｑ（ＬＰＦ）の生成手段自体は、本発明の対象外であるため図面には図示していない。Ｉｄ（ＬＰＦ）、Ｉｑ（ＬＰＦ）を見る限り、ｄ／ｑ軸の電流検出値Ｉｄ、Ｉｑは、定常的には検出誤差を生じていないことが分かる。 As shown in Fig. 5, the d/q-axis current detection values Id and Iq according to the conventional technology are affected by switching ripples and are approximately vertically symmetrical about the steady value of the d/q-axis current command value shown by the dotted line. It is vibrating. Here, in order to clearly show that there is no detection error occurring on a steady basis, the detected current values Id and Iq on the d/q axes are passed through a low-pass filter of approximately the electrical time constant (primary time constant) of the AC motor. Id and Iq are shown as Id(LPF) and Iq(LPF). Note that the means for generating Id (LPF) and Iq (LPF) are not shown in the drawings because they are outside the scope of the present invention. As far as Id (LPF) and Iq (LPF) are concerned, it can be seen that the current detection values Id and Iq on the d/q axes do not regularly generate detection errors.
　図６は、図５の場合と同様に、従来技術を用いて交流電動機を駆動した場合の電流波形の一例を示す図である。ここで、半導体スイッチング素子の動作遅延時間は、６０μｓの場合である。 Similar to the case of FIG. 5, FIG. 6 is a diagram showing an example of a current waveform when an AC motor is driven using the conventional technology. Here, the operation delay time of the semiconductor switching element is 60 μs.
　図６では、図５の場合と異なり、ｑ軸電流検出値ＩｑおよびＩｑ（ＬＰＦ）を見ると、ｑ軸電流側には検出誤差が生じていることが分かる。この結果、電流フィードバック制御を有効にすると、逆にトルク誤差が生じることになる。一方、ｄ軸電流側には検出誤差が生じていないことが分かる。 In FIG. 6, unlike the case in FIG. 5, when looking at the q-axis current detection value Iq and Iq (LPF), it can be seen that a detection error has occurred on the q-axis current side. As a result, if current feedback control is enabled, a torque error will occur. On the other hand, it can be seen that no detection error occurs on the d-axis current side.
　図７は、本発明の実施例を用いて交流電動機を駆動した場合の電流波形の一例を示す図である。ここで、半導体スイッチング素子の動作遅延時間は、図６の場合と同様に６０μｓの場合である。 FIG. 7 is a diagram showing an example of a current waveform when an AC motor is driven using an embodiment of the present invention. Here, the operation delay time of the semiconductor switching element is 60 μs, as in the case of FIG.
　図７に示すＩｄ（ＬＰＦ）およびＩｑ（ＬＰＦ）を見ると、本発明の効果によりｄ／ｑ軸の電流検出値Ｉｄ、Ｉｑの両方ともに検出誤差を生じていないことが分かる。 Looking at Id (LPF) and Iq (LPF) shown in FIG. 7, it can be seen that due to the effects of the present invention, no detection error occurs in both the d/q axis current detection values Id and Iq.
　図８は、半導体スイッチング素子の動作遅延の有無による交流電動機の電流波形の差を示す図である。ここで、電流波形の差を調べるために、電流フィードバック制御を無効化し、フィードフォワード制御としている。 FIG. 8 is a diagram showing the difference in current waveform of an AC motor depending on whether or not there is an operation delay of the semiconductor switching element. Here, in order to examine the difference in current waveforms, current feedback control is disabled and feedforward control is performed.
　搬送波（Ｃａｒｒｉｅｒ）について、ｔ１～ｔ２の区間は下り勾配であり、この期間はＵＶＷの三相共にパルスを立ち上げる。一方、ｔ２～ｔ３の区間は上り勾配であり、この期間はＵＶＷの三相共にパルスを立ち下げる。 Regarding the carrier wave (Carrier), the period from t1 to t2 has a downward slope, and during this period, pulses are raised in all three phases of UVW. On the other hand, the period from t2 to t3 has an upward slope, and during this period, the pulses of all three phases of UVW fall.
　図８に示す波形の内で、点線が、動作遅延無しの場合の電圧および電流の波形であり、実線が、動作遅延６０μｓの場合の電圧および電流の波形である。三相交流電圧ｖｕ、ｖｖおよびｖｗが等しく遅延するため、Ｕ相電流の検出値（Ａ／Ｄ変換値）ｉｕｆも等しく遅延している。ここで、時刻ｔ１、ｔ２およびｔ３は、各ＰＷＭ制御周期の先頭であり、このタイミングで出力電流の検出を行う。 Among the waveforms shown in FIG. 8, the dotted lines are the voltage and current waveforms when there is no operation delay, and the solid lines are the voltage and current waveforms when the operation delay is 60 μs. Since the three-phase AC voltages vu, vv, and vw are equally delayed, the detected value (A/D converted value) iuf of the U-phase current is also equally delayed. Here, times t1, t2, and t3 are the beginning of each PWM control cycle, and the output current is detected at these timings.
　また、Ｕ相電流の検出値（Ａ／Ｄ変換値）ｉｕｆにおいて、図８に示す符号で、×印が動作遅延無しの場合の電流検出値であり、◇印が動作遅延６０μｓの場合の電流検出値である。電流の時間変化率ｄｉ／ｄｔが負のため、動作遅延によって電流検出値が小さくなったように見える。 In addition, in the detected value (A/D conversion value) iuf of the U-phase current, the symbols shown in FIG. This is the detected value. Since the time rate of change di/dt of the current is negative, the detected current value appears to be small due to the operation delay.
　図９は、本発明に係る電力変換器の制御装置を用いて交流電動機を駆動した場合に、この制御装置を構成する各要素の動作波形を示す図である。ここで、時刻ｔ１、ｔ２およびｔ３は、各ＰＷＭ制御周期の先頭を示している。 FIG. 9 is a diagram showing operating waveforms of each element constituting the power converter control device according to the present invention when an AC motor is driven. Here, times t1, t2, and t3 indicate the beginning of each PWM control cycle.
　各ＰＷＭ制御周期の先頭で、回転座標変換手段２３（図１および図３）は、電流検出手段２２（図１および図２）に対するトリガ信号Ｔｒｉｇに、出力要求（ｒｅｑｕｅｓｔ）を書き込む。本実施例では、単純にトリガ信号Ｔｒｉｇの立ち上がりエッジを出力要求（ｒｅｑｕｅｓｔ）とする。電流検出手段２２（図１および図２）は、トリガ信号Ｔｒｉｇの出力要求（ｒｅｑｕｅｓｔ）である立ち上がりエッジを受け取ると、スイッチ３９～４２をオンにして、遅延素子３５～３８の内容をバッファ４３～４６にコピーし、その後遅延素子３５～３８をゼロクリアする。 At the beginning of each PWM control period, the rotational coordinate conversion means 23 (FIGS. 1 and 3) writes an output request to the trigger signal Trig for the current detection means 22 (FIGS. 1 and 2). In this embodiment, the rising edge of the trigger signal Trig is simply used as an output request. When the current detection means 22 (FIGS. 1 and 2) receives a rising edge that is an output request of the trigger signal Trig, it turns on the switches 39 to 42 and transfers the contents of the delay elements 35 to 38 to the buffers 43 to 43. 46, and then clear the delay elements 35 to 38 to zero.
　図９に示すカウンタ（ｃｏｕｎｔｅｒ）は、図２に示す遅延素子３８の出力であり、積算回数を示す。時刻ｔ１において、時刻ｔ１直前のカウンタの値ｎ１が、バッファ４６に積算回数Ｎとして書き込まれ、次のトリガ信号Ｔｒｉｇが書き込まれる時刻ｔ２までその値ｎ１を保持する。ｔ１～ｔ２の区間において、カウンタ（ｃｏｕｎｔｅｒ）は、ゼロから一定のレートで増加し、時刻ｔ２で再びゼロになる。時刻ｔ２直前のカウンタの値ｎ２が、バッファ４６に積算回数Ｎとして書き込まれ、時刻ｔ３までその値ｎ２を保持する。 The counter shown in FIG. 9 is the output of the delay element 38 shown in FIG. 2, and indicates the number of integrations. At time t1, the counter value n1 immediately before time t1 is written into the buffer 46 as the number of integrations N, and the value n1 is held until time t2 when the next trigger signal Trig is written. In the interval from t1 to t2, the counter increases from zero at a constant rate and reaches zero again at time t2. The value n2 of the counter immediately before time t2 is written into the buffer 46 as the number of integrations N, and the value n2 is held until time t3.
　図９に示す積算値（ｉｎｔｅｇｒａｔｏｒ）は、図２に示す遅延素子３５の出力であり、Ｕ相電流検出値（Ａ／Ｄ変換値）ｉｕｆの積算値である。時刻ｔ１において、時刻ｔ１直前の積算値ｓ１が、バッファ４３にＵ相電流積算値ｉｕｓとして書き込まれ、時刻ｔ２までその値ｓ１を保持する。ｔ１～ｔ２の区間において、積算値は、ゼロからＵ相電流検出値（Ａ／Ｄ変換値）ｉｕｆを積算し、時刻ｔ２で再びゼロになる。時刻ｔ２直前の積算値の値ｓ２がバッファ４３にＵ相電流積算値ｉｕｓとして書き込まれ、次のトリガ信号Ｔｒｉｇが書き込まれる時刻ｔ３までその値ｓ２を保持する。また、図９では省略しているが、Ｖ相およびＷ相の電流積算値についても、上記したＵ相の場合と同様である。 The integrated value (integrator) shown in FIG. 9 is the output of the delay element 35 shown in FIG. 2, and is the integrated value of the U-phase current detection value (A/D conversion value) iuf. At time t1, the integrated value s1 immediately before time t1 is written into the buffer 43 as the U-phase current integrated value ius, and the value s1 is held until time t2. In the interval from t1 to t2, the integrated value integrates the U-phase current detection value (A/D conversion value) iuf from zero, and becomes zero again at time t2. The integrated value s2 immediately before time t2 is written into the buffer 43 as the U-phase current integrated value ius, and the value s2 is held until time t3 when the next trigger signal Trig is written. Further, although not shown in FIG. 9, the current integrated values of the V phase and W phase are also the same as in the case of the U phase described above.
　回転座標変換手段２３（図１および図３）は、ソフトウェアで実行するため、図３に示す除算器５０～５２を同時ではなく順番に逐次実行した後、回転座標変換器５３を用いてｄ／ｑ軸電流検出値Ｉｄ、Ｉｑを求める。これ以降もソフトウェアにより、先に求めたｄ／ｑ軸電流検出値Ｉｄ、Ｉｑを用いて、電流制御手段（ＡＣＲ）２４（図１および図４）による電流制御、ＰＷＭ制御手段２５（図１）によるＰＷＭ制御を順次行っていく。ただし、これら一連のソフトウェア処理は、ＰＷＭ制御周期内に完了しなくてはならない。 Since the rotational coordinate conversion means 23 (FIGS. 1 and 3) is executed by software, after executing the dividers 50 to 52 shown in FIG. Find the q-axis current detection values Id and Iq. From this point on, the software uses the previously determined d/q axis current detection values Id and Iq to control the current by the current control means (ACR) 24 (Figs. 1 and 4) and the PWM control means 25 (Fig. 1). PWM control is performed sequentially. However, these series of software processes must be completed within the PWM control period.
　本発明の実施例において、高速サンプリングおよび積算を行う電流検出手段２２（図１および図２）は、ハードウェアで実行する。一方で、回転座標変換手段２３（図１および図３）、電流制御手段（ＡＣＲ）２４（図１および図４）、ＰＷＭ制御手段２５（図１）などは、処理時間の要する高度な演算をソフトウェアで実行する。 In an embodiment of the invention, the current detection means 22 (FIGS. 1 and 2), which performs high-speed sampling and integration, is implemented in hardware. On the other hand, the rotational coordinate conversion means 23 (FIGS. 1 and 3), the current control means (ACR) 24 (FIGS. 1 and 4), the PWM control means 25 (FIG. 1), etc. perform sophisticated calculations that require processing time. Run in software.
　ここで、高速性およびタイミングが重要とある電流検出手段２２をハードウェアで実行することにより、ソフトウェアの処理はタイミングに注意を払う必要性を抑制することができる。例えば、各ＰＷＭ制御周期の先頭で、トリガ信号Ｔｒｉｇに出力要求（ｒｅｑｕｅｓｔ）を書き込みさえすれば、三相の電流積算値ｉｕｓ、ｉｖｓ、ｉｗｓおよび積算回数Ｎは、ＰＷＭ制御周期内の任意のタイミングで読み出せばよいことになる。 Here, by executing the current detection means 22, for which high speed and timing are important, in hardware, it is possible to suppress the need to pay attention to timing in software processing. For example, as long as an output request is written to the trigger signal Trig at the beginning of each PWM control cycle, the three-phase current integrated values ius, ivs, iws and the number of integrations N can be set at any timing within the PWM control cycle. All you have to do is read it out.
　近年では、キャッシュメモリを搭載したマイコンが増加し、平均的には高い処理能力を有する一方で、キャッシュミスヒット時など最悪の場合に処理タイミングを保証することが難しくなっている。このようなマイコンを使用した制御に対して、本発明は特に有用である。 In recent years, the number of microcomputers equipped with cache memory has increased, and while they have high processing power on average, it has become difficult to guarantee processing timing in the worst case, such as when a cache miss occurs. The present invention is particularly useful for control using such a microcomputer.
　以上、本発明の実施例について説明したが、本発明は、上述した実施例に限定されるものではなく、本発明の要旨を逸脱しない範囲において種々の変更が可能である。 Although the embodiments of the present invention have been described above, the present invention is not limited to the embodiments described above, and various changes can be made without departing from the gist of the present invention.
１０　平滑化コンデンサ、１１～１６　半導体スイッチング素子、１７　電流センサ、１８　交流電動機（ＭＯＴＯＲ）、１９　電力変換器の制御装置、２０　ローパスフィルタ（ＬＰＦ）回路、２１　Ａ／Ｄ変換器、２２　電流検出手段、２３　回転座標変換手段、２４　電流制御手段（ＡＣＲ）、２５　ＰＷＭ制御手段、２６　ゲートドライバ（ＧＤ）回路、３０　書き込み検出回路、３１～３４　加算器、３５～３８　遅延素子（Ｚ－１）、３９～４２　スイッチ、４３～４６　バッファ（ｂｕｆ）、５０～５２　除算器、５３　回転座標変換器、６０，６１　ｄ／ｑ軸のＰＩ制御器、６２　電圧ベクトル演算器（ＶＥＣＴ）、６３　静止座標変換器Ｇｐｕ，Ｇｐｕ，Ｇｐｗ　ゲートドライバ回路へのゲート指令（上アーム）、Ｇｎｕ，Ｇｎｕ，Ｇｎｗ　ゲートドライバ回路へのゲート指令（下アーム）、Ｇｐｕ１，Ｇｐｖ１，Ｇｐｗ１　半導体スイッチング素子への第１のゲート信号（上アーム）、Ｇｎｕ１，Ｇｎｖ１，Ｇｎｗ１　半導体スイッチング素子への第１のゲート信号（下アーム）、Ｇｐｕ２，Ｇｐｖ２，Ｇｐｗ２　半導体スイッチング素子への第２のゲート信号（上アーム）、Ｇｎｕ２，Ｇｎｖ２，Ｇｎｗ２　半導体スイッチング素子への第２のゲート信号（下アーム）、Ｉｄｐ，Ｉｑｐ　ｄ／ｑ軸の電流指令値、Ｉｄ，Ｉｑ　ｄ／ｑ軸の電流検出値、Ｉｄ（ＬＰＦ）、Ｉｑ（ＬＰＦ）　ｄ／ｑ軸の電流検出値（ＬＰＦ出力）、ｉｕ，ｉｖ，ｉｗ　電力変換器の出力電流、ｉｕｆ，ｉｖｆ，ｉｗｆ　出力電流のＡ／Ｄ変換値、ｉｕｓ，ｉｖｓ，ｉｗｓ　出力電流積算値、Ｎ　積算回数、Ｔｒｉｇ　トリガ信号、Ｖｄｐ，Ｖｑｐ　ｄ／ｑ軸の電圧指令、ｄＶｄ，ｄＶｑ　ｄ／ｑ軸の電圧操作量、ｖｕｐ，ｖｖｐ，ｖｗｐ　三相交流電圧指令、ｖｕ，ｖｖ，ｖｗ　三相交流電圧 10 smoothing capacitor, 11 to 16 semiconductor switching element, 17 current sensor, 18 AC motor (MOTOR), 19 power converter control device, 20 low-pass filter (LPF) circuit, 21 A/D converter, 22 current detection means , 23 rotational coordinate conversion means, 24 current control means (ACR), 25 PWM control means, 26 gate driver (GD) circuit, 30 write detection circuit, 31 to 34 adder, 35 to 38 delay element (Z -1 ), 39-42 Switch, 43-46 Buffer (buf), 50-52 Divider, 53 Rotating coordinate converter, 60, 61 d/q axis PI controller, 62 Voltage vector calculator (VECT), 63 Stationary coordinate conversion Gpu, Gpu, Gpw Gate command to the gate driver circuit (upper arm), Gnu, Gnu, Gnw Gate command to the gate driver circuit (lower arm), Gpu1, Gpv1, Gpw1 First gate signal to the semiconductor switching element (upper arm), Gnu1, Gnv1, Gnw1 First gate signal to semiconductor switching element (lower arm), Gpu2, Gpv2, Gpw2 Second gate signal to semiconductor switching element (upper arm), Gnu2, Gnv2, Gnw2 Second gate signal to semiconductor switching element (lower arm), Idp, Iqp d/q axis current command value, Id, Iq d/q axis current detection value, Id (LPF), Iq (LPF) d/ Q-axis current detection value (LPF output), iu, iv, iw Power converter output current, iuf, ivf, iwf A/D conversion value of output current, ius, ivs, iws Output current integrated value, N Number of integrations , Trig trigger signal, Vdp, Vqp d/q axis voltage command, dVd, dVq d/q axis voltage operation amount, vup, vvp, vwp three-phase AC voltage command, vu, vv, vw three-phase AC voltage

Claims (9)

  1. 　半導体スイッチング素子を用いて直流電力を交流電力に変換する電力変換器の出力電流を検出する電流検出手段と、
    　前記電流検出手段の出力に基づく電流制御により前記電力変換器の出力電圧指令を生成する電流制御手段と、
    　前記出力電圧指令に基づいて前記半導体スイッチング素子に対するゲート指令を出力するＰＷＭ制御手段と、
    　前記半導体スイッチング素子をオンオフ駆動するゲート信号を前記ゲート指令から動作遅延を伴って生成するゲートドライバ回路と
    を備え、
    　前記電流検出手段は、前記電力変換器の出力側に設けた電流センサの出力を入力信号として、サンプリング周期毎の積算期間の電流積算値を求める電流積算部を有し、
    　前記電流制御手段は、前記電流積算値に基づいて前記電流制御を行い、
    　前記電流検出手段と前記電流制御手段と前記ＰＷＭ制御手段とは同期して動作する
    ことを特徴とする電力変換器の制御装置。     Current detection means for detecting an output current of a power converter that converts DC power to AC power using a semiconductor switching element;
    Current control means that generates an output voltage command of the power converter by current control based on the output of the current detection means;
    PWM control means for outputting a gate command to the semiconductor switching element based on the output voltage command;
    a gate driver circuit that generates a gate signal for driving the semiconductor switching element on and off from the gate command with an operation delay;
    The current detection means has a current integration unit that uses the output of a current sensor provided on the output side of the power converter as an input signal to obtain an integrated current value in an integration period for each sampling period,
    The current control means performs the current control based on the current integrated value,
    A control device for a power converter, wherein the current detection means, the current control means, and the PWM control means operate in synchronization.
  2. 　請求項１に記載の電力変換器の制御装置であって、
    　前記電流積算部のサンプリング周期は、前記電流センサの出力から前記電流検出手段までの検出遅延の時間と前記ゲートドライバ回路の前記動作遅延の時間との和よりも短い
    ことを特徴とする電力変換器の制御装置。     The power converter control device according to claim 1,
    A power converter characterized in that the sampling period of the current integration section is shorter than the sum of the detection delay time from the output of the current sensor to the current detection means and the operation delay time of the gate driver circuit. control device.
  3. 　請求項１または請求項２に記載の電力変換器の制御装置であって、
    　前記電流センサの出力から前記電流検出手段までの検出遅延の時間と前記ゲートドライバ回路の前記動作遅延の時間との和が、前記半導体スイッチング素子の最小パルス幅よりも長い
    ことを特徴とする電力変換器の制御装置。     A control device for a power converter according to claim 1 or 2,
    Power conversion characterized in that the sum of the detection delay time from the output of the current sensor to the current detection means and the operation delay time of the gate driver circuit is longer than the minimum pulse width of the semiconductor switching element. device control device.
  4. 　請求項１から請求項３のいずれか１項に記載の電力変換器の制御装置であって、
    　前記電流検出手段による処理態様は、ハードウェアで実行され、
    　前記電流制御手段および前記ＰＷＭ制御手段による処理態様は、ソフトウェアで実行される
    ことを特徴とする電力変換器の制御装置。     A control device for a power converter according to any one of claims 1 to 3,
    The processing mode by the current detection means is executed by hardware,
    A control device for a power converter, characterized in that processing by the current control means and the PWM control means is executed by software.
  5. 　請求項１から請求項４のいずれか１項に記載の電力変換器の制御装置であって、
    　前記半導体スイッチング素子は、デュアルゲートを有する半導体素子である
    ことを特徴とする電力変換器の制御装置。     A control device for a power converter according to any one of claims 1 to 4,
    A control device for a power converter, wherein the semiconductor switching element is a semiconductor element having dual gates.
  6. 　請求項１から請求項５のいずれか１項に記載の電力変換器の制御装置であって、
    　前記電流積算部は、前記積算期間の電流積算値を求める積算回路と、前記積算期間の積算回数を数えるカウンタと、前記電流積算値および前記積算回数を記憶するバッファとを備え、出力要求を受け取る毎に当該出力要求の受け取り時点のサンプリング周期の前回周期終了時点の電流積算値および積算回数を前記バッファに書き込むと共に、当該電流積算値および当該積算回数をゼロクリアして前記積算回路および前記カウンタの動作を新たに開始し、
    　前記電流検出手段は、前記バッファから読み出した前記電流積算値および前記積算回数に基づいて前記積算期間の電流平均値を求め、
    　前記電流制御手段は、前記電流平均値を用いて前記電流制御を行う
    ことを特徴とする電力変換器の制御装置。     A control device for a power converter according to any one of claims 1 to 5,
    The current integration unit includes an integration circuit that calculates a current integration value in the integration period, a counter that counts the number of integrations in the integration period, and a buffer that stores the current integration value and the number of integrations, and receives an output request. At each time, the current integrated value and the number of integrations at the end of the previous sampling cycle at the time of receiving the output request are written into the buffer, and the current integrated value and the number of integrations are cleared to zero to operate the integration circuit and the counter. start anew,
    The current detection means calculates a current average value for the integration period based on the current integration value and the number of integrations read from the buffer,
    A control device for a power converter, wherein the current control means performs the current control using the average current value.
  7. 　直流電力を交流電力に変換する電力変換器を構成する半導体スイッチング素子がゲート指令から動作遅延を伴ったゲート信号によりオンオフ駆動される電力変換器の制御方法であって、
    　前記電力変換器の出力電流を、前記電力変換器の出力側に設けた電流センサの出力をサンプリング周期毎の積算期間の電流積算値として検出し、併せて前記積算期間の積算回数を求め、
    　前記電流積算値および前記積算回数に基づいて前記積算期間の電流平均値を求め、
    　前記電流平均値を用いた電流制御により前記電力変換器の出力電圧指令を生成し、
    　前記出力電圧指令に基づいてＰＷＭ制御により前記ゲート指令を生成し、
    　生成した前記ゲート指令からゲートドライバにより前記ゲート信号を生成する
    ことを特徴とする電力変換器の制御方法。     A method for controlling a power converter in which a semiconductor switching element constituting a power converter that converts DC power into AC power is turned on and off by a gate signal with an operation delay from a gate command, the method comprising:
    Detecting the output current of the power converter by detecting the output of a current sensor provided on the output side of the power converter as a current integrated value in an integration period for each sampling period, and also determining the number of integrations in the integration period,
    Determining a current average value for the integration period based on the current integration value and the number of integrations,
    Generate an output voltage command of the power converter by current control using the average current value,
    generating the gate command by PWM control based on the output voltage command;
    A method for controlling a power converter, characterized in that the gate signal is generated by a gate driver from the generated gate command.
  8. 　請求項７に記載の電力変換器の制御方法であって、
    　前記サンプリング周期は、前記電流センサによる検出遅延の時間と前記ゲートドライバが前記ゲート指令から前記ゲート信号を生成する際に伴う動作遅延の時間との和よりも短い
    ことを特徴とする電力変換器の制御方法。     A method for controlling a power converter according to claim 7,
    The power converter is characterized in that the sampling period is shorter than the sum of the detection delay time by the current sensor and the operation delay time accompanying when the gate driver generates the gate signal from the gate command. Control method.
  9. 　請求項７または請求項８に記載の電力変換器の制御方法であって、
    　前記電流センサによる検出遅延の時間と前記ゲートドライバが前記ゲート指令から前記ゲート信号を生成する際に伴う動作遅延の時間との和を、前記半導体スイッチング素子の最小パルス幅よりも長くする
    ことを特徴とする電力変換器の制御方法。     A method for controlling a power converter according to claim 7 or 8, comprising:
    The sum of the detection delay time by the current sensor and the operation delay time accompanying when the gate driver generates the gate signal from the gate command is made longer than the minimum pulse width of the semiconductor switching element. A method for controlling a power converter.
PCT/JP2023/020695 2022-06-17 2023-06-02 Power converter control device and control method WO2023243451A1 (en)

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JP2006238637A (en) * 2005-02-25 2006-09-07 Toshiba Corp Inverter apparatus
JP2012110074A (en) * 2010-11-15 2012-06-07 Toshiba Corp Current detection device and motor control device
JP2017127046A (en) * 2016-01-12 2017-07-20 三菱電機株式会社 Power converter control device
JP2018113754A (en) * 2017-01-10 2018-07-19 株式会社デンソー Controller for ac motor
JP2019161720A (en) * 2018-03-08 2019-09-19 株式会社日立製作所 Inverter device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006238637A (en) * 2005-02-25 2006-09-07 Toshiba Corp Inverter apparatus
JP2012110074A (en) * 2010-11-15 2012-06-07 Toshiba Corp Current detection device and motor control device
JP2017127046A (en) * 2016-01-12 2017-07-20 三菱電機株式会社 Power converter control device
JP2018113754A (en) * 2017-01-10 2018-07-19 株式会社デンソー Controller for ac motor
JP2019161720A (en) * 2018-03-08 2019-09-19 株式会社日立製作所 Inverter device

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