JP2011109848A - Motor drive control device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve phase-current detection by fixing a DC link current detection timing for phase-current detection to a prescribed timing without changing it according to a value of a voltage command signal so as to reduce a circuit and a process for controlling the current detection timing. <P>SOLUTION: A PWM means generates multiple-phase PWM signals in the following manner. A one-phase PWM signal is generated by subjecting multiple-phase voltage command signal whose value is updated at a prescribed timing to pulse-width modulation by a carrier signal. The pulse width of at least one-phase PWM signal is increased in the rear-end direction on the basis of the front end of an update cycle of a value of the voltage command signal according to an increase in value of the voltage command signal. The pulse width of at least one-phase PWM signal, different from the PWM signal whose pulse width is increased in the rear-end direction, is increased in the front-end direction on the basis of the rear end of the update cycle of the value of the voltage command signal according to the increase in value of the voltage command signal. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention uses only a current detection circuit that detects a DC link current flowing from a bridge circuit to a ground GND in a bridge circuit that supplies a drive current for rotationally driving a motor having a plurality of phase coils. The present invention relates to a motor drive control device that detects an alternating phase current flowing through a coil.

  The bridge circuit composed of a plurality of transistors and diodes is a circuit that converts a DC voltage into an AC voltage by pulse width modulation, and is used as an OA device as an inverter for driving a non-commutator motor of a synchronous motor or an induction motor. It is widely used in the fields of household electrical appliances and vehicle driving motors.

  When driving a motor using such a bridge circuit, in order to accurately control the torque generated by the motor, it is necessary to perform feedback control by detecting the AC fundamental wave component of the phase current flowing through the coils of each phase. For the detection of the phase current, a method of providing a current detection means for each phase of the detection motor and detecting the phase current of each phase is the easiest.

  However, since the provision of a plurality of current detection means causes a cost increase, the current detection means is provided only in the DC link portion of the bridge circuit, and a method of detecting the values of the phase currents of the plurality of phases from the detection value of the DC link current. Has been proposed.

This method will be described below with reference to FIGS.
First, FIG. 14 is a diagram showing the overall configuration of the apparatus. The motor 1 is a non-commutator type three-phase motor, which is composed of three phases of a U phase, a V phase, and a W phase having a phase difference of 120 degrees from each other, and the three phase coils are Y-connected, and the U phase , V-phase, and W-phase coil terminals are connected to the bridge circuit 2.

As shown in FIG. 15, the bridge circuit 2 is configured by three-phase connection of an upper arm 21 in which a switching element 25 and a diode 26 are connected in parallel and a lower arm 22 similarly configured. . The upper arm 21 is connected to a DC power source 31, the lower arm 22 is connected to a ground GND 32, and is connected to a coil of each phase of the motor 1 at a connection point between the upper arm 21 and the lower arm 22. Each switching element 25 is ON / OFF driven by a gate signal (UH, VH, WH, UL, VL, WL), applies a pulse-width modulated voltage to the coil of the motor 1, and supplies a drive current to the coil. The motor 1 is rotationally driven. At this time, the phase currents flowing through the three-phase coils are respectively iu, iv, and iw. The phase currents iu, iv, iw are positive when flowing from the bridge circuit 2 to the coil of the motor 1, and the coil is Y-connected, so the sum of the phase currents iu, iv, iw becomes zero according to Kirchhoff's first law. .

  As shown in FIG. 16, the gate signals UH, VH, and WH of the upper arm 21 and the gate signals UL, VL, and WL of the lower arm 22 are signals that are complementarily turned on / off for each phase. At the time of switching / OFF, a dead time of length td is provided in order to prevent destruction of the switching element due to the through current. The DC link current ig indicates a current flowing between the bridge circuit 2 and the GND 32, and the direction from the bridge circuit 2 to the GND 32 is positive.

  In the bridge circuit 2, the phase current of the phase in which the gate signals UH, VH, and WH of the upper arm are high (the switching element of the upper arm is in the ON state) is supplied from the DC power supply 31 to the GND 32 if the phase current is positive. If the phase current is negative, it is supplied from the GND 32 and flows to the DC power source 31. That is, the DC link current ig is a combination of the phase currents iu, iv, iw.

Here, the relationship between the DC link current ig and the phase current will be described using the gate signal of FIG. 16 as an example. When the section (a) is divided into the section (d) by the ON / OFF of the switching element 25 of the upper arm 21, the state of the switching element of the upper arm in each section is as follows:
Section (a): There is no phase where the switching element of the upper arm is in the ON state (b): Section where the switching element of the upper arm of the U phase is in the ON state (c): Switching of the upper arm of the U phase and V phase Section (d) in which the element is in the ON state: All upper arms of the three phases are in the ON state

At this time, the DC link current ig in each of the section (a) to the section (d) is as follows, and becomes a pulsed current for each section as shown in FIG.
Section (a): DC link current ig is zero Section (b): DC link current ig is iu Section (c): DC link current ig is the sum of iu and iv (d): DC link The current ig is zero. In the case of section (d), all the switching elements of the upper arm are in the ON state, and the current circulates in the bridge circuit and the coil, so that the DC link current becomes zero. .

  Based on the gate signals UH, VH, and WH of the upper arm 21, the DC current detection unit 4 is in a state where one or two phases of the switching element 25 of the upper arm 21 are ON, and the other switching elements of the upper arm 21 At two detection timings with 25 different ON / OFF states, the value of the DC link current ig is detected, and the detected values ia and ib of these two DC link currents are output.

The phase current detection means 5 detects the phase currents iu, iv, iw from the high / low of the gate signals UH, VH, WH and the DC link current detection values ia, ib. Specifically, the phase current value for two phases is detected from the DC link current detection values ia and ib and the ON / OFF state of the switching element 25 of the upper arm 21 at the detection timing, and the remaining one phase is detected. By calculating the phase current value based on Kirchhoff's first law, the value of the three-phase phase current can be detected. For example, taking FIG. 16 as an example, the phase currents iu, iv, and iw are detected from the detected values ia and ib of the DC link current ig detected in the sections (b) and (c) by the process shown in Equation 2. Can do. As described above, the phase current can be detected by detecting the current only in the DC link unit.

  As described above, in the multi-phase phase current detection method using one current detection unit, two-phase phase current values are detected based on the DC link current values detected at different timings, and the detected two-phase phases are detected. The current value of the remaining phase is calculated based on the current value and Kirchhoff's first law. However, the AC current output by the bridge circuit is a waveform in which a high-frequency pulsation component derived from the carrier frequency of pulse width modulation is superimposed on the AC fundamental wave component, and two-phase current detection is executed at different timings. Compared with the case where the current is detected at the same timing, an error occurs within the range of the magnitude of the high-frequency pulsation component.

  As described above, the current detection means is provided only in the DC link portion of the bridge circuit, and the method of detecting the values of the phase currents of the plurality of phases from the detected value of the DC link current cannot know the accurate value of the phase current. There is a problem, and particularly when the carrier period of pulse width modulation is long or when the time constant of the coil is small, the high-frequency pulsation component becomes large, and the phase current detection error may also become large.

  With respect to such a problem, in the inverter device described in Patent Document 1, a bridge circuit connected to a DC power source, a DC power source, and a bridge circuit are provided in the same manner as in the conventional technique in which the current detection means is provided only in the DC link unit. A current sensor for detecting a DC link current between the current and a switching element of the bridge circuit by ON / OFF by a pulse width modulated voltage signal to output an alternating current to the motor coil, and at the appropriate timing, the current sensor A control circuit for detecting a DC link current and detecting a phase current flowing through the coil, wherein the control circuit includes an ON signal to the switching element of the upper arm of the phase having the second ON time length or Using the OFF signal as a reference, phase currents for two phases are detected by the current detection means at timings before and after the reference. At this time, the control circuit sets the minimum necessary interval between the two DC link current detection timings so that accurate current detection is possible. The position can be accurately detected.

  However, according to the technique described in Patent Document 1, the detection timing of the DC link current is increased within one carrier period according to the pulse width of the gate signal for driving the switching element, that is, the value of the voltage command value subjected to pulse width modulation. As a result, the timing for completing the detection of the values of the three-phase phase currents also varies greatly within one carrier cycle.

At this time, there is a problem that the circuit and processing for controlling the DC link current detection timing according to the pulse width of the gate signal become complicated.
Further, the phase current component included in the detected DC link current is one phase or two phases, and the phase current is calculated from the value of the DC link current according to the ON / OFF state (the state of the gate signal) of the switching element. Since it is necessary to select a process, there is a problem that a circuit and a process become complicated.

  Further, the detected phase current value is used for control calculation, and the calculation result is reflected in the voltage command signal applied to the coil and fed back. At this time, the control calculation is generally executed as a periodic process on a microprocessor, and it is necessary to complete the control calculation before the next voltage command signal value update timing. The calculation process cannot be started until completion. Therefore, when the phase current detection is completed most slowly, that is, when the time allowed for execution of the control operation is the shortest, a periodic processing schedule is set up, which requires higher processor performance and increases the cost of the device. There is also the problem of becoming.

  The present invention has been made in view of the above-described problems, and the phase current detection is performed by fixing the DC link current detection timing for phase current detection to a predetermined timing without changing the timing according to the value of the voltage command signal. It is an object to reduce the number of circuits and processes that control current detection timing.

  The above problem consists of a plurality of switching elements 25 and diodes 26 connected to the positive side 31 or the negative side 32 of the DC power supply, and is driven by a motor 1 having a multi-phase coil by the on / off operation of the switching elements. A bridge circuit 2 for supplying a current; PWM means 6 for generating a multi-phase PWM (pulse width modulation) signal by pulse-width-modulating a multi-phase voltage command signal whose value is updated at a predetermined timing with a carrier signal Gate driving means 7 for generating a gate signal for driving the switching element of the bridge circuit based on the PWM signal; DC for detecting a DC link current value flowing between the DC power sources 31 and 32 and the bridge circuit 2; Current detection means 4; the DC link power detected by the DC current detection means 4 before and after the value update timing of the voltage command signal. And a phase current detection means 5 for detecting a phase current value flowing through a plurality of coils of the motor 1 based on the value and the PWM signal or gate signal; The pulse width of the signal increases in the rear end direction with reference to the front end of the value update period of the voltage command signal in accordance with the increase in the value of the voltage command signal, and the PWM signal whose pulse width increases in the rear end direction The PWM pulse width of the PWM signal of at least one phase different from the PWM signal is increased in the front end direction with reference to the rear end of the value update period of the voltage command signal as the value of the voltage command signal increases. The means 6 is solved by generating the PWM signal.

  It is assumed that the motor 1 is a three-phase motor and the voltage command signal is a two-phase modulated signal. The PWM means 6 includes pulse width limiting means 61 that limits the pulse width of at least two phases to a predetermined minimum value or more by expanding the pulse width of a signal obtained by pulse width modulation of the voltage command signal. Is preferable. At this time, the PWM means 6 is a voltage correction means for correcting the pulse width of the other phase so that the voltage vector for the expansion is zero or substantially zero with respect to the expansion of the pulse width by the pulse width limiting means 61. If it has 62, it is more effective.

  It is preferable that the DC current detection means 4 includes a high frequency cutoff filter 46 and a data acquisition unit 42 that detects output values of the high frequency cutoff filter. At this time, the data acquisition unit 42 may be A / D conversion means for A / D converting the output signal of the high-frequency cutoff filter 46. Further, in the detection of the DC link current that is performed by the DC current detection means 4 before and after the value update timing of the voltage command signal, the interval between the two current detections is determined by the data acquisition unit from the start of value acquisition. It is also preferable that it is more than the time required to output the detected result.

  Control calculation means for calculating a voltage command value for driving the motor based on the detected phase current value and reflecting the calculated voltage command value in the voltage command signal at the predetermined value update timing 8 is assumed. At this time, it is convenient for the control calculation means 8 to execute a current vector calculation based on the phase current value to calculate the voltage command value for driving the motor in vector control.

  In the invention according to claim 1, a drive current is supplied to a motor having a plurality of switching elements and diodes connected to the plus side or the minus side of a DC power source and having a plurality of phase coils by the on / off operation of the switching elements. A PWM circuit for generating a multi-phase PWM signal by pulse-width modulating a multi-phase voltage command signal whose value is updated at a predetermined timing with a carrier signal; based on the PWM signal Gate drive means for generating a gate signal for driving the switching element of the bridge circuit; DC current detection means for detecting a DC link current value flowing between the DC power supply and the bridge circuit; and updating the value of the voltage command signal The DC link current value detected by the DC current detection means before and after timing, and the PWM And a phase current detecting means for detecting a phase current value flowing through a plurality of coils of the motor based on a signal or a gate signal, and a pulse width of at least one phase PWM signal is a value of the voltage command signal In response to an increase in the pulse width of the PWM signal of at least one phase different from the PWM signal having a pulse width increased in the rear end direction with reference to the front end of the value update period of the voltage command signal. Since the PWM means generates the PWM signal so that the width increases in the front end direction with reference to the rear end of the value update period of the voltage command signal as the value of the voltage command signal increases, the motor The drive control device can detect the phase current even if the DC link current detection timing for detecting the phase current is fixed at a predetermined timing before and after the value update timing. Value it is not necessary to change the current detection timing in accordance with the item, it is possible to reduce the circuit and process for controlling the current detection timing.

  If the motor is a three-phase motor and the voltage command signal is a two-phase modulated signal, the DC link current value detected a plurality of times indicates only one of the phase current values. The process of detecting the phase current based on the DC link current value and the gate signal can be reduced.

  If the PWM means includes pulse width limiting means for expanding a pulse width of a signal obtained by pulse width modulation of the voltage command signal and limiting at least two phase pulse widths to a predetermined minimum value or more. Even when the voltage is small, stable detection can be maintained in the detection of the phase current by DC link current detection. At this time, the PWM means includes voltage correction means for correcting the pulse width of the other phase so that the voltage vector for the expansion becomes zero or substantially zero with respect to the expansion of the pulse width by the pulse width limiting means. If this is the case, in addition to the above-described effect, the voltage can be accurately applied to the coil in accordance with the voltage command signal, and the motor can be driven accurately.

  If the DC current detection means includes a high frequency cutoff filter and a data acquisition unit that detects the output value of the high frequency cutoff filter, it is possible to reduce the influence of noise such as ringing and accurately detect the current. it can. At this time, if the data acquisition unit is an A / D conversion means for A / D converting the output signal of the high frequency cutoff filter, a control calculation using a microprocessor is performed to detect the phase current value as digital data. Can be used easily. In addition, in the detection of the DC link current executed by the DC current detection means before and after the value update timing of the voltage command signal, the interval between two current detections is detected by the data acquisition unit from the start of value acquisition. If it is longer than the time required to output the result, the phase current can be detected by one current detection means, and the influence of the high-frequency pulsation component included in the phase current of the motor driven by PWM is reduced. Thus, the phase current can be detected with high accuracy.

  Control calculation means for calculating a voltage command value for driving the motor based on the detected phase current value and reflecting the calculated voltage command value in the voltage command signal at the predetermined value update timing Since the timing for completing the phase current detection based on the DC link current detection is substantially fixed within the carrier signal period, the control calculation schedule based on the detected phase current value is not variable, It can be almost fixed. At this time, if the control calculation means executes a current vector calculation based on the phase current value to calculate the voltage command value for vector control driving of the motor, a DC signal is generated within the carrier signal period. The timing for completing phase current detection by link current detection is almost fixed, and the current vector calculation processing schedule based on the detected phase current value can be almost fixed, so the calculation time margin in the processing schedule is reduced. Thus, even a low-performance processor can drive the motor in vector control.

It is a figure which shows the whole structure of the apparatus in Example 1. FIG. It is a figure which shows the waveform of the two-phase modulation | alteration of the voltage command signal in Example 1. It is a figure which shows the structure of the PWM means in Example 1. 4 is a flowchart showing the operation of a voltage command limiting unit in Example 1. 6 is a flowchart showing the operation of voltage correction means in Example 1. FIG. 6 is a diagram illustrating a signal of a leading phase in Example 1. FIG. 6 is a diagram showing a signal of a trailing phase in Example 1. 6 is a diagram illustrating a waveform of a PWM signal when the minimum voltage is limited in Example 1. FIG. It is a figure which shows the structure of the DC current detection means in Example 1. 3 is a diagram illustrating a configuration of a current detection circuit in Example 1. FIG. It is a figure which shows the timing of the DC link current sampling in Example 1. It is a figure which shows the whole structure of the apparatus in Example 2. FIG. It is a figure which shows the process schedule in Example 2. FIG. It is a figure which shows the whole structure of the apparatus in a prior art. It is a figure which shows the structure of the upper arm which comprises a bridge circuit. It is a figure which shows the example of a waveform of the gate signal and DC link current in a prior art.

(Example 1)
Hereinafter, the motor drive control device in this example will be described with reference to FIG. However, the same parts as those in the description of the prior art are given the same reference numerals, and the description is omitted in the description of the background art section. The motor 1, the bridge circuit 2, the DC power supply 31, the ground GND 32, and the like are as described with reference to FIGS. 14 to 16. The example 1 corresponds to the configuration according to claims 1 to 7.

  The voltage command signal Vm (Vmu, Vmv, Vmw) is a signal indicating the voltage value to be applied to the three-phase coil of the motor 1 and is two-phase modulated so that all three phases are non-negative and at least one phase is always zero. Signal. For example, FIG. 2 shows a sinusoidal waveform (upper diagram) having a phase difference of 120 degrees relative to each other whose amplitude is normalized and a waveform obtained by modulating it in two phases (lower diagram). This is a modulation process for keeping the voltage difference between the coil terminals equal, and the voltage command vectors are equivalent. In the voltage command signal Vm and a later-described voltage command signal, which will be described later, a phase having a zero signal value is referred to as a zero phase, and a phase having a non-zero value is referred to as a non-zero phase.

  As shown in FIG. 3, the PWM means 6 of the drive detecting means 10 is a voltage command limiting means for limiting the minimum value of the non-zero phase voltage command signal Vm with respect to the voltage command signal Vm (Vmu, Vmv, Vmw). 61, voltage correction means 62 for correcting the deviation of the voltage vector caused by the limiting process of the voltage command limiting means 61, and the corrected voltage command signal Vr output from the voltage correction means 62 is subjected to pulse width modulation based on the carrier signal. Modulation means 63 for outputting PWM signals Uon, Von, Won.

  Hereinafter, the details of each part constituting the PWM means 6 will be described. The voltage command limiting means 61 limits the value of the non-zero-phase voltage command signal to the minimum voltage Vth, which is a predetermined minimum value, with respect to the voltage command signal Vm subjected to the two-phase modulation, thereby limiting the voltage The command signal Vl (Vlu, Vlv, Vlw) is output.

  Hereinafter, the limiting process executed by the voltage command limiting unit 61 will be described with reference to FIG. First, from the value of the three-phase voltage command signal Vm, a phase having a value of zero is determined as a zero phase, and a phase having a positive value is determined as a non-zero phase. However, when the voltage command signal Vm has a plurality of zero-valued phases, any one phase is regarded as a zero phase and the rest are regarded as non-zero phases (S11). Next, with respect to the two non-zero phases, the phase with the smaller value of the voltage command signal is determined as the voltage minimum phase (S12). If the values are the same, one of them is determined as the minimum voltage phase. Next, if the value of the voltage command signal of the minimum voltage phase is less than the predetermined minimum voltage Vth, it is determined that the limiting process is “necessary”, and the process branches to the limiting process (S14). If the voltage minimum phase is equal to or higher than the predetermined minimum voltage Vth, it is determined as “No”, and the voltage command signal Vm (Vmu, Vmv, Vmw) is output as it is as the limited voltage command signal Vl (Vlu, Vlv, Vlw). The process is completed (S13). In the limiting process, the minimum voltage phase limited voltage command value Vl (any one of Vlu, Vlv, and Vlw) is output as the minimum voltage Vth. Further, in the other phase of the zero phase and the non-zero phase, the voltage command signal Vm (two corresponding to Vmu, Vmv, Vmw) is directly used as the limited voltage command signal Vl (2 corresponding to the Vlu, Vlv, Vlw). (S14).

The above is the limiting process in the voltage command limiting means 61, and the above process is executed at every value update timing of the voltage command signal Vm. For example, when the U phase and the V phase are non-zero phases, the W phase is a zero phase, the U phase is the minimum voltage phase, and the value of the voltage command signal Vmu is less than the minimum voltage Vth, the limiting process is As shown. Note that the voltage command limiting means 61 directly limits the value of the voltage command signal, which corresponds to limiting the pulse width of a pulse width modulated voltage, which will be described later.

  The voltage correction means 62 corrects the deviation of the voltage vector of the voltage command signal caused by the restriction process, and outputs a corrected voltage command signal Vr (Vru, Vrv, Vrw). However, the zero phase is not corrected in the corrected voltage command signal Vr, but only the correction amount is output and corrected by the PWM means described later.

  Hereinafter, the correction process performed by the voltage correction unit 62 will be described with reference to FIG. First, the values of the three-phase voltage command signal Vm and the limited voltage command signal Vl are compared to determine whether correction processing is necessary. If the values of all three phases are the same, the necessity of the correction process is “No”, the limited voltage command signal Vl is output as the corrected voltage command signal Vr, and the correction amount dV indicating the correction voltage value is zero. To complete the processing (S21). If there is a phase having a different value in the comparison, the necessity of the correction process is “necessary” and the process proceeds to the next process (S21). Next, the phase on which the voltage correction process is to be executed is determined (S22). In the comparison between the voltage command signal Vm and the limited voltage command signal Vl, the remaining one phase is determined as the correction phase except for the phase having a different signal value and the zero phase having the signal value of zero. Next, a voltage value to be corrected is calculated (S23). Correspondence of the voltage command signal Vm (Vmu, Vmv, Vmw) from the limited voltage command signal Vl (one corresponding to Vlu, Vlv, Vlw) in a phase having a different value of the signal (phase in which the restriction process is executed) The value obtained by subtracting one of the values is set as the correction amount dV, and the process proceeds to the next process. Next, the corrected voltage command signal Vr (Vru, Vrv, Vrw) is added by adding the correction amount dV to the corrected phase limited voltage command signal Vl (any one corresponding to Vlu, Vlv, Vlw). Any one of the corresponding) is output, and for the remaining phases, the limited voltage command signal Vl (two corresponding ones of Vlu, Vlv, and Vlw) is directly used as the corrected voltage command signal Vr (Vru, Vrv, Vrw). Are output (S24).

The above is the correction processing in the voltage correction means 62, and the above processing is executed for each value update timing of the limited voltage command signal Vl. For example, when the U phase and the V phase are non-zero phases, the W phase is a zero phase, and the voltage command limiting means 61 executes a limiting process on the U phase, the above correction process is as shown in Equation 4. It is. In order to correct the voltage vector, the zero-phase voltage command signal must also be corrected. This is corrected based on the correction amount dV in the PWM means 63 described later.

  The modulation means 63 performs pulse width modulation on the corrected voltage command signal Vr based on the carrier signal, and outputs PWM signals Uon, Von, Won. Hereinafter, details of the operation of the modulation means 63 will be described with reference to the drawings. First, the three-phase corrected voltage command signal Vr is a non-zero phase in which two phases are equal to or higher than the minimum voltage Vth, and the remaining one phase is a zero phase having a value of zero, by the limiting process of the voltage command limiting means 61. For two non-zero phases, one of them is a leading phase in which the pulse of the voltage command signal subjected to pulse width modulation is shifted to the front side within one carrier period, and the other is similarly set to the rear side. It will be the late phase that has been submitted.

  Hereinafter, the pulse width modulation of the leading phase will be described by taking the case where the U phase is the leading phase as an example. As shown in FIG. 6, during the period tpwm, the value increases from 0 to the power supply voltage Vcc between the value update timing (v) of the periodic corrected voltage command signal Vr and the next value update timing (v). The PWM signal Uon is generated by comparing the sawtooth carrier signal Vcf with the corrected voltage command signal Vru.

Similarly, the pulse width modulation of the trailing phase will be described by taking the case where the phase before the V phase is the trailing phase as an example. As shown in FIG. 7, during the period tpwm, the value decreases from the power supply voltage Vcc to 0 between the value update timing (v) of the periodic corrected voltage command signal Vr and the next value update timing (v). The PWM signal Von is generated by comparing the sawtooth carrier signal Vcb with the corrected voltage command signal Vrv. At this time, since the value of the two-phase limited voltage command signal Vr that is a non-zero phase is always equal to or greater than the minimum voltage Vth, the minimum pulse width of the non-zero-phase PWM signal is the minimum pulse width th shown in Equation 5. That's it. It is assumed that the value update timing (v) in FIGS. 6 and 7 indicates the same timing.

Although not shown, an update signal vtrig indicating the update timing (v) is output.
Hereinafter, the process of the modulation means 63 for the zero phase will be described by taking the case where the W phase is the zero phase as an example. When the correction amount dV is 0, the PWM signal Won does not output any pulse. On the other hand, when the correction amount dV is non-zero, a signal obtained by subjecting the correction amount dV to pulse width modulation is output as the PWM signal Won. At this time, the relationship between the pulse width tz of the PWM signal Won and the correction amount dV is expressed by Equation 6. However, the pulse generation timing within one carrier cycle is set so as not to overlap with the timing of current sampling in DC link current detection described later.

  As an example, FIG. 8 shows a waveform example of a PWM signal when the U phase and the V phase are non-zero phases and the limiting process is executed on the V phase. In FIG. 8, the diagonally shaded portion of the PWM signal Von is the amount by which the minimum value of the voltage command value is limited by the limiting process, and as a result, the pulse width is increased. The shaded portions of the PWM signals Uon and Won are corrected by the correcting process. As a result, the increase in the pulse width is shown. Note that the maximum pulse width of the zero-phase PWM signal Won is equal to the minimum pulse width of the non-zero phase shown in Equation 5. The correction of the voltage vector generated in the limiting process is corrected by the correction process and the zero-phase process.

The above is the description of the operation of the modulation means 63.
Returning again to the description of the apparatus of this example using FIG.
The gate driving means 7 generates gate signals for driving the switching elements of the upper arm 21 and the lower arm 22 of the bridge circuit 2 for each phase with respect to the PWM signals Uon, Von, Won.

  The U phase will be described in detail as an example. As shown in FIG. 6, the gate signal UH of the switching element of the upper arm 21 rises with a delay td of the dead time from the rise of the PWM signal Uon. The signal Uon is generated so as to fall with a delay of the dead time length td from the falling of the signal Uon. The gate signal UL of the switching element of the lower arm 22 falls in synchronization with the rise of the PWM signal Uon, and is generated so as to rise with a delay of twice the dead time length td from the fall of the PWM signal Uon. Let The dead time is a section provided to prevent the switching element from being destroyed by a through current, and the length td is a fixed value. The above operation is performed in the same manner for the other phases regardless of the difference between the preceding phase, the trailing phase, and the zero phase.

  At this time, the pulse of the gate signal of the upper arm of the trailing phase in a certain carrier cycle and the pulse of the gate signal of the upper arm of the leading phase in the next carrier cycle in which the value of the voltage command signal is updated are always adjacent. It is supposed to be. As shown in FIG. 8, the modulation means 63 is configured so that the pulses of the non-zero-phase PWM signals Uon and Von are always adjacent to each other at the value update timing (v). Since the signal is a signal delayed from the PWM signal by the dead time length td, the pulses of both signals are adjacent to each other in the gate signal of the upper arm.

  As shown in FIG. 9, the DC current detection means 4 samples a current detection circuit 41 for detecting the DC link current ig of the bridge circuit 2 and the output of the current detection circuit 41 at a predetermined timing to obtain DC link current data. A data acquisition unit 42 for acquiring and outputting the data.

  Hereinafter, the details of each part constituting the DC current detection means 4 will be described. As shown in FIG. 10, the current detection circuit 41 is provided between the bridge circuit 2 and the GND 32. The current detection circuit 41 detects a current value by using a voltage drop caused by a current flowing through the resistor, and a resistor and a capacitor. And an amplifier 47 for amplifying and level-shifting the output of the LPF 46 and outputting a current detection signal idet. Note that the LPF 46 in this example is arranged at the front stage of the amplifier 47, but may be arranged at the rear stage.

  The data acquisition unit 42 includes an A / D converter, samples and A / D-converts the current detection signal idet twice continuously at a predetermined timing based on the update signal vtrig indicating the update timing (v), The detected DC link current data dia and dib are output.

  Hereinafter, sampling timing will be described with reference to FIG. However, as shown in FIG. 11, description will be made using signal names corresponding to the case where the U phase is the leading phase, the V phase is the trailing phase, and the W phase is the zero phase. First, a timing delayed by a dead time length td from a value update timing (v) indicated by the update signal vtrig is set as a gate update timing (p). The gate update timing (p) is a point at which the pulse of the trailing phase gate signal VH and the leading phase gate signal UH are adjacent to each other. When the value of the voltage command signal is updated, the updated value is It means that it is reflected in the gate signal from the update timing (p). When the gate signal VH is high, only the phase current iv flows in the DC link current ig. When the gate signal UH is high, only the phase current iu is included in the DC link current ig at the gate update timing (p). Flows.

  The data acquisition unit 42 performs two consecutive samplings at a predetermined timing based on the update signal vtrig. At this time, the predetermined timing is set so as to satisfy the following five conditions.

  The first condition is that the first sampling (sa) is executed while the gate signal VH is high, and the second sampling occurs when the gate signal UH generated after the gate update timing (p) is high. Sampling (sb) is executed. As a result, the DC link current ig at the time of the two samplings (sa) and (sb) is always one of the phase currents, so that the process of detecting the phase current value described later can be simplified.

  The second condition is that the data acquisition unit 42 samples the current detection signal idet and outputs an A / D conversion result at a sampling interval ts which is the length between two samplings (sa) and (sb). Set the time longer than the time required. Thereby, it is possible to perform sampling twice with one detection means.

  The third condition is that the first sampling (sa) is set to a timing delayed by the rise time of the LPF from the rising edge of the gate signal VH of the upper arm, and the second sampling (sb) is changed to the gate update. It is set to a timing delayed by a similar time or more from the timing (p). As a result, the sampling is performed after waiting for the signal of the current detection signal idet passing through the LPF 46 to rise, so that accurate current detection is possible.

  The fourth condition is that the samplings (sa) and (sb) are set within the minimum pulse width th from the gate update timing (p). As a result, only one of the DC link currents during the sampling always flows, and there is no need to change the sampling timing in accordance with the value of the voltage command signal.

  The fifth condition is to set the sampling interval ts as short as possible while satisfying the above four conditions. As a result, it is possible to perform current detection that reduces the influence of high-frequency component pulsation superimposed on the phase current waveform during PWM driving.

  The above is the description of the timing at which the data acquisition unit 42 samples the current detection signal idet. The current detection timing in this example is assumed to be fixed within one carrier cycle, but is not limited to this, and may be variable within the range satisfying the above five conditions. Need not be changed according to the value of the voltage command signal, and the timing may be freely changed within the range of the above conditions.

  Finally, the data acquisition unit 42 outputs the A / D conversion results in the two samplings (sa) and (sb) as DC link current data dia and dib, respectively. The above is the configuration of the DC current detection unit 4.

  The phase current detection means 5 detects the phase current values of the three phases based on the DC link current data dia, dib, the upper arm gate signals UH, VH, WH, and the update signal vtrig, and the phase current data diu, div , Diw are output.

  Details of the operation of the phase current detection means 5 will be described below. First, as described in the explanation of the DC current detection means 4, the DC link current data dia and dib are always detected values of the phase current of only one of the U phase, V phase, and W phase, and the sampling The phase current values of the phases in which the signal level of the gate signal of the upper arm is high at the timings (sa) and (sb) are shown.

  Using the above relationship, the phase current detection means 5 monitors the upper arm gate signals UH, VH, WH at the timing of the sampling (sa), (sb) based on the update signal vtrig, It is determined which phase current each of the link current data dia and dib indicates, and then, based on the determined two-phase phase current value and Kirchhoff's first law shown in Equation 1, the remaining 1 The phase current values of the phases are calculated, and finally, the detected phase current values of the three phases are output as phase current data diu, div, diw.

  The above is the configuration of the apparatus in this example. In the present example, the value update timing of the voltage command signal of the present invention corresponds to the gate update timing (p), which is a boundary where the pulses are adjacent to each other in the gate signal of the upper arm of the front approach phase and the rear approach phase. However, the present invention is not limited to this. If the signal indicates a voltage command value to be applied to the coil terminal, the voltage command signal Vm, the limited voltage command signal Vl, the corrected voltage command signal Vr, the PWM signals Uon, Von, Any of Won may be used.

  As described above, according to the present example, in the method of detecting the three-phase phase current by detecting the DC link current a plurality of times, the high frequency superimposed on the phase current waveform by setting the detection timing to the minimum. In addition to the conventional effect of reducing the influence of pulsation, the DC link current detection timing within one carrier period can be fixed, so that a complicated circuit for controlling the detection timing can be dispensed with, and twice Since the pulse width modulation method and the DC link current detection timing are set so that the current value detected at the time of DC link current sampling always includes only the phase current for one phase, the phase current is determined from a plurality of detected DC link currents. Processing to detect a value can be reduced.

(Example 2)
Next, a motor drive control device according to another example will be described with reference to FIG. However, the description common to the prior art and Example 1 is omitted. Example 2 corresponds to the configuration according to claims 8 and 9.

  The motor 1 is as described in the background section above. As shown in FIG. 1, the drive detection means 10 is composed of a bridge circuit 2, a DC power supply 31, a ground GND 32, a DC current detection means 4, a phase current detection means 5, a PWM means 6, and a gate drive means 7. Is the same as in Example 1 above. That is, a phase for applying a pulse width modulated voltage to the coil terminal of the motor 1 in accordance with the value of the two-phase modulated voltage command signal Vm input from the two-phase modulator 9 to rotationally drive the motor. Currents iu, iv and iw are supplied. Also, three-phase phase current data diu, div, diw detected based on the detection of the DC link current is output.

The Hall IC 15 periodically repeats binary high / low in synchronization with the rotor angle of the motor 1 and outputs a Hall signal hg in which the edge of the signal indicates the absolute value of the rotor angle.
The encoder 16 is a rotary encoder connected to the rotating shaft of the motor 1 and outputs a pulsed encoder signal Enc according to a change in the rotor angle. Further, it is assumed that the number of signal periods output per one rotation of the rotor is larger than the Hall signal hg of the Hall IC 15.

  The angle detector 17 counts the number of pulses of the encoder signal Enc with reference to the edge of the Hall signal hg indicating the rotor position, and outputs angle data θ indicating the absolute value of the rotor angle with high resolution.

  The control calculation means 8 includes a target frequency generator 81, a frequency comparator 82, a target current generator 83, a 3-axis 2-axis coordinate converter 85, a q-axis current controller 86, a d-axis current controller 87, and a 2-axis 3-axis. Coordinate terminals constituted by a coordinate converter 88 for performing current vector control calculation based on the phase current data div, div, diw, the angle data θ and the encoder signal Enc, and rotating the motor at a target speed A control output signal V (Vu, Vv, Vw) indicating a voltage to be applied to is output.

  Hereinafter, a detailed configuration of the control calculation means 8 will be described. The target frequency generator 81 generates a pulse signal having a target frequency corresponding to the target rotational speed of the motor 1. As a configuration in which a pulse signal having a target frequency is input from the outside of the apparatus, a pulse having a target frequency can be obtained from a configuration in which the target frequency generator 81 is not provided or from the output of the target frequency generator 81 and a pulse signal input from the outside. It is good also as a structure which enables selection of a signal.

  The frequency comparator 82 compares the frequency of the encoder signal Enc with the frequency of the pulse signal output from the target frequency generator 81, and outputs an error signal corresponding to the difference between the two frequencies. Instead of the encoder signal Enc, a signal obtained by dividing the encoder signal Enc may be used.

  Based on the value of the error signal output from the frequency comparator 82, the target current generator 83 sets the target of the current to be passed so that the rotational speed of the motor corresponding to the target frequency is substantially equal to the actual rotational speed of the motor. Q-axis target current data and d-axis target current data, which are values, are output.

  The three-axis / two-axis coordinate converter 85 rotates the phase current data diu, div, diw from the UVW axis coordinate system, which is a three-axis fixed coordinate system having a phase difference of 120 degrees, according to the rotor angle. Performs coordinate transformation to the dq axis coordinate system, which is a rotational orthogonal two axis coordinate system (hereinafter referred to as three axis two axis coordinate transformation), and calculates d axis current data did and q axis current data diq on the dq axis coordinate system. Output. At this time, the angle data θ is used as rotor angle information necessary for the three-axis / two-axis coordinate conversion.

  The q-axis current controller 86 calculates a q-axis current error which is an error between the q-axis target current data and the q-axis current data iq, and obtains a value obtained by amplifying the q-axis current error and a value obtained by integrating the q-axis current error. Add and output as q-axis control data.

  The d-axis current controller 87 calculates a d-axis current error that is an error between the d-axis target current data and the d-axis current data id, and obtains a value obtained by amplifying the d-axis current error and a value obtained by integrating the d-axis current error. Add and output as d-axis control data.

  The 2-axis 3-axis coordinate converter 88 converts the q-axis control data and the d-axis control data into a phase difference of 120 degrees from the dq-axis coordinate system, which is a rotational orthogonal 2-axis coordinate system that rotates according to the rotor angle. A value indicating the voltage to be applied to the three-phase coil terminals on the UVW axis coordinate system is obtained by performing coordinate conversion to the UVW axis coordinate system which is a three-axis fixed coordinate system (hereinafter referred to as “two-axis three-axis coordinate conversion”). Calculate and output as a control output signal V (Vu, Vv, Vw). At this time, the angle data θ is used as rotor angle information necessary for the biaxial triaxial coordinate conversion.

  Hereinafter, the description returns to the apparatus configuration using FIG. The two-phase modulator 9 performs two-phase modulation on the control output signal V (Vu, Vv, Vw) and outputs the voltage command signal Vm (Vmu, Vmv, Vmw). The process of the two-phase modulation will be described. First, the three-phase control output signals V (Vu, Vv, Vw) are compared in magnitude to determine the output minimum phase that is the phase having the smallest value. If there are multiple ones with the same value, one of the phases is set as the minimum output phase.

Next, the voltage command signal Vm (one corresponding to Vu, Vv, Vw) of the output minimum phase is output as zero, and the control output signal V (Vu, Vv, Vw) of each phase is output for the other two phases. Are subtracted from the value Vm (one corresponding to Vu, Vv, Vw) of the control output signal of the minimum output phase, respectively, and the voltage command signal Vm (Vmu, Vmv, Vmw) 2 corresponding to each other). For example, the processing when the value of the U-phase control output signal Vu is the smallest among the three phases is shown in Equation 7.

  Here, a schedule example of each process within one carrier cycle will be described with reference to FIG. First, based on the DC link current data dia and dib detected at the timings (sa) and (sb), the phase current detection means 5 detects the phase current data diu, div and diw, and then the control calculation means 8 Executes a control calculation based on the phase current data div, div, diw, outputs the calculation result as the control output signal V (Vu, Vv, Vw), and the two-phase modulator 9 outputs the control output signal. V is two-phase modulated, and finally, the processing result of the two-phase modulator 9 is reflected in the voltage command signal Vm at the timing (m) shown in FIG. At this time, it is assumed that the processing of the corrected voltage command signal Vr from the voltage command signal Vm described in Example 1 is completed by the value update timing (p) of the corrected voltage command signal Vr.

  The above is the outline of the processing within one carrier cycle, and is executed for each carrier cycle. The time required for control calculation and detection processing with little difference in processing amount due to such conditional branching is almost constant, and with the configuration of this example, detection of phase current data is completed at a substantially fixed timing within one carrier cycle. Therefore, the start timing of the control calculation can be fixed, and the processing schedule within one carrier cycle can be fixed.

  The above is the configuration of the motor drive control device in this example. In the method of detecting the phase current by detecting the DC link current a plurality of times, current detection is possible even if the current detection timing is fixed within one carrier cycle. Since it is configured to be possible and the vector control calculation is executed based on the detected phase current value, the timing at which the current detection is completed within one carrier period is almost fixed, and the vector control calculation process Since there are few factors that change the schedule, for example, when the control calculation is realized by software executed on the microprocessor, the vector control drive of the motor can be realized even by a low-cost processor with lower performance.

DESCRIPTION OF SYMBOLS 1 Motor 2 Bridge circuit 4 DC current detection means 5 Phase current detection means 6 PWM means 7 Gate drive means 8 Control calculation means 9 Two-phase modulator 10 Drive detection means 15 Hall IC
16 Encoder 17 Angle detector 21 Upper arm 22 Lower arm 25 Switching element 26 Diode 31 DC power supply 32 GND
41 Current detection circuit 42 Data acquisition unit 45 Shunt resistor 46 LPF
47 Amplifier 61 Voltage command limiting means 62 Voltage correcting means 63 Modulating means 81 Target frequency generator 82 Frequency comparator 83 Target current generator 85 3-axis 2-axis coordinate converter 86 q-axis current controller 87 d-axis current controller 88 2 3-axis coordinate converter

JP 2007-228788 A

Claims (9)

A bridge circuit configured by a plurality of switching elements and diodes connected to the positive side or the negative side of the DC power supply, and supplying a drive current to a motor having a coil of a plurality of phases by an on / off operation of the switching elements;
PWM means for generating a multi-phase PWM signal by pulse-width modulating a multi-phase voltage command signal whose value is updated at a predetermined timing with a carrier signal;
Gate driving means for generating a gate signal for driving the switching element of the bridge circuit based on the PWM signal;
DC current detection means for detecting a DC link current value flowing between the DC power supply and the bridge circuit;
Phase currents flowing through a plurality of coils of the motor based on the DC link current value detected by the DC current detection means and the PWM signal or gate signal before and after the value update timing of the voltage command signal Phase current detection means for detecting values;
The PWM means comprises:
The pulse width of at least one phase of the PWM signal increases in the rear end direction with reference to the front end of the value update period of the voltage command signal in response to an increase in the value of the voltage command signal. The pulse width of at least one phase of the PWM signal different from the increased PWM signal increases in the front end direction with reference to the rear end of the value update period of the voltage command signal as the value of the voltage command signal increases. Like
Generating the PWM signal;
The motor drive control apparatus characterized by the above-mentioned.   The motor drive control device according to claim 1, wherein the motor is a three-phase motor, and the voltage command signal is a two-phase modulated signal.   The PWM means includes pulse width restriction means for enlarging a pulse width of a signal obtained by pulse width modulation of the voltage command signal and restricting a pulse width of at least two phases to a predetermined minimum value or more. The motor drive control device according to claim 1 or 2.   The PWM means includes voltage correction means for correcting the pulse width of the other phase so that the voltage vector for the expansion becomes zero or substantially zero with respect to the expansion of the pulse width by the pulse width limiting means. The motor drive control device according to claim 3.   5. The motor drive according to claim 1, wherein the DC current detection unit includes a high frequency cutoff filter and a data acquisition unit that detects an output value of the high frequency cutoff filter. Control device.   6. The motor drive control device according to claim 5, wherein the data acquisition unit is an A / D conversion unit that performs A / D conversion on an output signal of the high-frequency cutoff filter.   In the detection of the DC link current executed by the DC current detection means before and after the value update timing of the voltage command signal, the interval between the two current detections is the result detected by the data acquisition unit from the start of value acquisition The motor drive control device according to claim 5, wherein the motor drive control device is equal to or longer than a time required to output.   Control calculation means for calculating a voltage command value for driving the motor based on the detected phase current value and reflecting the calculated voltage command value in the voltage command signal at the predetermined value update timing The motor drive control device according to any one of claims 1 to 7, further comprising:   9. The motor drive according to claim 8, wherein the control calculation means calculates a voltage command value for performing vector control drive of the motor by executing a current vector calculation based on the phase current value. Control device.

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