WO2023238562A1 - 多層基板 - Google Patents

多層基板 Download PDF

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Publication number
WO2023238562A1
WO2023238562A1 PCT/JP2023/017214 JP2023017214W WO2023238562A1 WO 2023238562 A1 WO2023238562 A1 WO 2023238562A1 JP 2023017214 W JP2023017214 W JP 2023017214W WO 2023238562 A1 WO2023238562 A1 WO 2023238562A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
laminate
multilayer substrate
conductor layers
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2023/017214
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
伸郎 池本
敬一 市川
健太朗 川辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to CN202390000263.5U priority Critical patent/CN223093990U/zh
Priority to JP2024526298A priority patent/JP7798193B2/ja
Publication of WO2023238562A1 publication Critical patent/WO2023238562A1/ja
Priority to US18/888,325 priority patent/US20250010577A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B15/00—Layered products comprising a layer of metal
    • B32B15/20—Layered products comprising a layer of metal comprising aluminium or copper
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B15/00—Layered products comprising a layer of metal
    • B32B15/04—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material
    • B32B15/08—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material of synthetic resin
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B7/00—Layered products characterised by the relation between layers; Layered products characterised by the relative orientation of features between layers, or by the relative values of a measurable parameter between layers, i.e. products comprising layers having different physical, chemical or physicochemical properties; Layered products characterised by the interconnection of layers
    • B32B7/03—Layered products characterised by the relation between layers; Layered products characterised by the relative orientation of features between layers, or by the relative values of a measurable parameter between layers, i.e. products comprising layers having different physical, chemical or physicochemical properties; Layered products characterised by the interconnection of layers with respect to the orientation of features
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2307/00—Properties of the layers or laminate
    • B32B2307/20—Properties of the layers or laminate having particular electrical or magnetic properties, e.g. piezoelectric
    • B32B2307/202—Conductive
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2307/00—Properties of the layers or laminate
    • B32B2307/20—Properties of the layers or laminate having particular electrical or magnetic properties, e.g. piezoelectric
    • B32B2307/206—Insulating
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2398/00—Unspecified macromolecular compounds
    • B32B2398/20—Thermoplastics
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2457/00—Electrical equipment

Definitions

  • the second laminate 12b is located above the first laminate 12a (in the positive direction of the Z-axis).
  • the second laminate 12b is fixed to the first laminate 12a by joining the first insulator layer 16a and the second insulator layer 17e.
  • the first insulator layer 16a and the second insulator layer 17e are fused together.
  • the second laminate 12b has an annular shape when viewed in the vertical direction.
  • the second laminate 12b has rectangular outer and inner edges when viewed in the vertical direction.
  • the second laminate 12b partially overlaps the first laminate 12a when viewed in the vertical direction.
  • the first area A1 where the first laminate 12a and the second laminate 12b are present when viewed in the up-down direction (Z-axis direction) and the first area A1 where the first laminate 12a and the second laminate 12b are present when viewed in the up-down direction (Z-axis direction).
  • 12a exists, and there is a second region A2 in which the second stacked body 12b does not exist.
  • the second area A2 is surrounded by the first area A1 when viewed in the vertical direction. Thereby, a cavity C is formed in the multilayer substrate 10.
  • the regions obtained by dividing the first laminate 12a into three equal parts in the vertical direction (Z-axis direction) are defined as a positive region A11, an intermediate region A12, and a negative region A13.
  • the positive area A11, the intermediate area A12, and the negative area A13 are arranged in this order downward (negative direction of the Z axis).
  • the first conductor layers 20a to 20f include one or more positive region first conductor layers, one or more intermediate region first conductor layers, and one or more negative region first conductor layers.
  • the one or more positive region first conductor layers are the first conductor layers 20a and 20b.
  • the one or more intermediate region first conductor layers are the first conductor layers 20c.
  • the one or more negative region first conductor layers are first conductor layers 20d to 20f.
  • each of the first conductor layers 20d to 20f is located in the negative region A13.
  • the entire first conductor layer 20e is located in the negative region A13.
  • Parts of the first conductor layers 20d and 20f are located in the negative region A13.
  • the vertical direction (Z-axis direction) of the first conductor layer 20a (first conductor layer on the most positive side, one or more positive area first conductor layers) and the first conductor layer 20b (one or more positive area first conductor layers) is larger than the thickness of the first conductor layer 20c (one or more intermediate region first conductor layers) in the vertical direction (Z-axis direction).
  • the vertical thickness of the conductor layer means the thickness in the normal direction of the main surface of the conductor layer. Therefore, when the conductor layer is curved, the vertical direction deviates from the vertical direction in the drawing.
  • the vertical thickness of the first conductor layers 20d to 20f is the same as the vertical thickness of the first conductor layer 20c.
  • the vertical thickness of the first conductor layers 20a, 20b is larger than the vertical thickness of the first conductor layer 20c due to manufacturing error. is larger than the vertical thickness of the first conductor layer 20c.
  • the manufacturing error is, for example, 10% of the vertical thickness of the first conductor layer 20c.
  • each of the first conductor layers 20a and 20b is located in the positive region A11.
  • the vertical thickness of the first conductor layers 20a and 20b is larger than the vertical thickness of the first conductor layer 20c.
  • the first conductor layers 20a and 20b having high strength are located near the upper main surface of the first laminate 12a. That is, the first conductor layers 20a and 20b having high strength are located near the bottom surface of the cavity C.
  • the vicinity of the bottom surface of the cavity C becomes difficult to deform during the thermocompression bonding process of the first laminate 12a and the second laminate 12b, and the cavity C becomes difficult to deform. Therefore, occurrence of short circuit between the first conductor layers 20a to 20f provided near the cavity C is suppressed.
  • the multilayer substrate 10 large deformation of the multilayer substrate 10 is suppressed in the thermocompression bonding process of the first laminate 12a and the second laminate 12b. More specifically, in the thermocompression bonding process of the first laminate 12a and the second laminate 12b, a large force is concentrated at the boundary B between the first region A1 and the second region A2. Therefore, the multilayer substrate 10 easily deforms significantly at the boundary B.
  • the first conductor layers 20a and 20b overlap the boundary B between the first region A1 and the second region A2 when viewed in the vertical direction. Since the vertical thickness of the first conductor layers 20a, 20b is larger than the vertical thickness of the first conductor layer 20c, the first conductor layers 20a, 20b have high strength. As a result, large deformation of the multilayer substrate 10 at the boundary B is suppressed.
  • the second laminate 12b has an angular U-shape when viewed in the vertical direction.
  • the first area A1 is located in a part of the periphery of the second area A2 when viewed in the vertical direction.
  • the first area A1 is not located in front of the second area A2.
  • the second laminate 12b has an L-shape when viewed in the vertical direction.
  • the first area A1 is located in a part of the periphery of the second area A2 when viewed in the vertical direction.
  • the first area A1 is not located in front of or to the right of the second area A2.
  • FIG. 7 is a cross-sectional view of the multilayer substrate 10e.
  • the multilayer substrate 10e differs from the multilayer substrate 10 in that the vertical thickness of the first conductor layer 20a is smaller than the vertical thickness of the first conductor layer 20b.
  • the vertical thickness of the first conductor layer 20a is equal to the vertical thickness of the first conductor layers 20c to 20f.
  • the other structure of the multilayer substrate 10e is the same as that of the multilayer substrate 10e.
  • the multilayer substrate 10e can have the same effects as the multilayer substrate 10.
  • the first conductor layer 20b located below of the first conductor layers 20a and 20b located in the positive region A11 has a large thickness in the vertical direction. Therefore, deformation of the first laminate 12a in the intermediate region A12 and the negative region A13 of the first laminate 12a is suppressed. Furthermore, since deformation of the first laminate 12a is suppressed in the vicinity of the first conductor layer 20b, short circuits are less likely to occur in the first conductor layer 20a located above the first conductor layer 20b.
  • FIG. 8 is a cross-sectional view of the multilayer substrate 10f.
  • the multilayer substrate 10f differs from the multilayer substrate 10e in that the vertical thickness of the first conductor layer 20e located in the negative region A13 is larger than the vertical thickness of the first conductor layer 20c located in the intermediate region A12. In this way, the other structure of the multilayer substrate 10f is the same as that of the multilayer substrate 10e, so a description thereof will be omitted.
  • the multilayer substrate 10f can have the same effects as the multilayer substrate 10e.
  • the first conductor layer 20e located in the negative region A13 has a large thickness in the vertical direction. Therefore, deformation of the first laminate 12a in the negative region A13 of the first laminate 12a is suppressed.
  • the vertical thickness of the first conductor layers 20b and 20e is larger than the vertical thickness of the first conductor layer 20c.
  • the first region A1 has a vertically symmetrical structure, making it difficult for the first laminate 12a to warp.
  • the vertical thickness of the first conductor layers 20b and 20e is larger than the vertical thickness of the first conductor layer 20c.
  • the first region A1 has a vertically symmetrical structure, making it difficult for the first laminate 12a to warp.
  • FIG. 11 is a cross-sectional view of the multilayer substrate 10i.
  • the multilayer substrate 10i differs from the multilayer substrate 10 in that the vertical thickness of the first conductor layer 20a is larger than the vertical thickness of the first conductor layers 20b to 20f. This makes it difficult for the vicinity of the upper main surface of the first conductor layer 20a to deform. As a result, deformation of the cavity C is effectively suppressed.
  • the other structure of the multilayer substrate 10i is the same as that of the multilayer substrate 10, so the description thereof will be omitted.
  • the multilayer substrate 10i can have the same effects as the multilayer substrate 10.
  • the first conductor layer 20a is fixed to the upper main surface of the first insulator layer 16a.
  • a first conductor layer 20f is fixed to the lower main surface of the first insulator layer 16f.
  • a protective layer 18a is laminated on the first insulator layer 16a.
  • a protective layer 18b is laminated under the first insulator layer 16f.
  • no conductor layer is located on the upper main surface of the protective layer 18a and the lower main surface of the protective layer 18b.
  • the other structure of the multilayer substrate 10k is the same as the multilayer substrate 10.
  • the multilayer substrate 10k can have the same effects as the multilayer substrate 10.
  • the first insulator layer 16a is located at the top of the insulator layers in the first stacked body 12a. That is, the first insulator layer 16a is joined to the second insulator layer 17e of the second stacked body 12b, and forms the bottom surface of the cavity C.
  • the first conductor layer 20a is in contact with the lower main surface of the first insulator layer 16a, and is located directly below the first insulator layer 16a.
  • the first insulator layers 16a, 16b are provided such that the vertical thickness T1 of the first insulator layer 16a in contact with the first conductor layer 20a is smaller than the vertical thickness of the first conductor layer 20a. This increases the rigidity near the bottom of the cavity C.
  • the multilayer substrate 10m differs from the multilayer substrate 10 mainly in the following points. - The vertical thickness of the first laminate 12a is smaller than the vertical thickness of the second laminate 12b. - The second area A2 surrounds the first area A1 when viewed in the vertical direction.
  • the first laminate 12a includes first insulator layers 16a to 16d stacked in the vertical direction, and first conductor layers 20a to 20d fixed to the lower main surfaces of the first insulator layers 16a to 16d. It is equipped with
  • the second laminate 12b includes second insulator layers 17a to 17f stacked in the vertical direction, and second conductor layers 21a to 21f fixed to the lower main surface of the second insulator layers 17a to 17f. .
  • the vertical thickness of the first laminate 12a is smaller than the vertical thickness of the second laminate 12b.
  • the first laminate 12a surrounds the second laminate 12b when viewed in the vertical direction.
  • the second area A2 surrounds the first area A1 when viewed in the vertical direction.
  • the multilayer substrate according to the present invention is not limited to the multilayer substrates 10, 10a to 10m, and can be modified within the scope of the gist. Note that the configurations of the multilayer substrates 10, 10a to 10m may be arbitrarily combined.
  • the number of positive region first conductor layers is not limited to two.
  • the number of positive region first conductor layers may be one, or may be three or more.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
PCT/JP2023/017214 2022-06-09 2023-05-06 多層基板 Ceased WO2023238562A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN202390000263.5U CN223093990U (zh) 2022-06-09 2023-05-06 多层基板
JP2024526298A JP7798193B2 (ja) 2022-06-09 2023-05-06 多層基板
US18/888,325 US20250010577A1 (en) 2022-06-09 2024-09-18 Multilayer substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2022093630 2022-06-09
JP2022-093630 2022-06-09

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/888,325 Continuation US20250010577A1 (en) 2022-06-09 2024-09-18 Multilayer substrate

Publications (1)

Publication Number Publication Date
WO2023238562A1 true WO2023238562A1 (ja) 2023-12-14

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ID=89118100

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2023/017214 Ceased WO2023238562A1 (ja) 2022-06-09 2023-05-06 多層基板

Country Status (4)

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US (1) US20250010577A1 (https=)
JP (1) JP7798193B2 (https=)
CN (1) CN223093990U (https=)
WO (1) WO2023238562A1 (https=)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002171036A (ja) * 2000-12-04 2002-06-14 Olympus Optical Co Ltd 多層基板
JP2006344828A (ja) * 2005-06-09 2006-12-21 Denso Corp 多層基板及びその製造方法
WO2014115433A1 (ja) * 2013-01-22 2014-07-31 株式会社村田製作所 コイル部品および電子機器
JP2014207346A (ja) * 2013-04-15 2014-10-30 株式会社村田製作所 多層配線基板およびこれを備えるモジュール
JP2019021863A (ja) * 2017-07-21 2019-02-07 株式会社村田製作所 多層基板

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002171036A (ja) * 2000-12-04 2002-06-14 Olympus Optical Co Ltd 多層基板
JP2006344828A (ja) * 2005-06-09 2006-12-21 Denso Corp 多層基板及びその製造方法
WO2014115433A1 (ja) * 2013-01-22 2014-07-31 株式会社村田製作所 コイル部品および電子機器
JP2014207346A (ja) * 2013-04-15 2014-10-30 株式会社村田製作所 多層配線基板およびこれを備えるモジュール
JP2019021863A (ja) * 2017-07-21 2019-02-07 株式会社村田製作所 多層基板

Also Published As

Publication number Publication date
CN223093990U (zh) 2025-07-11
US20250010577A1 (en) 2025-01-09
JP7798193B2 (ja) 2026-01-14
JPWO2023238562A1 (https=) 2023-12-14

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