CN107958875B - 半导体装置以及布线基板的设计方法 - Google Patents

半导体装置以及布线基板的设计方法 Download PDF

Info

Publication number
CN107958875B
CN107958875B CN201710963118.8A CN201710963118A CN107958875B CN 107958875 B CN107958875 B CN 107958875B CN 201710963118 A CN201710963118 A CN 201710963118A CN 107958875 B CN107958875 B CN 107958875B
Authority
CN
China
Prior art keywords
region
wiring
semiconductor chip
conductive member
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710963118.8A
Other languages
English (en)
Other versions
CN107958875A (zh
Inventor
町田英昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lapis Semiconductor Co Ltd
Original Assignee
Lapis Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lapis Semiconductor Co Ltd filed Critical Lapis Semiconductor Co Ltd
Publication of CN107958875A publication Critical patent/CN107958875A/zh
Application granted granted Critical
Publication of CN107958875B publication Critical patent/CN107958875B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Abstract

本发明涉及半导体装置以及布线基板的设计方法。在具备具有半导体芯片的搭载区域和焊料凸块等外部连接端子的配置区域不重叠的自由区域的布线基板的半导体装置中，减少布线产生断线的风险。半导体装置具备：半导体芯片；基体，具备供半导体芯片搭载的一侧的第一面以及与第一面相反侧的第二面，并且具备供半导体芯片搭载的第一区域以及与第一区域分离的第二区域；导电部件，被设置在基体的第二面上；保护部件，以覆盖导电部件的方式被设置在基体的第二面，并且具备使导电部件的配置在第二区域的部分局部露出的开口部；以及外部连接端子，经由开口部与导电部件连接。保护部件在与第一区域的外缘对应的部分与基体接触。

Description

半导体装置以及布线基板的设计方法
技术领域
本发明涉及半导体装置以及布线基板的设计方法。
背景技术
在构成为包括半导体芯片和搭载有半导体芯片的布线基板的半导体装置中，作为与设置在布线基板上的布线的断线防止有关的技术，已知以下的技术。
例如，在专利文献1中记载了在与设置在半导体芯片与安装基板之间的加强树脂层的端部相当的部分，将设置于安装基板的布线设置于距离安装基板的表面远处的位置。
在专利文献2中记载了具备在一个主面上设置有构成布线构造体的一部分的布线的绝缘性基体、和夹着阻焊剂层而搭载于绝缘性基体的一个主面的半导体芯片的半导体装置。在该半导体装置中，被设置为设定有防止在半导体芯片的外缘下方沿着该外缘存在于该区域内的布线部分的断线的断线防止区域，存在于断线防止区域内的布线构造体的布线部分向绝缘性基体的另一个主面侧迂回，与阻焊剂层分离。
在专利文献3中记载了包括基板、搭载在基板的一面上的电子部件、和形成在基板上并以在俯视时从电子部件的外缘的内侧向外侧横穿的方式形成的布线的电子装置。记载了在该电子装置中，布线构成为横穿电子部件的外缘的布线路径包括从电子装置的外缘上的第一位置沿着该外缘延伸到电子装置的外缘上的第二位置的部分，第一位置与第二位置之间的距离比布线的布线宽度宽。
专利文献1：日本特开2002－164385
专利文献2：日本特开2006－140512
专利文献3：日本特开2011－192678
上述的专利文献1以及专利文献2示出构成为包括半导体芯片和搭载有半导体芯片的布线基板的半导体装置的一般结构。即，在这种半导体装置中，在布线基板的一个面上搭载半导体芯片，在布线基板的另一个面上设置焊料凸块等外部连接端子，并且焊料凸块的配置区域与半导体芯片的搭载区域局部重叠。像这样焊料凸块的配置区域和半导体芯片的搭载区域局部重叠，由此布线基板在整个区域被半导体芯片以及焊料凸块中的至少一方支承。由此，即使在对布线基板施加热应力的情况下，也抑制起因于构成半导体装置的各部件的热膨胀系数差而产生的布线基板的挠曲(弯曲)，因此，认为较难产生由布线基板的挠曲所引起的布线的断线。
另一方面，近年来，半导体装置的多功能化发展，在布线基板的表面搭载有多个半导体芯片的半导体装置正被实用化。在布线基板的表面搭载有多个半导体芯片的半导体装置中，在要求安装面积的缩小的产品中，多个半导体芯片被层叠在布线基板上，在要求薄型化的产品中，多个半导体芯片并列设置在布线基板上。在多个半导体芯片并列设置在布线基板上的结构中，由于布线基板的面积比较大，所以有时采用半导体芯片的搭载区域和焊料凸块的配置区域不重叠的结构。在该情况下，在布线基板中产生未被半导体芯片以及焊料凸块中的任何一方支承的自由区域。
通过本发明人的潜心研究，在具备具有未被半导体芯片以及焊料凸块中的任何一方支承的自由区域的布线基板的半导体装置中，明白了以下的事实。即，明白了：若对具备具有未被半导体芯片以及焊料凸块中的任何一方支承的自由区域的布线基板的半导体装置施加热应力，则以自由区域为起点在布线基板产生挠曲；起因于布线基板的挠曲而在布线基板上所产生的应力集中于半导体芯片的外缘(边缘)的正下方区域；即使在半导体芯片的外缘的正下方区域内,在布线基板的与搭载有半导体芯片的一侧的第一面相反侧的第二面(即设置有焊料凸块的一侧的面)中应力特别大，在设置在布线基板的第二面上的布线的、与半导体芯片的外缘的正下方区域对应的部分，产生断线的风险变高。
根据在布线基板的表面上搭载有多个半导体芯片的半导体装置，应用使从某个半导体芯片引出的布线通过其它半导体芯片的下方的布线布局的情况较多。在该情况下，由于该布线通过应力集中的半导体芯片的外缘的正下方区域，所以需要防止该布线的断线的对策。
发明内容
本发明是鉴于上述的点而完成的，其目的在于在具备具有半导体芯片的搭载区域和焊料凸块等外部连接端子的配置区域不重叠的自由区域的布线基板的半导体装置中，减少布线产生断线的风险。
基于本发明的第一观点的半导体装置具备：半导体芯片；基体，具备供上述半导体芯片搭载的一侧的第一面以及与上述第一面相反侧的第二面，并且具备供上述半导体芯片搭载的第一区域以及与上述第一区域分离的第二区域；导电部件，被设置在上述基体的上述第二面上；保护部件，以覆盖上述导电部件的方式被设置在上述基体的上述第二面，并且具备使上述导电部件的配置在上述第二区域的部分局部露出的开口部；以及外部连接端子，经由上述开口部与上述导电部件连接。上述保护部件在与上述第一区域的外缘对应的部分与上述基体接触。
基于本发明的第二观点的半导体装置包括：第一半导体芯片；布线基板，具有第一面以及与上述第一面相反侧的第二面，在上述第一面侧搭载上述第一半导体芯片，并且在将上述第二面上作为布线层之一而包括的多个布线层的各层具有布线；以及外部连接端子，在上述布线基板的与搭载有上述第一半导体芯片的第一区域分离的第二区域内与配置在上述第二面上的布线连接。上述布线基板包括通过与上述第一半导体芯片的外缘对应的区域的第一布线，上述第一布线的在与上述第一半导体芯片的外缘对应的区域内延伸的部分被设置在上述多个布线层中的上述第二面上以外的布线层。
在本发明所涉及的布线基板的设计方法中，在该布线基板，具有第一面以及与上述第一面相反侧的第二面，在上述第一面侧搭载半导体芯片，在上述第二面侧设置外部连接端子，并且在将上述第二面上作为布线层之一而包括的多个布线层的各层具有布线，上述布线基板的设计方法包括：第一步骤，决定供上述半导体芯片搭载的芯片搭载区域；第二步骤，在与上述芯片搭载区域分离的区域内决定上述外部连接端子的配置区域；第三步骤，将与上述芯片搭载区域的外缘对应的区域决定为特定区域；以及第四步骤，在上述多个布线层的各层配置布线。在上述第四步骤中，在上述多个布线层中的上述第二面上以外的布线层配置通过上述特定区域的布线的在上述特定区域延伸的部分。
根据本发明，在具备具有半导体芯片的搭载区域和焊料凸块等外部连接端子的配置区域不重叠的自由区域的布线基板的半导体装置中，能够减少布线产生断线的风险。
附图说明
图1是表示本发明的实施方式所涉及的半导体装置的结构的俯视透视图。
图2A是沿着图1中的2－2线的剖视图。
图2B是表示本发明的实施方式所涉及的半导体装置的结构的剖视图。
图2C是安装在安装基板上的状态的本发明的实施方式所涉及的半导体装置的剖视图。
图3是表示在本发明的实施方式所涉及的半导体装置中，在布线基板产生了挠曲的状态的图。
图4是表示比较例所涉及的半导体装置的结构的俯视透视图。
图5是沿着图4中的5－5线的剖视图。
图6是表示本发明的实施方式所涉及的布线基板的设计顺序的设计流程图。
附图标记说明：1…半导体装置；10A…第一半导体芯片；10B…第二半导体芯片；10C…第三半导体芯片；20…布线基板；21…基体；24…连接布线；30…焊料凸块；A1…第一区域；A2…第二区域；A3…第三区域；B1…应力集中区域；C1…布线配置禁止区域；L1…第一布线层；L2…第二布线层；L3…第三布线层；L4…第四布线层。
具体实施方式
以下，参照附图对本发明的实施方式的一个例子进行说明。此外，在各附图中，对同一或者等效的构成要素以及部分赋予同一参照符号。
图1是表示本发明的实施方式所涉及的半导体装置1的结构的俯视透视图，图2A是沿着图1中的2－2线的剖视图。
半导体装置1构成为包括布线基板20、搭载在布线基板20的第一面S1侧的第一半导体芯片10A、第二半导体芯片10B以及第三半导体芯片10C。布线基板20作为对第一半导体芯片10A、第二半导体芯片10B以及第三半导体芯片10C与供半导体装置1安装的安装基板(未图示)之间的电连接进行中继的中介层(interposer)发挥作用。如图2A所示，半导体装置1还可以包括设置在布线基板20的第一面S1侧的密封树脂。在该情况下，第一半导体芯片10A、第二半导体芯片10B、第三半导体芯片10C以及将这些半导体芯片的各个与布线基板20连接的导线12、41、42被埋设在密封树脂50内。
作为一个例子，布线基板20具备：基体21，通过在由玻璃环氧树脂等绝缘体构成的芯材21b的两面层叠半固化片(Prepreg)21a以及21c而构成；以及布线层L1～L4，被设置在基体21的表面以及内部。在布线基板20中，半固化片21a的上表面成为第一布线层L1，芯材21b的上表面以及下表面分别成为第二布线层L2以及第三布线层L3，半固化片21c的下表面成为第四布线层L4，在各布线层例如设置有由铜箔等导电部件构成的布线。布线层间的布线彼此的连接通过导通孔25来进行。
布线基板20具备覆盖基体21的上表面亦即第一面S1的阻焊剂22。配置在第一布线层L1的布线被阻焊剂22覆盖。即，阻焊剂22作为保护外层布线亦即被配置在第一布线层L1的布线的保护部件发挥作用。在第一布线层L1中未形成布线的部分，基体21与阻焊剂22接触。
另外，布线基板20具备覆盖基体21的下表面亦即第二面S2的阻焊剂23。配置在第四布线层L4的布线被阻焊剂23覆盖。即，阻焊剂23作为保护外层布线亦即被配置在第四布线层L4的布线的保护部件发挥作用。在第四布线层L4中未形成布线的部分，基体21与阻焊剂23接触。
第一半导体芯片10A、第二半导体芯片10B以及第三半导体芯片10C分别被设置在布线基板20的第一面S1侧。第一半导体芯片10A、第二半导体芯片10B以及第三半导体芯片10C通过设置在阻焊剂22的表面的芯片粘接材料11与布线基板20接合。作为芯片粘接材料11，例如能够使用银膏、各向异性导电性粘合膜、芯片粘接膜等。
在本实施方式中，第一半导体芯片10A、第二半导体芯片10B以及第三半导体芯片10C分别主面的外形为正方形，第一半导体芯片10A的大小比第二半导体芯片10B以及第三半导体芯片10C的大小大。第二半导体芯片10B以及第三半导体芯片10C是相互具有相同的功能的同种半导体芯片，相互为相同的大小。
第一半导体芯片10A被配置在布线基板20的中央。在布线基板20中，将第一半导体芯片10A的搭载区域设为第一区域A1。即，布线基板20的第一区域A1是被第一半导体芯片10A支承的区域。第二半导体芯片10B以及第三半导体芯片10C被设置在布线基板20的第一区域A1的外侧，并且以之间夹着第一半导体芯片10A的方式被配置在第一半导体芯片10A的左右。
如图2A所示，第一半导体芯片10A通过导线12与被配置在布线基板20的第一布线层L1的布线电连接。阻焊剂22具有使配置在第一布线层L1的布线的与导线12连接的部分露出的开口部。
另外，如图1所示，第二半导体芯片10B以及第三半导体芯片10C分别通过导线41以及42与配置在布线基板20的第一布线层L1的布线电连接。阻焊剂22具有使配置在第一布线层L1的布线的与导线41以及42连接的部分露出的开口部。
在布线基板20的第二面S2侧设置有作为外部连接端子发挥作用的多个焊料凸块30。焊料凸块30与配置在布线基板20的第四布线层L4的布线的一部分亦即焊盘部26连接。阻焊剂23具有使配置在第四布线层L4的焊盘部26露出的开口部。多个焊料凸块30被设置在布线基板20的外周区域。即多个焊料凸块30被设置为包围第一半导体芯片10A的外周。在布线基板20中，将配置多个焊料凸块30的区域设为第二区域A2。即，布线基板20的第二区域A2是被多个焊料凸块30支承的区域。如图2C所示，半导体装置1在组装成最终产品的状态下被安装在安装基板60上。安装基板60具有与多个焊料凸块30的各个对应的多个电极61。通过在多个电极61上接合各个焊料凸块30，从而半导体装置1被固定在安装基板60上。即，布线基板20的第二区域A2是被与安装基板60接合的多个焊料凸块30支承的区域。
在布线基板20中，焊料凸块30的配置区域亦即第二区域A2与第一半导体芯片10A的搭载区域亦即第一区域A1不重叠。即，第二区域A2隔开间隙而与第一区域A1分离。布线基板20在第一区域A1与第二区域A2之间具有未被第一半导体芯片10A以及焊料凸块30中的任何一方支承的自由区域。将该自由区域设为第三区域A3。
若对具备具有自由区域的布线基板20的半导体装置1施加热应力，则如图3所示，以自由区域亦即第三区域A3为起点在布线基板20产生挠曲(弯曲)。因热应力的施加而在布线基板20产生挠曲是因为布线基板20的热膨胀系数大于第一半导体芯片10A以及芯片粘接材料11的热膨胀系数。
起因于布线基板20的挠曲而在布线基板20产生的应力集中在第一半导体芯片10A、第二半导体芯片10B以及第三半导体芯片10C的外缘(边缘)的正下方区域。以下，将该区域设为应力集中区域B1。应力集中区域B1是以各半导体芯片的外缘的投影线为中心而遍及该半导体芯片的外侧以及内侧的规定范围的区域中的、焊料凸块30的配置区域亦即第二区域A2以外的区域。在应力集中区域B1内应力特别大的是多个布线层中最远离芯片搭载面亦即第一面S1的第二面S2上亦即第四布线层L4。这是因为布线基板20的第一面S1侧搭载半导体芯片，受到半导体芯片所产生的支承力，所以挠曲所引起的应力变得比较小，另一方面，第二面S2侧不易受到半导体芯片所产生的支承力，所以挠曲所引起的应力变得比较大。因此，在配置在第四布线层L4的布线通过应力集中区域B1的情况下，该布线在应力集中区域B1内延伸的部分产生断线的风险变高。
在本实施方式所涉及的布线基板20中，第四布线层L4的在应力集中区域B1内延伸的区域成为布线配置禁止区域C1。即，对于设置在布线基板20的布线中的通过应力集中区域B1的布线而言，该布线的在应力集中区域B1内延伸的部分被配置在第四布线层L4以外的布线层(第一布线层L1、第二布线层L2以及第三布线层L3中的任意一个)。换言之，第四布线层L4的在应力集中区域B1内延伸的部分未被配置布线，在该部分中，布线基板20的基体21与阻焊剂23接触。通过像这样将通过应力集中区域B1的布线的、在应力集中区域B1内延伸的部分配置在第四布线层L4以外的布线层，从而在施加热应力的情况下，能够减少该布线产生断线的风险。
在图1以及图2A～图2C中，作为通过应力集中区域B1的布线的一个例子，示出与第二半导体芯片10B和第三半导体芯片10C双方连接的连接布线24。连接布线24的一端在第四布线层L4以及第一布线层L1分支，连接布线24的配置在第四布线层L4的部分经由焊盘部26与焊料凸块30连接，连接布线24的配置在第一布线层L1的部分经由导线41与第二半导体芯片10B连接。连接布线24的另一端被配置在第一布线层L1，经由导线42与第三半导体芯片10C连接。连接布线24被布局为从一端起通过第一半导体芯片10A的下方到达另一端。即，连接布线24通过应力集中区域B1亦即第一半导体芯片10A的外缘的正下方区域。连接布线24在应力集中区域B1内延伸的部分被设置为退避至第四布线层L4以外的布线层。在图2所示的例子中，连接布线24的在应力集中区域B1内延伸的部分被配置在第三布线层L3以及第二布线层L2。
此处，图4是表示比较例所涉及的半导体装置1X的结构的俯视透视图，图5是沿着图4中的5－5线的剖视图。比较例所涉及的半导体装置1X的连接布线24X的配置与本发明的实施方式所涉及的半导体装置1中的连接布线24的配置不同。连接布线24X与连接布线24同样地是与第二半导体芯片10B以及第三半导体芯片10C双方连接的布线，是通过应力集中区域B1的布线。
比较例所涉及的连接布线24X在应力集中区域B1内延伸的部分被配置在第四布线层L4。如上述那样，在应力集中区域B1内应力特别大的是多个布线层中的第四布线层L4，所以若将连接布线24X的在应力集中区域B1内延伸的部分配置于第四布线层L4，则在该部分中产生断线的风险变高。另一方面，根据本发明的实施方式所涉及的半导体装置1，连接布线24被设置成在应力集中区域B1内延伸的部分退避到第四布线层L4以外的布线层，所以在施加热应力的情况下，能够减少连接布线24产生断线的风险。
以下，对布线基板20的设计方法进行说明。图6是表示布线基板20的设计顺序的一个例子的设计流程图。
在步骤P1中，决定分别供第一半导体芯片10A、第二半导体芯片10B以及第三半导体芯片10C搭载的第一芯片搭载区域、第二芯片搭载区域、第三芯片搭载区域。第二芯片搭载以及第三芯片搭载区域被配置在第一芯片搭载区域亦即第一区域A1的外侧。
在步骤P2中，在与第一芯片搭载区域分离的区域内决定焊料凸块30的配置区域。即，在与第一区域A1分离的区域亦即第二区域A2内决定焊料凸块30的配置区域。
在步骤P3中，将以第一芯片搭载区域、第二芯片搭载区域、第三芯片搭载区域的各个的外缘的投影线为中心而遍及该半导体芯片的外侧以及内侧的规定范围的区域中的、焊料凸块30的配置区域亦即第二区域A2以外的区域决定为应力集中区域B1。
在步骤P4中，在第一布线层L1～第四布线层L4配置布线。对于通过在步骤P3中所决定的应力集中区域B1的布线，将该布线的在应力集中区域B1内延伸的部分配置于第四布线层L4以外的布线层。
从以上的说明可知，根据本发明的实施方式所涉及的半导体装置1以及布线基板的设计方法，在具备具有半导体芯片的搭载区域和焊料凸块等外部连接端子的配置区域不重叠的自由区域的布线基板的半导体装置中，能够减少布线产生断线的风险。
此外，在本实施方式中，例示出布线基板20具有4层布线层的情况，但布线层的层数可以适当地变更。
另外，在本实施方式中，例示出在布线基板20上搭载多个半导体芯片的情况，但在布线基板上搭载一个半导体芯片的结构也能够应用本发明。
另外，在本实施方式中，例示出仅对第四布线层L4设定布线配置禁止区域C1的情况，但在第三布线层L3以及第二布线层L2中在应力集中区域B1产生断线的风险较高的情况下，也可以不仅在第四布线层L4，而在第三布线层L3以及第二布线层L2中，也将在应力集中区域B1内延伸的区域设定为布线配置禁止区域C1。

Claims (7)

1.一种半导体装置，其特征在于，具备：
半导体芯片；
基体，具备供所述半导体芯片搭载的一侧的第一面以及与所述第一面相反侧的第二面，并且具备供所述半导体芯片搭载的第一区域以及与所述第一区域分离的第二区域；
导电部件，被设置在所述基体的所述第二面上；
保护部件，以覆盖所述导电部件的方式被设置于所述基体的所述第二面，并且具备使所述导电部件的配置在所述第二区域的部分局部露出的开口部；以及
外部连接端子，经由所述开口部与所述导电部件连接，
所述保护部件在与所述第一区域的外缘对应的部分与所述基体接触，
所述导电部件具备：第一导电部件，形成在与所述第二区域对应的所述第二面上，并且与所述外部连接端子连接；以及第二导电部件，形成在与所述第一区域对应的所述第二面上，并且与所述第一导电部件电连接，
所述基体具有将所述第二面上作为布线层之一而包括的多个布线层，
所述导电部件还具有第三导电部件，所述第三导电部件与所述第一导电部件以及所述第二导电部件电连接并且通过与所述半导体芯片的外缘对应的区域，
所述第三导电部件设置在所述多个布线层中的所述第二面上以外的布线层。
2.根据权利要求1所述的半导体装置，其特征在于，
在所述基体的所述第一面侧的与所述第一区域不同的区域搭载有与所述半导体芯片不同的其它半导体芯片。
3.根据权利要求1或者2所述的半导体装置，其特征在于，
所述保护部件仅在与所述第二区域对应的区域具有所述开口部。
4.一种半导体装置，其特征在于，包括：
第一半导体芯片；
布线基板，具有第一面以及与所述第一面相反侧的第二面，在所述第一面侧搭载所述第一半导体芯片，并且在将所述第二面上作为布线层之一而包括的多个布线层的各层具有布线；以及
外部连接端子，在所述布线基板的与搭载有所述第一半导体芯片的第一区域分离的第二区域内与配置在所述第二面上的布线连接，
所述布线基板包括通过与所述第一半导体芯片的外缘对应的区域的第一布线，
所述第一布线的在与所述第一半导体芯片的外缘对应的区域内延伸的部分被设置在所述多个布线层中的所述第二面上以外的布线层，
所述第一布线的除在与所述第一半导体芯片的外缘对应的区域内延伸的部分以外的部分被设置在所述第二面上的布线层。
5.根据权利要求4所述的半导体装置，其特征在于，
在所述布线基板的所述第一区域的外侧还包括搭载在所述第一面侧的第二半导体芯片，
所述第一布线与所述第二半导体芯片连接。
6.根据权利要求5所述的半导体装置，其特征在于，
在所述布线基板的所述第一区域的外侧还包括第三半导体芯片，所述第三半导体芯片被搭载在所述第一面侧，并且被设置成与所述第二半导体芯片之间夹着所述第一半导体芯片，
所述第一布线与所述第三半导体芯片连接。
7.根据权利要求4～6中的任意一项所述的半导体装置，其特征在于，
所述第二区域是与所述第一区域之间隔开间隙来包围所述第一区域的区域，在所述第二区域内，多个外部连接端子被设置成包围所述第一半导体芯片的外周。
CN201710963118.8A 2016-10-17 2017-10-17 半导体装置以及布线基板的设计方法 Active CN107958875B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2016-203694 2016-10-17
JP2016203694A JP6806520B2 (ja) 2016-10-17 2016-10-17 半導体装置および配線基板の設計方法

Publications (2)

Publication Number Publication Date
CN107958875A CN107958875A (zh) 2018-04-24
CN107958875B true CN107958875B (zh) 2023-12-05

Family

ID=61904698

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710963118.8A Active CN107958875B (zh) 2016-10-17 2017-10-17 半导体装置以及布线基板的设计方法

Country Status (3)

Country Link
US (1) US10347573B2 (zh)
JP (1) JP6806520B2 (zh)
CN (1) CN107958875B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7058772B2 (ja) * 2019-01-28 2022-04-22 三菱電機株式会社 基板アセンブリ及び空気調和装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004179647A (ja) * 2002-11-12 2004-06-24 Nec Corp 配線基板、半導体パッケージ、基体絶縁膜及び配線基板の製造方法
CN1996586A (zh) * 2006-01-06 2007-07-11 松下电器产业株式会社 半导体元件安装用衬底、半导体装置及电子设备
JP2011192678A (ja) * 2010-03-11 2011-09-29 Renesas Electronics Corp 電子装置および基板
CN104662655A (zh) * 2012-09-21 2015-05-27 日本特殊陶业株式会社 布线基板及其制造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5294750A (en) * 1990-09-18 1994-03-15 Ngk Insulators, Ltd. Ceramic packages and ceramic wiring board
US5763947A (en) * 1996-01-31 1998-06-09 International Business Machines Corporation Integrated circuit chip package having configurable contacts and a removable connector
US6255599B1 (en) * 1997-08-18 2001-07-03 Ibm Relocating the neutral plane in a PBGA substrate to eliminate chip crack and interfacial delamination
JP3497464B2 (ja) 2000-11-24 2004-02-16 沖電気工業株式会社 半導体装置を実装する実装基板および実装構造
US20040099958A1 (en) * 2002-11-21 2004-05-27 Schildgen William R. Crack resistant interconnect module
JP4355313B2 (ja) 2005-12-14 2009-10-28 Ｏｋｉセミコンダクタ株式会社 半導体装置
WO2007119608A1 (ja) * 2006-03-31 2007-10-25 Nec Corporation 配線基板、実装基板及び電子装置
JP2010050150A (ja) * 2008-08-19 2010-03-04 Panasonic Corp 半導体装置及び半導体モジュール
JP5993248B2 (ja) * 2012-08-27 2016-09-14 新光電気工業株式会社 電子部品内蔵基板及びその製造方法
JP6197619B2 (ja) * 2013-12-09 2017-09-20 富士通株式会社 電子装置及び電子装置の製造方法
US20160111380A1 (en) * 2014-10-21 2016-04-21 Georgia Tech Research Corporation New structure of microelectronic packages with edge protection by coating
US20160174365A1 (en) * 2014-12-15 2016-06-16 Bridge Semiconductor Corporation Wiring board with dual wiring structures integrated together and method of making the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004179647A (ja) * 2002-11-12 2004-06-24 Nec Corp 配線基板、半導体パッケージ、基体絶縁膜及び配線基板の製造方法
CN1996586A (zh) * 2006-01-06 2007-07-11 松下电器产业株式会社 半导体元件安装用衬底、半导体装置及电子设备
JP2011192678A (ja) * 2010-03-11 2011-09-29 Renesas Electronics Corp 電子装置および基板
CN104662655A (zh) * 2012-09-21 2015-05-27 日本特殊陶业株式会社 布线基板及其制造方法

Also Published As

Publication number Publication date
CN107958875A (zh) 2018-04-24
JP6806520B2 (ja) 2021-01-06
US10347573B2 (en) 2019-07-09
JP2018067575A (ja) 2018-04-26
US20180108603A1 (en) 2018-04-19

Similar Documents

Publication Publication Date Title
US11640860B2 (en) Circuit module and interposer
US9949368B2 (en) Resin substrate and electronic device
KR101772490B1 (ko) 인쇄회로기판 어셈블리
JP4844216B2 (ja) 多層回路配線基板及び半導体装置
US8785787B2 (en) Metal-based circuit board
KR101139084B1 (ko) 다층 프린트 기판 및 그 제조 방법
US9220164B2 (en) High frequency module
JPWO2020100849A1 (ja) 実装型電子部品、および、電子回路モジュール
CN107958875B (zh) 半导体装置以及布线基板的设计方法
US9922918B2 (en) Substrate for stacked module, stacked module, and method for manufacturing stacked module
US9437559B2 (en) High-frequency module
JP7020629B2 (ja) 半導体装置
JP2019040903A (ja) 回路基板及び半導体モジュール
US20210203302A1 (en) Multilayer body and method of manufacturing the same
JP4942452B2 (ja) 回路装置
JP6089557B2 (ja) 電子部品モジュール
JP6256575B2 (ja) 高周波モジュール
JP4589743B2 (ja) 半導体装置
KR102345061B1 (ko) 반도체 패키지
US20170257948A1 (en) Electronic device and method for manufacturing electronic device
JP4359110B2 (ja) 回路装置
CN111149177B (zh) 电感器及其制造方法
JP6370652B2 (ja) 半導体装置
JP2000138251A (ja) 半導体装置及び配線基板
KR100926088B1 (ko) 카트리지를 이용한 임베디드 반도체 패키지 및 그 제조 방법

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant