Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B12/00—Dynamic random access memory [DRAM] devices
  • H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
  • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
  • G11C11/409—Read-write [R-W] circuits 
  • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
  • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
  • H10D30/6733—Multi-gate TFTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
  • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
  • H10D30/6735—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes having gates fully surrounding the channels, e.g. gate-all-around

Definitions

• the present invention relates to a semiconductor memory device.
• SGT Silicon Gate Transistor
• Non-Patent Document 1 Using SGT (Surrounding Gate Transistor, see Patent Document 1, Non-Patent Document 1) as a selection transistor, connect a DRAM (Dynamic Random Access Memory, see Non-Patent Document 2, for example) with a capacitor connected, and a variable resistance element.
• PCM Phase Change Memory, see, for example, Non-Patent Document 3
• RRAM Resistive Random Access Memory
• MRAM Magneto-resistive Random Access Memory
• DRAM memory cells that are configured with one MOS transistor and do not have a capacitor. For example, holes, electron groups, or part or all of the hole groups generated in the channel by the impact ionization phenomenon due to the current between the source and drain of an N-channel MOS transistor are held in the channel to store logic storage data. 1” is written. Then, the hole group is removed from the channel to write logical storage data "0".
• the challenges of this memory cell are to improve the reduction in operating margin due to floating body channel voltage fluctuations, and to improve the reduction in data retention characteristics due to the removal of part of the hole group, which is the signal charge accumulated in the channel. It is.
• Twin-Transistor MOS transistor memory element in which one memory cell is formed using two MOS transistors in an SOI layer (see, for example, Patent Documents 2 and 3 and Non-Patent Document 11).
• an N + layer that serves as a source or drain that separates floating body channels of two MOS transistors is formed in contact with an insulating layer on the substrate side.
• a group of holes, which are signal charges, are accumulated in the channel of one MOS transistor. The problem is to improve the deterioration in data retention characteristics caused by the removal of part of the hole group, which is the signal charge.
• FIG. 4 there is a memory shown in FIG. 4 that is configured with MOS transistors and does not have a capacitor (see Patent Document 2 and Non-Patent Document 12).
• FIG. 4(a) there is a floating body semiconductor base body 102 on the SiO2 layer 101 of the SOI substrate. At both ends of the floating body semiconductor body 102, there are an n+ layer 103 connected to the source line SL and an N+ layer 104 connected to the bit line BL. Then, a first gate insulating layer 109a connected to the n+ layer 103 and covering the floating body semiconductor base 102, and a second gate insulating layer 109b connected to the n+ layer 104 and covering the floating body semiconductor base 102. be.
• first gate conductor layer 105a covering the first gate insulating layer 109a and connected to the plate line PL, and a second gate conductor layer covering the second gate insulating layer 109b and connected to the word line WL.
• 105b There is an insulating layer 110 between the first gate conductor layer 105a and the second gate conductor layer 105b.
• a DFM memory cell 111 is formed.
• the source line SL may be connected to the n+ layer 104 and the bit line BL may be connected to the n+ layer 103.
• the electric field becomes maximum in the boundary region of the channel region between the first N-channel MOS transistor region and the second N-channel MOS transistor region, and an impact ionization phenomenon occurs in this region.
• the electron group among the electron/hole groups generated by the impact ionization phenomenon is removed from the floating body semiconductor matrix 102, and part or all of the hole group 106 is transferred to the floating body semiconductor matrix 102.
• a memory write operation is performed by holding it in the body semiconductor matrix 102.
• the hole group 106 is moved into a floating body. It is removed from the semiconductor matrix 102 to perform an erasing operation. This state becomes logical storage data "0".
• the voltage applied to the first gate conductor layer 105a connected to the plate line PL is set to be higher than the threshold voltage when the logical storage data is "1" and higher than the threshold voltage when the logical storage data is "0".
• the channels of the first and second N-channel MOS transistor regions whose gates are the first gate conductor layer 105a connected to the plate line PL and the second gate conductor layer 105b connected to the word line WL are By connecting through the floating body semiconductor base body 102, voltage fluctuations in the floating body semiconductor base body 102 when a selection pulse voltage is applied to the word line WL are greatly suppressed.
• the problems of the aforementioned memory cell such as a reduction in the operating margin or a reduction in data retention characteristics due to the removal of a portion of the hole group, which is the signal charge accumulated in the channel, can be greatly improved. In the future, further improvements in the characteristics of this memory element will be required.
• An object of the present invention is to provide a method for stably erasing memory information in a dynamic flash memory, which is a memory device.
• a memory device using a semiconductor element includes: a semiconductor matrix extending horizontally or vertically on the substrate; a first impurity layer and a second impurity layer connected to both ends of the semiconductor matrix; a first gate insulating layer covering the semiconductor matrix; a first gate conductor layer covering the first gate insulating layer; a second gate insulating layer connected to the first gate insulating layer and covering the semiconductor base; a second gate conductor layer that covers the second gate insulating layer without contacting the first gate conductor layer, Applying a voltage so as to create a potential difference between the first impurity layer and the second impurity layer, and containing 0 V to either the first gate conductor layer or the second gate conductor layer; A voltage between 0 V and the threshold voltage is applied, and a voltage with the same polarity and an absolute value greater than the threshold voltage is applied to the other gate conductor layer, so that the remaining gate conductor layer remains in the semiconductor matrix. performing a memory erasing
• a source line is connected to the first impurity layer
• a bit line is connected to the second impurity layer
• the first gate conductor layer and the second gate conductor layer are connected to each other.
• One of the conductor layers is connected to a word line, and the other is connected to a plate line, and a voltage is applied to each of the source line, bit line, plate line, and word line to perform a memory write operation and a memory read operation. and the memory erasing operation to operate a dynamic flash memory (second invention).
• the first impurity layer, the second impurity layer, and the second impurity layer when the majority carriers of the semiconductor matrix are holes during the erasing operation of the dynamic flash memory, the first impurity layer, the second impurity layer, and the second impurity layer
• the voltage applied to the first gate conductor layer and the second gate conductor layer is 0V or a positive potential (third invention).
• the first impurity layer when the majority carriers of the semiconductor matrix are electrons, the first impurity layer, the second impurity layer, and the first The voltage applied to the gate conductor layer and the second gate conductor layer is 0V or a negative potential (fourth invention).
• either the source line or the bit line is at 0V in the memory erase operation of the dynamic flash memory (fifth invention).
• a first MOS transistor region comprising the first gate insulating layer and the first gate conductor layer is provided on the word line.
• a voltage having an absolute value greater than or equal to the absolute value of the threshold value and having the same polarity as the threshold value is applied, and the plate line is connected to the second gate insulating layer and the second gate conductor layer.
• a voltage having an absolute value greater than or equal to the absolute value of the threshold value of the second MOS transistor region consisting of A voltage that causes impact ionization is applied to the source line, 0V is applied to the source line, and an impact ionization phenomenon is caused by a current flowing between the first impurity layer and the second impurity layer, and electrons are an operation of generating a group of electrons and a group of holes in the semiconductor matrix and the first impurity layer;
• the method is characterized in that a part or all of the hole group remains in the semiconductor matrix (sixth invention).
• the absolute value of the current flowing through the bit line during the memory erase operation of the dynamic flash memory is lower than the absolute value of the current flowing through the bit line during the memory write operation of the dynamic flash memory. (Seventh invention).
• the voltages applied to the plate line, the word line, the source line, and the bit line are 0V or all It is characterized by having the same polarity (eighth invention).
• FIG. 1 is a diagram showing a cross-sectional structure of a memory device using a semiconductor element according to a first embodiment
• FIG. 1 is a diagram showing a cross-sectional structure of a memory device using a semiconductor element according to a first embodiment
• FIG. 3 is a diagram for explaining accumulation of hole carries and cell current during a write operation of the memory device using the semiconductor element according to the first embodiment.
• FIG. 3 is a diagram for explaining an erase operation of the memory device using the semiconductor element according to the first embodiment.
• FIG. 2 is a diagram showing the cross-sectional structure and operation of a conventional dynamic flash memory device.
• FIGS. 1A and 1B are also referred to as FIG. 1).
• FIGS. 1A and 1B are also referred to as FIG. 1.
• FIG. 1 shows the structure of a memory using a semiconductor element according to a first embodiment of the present invention.
• FIG. 1(a) is a plan view
• FIG. 1(b) is a vertical cross-sectional view taken along line XX' in FIG. 1(a).
• (c) is a cross-sectional view along the Y1-Y1' line
• (d) is an additional example of (c), which is a cross-sectional view along the Y1-Y1' line.
• (e) is a cross-sectional view along the Y2-Y2' line in (a)
• (f) is an additional example of (e), which is a cross-sectional view along the Y2-Y2' line.
• the structure (c) can be replaced with a structure (d)
• the structure (e) can be replaced with a structure (f).
• a p layer 1 is a silicon semiconductor matrix having a conductivity type of p-type or i-type (intrinsic type) containing acceptor impurities. (This is an example of a "semiconductor matrix").
• An n+ layer 2 (hereinafter, a semiconductor region containing donor impurities at a high concentration is referred to as an "n+ layer") on one side of the p layer 1 in the horizontal direction (an example of a "first impurity layer” in the claims) ).
• n+ layer 3 On the opposite side of the n+ layer 2 is an n+ layer 3 (which is an example of a "second impurity layer” in the claims).
• a gate insulating layer 4 (which is an example of a "first gate insulating layer” in the claims) covering the p layer 1 and in contact with or near the n+ layer 2.
• a first gate conductor layer 5 (which is an example of a “first gate conductor layer” in the claims) surrounds part or all of the gate insulating layer 4 and is close to the n+ layer 2.
• a gate insulating layer 6 (an example of a "second gate insulating layer” in the claims) is formed on a part of the surface of the p layer 1 and in contact with or near the n+ layer 3. ).
• a second gate conductor layer 7 (which is an example of a "second gate conductor layer” in the claims) surrounds the gate insulating layer 6 and forms an n+ layer without contacting the first gate conductor layer 5. It is close to 3.
• one dynamic flash memory cell is formed by the p layer 1, n+ layer 2, n+ layer 3, gate insulating layer 4, first gate conductor layer 5, gate insulating layer 6, and second gate conductor layer 7. It is formed.
• the n+ layer 2 is connected to the source line SL (which is an example of the "source line” in the claims) which is a wiring conductor
• the gate conductor layer 5 is connected to the word line WL (which is an example of the "source line” in the claims) which is a wiring conductor.
• the gate conductor layer 7 is connected to a plate line PL (which is an example of a "plate line” in the claims) which is a wiring conductor.
• the n+ layer 3 is connected to a bit line BL (which is an example of a "bit line” in the claims) which is a wiring conductor.
• Dynamic flash memory operates by manipulating the potentials of the source line, bit line, plate line, and word line individually. In the memory device of this embodiment, the plurality of dynamic flash memory cells described above are arranged two-dimensionally or three-dimensionally.
• a dynamic flash memory can also be configured with a structure in which the gate conductor layer 7 and the gate insulating layer 6 are divided above and below the p-layer 1 and surround only part of the p-layer 1, as shown in FIG. 1(d). Furthermore, as shown in FIG. 1(f), the first gate conductor layer 5 and gate insulating layer 4 may also be divided into upper and lower parts of the p-layer 1, and a structure in which only a part of the p-layer 1 is surrounded can constitute a dynamic flash memory. can.
• any insulating film used in a normal MOS process can be used for the gate insulating layers 4 and 6, such as a SiO2 film, a SiON film, a HfSiON film, or a laminated film of SiO2/SiN.
• the p layer 1 is made of a p-type semiconductor, but there may be a profile in the impurity concentration. Further, there may be a profile in the impurity concentration of the n+ layer 2 and the n+ layer 3. Further, an LDD (Lightly Doped Drain) may be provided between the p layer 1 and the n+ layers 2 and 3.
• LDD Lightly Doped Drain
• the p layer 1 is If it is an n-type semiconductor, the Dynac flash memory operates by using electrons as carriers for writing.
• the potential of a part of the memory cell can be changed by the first gate conductor layer 5 through the gate insulating layer 4 and the second gate conductor layer 7 through the gate insulating layer 6, for example, It may be a metal such as W, Pd, Ru, Al, TiN, TaN, or WN, a metal nitride, or an alloy thereof (including silicide), for example, a laminated structure such as TiN/W/TaN, It may also be formed of a heavily doped semiconductor.
• the memory cell has been described as having a rectangular cross-sectional structure perpendicular to the plane of the paper in FIG. 1A, but the memory cell may have a trapezoidal or polygonal shape, or the memory cell itself may have a cylindrical shape.
• the second gate conductor layer 7 is present at two locations on both sides of the upper and lower sides of the p-layer 1, but the dynamic flash memory can operate even if either one is present. This also applies to the first gate conductor layer 5.
• first gate conductor layer 5 and the second gate conductor layer 7 are each shown as being integral in the memory cell, but they may be divided in the horizontal or vertical direction. I do not care. Furthermore, the first gate conductor layer 5 and the second gate conductor layer 7 may be formed of different conductor material layers. Further, the gate insulating layer 4 and the gate insulating layer 6 may be formed of different insulating material layers.
• the first MOS transistor region whose gate is the part having the first gate conductor layer 5 is a WL-FET (field effect MOS transistor region connected to the word line WL), and the second gate conductor layer 7 is used as the first MOS transistor region.
• a PL-FET (a field effect MOS transistor region connected to the plate line PL) is shown as a second MOS transistor region.
• the threshold value of the WL-FET is expressed as Vth-WL
• the threshold value of the PL-FET is expressed as Vth-PL.
• the majority carriers in the n+ layer 2 and the n+ layer 3 are electrons, and for example, the first gate conductor layer 5 connected to the word line WL and the second gate connected to the plate line PL.
• n+ poly hereinafter, poly Si containing a high concentration of donor impurities is referred to as "n+ poly”
• n+ poly poly Si containing a high concentration of donor impurities
• p layer 1 a p-type semiconductor
• the voltage conditions to be applied to the bit line BL, source line SL, word line WL, and plate line PL are such that the voltage applied to the bit line is, for example, 10% higher than the higher voltage of Vth-PL. % or higher voltage is applied to the plate line, an inversion layer is formed on a part or the entire surface of the interface between the second gate insulating layer 6 and the p-layer 1 of the PL-FET, and the potential of the bit line is changed to the potential of the PL-FET. transmitting across the channel and applying a voltage higher than, for example, WL-Vth to the word line so that current flows from the bit line to the source line. Further, it is necessary to apply a voltage to the bit line such that the maximum electric field for causing impact ionization is, for example, 10 5 V/cm or more.
• 0V is input to the source line SL connected to the n+ layer 2
• 1.0V is input to the bit line BL connected to the n+ layer 3.
• 1.5V is inputted to the plate line PL connected to the gate conductor layer 7, and 1.2V is inputted to the gate conductor layer 5 connected to the word line WL.
• an inversion layer 14b is formed directly under the gate insulating layer 7 over the entire surface. Then, an inversion layer 14a is partially formed directly under the gate insulating layer 4. A pinch-off point 15 where the inversion layer 14a disappears exists directly under the gate insulating layer 4, and the electric field is at its maximum here. In this example, the maximum electric field is approximately 4 ⁇ 10 5 V/cm. Then, electrons flow from the n+ layer 2 toward the n+ layer 3. As a result, an impact ionization phenomenon occurs in the region near the pinch-off point 15.
• FIG. 2(b) shows the hole group 17 in the p-layer 1 when all biases become 0V immediately after writing.
• the generated hole group 17 is the majority carrier in the p-layer 1, and is temporarily accumulated in the p-layer 1 surrounded by the depletion layer 16, and in a non-equilibrium state, it is substantially used in the WL-FET or PL-FET.
• the p-layer 1, which is the substrate, is charged to a positive bias.
• the threshold voltage of the WL-FET with the gate conductor layer 5 and the threshold voltage of the PL-FET with the gate conductor layer 7 are increased due to the holes temporarily accumulated in the p-layer 1. Due to the bias effect, it becomes lower than the initial state.
• the voltage conditions applied to the bit line BL, source line SL, word line WL, and plate line PL are 1.0V (BL) / 0V (SL) / 2V (PL) / 2.0V(WL), 1.5V(BL)/0V(SL)/3V(PL)/1V(WL), 1.0V(BL)/0V(SL)/1.2V(PL)/2.
• a combination of 0V (WL), etc. is also possible.
• 1.0V is applied to the bit line BL, 0V to the source line SL, 2V to the word line WL, and 1.2V to the plate line PL, the position of the pinch-off point 15 shifts toward the gate conductor layer 7.
• a similar phenomenon can occur.
• the erase operation mechanism of the dynamic flash memory of the first embodiment will be explained using FIG. 3.
• the voltage conditions applied to the bit line BL, source line SL, word line WL, and plate line PL are as follows: By applying a voltage higher than the voltage to the plate line, an inversion layer 14b is formed at the interface between the gate oxide film 6 of the PL-FET and the p layer 1, and the recombination area of the holes and electrons accumulated in the p layer 1 is increased.
• the voltage applied to the bit line may be such that a maximum electric field of, for example, 10 4 V/cm or more is applied so that electrons injected from the source can drift to the bit line.
• FIG. 3 An example of the erase operation of the dynamic flash memory of the first embodiment shown in FIG. 1 will be explained using FIG. 3. From the state shown in FIG. 2B, a voltage of 0.6 V is applied to the bit line BL, 0 V to the source line SL, 2 V to the plate line PL, and 0 V to the word line WL. As a result, since the concentration of holes 17 accumulated in the p layer 1 is sufficiently higher than the hole concentration in the n+ layer 2, holes flow into the n+ layer 2 by diffusion due to the concentration gradient. Conversely, since the electron concentration in the n+ layer 2 is higher than the electron concentration in the p layer 1, electrons 18 flow into the p layer 1 by diffusion due to the concentration gradient.
• the electrons flowing into the p-layer 1 recombine with holes in the p-layer 1 and disappear. However, all of the injected electrons 18 are not annihilated, and the unannihilated electrons 18 flow into the n+ layer 3 through the depletion layer 16 due to drift due to the potential gradient of the bit line BL and source line SL. Since electrons are supplied one after another from the source line SL, excess holes recombine with electrons in a very short time and return to the initial state. The power consumed here is due to electrons flowing in from the source line SL, and is extremely smaller than the power consumption during writing. As a result, as shown in FIG.
• the WL-FET having the gate conductor layer 5 connected to the word line WL and the PL-FET having the gate conductor layer 7 return to their original threshold values. As shown in FIG. 3(c), no current flows in the WL-FET having the gate conductor layer 5 connected to the word line WL even if the voltage of WL is increased. The erased state of this memory element becomes logical storage data "0".
• a voltage of 1.5 times or more of the word line Vth-WL is applied to form an inversion layer
• a plate voltage of 0 V or lower than Vth-PL is applied to prevent the formation of an inversion layer. can also be deleted in the same way.
• a more accurate expression is to express the threshold value in terms of its “absolute value and plus/minus polarity.”
• one example would be "apply a voltage that has an absolute value greater than or equal to the absolute value of the threshold value of the MOS transistor region and has the same polarity as the threshold value.”
• the first gate conductor layer 5 adjacent to the n+ layer 2 is connected to the word line WL
• the second gate conductor layer 7 adjacent to the n+ layer 3 is connected to the plate line PL. ing.
• the main The memory erasing operation of the invention is possible.
• the voltage conditions applied to the bit line BL, source line SL, word line WL, and plate line PL are 0.6V (BL) / 0V (SL) / 2V(PL)/0V(WL), 0V(BL)/0.6V(SL)/0V(PL)/2V(WL), 0.6V(BL)/0V(SL)/2V(PL)/0 Combinations such as .2V (WL), 1.5V (BL) / 0V (SL) / 2V (PL) / 0V (WL), etc. are also possible, and the above bit line BL, source line SL, word line WL,
• the voltage condition applied to the plate line PL is an example for performing the memory erasing operation, and may be another operating condition that allows the memory erasing operation.
• the PL-FET or WL-FET is a p-type channel type
• the p layer 1 becomes an n-type semiconductor
• the donor concentration becomes the majority carrier
• the polarity of the potential applied to the bit line, word line, and plate line is shown in the example. All positive potentials become negative potentials.
• the present dynamic flash memory cell may have a structure that satisfies the condition that the hole group 17 generated by the impact ionization phenomenon is retained in the p layer 1.
• the p layer 1 may have a floating body structure separated from the substrate 20. From this, the p layer 1 can be attached to the substrate 20 using, for example, GAA (Gate All Around: see Non-Patent Document 10, for example) technology, which is one of the SGTs, or Nanosheet technology (see, for example, Non-Patent Documents 11 and 12).
• GAA Gate All Around: see Non-Patent Document 10, for example
• Nanosheet technology see, for example, Non-Patent Documents 11 and 12.
• a device structure using SOI Silicon On Insulator
• SOI Silicon On Insulator
• the bottom of the channel region is in contact with the insulating layer of the SOI substrate, and the other channel region is surrounded by a gate insulating layer and an element isolation insulating layer.
• the channel region has a floating body structure.
• the dynamic flash memory element provided by this embodiment only needs to satisfy the condition that the channel region has a floating body structure.
• this dynamic flash operation can be performed if the channel region has a floating body structure.
• This embodiment has the following features.
• (Feature 1) In the memory erasing operation of this embodiment, the memory erasing operation can be performed with low power consumption.
• the feature of the present invention is that an inversion layer 14b is formed in the p layer 1 of the PL-FET, connected to the n+ layer 3, during the memory erase operation period.
• the area where the holes accumulated in the memory cell and electrons recombine is determined by the contact area between the n+ layer 3 and the p layer 1, while when erasing the memory, the area directly under the gate insulating layer 6
• the area where holes and electrons recombine can be increased compared to when the memory is held, and the electron-hole recombination phenomenon increasing the chances of it happening.
• the WL-FET since the WL-FET is not in the on state at this time, no current flows from the bit line BL to the source line SL, and therefore no impact ionization that inhibits the erase operation occurs in the p layer 1.
• the semiconductor element according to the present invention it is possible to provide a semiconductor memory device with higher density, higher speed, and higher operating margin than conventional devices.

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