KR20250009483A - 반도체 메모리 장치 - Google Patents
반도체 메모리 장치 Download PDFInfo
- Publication number
- KR20250009483A KR20250009483A KR1020247040930A KR20247040930A KR20250009483A KR 20250009483 A KR20250009483 A KR 20250009483A KR 1020247040930 A KR1020247040930 A KR 1020247040930A KR 20247040930 A KR20247040930 A KR 20247040930A KR 20250009483 A KR20250009483 A KR 20250009483A
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- memory
- gate conductor
- conductor layer
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
- H10D30/6733—Multi-gate TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
- H10D30/6735—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes having gates fully surrounding the channels, e.g. gate-all-around
Landscapes
- Engineering & Computer Science (AREA)
- Databases & Information Systems (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2022/023426 WO2023238370A1 (ja) | 2022-06-10 | 2022-06-10 | 半導体メモリ装置 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20250009483A true KR20250009483A (ko) | 2025-01-17 |
Family
ID=89076654
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020247040930A Ceased KR20250009483A (ko) | 2022-06-10 | 2022-06-10 | 반도체 메모리 장치 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US12362005B2 (https=) |
| JP (1) | JPWO2023238370A1 (https=) |
| KR (1) | KR20250009483A (https=) |
| CN (1) | CN119366278A (https=) |
| TW (1) | TWI863343B (https=) |
| WO (1) | WO2023238370A1 (https=) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7705671B2 (ja) * | 2022-03-16 | 2025-07-10 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体を用いたメモリ装置 |
| WO2023238370A1 (ja) * | 2022-06-10 | 2023-12-14 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体メモリ装置 |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02188966A (ja) | 1989-01-17 | 1990-07-25 | Toshiba Corp | Mos型半導体装置 |
| US20030111681A1 (en) | 2001-12-14 | 2003-06-19 | Kabushiki Kaisha Toshiba | Semiconductor memory device and its manufacturing method |
| US20080137394A1 (en) | 2006-12-12 | 2008-06-12 | Renesas Technology Corp. | Semiconductor memory device |
| JP7057032B1 (ja) | 2020-12-25 | 2022-04-19 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体素子を用いたメモリ装置 |
Family Cites Families (32)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7919800B2 (en) | 2007-02-26 | 2011-04-05 | Micron Technology, Inc. | Capacitor-less memory cells and cell arrays |
| JP2013197269A (ja) * | 2012-03-19 | 2013-09-30 | Toshiba Corp | 不揮発性半導体記憶装置 |
| CN107592943B (zh) * | 2015-04-29 | 2022-07-15 | 芝诺半导体有限公司 | 提高漏极电流的mosfet和存储单元 |
| US10013798B2 (en) * | 2016-08-30 | 2018-07-03 | The Boeing Company | 3D vehicle localizing using geoarcs |
| WO2018063205A1 (en) * | 2016-09-29 | 2018-04-05 | Intel Corporation | On-chip wireless communication devices for qubits |
| KR102051306B1 (ko) * | 2018-02-28 | 2019-12-03 | 가천대학교 산학협력단 | 핀펫 구조를 갖는 폴리실리콘 기반의 1t 디램 셀 소자 및 그 제조방법 |
| US20220367473A1 (en) * | 2020-12-25 | 2022-11-17 | Unisantis Electronics Singapore Pte. Ltd. | Memory device using semiconductor element |
| US20230301057A1 (en) * | 2020-12-25 | 2023-09-21 | Unisantis Electronics Singapore Pte. Ltd. | Memory device including pillar-shaped semiconductor element |
| US12120864B2 (en) * | 2020-12-25 | 2024-10-15 | Unisantis Electronics Singapore Pte. Ltd. | Memory device using semiconductor element |
| US12048140B2 (en) * | 2020-12-25 | 2024-07-23 | Unisantis Electronics Singapore Pte. Ltd. | Memory device using semiconductor element |
| JP7057037B1 (ja) | 2021-01-29 | 2022-04-19 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体素子を用いたメモリ装置 |
| US20220392900A1 (en) * | 2021-03-29 | 2022-12-08 | Unisantis Electronics Singapore Pte. Ltd. | Memory device using semiconductor element and method for manufacturing the same |
| WO2022208658A1 (ja) * | 2021-03-30 | 2022-10-06 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | メモリ素子を有する半導体装置 |
| WO2022215155A1 (ja) * | 2021-04-06 | 2022-10-13 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体素子を用いたメモリ装置 |
| WO2022219696A1 (ja) * | 2021-04-13 | 2022-10-20 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体素子を用いたメモリ装置 |
| WO2022219703A1 (ja) * | 2021-04-13 | 2022-10-20 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体素子を用いたメモリ装置 |
| WO2022219704A1 (ja) * | 2021-04-13 | 2022-10-20 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体素子を用いたメモリ装置 |
| WO2022219763A1 (ja) * | 2021-04-15 | 2022-10-20 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体素子を用いたメモリ装置 |
| WO2022219767A1 (ja) * | 2021-04-15 | 2022-10-20 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | メモリ素子を有する半導体装置 |
| WO2022234614A1 (ja) * | 2021-05-06 | 2022-11-10 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体素子を用いたメモリ装置 |
| WO2022234656A1 (ja) * | 2021-05-07 | 2022-11-10 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体素子を有するメモリ装置 |
| WO2022239193A1 (ja) * | 2021-05-13 | 2022-11-17 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体素子を用いたメモリ装置 |
| WO2022239192A1 (ja) * | 2021-05-13 | 2022-11-17 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体素子を用いたメモリ装置 |
| WO2022239199A1 (ja) * | 2021-05-13 | 2022-11-17 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体素子を用いたメモリ装置 |
| WO2022269740A1 (ja) * | 2021-06-22 | 2022-12-29 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体素子を用いたメモリ装置 |
| WO2022269737A1 (ja) * | 2021-06-22 | 2022-12-29 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体素子を用いたメモリ装置 |
| WO2023281728A1 (ja) * | 2021-07-09 | 2023-01-12 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体素子を用いたメモリ装置 |
| WO2023058242A1 (ja) * | 2021-10-08 | 2023-04-13 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体素子を用いたメモリ装置 |
| WO2023105604A1 (ja) * | 2021-12-07 | 2023-06-15 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体素子を用いたメモリ装置 |
| WO2023112146A1 (ja) * | 2021-12-14 | 2023-06-22 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | メモリ装置 |
| WO2023238370A1 (ja) * | 2022-06-10 | 2023-12-14 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体メモリ装置 |
| WO2024042609A1 (ja) * | 2022-08-23 | 2024-02-29 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体素子を用いたメモリ装置 |
-
2022
- 2022-06-10 WO PCT/JP2022/023426 patent/WO2023238370A1/ja not_active Ceased
- 2022-06-10 KR KR1020247040930A patent/KR20250009483A/ko not_active Ceased
- 2022-06-10 CN CN202280096983.6A patent/CN119366278A/zh active Pending
- 2022-06-10 JP JP2024526189A patent/JPWO2023238370A1/ja active Pending
-
2023
- 2023-06-08 US US18/331,328 patent/US12362005B2/en active Active
- 2023-06-12 TW TW112121844A patent/TWI863343B/zh active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02188966A (ja) | 1989-01-17 | 1990-07-25 | Toshiba Corp | Mos型半導体装置 |
| US20030111681A1 (en) | 2001-12-14 | 2003-06-19 | Kabushiki Kaisha Toshiba | Semiconductor memory device and its manufacturing method |
| US20080137394A1 (en) | 2006-12-12 | 2008-06-12 | Renesas Technology Corp. | Semiconductor memory device |
| JP7057032B1 (ja) | 2020-12-25 | 2022-04-19 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体素子を用いたメモリ装置 |
Non-Patent Citations (15)
| Title |
|---|
| E. Yoshida : "A Capacitorless 1T-DRAM Technology Using Gate-Induced Drain-Leakage (GIDL) Current for Low-Power and High-Speed Embedded Memory," IEEE IEDM (2006). |
| F. Morishita, H. Noda, I. Hayashi, T. Gyohten, M. Oksmoto, T. Ipposhi, S. Maegawa, K. Dosaka, and K. Arimoto : "Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI," IEICE Trans. Electron., Vol.E90-c., No.4 pp.765 - 771(2007) |
| H. Chung, H. Kim, H. Kim, K. Kim, S. Kim, K. Dong, J. Kim, Y. C. Oh, Y. Hwang, H. Hong, G. Jin, and C. Chung : "4F2 DRAM Cell with Vertical Pillar Transistor (VPT)," 2011 Proceeding of the European Solid-State Device Research Conference, (2011) |
| H. Jiang, N. Xu, B. Chen, L. Zeng1, Y. He, G. Du, X. Liu and X. Zhang : "Experimental investigation of self heating effect (SHE) in multiple-fin SOI FinFETs," Semicond. Sci. Technol. 29 115021 pp.7(2014). |
| H. S. Philip Wong, S. Raoux, S. Kim, Jiale Liang, J. R. Reifenberg, B. Rajendran, M. Asheghi and K. E. Goodson : "Phase Change Memory," Proceeding of IEEE, Vol.98, No 12, December, pp.2201 - 2227(2010) |
| Hiroshi Takato, Kazumasa Sunouchi, Naoko Okabe, Akihiro Nitayama, Katsuhiko Hieda, Fumio Horiguchi, and Fujio Masuoka : IEEE Transaction on Electron Devices, Vol.38, No.3, pp.573 - 578(1991) |
| J. Wan, L. Rojer, A. Zaslavsky, and S. Critoloveanu : "A Compact Capacitor-Less High-Speed DRAM Using Field Effect-Controlled Charge Regeneration," Electron Device Letters, Vol.35, No.2, pp.179 - 181(2012) |
| J. Y. Song, W. Y. Choi, J. H. Park, J. D. Lee, and B - G. Park : "Design Optimization of Gate-All-Around (GAA) MOSFETs," IEEE Trans. Electron Devices, vol.5, no.3, pp.186 - 191,(2006) |
| K. Sakui, N. Harada, "Dynamic Flash Memory with Dual Gate Surrounding Gate Transistor (SGT)," Proc. IEEE IMW, pp.72 - 75(2021) |
| M. G. Ertosum, K. Lim, C. Park, J. Oh, P. Kirsch, and K. C. Saraswat : "Novel Capacitorless Single-Transistor Charge-Trap DRAM (1T CT DRAM) Utilizing Electron," IEEE Electron Device Letter, Vol.31, No.5, pp.405 - 407(2010) |
| N. Loubet, et al. : "Stacked Nanosheet Gate-All-Around Transistor to Enable Scaling Beyond FinFET," 2017 IEEE Symposium on VLSI Technology Digest of Technical Papers, T17 - 5, T230 - T231,(2017) |
| T. Shino, N. Kusunoki, T. Higashi, T. Ohsawa, K. Fujita, K. Hatsuda, N. Ikumi, F. Matsuoka, Y. Kajitani, R. Fukuda, Y. Watanabe, Y. Minami, A. Sakamoto, J. Nishimura, H. Nakajima, M. Morikado, K. Inoh, T. Hamamoto, A. Nitayama : "Floating Body RAM Technology and its Scalability to 32nm Node and Beyond," IEEE IEDM (2006). |
| T. Tsunoda, K. Kinoshita, H. Noshiro, Y. Yamazaki, T. Iizuka, Y. Ito, A. Takahashi, A. Okano, Y. Sato, T. Fukano, M. Aoki, and Y. Sugiyama : "Low Power and high Speed Switching of Ti-doped NiO ReRAM under the Unipolar Voltage Source of less than 3V," IEDM (2007) |
| Takashi Ohasawa and Takeshi Hamamoto, "Floating Body Cell - a Novel Body Capacitorless DRAM Cell", Pan Stanford Publishing (2011). |
| W. Kang, L. Zhang, J. Klein, Y. Zhang, D. Ravelosona, and W. Zhao : "Reconfigurable Codesign of STT-MRAM Under Process Variations in Deeply Scaled Technology," IEEE Transaction on Electron Devices, pp.1 - 9(2015) |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2023238370A1 (ja) | 2023-12-14 |
| US20230402089A1 (en) | 2023-12-14 |
| TW202406109A (zh) | 2024-02-01 |
| JPWO2023238370A1 (https=) | 2023-12-14 |
| US12362005B2 (en) | 2025-07-15 |
| TWI863343B (zh) | 2024-11-21 |
| CN119366278A (zh) | 2025-01-24 |
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