WO2023221172A1 - 显示面板及显示面板的制备方法 - Google Patents

显示面板及显示面板的制备方法 Download PDF

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Publication number
WO2023221172A1
WO2023221172A1 PCT/CN2022/096360 CN2022096360W WO2023221172A1 WO 2023221172 A1 WO2023221172 A1 WO 2023221172A1 CN 2022096360 W CN2022096360 W CN 2022096360W WO 2023221172 A1 WO2023221172 A1 WO 2023221172A1
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Prior art keywords
gate
electrode
transistor
display panel
layer
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PCT/CN2022/096360
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English (en)
French (fr)
Inventor
蒙艳红
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广州华星光电半导体显示技术有限公司
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Priority to US17/758,027 priority Critical patent/US20240170493A1/en
Publication of WO2023221172A1 publication Critical patent/WO2023221172A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Definitions

  • the present application relates to the field of display technology, and in particular, to a display panel and a method for manufacturing the display panel.
  • the preparation process of optical sensing circuits is complex, resulting in long production cycles and high costs.
  • the light sensing transistor is first prepared, and then the driving transistor is prepared.
  • the preparation of photosensitive transistors and the preparation of driving transistors are carried out independently, and the mask process required is relatively complex.
  • This application is mainly aimed at the technical problems of the complex photomask process of light sensing circuits.
  • the present application proposes a display panel and a method for manufacturing a display panel, which can prepare the first source electrode, the first drain electrode and the second gate electrode in one process, thereby reducing the use of photomasks. times, improve the preparation efficiency of the display panel, further reduce the production cost, and is simple and convenient.
  • a display panel includes a plurality of pixel units arranged in an array. At least one of the pixel units is provided with a first transistor and a second transistor.
  • the first transistor includes a first gate electrode, a first source electrode and a first drain electrode
  • the second transistor includes a second gate electrode, a second source electrode and a second drain electrode; wherein the first source electrode, first drain electrode and The second gate is located on the same layer.
  • the display panel further includes: a substrate, the first gate is disposed on the substrate; a first gate insulating layer is disposed on the first gate; a first active layer is disposed on on the first gate insulating layer and at least partially overlapping the first gate; a first source electrode and a first drain electrode are provided on the first active layer; a second gate insulating layer, disposed on the first source and first drain; and a second active layer disposed on the second gate insulating layer, and the second active layer and the second gate are at least Partially overlapped settings.
  • one end of the second gate is in contact with the first gate insulating layer, and the other end of the second gate is flush with one end of the second active layer.
  • the display panel further includes: a second source electrode and a second drain electrode, the second source electrode and the second drain electrode are spaced apart on the second active layer; a planarization layer is provided. On the second source electrode and the second drain electrode, a via hole is provided on the planarization layer for exposing at least one of the second source electrode and the second drain electrode; first A metal layer is provided on the planarization layer, and the first metal layer extends in the via hole and is connected to at least one of the second source electrode and the second drain electrode.
  • the first source electrode, the first drain electrode and the second gate electrode are arranged at intervals, the display panel includes a connection line, the connection line is arranged in the same layer as the second gate electrode, and The second gate electrode is electrically connected to one of the first source electrode or the first drain electrode.
  • connection line is disposed close to the first active layer, and the other end of the connection line is in contact with one end of the second gate.
  • the first active layer is made of amorphous silicon material
  • the second active layer is made of oxide semiconductor material.
  • the first transistor is a light-sensing transistor, used to sense external light and generate a light-sensing signal when light is sensed.
  • the second transistor is a driving transistor for transmitting the light sensing signal to the driving transistor through the drain or source of the light sensing transistor and the connecting line when the light sensing transistor senses light.
  • the gate of the transistor is a driving transistor for transmitting the light sensing signal to the driving transistor through the drain or source of the light sensing transistor and the connecting line when the light sensing transistor senses light.
  • first gate electrode, the first source electrode, the first drain electrode, and the second gate electrode, the second source electrode, and the second drain electrode are all made of a metal layer.
  • the first transistor is N-type or P-type
  • the second transistor is N-type or P-type
  • a method of manufacturing a display panel is provided.
  • the method of manufacturing the display panel is applied to the display panel.
  • the method of manufacturing the display panel includes: preparing a substrate; and depositing on the substrate. a first gate of the first transistor; depositing the first gate insulating layer on the first gate; depositing a first active layer of the first transistor on the first gate insulating layer; A second metal layer is deposited on the first active layer and the first gate insulating layer, and the second metal layer is patterned to form a first source electrode, a first drain electrode and a second gate electrode arranged at intervals. pole.
  • the first active layer is formed based on a first photomask
  • the first source electrode, first drain electrode and second gate electrode are formed based on a second photomask.
  • a second gate insulating layer is formed on the first source, first drain and second gate; a second active layer is formed on the second gate insulating layer; A third metal layer is deposited on the two active layers, and the third metal layer is patterned to form a second drain electrode and a second source electrode arranged at intervals.
  • the second drain electrode and the second source electrode are formed based on a third mask, wherein the third mask is a half-tone mask.
  • patterning the second metal layer also includes: forming a connection line at the same time, the connection line electrically connecting the second gate electrode and the first source electrode or the first drain electrode. .
  • patterning the second metal layer further includes: depositing a planarization layer on the second source electrode and the second drain electrode; A via hole is etched at the position of at least one of the electrode and the second drain electrode.
  • planarization layer and the via hole are formed based on the fourth photomask.
  • patterning the second metal layer further includes: filling the etched via holes with the metal layer.
  • patterning the second metal layer also includes: forming a metal layer filled in the etched via hole based on a fifth photomask.
  • first source electrode and the first drain electrode of the first transistor are prepared in one process, which reduces the number of times the photomask is used, improves the preparation efficiency of the display panel, further reduces the production cost, and is simple and convenient.
  • FIG. 1 shows a schematic diagram of a display panel according to an embodiment of the present application.
  • FIGS 2 to 6 show schematic diagrams of the preparation method of the display panel according to the embodiment of the present application.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features.
  • features defined as “first” and “second” may explicitly or implicitly include one or more of the described features.
  • “plurality” means two or more than two, unless otherwise explicitly and specifically limited.
  • connection should be understood in a broad sense.
  • connection or integral connection; it can be mechanical connection, electrical connection or mutual communication; it can be direct connection, or indirect connection through an intermediary, it can be the internal connection of two elements or the interaction of two elements relation.
  • the present application mainly provides a display panel.
  • the display panel includes a plurality of pixel units arranged in an array. At least one of the pixel units is provided with a first transistor and a second transistor.
  • the first transistor includes a first gate electrode. , a first source electrode and a first drain electrode, the second transistor includes a second gate electrode, a second source electrode and a second drain electrode; wherein, the first source electrode, the first drain electrode and the second drain electrode
  • the gate is on the same layer.
  • the present application can be fabricated in one process.
  • the first source electrode, the first drain electrode and the second gate electrode thereby reduce the number of times the photomask is used, improve the preparation efficiency of the display panel, further reduce the production cost, and are simple and convenient.
  • FIG. 1 shows a schematic diagram of a display panel according to an embodiment of the present application.
  • the display panel of the present application may include a substrate 11 , a first gate insulating layer 12 , a second gate insulating layer 13 and a planarization layer (ie, PV) 14 that are stacked in sequence.
  • the substrate 11 , the first gate insulating layer 12 , the second gate insulating layer 13 and the planarization layer 14 may be stacked in sequence along a direction perpendicular to the substrate.
  • the first transistor and the second transistor of the same pixel unit are arranged on the same side of the substrate.
  • FIG. 1 may be a cross-sectional view of a pixel unit.
  • the first transistor and the second transistor may be provided in some pixel units, or the first transistor and the second transistor may be provided in each pixel unit.
  • the number of first transistors in the pixel unit may be one or more, and the number of second transistors in the pixel unit may also be one or more. It can be understood that this application does not limit the number of pixel units, first transistors, and second transistors.
  • the first transistor may be a photosensitive transistor, used to sense external light, and when receiving light, generate carriers in the channel of the photosensitive transistor, thereby generating a photosensitive signal
  • the light-sensing signal may be a current signal or a voltage signal
  • the second transistor may be a driving transistor, used to pass through the drain or source of the light-sensing transistor when the light-sensing transistor senses light.
  • the connecting line transmits the light sensing signal to the gate of the driving transistor, thereby turning on the driving transistor to drive the corresponding pixel electrode.
  • the first transistor and the second transistor may each have a bottom-gate structure. It can be understood that the types of the first transistor and the second transistor are exemplary, and this application is not limited to the types of the first transistor and the second transistor.
  • first gate electrode, the first source electrode, the first drain electrode, and the second gate electrode, the second source electrode, and the second drain electrode can all be made of a metal layer.
  • the material of the metal layer may be copper or other materials such as silver, which is not limited in this application.
  • the first transistor may be an electronic device such as a MOSFET. Both the first transistor and the second transistor may be N-type, or both may be P-type. Alternatively, the first transistor is N-type and the second transistor is P-type. Alternatively, the first transistor is P-type and the second transistor is N-type.
  • the display panel further includes a substrate, a first gate insulating layer, a first active layer, a first source electrode, a first drain electrode, and a second active layer.
  • the first gate is disposed on the substrate, the first gate insulating layer is disposed on the first gate; the first active layer is disposed on the first gate insulating layer on, and at least partially overlaps with the first gate; the first source and the first drain are disposed on the active layer; the second gate insulating layer is disposed on the third on a source electrode and a first drain electrode; the second active layer is disposed on the second gate insulating layer, and the second active layer and the second gate electrode are at least partially overlapped.
  • the substrate may be an array substrate, and the array substrate may be a glass substrate.
  • the glass substrate may be transparent, translucent or opaque to block moisture and oxygen and provide a flat upper surface.
  • the first gate is disposed on the substrate, and the first gate insulating layer is disposed on the first gate.
  • the first gate insulating layer may be made of a single layer of SiNx, a single layer of SiOx, or other materials, or may be made of a double-layer film.
  • the first active layer is disposed on the first gate insulating layer and at least partially overlaps the first gate.
  • the first gate 121 is disposed on the substrate 11 , and the first gate 121 is disposed directly below the first active layer 131 , that is, the first gate 121 and the first active layer 131 are on the substrate.
  • the first gate insulation layer 12 may cover the first gate 121 .
  • the first active layer is made of amorphous silicon material.
  • the first transistor may be a thin film transistor (Thin film transistor). Film Transistor, TFT).
  • the amorphous silicon material is also called a-Si material.
  • the amorphous silicon material can be deposited on a large area substrate, further reducing costs.
  • first source electrode and the first drain electrode are disposed on the active layer.
  • the first source electrode 132 and the first drain electrode 133 may be disposed on the first active layer 131 .
  • the second gate insulating layer is disposed on the first source electrode and the first drain electrode.
  • the second gate insulating layer can be formed into a thin film using materials such as SiNx and SiOx, and form a flat carrying surface.
  • the display panel further includes a second active layer, the second active layer is disposed on the second gate insulating layer, and the second active layer at least partially intersects with the second gate.
  • Stack settings Specifically, one end of the second gate is in contact with the first gate insulating layer, and the other end of the second gate is flush with one end of the second active layer.
  • the second active layer 141 may be disposed on the second gate insulating layer 13 , and the second active layer 141 and the second gate 134 may be at least partially overlapped.
  • the second gate electrode 134 may extend in the horizontal direction to just below the second active layer 141 , and the right boundary of the second gate electrode 134 may coincide with the right boundary of the second active layer 141 .
  • the second active layer is made of oxide semiconductor material.
  • the oxide semiconductor material may be Indium Gallium Zinc Oxide (Indium Gallium Zinc Oxide). Zinc Oxide, IGZO) materials. It can be understood that the second active layer can also be made of other materials, which is not limited by this application.
  • the display panel further includes: a second source electrode, a second drain electrode, a planarization layer, and a first metal layer.
  • the second source electrode and the second drain electrode are spaced apart on the second active layer; the planarization layer is provided on the second source electrode and the second drain electrode, so The planarization layer is provided with a via hole for exposing at least one of the second source electrode and the second drain electrode; the first metal layer is provided on the planarization layer, and the first A metal layer extends within the via hole and is connected to at least one of the second source electrode and the second drain electrode.
  • the second source electrode 142 and the second drain electrode 143 are disposed on the second active layer 141 at intervals; the planarization layer 14 is disposed on the second source electrode 142 and the second drain electrode 143 .
  • the layer 14 is provided with a via hole, which can be used to expose the second drain electrode 143 so that the second drain electrode 143 is electrically connected to the corresponding first metal layer; the first metal layer 15 is provided on the planarization layer 14, A metal layer 15 can extend within the via hole and be electrically connected to the second drain electrode 143 .
  • the first metal layer may be a transparent indium tin oxide (ie, ITO) electrode.
  • the first metal layer may be connected to a data line to deliver a data signal to the second transistor.
  • the first source electrode, the first drain electrode and the second gate electrode are arranged at intervals
  • the display panel includes a connection line
  • the connection line is arranged in the same layer as the second gate electrode
  • the second gate electrode is electrically connected to one of the first source electrode or the first drain electrode.
  • the connection line is located between the first source or the first drain and the second gate.
  • metal wiring can be used to connect the light generated by the first photosensitive transistor.
  • the light sensing signal is transmitted from the source or drain of the first transistor to the gate of the second transistor.
  • the second gate insulating layer may cover the first source electrode, the first drain electrode, the connection line and the second gate electrode at the same time.
  • connection line is arranged in contact with the first active layer, and the other end of the connection line is in contact with one end of the second gate.
  • the first drain 133 can be electrically connected to the second gate 134 through a connection line 135 , that is, the first drain of the first transistor.
  • the first drain electrode of the first transistor may be shared with the second gate electrode of the second transistor, or the first drain electrode of the first transistor may be multiplexed as the second gate electrode of the second transistor.
  • the connection line may cover the first active layer, that is, the connection line may be disposed close to the first active layer. It can be understood that this application does not limit how the first drain electrode and the second gate electrode are electrically connected.
  • FIGS 2 to 6 show schematic diagrams of the preparation method of the display panel according to the embodiment of the present application.
  • the present application also provides a method for preparing a display panel, and the method for preparing a display panel is applied to the display panel.
  • the preparation method of the display panel includes:
  • Step S11 Prepare substrate
  • Step S12 Deposit the first gate of the first transistor on the substrate
  • Step S13 deposit the first gate insulating layer on the first gate
  • Step S14 Deposit the first active layer of the first transistor on the first gate insulating layer
  • Step S15 Deposit a second metal layer on the first active layer and the first gate insulating layer, and pattern the second metal layer to form first source electrodes and first drain electrodes arranged at intervals. pole and the second gate.
  • step S1 can be prepared using a 2W2D process.
  • the 2W2D process includes: 1st Etch WET (the first step of wet etching), 2nd Etch DRY (the second step of dry etching), 3rd Etch WET (the third step of wet etching), and 4th Etch DRY (the fourth step of dry etching).
  • a first photomask ie, mask layer or Mask
  • a second mask is required, and the second mask is used to define the pattern of the first source electrode or the first drain electrode of the first transistor.
  • the substrate 11 may first be prepared. Next, the first gate electrode 121 of the first transistor is deposited on the substrate, the first gate insulating layer 12 is then deposited on the first gate electrode, and then the first gate insulating layer 12 is deposited on the first gate insulating layer. For the first active layer 131 of a transistor, a second metal layer is finally deposited on the first active layer and the first gate insulating layer, and the second metal layer is patterned to form intervals. The first source electrode 132, the first drain electrode 133 and the second gate electrode 134.
  • patterning the second metal layer also includes:
  • Step S151 Form a connection line at the same time, and the connection line electrically connects the second gate electrode and the first source electrode or the first drain electrode. That is, while forming between the first source electrode or the first drain electrode and the second gate electrode, the second metal layer is also patterned to form the connection line 135 .
  • preparation method of the display panel may also include:
  • Step S21 Form a second gate insulating layer on the first source, first drain and second gate;
  • Step S22 Form a second active layer on the second gate insulating layer
  • Step S23 Deposit a third metal layer on the second active layer, and pattern the third metal layer to form a second drain electrode and a second source electrode arranged at intervals.
  • a half-tone mask ie, HTM
  • HTM half-tone mask
  • the second gate insulating layer 13 can be deposited on the first gate and the first drain, and then an IGZO layer 31 can be deposited on the second gate insulating layer, And deposit a third metal layer 32 on the IGZO layer.
  • the IGZO layer 31 is etched to obtain the second active layer 141 of the second transistor, and then the third metal layer 32 is etched to deposit the second source electrode on the second active layer. 142 and the second drain 143 .
  • preparation method of the display panel may also include:
  • Step S31 Deposit a planarization layer on the second source electrode and the second drain electrode;
  • Step S32 Etch a via hole in the planarization layer at a position corresponding to at least one of the second source electrode and the second drain electrode.
  • a planarization layer 14 may be deposited on the second source electrode and the second drain electrode, and then the planarization layer corresponds to at least one of the second source electrode and the second drain electrode.
  • a via hole 51 is etched at one of the positions. Among them, step S31 and step S32 need to be prepared using a fourth photomask.
  • preparation method of the display panel may also include:
  • Step S41 Fill the etched via holes with a metal layer.
  • the metal layer 15 may be filled in the etched via hole 51 .
  • a fifth photomask needs to be used to define the pattern of the ITO electrode.
  • FIG. 2 to FIG. 6 are exemplary. Based on the inventive concept of the present application, corresponding adjustments can be made in the process steps in practical applications. For a more detailed description of the preparation method of the display panel, reference may be made to the above specific description of the display panel, which will not be described again.
  • the actual preparation process of this application can be prepared in one process, thereby reducing the number of times of use of the photomask to five, improving the preparation efficiency of the display panel, and further reducing the production cost. easy and convenient.
  • the first source and first drain of the first transistor in at least one pixel unit and the corresponding second gate of the second transistor in the pixel unit are arranged on the same layer.
  • the first source electrode, the first drain electrode and the second gate electrode can be prepared in one process, thereby reducing the number of times the photomask is used, improving the preparation efficiency of the display panel, further reducing the production cost, being simple, convenient and applicable In many fields such as LCD, OLED, u-LED and mini-LED.

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Abstract

一种显示面板及显示面板的制备方法，其中，显示面板包括阵列设置的多个像素单元，至少一个像素单元中设置有第一晶体管以及第二晶体管，第一晶体管包括第一栅极（121）、第一源极（132）以及第一漏极（133），第二晶体管包括第二栅极（134）、第二源极（142）以及第二漏极（143）；其中，第一源极（132）、第一漏极（133）和第二栅极（134）位于同一层。

Description

显示面板及显示面板的制备方法 技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板及显示面板的制备方法。
 背景技术
相关技术中，光传感电路的制备工艺复杂，导致生产周期长，成本高。例如，相关技术在制备光传感电路时，先制备光感晶体管，然后制备驱动晶体管。光感晶体管的制备与驱动晶体管的制备各自独立进行，需要采用的光罩（mask）工艺较为复杂。
 技术问题
本申请主要针对光传感电路的光罩工艺复杂的技术问题。
 技术解决方案
有鉴于此，本申请提出了一种显示面板及显示面板的制备方法，能够在一道工序中制备所述第一源极、第一漏极和所述第二栅极，从而减少光罩使用的次数，提高显示面板的制备效率，进一步降低生产成本，简单方便。
根据本申请的一方面，提供了一种显示面板，所述显示面板包括阵列设置的多个像素单元，至少一个所述像素单元中设置有第一晶体管以及第二晶体管，所述第一晶体管包括第一栅极、第一源极以及第一漏极，所述第二晶体管包括第二栅极、第二源极以及第二漏极；其中，所述第一源极、第一漏极和所述第二栅极位于同一层。
进一步地，所述显示面板还包括：基板，所述第一栅极设置于所述基板上；第一栅极绝缘层，设置于所述第一栅极上；第一有源层，设置于所述第一栅极绝缘层上，并与所述第一栅极至少部分交叠；第一源极和第一漏极设置于所述第一有源层上；第二栅极绝缘层，设置于所述第一源极和第一漏极上；以及第二有源层，设置于所述第二栅极绝缘层上，且所述第二有源层与所述第二栅极至少部分交叠设置。
进一步地，所述第二栅极的一端与所述第一栅极绝缘层相贴合，所述第二栅极的另一端与所述第二有源层的一端平齐。
进一步地，所述显示面板还包括：第二源极和第二漏极，所述第二源极和所述第二漏极间隔设置在所述第二有源层上；平坦化层，设置在所述第二源极和所述第二漏极上，所述平坦化层上设有用于露出所述第二源极和所述第二漏极中的至少一者的过孔；第一金属层，设置于所述平坦化层上，所述第一金属层延伸设置于所述过孔内并与所述第二源极和所述第二漏极中的至少一者连接。
进一步地，所述第一源极、所述第一漏极和所述第二栅极间隔设置，所述显示面板包括连接线，所述连接线与所述第二栅极同层设置，并将所述第二栅极和所述第一源极或所述第一漏极中的一者电连接。
进一步地，所述连接线的一端贴合所述第一有源层设置，所述连接线的另一端与所述第二栅极的一端相接触。
进一步地，所述第一有源层采用非晶硅材料制成，所述第二有源层采用氧化物半导体材料制成。
进一步地，所述第一晶体管为光感晶体管，用于感应外接光线，并在感应到光线时产生光感信号。
进一步地，所述第二晶体管为驱动晶体管，用于在所述光感晶体管感应到光线时，通过所述光感晶体管的漏极或源极以及连接线将所述光感信号传输至该驱动晶体管的栅极。
进一步地，所述第一栅极、第一源极、第一漏极以及所述第二栅极、第二源极、第二漏极均采用金属层制成。
进一步地，所述第一晶体管为N型或P型，所述第二晶体管为N型或P型。
根据本申请的另一方面，提供了一种显示面板的制备方法，所述显示面板的制备方法应用于所述显示面板，所述显示面板的制备方法包括：制备基板；在所述基板上沉积第一晶体管的第一栅极；在所述第一栅极上沉积所述第一栅极绝缘层；在所述第一栅极绝缘层上沉积第一晶体管的第一有源层；在所述第一有源层和所述第一栅极绝缘层上沉积第二金属层，并对所述第二金属层进行图案化形成间隔设置的第一源极、第一漏极以及第二栅极。
进一步地，所述第一有源层基于第一道光罩形成，所述第一源极、第一漏极以及第二栅极基于第二道光罩形成。
进一步地，在所述第一源极、第一漏极以及第二栅极上形成第二栅极绝缘层；在所述第二栅极绝缘层上形成第二有源层；在所述第二有源层上沉积第三金属层，并对所述第三金属层进行图案化形成间隔设置的第二漏极和第二源极。
进一步地，所述第二漏极和第二源极基于第三道光罩形成，其中：所述第三道光罩为半色调光罩。
进一步地，在对所述第二金属层进行图案化时还包括：同时形成连接线，所述连接线将所述第二栅极和所述第一源极或所述第一漏极电连接。
进一步地，在对所述第二金属层进行图案化时还包括：在所述第二源极以及所述第二漏极上沉积平坦化层；在所述平坦化层对应所述第二源极和所述第二漏极中的至少一者的位置刻蚀过孔。
进一步地，所述平坦化层以及过孔基于第四道光罩形成。
进一步地，在对所述第二金属层进行图案化时还包括：在刻蚀的过孔中填充金属层。
进一步地，在对所述第二金属层进行图案化时还包括：在刻蚀的过孔中填充的金属层基于第五道光罩形成。
 有益效果
通过将至少一个像素单元中的第一晶体管的第一源极、第一漏极与对应的该像素单元中的第二晶体管的第二栅极设置为同一层，根据本申请的各方面能够在一道工序中制备所述第一源极、第一漏极和所述第二栅极，减少光罩使用的次数，提高显示面板的制备效率，进一步降低生产成本，简单方便。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1示出本申请实施例的显示面板的示意图。
图2-图6示出本申请实施例的显示面板的制备方法的示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接连接，也可以通过中间媒介间接连接，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。在一些实例中，对于本领域技术人员熟知的方法、手段、元件和电路未作详细描述，以便于凸显本申请的主旨。
本申请主要提供了一种显示面板，所述显示面板包括阵列设置的多个像素单元，至少一个所述像素单元中设置有第一晶体管以及第二晶体管，所述第一晶体管包括第一栅极、第一源极以及第一漏极，所述第二晶体管包括第二栅极、第二源极以及第二漏极；其中，所述第一源极、第一漏极和所述第二栅极位于同一层。
通过将至少一个像素单元中的第一晶体管的第一源极、第一漏极与对应的该像素单元中的第二晶体管的第二栅极设置为同一层，本申请能够在一道工序中制备所述第一源极、第一漏极和所述第二栅极，从而减少光罩使用的次数，提高显示面板的制备效率，进一步降低生产成本，简单方便。
图1示出本申请实施例的显示面板的示意图。
如图1所示，本申请的显示面板可包括依次层叠设置的基板11、第一栅极绝缘层12、第二栅极绝缘层13以及平坦化层（即，PV）14。基板11、第一栅极绝缘层12、第二栅极绝缘层13以及平坦化层14可沿与所述基板垂直的方向依次层叠设置。同一个像素单元的第一晶体管以及第二晶体管设置在所述基板的同一侧。
需要说明的是，图1中示出的可以是一个像素单元的剖面图。在本申请中，可以在部分像素单元中设置所述第一晶体管以及第二晶体管，也可以在各个像素单元中均设置所述第一晶体管以及第二晶体管。对于同一个像素单元而言，该像素单元中的第一晶体管的数量可以是一个或多个，该像素单元中的第二晶体管的数量也可以是一个或多个。可以理解，本申请对于像素单元、第一晶体管以及第二晶体管的数量均不限定。
其中，在一个像素单元中，所述第一晶体管可以是光感晶体管，用于感应外界光线，并在接收到光线时在该光感晶体管的沟道内产生载流子，进而产生光感信号，该光感信号可以是电流信号，也可以是电压信号；所述第二晶体管可以是驱动晶体管，用于在所述光感晶体管感应到光线时，通过所述光感晶体管的漏极或源极以及连接线将所述光感信号传输至该驱动晶体管的栅极，进而使该驱动晶体管开启，以驱动对应的像素电极。所述第一晶体管以及所述第二晶体管可以均为底栅型结构。可以理解的是，所述第一晶体管以及所述第二晶体管的类型是示例性的，本申请对于所述第一晶体管以及所述第二晶体管的类型并不限定。
进一步地，所述第一栅极、第一源极、第一漏极以及所述第二栅极、第二源极、第二漏极均可以采用金属层制成。所述金属层的材料可以是铜，也可以是银等其他材料，本申请对此并不限定。
示例性的，在本申请中，所述第一晶体管可以是例如MOSFET的电子器件。所述第一晶体管以及所述第二晶体管均可以是N型，也可以均为P型。或者，所述第一晶体管为N型，所述第二晶体管P型。又或者，所述第一晶体管为P型，所述第二晶体管N型。
进一步地，所述显示面板还包括基板、第一栅极绝缘层、第一有源层、第一源极、第一漏极以及第二有源层。其中：所述第一栅极设置于所述基板上，所述第一栅极绝缘层设置于所述第一栅极上；所述第一有源层设置于所述第一栅极绝缘层上，并与所述第一栅极至少部分交叠；所述第一源极和所述第一漏极设置于所述有源层上；所述第二栅极绝缘层设置于所述第一源极和第一漏极上；所述第二有源层设置于所述第二栅极绝缘层上，且所述第二有源层与所述第二栅极至少部分交叠设置。
进一步地，所述基板可以是阵列基板，所述阵列基板可以是玻璃基板。所述玻璃基板可以是透明的、半透明的或不透明的，用于阻挡湿气和氧气，并提供平坦的上表面。
进一步地，所述第一栅极设置于所述基板上，所述第一栅极绝缘层设置于所述第一栅极上。所述第一栅极绝缘层可以采用单层的SiNx或者单层SiOx等材料，也可以采用双层膜。
进一步地，所述第一有源层设置于所述第一栅极绝缘层上，并与所述第一栅极至少部分交叠。例如，在图1中，第一栅极121设置在基板11上，第一栅极121设置在第一有源层131的正下方，即第一栅极121与第一有源层131在基板11上的正投影对应设置。第一栅极绝缘层12可覆盖在第一栅极121上。所述第一有源层采用非晶硅材料制成。在一个示例中，所述第一晶体管可以是薄膜晶体管（Thin Film Transistor，TFT）。所述非晶硅材料也称a-Si材料，采用非晶硅材料能够沉积在大面积的衬底上，进一步降低成本。
进一步地，第一源极和第一漏极设置于所述有源层上。例如，在图1中，以所述第一晶体管为N型为例，所述第一源极132以及所述第一漏极133可设置在第一有源层131上。
进一步地，所述第二栅极绝缘层，设置于所述第一源极和第一漏极上。所述第二栅极绝缘层可以采用SiNx以及SiOx等材料形成薄膜，并形成平坦的承载面。
进一步地，所述显示面板还包括第二有源层，第二有源层设置于所述第二栅极绝缘层上，且所述第二有源层与所述第二栅极至少部分交叠设置。具体的，所述第二栅极的一端与所述第一栅极绝缘层相贴合，所述第二栅极的另一端与所述第二有源层的一端平齐。例如，在图1中，第二有源层141可设置在第二栅极绝缘层13上，且第二有源层141与第二栅极134至少部分交叠设置。第二栅极134可沿水平方向延伸至第二有源层141的正下方，第二栅极134的右边界可与第二有源层141的右边界重合。
其中，所述第二有源层采用氧化物半导体材料制成。所述氧化物半导体材料可以为铟镓锌氧化物（Indium Gallium Zinc Oxide，IGZO）材料。可以理解，所述第二有源层也可以采用其他材料，本申请并不限定。
进一步地，所述显示面板还包括：第二源极、第二漏极、平坦化层、第一金属层。其中：所述第二源极和所述第二漏极间隔设置在所述第二有源层上；所述平坦化层设置在所述第二源极和所述第二漏极上，所述平坦化层上设有用于露出所述第二源极和所述第二漏极中的至少一者的过孔；所述第一金属层设置于所述平坦化层上，所述第一金属层延伸设置于所述过孔内并与所述第二源极和所述第二漏极中的至少一者连接。
例如，在图1中，第二源极142以及第二漏极143间隔设置在第二有源层141上；平坦化层14设置在第二源极142以及第二漏极143上，平坦化层14设置有过孔，该过孔可以用于露出第二漏极143，以便第二漏极143与对应的第一金属层电连接；第一金属层15设置在平坦化层14上，第一金属层15可延伸设置在过孔内，并与第二漏极143电连接。
其中，所述第一金属层可以为透明的氧化铟锡（即，ITO）电极。所述第一金属层可以连接到数据线，以便为所述第二晶体管递送数据信号。
进一步地，所述第一源极、所述第一漏极和所述第二栅极间隔设置，所述显示面板包括连接线，所述连接线与所述第二栅极同层设置，并将所述第二栅极和所述第一源极或所述第一漏极中的一者电连接。所述连接线位于所述第一源极或所述第一漏极与所述第二栅极之间，在实际应用中可以采用金属走线，用于将所述第一光感晶体管产生的光感信号从所述第一晶体管的源极或漏极传输至所述第二晶体管的栅极。所述第二栅极绝缘层可同时覆盖在所述第一源极、第一漏极、连接线以及第二栅极上。
其中，所述连接线的一端贴合所述第一有源层设置，所述连接线的另一端与所述第二栅极的一端相接触。参见图1，以所述第一晶体管为N型为例，所述第一漏极133可通过连接线135与所述第二栅极134电连接，即，所述第一晶体管的第一漏极可与所述第二晶体管的第二栅极共用，或者，所述第一晶体管的第一漏极可复用为所述第二晶体管的第二栅极。示例性的，所述连接线可覆盖在所述第一有源层上，即，所述连接线可紧贴所述第一有源层设置。可以理解，本申请对于所述第一漏极与所述第二栅极如何电连接并不限定。
图2-图6示出本申请实施例的显示面板的制备方法的示意图。
如图2-图6所示，本申请还提供了一种显示面板的制备方法，所述显示面板的制备方法应用于所述显示面板。所述显示面板的制备方法包括：
步骤S11：制备基板；
步骤S12：在所述基板上沉积第一晶体管的第一栅极；
步骤S13：在所述第一栅极上沉积所述第一栅极绝缘层；
步骤S14：在所述第一栅极绝缘层上沉积第一晶体管的第一有源层；
步骤S15：在所述第一有源层和所述第一栅极绝缘层上沉积第二金属层，并对所述第二金属层进行图案化形成间隔设置的第一源极、第一漏极以及第二栅极。
其中，步骤S1可以采用2W2D工艺进行制备。2W2D工艺包括：1st Etch WET(第一步湿刻)、2nd Etch DRY(第二步干刻)、3rd Etch WET(第三步湿刻)、4th Etch DRY(第四步干刻)。在制备第一有源层时，需要采用第一道光罩（即，掩膜层或Mask），利用第一道光罩定义第一有源层的图案；在制备第一晶体管的第一源极或第一漏极时，需要采用第二道光罩，利用第二道光罩定义第一晶体管的第一源极或第一漏极的图案。
参考图2，首先可以制备基板11。接着在所述基板上沉积第一晶体管的第一栅极121，然后在所述第一栅极上沉积所述第一栅极绝缘层12，接着在所述第一栅极绝缘层上沉积第一晶体管的第一有源层131，最后在所述第一有源层和所述第一栅极绝缘层上沉积第二金属层，并对所述第二金属层进行图案化形成间隔设置的第一源极132、第一漏极133以及第二栅极134。
其中，在对所述第二金属层进行图案化时还包括：
步骤S151：同时形成连接线，所述连接线将所述第二栅极和所述第一源极或所述第一漏极电连接。即，在所述第一源极或所述第一漏极与所述第二栅极之间形成的同时，也同时对所述第二金属层进行图案化，形成连接线135。
进一步地，所述显示面板的制备方法还可包括：
步骤S21：在所述第一源极、第一漏极以及第二栅极上形成第二栅极绝缘层；
步骤S22：在所述第二栅极绝缘层上形成第二有源层；
步骤S23：在所述第二有源层上沉积第三金属层，并对所述第三金属层进行图案化形成间隔设置的第二漏极和第二源极。
其中，本申请可以采用半色调光罩（即，HTM）对第二有源层以及第三金属层进行蚀刻，得到第二晶体管的第二有源层、第二源极以及第二漏极。其中，所述半色调光罩为第三道光罩。
参考图3和图4，可以在所述第一栅极以及所述第一漏极上沉积所述第二栅极绝缘层13，接着在所述第二栅极绝缘层上沉积IGZO层31，并在IGZO层上沉积第三金属层32。对IGZO层31进行刻蚀，可得到第二晶体管的第二有源层141，然后对第三金属层32进行刻蚀，可得到在所述第二有源层上沉积所述第二源极142以及第二漏极143。
进一步地，所述显示面板的制备方法还可包括：
步骤S31:在所述第二源极以及所述第二漏极上沉积平坦化层；
步骤S32：在所述平坦化层对应所述第二源极和所述第二漏极中的至少一者的位置刻蚀过孔。
参考图5，可以在所述第二源极以及所述第二漏极上沉积平坦化层14，然后在所述平坦化层对应所述第二源极和所述第二漏极中的至少一者的位置刻蚀过孔51。其中，步骤S31以及步骤S32需要采用第四道光罩进行制备。
进一步地，所述显示面板的制备方法还可包括：
步骤S41：在刻蚀的过孔中填充金属层。
参见图6，可以在刻蚀的过孔51中填充金属层15。其中，在步骤S41中，需要采用第五道光罩，以定义ITO电极的图案。
需要说明的是，图2至图6是示例性的。基于本申请的发明构思，在实际应用中可以在工艺步骤方面做出相应调整。对于所述显示面板的制备方法更加详细的说明，可参照上述有关所述显示面板的具体描述，不再赘述。
因此，由于将至少一个像素单元中的第一晶体管的第一源极、第一漏极与对应的该像素单元中的第二晶体管的第二栅极设置为同一层，本申请在实际制备过程中能够在一道工序中制备所述第一源极、第一漏极和所述第二栅极，从而将光罩的使用次数减少到五道，提高显示面板的制备效率，进一步降低生产成本，简单方便。
综上所述，本申请实施例通过将至少一个像素单元中的第一晶体管的第一源极、第一漏极与对应的该像素单元中的第二晶体管的第二栅极设置为同一层，能够在一道工序中制备所述第一源极、第一漏极和所述第二栅极，从而减少光罩使用的次数，提高显示面板的制备效率，进一步降低生产成本，简单方便，适用于LCD、OLED、u-LED以及mini-LED等多个领域。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的显示面板及显示面板的制备方法进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种显示面板，其中，所述显示面板包括阵列设置的多个像素单元，至少一个所述像素单元中设置有第一晶体管以及第二晶体管，所述第一晶体管包括第一栅极、第一源极以及第一漏极，所述第二晶体管包括第二栅极、第二源极以及第二漏极；
    其中，所述第一源极、第一漏极和所述第二栅极位于同一层。
  2. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    基板，所述第一栅极设置于所述基板上；
    第一栅极绝缘层，设置于所述第一栅极上；
    第一有源层，设置于所述第一栅极绝缘层上，并与所述第一栅极至少部分交叠；
    第一源极和第一漏极设置于所述第一有源层上；
    第二栅极绝缘层，设置于所述第一源极和第一漏极上；以及
    第二有源层，设置于所述第二栅极绝缘层上，且所述第二有源层与所述第二栅极至少部分交叠设置。
  3. 根据权利要求2所述的显示面板，其中，所述第二栅极的一端与所述第一栅极绝缘层相贴合，所述第二栅极的另一端与所述第二有源层的一端平齐。
  4. 根据权利要求3所述的显示面板，其中，所述显示面板还包括：
    第二源极和第二漏极，所述第二源极和所述第二漏极间隔设置在所述第二有源层上；
    平坦化层，设置在所述第二源极和所述第二漏极上，所述平坦化层上设有用于露出所述第二源极和所述第二漏极中的至少一者的过孔；
    第一金属层，设置于所述平坦化层上，所述第一金属层延伸设置于所述过孔内并与所述第二源极和所述第二漏极中的至少一者连接。
  5. 根据权利要求4所述的显示面板，其中，所述第一源极、所述第一漏极和所述第二栅极间隔设置，所述显示面板包括连接线，所述连接线与所述第二栅极同层设置，并将所述第二栅极和所述第一源极或所述第一漏极中的一者电连接。
  6. 根据权利要求5所述的显示面板，其中，所述连接线的一端贴合所述第一有源层设置，所述连接线的另一端与所述第二栅极的一端相接触。
  7. 根据权利要求2所述的显示面板，其中，所述第一有源层采用非晶硅材料制成，所述第二有源层采用氧化物半导体材料制成。
  8. 根据权利要求5所述的显示面板，其中，所述第一晶体管为光感晶体管，用于感应外接光线，并在感应到光线时产生光感信号。
  9. 根据权利要求8所述的显示面板，其中，所述第二晶体管为驱动晶体管，用于在所述光感晶体管感应到光线时，通过所述光感晶体管的漏极或源极以及连接线将所述光感信号传输至该驱动晶体管的栅极。
  10. 根据权利要求1所述的显示面板，其中，所述第一栅极、第一源极、第一漏极以及所述第二栅极、第二源极、第二漏极均采用金属层制成。
  11. 根据权利要求1所述的显示面板，其中，所述第一晶体管为N型或P型，所述第二晶体管为N型或P型。
  12. 一种显示面板的制备方法，其中，所述显示面板的制备方法包括：
    制备基板；
    在所述基板上沉积第一晶体管的第一栅极；
    在所述第一栅极上沉积所述第一栅极绝缘层；
    在所述第一栅极绝缘层上沉积第一晶体管的第一有源层；
    在所述第一有源层和所述第一栅极绝缘层上沉积第二金属层，并对所述第二金属层进行图案化形成间隔设置的第一源极、第一漏极以及第二栅极。
  13. 根据权利要求12所述的制备方法，其中，所述第一有源层基于第一道光罩形成，所述第一源极、第一漏极以及第二栅极基于第二道光罩形成。
  14. 根据权利要求12所述的制备方法，其中，所述制备方法还包括：
    在所述第一源极、第一漏极以及第二栅极上形成第二栅极绝缘层；
    在所述第二栅极绝缘层上形成第二有源层；
    在所述第二有源层上沉积第三金属层，并对所述第三金属层进行图案化形成间隔设置的第二漏极和第二源极。
  15. 根据权利要求14所述的制备方法，其中，所述第二漏极和第二源极基于第三道光罩形成，其中：所述第三道光罩为半色调光罩。
  16. 根据权利要求12所述的制备方法，其中，在对所述第二金属层进行图案化时还包括：同时形成连接线，所述连接线将所述第二栅极和所述第一源极或所述第一漏极电连接。
  17. 根据权利要求12所述的制备方法，其中，在对所述第二金属层进行图案化时还包括：
    在所述第二源极以及所述第二漏极上沉积平坦化层；
    在所述平坦化层对应所述第二源极和所述第二漏极中的至少一者的位置刻蚀过孔。
  18. 根据权利要求17所述的制备方法，其中，所述平坦化层以及过孔基于第四道光罩形成。
  19. 根据权利要求12所述的制备方法，其中，在对所述第二金属层进行图案化时还包括：在刻蚀的过孔中填充金属层。
  20. 根据权利要求19所述的制备方法，其中，在对所述第二金属层进行图案化时还包括：在刻蚀的过孔中填充的金属层基于第五道光罩形成。
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