WO2023168820A1 - 偏置信号生成电路与时钟输入电路 - Google Patents

偏置信号生成电路与时钟输入电路 Download PDF

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Publication number
WO2023168820A1
WO2023168820A1 PCT/CN2022/091771 CN2022091771W WO2023168820A1 WO 2023168820 A1 WO2023168820 A1 WO 2023168820A1 CN 2022091771 W CN2022091771 W CN 2022091771W WO 2023168820 A1 WO2023168820 A1 WO 2023168820A1
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Prior art keywords
transistor
node
bias signal
switching element
bias
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PCT/CN2022/091771
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English (en)
French (fr)
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刘忠来
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长鑫存储技术有限公司
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Priority to US17/869,796 priority Critical patent/US11791804B2/en
Publication of WO2023168820A1 publication Critical patent/WO2023168820A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals

Definitions

  • the present disclosure relates to the field of electronic circuit technology, and specifically to a bias signal generation circuit capable of flexibly adjusting a bias voltage, and a clock input circuit using the bias signal generation circuit to control power.
  • clock circuits are used to control signal timing and have a wide range of applications.
  • the clock circuit usually includes a clock generation circuit, a clock calibration circuit and other related auxiliary circuits to maintain the accuracy of the input clock.
  • the clock circuit usually remains stable and has fixed power consumption.
  • optimizing power consumption of integrated circuits in order to maintain the stability of the clock, optimizing power from the perspective of the clock circuit is usually not considered.
  • the purpose of this disclosure is to provide a bias signal generation circuit that can flexibly adjust the bias voltage, and a clock input circuit that uses the bias signal generation circuit to control power, so as to reduce the power of the clock circuit at least to a certain extent.
  • a bias signal generating circuit including: a first branch, a first end connected to a power supply voltage through a first node, a second end connected to a current stabilizing module through a second node, the third branch One branch is used to generate a bias signal and output the bias signal through the second node, and the current stabilization module is used to provide a constant current for the second node; the second branch is connected to both ends respectively.
  • the first node and the second node include a first resistor unit and a first switching element connected in series.
  • the first switching element is controlled to be turned on or off by a low-speed mode control signal; wherein the low-speed mode control signal is The first switching element is controlled to be turned on to control the second branch to be connected in parallel with the first branch to increase the bias voltage of the bias signal of the second node.
  • the first branch includes a first transistor and a second transistor, both of the first transistor and the second transistor are transistors of the same type, and the first transistor has a One end is connected to the first node, the second end of the first transistor is connected to the first end of the second transistor, and the control end of the first transistor is connected to the second end of the second transistor.
  • the second node and the control end of the second transistor are connected to a bias control voltage.
  • the first resistance unit includes a third transistor and a fourth transistor
  • the third transistor and the fourth transistor are transistors of the same type
  • the third transistor is One end is connected to the first node
  • the second end of the third transistor is connected to the first end of the fourth transistor
  • the control end of the third transistor is connected to the second node
  • the fourth transistor The second end of the transistor is connected to the second node through the first switching element, and the control end of the fourth transistor is connected to the bias control voltage.
  • the first transistor, the second transistor, the third transistor and the fourth transistor are all P-type transistors.
  • the conductive channel width-to-length ratio of the third transistor and the first transistor are the same, and the conductive channel width-to-length ratio of the second transistor and the fourth transistor are the same.
  • the current stabilization module includes a fifth transistor and a second resistance unit, the first end of the fifth transistor is connected to the second node, and the second end is connected to the third node, Two ends of the second resistor unit are respectively connected to the third node and ground.
  • the gate of the fifth transistor is connected to the output terminal of the amplifier, and the first input terminal of the amplifier is connected to the bias control voltage.
  • the third node is connected to the second input terminal of the amplifier.
  • a third branch is further included, with two ends respectively connected to the first node and the third node, for reducing the current of the second node.
  • the third branch includes a third resistance unit and a sixth transistor, a first end of the sixth transistor is connected to the third resistance unit, and a second end is connected to the The gate of the third node is connected to the bias control voltage.
  • the first node is connected to the power supply voltage through a second switching element, and the second switching element is controlled by a bias voltage enable control signal.
  • the bias signal is used to control a third switching element
  • the third switching element is a P-type transistor
  • the first end of the third switching element is electrically connected to the power supply voltage
  • the second terminal of the third switching element is connected to the load circuit
  • the control terminal of the third switching element is connected to the second node.
  • the load circuit is a clock calibration circuit.
  • a clock input circuit including: a clock calibration circuit, a first input terminal connected to an external input clock, and a second input terminal connected to a reference clock for calibrating the external input clock and outputting a differential clock signal,
  • the clock calibration circuit is connected to the power supply voltage through a third switching element; the bias signal generating circuit as described in any one of the above is connected to the control end of the third switching element for generating a bias signal, and the bias signal is generated through the bias signal.
  • the setting signal controls the opening degree of the third switching element.
  • the third switching element is a P-type transistor
  • the bias signal generating circuit increases the voltage of the bias signal in response to the low-speed mode control signal to reduce the word clock Calibrate the power of the circuit.
  • Embodiments of the present disclosure increase the output bias voltage by controlling the second branch to be connected in parallel with the first branch, and can flexibly adjust the bias voltage, and then flexibly control the power of the load circuit controlled by the bias voltage.
  • this bias signal generation circuit in a clock calibration circuit to flexibly adjust the bias signal, the power of the clock calibration circuit can be reduced in a low-speed mode with lower power requirements, thereby reducing the overall power of the integrated circuit.
  • FIG. 1 is a schematic structural diagram of a bias signal generating circuit in an exemplary embodiment of the present disclosure.
  • Figure 2 is a schematic diagram of a first branch and a second branch in an embodiment of the present disclosure.
  • Figure 3 is a circuit schematic diagram of a current stabilization module in an embodiment of the present disclosure.
  • FIG. 4 is a circuit schematic diagram of a bias signal generating circuit in an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of a bias signal generating circuit controlling a load circuit in an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a clock input circuit according to an embodiment of the present disclosure.
  • Figure 7 is a block diagram of a low-speed mode control signal generation module in one embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concepts of the example embodiments.
  • the described features, structures or characteristics may be combined in any suitable manner in one or more embodiments.
  • numerous specific details are provided to provide a thorough understanding of embodiments of the disclosure.
  • those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details described, or other methods, components, devices, steps, etc. may be adopted.
  • well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the disclosure.
  • FIG. 1 is a schematic structural diagram of a bias signal generating circuit in an exemplary embodiment of the present disclosure.
  • the bias signal generation circuit 100 may include:
  • the first branch 11 has a first end connected to the power supply voltage Vcc through the first node N1, and a second end connected to the current stabilizing module 13 through the second node N2.
  • the first branch 11 is used to generate the bias signal Sbias and passes it through the second node.
  • N2 outputs the bias signal Sbias, and the current stabilization module 13 is used to provide a constant current I for the second node N2;
  • the second branch 12 has both ends connected to the first node N1 and the second node N2 respectively, and includes a series-connected first resistor unit 121 and a first switching element K1.
  • the first switching element K1 is controlled by the low-speed mode control signal Slsp to turn on or closure;
  • the low-speed mode control signal Slsp is used to control the first switching element K1 to turn on to control the parallel connection of the second branch 12 and the first branch 11 to increase the bias voltage Vbias of the bias signal Sbias of the second node N2.
  • Vbias Vcc-I*R0 (1)
  • the bias voltage Vbias at this time is formula (2):
  • the rising value of the bias voltage Vbias can be determined by controlling the resistance of the first resistor unit 121 .
  • multiple parallel second branches can be provided. Each second branch is provided with a switching element to control entry into the parallel state. Each second branch has a different resistance value, so that it can be controlled by Branches with different resistance values are connected in parallel between the first node N1 and the second node N2 to control the bias voltage Vbias to rise to different voltage values.
  • Figure 2 is a schematic diagram of a first branch and a second branch in an embodiment of the present disclosure.
  • the first branch 11 may include a first transistor M1 and a second transistor M2.
  • the first transistor M1 and the second transistor M2 are both transistors of the same type.
  • the first terminal of the first transistor M1 The first node N1 is connected, the second terminal of the first transistor M2 is connected to the first terminal of the second transistor M2, the control terminal of the first transistor M1 and the second terminal of the second transistor M2 are both connected to the second node N2, the second The control terminal of the transistor M2 is connected to the bias control voltage VIBCOM.
  • the first resistor unit 121 in the second branch 12 may include a third transistor M3 and a fourth transistor M4.
  • the third transistor M3 and the fourth transistor M4 are both transistors of the same type.
  • the first end of the third transistor M3 is connected to the first Node N1
  • the second terminal of the third transistor M3 is connected to the first terminal of the fourth transistor M4
  • the control terminal of the third transistor M3 is connected to the second node N2
  • the second terminal of the fourth transistor M4 is connected through the first switching element K1
  • the second node N2 and the control terminal of the fourth transistor M4 are connected to the bias control voltage VIBCOM.
  • the first transistor M1 , the second transistor M2 , the third transistor M3 , and the fourth transistor M4 are all P-type transistors, more specifically, they are all channel enhancement type P-type transistors.
  • the source of the first transistor M1 is connected to the first node N1, and the drain of the first transistor M1
  • the gate of the first transistor M1 and the drain of the second transistor M2 are both connected to the second node N2, and the gate of the second transistor M2 is connected to the bias control voltage VIBCOM; the third transistor The source of M3 is connected to the first node N1.
  • the drain of the third transistor M3 is connected to the source of the fourth transistor M4.
  • the gate of the third transistor M3 and the drain of the fourth transistor M4 are both connected to the second node N2.
  • the gate of the four transistor M4 is connected to the bias control voltage VIBCOM.
  • the first transistor M1 is controlled to be turned on by the bias voltage Vbias of the second node N2 and has a first resistance.
  • the gate of the second transistor M2 is controlled by the bias control voltage VIBCOM and has a second resistance.
  • the sum of the first resistance and the second resistance constitutes the resistance R0 of the first branch.
  • the third transistor M3 and the first transistor M1 have the same conductive channel width-to-length ratio
  • the fourth transistor M4 and the second transistor M2 have the same conductive channel width-to-length ratio.
  • the channel lengths of the first transistor M1 and the second transistor M2 may be the same or different, that is, the resistance of the first resistance unit 121 is equal to the resistance R0 of the first branch 11 . After the first switching element K1 is closed, the resistance between the power supply voltage Vcc and the second node N2 may be R0/2.
  • the first transistor M1 and the second transistor M2 have the same channel length.
  • the third transistor M3 and the fourth transistor M4 in the second branch 12 may be fabricated in the same active region as the first transistor M1 and the second transistor M2 in the first branch 11 to reduce Occupied area of small branch road.
  • the bias voltage Vbias can be set to be adjustable by simply increasing the area of the first switch unit K1.
  • the first switching element K1 is also a channel enhancement mode P-type transistor, and the ratio of the conductive channel width-to-length ratio of the first switching element K1 to the conductive channel width-to-length ratio of the fourth transistor M4 can be, for example, is 1 to 3, in order to realize that the channel length of the first switching element K1 is larger than that of the fourth transistor M4 and the third transistor M3, ensuring that the current that can flow through the first switching element K1 when it is turned on is much larger than that flowing through the second branch 12 current to prevent the first switching element K1 from becoming the current bottleneck of the second branch 12.
  • the channel length of the first switching element K1 is twice the channel length of the fourth transistor M4.
  • the second branch 12 may also be implemented by one or more resistors and/or one or more other equivalent resistance components capable of achieving the same resistance, and the present disclosure does not impose any special limitation on this.
  • Figure 3 is a circuit schematic diagram of a current stabilization module in an embodiment of the present disclosure.
  • the current stabilizing module 13 that provides the constant current I to the second node N2 may be implemented by an N-type transistor operating in the saturation region, that is, the current stabilizing module 13 may include a fifth transistor M5 and a third transistor M5 .
  • the fifth transistor M5 works in the saturation region, the first end of the fifth transistor M5 is connected to the second node N2, the second end is connected to the third node N3, and both ends of the second resistor unit 131 are connected to the third node respectively. N3 and ground.
  • the drain ie, the second node N2
  • the drain has a constant current I.
  • a gate control voltage greater than the transistor threshold needs to be provided.
  • the gate of the fifth transistor M5 is connected to the output terminal of the amplifier OP, the first input terminal of the amplifier OP is connected to the bias control voltage VIBCOM, and the second input terminal of the amplifier OP is connected to the third node N3.
  • the first input terminal of the amplifier OP may be a non-inverting input terminal or an inverting input terminal, and correspondingly, the second input terminal may be an inverting input terminal or a non-inverting input terminal.
  • the first input terminal of the amplifier OP is a non-inverting input terminal
  • the second input terminal is an inverting input terminal
  • the voltage of the third node N3 is always equal to the bias control voltage VIBCOM.
  • the second resistor unit 131 has a resistor R2
  • the current I0 of the third node N3 is according to formula (3):
  • the saturated current flowing through the fifth transistor M5 that is, the current I of the second node N2 is equal to the current I0 of the third node N3.
  • the size of the saturation current I is only related to the gate voltage applied to the fifth transistor M5.
  • the gate voltage applied to The gate voltage on the fifth transistor M5 is the output voltage Vop of the amplifier OP.
  • the input terminal voltage of the amplifier OP that is, the bias control voltage VIBCOM
  • the gate voltage Vop of the fifth transistor M5 does not change.
  • the conduction state maintained in the saturation region does not change, and the saturation current does not change, that is, the current I of the second node N2 remains constant.
  • the second resistance unit 131 can be implemented in a variety of ways, such as including one or more variable resistors, fixed resistors, and/or one or more elements equivalent to resistors (such as transistors that control the turn-on degree through the gate voltage, etc.) , this disclosure does not impose special restrictions on this.
  • FIG. 4 is a circuit schematic diagram of a bias signal generating circuit in an embodiment of the present disclosure.
  • the bias signal generating circuit further includes a third branch 14 for reducing the current of the second node N2.
  • the third branch 14 has a resistor R3
  • the current I3 flowing through the third branch 14 is the ratio of the voltage difference between the voltage Vcc of the first node N1 and the voltage VIBCOM of the third node N3 and the resistor R3, that is:
  • the current I0 (equal to VIBCOM/R2) flowing through the second resistor unit 131 remains unchanged, and the current I0 of the third node N3 is the current I1 of the first branch 11, the current I2 of the second branch 12, and the current I0 of the third node N3.
  • the sum of the currents I3 of the three branches 14 is:
  • the constant current of the second node N2 is smaller than I0 in the embodiment shown in FIG. 3 .
  • the bias The voltage Vbias rises further.
  • the current of the second node N2 can be reduced when the power supply voltage Vcc is high, the first branch 11 carries limited current, and other components of the circuit are limited by conditions and cannot be adjusted. to the appropriate value.
  • the third branch 14 may include a third resistor unit 141 and a sixth transistor M6.
  • the first end of the sixth transistor is connected to the third resistor unit 141, and the second end is connected to the third node N3.
  • the gate is connected to the bias control voltage VIBCOM.
  • the sixth transistor M6 is, for example, a P-type transistor of the same type as the second transistor M2 and the fourth transistor M4. Since the sixth transistor M6 is controlled by the bias control voltage VIBCOM, it has a certain resistance.
  • the setting of the third branch 14 can reduce the current of the second node N2 while maintaining the bias voltage Vbias within a certain range, thereby reducing the driving current of the load circuit and ensuring that in high-speed mode, the current of the subsequent stage circuit It can maintain high-frequency operation and avoid excessive power consumption.
  • the first node N1 can be connected to the power supply voltage Vcc through the second switching element K2.
  • the second switching element K2 is controlled to be turned on or off according to the bias voltage enable control signal En, and then turned on. Or the operation of the bias signal generating circuit 100 is turned off.
  • the first switching element K1 and the second switching element K2 can both be P-type transistors.
  • FIG. 5 is a schematic diagram of a bias signal generating circuit controlling a load circuit in an embodiment of the present disclosure.
  • the bias signal Sbias can be used to control the third switching element K3.
  • the third switching element K3 is a P-type transistor.
  • the first end of the third switching element K3 is electrically connected to the power supply voltage Vcc.
  • the second terminal of the third switching element K3 is connected to the load circuit 51, and the control terminal of the third switching element K3 is connected to the second node N2.
  • the bias signal Sbias controls the load circuit.
  • the third switching element K3 in the load circuit through the voltage of the second node N2
  • it can also be realized by using the first branch 11 as a current generating unit of the current mirror.
  • the current flowing through the first branch 11 can be mirrored as the driving current of the load circuit.
  • the load circuit may be, for example, a clock calibration circuit, that is, the bias signal generating circuit may be used to reduce the power of the clock calibration circuit.
  • the bias voltage (used to control the power of the clock input circuit) generated in the existing word clock (WCK) input buffer bias generation circuit (clock input circuit for short) is certain. That is, the power of the clock input circuit is fixed and cannot be applied to scenarios with different power requirements. In low-speed mode, the clock circuit does not need to maintain high power, and there is room for reduction in the power of the clock circuit.
  • the bias signal generation circuit 100 provided by the embodiment of the present disclosure is applied in a clock circuit.
  • the clock calibration circuit operates in the low-speed mode, it has lower power requirements.
  • the first power can be controlled by the low-speed mode control signal Slsp.
  • the switching element K1 is closed, causing the bias voltage Vbias of the second node N2 to increase, the opening degree of the P-type third switching element K3 is reduced, and the current flowing through the third switching element K3 is reduced, thereby effectively reducing the load circuit 51 of power.
  • the first switching element K1 can be controlled to close through the low-speed mode control signal Slsp, so that the current I1 of the first branch 11 is reduced. In turn, the drive current of the load circuit is reduced and the power of the load circuit is reduced.
  • the first switching element K1 can be controlled to be turned off, and the bias voltage Vbias of the second node N2 is reduced, so that the third switching element K3 can be maintained at Driven by a smaller high-speed voltage, high power is provided to the load circuit 51 .
  • FIG. 6 is a schematic diagram of a clock input circuit according to an embodiment of the present disclosure.
  • clock input circuit 600 may include:
  • the clock calibration circuit 61 has a first input terminal connected to the external input clock WCKT and a second input terminal connected to the reference clock WCKC for calibrating the external input clock WCKT and outputting differential clock signals WCKT_int and WCKC_int.
  • the clock calibration circuit 61 passes the third switching element K3 Connect the power supply voltage Vcc;
  • the bias signal generating circuit 62 is connected to the control terminal of the third switching element K3, and is used to generate the bias signal Sbias, and control the opening degree of the third switching element K3 through the bias signal Sbias.
  • the bias signal generating circuit 62 may include the embodiment shown in any one of FIGS. 1 to 5 .
  • the third switching element K3 is a P-type transistor.
  • the bias signal generation circuit 100 responds to the low-speed mode control signal Slsp to increase the bias voltage Vbias of the bias signal Sbias to reduce the power of the clock calibration circuit 61 .
  • the third switching element K3 provides operating power for the clock calibration circuit 61 .
  • the opening degree of the third switching element K3 decreases, the internal resistance increases, and the partial voltage increases, resulting in the leakage of the third switching element K3.
  • the pole voltage decreases and the current decreases, that is, the driving voltage and driving current of the clock calibration circuit 61 decrease, and thus the power of the clock calibration circuit 61 decreases.
  • the low-speed mode control signal Slsp can be turned on through the first switching element K1 to control the power of the clock calibration circuit 61 to decrease.
  • the third switching element K3 can be connected to the power supply voltage Vcc through the fourth switching element K4.
  • the fourth switching element K4 is controlled by the clock calibration enable signal WCKEn and is used to control the operation of the clock input circuit 600. Enable or disable the clock calibration.
  • the clock calibration circuit 61 in FIG. 6 is only a simplified diagram and does not limit the detailed circuit diagram of the clock calibration circuit.
  • the third switching element K3 can be a P-type transistor or an N-type transistor. Considering that the third switching element K3 is directly connected to the high power supply voltage, a P-type transistor can be used here. More specifically, the third switching element K3 and the fourth switching element K4 are channel enhancement type P-type transistors.
  • the low-speed mode control signal Slsp controlled by the first switching element K1 can be output based on the frequency judgment of the input clock WCKT.
  • Figure 7 is a block diagram of a low-speed mode control signal generation module in one embodiment of the present disclosure.
  • the generation module 700 of the low-speed mode control signal Slsp may include:
  • the input terminal of the frequency counting unit 71 is used to receive the input clock WCKT, so as to perform frequency sampling on the input clock WCKT input per unit time.
  • the sampling method may be, for example, by collecting the rising edge and falling edge of the clock, accumulating the number of input clocks WCKT per unit time, and then obtaining the sampling clock frequency.
  • the frequency counting unit 71 can be implemented by a counter to detect the frequency of the input clock WCKT in real time.
  • the frequency comparison unit 72 is connected to the frequency counting unit 71 and is used to compare the sampling clock frequency measured by the frequency counting unit 71 with the set reference frequency, and output when the sampling clock frequency value per unit time is less than the reference frequency value. Low speed mode control signal Slsp. When the sampling clock frequency value per unit time is greater than or equal to the reference frequency value, the frequency comparison unit 72 does not output any signal.
  • the input end of the low-speed mode control signal Slsp generation module 700 can be connected to the output end of the clock calibration circuit 61 of the embodiment shown in Figure 6, and the output end of the low-speed mode control signal Slsp generation module 700 can be connected as shown in Figure 6
  • the bias signal generation circuit 62 of the embodiment shown in 6 is used to output the low-speed mode control signal Slsp when it is determined that the frequency of the input clock WCKT is less than the reference frequency value, to control the first switching element K1 to close, and to increase the bias of the second node N2
  • the voltage Vbias further reduces the turn-on degree of the third switching element K3 and reduces the driving voltage and driving current of the clock calibration circuit 61 , thereby reducing the power of the clock calibration circuit 61 .
  • the embodiment of the present disclosure can flexibly adjust the bias voltage, and then flexibly control the power of the load circuit controlled by the bias voltage.
  • this bias signal generation circuit in a clock calibration circuit to flexibly adjust the bias signal, the power of the clock calibration circuit can be reduced in a low-speed mode with lower power requirements, thereby reducing the overall power of the integrated circuit.

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Abstract

一种偏置信号生成电路（100）和应用该偏置信号生成电路（100）的时钟输入电路。偏置信号生成电路（100）包括：第一支路（11），第一端通过第一节点连接电源电压，第二端通过第二节点连接电流稳定模块（13），第一支路（11）用于产生偏置信号并通过第二节点输出偏置信号，电流稳定模块（13）用于为第二节点提供恒定电流；第二支路（12），两端分别连接第一节点和第二节点，包括串联的第一电阻单元（121）和第一开关元件，第一开关元件受控于低速模式控制信号开启或关闭；其中，低速模式控制信号用于控制第一开关元件开启以控制第二支路（12）与第一支路（11）并联，提高第二节点的偏置信号的偏置电压。该电路可以实现对偏置电压的灵活调节，继而扩大偏置电路的应用范围。

Description

偏置信号生成电路与时钟输入电路
交叉引用
本公开要求于2022年3月11日提交的申请号为202210237656.X、名称为“偏置信号生成电路与时钟输入电路”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及电子电路技术领域，具体而言，涉及一种能够灵活调节偏置电压的偏置信号生成电路，以及应用该偏置信号生成电路控制功率的时钟输入电路。
背景技术
在存储器中，时钟电路用于控制信号时序，具有较广泛的应用。
时钟电路通常包括时钟产生电路、时钟校准电路等等相关辅助电路，以保持输入时钟的准确性，在相关技术中，时钟电路通常保持稳定，具有固定的功耗。在集成电路优化功耗的大背景下，为了保持时钟的稳定，通常不考虑从时钟电路角度优化功率。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种能够灵活调节偏置电压的偏置信号生成电路，以及应用该偏置信号生成电路控制功率的时钟输入电路，用于至少在一定程度上降低时钟电路的功率。
根据本公开的第一方面，提供一种偏置信号生成电路，包括：第一支路，第一端通过第一节点连接电源电压，第二端通过第二节点连接电流稳定模块，所述第一支路用于产生偏置信号并通过所述第二节点输出所述偏置信号，所述电流稳定模块用于为所述第二节点提供恒定电流；第二支路，两端分别连接所述第一节点和所述第二节点，包括串联的第一电阻单元和第一开关元件，所述第一开关元件受控于低速模式控制信号开启或关闭；其中，所述低速模式控制信号用于控制所述第一开关元件开启以控制所述第二支路与所述第一支路并联，提高所述第二节点的偏置信号的偏置电压。
在本公开的一个示例性实施例中，所述第一支路包括第一晶体管和第二晶体管，所述第一晶体管和所述第二晶体管均为同类型晶体管，所述第一晶体管的第一端连接所述第一节点，所述第一晶体管的第二端和所述第二晶体管的第一端相连，所述第一晶体管的控制端和所述第二晶体管的第二端均连接所述第二节点，所述第二晶体管的控制端连接偏置控制电压。
在本公开的一个示例性实施例中，所述第一电阻单元包括第三晶体管和第四晶体管，所述第三晶体管和所述第四晶体管均为同类型晶体管，所述第三晶体管的第一端连接所述第一节点，所述第三晶体管的第二端和所述第四晶体管的第一端相连，所述第三晶体管的控制端连接所述第二节点，所述第四晶体管的第二端通过所述第一开关元件连接所述第二节点，所述第四晶体管的控制端连接偏置控制电压。
在本公开的一个示例性实施例中，所述第一晶体管、所述第二晶体管、所述第三晶体管和所述第四晶体管均为P型晶体管。
在本公开的一个示例性实施例中，所述第三晶体管与第一晶体管导电沟道宽长比相同，第二晶体管与第四晶体管导电沟道宽长比相同。
在本公开的一个示例性实施例中，所述电流稳定模块包括第五晶体管和第二电阻单元，所述第五晶体管的第一端连接所述第二节点，第二端连接第三节点，所述第二电阻单元的两端分别连接所述第三节点和接地。
在本公开的一个示例性实施例中，所述第五晶体管的栅极连接放大器的输出端，所述放大器的第一输入端连接偏置控制电压。
在本公开的一个示例性实施例中，所述第三节点连接所述放大器的第二输入端。
在本公开的一个示例性实施例中，还包括：第三支路，两端分别连接所述第一节点和所述第三节点，用于降低所述第二节点的电流。
在本公开的一个示例性实施例中，所述第三支路包括第三电阻单元和第六晶体管，所述第六晶体管的第一端连接所述第三电阻单元，第二端连接所述第三节点，栅极连接所述偏置控制电压。
在本公开的一个示例性实施例中，所述第一节点通过第二开关元件连接所述电源电压，所述第二开关元件受控于偏置电压使能控制信号。
在本公开的一个示例性实施例中，所述偏置信号用于控制第三开关元件，所述第三开关元件为P型晶体管，所述第三开关元件的第一端电连接电源电压，所述第三开关元件的第二端连接负载电路，所述第三开关元件的控制端连接所述第二节点。
在本公开的一个示例性实施例中，所述负载电路为时钟校准电路。
根据本公开的第二方面，提供一种时钟输入电路，包括：时钟校准电路，第一输入端连接外部输入时钟，第二输入端连接参考时钟，用于校准外部输入时钟，输出差分时钟信号，所述时钟校准电路通过第三开关元件连接电源电压；如上任一项所述的偏置信号生成电路，连接所述第三开关元件的控制端，用于生成偏置信号，并通过所述偏置信号控制所述第三开关元件的开启程度。
在本公开的一个示例性实施例中，所述第三开关元件为P型晶体管，所述偏置信号生成电路响应低速模式控制信号升高所述偏置信号的电压，以降低所述字时钟校准电路的功率。
本公开实施例通过控制第二支路与第一支路并联，提高输出的偏置电压，可以灵活调 节偏置电压，继而灵活控制受该偏置电压控制的负载电路的功率。通过在时钟校准电路中应用该偏置信号生成电路，以灵活调节偏置信号，可以在具有较低功率需求的低速模式下降低时钟校准电路的功率，进而降低集成电路的整体功率。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开示例性实施例中偏置信号生成电路的结构示意图。
图2是本公开一个实施例中第一支路和第二支路的示意图。
图3是本公开一个实施例中电流稳定模块的电路示意图。
图4是本公开一个实施例中偏置信号生成电路的电路示意图。
图5是本公开一个实施例中偏置信号生成电路控制负载电路的示意图。
图6是本公开实施例的时钟输入电路的示意图。
图7是本公开一个实施例中低速模式控制信号的产生模块的方框图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知技术方案以避免喧宾夺主而使得本公开的各方面变得模糊。
此外，附图仅为本公开的示意性图解，图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。附图中所示的一些方框图是功能实体，不一定必须与物理或逻辑上独立的实体相对应。可以采用软件形式来实现这些功能实体，或在一个或多个硬件模块或集成电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。
下面结合附图对本公开示例实施方式进行详细说明。
图1是本公开示例性实施例中偏置信号生成电路的结构示意图。
参考图1，偏置信号生成电路100可以包括：
第一支路11，第一端通过第一节点N1连接电源电压Vcc，第二端通过第二节点N2连接电流稳定模块13，第一支路11用于产生偏置信号Sbias并通过第二节点N2输出偏置信号Sbias，电流稳定模块13用于为第二节点N2提供恒定电流I；
第二支路12，两端分别连接第一节点N1和第二节点N2，包括串联的第一电阻单元121和第一开关元件K1，第一开关元件K1受控于低速模式控制信号Slsp开启或关闭；
其中，低速模式控制信号Slsp用于控制第一开关元件K1开启以控制第二支路12与第一支路11并联，提高第二节点N2的偏置信号Sbias的偏置电压Vbias。
在图1所示实施例中，设第一支路的电阻为R0，由于第二节点N2的电流被电流稳定模块13设置为恒定电流I，第二节点N2的电压即偏置电压Vbias根据公式(1)确定：
Vbias＝Vcc-I*R0           (1)
当第一开关元件K1开启时，第二支路中的第一电阻单元121与第一支路11并联，导致第二节点N2和电源电压Vcc之间的电阻降低。设电阻单元121的电阻为R1，则此时偏置电压Vbias为公式(2)：
Figure PCTCN2022091771-appb-000001
可见，第一开关元件K1闭合后，偏置电压Vbias上升。
可以通过控制第一电阻单元121的阻值来确定偏置电压Vbias的上升值。在一些实施例中，可以设置多条并联的第二支路，每条第二支路均设置开关元件以控制并联状态的进入，每条第二支路具有不同的阻值，从而可以通过控制不同阻值的支路并联到第一节点N1和第二节点N2之间，来控制偏置电压Vbias上升到不同的电压值。
图2是本公开一个实施例中第一支路和第二支路的示意图。
参考图2，在一个实施例中，第一支路11可以包括第一晶体管M1和第二晶体管M2，第一晶体管M1和第二晶体管M2均为同类型晶体管，第一晶体管M1的第一端连接第一节点N1，第一晶体管M2的第二端和第二晶体管M2的第一端相连，第一晶体管M1的控制端和第二晶体管M2的第二端均连接第二节点N2，第二晶体管M2的控制端连接偏置控制电压VIBCOM。
第二支路12中的第一电阻单元121可以包括第三晶体管M3和第四晶体管M4，第三晶体管M3和第四晶体管M4均为同类型晶体管，第三晶体管M3的第一端连接第一节点N1，第三晶体管M3的第二端和第四晶体管M4的第一端相连，第三晶体管M3的控制端连接第二节点N2，第四晶体管M4的第二端通过第一开关元件K1连接第二节点N2，第四晶体管M4的控制端连接偏置控制电压VIBCOM。
在图2所示实施例中，第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4均为P型晶体管，更具体的均为沟道增强型P型晶体管。当第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4均为沟道增强型P型晶体管时，第一晶体 管M1的源极连接第一节点N1，第一晶体管M1的漏极与第二晶体管M2的源极相连，第一晶体管M1的栅极和第二晶体管M2的漏极均连接第二节点N2，第二晶体管M2的栅极连接偏置控制电压VIBCOM；第三晶体管M3的源极连接第一节点N1，第三晶体管M3的漏极与第四晶体管M4的源极相连，第三晶体管M3的栅极和第四晶体管M4的漏极均连接第二节点N2，第四晶体管M4的栅极连接偏置控制电压VIBCOM。
在图2所示实施例中，第一晶体管M1受第二节点N2的偏置电压Vbias控制导通，具有第一电阻。第二晶体管M2的栅极受偏置控制电压VIBCOM控制，具有第二电阻。第一电阻和第二电阻之和构成第一支路的电阻R0。
在一个实施例中，第三晶体管M3与第一晶体管M1的导电沟道宽长比相同，第四晶体管M4与第二晶体管M2的导电沟道宽长比相同。第一晶体管M1与第二晶体管M2的沟道长度可以相同也可以不同，即，第一电阻单元121的电阻等于第一支路11的电阻R0。第一开关元件K1闭合后，电源电压Vcc和第二节点N2之间的电阻可以为R0/2。
在此实施例中，第一晶体管M1与第二晶体管M2具有相同的沟道长度。
在此实施例中，第二支路12中的第三晶体管M3和第四晶体管M4可以与第一支路11中的第一晶体管M1和第二晶体管M2在同一有源区中制备，以减小支路的占用面积。如此，只需增加一个第一开关单元K1的面积，即可实现将偏置电压Vbias设置为可调节。通过使用第一晶体管M1和第二晶体管M2作为第一电阻，使用第三晶体管M3和第四晶体管M4作为第二电阻，可以使电路的性能稳定，可靠性好，易于稳定调节流经第一支路11的电流。
在一个实施例中，第一开关元件K1同样为沟道增强型P型晶体管，且第一开关元件K1的导电沟道宽长比与第四晶体管M4的导电沟道宽长比的比值例如可以为1～3，以实现第一开关元件K1的沟道长度大于第四晶体管M4和第三晶体管M3，保证第一开关元件K1在导通时的可流通电流远大于流经第二支路12的电流，避免第一开关元件K1成为第二支路12的电流瓶颈。在本实施例中第一开关元件K1选用沟道长度是第四晶体管M4沟道长度的2倍。
第二支路12还可以通过一个或多个电阻和/或一个或多个能够达到相同电阻的其他等效电阻的元件实现，本公开对此不作特殊限制。
图3是本公开一个实施例中电流稳定模块的电路示意图。
参考图3，在一个实施例中，为第二节点N2提供恒定电流I的电流稳定模块13可以通过工作在饱和区的N型晶体管实现，即，电流稳定模块13可以包括第五晶体管M5和第二电阻单元131，第五晶体管M5工作在饱和区，第五晶体管M5的第一端连接第二节点N2，第二端连接第三节点N3，第二电阻单元131的两端分别连接第三节点N3和接地。
当N型的第五晶体管M5工作在饱和区时，漏极(即第二节点N2)具有恒定电流I。为了控制第五晶体管M5工作在饱和区，需提供大于晶体管阈值的栅极控制电压。
在图3所示实施例中，第五晶体管M5的栅极连接放大器OP的输出端，放大器OP 的第一输入端连接偏置控制电压VIBCOM，放大器OP的第二输入端连接第三节点N3。放大器OP的第一输入端可以为同相输入端或反相输入端，对应的，第二输入端为反相输入端或同相输入端。
本实施例中，放大器OP的第一输入端为同相输入端，第二输入端为反相输入端。
由于放大器OP的虚短特性，第三节点N3的电压恒等于偏置控制电压VIBCOM，设第二电阻单元131具有电阻R2，则第三节点N3的电流I0根据公式(3)有：
Figure PCTCN2022091771-appb-000002
此时，流经第五晶体管M5的饱和电流即第二节点N2的电流I等于第三节点N3的电流I0。
对于工作在饱和区的第五晶体管M5而言，在制备工艺及器件尺寸一定时，饱和电流I的大小仅与施加在第五晶体管M5上的栅极电压有关，在本实施例中，施加在第五晶体管M5上的栅极电压为放大器OP的输出电压Vop，在放大器OP的输入端电压即偏置控制电压VIBCOM不变时，第五晶体管M5的栅极电压Vop不变，第五晶体管M5维持在饱和区的导通状态不改变，饱和电流不变，即第二节点N2的电流I维持恒定。
第二电阻单元131可以通过多种方式实现，例如包括一个或多个可变电阻、固定电阻和/或一个或多个与电阻等效的元件(例如通过栅极电压控制开启程度的晶体管等)，本公开对此不作特殊限制。
图4是本公开一个实施例中偏置信号生成电路的电路示意图。
参考图4，在一个实施例中，偏置信号生成电路还包括第三支路14，用于降低第二节点N2的电流。设第三支路14具有电阻R3，则流经第三支路14的电流I3为第一节点N1的电压Vcc和第三节点N3的电压VIBCOM的电压差与电阻R3的比值，即：
Figure PCTCN2022091771-appb-000003
此时，流经第二电阻单元131的电流I0(等于VIBCOM/R2)不变，且第三节点N3的电流I0为第一支路11的电流I1、第二支路12的电流I2、第三支路14的电流I3之和，即：
I0＝I1+I2+I3           (5)
在图4所示实施例中，当第一开关元件K1闭合且VIBCOM控制第四晶体管M4导通、第六晶体管M6导通或部分导通时，第二节点N2的恒定电流I＝I1+I2＝I0-I3，第二节点N2的恒定电流小于图3所示实施例中的I0。此时，由于第一支路11和第二支路12的等效电阻相比第一开关元件K1断开时下降，在第二节点N2的恒定电流I下降，根据公式(2)，偏置电压Vbias进一步上升。
通过调节第三支路14的电阻值，可以在电源电压Vcc较高、第一支路11承接电流有限、电路其他元件均受限于条件无法调节等情况时，将第二节点N2的电流降低到合适的值。
参考图4，在一个实施例中，第三支路14可以包括第三电阻单元141和第六晶体管M6，第六晶体管的第一端连接第三电阻单元141，第二端连接第三节点N3，栅极连接偏置控制电压VIBCOM。第六晶体管M6例如为与第二晶体管M2、第四晶体管M4种类相同的P型晶体管。由于第六晶体管M6受到偏置控制电压VIBCOM控制，具有一定的电阻。
第三支路14的设置，可以在保持偏置电压Vbias在一定范围内的同时降低第二节点N2的电流，从而降低对负载电路的驱动电流，确保在高速模式下，后一级电路的电流既能维持高频运行，也能避免功耗过大。
在图2～图4所示实施例中，第一节点N1可以通过第二开关元件K2连接电源电压Vcc，第二开关元件K2受控于偏置电压使能控制信号En开启或关闭，继而开启或关闭偏置信号生成电路100的工作。
由于P型晶体管的耐高压性较好，能够在电压值较大的电源电压Vcc下运行稳定，第一开关元件K1、第二开关元件K2均可以为P型晶体管。
图5是本公开一个实施例中偏置信号生成电路控制负载电路的示意图。
参考图5，在一个实施例中，偏置信号Sbias可以用于控制第三开关元件K3，第三开关元件K3为P型晶体管，第三开关元件K3的第一端电连接电源电压Vcc，第三开关元件K3的第二端连接负载电路51，第三开关元件K3的控制端连接第二节点N2。
偏置信号Sbias控制负载电路的方式，除了通过第二节点N2的电压驱动负载电路中的第三开关元件K3，还可以通过将第一支路11作为电流镜的一个电流生成单元实现。通过在电流镜中设置另一个电流生成单元，对流经第一支路11的恒定电流I进行镜像，可以将流经第一支路11的电流镜像为负载电路的驱动电流。在闭合第一开关元件K1时，第一支路11上的电流减小(被第二支路12分流)，则负载电路的驱动电流减小，同样可以降低负载电路的功率。
负载电路例如可以为时钟校准电路，即偏置信号生成电路可以应用于降低时钟校准电路的功率。
本公开的发明人在研究中发现，相关技术中为了维持时钟稳定，在考虑集成电路功率降低时通常不考虑对时钟电路进行改动。由于时钟电路在集成电路中广泛应用，降低时钟电路的功率对降低集成电路/芯片的整体功率具有重大意义。
发明人发现，在存储器中，现有字时钟(Word Clock，WCK)输入缓冲偏置生成电路(简称时钟输入电路)中产生的偏置电压(用于控制时钟输入电路的功率)是一定的，即时钟输入电路的功率是一定的，无法适用于对功率要求不同的场景，在低速模式下时钟电路无需保持高功率，时钟电路的功率还具有降低空间。
将本公开实施例提供的偏置信号生成电路100应用在时钟电路中，当时钟校准电路工作在低速模式下时，对功率具有较低的要求，此时可以通过低速模式控制信号Slsp控制第一开关元件K1闭合，使第二节点N2的偏置电压Vbias上升，P型的第三开关元件K3 的开启程度减小，流经第三开关元件K3的电流减小，从而有效降低了负载电路51的功率。或者，当通过电流镜将第一支路11的电流I1镜像为负载电路的驱动电流时，可以通过低速模式控制信号Slsp控制第一开关元件K1闭合，使第一支路11的电流I1降低，进而降低负载电路的驱动电流，降低负载电路的功率。
当时钟校准电路工作在高速模式下时，对功率有较高的要求，此时可以控制第一开关元件K1断开，降低第二节点N2的偏置电压Vbias，使第三开关元件K3维持在较小的高速电压的驱动下，为负载电路51提供高功率。
图6是本公开实施例的时钟输入电路的示意图。
参考图6，在一个实施例中，时钟输入电路600可以包括：
时钟校准电路61，第一输入端连接外部输入时钟WCKT，第二输入端连接参考时钟WCKC，用于校准外部输入时钟WCKT，输出差分时钟信号WCKT_int和WCKC_int，时钟校准电路61通过第三开关元件K3连接电源电压Vcc；
偏置信号生成电路62，连接第三开关元件K3的控制端，用于生成偏置信号Sbias，并通过偏置信号Sbias控制第三开关元件K3的开启程度。
其中，偏置信号生成电路62可以包括如图1～图5任一项所示的实施例。第三开关元件K3为P型晶体管，偏置信号生成电路100响应低速模式控制信号Slsp升高偏置信号Sbias的偏置电压Vbias，以降低时钟校准电路61的功率。
第三开关元件K3为时钟校准电路61提供工作电源。
当低速模式控制信号Slsp控制第一开关元件K1开启，偏置电压Vbias升高时，第三开关元件K3的开启程度下降，内阻升高，分压增大，导致第三开关元件K3的漏极电压下降、电流下降，即时钟校准电路61的驱动电压下降、驱动电流下降，从而时钟校准电路61的功率下降。
在通过电流镜将第一支路11的电流镜像为第三开关元件K3的输出电流作为时钟校准电路61的驱动电流时，如果低速模式控制信号Slsp控制第一开关元件K1开启，第一支路11的电流I1下降，时钟校准电路61的驱动电流下降，也会导致时钟校准电路61的功率下降。
由此，低速模式控制信号Slsp可以通过第一开关元件K1开启，而控制时钟校准电路61的功率下降。
在图6所示实施例中，第三开关元件K3可以通过第四开关元件K4连接电源电压Vcc，第四开关元件K4受时钟校准使能信号WCKEn的控制，用于控制时钟输入电路600的使能或禁用，对时钟进行校准。图6中的时钟校准电路61仅为简化示意，不限制时钟校准电路的详细电路图。
第三开关元件K3可为P型晶体管或N型晶体管，考虑第三开关元件K3直接与高电源电压连接，此处可采用P型晶体管。更具体的，第三开关元件K3和第四开关元件K4为沟道增强型P型晶体管。
结合图6实施例，第一开关元件K1受控的低速模式控制信号Slsp，可以依据对输入时钟WCKT的频率判断而进行输出。
图7是本公开一个实施例中低速模式控制信号的产生模块的方框图。
参考图7，在一个实施例中，低速模式控制信号Slsp的产生模块700可以包括：
频率计数单元71，输入端用于接收输入时钟WCKT，以对单位时间内输入的输入时钟WCKT进行频率采样。采样方式例如可以为通过采集时钟的上升沿和下降沿，累加得出单位时间内输入时钟WCKT的数量，进而得到采样时钟频率。频率计数单元71可通过计数器实现，以实时检测输入时钟WCKT的频率。
频率比较单元72，连接频率计数单元71，用于将频率计数单元71测得的采样时钟频率与设定的参考频率进行比较，并在单位时间内的采样时钟频率数值小于参考频率数值时，输出低速模式控制信号Slsp。当单位时间内的采样时钟频率数值大于或等于参考频率数值时，频率比较单元72不输出任何信号。
在一个实施例中，低速模式控制信号Slsp的产生模块700的输入端可以连接图6所示实施例的时钟校准电路61的输出端，低速模式控制信号Slsp的产生模块700输出端可以连接如图6所示实施例的偏置信号生成电路62，以在判断输入时钟WCKT的频率小于参考频率数值时，输出低速模式控制信号Slsp，控制第一开关元件K1闭合，提高第二节点N2的偏置电压Vbias，进而降低第三开关元件K3的开启程度，降低时钟校准电路61的驱动电压和驱动电流，从而降低时钟校准电路61的功率。当将第一支路11的电流I1镜像为时钟校准电路61的驱动电流时，第一开关元件K1闭合时，导通的第二支路12对第一支路11的电流进行分流，使第一支路11的电流I1下降，从而使时钟校准电路61的驱动电流下降，降低时钟校准电路61的功率。
通过降低时钟校准电路在低速模式下的功率，可以节省时钟电路的整体功率。
应当注意，尽管在上文详细描述中提及了用于动作执行的设备的若干模块或者单元，但是这种划分并非强制性的。实际上，根据本公开的实施方式，上文描述的两个或更多模块或者单元的特征和功能可以在一个模块或者单元中具体化。反之，上文描述的一个模块或者单元的特征和功能可以进一步划分为由多个模块或者单元来具体化。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和构思由权利要求指出。
工业实用性
本公开实施例通过控制第二支路与第一支路并联，提高输出的偏置电压，可以灵活调节偏置电压，继而灵活控制受该偏置电压控制的负载电路的功率。通过在时钟校准电路中 应用该偏置信号生成电路，以灵活调节偏置信号，可以在具有较低功率需求的低速模式下降低时钟校准电路的功率，进而降低集成电路的整体功率。

Claims (15)

  1. 一种偏置信号生成电路，包括：
    第一支路，第一端通过第一节点连接电源电压，第二端通过第二节点连接电流稳定模块，所述第一支路用于产生偏置信号并通过所述第二节点输出所述偏置信号，所述电流稳定模块用于为所述第二节点提供恒定电流；
    第二支路，两端分别连接所述第一节点和所述第二节点，包括串联的第一电阻单元和第一开关元件，所述第一开关元件受控于低速模式控制信号开启或关闭；
    其中，所述低速模式控制信号用于控制所述第一开关元件开启以控制所述第二支路与所述第一支路并联，提高所述第二节点的偏置信号的偏置电压。
  2. 如权利要求1所述偏置信号生成电路，其中，所述第一支路包括第一晶体管和第二晶体管，所述第一晶体管和所述第二晶体管均为同类型晶体管，所述第一晶体管的第一端连接所述第一节点，所述第一晶体管的第二端和所述第二晶体管的第一端相连，所述第一晶体管的控制端和所述第二晶体管的第二端均连接所述第二节点，所述第二晶体管的控制端连接偏置控制电压。
  3. 如权利要求2所述偏置信号生成电路，其中，所述第一电阻单元包括第三晶体管和第四晶体管，所述第三晶体管和所述第四晶体管均为同类型晶体管，所述第三晶体管的第一端连接所述第一节点，所述第三晶体管的第二端和所述第四晶体管的第一端相连，所述第三晶体管的控制端连接所述第二节点，所述第四晶体管的第二端通过所述第一开关元件连接所述第二节点，所述第四晶体管的控制端连接偏置控制电压。
  4. 如权利要求3所述的偏置信号生成电路，其中，所述第一晶体管、所述第二晶体管、所述第三晶体管和所述第四晶体管均为P型晶体管。
  5. 如权利要求3所述的偏置信号生成电路，其中，所述第三晶体管与第一晶体管导电沟道宽长比相同，第二晶体管与第四晶体管导电沟道宽长比相同。
  6. 如权利要求1所述偏置信号生成电路，其中，所述电流稳定模块包括第五晶体管和第二电阻单元，所述第五晶体管的第一端连接所述第二节点，第二端连接第三节点，所述第二电阻单元的两端分别连接所述第三节点和接地。
  7. 如权利要求6所述的偏置信号生成电路，其中，所述第五晶体管的栅极连接放大器的输出端，所述放大器的第一输入端连接偏置控制电压。
  8. 如权利要求7所述的偏置信号生成电路，其中，所述第三节点连接所述放大器的第二输入端。
  9. 如权利要求6或8所述的偏置信号生成电路，其中，还包括：
    第三支路，两端分别连接所述第一节点和所述第三节点，用于降低所述第二节点的电流。
  10. 如权利要求9所述偏置信号生成电路，其中，所述第三支路包括第三电阻单元和 第六晶体管，所述第六晶体管的第一端连接所述第三电阻单元，第二端连接所述第三节点，栅极连接所述偏置控制电压。
  11. 如权利要求1所述偏置信号生成电路，其中，所述第一节点通过第二开关元件连接所述电源电压，所述第二开关元件受控于偏置电压使能控制信号。
  12. 如权利要求1所述偏置信号生成电路，其中，所述偏置信号用于控制第三开关元件，所述第三开关元件为P型晶体管，所述第三开关元件的第一端电连接电源电压，所述第三开关元件的第二端连接负载电路，所述第三开关元件的控制端连接所述第二节点。
  13. 如权利要求11所述偏置信号生成电路，其中，所述负载电路为时钟校准电路。
  14. 一种时钟输入电路，包括：
    时钟校准电路，第一输入端连接外部输入时钟，第二输入端连接参考时钟，用于校准外部输入时钟，输出差分时钟信号，所述时钟校准电路通过第三开关元件连接电源电压；
    如权利要求1～13任一项所述的偏置信号生成电路，连接所述第三开关元件的控制端，用于生成偏置信号，并通过所述偏置信号控制所述第三开关元件的开启程度。
  15. 如权利要求14所述的时钟输入电路，其中，所述第三开关元件为P型晶体管，所述偏置信号生成电路响应低速模式控制信号升高所述偏置信号的电压。
PCT/CN2022/091771 2022-03-11 2022-05-09 偏置信号生成电路与时钟输入电路 WO2023168820A1 (zh)

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