WO2023159516A1 - 显示基板及显示装置 - Google Patents
显示基板及显示装置 Download PDFInfo
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- WO2023159516A1 WO2023159516A1 PCT/CN2022/078082 CN2022078082W WO2023159516A1 WO 2023159516 A1 WO2023159516 A1 WO 2023159516A1 CN 2022078082 W CN2022078082 W CN 2022078082W WO 2023159516 A1 WO2023159516 A1 WO 2023159516A1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
Definitions
- Embodiments of the present disclosure relate to but are not limited to the field of display technology, and in particular, relate to a display substrate and a display device.
- ESD Electro-Static discharge
- the display substrate In the manufacturing process of display substrates (such as array substrates), Electro-Static discharge (ESD) is prone to occur on the display substrate, causing damage to the traces or circuits on the display substrate. Therefore, in order to avoid ESD damage, usually the display An ESD protection unit is provided on the substrate.
- ESD protection unit layout solutions in some technologies are not conducive to the rational utilization of wiring space.
- an embodiment of the present disclosure provides a display substrate, including: a display area and a non-display area located around the display area, the non-display area includes: at least one electrostatic discharge ESD protection unit, each ESD protection unit It includes: a plurality of transistors connected in series, the first electrode of each transistor is connected to the gate, and the plurality of transistors are arranged along a first oblique direction, and there is a first preset angle between the first oblique direction and the first direction, The first preset included angle is 10° to 80°, and the first direction is the extending direction of the grid lines in the display area.
- the embodiments of the present disclosure further provide a display device, including: the display substrate described in the above embodiments.
- FIG. 1A is a schematic structural view of a display substrate
- FIG. 1B is a schematic diagram showing the arrangement of the first corner region of the display substrate shown in FIG. 1A;
- FIG. 1C is a simulated current density diagram showing the first corner region of the substrate shown in FIG. 1A;
- FIG. 2 is a schematic structural diagram of a display substrate in an exemplary embodiment of the present disclosure
- 3A is a schematic diagram of a first arrangement of ESD protection units in an exemplary embodiment of the present disclosure
- 3B is a schematic diagram of a second arrangement of ESD protection units in an exemplary embodiment of the present disclosure
- FIG. 4 is a schematic diagram of an equivalent circuit of an ESD protection unit in an exemplary embodiment of the present disclosure
- FIG. 5A is a schematic structural view after forming a semiconductor layer in an ESD protection unit in an exemplary embodiment of the present disclosure
- FIG. 5B is a schematic structural view after forming the first conductive layer in the ESD protection unit in an exemplary embodiment of the present disclosure
- FIG. 5C is a schematic structural view after forming the second conductive layer in the ESD protection unit in an exemplary embodiment of the present disclosure
- FIG. 5D is a schematic structural view after forming the third conductive layer in the ESD protection unit in an exemplary embodiment of the present disclosure
- FIG. 6 is a schematic diagram showing the arrangement of the first corner region of the substrate shown in FIG. 2 .
- connection should be interpreted in a broad sense.
- it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two components.
- electrically connected includes the case where constituent elements are connected together through an element having some kind of electrical effect.
- the "element having some kind of electrical function” is not particularly limited as long as it can transmit and receive electrical signals between connected components.
- the “element having some kind of electrical function” may be, for example, an electrode or a wiring, or a switching element such as a transistor, or other functional elements such as a resistor, an inductor, or a capacitor.
- a transistor refers to at least three components including a gate electrode (gate or control electrode), a drain electrode (drain electrode terminal, drain region or drain electrode), and a source electrode (source electrode terminal, source region or source electrode). Components of the terminal.
- a transistor has a channel region between a drain electrode and a source electrode, and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, a channel region refers to a region through which current mainly flows.
- the gate electrode gate or control electrode
- the first electrode can be the drain electrode and
- the second pole may be a source electrode, or, the first pole may be a source electrode and the second pole may be a drain electrode.
- the functions of the "source electrode” and “drain electrode” may be interchanged. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged with each other.
- the transistors in the embodiments of the present disclosure may be thin film transistors (Thin Film Transistor, TFT) or field effect transistors (Field Effect Transistor, FET) or other devices with the same characteristics.
- the thin film transistors used in the embodiments of the present disclosure may include but not limited to oxide transistors (Oxide TFT) or low temperature polysilicon thin film transistors (Low Temperature Poly-silicon TFT, LTPS TFT) and the like.
- oxide transistors Oxide TFT
- Low Temperature Poly-silicon TFT Low Temperature Poly-silicon TFT, LTPS TFT
- the embodiments of the present disclosure do not limit this.
- parallel refers to a state where the angle formed by two straight lines is -10° to 10°, and therefore includes a state where the angle is -5° to 5°.
- perpendicular means a state in which the angle formed by two straight lines is 80° to 100°, and therefore also includes an angle of 85° to 95°.
- the "integrated structure" in the embodiments of the present disclosure may refer to two (or more than two) structures formed by the same deposition process and patterned by the same patterning process to form interconnected structures, and their materials may be the same or different.
- the first direction X may refer to the extending direction or the horizontal direction of the gate lines in the display area
- the second direction Y may refer to the extending direction or the vertical direction of the data lines in the display area
- the third direction Z It may refer to the direction perpendicular to the plane of the display substrate or the thickness direction of the display substrate.
- the first direction X and the second direction Y may be perpendicular to each other
- the first direction X and the third direction Z may be perpendicular to each other.
- Electrostatic discharge refers to the charge transfer caused by objects with different electrostatic charge potentials approaching or in direct contact. , that is, the electrostatic charge transfer between objects or surfaces with different electrostatic potentials (potential differences).
- Array substrate gate drive (Gate Driver on Array, GOA) technology refers to the technology of setting the GOA unit used to drive the gate line in the non-display area.
- FIG. 1A is a schematic structural view of a display substrate.
- the display substrate may include a display area (also called an active area (Active Area, AA)) 100 and a non-display area 200 located around the display area 100.
- AA Active Area
- the outer shape of the display area 100 and the outer shape of the non-display area are both rectangular shapes with rounded corners for illustration.
- the display area 100 may include: a first edge (also referred to as the left edge) and a second edge (also referred to as the left edge) oppositely disposed in the first direction X. right edge), and the third edge (also called the upper edge) and the fourth edge (also called the lower edge) that are oppositely arranged in the second direction Y, and the adjacent edges are connected by arc-shaped chamfers , forming a quadrilateral shape with rounded corners.
- first edge and the second edge may be parallel to the second direction Y
- third edge and the fourth edge may be parallel to the first direction X
- first direction X may be the extending direction of the gate lines in the display area
- second direction Y may be the extending direction of the data lines in the display area
- first direction X and the second direction Y may be perpendicular to each other.
- the shape of the non-display area 200 may be a rectangle with rounded corners.
- the non-display area 200 may include: a first frame area (also referred to as a lower frame area) 201 and a second frame area (also referred to as an upper frame area) 201 oppositely arranged in the second direction Y.
- the non-display area 200 may also include : the first corner area 211 connecting the first frame area 201 and the third frame area 203, the second corner area 212 connecting the first frame area 201 and the fourth frame area 204, connecting the second frame area 202 and the third frame area
- FIG. 1B is a schematic diagram of the arrangement of the first corner region of the display substrate shown in FIG. 1A
- FIG. 1C is a simulated current density diagram of the first corner region of the display substrate shown in FIG. 1A .
- FIG. 1B and FIG. 1C take a rounded first corner region 211 in the non-display region as an example for illustration.
- the area indicated by the arrow indicates the routing portion of the first power line VSS with a relatively high current density.
- the internal circuit unit of the display device such as a mobile phone, etc.
- the signal provided to the GOA unit from one end (Pad end) of the display substrate connected to the external circuit It is necessary to pass through the bending (Bending) area for transfer, and the metal trace from the lead wire starting from the Bending area to the GOA unit is long, and it is easy to accumulate electrostatic charges in the corner area due to the long trace. Therefore, An electrostatic discharge (ESD) protection unit may be provided in the arc-shaped corner region to prevent ESD damage.
- ESD electrostatic discharge
- the layout of the ESD protection unit in some technologies is unreasonable, and the wiring space is wasted, so that the ESD protection unit occupies the lower part of the wiring space to a certain extent.
- the ESD protection unit will occupy the wiring space of the first power line VSS to a certain extent, resulting in a higher current density of the first power line VSS, increasing the risk of burning the first power line VSS, and making the display products uniform and lower yields.
- the display substrate may include: a display area and a non-display area positioned at the periphery of the display area, the non-display area may include: at least one ESD protection unit, each ESD protection unit may include: a plurality of transistors connected in series, the first of each transistor The electrode is connected to the gate, and a plurality of transistors are arranged along the first inclined direction DR1, and there is a first preset included angle between the first inclined direction DR1 and the first direction X, wherein the first preset included angle may be approximately 10° to 80°, the first direction X is the extending direction of the grid lines in the display area.
- the ESD protection unit is implemented with a transistor structure, so that when other transistors in the display substrate are manufactured, the ESD protection unit can be manufactured at the same time without adding additional manufacturing processes.
- a plurality of transistors are arranged along the first oblique direction DR1, which may include: a plurality of transistors are arranged sequentially along the first oblique direction DR1 and arranged in a row along the second oblique direction DR2, wherein the first The second tilting direction DR2 may be perpendicular to the first tilting direction DR1.
- the sequential arrangement of multiple transistors along the first oblique direction DR1 may refer to: the active layers of the multiple transistors are sequentially arranged along the first oblique direction DR1, the gates of the multiple transistors are sequentially arranged along the first oblique direction DR1, and the plurality of transistors are sequentially arranged along the first oblique direction DR1.
- the first electrodes of the transistors are sequentially arranged along the first oblique direction DR1, and the second electrodes of the plurality of transistors are arranged sequentially along the first oblique direction DR1.
- the plurality of transistors are arranged along the first oblique direction DR1, which may include: the active layer of each transistor extends along the first oblique direction DR1, and the first pole, the second pole of each transistor Both the pole and the gate extend along the second oblique direction DR2, which is perpendicular to the first oblique direction DR1.
- active layers of a plurality of transistors may be an integrated structure connected to each other.
- the active layers of the multiple transistors in the multiple ESD protection units may be an integral structure connected to each other.
- the two ESD protection units sequentially arranged along the first inclination direction DR1 or the active layers of the transistors in the three ESD units may be an integral structure connected to each other.
- the ESD protection unit may further include: a first voltage signal line VGH, a second voltage signal line VGL, and an electrostatic discharge protection line Signal, the first voltage signal line VGH is connected to one end of the ESD protection unit The transistors are connected, the second voltage signal line VGL is connected to another transistor at the other end of the ESD protection unit, and the electrostatic discharge protection line Signal is connected to any connection node between the one transistor and the other transistor.
- the connection node may refer to a node formed between two adjacent transistors connected in series.
- the ESD protection unit includes four transistors in series as an example, the transistor at one end of the ESD protection unit may refer to the first transistor, and the other transistor at the other end of the ESD protection unit may refer to the fourth transistor , the arbitrary connection node between the one transistor and the other transistor may include: the first connection node formed by the first transistor connected in series with the second transistor, the second transistor connected with the third The second connection node formed by connecting transistors in series, or the third connection node formed by connecting the third transistor and the fourth transistor in series.
- the electrostatic discharge protection line Signal is connected to the second connection node formed by connecting the second transistor and the third transistor in series.
- the ESD protection line Signal refers to the wiring on the display substrate that is prone to accumulate electrostatic charges, and the ESD protection unit is configured to release the electrostatic charge accumulated on the ESD protection line Signal.
- electrostatic charges can be positive or negative.
- the electrostatic discharge protection line Signal may include but not limited to: the first clock signal line ESTV, the second clock signal line ECB, the third clock signal line At least part of signal lines such as ECK, fourth clock signal line GSTV, fifth clock signal line GCB, sixth clock signal line GCK, seventh clock signal line RSTV, eighth clock signal line RCB, or ninth clock signal line RCK .
- the ESD protection line Signal may also be other signal lines requiring anti-static, which is not limited in this embodiment of the present disclosure.
- each ESD protection line Signal may be connected to an ESD protection unit to implement anti-static.
- the signal of the first voltage signal line VGH is a high level signal
- the signal of the second voltage signal line VGL is a low level signal
- the plurality of series-connected transistors may include but not limited to: two series-connected transistors, three series-connected transistors, four series-connected transistors, five series-connected transistors , or six transistors connected in series.
- the number of transistors in the ESD protection unit may be set according to actual application scenarios, which is not limited in this embodiment of the present disclosure.
- the non-display area may include: a first frame area and a second frame area oppositely arranged in the second direction, a third frame area and a fourth frame area oppositely arranged in the first direction , the first corner area connecting the first frame area and the third frame area, the second corner area connecting the first frame area and the fourth frame area, and the third corner area connecting the second frame area and the third frame area , and the fourth corner area connecting the second frame area and the fourth frame area, at least one of the first corner area to the fourth corner area is an arc-shaped corner area, and the ESD protection unit is located at the corner of the arc
- the first direction may be the extending direction of the gate lines in the display area
- the second direction may be the extending direction of the data lines in the display area.
- the non-display area of the display substrate may include but not limited to: a gate drive circuit (Gate GOA unit), a light emission control drive circuit (EM GOA unit), an electrostatic discharge protection unit (ESD circuit) and wires (for example, the first power line VSS).
- the non-display area may also include: other circuits, for example, a source driver circuit for supplying data voltages to the data lines, or a detection circuit (CT) for performance detection, etc.
- CT detection circuit
- the non-display area may further include: a first power supply line VSS, and part of the routing of the first power supply line VSS located in the corner area of the arc includes: a first A sub-trace part and a second sub-trace part extending along the first direction.
- the width of the second sub-trace part may be 300 microns to 343 microns, for example, the width of the second sub-trace part may be 323.49 microns.
- the width of the first sub-trace part may be between 250 microns and 270 microns, and the width of the first sub-trace part may be 260 microns.
- the width refers to the dimension characteristic along the second direction Y.
- the exemplary embodiments of the present disclosure make no limitation thereto.
- the ESD protection unit can be prevented from encroaching on the VSS wiring space, thereby increasing the line width of the first power supply line VSS, reducing the current of the first power supply line VSS, and reducing Risk of burns on the first power line VSS.
- the first power line VSS is configured to provide a low voltage signal to the display substrate.
- the non-display area may further include: a gate driving GOA unit connected to the gate line in the display area and connected to the electrostatic discharge protection line in the ESD protection unit.
- a gate driving GOA unit connected to the gate line in the display area and connected to the electrostatic discharge protection line in the ESD protection unit.
- the ESD protection unit can protect the GOA unit from ESD damage .
- the display substrate may be an array substrate.
- the display substrate may be an organic light emitting diode (Organic Light Emitting Diode, OLED) display substrate or a liquid crystal display (Liquid Crystal Display, LCD) display substrate or the like.
- OLED Organic Light Emitting Diode
- LCD liquid crystal Display
- the display substrate in the exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings by taking a display substrate in which both the display area and the non-display area have a rectangular shape with rounded corners as an example.
- FIG. 2 is a schematic structural diagram of a display substrate in an exemplary embodiment of the present disclosure.
- the display substrate may include: a display area 100 and a non-display area 200 located around the display area 100 .
- the non-display area 200 may include: a first frame area 201 and a second frame area 202 oppositely arranged in the second direction Y, a third frame area 203 and a fourth frame area 204 oppositely arranged in the first direction X, non-
- the display area 200 may further include: a first corner area 211 connecting the first frame area 201 and the third frame area 203, a second corner area 212 connecting the first frame area 201 and the fourth frame area 204, connecting the second The frame area 202 and the third corner area 213 of the third frame area 203, and the fourth corner area 214 connecting the second frame area 202 and the fourth frame area 204,
- the first direction X is the extension of the grid lines in the display area 100
- the second direction Y is the extending direction of the data lines
- first corner region 211 to the fourth corner region 214 are rounded corner regions.
- first corner area 211 may include: at least one ESD protection unit 30
- second corner area 212 may include: at least one ESD protection unit 30 .
- the non-display area 100 may further include: GOA units 50 located on both sides of the display area 100 in the first direction X, and the GOA units 50 are connected to the gate lines in the display area 100 , the GOA unit 50 is connected to the corresponding ESD protection line in the ESD protection unit 30 .
- the GOA units 50 are arranged along the outer contour of the display area 100, by tilting the ESD protection unit 30 along the first inclination direction DR1, the wiring space occupied by the ESD protection unit can be reduced, and the GOA can be saved. The wiring space occupied by the connecting wires between the unit and the ESD protection unit. Thus, product uniformity and yield can be effectively improved.
- the ESD protection unit 30 can protect the GOA unit to avoid ESD damage.
- the GOA unit 50 may include: a plurality of cascaded gate shift register units, each gate shift register unit is connected to at least one gate line in the display area of the display substrate, configured To provide a row-by-row shifted gate drive signal to at least one gate line in the display area.
- the GOA unit 50 may include: a plurality of cascaded light emission control shift register units, each light emission control shift register unit is connected to at least one gate line in the display area of the display substrate, and is configured to send to at least one of the display area The gate line provides a row-by-row shifted light emission control signal, which is a gate drive circuit for outputting the light emission control signal.
- the shift register unit may be implemented in various forms, which are not limited in this embodiment of the present disclosure.
- a plurality of cascaded gate shift register units can be set along the The outer contour of the area 100 is arranged, and the extension direction of the clock signal lines of the gate shift register unit of the last stage is the same or approximately the same as the first inclination direction DR1.
- the gate shift register unit of the last stage in the GOA unit 50 can be reduced in size.
- the extension direction of the clock signal line of the gate shift register unit of the last stage is the same as the first inclined direction DR1
- the extension direction of the main part of the clock signal line is the same as the first inclination direction DR1
- the gate shift register unit of the last stage is The extension direction of the clock signal line of the bit register unit is the same as the first inclination direction DR1” may mean that the tangent direction of the clock signal line is the same as the first inclination direction DR1.
- the embodiments of the present disclosure do not limit this.
- the clock signal lines of the gate shift register unit of the last stage may include: the first clock signal line ESTV, the second clock signal line ECB, the third clock signal line ECK, the fourth clock signal line GSTV, the fifth clock signal line At least one of the signal lines GCB, the sixth clock signal line GCK, the seventh clock signal line RSTV, the eighth clock signal line RCB, or the ninth clock signal line RCK.
- the embodiments of the present disclosure do not limit this.
- the non-display area 100 may further include: a wiring 40 arranged on a side of the GOA unit 50 and the ESD protection unit 30 away from the display area 100 , for example, the wiring 40 It may be the first power supply line VSS.
- the ESD protection unit can be prevented from encroaching on the wiring space of the first power supply line VSS, thereby, the line width of the first power supply line VSS can be increased, and the width of the first power supply line VSS can be reduced. VSS current, reducing the risk of burning the first power line VSS.
- FIG. 3A is a schematic diagram of a first arrangement of ESD protection units in an exemplary embodiment of the present disclosure
- FIG. 3B is a schematic diagram of a second arrangement of ESD protection units in an exemplary embodiment of the present disclosure.
- the traces in FIG. 3A to FIG. 3B are only exemplary illustrations, the number of traces does not represent the actual number, and the shape of the traces does not represent the actual shape.
- 3A and 3B show an ESD protection unit in the substrate as an example.
- the ESD protection unit includes 4 transistors connected in series, the electrostatic discharge protection line Signal, the first voltage signal line VGH and the second voltage signal line VGL. Make a gesture.
- FIG. 3A is a schematic diagram of a first arrangement of ESD protection units in an exemplary embodiment of the present disclosure
- FIG. 3B is a schematic diagram of a second arrangement of ESD protection units in an exemplary embodiment of the present disclosure.
- the traces in FIG. 3A to FIG. 3B are only exemplary illustrations, the number
- the first voltage signal line VGH, the second voltage signal line VGL and the ESD protection line Signal all including: a first wiring and a second wiring as an example.
- the first voltage signal line VGH and the second voltage signal line VGL both include: the first wiring and the second wiring
- the electrostatic discharge protection line Signal includes: the first wiring, the second wiring and the second wiring. Take three wires as an example to illustrate.
- the ESD protection unit 30 may include: a first voltage signal line VGH, a second voltage signal line VGL, an electrostatic discharge protection line Signal and four transistors connected in series , wherein the first pole of each transistor is connected to the gate, the first voltage signal line VGH is connected to the first transistor at one end of the ESD protection unit, and the second voltage signal line VGL is connected to the fourth transistor at the other end of the ESD protection unit.
- the transistors are connected, and the electrostatic discharge protection line Signal is connected to the connection node formed between the second transistor and the third transistor.
- the first electrode of each transistor is connected to the gate, and the four transistors are arranged along the first oblique direction DR1, and the first oblique direction DR1 is connected to the first oblique direction DR1.
- There is a first preset angle between one direction X the first preset angle may be about 10° to 80°, and the first direction X is the extending direction of the grid lines in the display area.
- the ESD protection unit 30 can be reduced in the first direction X and The wiring space occupied by the second direction Y. Therefore, the wiring space of the ESD protection unit can be reduced, the wiring space of other wirings can be avoided, and the uniformity and yield of display products can be improved.
- the degree of the first preset included angle is related to the shape of the outer contour of the corner region of the display area (AA area), therefore, it can be set according to the radian of the rounded corner of the outer outline of the display area (AA area), As long as the wiring space of the ESD protection unit can be reduced and the wiring space of other wirings can be avoided. Embodiments of the present disclosure do not limit this.
- At least one of the electrostatic discharge protection line Signal, the first voltage signal line VGH, and the second voltage signal line VGL may include: a first wiring and a second wiring, the first wiring It is arranged on the same layer as the first electrode and the second electrode of the transistor, and the second wiring is arranged on the same layer as the gate of the transistor.
- the first routing extends along the second oblique direction DR2
- the second routing extends along the first oblique direction DR1
- the second oblique direction DR2 is perpendicular to the first oblique direction DR1 .
- the first voltage signal line VGH may include: a first connection line 31 - 1 and a first extension line 32 - 1 .
- the first connection line 31 - 1 as the first routing in the first voltage signal line VGH, may be a straight line extending along the second oblique direction DR2 .
- the first extension line 32-1 as the second routing in the first voltage signal line VGH, can be a straight line or a broken line extending along the first inclination direction DR1, and the second inclination direction DR2 is perpendicular to the first inclination direction DR1 .
- 3A and 3B take the first extension line 32-1 as a broken line as an example.
- the main body of the first extension line 32-1 can be inclined The direction DR1 extends, and the extension portion of the first extension line 32 - 1 may extend along the first direction X.
- the main body portion of the first extension line 32-1 may extend along the first oblique direction DR1, and the extension portion of the first extension line 32-1 may extend along the second direction Y.
- the embodiments of the present disclosure do not limit this.
- the ESD protection line Signal may include: a second connection line 31 - 2 and a second extension line 32 - 2 .
- the second connecting line 31 - 2 as the first routing in the electrostatic discharge protection line Signal, may be a straight line extending along the second oblique direction DR2 .
- the second extension line 32 - 2 as the second routing in the ESD protection line Signal, may be a straight line or a broken line extending along the first inclination direction DR1 , and the second inclination direction DR2 is perpendicular to the first inclination direction DR1 .
- the second extension line 32 - 2 is taken as a broken line as an example for illustration.
- the main body portion of the second extension line 32 - 2 may extend along the first oblique direction DR1
- the extension portion of the second extension line 32 - 2 may extend along the first direction X.
- the main body portion of the second extension line 32-2 may extend along the first oblique direction DR1
- the extension portion of the second extension line 32-2 may extend along the second direction Y.
- the embodiments of the present disclosure do not limit this.
- the second voltage signal line VGL may include: a third connection line 31 - 3 and a third extension line 32 - 3 .
- the third connecting line 31 - 3 as the first routing in the second voltage signal line VGL, may be a straight line extending along the second oblique direction DR2 .
- the third extension line 32-3 as the second routing in the second voltage signal line VGL, can be a straight line or a broken line extending along the first inclination direction DR1, and the second inclination direction DR2 is perpendicular to the first inclination direction DR1 .
- the third extension line 32-3 is taken as a broken line as an example for illustration.
- the extension may extend along the first direction X.
- the main body portion of the third extension line 32-3 may extend along the first oblique direction DR1, and the extension portion of the third extension line 32-3 may extend along the second direction Y.
- the embodiments of the present disclosure do not limit this.
- At least one of the electrostatic discharge protection line Signal, the first voltage signal line VGH, and the second voltage signal line VGL may further include: a third wiring, where the film layer of the third wiring is located on Between the film layer where the first wiring is located and the film layer where the second wiring is located.
- the third trace may include: at least one of a straight line extending along the first inclination direction DR1 and a folded line at least including a trace portion extending along the first inclination direction DR1.
- the fold lines may include at least one of the following first fold lines, second fold lines and third fold lines.
- the first fold line may include: a first sub-line extending along the first oblique direction DR1 and a second sub-line extending along the first direction X, which are connected in sequence.
- the second folding line may include: a third sub-line extending along the first inclination direction DR1, a fourth sub-line extending in the first direction X, and a fifth sub-line extending in the third inclination direction DR3, which are sequentially connected.
- the second preset included angle may be different from the first preset included angle.
- the third fold line may include: a sixth sub-line extending along the first oblique direction DR1 and a seventh sub-line extending along the second direction Y, which is the extending direction of the data lines in the display area, connected in sequence.
- other fold lines may also be used, which is not limited in this embodiment of the present disclosure.
- the degree of the second preset angle is related to the shape of the outer contour of the corner area of the display area (AA area), therefore, it can be set according to the radian of the rounded corner of the outer outline of the display area (AA area), As long as the wiring space of the ESD protection unit can be reduced and the wiring space of other wirings can be avoided. Embodiments of the present disclosure do not limit this.
- the ESD protection line Signal may include: a second connection line 31 - 2 , a second extension line 32 - 2 and a second lead line 33 - 2 .
- the second connecting line 31 - 2 as the first routing in the electrostatic discharge protection line Signal, may be a straight line extending along the second oblique direction DR2 .
- the second extension line 32 - 2 as the second routing in the ESD protection line Signal, may be a straight line or a broken line extending along the first inclination direction DR1 , and the second inclination direction DR2 is perpendicular to the first inclination direction DR1 .
- the second lead-out line 33 - 2 as the third routing in the ESD protection line Signal, may be a straight line or a broken line extending along the first inclined direction DR1 , and the second inclined direction DR2 is perpendicular to the first inclined direction DR1 .
- the second lead-out line 33 - 2 as the third routing in the electrostatic discharge protection line Signal, may be at least one of the first folded line, the second folded line, and the third folded line. For example, as shown in FIG.
- the second lead-out line 33-2 may include: a third sub-line extending along the first oblique direction DR1 and a third sub-line extending along the first direction X that are sequentially connected.
- the four sub-wires and the fifth sub-wire extend along the third inclination direction DR3, and the third inclination direction DR3 has a second preset included angle with the first direction X.
- the second preset included angle may be different from the first preset included angle.
- the second extension line 32 - 2 is a straight line
- the second lead-out line 33 - 2 is a second folding line as an example for illustration.
- the embodiments of the present disclosure do not limit this.
- the line shapes of the ESD protection line Signal, the first voltage signal line VGH, and the second voltage signal line VGL can also be other shapes that enable the ESD protection unit to move along the first The implementation of the arrangement in the oblique direction DR1.
- the embodiments of the present disclosure do not limit this.
- FIG. 4 is a schematic diagram of an equivalent circuit of an ESD protection unit in an exemplary embodiment of the present disclosure.
- the ESD protection unit may include: 4 transistors in series (the first transistor M1 to the fourth transistor M4) and 3 signal lines (the first voltage signal line VGH, the second voltage signal line VGL and the electrostatic discharge Protection line Signal).
- the first pole of the first transistor M1 and the gate of the first transistor M1 are connected to the first voltage signal line VGH, and the second pole of the first transistor M1 is connected to the first voltage signal line VGH.
- the first pole of the second transistor M2 is connected to the gate of the second transistor M2, the second pole of the second transistor M2, the first pole of the third transistor M3 and the gate of the third transistor M3 are connected to the electrostatic discharge protection signal line Signal , the second pole of the third transistor M3 is connected to the first pole of the fourth transistor M4 and the gate of the fourth transistor M4, and the second pole of the fourth transistor M4 is connected to the second voltage signal line VGL.
- the electrostatic discharge (ESD) protection unit can discharge the electrostatic charge accumulated in the electrostatic discharge protection line Signal.
- the working principle of the ESD protection unit shown in FIG. 4 is: when the positive charge accumulated on the ESD protection line Signal satisfies the first condition, the ESD protection line Signal will output a high voltage signal, Turning on the first transistor M1 and the second transistor M2 causes the high voltage signal to be pulled down by the first voltage signal line VGH, thereby realizing static electricity elimination.
- the ESD protection line Signal When the negative charge accumulated on the ESD protection line Signal satisfies the second condition, the ESD protection line Signal will output a low-voltage signal, making the third transistor M3 and the fourth transistor M4 turn on, causing the low-voltage signal to be suppressed by the second voltage.
- the signal line VGL is pulled high, thereby eliminating static electricity.
- the first condition may refer to the minimum amount of positive charge that can cause the ESD protection unit to burn
- the second condition may refer to the minimum amount of negative charge that can cause the ESD protection unit to burn.
- the first transistor M1 to the fourth transistor M4 may be P-type transistors, or may be N-type transistors.
- the embodiments of the present disclosure do not limit this.
- the preparation process of the ESD protection unit is exemplified below.
- the "patterning process” mentioned in this disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist and other treatments for metal materials, inorganic materials or transparent conductive materials, and for organic materials, including Coating of organic materials, mask exposure and development, etc.
- Deposition can use any one or more of sputtering, evaporation, chemical vapor deposition
- coating can use any one or more of spray coating, spin coating and inkjet printing
- etching can use dry etching and wet Any one or more of the engravings is not limited in the present disclosure.
- “Thin film” refers to a layer of thin film made of a certain material on a substrate by deposition, coating or other processes.
- the "thin film” does not require a patterning process during the entire manufacturing process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “film” before the patterning process, and it is called a “layer” after the patterning process.
- the “layer” after the patterning process includes at least one "pattern”. "A and B are arranged in the same layer” in this disclosure means that A and B are formed simultaneously through the same patterning process.
- the ESD protection unit 30 may include: a semiconductor layer, a first conductive layer, a second conductive layer and a third conductive layer sequentially arranged on the substrate,
- the semiconductor layer may include: active layers of multiple transistors, and the first conductive layer may include: gates of multiple transistors and at least one of the electrostatic discharge protection line Signal, the first voltage signal line VGH, and the second voltage signal line VGL
- the included second wiring, the second conductive layer may include: at least one of the electrostatic discharge protection line Signal, the first voltage signal line VGH, and the second voltage signal line VGL.
- the third wiring included in the third conductive layer It may include: first poles of multiple transistors, second poles of multiple transistors, and a first wiring included in at least one of the electrostatic discharge protection line Signal, the first voltage signal line VGH, and the second voltage signal line VGL .
- FIGS. 5A to 5D are schematic diagrams of the preparation process of the ESD protection unit in the display substrate shown in FIG. 2 , illustrating a layout structure of an ESD protection unit of the display substrate. Referring to the structure of the ESD protection unit shown in FIG. 3B , the preparation process of the ESD protection unit in the display substrate provided in the exemplary embodiment of the present disclosure will be described in conjunction with FIGS. 5A to 5D .
- the preparation process of the ESD protection unit may include the following operations:
- forming the semiconductor layer pattern on the substrate may include: sequentially depositing a first insulating film and a semiconductor film on the substrate, and patterning the semiconductor film through a patterning process to form a first layer covering the entire substrate. an insulating layer, and a semiconductor layer disposed on the first insulating layer.
- the first insulating layer may be called a buffer (Buffer) layer
- the semiconductor layer may be called an Active (ACT) layer.
- the semiconductor layer may include: a first active layer 61, a second active layer 71, a third active layer 81 and a fourth active layer in each ESD protection unit.
- Active layer 91 wherein the first active layer 61 serves as the active layer of the first transistor M1, the second active layer 71 serves as the active layer of the second transistor M2, and the third active layer 81 serves as the third transistor M3
- the active layer of the fourth active layer 91 is used as the active layer of the fourth transistor M4.
- the first active layer 61, the second active layer 71, the third active layer 81, and the fourth active layer 91 are sequentially set, flush in the second inclination direction DR2.
- the ESD units can be obliquely arranged along the first inclination direction DR1.
- the shapes of the first active layer 61, the second active layer 71, the third active layer 81 and the fourth active layer 91 can be along the first slope A long strip extending in the direction DR1.
- the active layer 61 of the first transistor M1, the active layer 71 of the second transistor M2, and the active layer 81 of the third transistor M3 can be integrated with each other. structure.
- the substrate may be a flexible substrate, or a rigid substrate.
- the semiconductor layer may be made of metal oxide material.
- metal oxide materials may include, but are not limited to: oxides containing indium and tin, oxides containing tungsten and indium, oxides containing tungsten and indium and zinc, oxides containing titanium and indium, oxides containing titanium and indium and tin oxides, oxides containing indium and zinc, oxides containing silicon and indium and tin, oxides containing indium, gallium and zinc, and the like.
- the semiconductor layer can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si) , Hexathiophene or polythiophene and other materials.
- a-IGZO amorphous indium gallium zinc oxide
- ZnON zinc oxynitride
- IZTO indium zinc tin oxide
- a-Si amorphous silicon
- p-Si polycrystalline silicon
- Hexathiophene or polythiophene and other materials amorphous silicon
- the semiconductor layer may be a single layer, a double layer, or a multilayer, and the like.
- the embodiments of the present disclosure do not limit this.
- the first insulating layer can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be single layer, multilayer layers or composite layers.
- forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first metal film on the substrate forming the aforementioned pattern, and performing a patterning process on the first conductive layer.
- the metal thin film is patterned to form a second insulating layer covering the pattern of the semiconductor layer, and a first conductive layer disposed on the second insulating layer.
- the second insulating layer may be called a gate insulating (GI) layer
- the first conductive layer may be called a first gate metal (Gate1) layer.
- the first conductive layer may include: a first gate electrode 62, a second gate electrode 72, a third gate electrode 82 and a fourth gate electrode of each ESD protection unit 92, may further include: a first extension line 32-1, a second extension line 32-2, and a third extension line 32-3.
- the first gate electrode 62 is used as the gate of the first transistor M1, and the orthographic projection of the first gate electrode 62 on the substrate overlaps with the orthographic projection of the first active layer 61 on the substrate. area.
- the second gate electrode 72 is used as the gate of the second transistor M2, and the orthographic projection of the second gate electrode 72 on the substrate overlaps with the orthographic projection of the second active layer 71 on the substrate.
- the third gate electrode 82 serves as the gate of the third transistor M3, and the orthographic projection of the third gate electrode 82 on the substrate overlaps with the orthographic projection of the first active layer 81 on the substrate.
- the fourth gate electrode 92 serves as the gate of the fourth transistor M4, and the orthographic projection of the fourth gate electrode 92 on the substrate overlaps with the orthographic projection of the first active layer 91 on the substrate.
- the first gate electrode 62, the second gate electrode 72, the third gate electrode 82, and the fourth gate electrode 92 may be sequentially arranged at intervals along the first inclination direction DR1, And they are aligned in the second inclination direction DR2.
- the first extension line 32-1 serves as the second wiring in the first voltage signal line VGH, so as to be connected to the first wiring in the subsequently formed first voltage signal line VGH, A first voltage signal line VGH is formed.
- the second extension line 32 - 2 is used as the second line in the ESD protection line Signal, so as to be connected with the first line in the subsequently formed ESD protection line Signal to form the ESD protection line Signal.
- the third extension line 32 - 3 is used as the second wiring in the second voltage signal line VGL so as to be connected with the first wiring in the second voltage signal line VGL formed later to form the second voltage signal line VGL.
- the second insulating layer can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be single-layer, multilayer layers or composite layers.
- the second conductive layer may be formed using a metal material.
- metal materials may include, but are not limited to: any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the metals listed above, such as aluminum Neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), etc.
- the second conductive layer may be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo and the like.
- forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second metal film on the substrate forming the aforementioned pattern, and patterning the second conductive layer through a patterning process.
- the metal thin film is patterned to form a third insulating layer covering the first conductive layer, and a second conductive layer disposed on the third insulating layer.
- the third insulating film may be called an interlayer dielectric (ILD) layer, and the second conductive layer may be called a second gate metal (Gate2) layer.
- ILD interlayer dielectric
- Gate2 second gate metal
- the third conductive layer may include: a second lead-out line 33 - 2 .
- the second lead-out line 33-2 as the third line in the ESD protection line Signal, is connected to the second line in the ESD protection line Signal through a via hole, so as to be connected to the ESD protection line Signal formed later. first trace connection.
- the second lead-out line 33-2 may be at least one of the first fold line, the second fold line and the third fold line.
- the second lead-out line 33-2 is taken as an example to illustrate the second broken line.
- the second lead-out line 33-2 may include: third sub-lines connected in sequence and extending along the first oblique direction DR1 , a fourth sub-wire extending along the first direction X and a fifth sub-wire extending along the third oblique direction DR3.
- forming the third conductive layer pattern may include: sequentially depositing a fourth insulating film and a third metal film on the substrate forming the aforementioned pattern, and patterning the third conductive layer through a patterning process.
- the metal thin film is patterned to form a fourth insulating layer covering the second conductive layer, and a third conductive layer disposed on the fourth insulating layer.
- the fourth insulating film may be called an interlayer dielectric (ILD) layer, and the third conductive layer may be called a second gate metal (Gate2) layer.
- ILD interlayer dielectric
- Gate2 second gate metal
- the third conductive layer may include: a first connection line 31-1, a second connection line 31-2, a third connection line 31-3, a first connection electrode 63 , the second connection electrode 73 , the third connection electrode 83 , and the fourth connection electrode 93 .
- the first connection line 31-1 as the first wiring in the first voltage signal line VGH, extends along the second oblique direction DR2.
- the first connection The line 31-1 is connected to the first extension line 32-1 through a via hole, so as to form a first voltage signal line VGH.
- the second connection line 31-2 as the first line in the electrostatic discharge protection line Signal, may extend along the second inclined direction DR2, so that the second connection The line 31-2 is connected to the second extension line 32-2 through the via hole, and the second extension line 32-2 is connected to the second lead-out line 33-2 through the via hole, so as to form an electrostatic discharge protection line Signal.
- the third connecting line 31-3 as the first wiring in the second voltage signal line VGL, may extend along the second oblique direction DR2, so that the third The connection line 31-3 is connected to the third extension line 32-3 through the via hole, so as to form the second voltage signal line VGL.
- the first connection electrode 63 serves as the first pole of the first transistor M1 .
- the shape of the first connection electrode 63 may be an "L" shape, one end of the first connection electrode 63 is connected to the first region of the first active layer 61, and the other end of the first connection electrode 63 is connected to the first gate electrode 62, In order to realize the connection between the gate of the first transistor M1 and the first electrode of the first transistor M1.
- the first connection electrode 63 and the first connection line 31 - 1 may be an integral structure connected to each other, and the gate of the first transistor M1 , the first electrode of the first transistor M1 may be connected to the first voltage signal line VGH.
- the second connection electrode 73 serves as the second pole of the first transistor M1 and the first pole of the second transistor M2 .
- the shape of the second connection electrode 73 can be "L" shape, and one end of the second connection electrode 73 is connected with the second region of the first active layer 61 and the first region of the second active layer 71 at the same time, and the second connection electrode The other end of 73 is connected to the second gate electrode 72 to realize the connection of the second pole of the first transistor M1, the gate of the second transistor M2 and the first pole of the second transistor M2, that is, to realize the connection between the first transistor M1 and the second Transistor M2 is connected in series.
- the third connection electrode 83 serves as the second pole of the second transistor M2 and the first pole of the third transistor M3 .
- the shape of the third connecting electrode 83 can be "L" shape, and one end of the third connecting electrode 83 is connected with the second region of the second active layer 71 and the first region of the third active layer 81, and the third connecting electrode 83 The other end of is connected to the third gate electrode 82, so as to realize the connection of the second electrode of the second transistor M2, the gate of the third transistor M3, and the first electrode of the third transistor M3.
- the third connection electrode 83 and the second connection line 31-2 can be an integral structure connected to each other, which can realize the connection between the second pole of the second transistor M2, the gate of the third transistor M3, and the first pole of the third transistor M3.
- the discharge protection cable is connected to Signal.
- the fourth connection electrode 93 serves as the second pole of the third transistor M3 and the first pole of the fourth transistor M4.
- the shape of the fourth connecting electrode 93 can be "L" shape, and one end of the fourth connecting electrode 93 is connected with the second region of the third active layer 81 and the first region of the fourth active layer 91, and the fourth connecting electrode 93 The other end of is connected to the fourth gate electrode 92, so as to realize the connection of the second electrode of the third transistor M3, the gate of the fourth transistor M4, and the first electrode of the fourth transistor M4.
- one end of the third connection line 31-3 connected to the second region of the fourth active layer 91 is used as the second pole of the fourth transistor M4 to realize
- the second electrode of the fourth transistor M4 is connected to the second voltage signal line VGL.
- the third conductive layer may be formed using a metal material.
- metal materials may include, but are not limited to: any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the metals listed above, such as aluminum Neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), etc.
- the third conductive layer can be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo and the like.
- the display area 100 may include: a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P may include: a first sub-pixel P1 that emits light of a first color, The second sub-pixel P2 that emits the light of the second color and the third sub-pixel P3 that emits the light of the third color, for example, the first sub-pixel P1 can be a red (R) sub-pixel, and the second sub-pixel P2 can be a green (G) sub-pixel. ) sub-pixel, and the third sub-pixel P3 may be a blue (B) sub-pixel.
- R red
- G green
- B blue
- At least one of the plurality of pixel units P may include: a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4 that emit light of different colors.
- the pixel unit P may include four sub-pixels, such as red sub-pixels, green sub-pixels, blue sub-pixels and white sub-pixels.
- the embodiments of the present disclosure do not limit this.
- each sub-pixel may include: a pixel driving circuit and a light emitting device.
- the pixel driving circuits in the sub-pixels are respectively connected to the gate lines, the data lines and the light-emitting signal lines, and the light-emitting devices in the sub-pixels are connected to the pixel driving circuits of the sub-pixels respectively, and the pixel driving circuits are configured to connect the gate lines and the light emitting Under the control of the signal line, the data voltage transmitted by the data line is received, and a corresponding current is output to the light-emitting device, and the light-emitting device is configured to respond to the current output by the pixel driving circuit of the sub-pixel to emit light with a corresponding brightness.
- the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure, or the like.
- the embodiments of the present disclosure do not limit this.
- the plurality of sub-pixels in a pixel unit may be arranged in a horizontal arrangement, a vertical arrangement, an X shape, a cross shape, or a square shape.
- the three sub-pixels may be arranged horizontally, vertically or in a zigzag manner.
- the four sub-pixels may be arranged horizontally, vertically, or squarely.
- the embodiments of the present disclosure do not limit this.
- FIG. 6 is a schematic diagram showing the arrangement of the first corner region in the substrate shown in FIG. 2, wherein the ESD protection unit 30, the wiring, and the GOA unit 50 in FIG. 6 are only an exemplary illustration, and the number of ESD protection units It does not represent the actual number, the number of traces does not represent the actual number, and the shape of the traces does not represent the actual shape.
- the ESD protection unit 30 is arranged obliquely along the first inclination direction DR1 Compared with setting the arrangement direction of a plurality of serial transistors in parallel with the first direction X, the wiring space occupied by the ESD protection unit 30 in the first direction X can be reduced, and the space occupied by the ESD protection unit 30 can be reduced.
- the wiring space can save the wiring space occupied by the connection line between the ESD protection unit 30 and the GOA unit 50, and reduce the wiring space occupied by the ESD protection unit 30 in the second direction Y, which can avoid the occupation of the ESD protection unit 30
- the wiring space of the first power supply line VSS, thus, the line width of the first power supply line VSS can be increased.
- the GOA unit 50 including a plurality of cascaded gate shift register units as an example, in addition to the ESD protection unit 30 being inclined along the first inclination direction DR1, it is also possible to set the gate of the last stage
- the extension direction of the clock signal line of the shift register unit is the same or approximately the same as the first inclination direction DR1 , so that the gate shift register unit of the last stage can be obliquely arranged along the first inclination direction DR1 .
- the wiring space occupied by the gate shift register unit of the last stage in the first direction X and the second direction Y perpendicular to the first direction X in the GOA unit 50 can be reduced, thereby reducing the GOA unit.
- the wiring space can further save the wiring space occupied by the connection line between the GOA unit and the ESD protection unit, avoid encroaching on other wiring spaces, and effectively improve product uniformity and yield.
- the ESD protection unit 30 is arranged obliquely along the first inclination direction DR1 in FIG. 6 .
- the line width of the first power line VSS can be increased to about 323.49 microns, thereby reducing the current of the first power line VSS, reducing the risk of burning the first power line VSS, and improving the uniformity and yield of products.
- a display device may include: the display substrate in one or more of the above-mentioned exemplary embodiments.
- the display device may include but not limited to: a thin film transistor liquid crystal display (Thin Film Transistor-Liquid Crystal Display, TFT-LCD) display device or an active matrix organic light emitting diode (Active Matrix Organic Light Emitting Diode , AMOLED) display devices, etc.
- TFT-LCD Thin Film Transistor-Liquid Crystal Display
- AMOLED Active Matrix Organic Light Emitting Diode
- the display device may include, but not limited to, any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, or a navigator.
- a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, or a navigator.
- the embodiment of the present disclosure does not limit this.
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Abstract
一种显示基板及显示装置,该显示基板,包括:显示区域和位于所述显示区域周边的非显示区域,所述非显示区域包括:至少一个静电放电ESD保护单元,每一个ESD保护单元包括:多个串联的晶体管,每一个晶体管的第一极与栅极连接,且多个晶体管沿第一倾斜方向排布,第一倾斜方向与第一方向之间具有第一预设夹角,第一预设夹角为10°至80°,第一方向为显示区域中栅线的延伸方向。
Description
本公开实施例涉及但不限于显示技术领域,尤其涉及一种显示基板及显示装置。
显示基板(如阵列基板)制备工艺中,显示基板上容易出现静电放电(Electro-Static discharge,ESD),对显示基板上的走线或电路造成损伤,因此,为了避免ESD损伤,通常会在显示基板上设置ESD保护单元。然而,一些技术中的ESD保护单元布设方案不利于布线空间的合理利用。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面,本公开实施例提供了一种显示基板,包括:显示区域和位于所述显示区域周边的非显示区域,所述非显示区域包括:至少一个静电放电ESD保护单元,每一个ESD保护单元包括:多个串联的晶体管,每一个晶体管的第一极与栅极连接,且多个晶体管沿第一倾斜方向排布,第一倾斜方向与第一方向之间具有第一预设夹角,第一预设夹角为10°至80°,第一方向为显示区域中栅线的延伸方向。
另一方面,本公开实施例还提供了一种显示装置,包括:上述实施例中所述的显示基板。
本公开的其它特征和优点将在随后的说明书中阐述,并且,部分地从说明书中变得显而易见,或者通过实施本公开而了解。本公开的其他优点可通过在说明书以及附图中所描述的方案来实现和获得。
在阅读并理解了附图和详细描述后,可以明白其他方面。
附图用来提供对本公开技术方案的理解,并且构成说明书的一部分,与本公开的实施例一起用于解释本公开的技术方案,并不构成对本公开的技术方案的限制。附图中每个部件的形状和大小不反映真实比例,目的只是示意说明本公开内容。
图1A为一种显示基板的结构示意图;
图1B为图1A所示显示基板中第一角部区域的排布示意图;
图1C为图1A所示显示基板中第一角部区域的仿真电流密度图;
图2为本公开示例性实施例中的显示基板的结构示意图;
图3A为本公开示例性实施例中的ESD保护单元的第一种排布示意图;
图3B为本公开示例性实施例中的ESD保护单元的第二种排布示意图;
图4为本公开示例性实施例中的ESD保护单元的等效电路示意图;
图5A为本公开示例性实施例中的形成ESD保护单元中半导体层后的结构示意图;
图5B为本公开示例性实施例中的形成ESD保护单元中第一导电层后的结构示意图;
图5C为本公开示例性实施例中的形成ESD保护单元中第二导电层后的结构示意图;
图5D为本公开示例性实施例中的形成ESD保护单元中第三导电层后的结构示意图;
图6为图2所示显示基板中第一角部区域的排布示意图。
本文描述了多个实施例,但是该描述是示例性的,而不是限制性的,在本文所描述的实施例包含的范围内可以有更多的实施例和实现方案。尽管在附图中示出了许多可能的特征组合,并在示例性实施方式中进行了讨论,但是所公开的特征的许多其它组合方式是可能的。除非特意加以限制的情况以 外,任何实施例的任何特征或元件可以与任何其它实施例中的任何其他特征或元件结合使用,或可以替代任何其它实施例中的任何其他特征或元件。
在描述具有代表性的实施例时,说明书可能已经将方法或过程呈现为特定的步骤序列。然而,在该方法或过程不依赖于本文步骤的特定顺序的程度上,该方法或过程不应限于的特定顺序的步骤。如本领域普通技术人员将理解的,其它的步骤顺序是可能的。因此,说明书中阐述的步骤的特定顺序不应被解释为对权利要求的限制。此外,针对该方法或过程的权利要求不应限于按照所写顺序执行它们的步骤,本领域技术人员可以容易地理解,这些顺序可以变化,并且仍然保持在本公开实施例的精神和范围内。
在附图中,有时为了明确起见,夸大表示了每个构成要素的大小、层的厚度或区域。因此,本公开的一个方式并不一定限定于该尺寸,附图中每个部件的形状和大小不反映真实比例。此外,附图示意性地示出了理想的例子,本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置,而不是为了在数量方面上进行限定的。
在本说明书中,为了方便起见,使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系,仅是为了便于描述本说明书和简化描述,而不是指示或暗示所指的装置或元件具有特定的方位、以特定的方位构造和操作,因此不能理解为对本公开的限制。构成要素的位置关系根据描述每个构成要素的方向适当地改变。因此,不局限于在说明书中说明的词句,根据情况可以适当地更换。
在本说明书中,除非另有明确的规定和限定,术语“安装”、“相连”、“连接”应做广义理解。例如,可以是固定连接,或可拆卸连接,或一体地连接;可以是机械连接,或电连接;可以是直接相连,或通过中间件间接相连,或两个元件内部的连通。对于本领域的普通技术人员而言,可以根据情况理解上述术语在本公开中的含义。
在本说明书中,“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的 电信号的授受,就对其没有特别的限制。“具有某种电作用的元件”例如可以是电极或布线,或者是晶体管等开关元件,或者是电阻器、电感器或电容器等其它功能元件等。
在本说明书中,晶体管是指至少包括栅电极(栅极或控制极)、漏电极(漏电极端子、漏区域或漏极)以及源电极(源电极端子、源区域或源极)这三个端子的元件。晶体管在漏电极与源电极之间具有沟道区域,并且电流能够流过漏电极、沟道区域以及源电极。注意,在本说明书中,沟道区域是指电流主要流过的区域。
在本说明书中,为了区分晶体管除栅电极(栅极或控制极)之外的两极,直接描述了其中一极为第一极,另一极为第二极,其中,第一极可以为漏电极且第二极可以为源电极,或者,第一极可以为源电极且第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下,“源电极”及“漏电极”的功能有时互相调换。因此,在本说明书中,“源电极”和“漏电极”可以互相调换。
本公开实施例中的晶体管均可以为薄膜晶体管(Thin Film Transistor,TFT)或场效应管(Field Effect Transistor,FET)或其它特性相同的器件。例如,本公开实施例中使用的薄膜晶体管可以包括但不限于氧化物晶体管(Oxide TFT)或者低温多晶硅薄膜晶体管(Low Temperature Poly-silicon TFT,LTPS TFT)等。这里,本公开实施例对此不做限定。
在本说明书中,“平行”是指两条直线形成的角度为-10°以上且10°以下的状态,因此,也包括该角度为-5°以上且5°以下的状态。另外,“垂直”是指两条直线形成的角度为80°以上且100°以下的状态,因此,也包括85°以上且95°以下的角度的状态。
本公开中的“约”,是指不严格限定界限,允许工艺和测量误差范围内的数值。
本公开实施例中的“一体结构”可以是指两种(或两种以上)结构通过同一道沉积工艺形成并通过同一道构图工艺得以图案化而形成的彼此连接的结构,它们的材料可以相同或不同。
在本公开实施例中,第一方向X可以是指显示区域中栅线的延伸方向或 者水平方向,第二方向Y可以是指显示区域中数据线的延伸方向或者竖直方向,第三方向Z可以是指垂直于显示基板平面的方向或者显示基板的厚度方向等。其中,第一方向X和第二方向Y可以相互垂直,第一方向X和第三方向Z可以相互垂直。
为了便于本领域技术人员更好地理解本公开的技术方案,下面对本公开示例性实施例中可能涉及到的技术名词进行简要介绍。
静电放电(ESD)是指具有不同静电荷电位的物体相互靠近或直接接触引起的电荷转移,简单来说,就是静电电荷瞬间从一个物体移到另一个物体上,形成一个电荷转移的过程的现象,即具有不同静电电势(电位差)的物体或表面之间的静电电荷转移。阵列基板栅极驱动(Gate Driver on Array,GOA)技术是指将用于驱动栅线的GOA单元设置在非显示区域的技术。
随着显示技术的发展,“屏占比”已经成为显示产品比较重要的性能参数,根据消费者对显示产品便携、视角效果等方面的追求,高分辨率、窄边框甚至全屏显示成为显示产品发展的新趋势,因此边框的窄化在显示产品设计中越来越受到重视。
图1A为一种显示基板的结构示意图,如图1A所示,显示基板可以包括显示区域(又可称为有效显示区(Active Area,AA))100和位于显示区域100周边的非显示区域200。这里,图1A中是以显示区域100的外形和非显示区域的外形均为带倒圆角的矩形形状为例进行示意。
在一种示例性实施例中,如图1A所示,显示区域100可以包括:在第一方向X上相对设置的第一边缘(又可称为左边缘)和第二边缘(又可称为右边缘),以及在第二方向Y上相对设置的第三边缘(又可称为上边缘)和第四边缘(又可称为下边缘),相邻边缘之间通过弧形的倒角连接,形成倒圆角的四边形形状。例如,第一边缘和第二边缘可以平行于第二方向Y,第三边缘和第四边缘可以平行于第一方向X,第一方向X可以是显示区域中栅线的延伸方向,第二方向Y可以是显示区域中数据线的延伸方向,第一方向X和第二方向Y可以相互垂直。
在一种示例性实施例中,非显示区域200的外形可以为矩形倒圆角形状。例如,如图1A所示,非显示区域200可以包括:在第二方向Y上相对设置 的第一边框区域(又可称为下边框区域)201和第二边框区域(又可称为上边框区域)202,在第一方向X上相对设置的第三边框区域(又可称为左边框区域)203和第四边框区域(又可称为右边框区域)204,非显示区域200还可以包括:连接第一边框区域201和第三边框区域203的第一角部区域211、连接第一边框区域201和第四边框区域204的第二角部区域212、连接第二边框区域202和第三边框区域203的第三角部区域213、以及连接第二边框区域202和第四边框区域204的第四角部区域214。
图1B为图1A所示显示基板中第一角部区域的排布示意图,图1C为图1A所示显示基板中第一角部区域的仿真电流密度图。其中,图1B和图1C中是以非显示区域中的一个倒圆角的第一角部区域211为例进行示意。图1C中是以箭头所指区域表示第一电源线VSS中电流密度较大的走线部分。
在一种示例性实施例中,如图1B和图1C所示,显示装置(如手机等)的内部电路单元,从显示基板的连接外部电路的一端(Pad端)向GOA单元提供的信号,要经过弯折(Bending)区进行转接,而从Bending区开始的引线至接入GOA单元前的这段金属走线较长,容易因走线较长导致角部区域静电电荷累积,因此,可以在圆弧形的角部区域中设置静电放电(ESD)保护单元来防止ESD损伤。但是,一些技术中的ESD保护单元布设不合理,布线空间被浪费,使得ESD保护单元在一定程度上占据了下部分的布线空间。例如,ESD保护单元在一定程度上会侵占第一电源线VSS的走线的布线空间,导致第一电源线VSS的电流密度较大,增加第一电源线VSS灼伤的风险,使得显示产品的均一性和良率降低。
本公开实施例提供一种显示基板。该显示基板可以包括:显示区域和位于显示区域周边的非显示区域,非显示区域可以包括:至少一个ESD保护单元,每一个ESD保护单元可以包括:多个串联的晶体管,每一个晶体管的第一极与栅极连接,且多个晶体管沿第一倾斜方向DR1排布,第一倾斜方向DR1与第一方向X之间具有第一预设夹角,其中,第一预设夹角可以约为10°至80°,第一方向X为显示区域中栅线的延伸方向。
如此,通过将ESD保护单元中的多个串联的晶体管的排布方向与第一方向X呈第一预设角度进行设置,相比于将多个串联的晶体管的排布方向与第 一方向X平行设置,可以减小ESD保护单元在第一方向X和与第一方向X垂直的第二方向Y上所占用的布线空间。从而,能够实现减少ESD保护单元的布线空间,避免挤占其它走线的布线空间,实现提升产品的均一性和良率。此外,ESD保护单元采用晶体管结构实现,使得在制造显示基板中的其它晶体管时,可以同时制造ESD保护单元,无需增加额外制造工序。
在一种示例性实施例中,多个晶体管沿第一倾斜方向DR1排布,可以包括:多个晶体管沿第一倾斜方向DR1依次设置且在第二倾斜方向DR2上平齐设置,其中,第二倾斜方向DR2与第一倾斜方向DR1可以垂直。例如,多个晶体管沿第一倾斜方向DR1依次设置可以是指:多个晶体管的有源层沿第一倾斜方向DR1依次设置,多个晶体管的栅极沿第一倾斜方向DR1依次设置,多个晶体管的第一极沿第一倾斜方向DR1依次设置,多个晶体管的第二极沿第一倾斜方向DR1依次设置。
在一种示例性实施例中,多个晶体管沿第一倾斜方向DR1排布,可以包括:每一个晶体管的有源层沿第一倾斜方向DR1延伸,且每一个晶体管的第一极、第二极和栅极均沿第二倾斜方向DR2延伸,第二倾斜方向DR2与第一倾斜方向DR1垂直。
在一种示例性实施例中,在每一个ESD保护单元中,多个晶体管的有源层可以为相互连接的一体结构。
在一种示例性实施例中,多个ESD保护单元中的多个晶体管的有源层可以为相互连接的一体结构。例如,沿第一倾斜方向DR1依次设置的两个ESD保护单元,或者,三个ESD单元中晶体管的有源层可以为相互连接的一体结构。
在一种示例性实施例中,ESD保护单元还可以包括:第一电压信号线VGH、第二电压信号线VGL和静电放电保护线Signal,第一电压信号线VGH与位于ESD保护单元一端的一个晶体管连接,第二电压信号线VGL与位于ESD保护单元另一端的另一个晶体管连接,静电放电保护线Signal与位于该一个晶体管与该另一个晶体管之间的任意一个连接节点连接。其中,连接节点可以是指串联的两个相邻的晶体管之间所形成的节点。例如,以ESD保护单元包括:四个串联的晶体管为例,该位于ESD保护单元一端的一个晶体管 可以是指第1个晶体管,位于ESD保护单元另一端的另一个晶体管可以是指第4个晶体管,该位于该一个晶体管与该另一个晶体管之间的任意一个连接节点可以包括:由第1个晶体管与第2个晶体管串联所形成的第1个连接节点、由第2个晶体管与第3个晶体管串联所形成的第2个连接节点、或者由第3个晶体管与第4个晶体管串联所形成的第3个连接节点。例如,静电放电保护线Signal与由第2个晶体管与第3个晶体管串联所形成的第2个连接节点连接。
这里,静电放电保护线Signal是指显示基板上容易聚集静电电荷的走线,ESD保护单元被配置为释放静电放电保护线Signal上聚集的静电电荷。例如,静电电荷可以为正电荷或者负电荷。
在一种示例性实施例中,以ESD保护单元与GOA单元连接为例,静电放电保护线Signal可以包括但不限于:第一时钟信号线ESTV、第二时钟信号线ECB、第三时钟信号线ECK、第四时钟信号线GSTV、第五时钟信号线GCB、第六时钟信号线GCK、第七时钟信号线RSTV、第八时钟信号线RCB、或者第九时钟信号线RCK等信号线的至少部分。当然,静电放电保护线Signal还可以为其它需防静电的信号线,这里,本公开实施例对此不做限定。
在一种示例性实施例中,每一条静电放电保护线Signal可以连接一个ESD保护单元,来实现防静电。
在一种示例性实施例中,第一电压信号线VGH的信号为高电平信号,第二电压信号线VGL的信号为低电平信号。
在一种示例性实施例中,针对每一个ESD保护单元,多个串联的晶体管可以包括但不限于:二个串联的晶体管、三个串联的晶体管、四个串联的晶体管、五个串联的晶体管、或者六个串联的晶体管等结构。其中,ESD保护单元中晶体管的数量可以根据实际应用场景进行设置,这里,本公开实施例对此不做限定。
在一种示例性实施例中,非显示区域可以包括:在第二方向上相对设置的第一边框区域和第二边框区域,在第一方向上相对设置的第三边框区域和第四边框区域,连接第一边框区域和第三边框区域的第一角部区域,连接第一边框区域和第四边框区域的第二角部区域,连接第二边框区域和第三边框 区域的第三角部区域,以及连接第二边框区域和第四边框区域的第四角部区域,第一角部区域至第四角部区域中的至少一个为弧形的角部区域,ESD保护单元位于弧形的角部区域,第一方向可以为显示区域中栅线的延伸方向,第二方向可以为显示区域中数据线的延伸方向。
在一种示例性实施例中,显示基板的非显示区域可以包括但不限于:栅极驱动电路(Gate GOA单元)、发光控制驱动电路(EM GOA单元)、静电放电保护单元(ESD电路)和走线(如,第一电源线VSS)。当然,非显示区域还可以包括:其它电路,例如,用于向数据线提供数据电压的源极驱动电路、或者用于性能检测的检测电路(CT)等,这里,本公开实施例对此不做限定。
在一种示例性实施例中,非显示区域还可以包括:第一电源线VSS,第一电源线VSS位于弧形的角部区域中的部分走线包括:沿第一倾斜方向延伸的第一子走线部分和沿第一方向延伸的第二子走线部分。例如,第二子走线部分的宽度可以为300微米至343微米,如,第二子走线部分的宽度可以为323.49微米。例如,第一子走线部分的宽度可以为250微米至270微米之间,第一子走线部分的宽度可以为260微米。其中,宽度是指沿第二方向Y的尺寸特征。这里,本公开示例性实施例对此不作限定。
如此,通过合理设置ESD保护单元所占用的布线空间,可以避免ESD保护单元侵占VSS走线空间,从而,可以增大第一电源线VSS的线宽,能够降低第一电源线VSS的电流,降低第一电源线VSS灼伤的风险。
例如,第一电源线VSS被配置为向显示基板提供低电压信号。
在一种示例性实施例中,非显示区域还可以包括:栅极驱动GOA单元,栅极驱动GOA单元与显示区域中的栅线连接,并与ESD保护单元中的静电放电保护线连接。如此,通过将ESD保护单元沿第一倾斜方向DR1倾斜设置,既可以减少ESD保护单元所占用的布线空间,又可以节省GOA单元与ESD保护单元之间连接线所占用的布线空间。从而,能够有效提升产品均一性和良率。此外,由于GOA单元与对应的ESD保护单元中的静电放电保护线连接,而ESD保护单元被配置为释放静电放电保护线Signal上累积的静电电荷,因此,ESD保护单元能够保护GOA单元避免ESD损伤。
在一种示例性实施例中,显示基板可以为阵列基板。
在一种示例性实施例中,显示基板可以为有机发光二极管(Organic Light Emitting Diode,OLED)显示基板或者液晶显示(Liquid Crystal Display,LCD)显示基板等。这里,本公开实施例对此不做限定。
下面以显示基板中的显示区域和非显示区域的外形均为带倒圆角的矩形形状为例,结合附图对本公开示例性实施例中的显示基板进行说明。
图2为本公开示例性实施例中的显示基板的结构示意图,如图2所示,该显示基板可以包括:显示区域100和位于显示区域100周边的非显示区域200。非显示区域200可以包括:在第二方向Y上相对设置的第一边框区域201和第二边框区域202,在第一方向X上相对设置的第三边框区域203和第四边框区域204,非显示区域200还可以包括:连接第一边框区域201和第三边框区域203的第一角部区域211、连接第一边框区域201和第四边框区域204的第二角部区域212、连接第二边框区域202和第三边框区域203的第三角部区域213、以及连接第二边框区域202和第四边框区域204的第四角部区域214,第一方向X为显示区域100中栅线的延伸方向,第二方向Y为显示区域100中数据线的延伸方向。例如,第一角部区域211至第四角部区域214为倒圆角的角部区域。例如,第一角部区域211可以包括:至少一个ESD保护单元30,第二角部区域212可以包括:至少一个ESD保护单元30。
在一种示例性实施例中,如图2所示,非显示区域100还可以包括:位于显示区域100第一方向X两侧的GOA单元50,GOA单元50与显示区域100中的栅线连接,GOA单元50与对应的ESD保护单元30中的静电放电保护线连接。如此,由于GOA单元50沿着显示区域100的外轮廓进行排布设置,通过将ESD保护单元30沿第一倾斜方向DR1倾斜设置,既可以减少ESD保护单元所占用的布线空间,又可以节省GOA单元与ESD保护单元之间连接线所占用的布线空间。从而,能够有效提升产品均一性和良率。此外,由于GOA单元50与对应的ESD保护单元30中的静电放电保护线连接,而ESD保护单元30被配置为释放静电放电保护线Signal上累积的静电电荷,因此,ESD保护单元30能够保护GOA单元避免ESD损伤。
在一种示例性实施例中,GOA单元50可以包括:多个级联的栅极移位寄存器单元,每一个栅极移位寄存器单元连接显示基板的显示区域中的至少一个栅线,被配置为向显示区域的至少一个栅线提供逐行移位的栅极驱动信号。或者,GOA单元50可以包括:多个级联的发光控制移位寄存器单元,每一个发光控制移位寄存器单元连接显示基板的显示区域中的至少一个栅线,被配置为向显示区域的至少一个栅线提供逐行移位的发光控制信号,即是用于输出发光控制信号的栅极驱动电路。在一些可能的实现方式中,移位寄存器单元的实现形式是多样的,这里,本公开实施例对此不做限定。
在一种示例性实施例中,如图2所示,以GOA单元50包括多个级联的栅极移位寄存器单元为例,可以设置多个级联的栅极移位寄存器单元沿着显示区域100的外轮廓进行排布设置,并设置最后一级的栅极移位寄存器单元的时钟信号线的延伸方向与第一倾斜方向DR1相同或近似相同。如此,通过设置GOA单元50中最后一级的栅极移位寄存器单元的时钟信号线的延伸方向与第一倾斜方向DR1相同,可以减小GOA单元50中最后一级的栅极移位寄存器单元在第一方向X和与第一方向X垂直的第二方向Y上所占用的布线空间,从而,能够减少GOA单元的布线空间,可以节省GOA单元与ESD保护单元之间连接线所占用的布线空间,可以避免侵占其它走线空间,能够有效提升产品均一性和良率。
例如,以最后一级的栅极移位寄存器单元的时钟信号线为折线为例,“最后一级的栅极移位寄存器单元的时钟信号线的延伸方向与第一倾斜方向DR1相同”可以是指:该时钟信号线的主体部分的延伸方向与第一倾斜方向DR1相同;或者,以最后一级的栅极移位寄存器单元的时钟信号线为曲线为例,“最后一级的栅极移位寄存器单元的时钟信号线的延伸方向与第一倾斜方向DR1相同”可以是指:该时钟信号线的切线方向与第一倾斜方向DR1相同。这里,本公开实施例对此不做限定。
例如,最后一级的栅极移位寄存器单元的时钟信号线可以包括:第一时钟信号线ESTV、第二时钟信号线ECB、第三时钟信号线ECK、第四时钟信号线GSTV、第五时钟信号线GCB、第六时钟信号线GCK、第七时钟信号线RSTV、第八时钟信号线RCB、或者第九时钟信号线RCK等信号线中的 至少一种。这里,本公开实施例对此不做限定。
在一种示例性实施例中,如图2所示,非显示区域100还可以包括:设置于GOA单元50和ESD保护单元30的远离显示区域100的一侧走线40,例如,走线40可以为第一电源线VSS。如此,通过合理设置ESD保护单元所占用的布线空间,可以避免ESD保护单元侵占第一电源线VSS的走线空间,从而,可以增大第一电源线VSS的线宽,能够降低第一电源线VSS的电流,降低第一电源线VSS灼伤的风险。
图3A为本公开示例性实施例中的ESD保护单元的第一种排布示意图,图3B为本公开示例性实施例中的ESD保护单元的第二种排布示意图。这里,图3A至图3B中的走线仅仅是一种示例性说明,走线的数量并不代表实际数量,走线的形状并不代表实际形状。其中,图3A和图3B中是以显示基板中的一个ESD保护单元,ESD保护单元包括4个串联的晶体管、静电放电保护线Signal、第一电压信号线VGH和第二电压信号线VGL为例进行示意。图3A中以第一电压信号线VGH、第二电压信号线VGL和静电放电保护线Signal均包括:第一走线和第二走线为例进行示意。图3B中是以以第一电压信号线VGH和第二电压信号线VGL均包括:第一走线和第二走线,静电放电保护线Signal包括:第一走线、第二走线和第三走线为例进行示意。
在一种示例性实施例中,如图3A和图3B所示,ESD保护单元30可以包括:第一电压信号线VGH、第二电压信号线VGL、静电放电保护线Signal和四个串联的晶体管,其中,每一个晶体管的第一极与栅极连接,第一电压信号线VGH与位于ESD保护单元一端的第1个晶体管连接,第二电压信号线VGL与位于ESD保护单元另一端的第4个晶体管连接,静电放电保护线Signal与第2个晶体管和第3个晶体管之间所形成的连接节点连接。
在一种示例性实施例中,如图3A和图3B所示,每一个晶体管的第一极与栅极连接,且四个晶体管沿第一倾斜方向DR1排布,第一倾斜方向DR1与第一方向X之间具有第一预设夹角,第一预设夹角可以约为10°至80°,第一方向X为显示区域中栅线的延伸方向。如此,通过将ESD保护单元30中的四个晶体管沿第一倾斜方向DR1倾斜设置,相比于将ESD保护单元30沿第一方向X水平设置,可以减小ESD保护单元在第一方向X和第二方向 Y上所占用的布线空间。从而,能够实现减少ESD保护单元的布线空间,避免挤占其它走线的布线空间,实现提升显示产品的均一性和良率。这里,第一预设夹角的度数与显示区域(AA区)的角部区域的外轮廓的形状相关,因此,可根据显示区域(AA区)的外轮廓的倒圆角的弧度进行设置,只要能够实现减少ESD保护单元的布线空间,避免挤占其它走线的布线空间即可。本公开实施例对此不做限定。
在一种示例性实施例中,静电放电保护线Signal、第一电压信号线VGH和第二电压信号线VGL中的至少一条,可以包括:第一走线和第二走线,第一走线与晶体管的第一极和第二极同层设置,第二走线与晶体管的栅极同层设置。例如,第一走线沿第二倾斜方向DR2延伸,第二走线沿第一倾斜方向DR1延伸,第二倾斜方向DR2与第一倾斜方向DR1垂直。
在一种示例性实施例中,如图3A和图3B所示,第一电压信号线VGH可以包括:第一连接线31-1和第一延伸线32-1。例如,第一连接线31-1,作为第一电压信号线VGH中的第一走线,可以为沿第二倾斜方向DR2延伸的直线。例如,第一延伸线32-1,作为第一电压信号线VGH中的第二走线,可以为沿第一倾斜方向DR1延伸的直线或者折线,第二倾斜方向DR2与第一倾斜方向DR1垂直。其中,图3A和图3B中是以第一延伸线32-1为折线为例进行示意,例如,如图3A和图3B所示,第一延伸线32-1的主体部可以沿第一倾斜方向DR1延伸,第一延伸线32-1的延伸部可以沿第一方向X延伸。或者,第一延伸线32-1的主体部可以沿第一倾斜方向DR1延伸,第一延伸线32-1的延伸部可以沿第二方向Y延伸。这里,本公开实施例对此不做限定。
在一种示例性实施例中,如图3A所示,静电放电保护线Signal可以包括:第二连接线31-2和第二延伸线32-2。例如,第二连接线31-2,作为静电放电保护线Signal中的第一走线,可以为沿第二倾斜方向DR2延伸的直线。例如,第二延伸线32-2,作为静电放电保护线Signal中的第二走线,可以为沿第一倾斜方向DR1延伸的直线或者折线,第二倾斜方向DR2与第一倾斜方向DR1垂直。其中,图3A中是以第二延伸线32-2为折线为例进行示意。例如,如图3A所示,第二延伸线32-2的主体部可以沿第一倾斜方向DR1 延伸,第二延伸线32-2的延伸部可以沿第一方向X延伸。或者,第二延伸线32-2的主体部可以沿第一倾斜方向DR1延伸,第二延伸线32-2的延伸部可以沿第二方向Y延伸。这里,本公开实施例对此不做限定。
在一种示例性实施例中,如图3A和图3B所示,第二电压信号线VGL可以包括:第三连接线31-3和第三延伸线32-3。例如,第三连接线31-3,作为第二电压信号线VGL中的第一走线,可以为沿第二倾斜方向DR2延伸的直线。例如,第三延伸线32-3,作为第二电压信号线VGL中的第二走线,可以为沿第一倾斜方向DR1延伸的直线或者折线,第二倾斜方向DR2与第一倾斜方向DR1垂直。其中,图3中是以第三延伸线32-3为折线为例进行示意,例如,第三延伸线32-3的主体部可以沿第一倾斜方向DR1延伸,第三延伸线32-3的延伸部可以沿第一方向X延伸。或者,第三延伸线32-3的主体部可以沿第一倾斜方向DR1延伸,第三延伸线32-3的延伸部可以沿第二方向Y延伸。这里,本公开实施例对此不做限定。
在一种示例性实施例中,静电放电保护线Signal、第一电压信号线VGH和第二电压信号线VGL中的至少一条,还可以包括:第三走线,第三走线所在膜层位于第一走线所在膜层和第二走线所在膜层之间。
在一种示例性实施例中,第三走线可以包括:直线和折线中的至少一种,直线沿第一倾斜方向DR1延伸,折线至少可以包括沿第一倾斜方向DR1延伸的走线部分。
在一种示例性实施例中,折线可以包括以下第一折线、第二折线和第三折线中的至少一种。例如,第一折线可以包括:依次连接的沿第一倾斜方向DR1延伸的第一子线和沿第一方向X延伸的第二子线。例如,第二折线可以包括:依次连接的沿第一倾斜方向DR1延伸的第三子线、沿第一方向X延伸的第四子线和沿第三倾斜方向DR3延伸的第五子线,第三倾斜方向与第一方向X之间具有第二预设夹角。例如,第二预设夹角与第一预设夹角可以不同。例如,第三折线可以包括:依次连接的沿第一倾斜方向DR1延伸的第六子线和沿第二方向Y延伸的第七子线,第二方向Y为显示区域中数据线的延伸方向。当然,还可以为其它折线,这里,本公开实施例对此不做限定。此外,第二预设夹角的度数与显示区域(AA区)的角部区域的外轮廓的形状 相关,因此,可根据显示区域(AA区)的外轮廓的倒圆角的弧度进行设置,只要能够实现减少ESD保护单元的布线空间,避免挤占其它走线的布线空间即可。本公开实施例对此不做限定。
在一种示例性实施例中,如图3B所示,静电放电保护线Signal可以包括:第二连接线31-2、第二延伸线32-2和第二引出线33-2。例如,第二连接线31-2,作为静电放电保护线Signal中的第一走线,可以为沿第二倾斜方向DR2延伸的直线。例如,第二延伸线32-2,作为静电放电保护线Signal中的第二走线,可以为沿第一倾斜方向DR1延伸的直线或者折线,第二倾斜方向DR2与第一倾斜方向DR1垂直。例如,第二引出线33-2,作为静电放电保护线Signal中的第三走线,可以为沿第一倾斜方向DR1延伸的直线或者折线,第二倾斜方向DR2与第一倾斜方向DR1垂直。例如,第二引出线33-2,作为静电放电保护线Signal中的第三走线,可以为第一折线、第二折线和第三折线中的至少一种。例如,如图3B所示,以第二引出线33-2为第二折线为例,可以包括:依次连接的沿第一倾斜方向DR1延伸的第三子线、沿第一方向X延伸的第四子线和沿第三倾斜方向DR3延伸的第五子线,第三倾斜方向DR3与第一方向X之间具有第二预设夹角。例如,第二预设夹角与第一预设夹角可以不同。其中,图3B中是以第二延伸线32-2为直线,第二引出线33-2为第二折线为例进行示意。这里,本公开实施例对此不做限定。
当然,静电放电保护线Signal、第一电压信号线VGH和第二电压信号线VGL三者的线形除了以上所列出的示例性实施方式之外,还可以为其它能够使ESD保护单元沿第一倾斜方向DR1排布的实施方式。这里,本公开实施例对此不做限定。
图4为本公开示例性实施例中的ESD保护单元的等效电路示意图。如图4所示,ESD保护单元可以包括:4个串联的晶体管(第一晶体管M1至第四晶体管M4)和3个信号线(第一电压信号线VGH、第二电压信号线VGL和静电放电保护线Signal)。
在一种示例性实施例中,如图4所示,第一晶体管M1的第一极和第一晶体管M1的栅极与第一电压信号线VGH连接,第一晶体管M1的第二极与第二晶体管M2的第一极和第二晶体管M2的栅极连接,第二晶体管M2的 第二极、第三晶体管M3的第一极和第三晶体管M3的栅极与静电放电保护信号线Signal连接,第三晶体管M3的第二极与第四晶体管M4的第一极和第四晶体管M4的栅极连接,第四晶体管M4的第二极与第二电压信号线VGL连接。如此,静电放电(ESD)保护单元可以将静电放电保护线Signal积累的静电电荷泄放。
在一种示例性实施例中,图4所示的静电放电保护单元的工作原理为:当静电放电保护线Signal聚集的正电荷满足第一条件时,静电放电保护线Signal会输出高电压信号,使得第一晶体管M1和第二晶体管M2导通,导致该高电压信号被第一电压信号线VGH拉低,从而,实现消除静电。而当静电放电保护线Signal聚集的负电荷满足第二条件时,静电放电保护线Signal会输出低电压信号,使得第三晶体管M3和第四晶体管M4导通,导致此低电压信号被第二电压信号线VGL拉高,从而,实现消除静电。其中,第一条件可以是指能够使ESD保护单元产生灼烧的最低正电荷量,第二条件可以是指能够使ESD保护单元产生灼烧的最低负电荷量。
在一种示例性实施例中,第一晶体管M1至第四晶体管M4可以是P型晶体管,或者可以是N型晶体管。这里,本公开实施例对此不做限定。
下面通过ESD保护单元的制备过程进行示例性说明。本公开所说的“图案化工艺”,对于金属材料、无机材料或透明导电材料,包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理,对于有机材料,包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种,涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种,刻蚀可以采用干刻和湿刻中的任意一种或多种,本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺,则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺,则在图案化工艺前称为“薄膜”,图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指,A和B通过同一次图案化工艺同时形成。
在一种示例性实施例中,在垂直于显示基板平面的方向上,ESD保护单 元30可以包括:在基底上依次设置的半导体层、第一导电层、第二导电层和第三导电层,半导体层可以包括:多个晶体管的有源层,第一导电层可以包括:多个晶体管的栅极以及静电放电保护线Signal、第一电压信号线VGH和第二电压信号线VGL中的至少一条所包括的第二走线,第二导电层可以包括:静电放电保护线Signal、第一电压信号线VGH和第二电压信号线VGL中的至少一条所包括的第三走线,第三导电层可以包括:多个晶体管的第一极、多个晶体管的第二极、以及静电放电保护线Signal、第一电压信号线VGH和第二电压信号线VGL中的至少一条所包括的第一走线。
图5A至图5D为图2所示的显示基板中ESD保护单元的制备过程的示意图,示意了显示基板的一个ESD保护单元的版图结构。下面以图3B所示ESD保护单元的结构作参考,结合图5A至图5D,对本公开示例性实施例中提供的显示基板中的ESD保护单元的制备过程进行说明。
在一种示例性实施例中,如图5A至图5D所示,ESD保护单元的制备过程可以包括如下操作:
(1)在基底上形成半导体层图案。
在一种示例性实施例中,在基底上形成半导体层图案可以包括:在基底上依次沉积第一绝缘薄膜和半导体薄膜,通过图案化工艺对半导体薄膜进行图案化,形成覆盖整个基底的第一绝缘层,以及设置在第一绝缘层上的半导体层。
在一种示例性实施例中,第一绝缘层可以称为缓冲(Buffer)层,半导体层可以称为有源(Active,ACT)层。
在一种示例性实施例中,如图5A所示,半导体层可以包括:每一个ESD保护单元中的第一有源层61、第二有源层71、第三有源层81和第四有源层91,其中,第一有源层61作为第一晶体管M1的有源层,第二有源层71作为第二晶体管M2的有源层,第三有源层81作为第三晶体管M3的有源层,第四有源层91作为第四晶体管M4的有源层。
在一种示例性实施例中,如图5A所示,第一有源层61、第二有源层71、第三有源层81和第四有源层91沿着第一倾斜方向DR1依次设置,在第二倾 斜方向DR2上平齐。如此,可以使得ESD单元沿第一倾斜方向DR1倾斜排布。
在一种示例性实施例中,如图5A所示,第一有源层61、第二有源层71、第三有源层81和第四有源层91的形状可以为沿第一倾斜方向DR1延伸的长条状。
在一种示例性实施例中,如图5A所示,第一晶体管M1的有源层61、第二晶体管M2的有源层71和第三晶体管M3的有源层81可以为相互连接的一体结构。
在一种示例性实施例中,基底可以是柔性基底,或者是刚性基底。
在一种示例性实施例中,半导体层可以采用金属氧化物材料制成。例如,金属氧化物材料可以包括但不限于:包含铟和锡的氧化物、包含钨和铟的氧化物、包含钨和铟和锌的氧化物、包含钛和铟的氧化物、包含钛和铟和锡的氧化物、包含铟和锌的氧化物、包含硅和铟和锡的氧化物、包含铟和镓和锌的氧化物等。例如,半导体层可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或聚噻吩等材料制成。例如,半导体层可以是单层、双层或者多层等。这里,本公开实施例对此不做限定。
在一种示例性实施例中,第一绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种,可以是单层、多层或复合层。
(2)形成第一导电层图案。
在一种示例性实施例中,如图5B所示,形成第一导电层图案可以包括:在形成前述图案的基底上依次沉积第二绝缘薄膜和第一金属薄膜,通过图案化工艺对第一金属薄膜进行图案化,形成覆盖半导体层图案的第二绝缘层,以及设置在第二绝缘层上的第一导电层。
在一种示例性实施例中,第二绝缘层可以称为栅极绝缘(GI)层,第一导电层可以称为第一栅金属(Gate1)层。
在一种示例性实施例中,如图5B所示,第一导电层可以包括:每一个 ESD保护单元的第一栅电极62、第二栅电极72、第三栅电极82和第四栅电极92,还可以包括:第一延伸线32-1、第二延伸线32-2和第三延伸线32-3。
在一种示例性实施例中,第一栅电极62作为第一晶体管M1的栅极,第一栅电极62在基底上的正投影与第一有源层61在基底上的正投影存在交叠区域。第二栅电极72作为第二晶体管M2的栅极,第二栅电极72在基底上的正投影与第二有源层71在基底上的正投影存在交叠区域。第三栅电极82作为第三晶体管M3的栅极,第三栅电极82在基底上的正投影与第一有源层81在基底上的正投影存在交叠区域。第四栅电极92作为第四晶体管M4的栅极,第四栅电极92在基底上的正投影与第一有源层91在基底上的正投影存在交叠区域。
在一种示例性实施例中,如图5B所示,第一栅电极62、第二栅电极72、第三栅电极82和第四栅电极92可以沿着第一倾斜方向DR1依次间隔设置,并且在第二倾斜方向DR2上平齐。
在一种示例性实施例中,第一延伸线32-1,作为第一电压信号线VGH中的第二走线,以便与后续形成的第一电压信号线VGH中的第一走线连接,形成第一电压信号线VGH。第二延伸线32-2,作为静电放电保护线Signal中的第二走线,以便与后续形成的静电放电保护线Signal中的第一走线连接,形成静电放电保护线Signal。第三延伸线32-3,作为第二电压信号线VGL中的第二走线,以便与后续形成的第二电压信号线VGL中的第一走线连接,形成第二电压信号线VGL。
在一种示例性实施例中,第二绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种,可以是单层、多层或复合层。
在一种示例性实施例中,第二导电层可以采用金属材料形成。例如,金属材料可以包括但不限于:银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种,或者上述列出的金属的合金材料,如铝钕合金(AlNd)或钼铌合金(MoNb)等。例如,第二导电层可以是单层结构,或者多层复合结构,如Mo/Cu/Mo等。
(3)形成第二导电层图案。
在一种示例性实施例中,如图5C所示,形成第二导电层图案可以包括:在形成前述图案的基底上依次沉积第三绝缘薄膜和第二金属薄膜,通过图案化工艺对第二金属薄膜进行图案化,形成覆盖第一导电层的第三绝缘层,以及设置在第三绝缘层上的第二导电层。
在一种示例性实施例中,第三绝缘薄膜可以称为层间介质(ILD)层,第二导电层可以称为第二栅金属(Gate2)层。
在一种示例性实施例中,如图5C所示,第三导电层可以包括:第二引出线33-2。第二引出线33-2,作为静电放电保护线Signal中的第三走线,通过过孔与静电放电保护线Signal中的第二走线连接,以便与后续形成的静电放电保护线Signal中的第一走线连接。
在一种示例性实施例中,第二引出线33-2,可以为第一折线、第二折线和第三折线中的至少一种。其中,在图5C中以第二引出线33-2为第二折线为例进行示意,如此,第二引出线33-2可以包括:依次连接的沿第一倾斜方向DR1延伸的第三子线、沿第一方向X延伸的第四子线和沿第三倾斜方向DR3延伸的第五子线。
(4)形成第三导电层图案。
在一种示例性实施例中,如图5D所示,形成第三导电层图案可以包括:在形成前述图案的基底上依次沉积第四绝缘薄膜和第三金属薄膜,通过图案化工艺对第三金属薄膜进行图案化,形成覆盖第二导电层的第四绝缘层,以及设置在第四绝缘层上的第三导电层。
在一种示例性实施例中,第四绝缘薄膜可以称为层间介质(ILD)层,第三导电层可以称为第二栅金属(Gate2)层。
在一种示例性实施例中,如图5D所示,第三导电层可以包括:第一连接线31-1、第二连接线31-2、第三连接线31-3、第一连接电极63、第二连接电极73、第三连接电极83、和第四连接电极93。
在一种示例性实施例中,如图5D所示,第一连接线31-1,作为第一电压信号线VGH中的第一走线,沿第二倾斜方向DR2延伸,如此,第一连接线31-1通过过孔与第一延伸线32-1连接,可以形成第一电压信号线VGH。
在一种示例性实施例中,如图5D所示,第二连接线31-2,作为静电放电保护线Signal中的第一走线,可以沿第二倾斜方向DR2延伸,如此,第二连接线31-2通过过孔与第二延伸线32-2连接,且第二延伸线32-2通过过孔与第二引出线33-2连接,可以形成静电放电保护线Signal。
在一种示例性实施例中,如图5D所示,第三连接线31-3,作为第二电压信号线VGL中的第一走线,可以沿第二倾斜方向DR2延伸,如此,第三连接线31-3通过过孔与第三延伸线32-3连接,可以形成第二电压信号线VGL。
在一种示例性实施例中,如图5D所示,第一连接电极63作为第一晶体管M1的第一极。第一连接电极63的形状可以为“L”型,第一连接电极63的一端与第一有源层61的第一区连接,第一连接电极63的另一端与第一栅电极62连接,以实现第一晶体管M1的栅极与第一晶体管M1的第一极连接。第一连接电极63与第一连接线31-1可以为相互连接的一体结构,可以实现第一晶体管M1的栅极、第一晶体管M1的第一极与第一电压信号线VGH连接。
在一种示例性实施例中,如图5D所示,第二连接电极73作为第一晶体管M1的第二极和第二晶体管M2的第一极。第二连接电极73的形状可以为“L”型,第二连接电极73的一端同时与第一有源层61的第二区和第二有源层71的第一区连接,第二连接电极73的另一端与第二栅电极72连接,以实现第一晶体管M1的第二极、第二晶体管M2的栅极以及第二晶体管M2的第一极连接,即实现第一晶体管M1与第二晶体管M2串联。
在一种示例性实施例中,如图5D所示,第三连接电极83作为第二晶体管M2的第二极和第三晶体管M3的第一极。第三连接电极83的形状可以为“L”型,第三连接电极83的一端与第二有源层71的第二区和第三有源层81的第一区连接,第三连接电极83的另一端与第三栅电极82连接,以实现第二晶体管M2的第二极、第三晶体管M3的栅极、以及第三晶体管M3的第一极连接。第三连接电极83与第二连接线31-2可以为相互连接的一体结构,可以实现第二晶体管M2的第二极、第三晶体管M3的栅极和第三晶体管M3的第一极与静电放电保护线Signal连接。
在一种示例性实施例中,如图5D所示,第四连接电极93作为第三晶体 管M3的第二极和第四晶体管M4的第一极。第四连接电极93的形状可以为“L”型,第四连接电极93的一端与第三有源层81的第二区和第四有源层91的第一区连接,第四连接电极93的另一端与第四栅电极92连接,以实现第三晶体管M3的第二极、第四晶体管M4的栅极、以及第四晶体管M4的第一极连接。
在一种示例性实施例中,如图5D所示,第三连接线31-3中与第四有源层91的第二区连接的一端,作为第四晶体管M4的第二极,以实现第四晶体管M4的第二极与第二电压信号线VGL连接。
在一种示例性实施例中,第三导电层可以采用金属材料形成。例如,金属材料可以包括但不限于:银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种,或者上述列出的金属的合金材料,如铝钕合金(AlNd)或钼铌合金(MoNb)等。第三导电层可以是单层结构,或者多层复合结构,如Mo/Cu/Mo等。
在一种示例性实施例中,显示区域100可以包括:以矩阵方式排布的多个像素单元P,多个像素单元P的至少一个可以包括:出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2和出射第三颜色光线的第三子像素P3,例如,第一子像素P1可以是红色(R)子像素,第二子像素P2可以是绿色(G)子像素,第三子像素P3可以是蓝色(B)子像素。或者,多个像素单元P的至少一个可以包括:出射不同颜色光线的第一子像素P1、第二子像素P2、第三子像素P3和第四子像素P4,例如,像素单元P可以包括四个子像素,如红色子像素、绿色子像素、蓝色子像素和白色子像素。这里,本公开实施例对此不做限定。
在一种示例性实施例中,每个子像素均可以包括:像素驱动电路和发光器件。其中,子像素中的像素驱动电路分别与栅线、数据线和发光信号线连接,子像素中的发光器件分别与所在子像素的像素驱动电路连接,像素驱动电路被配置为在栅线和发光信号线的控制下,接收数据线传输的数据电压,向发光器件输出相应的电流,发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中,像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、 6T1C或者7T1C结构等。这里,本公开实施例对此不做限定。
在一种示例性实施例中,像素单元中的多个子像素可以采用水平并列、竖直并列、X形、十字形或品字形等排布方式。例如,以像素单元包括三个子像素为例,三个子像素可以采用水平并列、竖直并列或品字形方式排列等。例如,以像素单元包括四个子像素为例,四个子像素可以采用水平并列、竖直并列或正方形(Square)方式排列等。这里,本公开实施例对此不做限定。
图6为图2所示显示基板中第一角部区域的排布示意图,其中,图6中的ESD保护单元30、走线、GOA单元50仅仅是一种示例性说明,ESD保护单元的数量并不代表实际数量,走线的数量并不代表实际数量,走线的形状不代表实际形状。
如图6所示,通过将ESD保护单元30中的多个串联的晶体管的排布方向与第一方向X呈第一预设角度进行设置,使得ESD保护单元30沿第一倾斜方向DR1倾斜设置,相比于将多个串联的晶体管的排布方向与第一方向X平行设置,可以减小ESD保护单元30在第一方向X上所占用的布线空间,可以减少ESD保护单元30所占用的布线空间,又可以节省ESD保护单元30与GOA单元50之间连接线所占用的布线空间,并且减小ESD保护单元30在第二方向Y上所占用的布线空间,可以避免ESD保护单元30挤占第一电源线VSS的布线空间,从而,可以增大第一电源线VSS的线宽。
如图6所示,以GOA单元50包括多个级联的栅极移位寄存器单元为例,除了ESD保护单元30沿第一倾斜方向DR1倾斜设置之外,还可以设置最后一级的栅极移位寄存器单元的时钟信号线的延伸方向与第一倾斜方向DR1相同或近似相同,使得最后一级的栅极移位寄存器单元可以沿第一倾斜方向DR1倾斜设置。如此,可以减小GOA单元50中最后一级的栅极移位寄存器单元在第一方向X和与第一方向X垂直的第二方向Y上所占用的布线空间,从而,能够减少GOA单元的布线空间,可以进一步节省GOA单元与ESD保护单元之间连接线所占用的布线空间,可以避免侵占其它走线空间,能够有效提升产品均一性和良率。
例如,相比于图1B中ESD保护单元30沿第一方向X排布,导致第一电源线VSS的线宽约为291.04微米,图6中ESD保护单元30沿第一倾斜方 向DR1倾斜设置,可以使得第一电源线VSS的线宽增大至约323.49微米,从而,能够降低第一电源线VSS的电流,降低第一电源线VSS灼伤的风险,实现提升产品的均一性和良率。
本公开实施例还提供了一种显示装置。显示装置可以包括:上述一个或多个示例性实施例中的显示基板。
在一种示例性实施例中,显示装置可以包括但不限于:薄膜晶体管液晶显示(Thin Film Transistor-Liquid Crystal Display,TFT-LCD)显示装置或者有源矩阵有机发光二极管(Active Matrix Organic Light Emitting Diode,AMOLED)显示装置等。这里,本公开实施例对此不不做限定。
在一种示例性实施例中,显示装置可以包括但不限于为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或者导航仪等任何具有显示功能的产品或部件。这里,本公开实施例对此不不做限定。
以上显示装置实施例的描述,与上述显示基板实施例的描述是类似的,具有同显示基板实施例相似的有益效果。对于本公开显示装置实施例中未披露的技术细节,本领域的技术人员请参照本公开显示基板实施例中的描述而理解,这里不再赘述。
虽然本公开所揭露的实施方式如上,但上述的内容仅为便于理解本公开而采用的实施方式,并非用以限定本公开。任何本公开所属领域内的技术人员,在不脱离本公开所揭露的精神和范围的前提下,可以在实施的形式及细节上进行任何的修改与变化,但本公开的专利保护范围,仍须以所附的权利要求书所界定的范围为准。
Claims (15)
- 一种显示基板,包括:显示区域和位于所述显示区域周边的非显示区域,所述非显示区域包括:至少一个静电放电ESD保护单元,每一个ESD保护单元包括:多个串联的晶体管,每一个晶体管的第一极与栅极连接,且多个晶体管沿第一倾斜方向排布,第一倾斜方向与第一方向之间具有第一预设夹角,第一预设夹角为10°至80°,第一方向为显示区域中栅线的延伸方向。
- 根据权利要求1所述的显示基板,其中,所述多个晶体管沿第一倾斜方向排布,包括:所述多个晶体管沿第一倾斜方向依次设置且在第二倾斜方向上平齐设置,第二倾斜方向与第一倾斜方向垂直。
- 根据权利要求1所述的显示基板,其中,所述多个晶体管沿第一倾斜方向排布,包括:每一个晶体管的有源层沿第一倾斜方向延伸,且每一个晶体管的第一极、第二极和栅极均沿第二倾斜方向延伸,第二倾斜方向与第一倾斜方向垂直。
- 根据权利要求3所述的显示基板,其中,在每一个ESD保护单元中,多个晶体管的有源层为相互连接的一体结构。
- 根据权利要求1至4任一项所述的显示基板,其中,所述ESD保护单元还包括:第一电压信号线、第二电压信号线和静电放电保护线,所述第一电压信号线与位于所述ESD保护单元一端的一个晶体管连接,所述第二电压信号线与位于所述ESD保护单元另一端的另一个晶体管连接,所述静电放电保护线与位于所述一个晶体管与所述另一个晶体管之间的任意一个连接节点连接。
- 根据权利要求5所述的显示基板,其中,所述静电放电保护线、第一电压信号线和第二电压信号线中的至少一条,包括:第一走线和第二走线,所述第一走线与晶体管的第一极和第二极同层设置,所述第二走线与晶体管的栅极同层设置,所述第一走线沿第二倾斜方向延伸,且所述第二走线沿第一倾斜方向延伸,第二倾斜方向与第一倾斜方向垂直。
- 根据权利要求6所述的显示基板,其中,所述静电放电保护线、第一 电压信号线和第二电压信号线中的至少一条,还包括:第三走线,所述第三走线所在膜层位于所述第一走线所在膜层和所述第二走线所在膜层之间。
- 根据权利要求7所述的显示基板,其中,所述第三走线包括:直线和折线中的至少一种,所述直线沿第一倾斜方向延伸,所述折线至少包括沿第一倾斜方向延伸的走线部分。
- 根据权利要求8所述的显示基板,其中,所述折线包括以下第一折线、第二折线和第三折线中的至少一种,第一折线包括:依次连接的沿第一倾斜方向延伸的第一子线和沿第一方向延伸的第二子线;第二折线包括:依次连接的沿第一倾斜方向延伸的第三子线、沿第一方向延伸的第四子线和沿第三倾斜方向延伸的第五子线,第三倾斜方向与第一方向之间具有第二预设夹角,第二预设夹角与第一预设夹角不同;第三折线包括:依次连接的沿第一倾斜方向延伸的第六子线和沿第二方向延伸的第七子线,第二方向为所述显示区域中数据线的延伸方向。
- 根据权利要求7所述的显示基板,其中,在垂直于显示基板平面的方向上,所述ESD保护单元包括:在基底上依次设置的半导体层、第一导电层、第二导电层和第三导电层,所述半导体层包括:多个晶体管的有源层,所述第一导电层包括:多个晶体管的栅极以及所述静电放电保护线、第一电压信号线和第二电压信号线中的至少一条所包括的第二走线,所述第二导电层包括:所述静电放电保护线、第一电压信号线和第二电压信号线中的至少一条所包括的第三走线,所述第三导电层包括:多个晶体管的第一极、多个晶体管的第二极、以及所述静电放电保护线、第一电压信号线和第二电压信号线中的至少一条所包括的第一走线。
- 根据权利要求5所述的显示基板,其中,多个晶体管包括:第一晶体管、第二晶体管、第三晶体管和第四晶体管,第一晶体管的第一极和第一晶体管栅极与所述第一电压信号线连接,第一晶体管的第二极、第二晶体管的第一极和第二晶体管的栅极与第一连接节点连接,第二晶体管的第二极、第三晶体管的第一极、第三晶体管的栅极和所述静电放电保护线与第二连接节点连接,第三晶体管的第二极、第四晶体管的第一极和第四晶体管的栅极 与第三连接节点连接,第四晶体管的第二极与第二电压信号线连接。
- 根据权利要求5所述的显示基板,其中,所述非显示区域包括:在第二方向上相对设置的第一边框区域和第二边框区域,在第一方向上相对设置的第三边框区域和第四边框区域,连接第一边框区域和第三边框区域的第一角部区域,连接第一边框区域和第四边框区域的第二角部区域,连接第二边框区域和第三边框区域的第三角部区域,以及连接第二边框区域和第四边框区域的第四角部区域,所述第一角部区域至第四角部区域中的至少一个为弧形的角部区域,所述ESD保护单元位于所述弧形的角部区域,所述第二方向为所述显示区域中数据线的延伸方向。
- 根据权利要求12所述的显示基板,其中,所述非显示区域还包括:第一电源线,所述第一电源线位于所述弧形的角部区域中的部分走线包括:沿第一倾斜方向延伸的第一子走线部分和沿第一方向延伸的第二子走线部分,所述第二子走线部分的宽度为300微米至343微米,宽度是指沿第二方向的尺寸特征。
- 根据权利要求12所述的显示基板,其中,所述非显示区域还包括:栅极驱动GOA单元,所述栅极驱动GOA单元与所述显示区域中的栅线连接,并与所述ESD保护单元中的静电放电保护线连接。
- 一种显示装置,包括:如权利要求1至14任一项所述的显示基板。
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CN111599847A (zh) * | 2020-05-29 | 2020-08-28 | 京东方科技集团股份有限公司 | 显示面板及其制造方法、显示装置 |
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JP2009116116A (ja) * | 2007-11-07 | 2009-05-28 | Sharp Corp | 液晶表示パネル及び液晶表示装置 |
CN109742128A (zh) * | 2019-01-28 | 2019-05-10 | 昆山国显光电有限公司 | 显示器及其显示面板 |
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