WO2023142698A1 - 阵列基板及其制备方法、显示面板及显示装置 - Google Patents

阵列基板及其制备方法、显示面板及显示装置 Download PDF

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Publication number
WO2023142698A1
WO2023142698A1 PCT/CN2022/137264 CN2022137264W WO2023142698A1 WO 2023142698 A1 WO2023142698 A1 WO 2023142698A1 CN 2022137264 W CN2022137264 W CN 2022137264W WO 2023142698 A1 WO2023142698 A1 WO 2023142698A1
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WIPO (PCT)
Prior art keywords
array substrate
groove
substrate
layer
glue
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PCT/CN2022/137264
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English (en)
French (fr)
Inventor
张炼
陈国朵
袁海江
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绵阳惠科光电科技有限公司
惠科股份有限公司
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Publication of WO2023142698A1 publication Critical patent/WO2023142698A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement

Definitions

  • the present application relates to the field of display technology, in particular to an array substrate and a manufacturing method thereof, a display panel and a display device.
  • Display technology has always been one of the important research directions in display panels.
  • OLB Outer Lead Bonding
  • ITO indium tin oxide
  • the present application discloses an array substrate, which enhances the fluidity of the sealant in the groove area, prevents the metal layer in the groove area from being corroded, and improves the quality of the array substrate.
  • the present application provides an array substrate, the array substrate has a display area and a non-display area, and the array substrate includes a substrate disposed in the non-display area, a metal layer, an intermediate layer, a conductive film, and a conductive adhesive , the metal layer is disposed on one side of the substrate, the intermediate layer is disposed on a side of the metal layer away from the substrate, the array substrate further includes a groove penetrating through the intermediate layer, and the conductive The thin film is arranged on the side of the middle layer away from the substrate and extends to the groove, and the conductive glue is arranged on the side of the conductive film in the groove away from the substrate and extends at least to the edge of the groove adjacent to the side of the display area.
  • the present application also provides a method for preparing an array substrate, and the method for preparing the array substrate includes:
  • the metal layer is disposed on one side of the substrate, and the intermediate layer is disposed on a side of the metal layer away from the substrate;
  • the conductive glue is disposed on the side of the conductive film in the groove facing away from the substrate, and the overflow of the conductive glue extends at least to the edge of the groove adjacent to the display area.
  • the present application also provides a display panel, the display panel includes an opposite substrate, a sealant, a liquid crystal layer, and the array substrate as described in the first aspect, and the opposite substrate and the array substrate pass through the
  • the frame glue is arranged opposite to the box, and the liquid crystal layer is arranged between the array substrate and the opposite substrate.
  • the present application further provides a display device, which includes a backlight module and the display panel as described in the third aspect, and the display panel is arranged on the light emitting side of the backlight module.
  • the conductive glue disposed in the groove extends at least to the edge of the groove adjacent to the side of the display area, so as to prevent the conductive glue from forming a step structure in the grooved area of the intermediate layer, so that the sealing
  • the fluidity of the glue is enhanced in the groove area, preventing the metal layer in the groove area from being corroded, and improving the quality of the array substrate.
  • FIG. 1 is a schematic partial top view of an array substrate provided by an embodiment of the present application.
  • Fig. 2 is a schematic cross-sectional view along line I-I in Fig. 1 .
  • FIG. 3 is a schematic flowchart of a method for preparing an array substrate provided in an embodiment of the present application.
  • FIG. 4 is a schematic cross-sectional view of a display panel provided by an embodiment of the present application.
  • FIG. 5 is a schematic cross-sectional view of a display device provided by an embodiment of the present application.
  • ACF Anaisotropic Conductive Film
  • the glue will overflow, and due to the size design of the slot, the overflow will be at the bottom of the slot, so that the overflow of ACF glue will form a step relative to the bottom of the slot, which will affect the flow of the subsequent sealant in the slot properties, resulting in the generation of air bubbles in the sealant, resulting in water vapor corrosion of the metal terminals.
  • FIG. 1 is a schematic partial top view of the array substrate provided by an embodiment of the present application
  • FIG. 2 is a schematic cross-sectional view along line I-I in FIG. 1
  • the array substrate 1 has a display area 1a and a non-display area 1b.
  • the array substrate 1 includes a substrate 11 disposed in the non-display area 1b, a metal layer 12 (ie, the above-mentioned metal terminals), an intermediate layer 13, and a conductive film.
  • the metal layer 12 is arranged on one side of the substrate 11, the intermediate layer 13 is arranged on the side of the metal layer 12 away from the substrate 11, and the array substrate 1 also includes a penetrating The groove 1c of the intermediate layer 13, the conductive thin film 14 is arranged on the side of the intermediate layer 13 away from the substrate 11, and extends to the groove 1c, the conductive glue 15 is arranged in the groove
  • the conductive thin film 14 in the groove 1c is on a side away from the substrate 11 and extends at least to the edge of the groove 1c on a side adjacent to the display area 1a.
  • the display area 1a is used as an area for displaying images on the array substrate 1, and the non-display area 1b is surrounded by the display area 1a, and the non-display area 1b is used for setting and driving A circuit for working pixels in the display area 1a.
  • the process of setting up the circuit which involves the chip pin bonding process on the chip-on-chip film 17, it is necessary to groove the intermediate layer 13 arranged in the non-display area 1b to form the groove 1c, so that the The metal layer 12 is at least partially exposed in the groove 1c, and the conductive film 14 is plated to protect the exposed part of the metal layer 12 .
  • the sealant is usually injected into the groove 1c from the side of the groove 1c adjacent to the display area 1a
  • the material of the conductive glue 15 can be ACF
  • the conductive glue 15 is arranged in the groove
  • the conductive thin film 14 in the groove 1c is away from the side of the substrate 11 and extends at least to the edge of the groove 1c adjacent to the side of the display area 1a, that is, the conductive glue 15 is on the side of the groove 1c.
  • the edge of the groove of the middle layer 13 is bonded, and the sealant can flow into the bottom of the groove 1c along the shape of the side wall of the groove 1c along the conductive glue 15 to avoid generation of air bubbles.
  • the length of the groove 1c may range from 850 ⁇ m to 1000 ⁇ m, and in this embodiment, the length of the groove 1 c is 928 ⁇ m. It can be understood that, in other possible implementation manners, the groove 1c may also have other lengths, which is not limited in the present application.
  • the conductive glue 15 disposed in the groove 1c extends at least to the edge of the groove 1c adjacent to the side of the display area 1a, so as to avoid the conductive glue 15
  • a stepped structure is formed in the grooved area of the intermediate layer 13, so that the fluidity of the sealant in the groove 1c area is enhanced, preventing the metal layer 12 in the groove 1c area from being corroded, and improving the array substrate 1 quality.
  • the conductive adhesive 15 includes a body 151, an overflowing adhesive 152 and an extension 153, the main body 151 is located at the bottom of the groove 1c, and the overflowing adhesive 152 is located at the bottom of the groove 1c.
  • the groove 1 c is adjacent to an edge of one side of the display area 1 a and is connected to the main body 151 through the extension portion 153 .
  • the extension part 153 extending from the body 151 and the overflowing glue 152 may overflow the Groove 1c.
  • the glue overflow 152 is used.
  • the glue overflow 152 is located at the edge of the groove 1c adjacent to the side of the display area 1a, and communicates with the body 151 through the extension 153 Connection, that is to say, the extension part 153 is attached to the grooved area of the middle layer 13, avoiding the formation of a step structure, so that the sealant can flow in better through the overflow glue 152 and the extension part 153 The bottom of the groove 1c where the body 151 is located.
  • the intermediate layer 13 includes an insulating layer 131, a passivation layer 132 and a planar layer 133, and the insulating layer 131 is disposed on the metal layer 12 away from the substrate.
  • the passivation layer 132 is disposed on the side of the insulating layer 131 away from the substrate 11
  • the flat layer 133 is disposed on the side of the passivation layer 132 away from the substrate 11, so
  • the orthographic projection of the flat layer 133 on the substrate 11 is at least partially overlapped with the orthographic projection of the overflow glue 152 on the substrate 11 .
  • the orthographic projection of the planar layer 133 on the substrate 11 at least partially covers the orthographic projection of the overflow glue 152 on the substrate 11 , in other words, the overflow glue 152 on the metal layer 12
  • the planar layer 133 exists in a region downward from the stacking direction of the substrate 11 . Since the intermediate layer 13 is grooved, and in the lamination direction, the planar layer 133 is higher than the insulating layer 131 and the passivation layer 132, then the insulating layer 131 and the passivation layer 132 The portion located on the inner sidewall of the groove 1c protrudes from the portion of the planar layer 133 located on the inner sidewall of the groove 1c.
  • the orthographic projection of the flat layer 133 on the substrate 11 at least partially covers the orthographic projection of the overflow glue 152 on the substrate 11, so that the extension 153 is completely attached to the flat layer 133,
  • the passivation layer 132 and the insulating layer 131 increase the fluidity of the sealant in the extension portion 153 .
  • the material of the passivation layer 132 may be polytetrafluoroethylene (PFA), and the material of the flat layer 133 may be polyaryl sulfide (PAS). It can be understood that, in other possible implementation manners, the materials of the passivation layer 132 and the flat layer 133 may also be other materials, which are not limited in this application.
  • PFA polytetrafluoroethylene
  • PAS polyaryl sulfide
  • the shape of the overflow glue 152 is any one of trapezoid, triangle and semicircle.
  • the shape of the overflow glue 152 refers to the outline in a cross-sectional view.
  • the shape of the overflow glue 152 is trapezoidal, and the right hypotenuse of the overflow glue 152 is roughly parallel to the side where the extension part 153 connects, so that the sealant can be smoothly Flows into the bottom of the groove 1c through the overflow glue 152 and the extension portion 153 .
  • the shape of the overflow glue 152 is a triangle, the right hypotenuse of the overflow glue 152 is roughly parallel to the side where the extension 153 connects; when the shape of the overflow glue 152 is a semicircle , the side of the glue overflow 152 connected with the extension portion 153 should be tangent to the glue overflow 152 .
  • the shape of the overflow glue 152 may also be other shapes, which are not limited in this application.
  • the array substrate 1 further includes a chip-on-chip film 17, and the array substrate 1 also has a bonding region 1d for bonding the chip-on film 17
  • the bonding area 1d In the bonding area 1d, the conductive glue 15 and the conductive film 14 are bonded to the metal layer 12, the bonding area 1d is located in the area where the groove 1c is located, and the bonding The region 1d is flush with the border of the region where the trench 1c is located adjacent to the display region 1a.
  • the non-display area 1b includes the binding area 1d, and the binding area 1d can be regarded as a part of the non-display area 1b.
  • the chip is usually disposed on the COF 17 , and the pins of the chip are bonded to the metal layer 12 at the bonding region 1 d through the COF 17 .
  • the conductive glue 15 is usually set corresponding to the bonding area 1d. In the prior art, the boundary of the bonding area 1d and the area where the groove 1c is located is usually not aligned, so the overflow glue 152 of the conductive glue 15 is easy to form
  • the step structure affects the fluidity of the sealant.
  • the bonding area 1d is flush with the boundary of the area where the trench 1c is adjacent to the display area 1a, and the conductive glue 15 disposed on the bonding area 1d
  • the overflow glue 152 is easy to extend to the edge of the side of the groove 1c adjacent to the display area 1a, so that the sealant injected from the side adjacent to the display area 1a preferably passes through the overflow glue 152 and the extension.
  • the portion 153 flows into the bottom of the groove 1c.
  • the array substrate 1 further includes optical glue 16, the optical glue 16 is disposed on the conductive film 14 away from the flat layer 133 one side, and extend into the trench 1c to cover the conductive glue 15 and the COF 17 .
  • the optical glue 16 is used as a sealant for the array substrate 1 , and the optical glue 16 has adhesiveness and light transmittance. It can be understood that under the double isolation protection of the optical adhesive 16 and the conductive adhesive 15, the effect of external water vapor is isolated, the chip pins on the metal layer 12 and the chip-on-chip film 17 are prevented from being corroded, and the improvement of the efficiency is improved. The quality of the array substrate 1 .
  • FIG. 3 is a schematic flowchart of the method for preparing an array substrate provided in an embodiment of the present application.
  • the method for preparing the array substrate includes: steps S301, S302, S303, S304, and S305.
  • steps S301, S302, S303, S304, and S305 are as follows.
  • the conductive glue 15 disposed in the groove 1c extends at least to the edge of the groove 1c adjacent to the side of the display area 1a, so as to avoid the conductive glue 15
  • a stepped structure is formed in the grooved area of the intermediate layer 13, so that the fluidity of the sealant in the groove 1c area is enhanced, preventing the metal layer 12 in the groove 1c area from being corroded, and improving the array substrate 1 quality.
  • the array substrate preparation method further includes step S306, and the detailed description of step S306 is as follows.
  • optical glue 16 please refer to the above description, which will not be repeated here. It can be understood that in this embodiment, under the double isolation protection of the optical adhesive 16 and the conductive adhesive 15, the effect of external water vapor is isolated, and the chip leads on the metal layer 12 and the chip-on-chip film 17 are avoided. The feet are corroded, which improves the quality of the array substrate 1 .
  • FIG. 4 is a schematic cross-sectional view of a display panel provided in an embodiment of the present application.
  • the display panel 2 includes an opposite substrate 21, a sealant 22, a liquid crystal layer 23, and the array substrate 1 as described above, and the opposite substrate 21 and the array substrate 1 are arranged in a box through the sealant 22,
  • the liquid crystal layer 23 is disposed between the array substrate 1 and the opposite substrate 21 .
  • the array substrate 1 please refer to the above description, which will not be repeated here.
  • the opposing substrate 21 and the array substrate 1 are arranged in a box through the sealant 22 as a process technology, so that the opposing substrate 21 and the array substrate 1 can be aligned in a fixed relative position. bit setting.
  • the opposite substrate 21 is used as a filter glass plate (Color Filter, CF) of the display panel 2 to perform light filtering.
  • at least part of the optical glue 16 is also used to support the opposite substrate 21 .
  • the sealant 22 prevents the optical glue 16 from entering the display area 1a.
  • FIG. 5 is a schematic cross-sectional view of a display device provided in an embodiment of the present application.
  • the display device 3 includes a backlight module 31 and the above-mentioned display panel 2 , and the display panel 2 is disposed on the light emitting side of the backlight module 31 .
  • the display panel 2 please refer to the above description, which will not be repeated here.
  • the light output direction of the backlight module 31 is shown by the dotted arrow in FIG. 5 , that is, the light output side of the backlight module 31 is the side adjacent to the display panel 2 .
  • the backlight module 31 is used to provide a light source for the display panel 2, so that the user can observe the light emitted from the light output side of the backlight module 31 and processed by the display panel 2, thereby realizing the described The display function of the display device 3 .
  • the display device 3 in the embodiment of the present application can be a display device 3 in a mobile phone, a smart phone, a tablet computer, an e-reader, a portable device when worn, a notebook computer, etc.
  • the data transfer server communicates, and the data transfer server can be an instant messaging server, an SNS (Social Networking Services, social network service) server, etc., and the implementation manner of the present application does not limit this.
  • SNS Social Networking Services, social network service

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Abstract

本申请提供一种阵列基板(1)及其制备方法、显示面板(2)，阵列基板(1)具有显示区(1a)及非显示区(1b)，阵列基板(1)包括设置于非显示区(1b)的基板(11)、金属层(12)、中间层(13)、导电薄膜(14)及导电胶(15)，金属层(12)设置于基板(11)的一侧，中间层(13)设置于金属层(12)背离基板(11)的一侧，阵列基板(1)还包括贯穿中间层(13)的沟槽(1c)，导电薄膜(14)设置于中间层(13)背离基板(11)的一侧，并延伸至沟槽(1c)，导电胶(15)设置于沟槽(1c)内的导电薄膜(14)背离基板(11)的一侧，并至少延伸至沟槽(1c)邻近显示区(1a)一侧的边缘。

Description

阵列基板及其制备方法、显示面板及显示装置
本申请要求于2022年01月27日提交中国专利局、申请号为202210102001.1、申请名称为“阵列基板及其制备方法、显示面板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其是涉及一种阵列基板及其制备方法、显示面板及显示装置。
背景技术
显示技术一直以来是显示面板中的重要研究方向之一。为了满足阵列基板的邦定及测试需求，需要在阵列基板的外引脚结合(Outer Lead Bonding，OLB)区域进行开槽，使阵列基板的金属部分露出，之后再镀上一层氧化铟锡(ITO)薄膜，保护裸露出的金属端子，防止被腐蚀。
相关技术中，在OLB区域的开槽内进行邦定时，容易造成水汽腐蚀，导致信赖性不良。
发明内容
本申请公开了一种阵列基板，使得密封胶在沟槽区域流动性增强，防止沟槽区域的金属层被腐蚀，改善阵列基板的品质。
第一方面，本申请提供一种阵列基板，所述阵列基板具有显示区及非显示区，所述阵列基板包括设置于所述非显示区的基板、金属层、中间层、导电薄膜及导电胶，所述金属层设置于所述基板的一侧，所述中间层设置于所述金属层背离所述基板的一侧，所述阵列基板还包括贯穿所述中间层的沟槽，所述导电薄膜设置于所述中间层背离所述基板的一侧，并延伸至所述沟槽，所述导电胶设置于所述沟槽内的所述导电薄膜背离所述基板的一侧，并至少延伸至所述沟槽邻近所述显示区一侧的边缘。
第二方面，本申请还提供一种阵列基板制备方法，所述阵列基板制备方法包括：
提供基板、金属层、中间层、导电薄膜及导电胶；
在所述基板的一侧设置所述金属层，所述金属层背离所述基板的一侧设置所述中间层；
开设沟槽，所述沟槽贯穿所述中间层；
在所述中间层背离所述基板的一侧设置所述导电薄膜，并延伸至所述沟槽；
在所述沟槽内的所述导电薄膜背离所述基板的一侧设置所述导电胶，并使所述导电胶的溢胶至少延伸至所述沟槽邻近所述显示区一侧的边缘。
第三方面，本申请还提供一种显示面板，所述显示面板包括对置基板、框胶、液晶层及如第一方面所述的阵列基板，所述对置基板和所述阵列基板通过所述框胶对盒设置，所述液晶层设在所述阵列基板和所述对置基板之间。
第四方面，本申请还提供了一种显示装置，所述显示装置包括背光模组及如第三方面所述的显示面板，所述显示面板设置于所述背光模组的出光侧。
设置于所述沟槽内的所述导电胶至少延伸至所述沟槽邻近所述显示区一侧的边缘，从而避免所述导电胶在所述中间层的开槽区域形成台阶结构，使得密封胶在所述沟槽区域流动性增强，防止所述沟槽区域的所述金属层被腐蚀，改善所述阵列基板的品质。
附图说明
为了更清楚的说明本申请实施方式中的技术方案，下面将对实施方式中所需要使用的附图作简单的介绍，显而易见的，下面描述中的附图仅仅是本申请的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本申请一实施方式提供的阵列基板局部俯视示意图。
图2为图1中沿I-I线的剖视示意图。
图3为本申请一实施方式提供的阵列基板制备方法流程示意图。
图4为本申请一实施方式提供的显示面板剖视示意图。
图5为本申请一实施方式提供的显示装置剖视示意图。
具体实施方式
下面将结合本申请实施方式中的附图，对本申请实施方式中的技术方案进行清楚、完整的描述，显然，所描述的实施方式仅是本申请一部分实施方式，而不是全部的实施方式。基于本申请中的实施方式，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施方式，都属于本申请保护的范围。
发明人在研究中发现，由于OLB区域的开槽长度较大(一般在1280μm-1350μm之间)，当在开槽内进行邦定时，热压头的高温及压力会使得ACF(Anisotropic Conductive Film)胶产生溢胶，且因开槽的尺寸设计，该溢胶会处于开槽的槽底，这样就使得ACF胶的溢胶处相对槽底形成台阶，进而影响后续密封胶在开槽内的流动性，从而导致密封胶内产生气泡，造成金属端子发生水汽腐蚀。
本申请提供一种阵列基板1，请一并参阅图1及图2，图1为本申请一实施方式提供的阵列基板局部俯视示意图；图2为图1中沿I-I线的剖视示意图。所述阵列基板1具有显示区1a及非显示区1b，所述阵列基板1包括设置于所述非显示区1b的基板11、金属层12(即上述的金属端子)、中间层13、导电薄膜14及导电胶15，所述金属层12设置于所述基板11的一侧，所述中间层13设置于所述金属层12背离所述基板11的一侧，所述阵列基板1还包括贯穿所述中间层13的沟槽1c，所述导电薄膜14设置于所述中间层13背离所述基板11的一侧，并延伸至所述沟槽1c，所述导电胶15设置于所述沟槽1c内的所述导电薄膜14背离所述基板11的一侧，并至少延伸至所述沟槽1c邻近所述显示区1a一侧的边缘。
需要说明的是，通常情况下，所述显示区1a作为所述阵列基板1显示画面的区域，所述非显示区1b围设于所述显示区1a，所述非显示区1b用于设置驱动所述显示区1a内像素工作的电路。在设置电路的过程中，涉及到覆晶薄膜17上芯片引脚邦定的工艺，需要对设置于所述非显示区1b的所述中间层13开槽，形成所述沟槽1c，使得所述金属层12至少部分裸露于所述沟槽1c，并镀上所述导电薄膜14以保护所述金属层12的裸露部分。
具体的，密封胶通常由所述沟槽1c邻近所述显示区1a的一侧注入所述沟槽1c内，所述导电胶15的材料可以是ACF，所述导电胶15设置于所述沟槽1c内的所述导电薄膜14背离所述基板11的一侧，并至少延伸至所述沟槽1c邻近所述显示区1a一侧的边缘，也就是说，所述导电胶15在所述中间层13的开槽边缘贴合，密封胶可以沿所述导电胶15顺着所述沟槽1c侧壁的形状较好的流入所述沟槽1c底部，避免产生气泡。
具体的，所述沟槽1c的长度范围可以是850μm-1000μm，在本实施方式中，所述沟槽1c的长度为928μm。可以理解的，在其他可能的实施方式中，所述沟槽1c还可以是其他长度， 本申请对此不加以限制。
可以理解的，在本实施方式中，设置于所述沟槽1c内的所述导电胶15至少延伸至所述沟槽1c邻近所述显示区1a一侧的边缘，从而避免所述导电胶15在所述中间层13的开槽区域形成台阶结构，使得密封胶在所述沟槽1c区域流动性增强，防止所述沟槽1c区域的所述金属层12被腐蚀，改善所述阵列基板1的品质。
在一种可能的实施方式中，请再次参阅图2，所述导电胶15包括本体151、溢胶152及延伸部153，所述本体151位于所述沟槽1c底部，所述溢胶152位于所述沟槽1c邻近所述显示区1a一侧的边缘，并通过所述延伸部153与所述本体151相连接。
需要说明的是，在所述沟槽1c内设置所述导电胶15时，由于技术工艺原因，可能产生由所述本体151延伸而出的所述延伸部153及所述溢胶152溢出所述沟槽1c。本申请利用所述溢胶152，在本实施方式中，所述溢胶152位于所述沟槽1c邻近所述显示区1a一侧的边缘，并通过所述延伸部153与所述本体151相连接，也就是说，所述延伸部153贴合于所述中间层13的开槽区域，避免形成台阶结构，使得密封胶可经由所述溢胶152及所述延伸部153，较好的流入所述本体151所在的所述沟槽1c底部。
在一种可能的实施方式中，请再次参阅图2，所述中间层13包括绝缘层131、钝化层132及平坦层133，所述绝缘层131设置于所述金属层12背离所述基板11的一侧，所述钝化层132设置于所述绝缘层131背离所述基板11的一侧，所述平坦层133设置于所述钝化层132背离所述基板11的一侧，所述平坦层133在所述基板11上的正投影与所述溢胶152在所述基板11上的正投影至少部分重叠。
具体的，所述平坦层133在所述基板11上的正投影至少部分覆盖所述溢胶152在所述基板11上的正投影，换句话说，所述溢胶152在所述金属层12和所述基板11层叠方向向下的区域均存在所述平坦层133。由于在所述中间层13开槽，且在层叠方向上，所述平坦层133高于所述绝缘层131及所述钝化层132，那么，所述绝缘层131及所述钝化层132位于所述沟槽1c的内侧壁的部分凸出于所述平坦层133位于所述沟槽1c内侧壁的部分。因此，所述平坦层133在所述基板11上的正投影至少部分覆盖所述溢胶152在所述基板11上的正投影，使得所述延伸部153完全贴合于所述平坦层133、所述钝化层132及所述绝缘层131，增加了密封胶在所述延伸部153的流动性。
在本实施方式中，所述钝化层132的材料可以是聚四氟乙烯(PFA)，所述平坦层133的材料可以是聚芳基硫醚(PAS)。可以理解的，在其他可能的实施方式中，所述钝化层132和所述平坦层133的材料还可以是其他材料，本申请对此不加以限制。
在一种可能的实施方式中，所述溢胶152的形状为梯形、三角形、半圆形中的任意一种。
需要说明的是，所述溢胶152的形状是指在剖视图下的外形轮廓。在本实施方式中，如图2所示，所述溢胶152的形状为梯形，所述溢胶152的右斜边与所述延伸部153相接的一边大致平行，从而使得密封胶能够顺利经由所述溢胶152及所述延伸部153流入所述沟槽1c底部。同理，当所述溢胶152的形状为三角形时，所述溢胶152的右斜边与所述延伸部153相接的一边大致平行；当所述溢胶152的形状为半圆形时，所述溢胶152与所述延伸部153相接的一边应相切于所述溢胶152。
可以理解的，在其他可能的实施方式中，所述溢胶152的形状还可以是其他形状，本申请对此不加以限制。
在一种可能的实施方式中，请再次参阅图1及图2，所述阵列基1还包括覆晶薄膜17，所述阵列基板1还具有邦定区1d，用于将所述覆晶薄膜17在所述邦定区1d通过所述导电胶 15及所述导电薄膜14与所述金属层12邦定，所述邦定区1d位于所述沟槽1c所在区域内，且所述邦定区1d与所述沟槽1c所在区域邻近所述显示区1a一侧的边界平齐。
需要说明的是，所述非显示区1b包含所述邦定区1d，所述邦定区1d可以认为是所述非显示区1b的一部分。芯片通常设置于所述覆晶薄膜17上，芯片引脚通过所述覆晶薄膜17在所述邦定区1d与所述金属层12邦定。所述导电胶15通常对应所述邦定区1d设置，在现有技术中，邦定区1d与沟槽1c所在区域的边界通常是不对齐的，因此，导电胶15的溢胶152容易形成台阶结构，影响密封胶的流动性。
在本实施方式中，所述邦定区1d与所述沟槽1c所在区域邻近所述显示区1a一侧的边界平齐，设置于所述邦定区1d的所述导电胶15的所述溢胶152易于延伸至所述沟槽1c邻近所述显示区1a的一侧边缘，从而使得由邻近所述显示区1a一侧注入的密封胶较好的经由所述溢胶152及所述延伸部153流入所述沟槽1c底部。
在一种可能的实施方式中，请再次参阅图2，所述阵列基板1还包括光学胶16，所述光学胶16，所述光学胶16设置于所述导电薄膜14背离所述平坦层133的一侧，且延伸至所述沟槽1c内覆盖所述导电胶15及所述覆晶薄膜17。
在本实施方式中，所述光学胶16作为所述阵列基板1的密封胶，所述光学胶16具有粘结性及透光性。可以理解的，在所述光学胶16和所述导电胶15的双重隔绝保护下，隔绝了外界水汽的作用，避免所述金属层12及覆晶薄膜17上的芯片引脚被腐蚀，提高了所述阵列基板1的品质。
本申请还提供一种阵列基板制备方法，请一并参阅图3，图3为本申请一实施方式提供的阵列基板制备方法流程示意图。所述阵列基板制备方法包括：步骤S301、S302、S303、S304、S305，步骤S301、S302、S303、S304、S305的详细说明如下。
S301，提供基板、金属层、中间层、导电薄膜及导电胶；
S302，在所述基板的一侧设置所述金属层，所述金属层背离所述基板的一侧设置所述中间层；
S303，开设沟槽，所述沟槽贯穿所述中间层；
S304，在所述中间层背离所述基板的一侧设置所述导电薄膜，并延伸至所述沟槽；
S305，在所述沟槽内的所述导电薄膜背离所述基板的一侧设置所述导电胶，并使所述导电胶的溢胶至少延伸至所述沟槽邻近所述显示区一侧的边缘。
具体的，所述基板11、所述金属层12、所述中间层13、所述导电薄膜14、所述导电胶15及所述沟槽1c请参阅上文描述，在此不再赘述。可以理解的，在本实施方式中，设置于所述沟槽1c内的所述导电胶15至少延伸至所述沟槽1c邻近所述显示区1a一侧的边缘，从而避免所述导电胶15在所述中间层13的开槽区域形成台阶结构，使得密封胶在所述沟槽1c区域流动性增强，防止所述沟槽1c区域的所述金属层12被腐蚀，改善所述阵列基板1的品质。
在一种可能的实施方式中，请再次参阅图3，所述阵列基板制备方法还包括步骤S306，步骤S306的详细说明如下。
S306，在所述导电薄膜背离所述中间层的一侧注入光学胶，且所述光学胶延伸至所述沟槽内覆盖所述导电胶。
具体的，所述光学胶16请参阅上文描述，在此不再赘述。可以理解的，在本实施方式中，在所述光学胶16和所述导电胶15的双重隔绝保护下，隔绝了外界水汽的作用，避免所述金属层12及覆晶薄膜17上的芯片引脚被腐蚀，提高了所述阵列基板1的品质。
本申请还提供一种显示面板2，请一并参阅图4，图4为本申请一实施方式提供的显示面板剖视示意图。所述显示面板2包括对置基板21、框胶22、液晶层23及如上文所述的阵列基板1，所述对置基板21和所述阵列基板1通过所述框胶22对盒设置，所述液晶层23设在所述阵列基板1和所述对置基板21之间。具体的，所述阵列基板1请参阅上文描述，在此不再赘述。
具体的，所述对置基板21和所述阵列基板1通过所述框胶22对盒设置为一种工艺技术，使得所述对置基板21与所述阵列基板1能够以固定的相对位置对位设置。所述对置基板21作为所述显示面板2的滤光玻璃板(Color Filter，CF)，起到滤光作用。在本实施方式中，所述光学胶16的至少部分还用于承载所述对置基板21。同时，所述框胶22避免所述光学胶16进入所述显示区1a。
本申请还提供了一种显示装置3，请一并参阅图5，图5为本申请一实施方式提供的显示装置剖视示意图。所述显示装置3包括背光模组31及如上文所述的显示面板2，所述显示面板2设置于所述背光模组31的出光侧。具体的，所述显示面板2请参阅上文描述，在此不再赘述。
具体的，所述背光模组31的出光方向请参阅图5中虚线箭头所示，即所述背光模组31的出光侧为邻近所述显示面板2的一侧。所述背光模组31用于为所述显示面板2提供光源，使得用户可以观察到由所述背光模组31出光侧出射，并经由所述显示面板2处理得到后的光线，从而实现所述显示装置3的显示功能。
需要说明的是，本申请实施方式中的所述显示装置3可以为手机、智能手机、平板电脑、电子阅读器、佩戴时便携设备、笔记本电脑等设备中的显示装置3，其可以通过互联网与数据转移服务器进行通信，所述数据转移服务器可以为即时通讯服务器、SNS(Social Networking Services，社会性网络服务)服务器等，本申请实施方式对此不加以限制。
本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施方式的说明只是用于帮助理解本申请的核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (16)

  1. 一种阵列基板，所述阵列基板具有显示区及非显示区，所述阵列基板包括设置于所述非显示区的基板、金属层、中间层、导电薄膜及导电胶，所述金属层设置于所述基板的一侧，所述中间层设置于所述金属层背离所述基板的一侧，所述阵列基板还包括贯穿所述中间层的沟槽，所述导电薄膜设置于所述中间层背离所述基板的一侧，并延伸至所述沟槽，所述导电胶设置于所述沟槽内的所述导电薄膜背离所述基板的一侧，并至少延伸至所述沟槽邻近所述显示区一侧的边缘。
  2. 如权利要求1所述的阵列基板，其中，所述非显示区围设于所述显示区，所述非显示区用于设置驱动所述显示区内像素工作的电路。
  3. 如权利要求2所述的阵列基板，其中，在所述非显示区的所述中间层开槽以形成所述沟槽，所述金属层至少部分裸露于所述沟槽，所述导电薄膜对应所述金属层裸露于所述沟槽的部分设置。
  4. 如权利要求1所述的阵列基板，其中，所述导电胶的材料为ACF。
  5. 如权利要求1所述的阵列基板，其中，所述沟槽的长度范围为850μm-1000μm。
  6. 如权利要求1所述的阵列基板，其中，所述导电胶包括本体、溢胶及延伸部，所述本体位于所述沟槽底部，所述溢胶位于所述沟槽邻近所述显示区一侧的边缘，并通过所述延伸部与所述本体相连接。
  7. 如权利要求6所述的阵列基板，其中，所述中间层包括绝缘层、钝化层及平坦层，所述绝缘层设置于所述金属层背离所述基板的一侧，所述钝化层设置于所述绝缘层背离所述基板的一侧，所述平坦层设置于所述钝化层背离所述基板的一侧，所述平坦层在所述基板上的正投影与所述溢胶在所述基板上的正投影至少部分重叠。
  8. 如权利要求7所述的阵列基板，其中，所述钝化层的材料为PFA，所述平坦层的材料为PAS。
  9. 如权利要求6所述的阵列基板，其中，所述溢胶的形状为梯形、三角形、半圆形中的任意一种。
  10. 如权利要求1所述的阵列基板，其中，所述阵列基板还包括覆晶薄膜，所述阵列基板还具有邦定区，用于将所述覆晶薄膜在所述邦定区通过所述导电胶及所述导电薄膜与所述金属层邦定，所述邦定区位于所述沟槽所在区域内，且所述邦定区与所述沟槽所在区域邻近所述显示区一侧的边界平齐。
  11. 如权利要求10所述的阵列基板，其中，所述阵列基板还包括光学胶，所述光学胶，所述光学胶设置于所述导电薄膜背离所述平坦层的一侧，且延伸至所述沟槽内覆盖所述导电胶及所述覆晶薄膜。
  12. 一种阵列基板制备方法，所述阵列基板制备方法包括：
    提供基板、金属层、中间层、导电薄膜及导电胶；
    在所述基板的一侧设置所述金属层，所述金属层背离所述基板的一侧设置所述中间层；
    开设沟槽，所述沟槽贯穿所述中间层；
    在所述中间层背离所述基板的一侧设置所述导电薄膜，并延伸至所述沟槽；
    在所述沟槽内的所述导电薄膜背离所述基板的一侧设置所述导电胶，并使所述导电胶的溢胶至少延伸至所述沟槽邻近所述显示区一侧的边缘。
  13. 如权利要求12所述的阵列基板制备方法，其中，所述阵列基板制备方法还包括：
    在所述导电薄膜背离所述中间层的一侧注入光学胶，且所述光学胶延伸至所述沟槽内覆 盖所述导电胶。
  14. 一种显示面板，所述显示面板包括对置基板、框胶、液晶层及阵列基板，所述对置基板和所述阵列基板通过所述框胶对盒设置，所述液晶层设在所述阵列基板和所述对置基板之间。
  15. 如权利要求14所述的显示面板，其中，所述阵列基板包括光学胶，所述光学胶的至少部分用于承载所述对置基板。
  16. 如权利要求15所述的显示面板，其中，所述框胶用于将所述光学胶阻隔于所述非显示区。
PCT/CN2022/137264 2022-01-27 2022-12-07 阵列基板及其制备方法、显示面板及显示装置 WO2023142698A1 (zh)

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