WO2023140046A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2023140046A1
WO2023140046A1 PCT/JP2022/047567 JP2022047567W WO2023140046A1 WO 2023140046 A1 WO2023140046 A1 WO 2023140046A1 JP 2022047567 W JP2022047567 W JP 2022047567W WO 2023140046 A1 WO2023140046 A1 WO 2023140046A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor device
resin
terminal portions
sealing resin
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2022/047567
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
瑛典 二井
宏明 青山
賢治 藤井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to DE112022006058.1T priority Critical patent/DE112022006058T5/de
Priority to JP2023575158A priority patent/JPWO2023140046A1/ja
Priority to CN202280089019.0A priority patent/CN118556287A/zh
Publication of WO2023140046A1 publication Critical patent/WO2023140046A1/ja
Priority to US18/777,108 priority patent/US20240379507A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H10W70/424—Cross-sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/481—Leadframes for devices being provided for in groups H10D8/00 - H10D48/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/811—Multiple chips on leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/222—Multilayered bumps, e.g. a coating on top and side surfaces of a bump core
    • H10W72/223—Multilayered bumps, e.g. a coating on top and side surfaces of a bump core characterised by the structure of the outermost layers, e.g. multilayered coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/245—Dispositions, e.g. layouts of outermost layers of multilayered bumps, e.g. bump coating being only on a part of a bump core
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/726—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

Definitions

  • the present disclosure relates to semiconductor devices.
  • Patent Document 1 discloses an example of a conventional semiconductor device.
  • the semiconductor device disclosed in the document includes leads, a semiconductor element and a sealing resin.
  • a lead has a plurality of terminal portions. The plurality of terminal portions are arranged along a direction perpendicular to the thickness direction of the lead.
  • the sealing resin covers part of the leads and the semiconductor element.
  • the sealing resin has a rectangular shape when viewed in the thickness direction.
  • the semiconductor element is mounted on the lead by flip-chip mounting.
  • the lead has a major surface facing one side in the thickness direction.
  • the semiconductor element has a plurality of electrodes provided on the side facing the main surface, and the plurality of electrodes are joined to the main surface of the lead via a joining layer made of solder or the like.
  • the plurality of terminal portions arranged along the direction orthogonal to the thickness direction of the lead are electrically connected to the internal circuit of the semiconductor element through the plurality of electrodes.
  • the semiconductor element is flip-chip mounted as described above, it is not possible to directly observe the joints to the leads of each of the plurality of electrodes, and there is no appropriate means for checking the joint state of the joints.
  • the outermost electrode in the arrangement direction of the plurality of terminal portions among the plurality of electrodes is closest to the corner of the package formed by the sealing resin.
  • the internal stress is maximized at the electrode joints closest to the corners of the package.
  • An object of the present disclosure is to provide a semiconductor device that is improved over conventional semiconductor devices.
  • an object of the present disclosure is to provide a semiconductor device suitable for improving the bonding reliability of a semiconductor element mounted on leads by flip-chip mounting.
  • a semiconductor device provided by one aspect of the present disclosure includes a lead having a main surface facing one side in the thickness direction, a semiconductor element, a sealing resin, and a first conductive portion.
  • the semiconductor element has a circuit portion, an element first surface facing the main surface in the thickness direction, and a plurality of first electrodes provided on the element first surface.
  • the plurality of first electrodes are connected to the main surface.
  • the sealing resin covers part of the leads and the semiconductor element.
  • the lead includes a plurality of first terminal portions arranged along a first direction orthogonal to the thickness direction, and a second terminal portion disposed closer to an end of the sealing resin in the first direction than the plurality of first terminal portions. Each of the plurality of first electrodes is electrically connected to the circuit section.
  • Each of the plurality of first terminal portions is electrically connected to the circuit portion via at least one of the plurality of first electrodes.
  • the first conductive portion is interposed between the second terminal portion and the element first surface, and is connected to both the second terminal portion and the element first surface.
  • the first conductive portion is insulated from the circuit portion.
  • FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure
  • FIG. FIG. 2 is a plan view of the semiconductor device shown in FIG. 1 (see through the sealing resin).
  • FIG. 3 is a plan view of the semiconductor device shown in FIG. 1 (semiconductor element and encapsulation resin are seen through).
  • 4 is a bottom view of the semiconductor device shown in FIG. 1.
  • FIG. 5 is a front view of the semiconductor device shown in FIG. 1.
  • FIG. 6 is a rear view of the semiconductor device shown in FIG. 1.
  • FIG. 7 is a right side view of the semiconductor device shown in FIG. 1.
  • FIG. 8 is a left side view of the semiconductor device shown in FIG. 1.
  • FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 3.
  • FIG. 10 is a cross-sectional view taken along line XX of FIG. 3.
  • FIG. 11 is a cross-sectional view along line XI-XI in FIG. 12 is a cross-sectional view along line XII-XII in FIG. 3.
  • FIG. 13 is a partially enlarged view of FIG. 11.
  • FIG. 14 is an enlarged cross-sectional view similar to FIG. 11, showing a state in which the semiconductor element is tilted with respect to the leads.
  • 15 is a plan view, similar to FIG. 3, showing a semiconductor device according to a modification of the first embodiment;
  • FIG. 16 is a cross-sectional view taken along line XVI--XVI of FIG. 15.
  • FIG. 17 is a plan view, similar to FIG. 3, showing a semiconductor device according to a second embodiment of the present disclosure;
  • a certain entity A is formed on a certain entity B
  • a certain entity A is formed on a certain entity B
  • include a certain entity A is formed directly on a certain entity B” and "a certain entity A is formed on a certain entity B while another entity is interposed between the entity A and the entity B", unless otherwise specified.
  • phrases “an entity A is placed on an entity B” and “an entity A is located on an entity B” include “an entity A is directly located on an entity B” and “an entity A is located on an entity B while another entity is interposed between the entity A and the entity B.”
  • an entity A is located on an entity B includes “an entity A is adjacent to an entity B and an entity A is located on an entity B” and “an entity A is located on an entity B while another entity is interposed between an entity A and an entity B.”
  • “an entity A overlaps an entity B in a certain direction” includes “an entity A that overlaps all of an entity B” and "an entity A that overlaps a part of an entity B”.
  • FIG. A semiconductor device A10 of this embodiment includes leads 1, a semiconductor element 3, a sealing resin 4, and a first conductive portion 6.
  • the lead 1 includes a main portion 10 , a plurality of first terminal portions 21 , two second terminal portions 22 , a terminal portion 25 , two terminal portions 26 , a plurality of terminal portions 27 and a plurality of terminal portions 28 .
  • the sealing resin 4 has a rectangular shape in plan view.
  • the package format of the semiconductor device A10 is QFN (Quad For Non-Lead Package).
  • a specific configuration of the semiconductor element 3 is not particularly limited, and the semiconductor element 3 is, for example, a flip-chip type LSI (Large Scale Integration).
  • the semiconductor element 3 is, for example, a flip-chip type LSI in which a switching circuit 321 and a control circuit 322 (details of which will be described later) are configured.
  • the switching circuit 321 converts DC power (voltage) into AC power (voltage).
  • the semiconductor device A10 is used, for example, as one element forming a circuit of a DC/DC converter.
  • FIG. 1 is a perspective view showing the semiconductor device A10.
  • FIG. 2 is a plan view showing the semiconductor device A10.
  • FIG. 3 is a plan view showing the semiconductor device A10.
  • FIG. 4 is a bottom view showing the semiconductor device A10.
  • FIG. 5 is a front view showing the semiconductor device A10.
  • FIG. 6 is a back view showing the semiconductor device A10.
  • FIG. 7 is a right side view showing the semiconductor device A10.
  • FIG. 8 is a left side view of the semiconductor device A10.
  • 9 is a cross-sectional view taken along line IX-IX in FIG. 3.
  • FIG. 10 is a cross-sectional view taken along line XX of FIG. 3.
  • FIG. 11 is a cross-sectional view along line XI-XI in FIG.
  • FIG. 12 is a cross-sectional view along line XII-XII in FIG. 3.
  • FIG. 13 is a partially enlarged view of FIG. 11.
  • FIG. 2 is transparent through the sealing resin 4 for convenience of understanding.
  • FIG. 3 shows the semiconductor element 3 and the sealing resin 4 through.
  • the semiconductor element 3 and the encapsulating resin 4 that are transmitted through are indicated by an imaginary line (chain double-dashed line).
  • the thickness direction of the main portion 10 is called "thickness direction z".
  • a direction perpendicular to the thickness direction z (vertical direction in FIG. 2) is called a “first direction x”.
  • a direction perpendicular to both the thickness direction z and the first direction x (horizontal direction in FIG. 2) is called a “second direction y”.
  • the semiconductor device A10 has a rectangular shape when viewed in the thickness direction z (planar view).
  • the leads 1 are all configured, for example, from the same lead frame.
  • a constituent material of the lead frame is not particularly limited, and is made of, for example, copper (Cu) or a copper alloy.
  • the main part 10 supports the semiconductor element 3, as shown in FIGS. At least part of the main portion 10 is covered with the sealing resin 4 .
  • main portion 10 has main surface 11 and back surface 12 .
  • the main surface 11 faces one side in the thickness direction z and faces the semiconductor element 3 .
  • the back surface 12 faces the side opposite to the main surface 11 (the other side in the thickness direction z).
  • Main surface 11 is covered with sealing resin 4 .
  • the rear surface 12 is exposed from the sealing resin 4 .
  • the main part 10 includes a first main part 101 , two second main parts 102 , a third main part 103 , a plurality of fourth main parts 104 and a plurality of fifth main parts 105 .
  • the principal surface 11 described above has a first principal surface 111 , a second principal surface 112 , a third principal surface 113 , a fourth principal surface 114 and a fifth principal surface 115 .
  • These first to fifth main surfaces 111 to 115 belong to any one of the first to fifth main portions 101 to 105 .
  • the back surface 12 has a first back surface 121 and a second back surface 122 . These first rear surface 121 and second rear surface 122 belong to either the first main portion 101 or the second main portion 102 .
  • the first main portion 101 is located in the center (or approximately the center) of the semiconductor device A10 in the second direction y and extends in the first direction x.
  • the first main section 101 is an input terminal to which DC power (voltage) to be converted in the semiconductor device A10 is input.
  • the first main portion 101 is a positive electrode (P terminal).
  • the first main portion 101 has a first main surface 111 and a first back surface 121. As shown in FIGS. The semiconductor element 3 is supported by the first principal surface 111 .
  • the first main portion 101 has a portion exposed from the sealing resin 4 on the other side in the thickness direction z, and the exposed portion includes the first rear surface 121 .
  • the two second main parts 102 are located on one side (right side in the drawing) in the second direction y of the semiconductor device A10 and are spaced apart in the second direction y.
  • the two second main portions 102 are adjacent to each other in the second direction y and each extend in the first direction x.
  • Each of the two second main sections 102 outputs AC power (voltage) that is power-converted by the switching circuit 321 configured in the semiconductor device 3 .
  • the second main portion 102 has a second main surface 112 and a second back surface 122.
  • the semiconductor element 3 is supported by the second principal surface 112 .
  • the second main portion 102 has a portion exposed from the sealing resin 4 on the other side in the thickness direction z, and the exposed portion includes the second rear surface 122 .
  • the third main portion 103 is located near the end portion of the semiconductor device A10 on one side in the second direction y (on the right side in the figure), and is arranged adjacent to one of the second main portions 102 on one side in the second direction y.
  • the third main portion 103 extends in the first direction x.
  • the third main section 103 is an input terminal to which DC power (voltage) to be converted in the semiconductor device A10 is input.
  • the third main portion 103 is a negative electrode (N terminal).
  • the third main portion 103 has a third main surface 113. As shown in FIGS. 3, 9 and 11, the third main portion 103 has a third main surface 113. As shown in FIGS. Semiconductor element 3 is supported by third main surface 113 .
  • the plurality of fourth main portions 104 are located on the other side (left side in the figure) in the second direction y relative to the first main portion 101 .
  • the plurality of fourth main portions 104 are arranged at intervals in the first direction x. Power (voltage) for driving control circuit 322 or an electric signal for transmission to control circuit 322 is input to each of fourth main sections 104 .
  • the fourth main portion 104 has a fourth main surface 114. As shown in FIGS. 3 and 9, the fourth main portion 104 has a fourth main surface 114. As shown in FIGS. The semiconductor element 3 is supported by the fourth principal surface 114 .
  • the plurality of fifth main parts 105 are located on the other side (left side in the figure) in the second direction y relative to the first main part 101 .
  • Some of the plurality of fifth main portions 105 are positioned on one side (upper side in the figure) in the first direction x in the semiconductor device A10.
  • the rest of the plurality of fifth main portions 105 are located on the other side (lower side in the figure) in the first direction x in the semiconductor device A10.
  • An electrical signal for transmission to control circuit 322 is input to each of fifth main sections 105, for example.
  • the fifth main portion 105 has a fifth main surface 115. As shown in FIGS. 3 and 12, the fifth main portion 105 has a fifth main surface 115. As shown in FIGS. The semiconductor element 3 is supported by the fifth main surface 115 .
  • the main surface 11 (first main surface 111 to fifth main surface 115) on which the semiconductor element 3 is supported may be plated with silver (Ag), for example.
  • back surface 12 (first back surface 121 and second back surface 122) exposed from sealing resin 4 may be plated with tin (Sn), for example.
  • tin plating for example, a plurality of metal plating layers of nickel (Ni), palladium (Pd), and gold (Au) may be used.
  • portions of the lead 1 (the main portion 10, the plurality of first terminal portions 21, the two second terminal portions 22, the terminal portion 25, the two terminal portions 26, the plurality of terminal portions 27 and the plurality of terminal portions 28) exposed from the sealing resin 4 are indicated by a plurality of dot regions.
  • the plurality of first terminal portions 21 are arranged along the first direction x.
  • the plurality of first terminal portions 21 are arranged at one side end (right end in the drawing) of the semiconductor device A10 (sealing resin 4) in the second direction y.
  • Each of the multiple first terminal portions 21 is connected to the third main portion 103 .
  • Each configuration of the plurality of first terminal portions 21 is the same. Regarding the configuration of the plurality of first terminal portions 21 in the semiconductor device A10, one of them will be described as a representative.
  • the first terminal portion 21 has a first mounting surface 211 and a first side surface 212.
  • the first mounting surface 211 faces the other side in the thickness direction z.
  • the first side surface 212 faces one side in the second direction y.
  • the first side surface 212 is connected to the first mounting surface 211 and is flush.
  • the first mounting surface 211 and the first side surface 212 are exposed from the sealing resin 4 .
  • the first mounting surface 211 and the first side surface 212 exposed from the sealing resin 4 may be plated with tin, for example.
  • tin plating for example, multiple metal platings in which nickel, palladium, and gold are laminated in this order may be employed.
  • the second terminal portion 22 is arranged at a position closer to the end of the sealing resin 4 in the first direction x than the plurality of first terminal portions 21 are.
  • the two second terminal portions 22 are arranged on one side and the other side in the first direction x with respect to the plurality of first terminal portions 21 .
  • the two second terminal portions 22 are arranged on one side in the second direction y and on both corners in the first direction x among the four corners of the rectangular sealing resin 4 when viewed in the thickness direction z.
  • the second terminal portion 22 has an extension portion 221, a second mounting surface 222, a second side surface 223 and a third side surface 224.
  • the extending portion 221 is a portion extending inward of the sealing resin 4 from the end of the sealing resin 4 in the first direction x and the end in the second direction y.
  • the first conductive portion 6 is connected to the extension portion 221 (second terminal portion 22).
  • the second mounting surface 222 faces the other side in the thickness direction z.
  • the second side surface 223 faces the same side as the first side surface 212 of the first terminal portion 21 and faces one side in the second direction y.
  • the third side surface 224 faces either one side in the first direction x or the other side in the first direction x.
  • the second side surface 223 is connected to the second mounting surface 222 and is flush.
  • the third side surface 224 is connected to both the second mounting surface 222 and the second side surface 223 and is flush.
  • the second mounting surface 222 , the second side surface 223 and the third side surface 224 are exposed from the sealing resin 4 .
  • the upper surface (the surface facing one side in the thickness direction z) of the extension portion 221 to which the first conductive portion 6 is connected may be plated with silver, for example.
  • the second mounting surface 222, the second side surface 223 and the third side surface 224 exposed from the sealing resin 4 may be plated with tin, for example.
  • tin plating for example, multiple metal platings in which nickel, palladium, and gold are laminated in this order may be employed.
  • the terminal portion 25 is arranged at one side end (upper end in the drawing) of the semiconductor device A10 in the first direction x.
  • the terminal portion 25 is connected to the first main portion 101 .
  • the terminal portion 25 has a mounting surface 251 and side surfaces 252.
  • the mounting surface 251 faces the other side in the thickness direction z.
  • the side surface 252 faces one side in the first direction x.
  • the side surface 252 is connected to the mounting surface 251 and is flush.
  • the mounting surface 251 and side surfaces 252 are exposed from the sealing resin 4 .
  • the two terminal portions 26 are arranged at one end (upper end in the figure) in the first direction x and the other end (lower end in the figure) in the first direction x of the semiconductor device A10.
  • the two terminal portions 26 are connected to the two second main portions 102 respectively.
  • the terminal portion 26 has a mounting surface 261 and side surfaces 262.
  • the mounting surface 261 faces the other side in the thickness direction z.
  • the side surface 262 faces either one side in the first direction x or the other side in the first direction x.
  • the side surface 262 is connected to the mounting surface 261 and is flush.
  • the mounting surface 261 and side surfaces 262 are exposed from the sealing resin 4 .
  • the plurality of terminal portions 27 are arranged at the other side end (the left end in the drawing) of the semiconductor device A10 in the second direction y.
  • Each of the multiple terminal portions 27 is connected to one of the multiple fourth main portions 104 .
  • the terminal portion 27 has a mounting surface 271 and side surfaces 272.
  • the mounting surface 271 faces the other side in the thickness direction z.
  • the side surface 272 faces the other side in the second direction y.
  • the side surface 272 is connected to the mounting surface 271 and is flush.
  • the mounting surface 271 and side surfaces 272 are exposed from the sealing resin 4 .
  • the plurality of terminal portions 28 are arranged at one side end (upper end in the figure) of the semiconductor device A10 in the first direction x and the other side end (lower end in the figure) of the first direction x.
  • Each of the multiple terminal portions 27 is connected to one of the multiple fifth main portions 105 .
  • the terminal portion 28 has a mounting surface 281 and side surfaces 282.
  • the mounting surface 281 faces the other side in the thickness direction z.
  • the side surface 282 faces either one side in the first direction x or the other side in the first direction x.
  • the side surface 282 is connected to the mounting surface 281 and is flush.
  • the mounting surface 281 and side surfaces 282 are exposed from the sealing resin 4 .
  • the portions exposed from the sealing resin 4 (mounting surfaces 251, 261, 271, 281 and side surfaces 252, 262, 272, 282) of the terminal portion 25, the two terminal portions 26, the plurality of terminal portions 27, and the plurality of terminal portions 28 may be plated with tin, for example.
  • tin plating for example, multiple metal platings in which nickel, palladium, and gold are laminated in this order may be employed.
  • the semiconductor element 3 has a semiconductor substrate 31 , a semiconductor layer 32 , a plurality of first electrodes 33 , a plurality of electrodes 34 and a plurality of electrodes 35 .
  • the semiconductor substrate 31 supports a semiconductor layer 32, a plurality of first electrodes 33, a plurality of electrodes 34 and a plurality of electrodes 35 thereunder.
  • the constituent material of the semiconductor substrate 31 is, for example, Si (silicon) or silicon carbide (SiC).
  • the semiconductor layer 32 is stacked on the semiconductor substrate 31 on the side facing the main surface 11 in the thickness direction z.
  • the semiconductor layer 32 has a device first surface 320 .
  • the element first surface 320 faces the other side in the thickness direction z and faces the main surface 11 in the thickness direction z.
  • the semiconductor layer 32 includes a plurality of types of p-type semiconductors and n-type semiconductors based on different amounts of doped elements.
  • a switching circuit 321 and a control circuit 322 electrically connected to the switching circuit 321 are formed in the semiconductor layer 32 .
  • the switching circuit 321 is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), or the like.
  • the switching circuit 321 is divided into two regions, a high voltage region (upper arm circuit) and a low voltage region (lower arm circuit). Each region is composed of one n-channel MOSFET.
  • the control circuit 322 includes a gate driver for driving the switching circuit 321, a bootstrap circuit corresponding to the high voltage region of the switching circuit 321, and the like, and performs control for driving the switching circuit 321 normally.
  • a wiring layer (not shown) is further formed in the semiconductor layer 32 . The wiring layer electrically connects the switching circuit 321 and the control circuit 322 to each other.
  • the switching circuit 321 and the control circuit 322 are examples of the "circuit section".
  • the semiconductor element 3 has a first wiring 325 provided on the semiconductor layer 32 (see FIGS. 2 and 3). 2 and 3, the route of the first wiring 325 is simplified and represented by dotted lines. The first wiring 325 is not conducting to any of the switching circuit 321, the control circuit 322 and the above wiring layers.
  • the plurality of first electrodes 33, the plurality of electrodes 34, and the plurality of electrodes 35 are provided on the element first surface 320, which is the side facing the main surface 11 (the first main surface 111 to the fifth main surface 115) in the thickness direction z.
  • the plurality of first electrodes 33 , the plurality of electrodes 34 and the plurality of electrodes 35 are in contact with the semiconductor layer 32 .
  • the plurality of first electrodes 33 are electrically connected to the switching circuit 321 of the semiconductor layer 32 .
  • Each of the multiple first electrodes 33 is connected to the third main portion 103 .
  • the plurality of first electrodes 33 are arranged along the first direction x.
  • the first electrode 33 is connected to the third main surface 113 of the third main portion 103 via a conductive bonding layer such as solder (see bonding layer 331 in FIG. 14).
  • Each of the plurality of first terminal portions 21 is connected to the third main portion 103 . Thereby, each of the plurality of first terminal portions 21 is electrically connected to the switching circuit 321 (circuit portion) via at least one of the plurality of first electrodes 33 .
  • the plurality of electrodes 34 are electrically connected to the switching circuit 321 of the semiconductor layer 32 .
  • Each of the plurality of electrodes 34 is connected to either the first main surface 111 of the first main portion 101 or the second main surface 112 of the two second main portions 102 .
  • the electrode 34 is connected to the first principal surface 111 (second principal surface 112) via a conductive bonding layer (not shown) such as solder, like the first electrode 33 .
  • a conductive bonding layer not shown
  • the plurality of electrodes 35 are electrically connected to the control circuit 322 of the semiconductor layer 32 .
  • Each of the plurality of electrodes 35 is connected to either the fourth main surface 114 of the plurality of fourth main portions 104 or the fifth main surface 115 of the plurality of fifth main portions 105 .
  • the electrode 35 is connected to the fourth main surface 114 (fifth main surface 115) through a conductive bonding layer (not shown) such as solder, similarly to the first electrode 33 .
  • the plurality of 104 and the plurality of fifth main sections 105 are electrically connected to the control circuit 322 .
  • the constituent material of the plurality of first electrodes 33, the plurality of electrodes 34, and the plurality of electrodes 35 includes, for example, copper.
  • the first conductive portion 6 is interposed between the extending portion 221 of the second terminal portion 22 and the element first surface 320 of the semiconductor element 3 .
  • the first conductive portion 6 is connected to both the extension portion 221 (second terminal portion 22 ) and the element first surface 320 .
  • the first conductive portion 6 is connected to the upper surface of the extending portion 221 (the surface facing one side in the thickness direction z) via a conductive bonding layer 61 such as solder.
  • two first conductive portions 6 are provided between each of the two second terminal portions 22 and the element first surface 320 of the semiconductor layer 32 .
  • Each of the two first conductive parts 6 overlaps the plurality of first electrodes 33 when viewed in the first direction x.
  • Each of the two first conductive parts 6 is not conducting to any of the switching circuit 321, the control circuit 322 and the wiring layer in the semiconductor layer 32. Therefore, the two first conductive parts 6 are insulated from the switching circuit 321 and the control circuit 322 (circuit part). On the other hand, each of the two first conductive parts 6 is electrically connected to the first wiring 325 in the semiconductor layer 32 .
  • the sealing resin 4 has a resin main surface 41, a resin back surface 42, two first resin side surfaces 431, 432, and two second resin side surfaces 433, 434, as shown in FIGS.
  • a constituent material of the sealing resin 4 is, for example, a black epoxy resin.
  • the resin main surface 41 faces the same side as the main surface 11 (the first main surface 111 to the fifth main surface 115) in the thickness direction z.
  • the resin rear surface 42 faces the side opposite to the resin main surface 41.
  • from the resin back surface 42 (sealing resin 4) the first back surface 121 of the first main portion 101, the second back surface 122 of each second main portion 102, the first mounting surface 211 of each first terminal portion 21, the second mounting surface 222 of each second terminal portion 22, the mounting surface 251 of each terminal portion 25, the mounting surface 261 of each terminal portion 26, and the mounting surface 271 of each terminal portion 27. and the mounting surface 281 of each terminal portion 28 is exposed.
  • the first resin side surface 431 is positioned at one end of the sealing resin 4 in the second direction y and faces one side in the second direction y.
  • the first resin side surface 431 is connected to both the resin main surface 41 and the resin back surface 42 .
  • the first side surface 212 is flush with the first resin side surface 431.
  • the second side surface 223 is flush with the first resin side surface 431.
  • the first resin side surface 432 is positioned on the other side end of the sealing resin 4 in the second direction y and faces the other side in the second direction y.
  • the first resin side surface 432 is connected to both the resin main surface 41 and the resin back surface 42 .
  • the side surface 272 is flush with the first resin side surface 432 in each of the plurality of terminal portions 27 arranged on the other side end in the second direction y in the semiconductor device A10.
  • the second resin side surface 433 is located at one end of the sealing resin 4 in the first direction x and faces one side in the first direction x.
  • the second resin side surface 433 is connected to both the resin main surface 41 and the resin back surface 42 .
  • the side surface 252, the side surface 262, and the side surface 282 are flush with the second resin side surface 433.
  • the third side surface 224 is flush with the second resin side surface 433.
  • the second resin side surface 434 is located on the other side end of the sealing resin 4 in the first direction x and faces the other side in the first direction x.
  • the second resin side surface 434 is connected to both the resin main surface 41 and the resin back surface 42 .
  • the side surface 262 and the side surface 282 are flush with the second resin side surface 434.
  • the third side surface 224 is flush with the second resin side surface 434.
  • the lead 1 includes a plurality of first terminal portions 21 and second terminal portions 22.
  • the plurality of first terminal portions 21 are arranged along the first direction x, and the second terminal portion 22 is arranged closer to the end of the sealing resin 4 in the first direction x than the plurality of first terminal portions 21.
  • the semiconductor element 3 has an element first surface 320 facing the main surface 11 of the lead 1 and a plurality of first electrodes 33 provided on the element first surface 320 .
  • the plurality of first electrodes 33 are connected to the third main surface 113 (main surface 11), and each of the plurality of first terminal portions 21 is electrically connected to the switching circuit 321 (circuit portion) of the semiconductor element 3 via at least one of the plurality of first electrodes 33.
  • the semiconductor device A10 further includes a first conductive portion 6 interposed between the second terminal portion 22 and the element first surface 320, and the first conductive portion 6 is connected to both the second terminal portion 22 and the element first surface 320.
  • the first conductive section 6 is insulated from the switching circuit 321 and the control circuit 322 (circuit section).
  • the first conductive portion 6 that does not conduct with the circuit portion that functions as the semiconductor element 3 is positioned closer to the corner of the package formed by the sealing resin 4 than the plurality of first electrodes 33 . Therefore, the joint portion of the first conductive portion 6 with the second terminal portion 22 has a larger internal stress than the joint portion of the plurality of first electrodes 33 with the third main portion 103 (the third main surface 113 ).
  • the first conductive portion 6 is insulated without being connected to the switching circuit 321 (circuit portion) that functions as the semiconductor element 3 , and does not provide an electrical conduction path for the semiconductor element 3 .
  • the internal stress of the joint portion is reduced by providing the first conductive portion 6 close to the corner portion of the sealing resin 4 .
  • the bonding reliability of the semiconductor element 3 mounted by flip-chip mounting can be improved.
  • two second terminal portions 22 are arranged on one side and the other side in the first direction x with respect to the plurality of first terminal portions 21 .
  • two first conductive portions 6 interposed between each of the two second terminal portions 22 and the element first surface 320 of the semiconductor layer 32 are provided. According to such a configuration, it is possible to reduce the internal stress of the joint portions of the first electrodes 33 located at both ends in the arrangement direction (first direction x) among the plurality of first electrodes 33 . This is more preferable for improving the bonding reliability of the semiconductor element 3 .
  • the plurality of first electrodes 33 are arranged along the first direction x. Each first conductive portion 6 overlaps the plurality of first electrodes 33 when viewed in the first direction x. According to such a configuration, it is possible to efficiently reduce the internal stress of the joint portions of the first electrodes 33 .
  • the semiconductor layer 32 semiconductor element 3
  • the semiconductor layer 32 has a first wiring 325 electrically connected to both of the two first conductive parts 6 .
  • FIG. 15 and 16 show a semiconductor device A11 according to a modification of the first embodiment.
  • FIG. 15 is a plan view showing the semiconductor device A11. 16 is a cross-sectional view taken along line XVI--XVI of FIG. 15.
  • FIG. 15 shows the semiconductor element 3 and the sealing resin 4 through. In the figure, the transmitted semiconductor element 3 and the sealing resin 4 are indicated by an imaginary line (chain double-dashed line).
  • a second terminal portion 23 is provided in place of the second terminal portion 22 of the above-described embodiment, and various modifications are made accordingly.
  • two second terminal portions 23 are arranged close to each other on one side in the first direction x with respect to the plurality of first terminal portions 21 .
  • two second terminal portions 23 are arranged close to each other separately from the above.
  • the second terminal portion 23 has an extension portion 231, a third mounting surface 232 and a fourth side surface 233.
  • the extending portion 231 is a portion extending inward of the sealing resin 4 from the end of the sealing resin 4 in the first direction x and the end in the second direction y.
  • the first conductive portion 6 is connected to the extension portion 231 (second terminal portion 23).
  • the third mounting surface 232 faces the other side in the thickness direction z.
  • the fourth side surface 233 faces either the first direction x or the second direction y.
  • the fourth side surface 233 of one of the second terminal portions 23 faces one side in the first direction x, and the fourth side surface 233 of the other second terminal portion 23 faces one side in the second direction y.
  • the fourth side surface 233 of one of the second terminal portions 23 faces the other side in the first direction x, and the fourth side surface 233 of the other second terminal portion 23 faces one side in the second direction y.
  • the fourth side surface 233 is connected to the third mounting surface 232 and is flush. The third mounting surface 232 and the fourth side surface 233 are exposed from the sealing resin 4 .
  • two first conductive portions 6 are interposed between each of the two second terminal portions 22 arranged on one side in the first direction x with respect to the plurality of first terminal portions 21 and the element first surface 320 of the semiconductor layer 32.
  • two first conductive portions 6 different from the above are provided between each of the two second terminal portions 22 arranged on the other side in the first direction x with respect to the plurality of first terminal portions 21 and the element first surface 320 of the semiconductor layer 32.
  • the semiconductor element 3 has a second wiring 326 provided in the semiconductor layer 32 instead of the first wiring 325 of the above embodiment.
  • the route of the second wiring 326 is simplified and represented by a dotted line.
  • the second wiring 326 is electrically connected to none of the switching circuit 321, the control circuit 322, and the above wiring layers.
  • second wirings 326 are provided at two locations, one side and the other side in the first direction x, corresponding to two second terminal portions 23 arranged on one side in the first direction x with respect to the plurality of first terminal portions 21 and two second terminal portions 23 arranged on the other side in the first direction x with respect to the plurality of first terminal portions 21, respectively.
  • Each first conductive portion 6 is not conducting to any of the switching circuit 321, the control circuit 322, and the wiring layer in the semiconductor layer 32. Therefore, each first conductive section 6 is insulated from the switching circuit 321 and the control circuit 322 (circuit section).
  • each of the two first conductive portions 6 arranged on one side in the first direction x with respect to the plurality of first electrodes 33 is electrically connected to one of the second wirings 326 in the semiconductor layer 32 .
  • Each of the two first conductive portions 6 arranged on the other side in the first direction x with respect to the plurality of first electrodes 33 is electrically connected to the other second wiring 326 in the semiconductor layer 32 .
  • the first conductive portion 6 that does not conduct with the circuit portion functioning as the semiconductor element 3 is positioned closer to the corner of the package formed by the sealing resin 4 than the plurality of first electrodes 33. Therefore, the internal stress is greater at the joint portion of the first conductive portion 6 with the second terminal portion 23 than at the joint portion with the third main portion 103 (the third main surface 113) of the plurality of first electrodes 33 .
  • the first conductive portion 6 is insulated without being connected to the switching circuit 321 (circuit portion) that functions as the semiconductor element 3 , and does not provide an electrical conduction path for the semiconductor element 3 .
  • the internal stress of the joint portion is reduced by providing the first conductive portion 6 close to the corner portion of the sealing resin 4 .
  • the bonding reliability of the semiconductor element 3 mounted by flip-chip mounting can be improved.
  • two second terminal portions 23 are arranged close to each other on one side of the plurality of first terminal portions 21 in the first direction x.
  • Two first conductive portions 6 are provided between each of the two second terminal portions 23 and the element first surface 320 of the semiconductor layer 32 .
  • the semiconductor layer 32 semiconductor element 3 ) has a second wiring 326 electrically connected to both of the two first conductive portions 6 . According to such a configuration, by electrically measuring the path of the two first conductive portions 6 and the second wiring 326 using the two second terminal portions 23 to which the two first conductive portions 6 are connected, the change in the joint state of the joint portion of the first conductive portion 6 can be detected as a change in the resistance value.
  • two second terminal portions 23 are arranged close to each other on the other side of the plurality of first terminal portions 21 in the first direction x. Further, two first conductive portions 6 different from the above are provided between the two second terminal portions 23 and the element first surface 320 of the semiconductor layer 32 .
  • the semiconductor layer 32 semiconductor element 3 ) has a second wiring 326 electrically connected to both of the two first conductive portions 6 . According to such a configuration, by electrically measuring the path of the two first conductive portions 6 and the second wiring 326 using the two second terminal portions 23 to which the two first conductive portions 6 are connected, the change in the joint state of the joint portion of the first conductive portion 6 can be detected as a change in the resistance value.
  • FIG. 17 shows a semiconductor device A20 according to the second embodiment of the present disclosure.
  • FIG. 17 is a plan view showing the semiconductor device A20.
  • FIG. 17 shows the semiconductor element 3 and the sealing resin 4 through.
  • the transmitted semiconductor element 3 and the sealing resin 4 are indicated by an imaginary line (chain double-dashed line).
  • a third wiring 327 is provided in place of the first wiring 325 provided in the semiconductor layer 32 (semiconductor element 3) of the above embodiment.
  • a route of the third wiring 327 is simplified and represented by a dotted line.
  • the third wiring 327 is electrically connected to both the first conductive portion 6 and one of the plurality of first electrodes 33 .
  • the third wirings 327 are provided at two locations, one side and the other side in the first direction x, corresponding to the two second terminal portions 22 provided on one side and the other side in the first direction x with respect to the plurality of first terminal portions 21, respectively.
  • the third wiring 327 provided on one side in the first direction x is electrically connected to the first conductive portion 6 arranged on one side in the first direction x and the first electrode 33 positioned on one end of the plurality of first electrodes 33 in the first direction x.
  • the third wiring 327 provided on the other side in the first direction x is electrically connected to the first conductive portion 6 arranged on the other side in the first direction x and the first electrode 33 positioned on the other side end in the first direction x among the plurality of first electrodes 33.
  • the first conductive portion 6 is positioned closer to the corner of the package formed by the sealing resin 4 than the plurality of first electrodes 33 are. Therefore, the joint portion of the first conductive portion 6 with the second terminal portion 22 has a larger internal stress than the joint portion of the plurality of first electrodes 33 with the third main portion 103 (the third main surface 113 ). Therefore, in the plurality of first electrodes 33 electrically connected to the switching circuit 321 (circuit portion), the internal stress of the joint portion is reduced by providing the first conductive portion 6 close to the corner portion of the sealing resin 4 . As a result, the bonding reliability of the semiconductor element 3 mounted by flip-chip mounting can be improved.
  • the two second terminal portions 22 are arranged on one side and the other side of the plurality of first terminal portions 21 in the first direction x. Also, two first conductive portions 6 interposed between each of the two second terminal portions 22 and the element first surface 320 of the semiconductor layer 32 are provided. According to such a configuration, it is possible to reduce the internal stress of the joint portions of the first electrodes 33 located at both ends in the arrangement direction (first direction x) among the plurality of first electrodes 33 . This is more preferable for improving the bonding reliability of the semiconductor element 3 .
  • the plurality of first electrodes 33 are arranged along the first direction x. Each first conductive portion 6 overlaps the plurality of first electrodes 33 when viewed in the first direction x. According to such a configuration, internal stress in the joints of the plurality of first electrodes 33 can be efficiently reduced.
  • the semiconductor layer 32 (semiconductor element 3) has a third wiring 327 electrically connected to both the first conductive portion 6 and one of the plurality of first electrodes 33.
  • the semiconductor layer 32 semiconductor element 3 has a third wiring 327 electrically connected to both the first conductive portion 6 and one of the plurality of first electrodes 33.
  • the semiconductor device according to the present disclosure is not limited to the above-described embodiments.
  • the specific configuration of each part of the semiconductor device according to the present disclosure can be changed in various ways.
  • the first terminal portion 21 (first side surface 212 ) may have a shape that protrudes outward from the sealing resin 4 . Further, a portion of the tip of the first terminal portion 21 in the second direction y and a portion of the surrounding sealing resin 4 may be removed so that the first side surface 212 is located inside the sealing resin 4 relative to the first resin side surface 431 when viewed in the thickness direction z.
  • the same modification as that for the first side surface 212 of the first terminal portion 21 described above can also be applied to the second side surface 223 and the third side surface 224 of the second terminal portion 22 of the first terminal portion 21 .
  • the second terminal portion 22 (the second side surface 223 and the third side surface 224 ) may have a shape that protrudes outward from the sealing resin 4 .
  • the second side surface 223 may be positioned inside the sealing resin 4 relative to the first resin side surface 431 when viewed in the thickness direction z
  • the third side surface 224 may be positioned inside the sealing resin 4 relative to the second resin side surface 433 (434) when viewed in the thickness direction z.
  • the second terminal portion 22 and the first conductive portion 6 connected thereto are arranged on one side of the sealing resin 4 in the second direction y and on both corners in the first direction x.
  • Appendix 1 a lead having a main surface facing one side in the thickness direction; a semiconductor element having a circuit portion, an element first surface facing the main surface in the thickness direction, and a plurality of first electrodes provided on the element first surface, wherein the plurality of first electrodes are connected to the main surface; a sealing resin covering a portion of the lead and the semiconductor element; and a first conductive part
  • the lead includes a plurality of first terminal portions arranged along a first direction perpendicular to the thickness direction, and a second terminal portion disposed closer to the end of the sealing resin in the first direction than the plurality of first terminal portions, each of the plurality of first electrodes is electrically connected to the circuit section; each of the plurality of first terminal portions is electrically connected to the circuit portion via at least one of the plurality of first electrodes; the first conductive portion is interposed between the second terminal portion and the element first surface and connected to both the second terminal portion and the element first surface;
  • the semiconductor device
  • the lead includes two second terminal portions arranged on one side and the other side in the first direction with respect to the plurality of first terminal portions;
  • the semiconductor device according to appendix 1 comprising two of the first conductive portions interposed between each of the two of the second terminal portions and the first surface of the element.
  • Appendix 3. The semiconductor device according to appendix 2, wherein the semiconductor element has a first wiring electrically connected to both of the two first conductive parts.
  • each of the plurality of first terminal portions has a first mounting surface facing the other side in the thickness direction and a first side surface facing the second direction orthogonal to both the thickness direction and the first direction; 4.
  • the semiconductor device according to any one of appendices 1 to 3, wherein the first mounting surface and the first side surface are exposed from the sealing resin.
  • Appendix 5. the sealing resin has a first resin side surface facing the second direction and positioned at an end in the second direction; 5.
  • the second terminal portion has a second mounting surface facing the other side in the thickness direction, a second side surface facing the second direction, and a third side surface facing the first direction, 6.
  • the semiconductor device according to appendix 5 wherein the second mounting surface, the second side surface, and the third side surface are exposed from the sealing resin.
  • the sealing resin has a second resin side surface located at the end in the first direction and facing the first direction, The second side surface is flush with the first resin side surface, or is located inside the sealing resin from the first resin side surface when viewed in the thickness direction, 7.
  • Appendix 8. The semiconductor device according to any one of Appendixes 1 to 7, wherein the plurality of first electrodes are arranged along the first direction.
  • Appendix 9. The semiconductor device according to appendix 8, wherein the first conductive portion overlaps with the plurality of first electrodes when viewed in the first direction.
  • the lead includes two second terminal portions arranged close to one side in the first direction with respect to the plurality of first terminal portions; comprising two first conductive portions interposed between each of the two second terminal portions and the first surface of the element,
  • the semiconductor device according to appendix 1 wherein the semiconductor element has a second wiring electrically connected to both of the two first conductive parts.
  • each of the plurality of first terminal portions has a first mounting surface facing the other side in the thickness direction and a first side surface facing the second direction orthogonal to both the thickness direction and the first direction; 11.
  • the semiconductor device according to appendix 10 wherein the first mounting surface and the first side surface are exposed from the sealing resin.
  • the sealing resin has a first resin side surface facing the second direction and positioned at an end in the second direction; 12.
  • Appendix 13 the second terminal portion has a third mounting surface facing the other side in the thickness direction and a fourth side surface facing the first direction or the second direction; 13.
  • the sealing resin has a second resin side surface located at the end in the first direction and facing the first direction, 13.
  • Appendix 13 wherein the fourth side surface is flush with the first resin side surface or the second resin side surface, or positioned inside the sealing resin from the first resin side surface or the second resin side surface when viewed in the thickness direction.
  • Appendix 15 a lead having a main surface facing one side in the thickness direction; a semiconductor element having a circuit portion, an element first surface facing the main surface in the thickness direction, and a plurality of first electrodes provided on the element first surface, wherein the plurality of first electrodes are connected to the main surface; a part of the lead and a sealing resin covering the semiconductor element,
  • the lead includes a plurality of first terminal portions arranged along a first direction perpendicular to the thickness direction, and a second terminal portion disposed closer to the end of the sealing resin in the first direction than the plurality of first terminal portions, each of the plurality of first electrodes is electrically connected to the circuit section; each of the plurality of first terminal portions is electrically connected to the circuit portion via at least one of the plurality of first electrodes; a second

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CN202280089019.0A CN118556287A (zh) 2022-01-20 2022-12-23 半导体器件
US18/777,108 US20240379507A1 (en) 2022-01-20 2024-07-18 Semiconductor device

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005347710A (ja) * 2004-06-07 2005-12-15 Sony Corp 表面実装型電子部品、プリント配線板及び実装基板
JP2010087395A (ja) * 2008-10-02 2010-04-15 Panasonic Corp 半導体装置
JP2016197636A (ja) * 2015-04-02 2016-11-24 株式会社デンソー モールドパッケージ
JP2017079215A (ja) * 2014-02-27 2017-04-27 パナソニックＩｐマネジメント株式会社 樹脂封止型半導体装置、およびその製造方法、ならびにその実装体
JP2021158317A (ja) * 2020-03-30 2021-10-07 ローム株式会社 半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005347710A (ja) * 2004-06-07 2005-12-15 Sony Corp 表面実装型電子部品、プリント配線板及び実装基板
JP2010087395A (ja) * 2008-10-02 2010-04-15 Panasonic Corp 半導体装置
JP2017079215A (ja) * 2014-02-27 2017-04-27 パナソニックＩｐマネジメント株式会社 樹脂封止型半導体装置、およびその製造方法、ならびにその実装体
JP2016197636A (ja) * 2015-04-02 2016-11-24 株式会社デンソー モールドパッケージ
JP2021158317A (ja) * 2020-03-30 2021-10-07 ローム株式会社 半導体装置

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