DE112022006058T5 - Halbleitervorrichtung - Google Patents

Halbleitervorrichtung Download PDF

Info

Publication number
DE112022006058T5
DE112022006058T5 DE112022006058.1T DE112022006058T DE112022006058T5 DE 112022006058 T5 DE112022006058 T5 DE 112022006058T5 DE 112022006058 T DE112022006058 T DE 112022006058T DE 112022006058 T5 DE112022006058 T5 DE 112022006058T5
Authority
DE
Germany
Prior art keywords
terminal
semiconductor device
regions
resin
sealing resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE112022006058.1T
Other languages
German (de)
English (en)
Inventor
Akinori NII
Hiroaki Aoyama
Kenji Fujii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Publication of DE112022006058T5 publication Critical patent/DE112022006058T5/de
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H10W70/424—Cross-sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/481—Leadframes for devices being provided for in groups H10D8/00 - H10D48/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/811—Multiple chips on leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/222—Multilayered bumps, e.g. a coating on top and side surfaces of a bump core
    • H10W72/223—Multilayered bumps, e.g. a coating on top and side surfaces of a bump core characterised by the structure of the outermost layers, e.g. multilayered coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/245—Dispositions, e.g. layouts of outermost layers of multilayered bumps, e.g. bump coating being only on a part of a bump core
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/726—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
DE112022006058.1T 2022-01-20 2022-12-23 Halbleitervorrichtung Pending DE112022006058T5 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2022007110 2022-01-20
JP2022-007110 2022-03-31
PCT/JP2022/047567 WO2023140046A1 (ja) 2022-01-20 2022-12-23 半導体装置

Publications (1)

Publication Number Publication Date
DE112022006058T5 true DE112022006058T5 (de) 2025-03-06

Family

ID=87348609

Family Applications (1)

Application Number Title Priority Date Filing Date
DE112022006058.1T Pending DE112022006058T5 (de) 2022-01-20 2022-12-23 Halbleitervorrichtung

Country Status (5)

Country Link
US (1) US20240379507A1 (https=)
JP (1) JPWO2023140046A1 (https=)
CN (1) CN118556287A (https=)
DE (1) DE112022006058T5 (https=)
WO (1) WO2023140046A1 (https=)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005347710A (ja) * 2004-06-07 2005-12-15 Sony Corp 表面実装型電子部品、プリント配線板及び実装基板
JP2010087395A (ja) * 2008-10-02 2010-04-15 Panasonic Corp 半導体装置
JP2017079215A (ja) * 2014-02-27 2017-04-27 パナソニックＩｐマネジメント株式会社 樹脂封止型半導体装置、およびその製造方法、ならびにその実装体
JP2016197636A (ja) * 2015-04-02 2016-11-24 株式会社デンソー モールドパッケージ
JP2021158317A (ja) * 2020-03-30 2021-10-07 ローム株式会社 半導体装置

Also Published As

Publication number Publication date
US20240379507A1 (en) 2024-11-14
JPWO2023140046A1 (https=) 2023-07-27
WO2023140046A1 (ja) 2023-07-27
CN118556287A (zh) 2024-08-27

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Legal Events

Date Code Title Description
R012 Request for examination validly filed
R079 Amendment of ipc main class

Free format text: PREVIOUS MAIN CLASS: H01L0023500000

Ipc: H10W0072200000