WO2023139926A1 - 半導体装置および半導体装置の製造方法 - Google Patents

半導体装置および半導体装置の製造方法 Download PDF

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WO2023139926A1
WO2023139926A1 PCT/JP2022/043674 JP2022043674W WO2023139926A1 WO 2023139926 A1 WO2023139926 A1 WO 2023139926A1 JP 2022043674 W JP2022043674 W JP 2022043674W WO 2023139926 A1 WO2023139926 A1 WO 2023139926A1
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layer
semiconductor
insulating
wiring
electrode
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French (fr)
Japanese (ja)
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哲雄 牛膓
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Sony Semiconductor Solutions Corp
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Sony Semiconductor Solutions Corp
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Priority to JP2023575095A priority Critical patent/JPWO2023139926A1/ja
Priority to EP22922077.7A priority patent/EP4462472A4/en
Publication of WO2023139926A1 publication Critical patent/WO2023139926A1/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/809—Constructional details of image sensors of hybrid image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
    • H10F39/018—Manufacture or treatment of image sensors covered by group H10F39/12 of hybrid image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/811—Interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0234—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes that stop on pads or on electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0242—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0249—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/212—Top-view shapes or dispositions, e.g. top-view layouts of the vias
    • H10W20/2125—Top-view shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/802—Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias

Definitions

  • the present technology relates to a semiconductor device and a method for manufacturing a semiconductor device. Specifically, the present technology relates to a semiconductor device having a through hole provided in a semiconductor substrate and a method for manufacturing the semiconductor device.
  • through electrodes are sometimes formed in a semiconductor substrate on which a semiconductor device is formed on the front side, and electrodes are provided on the back side of the semiconductor substrate.
  • a semiconductor device in which such a through electrode is formed for example, a semiconductor device in which a first through electrode and a second through electrode are formed has been proposed.
  • the first through electrode penetrates the first semiconductor substrate and is connected to the wiring layer of the first semiconductor substrate.
  • the second through electrode penetrates the first semiconductor substrate and its wiring layer, and is connected to the wiring layer of the second semiconductor substrate laminated on the first semiconductor substrate (see, for example, Patent Document 1).
  • This technology was created in view of this situation, and aims to increase the thickness of the semiconductor substrate while suppressing the increase in overetching during the formation of through holes.
  • the present technology has been made to solve the above-described problems, and a first aspect thereof includes a semiconductor layer in which a semiconductor element is formed, an insulating layer in which the semiconductor layers are stacked, a semiconductor substrate in which the insulating layer is stacked, a wiring layer formed on the semiconductor layer, an insulating separation layer that penetrates the semiconductor layer to reach the insulating layer and insulates and separates a part of the semiconductor layer, a semiconductor that penetrates the semiconductor substrate, the insulating layer, and the semiconductor layer and is connected to the wiring layer.
  • a semiconductor device comprising: a through electrode surrounded by the insulating isolation layer at a layer penetrating position; and an insulating film extending through the semiconductor substrate to reach the insulating layer and positioned between the semiconductor substrate and the through electrode.
  • the through electrode may be insulated from the semiconductor layer by the insulating separation layer and the insulating layer, and may be insulated from the semiconductor substrate by the insulating film and the insulating layer. This brings about an effect that the through electrode is embedded in the semiconductor layer and the semiconductor substrate while insulating the through electrode from the semiconductor layer and the semiconductor substrate.
  • the first side surface may further include an embedded wiring connected to the through electrode and embedded in the semiconductor layer while being surrounded by the insulating separation layer.
  • the wiring area can be expanded without increasing the area of the semiconductor layer in which the semiconductor element is formed.
  • the first side surface may further include a capacitive electrode connected to the through electrode and embedded in the semiconductor layer while being surrounded by the insulating separation layer. This provides an effect of increasing the capacitance without increasing the area of the semiconductor layer in which the semiconductor element is formed.
  • a semiconductor chip having pixels formed on a semiconductor substrate may be further provided, a logic circuit for processing pixel signals output from the pixels may be formed on the semiconductor layer, and the semiconductor chip may be stacked on the wiring layer. This brings about the effect of adding the image sensor function without increasing the area of the semiconductor layer in which the logic circuit is formed.
  • the material of the semiconductor layer and the semiconductor substrate may be Si. This brings about the effect of securing the etching selectivity of the insulating layer with respect to the semiconductor layer and the semiconductor substrate.
  • the material of the insulating layer may be SiO 2 . This brings about the effect of stopping the etching at the position of the insulating layer during the dry etching of the semiconductor substrate.
  • the second side surface includes the steps of: forming an insulating separation layer penetrating through a semiconductor layer laminated on a semiconductor substrate via an insulating layer and reaching the insulating layer; forming a semiconductor element in the semiconductor layer; forming a first wiring layer connected to the semiconductor element on the semiconductor layer; forming a first through hole in the semiconductor substrate that penetrates the semiconductor substrate and reaches the insulating layer; A method of manufacturing a semiconductor device, comprising the steps of: forming a second through hole in the insulating layer reaching the semiconductor layer through the insulating layer; forming a third through hole in the semiconductor layer reaching the first wiring layer through the first through hole and the second through hole; and embedding a through electrode surrounded by the insulating separation layer, the insulating layer and the insulating film in the first through hole, the second through hole and the third through hole.
  • the first through holes may be formed in the semiconductor substrate based on anisotropic etching
  • the second through holes may be formed in the insulating layer based on anisotropic etching through the first through holes
  • the third through holes may be formed in the semiconductor layer through isotropic etching through the first through holes and the second through holes.
  • the method may further include a step of bonding the second wiring layer of a semiconductor chip in which a second wiring layer is formed on a semiconductor substrate having pixels formed thereon to the first wiring layer, and a step of thinning the semiconductor substrate from the surface opposite to the surface on which the second wiring layer is formed.
  • FIG. 1 is a diagram showing a configuration example of a semiconductor device according to a first embodiment
  • FIG. 2 is an enlarged cross-sectional view showing a specific example of a wiring layer of the semiconductor device according to the first embodiment
  • FIG. 1A to 1D are first diagrams illustrating an example of a method for manufacturing a semiconductor device according to a first embodiment
  • FIG. 10 is a second diagram showing an example of the method for manufacturing the semiconductor device according to the first embodiment
  • FIG. 13 is a third diagram showing an example of the method for manufacturing the semiconductor device according to the first embodiment
  • FIG. 4 is a fourth diagram showing an example of the method for manufacturing the semiconductor device according to the first embodiment
  • FIG. 15 is a fifth diagram showing an example of the method for manufacturing the semiconductor device according to the first embodiment
  • FIG. 10 is a second diagram showing an example of the method for manufacturing the semiconductor device according to the first embodiment
  • FIG. 13 is a third diagram showing an example of the method for manufacturing the semiconductor device according to the first embodiment
  • FIG. 4 is a fourth
  • FIG. 10 is a diagram showing a configuration example of a semiconductor device according to a second embodiment
  • FIG. 11 is a first diagram showing an example of a method for manufacturing a semiconductor device according to a second embodiment
  • FIG. 10 is a second diagram showing an example of a method for manufacturing a semiconductor device according to a second embodiment
  • FIG. 13 is a third diagram showing an example of the method for manufacturing the semiconductor device according to the second embodiment
  • FIG. 10 is a fourth diagram showing an example of the method of manufacturing the semiconductor device according to the second embodiment
  • FIG. 15 is a fifth diagram showing an example of the method for manufacturing the semiconductor device according to the second embodiment
  • FIG. 10 is a sixth diagram showing an example of the method for manufacturing the semiconductor device according to the second embodiment
  • FIG. 11 is a first diagram showing an example of a method for manufacturing a semiconductor device according to a second embodiment
  • FIG. 10 is a second diagram showing an example of a method for manufacturing a semiconductor device according to a second embodiment
  • FIG. 13 is a third diagram showing
  • FIG. 11 is a seventh diagram showing an example of the method for manufacturing the semiconductor device according to the second embodiment
  • FIG. 13 is a diagram showing a configuration example of a semiconductor device according to a third embodiment
  • FIG. 11 is a diagram showing a configuration example of a semiconductor device according to a fourth embodiment
  • FIG. 11 is a diagram showing a configuration example of a semiconductor device according to a fifth embodiment
  • FIG. 11 is a diagram showing a configuration example of a semiconductor device according to a sixth embodiment
  • FIG. 14 is a diagram showing a configuration example of a semiconductor device according to a seventh embodiment
  • FIG. 12 is a diagram showing a configuration example of a semiconductor device according to an eighth embodiment
  • FIG. 20 is a diagram showing a configuration example of a semiconductor device according to a ninth embodiment; It is the 1st figure which shows an example of the manufacturing method of the semiconductor device which concerns on 9th Embodiment.
  • FIG. 20 is a second diagram illustrating an example of a method for manufacturing a semiconductor device according to a ninth embodiment;
  • FIG. 20 is a third diagram illustrating an example of a method for manufacturing a semiconductor device according to a ninth embodiment;
  • FIG. 20 is a fourth diagram showing an example of a method for manufacturing a semiconductor device according to the ninth embodiment;
  • FIG. 20 is a fifth diagram showing an example of a method of manufacturing a semiconductor device according to a ninth embodiment;
  • FIG. 20 is a sixth diagram showing an example of a method for manufacturing a semiconductor device according to a ninth embodiment;
  • First embodiment an example in which a through electrode is provided in an SOI (Silicon on Insulator) substrate provided with an isolation layer
  • Second embodiment an example in which through electrodes and embedded wiring are provided in an SOI substrate provided with an insulating isolation layer
  • Third Embodiment Example in which a through electrode and a buried wiring are provided in an SOI substrate provided with an insulating separation layer, and the through electrode and the projecting electrode are connected via a back surface wiring
  • FIG. 1 is a diagram showing a configuration example of a semiconductor device according to a first embodiment.
  • a is a cross-sectional view showing a configuration example of the semiconductor device 100 cut in the vertical direction
  • b is a rear view showing a configuration example of the semiconductor device 100.
  • FIG. 1 shows the wiring layers 117 and 152 in a simplified manner, and a specific example of the wiring layers 117 and 152 in FIG. 1 is shown in FIG.
  • a semiconductor device 100 includes semiconductor chips 101 and 102 .
  • a semiconductor chip 102 is stacked on the semiconductor chip 101 .
  • the semiconductor chips 101 and 102 can be joined together so that the wiring layers 117 and 152 face each other.
  • an image sensor in which pixels that perform photoelectric conversion are arranged in a matrix can be formed on the semiconductor chip 102 .
  • This image sensor may be a CMOS (Complementary Metal Oxide Semiconductor) image sensor or a CCD (Charge Coupled Device) image sensor.
  • this image sensor may be a back-illuminated image sensor.
  • a logic circuit for processing pixel signals output from pixels formed on the semiconductor chip 102 can be formed on the semiconductor chip 101 .
  • This processing may include, for example, gamma correction, white balance processing, sharpness processing, tone conversion processing, and the like.
  • the semiconductor chip 101 comprises a semiconductor substrate 111 , an intermediate insulating layer 112 and a semiconductor layer 113 .
  • An intermediate insulating layer 112 is laminated on the semiconductor substrate 111
  • a semiconductor layer 113 is laminated on the intermediate insulating layer 112 .
  • the SOI substrate 110 can be used as the laminated structure of the semiconductor substrate 111 , the intermediate insulating layer 112 and the semiconductor layer 113 .
  • the material of the semiconductor substrate 111 and the semiconductor layer 113 may be Si, and the material of the intermediate insulating layer 112 may be SiO2 .
  • the materials of the semiconductor substrate 111 and the semiconductor layer 113 may be compound semiconductors such as GaAs, SiC or GaN, for example.
  • the thickness of the semiconductor substrate 111 can be about 100 ⁇ m
  • the thickness of the intermediate insulating layer 112 can be about 0.1 ⁇ m
  • the thickness of the semiconductor layer 113 can be about 5 ⁇ m.
  • the intermediate insulating layer 112 is an example of the insulating layer described in the claims.
  • a semiconductor element is formed on the semiconductor layer 113 .
  • Semiconductor elements can include transistors used in logic circuits and the like.
  • a gate electrode 116 can be formed over the semiconductor layer 113 with a gate insulating film interposed therebetween.
  • the semiconductor layer 113 is formed with an insulating isolation layer 115 that isolates a part of the semiconductor layer 113 .
  • the insulating separation layer 115 can be formed so as to surround part of the semiconductor layer 113 .
  • the position of the semiconductor layer 113 surrounded by the insulating separation layer 115 can correspond to the formation position of the through electrode 132 .
  • the insulating isolation layer 115 may be an element isolation layer that isolates the semiconductor elements formed in the semiconductor layer 113, or may be provided separately from the element isolation layer that isolates the semiconductor elements formed in the semiconductor layer 113.
  • STI Shallow Trench Isolation
  • the insulating separation layer 115 penetrates the semiconductor layer 113 and reaches the intermediate insulating layer 112 . At this time, the insulating isolation layer 115 may come into contact with the intermediate insulating layer 112 , may enter the intermediate insulating layer 112 , or may penetrate the intermediate insulating layer 112 .
  • As an insulator used for the insulating isolation layer 115 for example, SiO 2 can be used.
  • the thickness of the insulating isolation layer 115 can be about 0.2 ⁇ m.
  • a wiring layer 117 is formed on the semiconductor layer 113 .
  • Pad electrodes 130 and wirings 131 and 181 to 185 are formed on the wiring layer 117, as shown in FIG.
  • the wirings 131 and 181 to 185 can constitute multilayer wirings. At this time, the wirings 131 and 181 to 185 can be connected between the layers through vias 186 .
  • the gate electrode 116 , the pad electrode 130 , the wirings 131 and 181 to 185 are embedded in the insulating layer 140 .
  • Pad electrode 130 is connected to wiring 131 , and wiring 131 is connected to gate electrode 116 .
  • the pad electrode 130 can be arranged at the connection position of the through electrode 132 .
  • the surface of the uppermost wiring 185 is exposed from the insulating layer 140 .
  • the material of the pad electrode 130 and the wirings 131 and 181 to 185 is Cu, for example.
  • a back surface insulating film 118 is formed on the back surface side of the semiconductor substrate 111 .
  • the material of the back insulating film 118 is, for example, SiO 2 .
  • the thickness of the back surface insulating film 118 can be about 0.1 ⁇ m.
  • a back wiring 133 is formed on the back insulating film 118 .
  • the material of the back wiring 133 is Cu, for example.
  • through holes 121 to 124 are formed in the rear insulating film 118, the semiconductor substrate 111, the intermediate insulating layer 112 and the semiconductor layer 113, respectively.
  • the through hole 124 is formed at a position surrounded by the insulating isolation layer 115 .
  • Side wall insulating films 114 are formed on the side walls of the through holes 121 and 122 in the back surface insulating film 118 and the semiconductor substrate 111 .
  • a material of the sidewall insulating film 114 is, for example, SiO 2 .
  • the sidewall insulating film 114 can have a thickness of about 0.1 ⁇ m. Note that the sidewall insulating film 114 is an example of the insulating film described in the claims.
  • through electrodes 132 are formed that penetrate through the rear insulating film 118, the semiconductor substrate 111, the intermediate insulating layer 112 and the semiconductor layer 113 and are connected to the wiring layer 117. Further, the through electrode 132 is connected to the back wiring 133 on the back side of the semiconductor substrate 111 . Here, the through electrode 132 can contact the pad electrode 130 in the wiring layer 117 . In addition, the through electrode 132 is surrounded by the intermediate insulating layer 112 , the side wall insulating film 114 and the insulating separation layer 115 .
  • the through electrode 132 is insulated from the semiconductor layer 113 by the intermediate insulating layer 112 and the insulating separation layer 115 , and is insulated from the semiconductor substrate 111 by the intermediate insulating layer 112 and the sidewall insulating film 114 .
  • the shape of the through electrode 132 can be cylindrical, for example.
  • the material of the through electrode 132 is Cu, for example.
  • the through electrode 132 and the back wiring 133 can be formed based on electrolytic plating.
  • a protective film 119 is formed on the back insulating film 118 .
  • the protective film 119 covers the back wiring 133 and is buried inside the through electrode 132 .
  • the material of the protective film 119 may be, for example, resin such as solder resist.
  • An opening 125 is formed in the protective film 119 at a position where the back wiring 133 is exposed.
  • a pad electrode 134 is embedded in the opening 125 and connected to the back wiring 133 .
  • the material of the pad electrode 134 is Cu, for example. Here, by using Cu as the material of the pad electrode 134, the pad electrode 134 can be embedded in the opening 125 based on electrolytic plating.
  • the semiconductor chip 102 includes a semiconductor substrate 151 on which semiconductor elements are formed.
  • the semiconductor element can include a photodiode used for a pixel and a pixel transistor for controlling readout of a signal from the pixel.
  • a gate electrode 156 can be formed over the semiconductor layer 151 with a gate insulating film interposed therebetween.
  • Si can be used for sensitivity in the visible region
  • InGaAs can be used for sensitivity in the infrared region.
  • a wiring layer 152 is formed on the semiconductor substrate 151 .
  • a wiring 161 is formed in the wiring layer 152 .
  • the wiring 161 may be, for example, a multilayer wiring including wirings 191 to 194 as shown in FIG. At this time, the wirings 191 to 194 can be connected between the layers through vias 196 .
  • the gate electrode 156 and the wirings 191 to 194 are embedded in the insulating layer 160 .
  • a wiring 191 is connected to the gate electrode 156 .
  • the surface of the lowermost wiring 195 is exposed from the insulating layer 160 .
  • the material of the wirings 181 to 185 is Cu, for example.
  • hybrid bonding between the wiring layers 117 and 152 can be used.
  • the wirings 185 and 195 are formed at positions facing each other.
  • each of the wirings 185 and 195 is configured so as to be recessed from the surfaces of the insulating layers 140 and 160 by several tens of nanometers.
  • the insulating layers 140 and 160 are surface-treated, the insulating layers 140 and 160 are brought into contact with each other so that the insulating layers 140 and 160 are connected to each other. At this time, a slight gap is formed between the wirings 185 and 195 .
  • the insulation layers 140 and 160 are heat-treated while being pressure-bonded to each other, the wirings 185 and 195 expand and the wirings 185 and 195 come into contact with each other.
  • a color filter 171 is formed for each pixel on the back side of the semiconductor substrate 151 .
  • the color filters 171 can form, for example, a Bayer array.
  • an on-chip lens 172 is formed for each pixel.
  • 3 to 7 are diagrams showing an example of the method for manufacturing the semiconductor device according to the first embodiment.
  • 3 to 7 are cross-sectional views taken at the same position as a in FIG. 1, and b in FIGS.
  • an isolation layer 115 is formed on the semiconductor layer 113 of the SOI substrate 110, and semiconductor elements such as transistors are formed on the semiconductor layer 113.
  • a wiring layer 117 is formed over the semiconductor layer 113 .
  • a semiconductor element such as a solid-state imaging element is formed on a semiconductor substrate 151 and a wiring layer 152 is formed on the semiconductor substrate 151 .
  • the wiring layers 117 and 152 are bonded to each other by a method such as hybrid bonding.
  • a back surface insulating film 118 is formed on the back surface side of the semiconductor substrate 111 by CVD (Chemical Vapor Deposition). Further, a resist pattern 173 provided with an opening 174 is formed on the back insulating film 118 by photolithography. The opening 174 can be arranged at the position of the pad electrode 130 when viewed from the back side of the SOI substrate 110 .
  • Anisotropic etching such as RIE (Reactive Ion Etching) can be used to form the through holes 121 and 122 .
  • the intermediate insulating layer 112 can be used as an etch stopper when etching the semiconductor substrate 111 . Note that the intermediate insulating layer 112 may be overetched.
  • the resist pattern 173 is removed.
  • the side wall insulating film 114 is formed by CVD, and the side wall insulating film 114 on the rear surface insulating film 118 is removed by etch back.
  • intermediate insulating layer 112 is etched using rear insulating film 118 having through hole 121 formed therein and side wall insulating film 114 as an etching mask, thereby forming through hole 123 in intermediate insulating layer 112 .
  • Anisotropic etching such as RIE can be used to form the through holes 123 .
  • the semiconductor layer 113 can be used as an etch stopper when etching the intermediate insulating layer 112 . Note that the semiconductor layer 113 may be over-etched.
  • the back insulating film 118 is made thicker than the intermediate insulating layer 112.
  • the semiconductor layer 113 is etched using the intermediate insulating layer 112 having the through holes 123 as an etching mask, thereby forming the through holes 124 in the semiconductor layer 113 .
  • isotropic etching can be used to form the through holes 124 .
  • the isotropic etching may be, for example, wet etching using a KOH solution as an etchant, or chemical dry etching using XeF 2 , CF 4 , NF 3 , CH 2 F 2 or the like as an etching gas.
  • the inner periphery of the through hole 124 can be covered with the insulating separation layer 115 .
  • the insulating isolation layer 115 and the wiring layer 117 can be used as an etch stopper.
  • the back surface of the pad electrode 130 is exposed by etching the insulating layer 140 on the back surface side of the pad electrode 130 through the through holes 121 to 124 .
  • anisotropic etching such as RIE can be used for etching the insulating layer 140 .
  • the through electrodes 132 connected to the pad electrodes 130 are formed in the through holes 121 to 124 and the rear wiring 133 is formed on the rear insulating film 118 .
  • a plated layer can be used for the through electrode 132 and the back wiring 133 .
  • the plating layer is formed by electroplating, a seed layer can be formed on the entire surface before electroplating, and the plating layer can be formed on the seed layer.
  • the through electrode 132 and the back wiring 133 can be formed.
  • Cu can be used as the material of the seed layer.
  • CVD using a monovalent Cu ⁇ -diketone complex and a reducing agent for reducing the monovalent Cu ⁇ -diketone complex as raw materials can be used.
  • a seed layer may be deposited by ALD (Atomic Layer Deposition) CVD.
  • a Cu seed layer may be formed by a sputtering method.
  • a protective film 119 is formed on the back insulating film 118 by a method such as coating so as to be embedded inside the through electrode 132 .
  • an opening 125 is formed in the protective film 119 by patterning the protective film 119 using a photolithographic technique and an etching technique.
  • a pad electrode 134 connected to the back wiring 133 is formed in the opening 125 .
  • Electroplating for example, can be used to form the pad electrodes 134 .
  • a seed layer can be formed on the entire surface before electroplating, and a plated layer can be formed on the seed layer.
  • the pad electrode 134 can be embedded in the opening 125 by removing the seed layer and plating layer on the protective film 119 by CMP.
  • the semiconductor substrate 151 is thinned from the back side by a method such as CMP. Then, a color filter 171 is formed on the back surface of the semiconductor substrate 151 , and an on-chip lens 172 is formed on the color filter 171 .
  • the surface on the back side of the semiconductor substrate 151 referred to here is the surface opposite to the surface on which the wiring layer 152 is formed.
  • the semiconductor chip 101 is provided with the through electrode 132 that penetrates the semiconductor substrate 111, the intermediate insulating layer 112 and the semiconductor layer 113 and is surrounded by the side wall insulating film 114, the intermediate insulating layer 112 and the insulating isolation layer 115.
  • the intermediate insulating layer 112 can be used as an etch stopper when forming the through hole 122, and overetching of the wiring layer 117 can be suppressed even when the semiconductor substrate 111 is thickened.
  • the through electrode 132 is surrounded by the insulating isolation layer 115 .
  • the through holes 124 can be formed in the semiconductor layer 113 by isotropic etching while suppressing side etching of the semiconductor layer 113, and damage during the formation of the through holes 124 can be suppressed.
  • the etching selectivity of the intermediate insulating layer 112 with respect to the semiconductor layer 113 and the semiconductor substrate 111 can be ensured. Therefore, the intermediate insulating layer 112 can be used as an etch stopper when forming the through hole 122 in the semiconductor substrate 111, and erosion of the insulating separation layer 115 and the intermediate insulating layer 112 can be suppressed when forming the through hole 124 in the semiconductor layer 113.
  • the intermediate insulating layer 112 can be used as an etch stopper when forming the through holes 122 in the semiconductor substrate 111 .
  • the semiconductor chip 102 is formed with an image sensor
  • the semiconductor chip 101 is formed with a logic circuit for processing pixel signals output from the image sensor.
  • the semiconductor device 100 to which the image sensor function is added can be configured without increasing the area of the semiconductor chip 101 .
  • semiconductor chip 101 is provided with through electrode 132 which penetrates semiconductor substrate 111, intermediate insulating layer 112 and semiconductor layer 113 and is surrounded by side wall insulating film 114, intermediate insulating layer 112 and insulating separation layer 115.
  • the semiconductor chip in addition to the semiconductor substrate, the intermediate insulating layer, and the through electrodes penetrating the semiconductor layer, the semiconductor chip is provided with embedded wiring embedded in the semiconductor layer.
  • FIG. 8 is a diagram showing a configuration example of a semiconductor device according to the second embodiment.
  • a is a cross-sectional view showing a configuration example of the semiconductor device 200 cut in the vertical direction
  • b in the figure is a rear view showing the configuration example of the semiconductor device 200
  • c is a cross-sectional view showing the configuration example of the semiconductor device 200 cut in the horizontal direction.
  • a in the same figure was cut at the position B1-B2 of b in the same figure.
  • c in the same figure was cut at the position of C1-C2 of a in the same figure.
  • a semiconductor device 200 includes a semiconductor chip 201 instead of the semiconductor chip 101 of the first embodiment described above.
  • Other configurations of the semiconductor device 200 of the second embodiment are the same as those of the semiconductor device 100 of the above-described first embodiment.
  • the semiconductor chip 101 comprises a semiconductor substrate 211 , an intermediate insulating layer 212 and a semiconductor layer 213 .
  • An intermediate insulating layer 212 is laminated on the semiconductor substrate 211
  • a semiconductor layer 213 is laminated on the intermediate insulating layer 212 .
  • the SOI substrate 210 can be used as the laminated structure of the semiconductor substrate 211 , the intermediate insulating layer 212 and the semiconductor layer 213 .
  • Semiconductor elements such as transistors are formed in the semiconductor layer 213 .
  • a gate electrode 216 can be formed over the semiconductor layer 213 with a gate insulating film interposed therebetween.
  • the semiconductor layer 213 is formed with an insulating separation layer 215 for insulating and separating a part of the semiconductor layer 213 .
  • the insulating separation layer 215 can be formed to surround part of the semiconductor layer 213 .
  • the position of the semiconductor layer 213 surrounded by the insulating isolation layer 215 can correspond to the formation position of the through electrode 232 and the embedded wiring 233 .
  • STI can be used for the insulating separation layer 215 .
  • the insulating separation layer 215 penetrates the semiconductor layer 213 and reaches the intermediate insulating layer 212 .
  • a wiring layer 217 is formed on the semiconductor layer 213 .
  • a pad electrode 230 and a wiring 231 are formed on the wiring layer 217 .
  • Pad electrode 230 and wiring 231 are embedded in insulating layer 240 .
  • Pad electrode 230 is connected to wiring 231 .
  • a back surface insulating film 218 is formed on the back surface side of the semiconductor substrate 211 .
  • through holes 221 to 224 are formed in the rear insulating film 218, the semiconductor substrate 211, the intermediate insulating layer 212 and the semiconductor layer 213, respectively.
  • a cavity 225 communicating with the through hole 224 is formed in the semiconductor layer 213 .
  • the through holes 224 and the cavities 225 are formed at positions surrounded by the insulating isolation layer 215 .
  • Side wall insulating films 214 are formed on the side walls of the through holes 221 and 222 in the back surface insulating film 218 and the semiconductor substrate 211 .
  • through electrodes 232 are formed that penetrate through the rear insulating film 218, the semiconductor substrate 211, the intermediate insulating layer 212 and the semiconductor layer 213 and are connected to the wiring layer 217.
  • the through electrode 232 can contact the pad electrode 230 in the wiring layer 217 .
  • An embedded wiring 233 connected to the through electrode 232 is formed in the cavity 225 .
  • the periphery of the through electrode 232 is surrounded by the side wall insulating film 214 .
  • the through electrodes 232 and the embedded wirings 233 are surrounded by an insulating isolation layer 215 .
  • the through electrode 232 is insulated from the semiconductor layer 213 by the intermediate insulating layer 212 and the insulating separation layer 215 , and is insulated from the semiconductor substrate 211 by the intermediate insulating layer 212 and the sidewall insulating film 214 .
  • the embedded wiring 233 is insulated from the semiconductor layer 213 by the insulating separation layer 215 and insulated from the semiconductor substrate 211 by the intermediate insulating layer 212 .
  • the embedded wiring 233 may be used as a power supply line or a signal line.
  • the material of the through electrode 232 and the embedded wiring 233 is Cu, for example.
  • the through electrode 232 and the embedded wiring 233 can be formed based on electrolytic plating.
  • a protective film 242 is formed on the back insulating film 218 .
  • the material of the protective film 242 may be, for example, SiO 2 or SiN.
  • An opening 243 is formed in the protective film 242 at a position where the through electrode 232 is exposed.
  • a pad electrode 241 is embedded in the opening 243 and connected to the through electrode 232 .
  • a projecting electrode 244 is formed on the pad electrode 241 .
  • the protruding electrodes 244 may be bump electrodes or pillar electrodes.
  • the material of the projecting electrodes 244 and the pad electrodes 241 is Cu, for example.
  • the projecting electrodes 244 and the pad electrodes 241 can be formed based on electrolytic plating.
  • 9 to 15 are diagrams showing an example of a method for manufacturing a semiconductor device according to the second embodiment.
  • 9 to 15 are cross-sectional views taken at the same position as a in FIG. 8, and b in FIGS.
  • an isolation layer 215 is formed on the semiconductor layer 213 of the SOI substrate 210, and semiconductor elements such as transistors are formed on the semiconductor layer 213.
  • a wiring layer 217 is formed on the semiconductor layer 213, and the wiring layer 217 is bonded to the wiring layer 152 by a method such as hybrid bonding.
  • a back surface insulating film 218 is formed on the back surface side of the semiconductor substrate 211 by CVD. Further, a resist pattern 281 having an opening 282 is formed on the back insulating film 218 by photolithography. The opening 282 can be arranged at the position of the pad electrode 230 when viewed from the back side of the SOI substrate 210 .
  • the resist pattern 281 is removed.
  • a side wall insulating film 214 is formed by CVD, and the side wall insulating film 214 on the rear surface insulating film 218 is removed by etchback.
  • the intermediate insulating layer 212 is etched using the rear insulating film 218 and the sidewall insulating film 214 in which the through holes 221 are formed as an etching mask, thereby forming the through holes 223 in the intermediate insulating layer 212 .
  • the semiconductor layer 213 is etched using the intermediate insulating layer 212 with the through holes 223 formed therein as an etching mask, thereby forming through holes 224 and cavities 225 in the semiconductor layer 213 .
  • isotropic etching can be used to form the through holes 224 and the cavities 225 .
  • the semiconductor layer 213 can be etched horizontally through the through-holes 224 , and a cavity 225 communicating with the through-holes 224 can be formed in the semiconductor layer 213 .
  • the insulating separation layer 215 and the insulating layer 240 can be used as an etch stopper.
  • the back side of the pad electrode 230 is exposed by etching the insulating layer 240 on the back side of the pad electrode 230 through the through holes 221 to 224 .
  • through electrodes 232 connected to the pad electrodes 230 are formed in the through holes 221 to 224, and embedded wirings 233 connected to the through electrodes 232 are formed in the cavity 225.
  • a plated layer can be used for the through electrode 232 and the embedded wiring 233 .
  • CVD using a monovalent Cu ⁇ -diketone complex and a reducing agent that reduces the monovalent Cu ⁇ -diketone complex as raw materials may be used to form the seed layer used to form this plating layer, or ALD CVD may be used.
  • the through electrode 232 is flattened by CMP to expose the back insulating film 218 .
  • a protective film 242 is formed on the rear insulating film 218 by a method such as CVD or sputtering. Then, an opening 243 is formed by patterning the protective film 242 using a photolithographic technique and an etching technique. Then, a plated layer is formed so as to fill the opening 243 , and the plated layer is thinned by CMP to expose the surface of the protective film 242 and form the pad electrode 241 buried in the opening 243 . Then, a projecting electrode 244 is formed on the pad electrode 241 by a method such as electrolytic plating. At this time, since the pad electrode 241 exists under the projecting electrode 244, the formation of the seed layer for electroplating may be omitted.
  • the semiconductor substrate 151 is thinned from the back side by a method such as CMP. Then, a color filter 171 is formed on the back side of the semiconductor substrate 151 and an on-chip lens 172 is formed on the color filter 171 .
  • the embedded wiring 233 surrounded by the insulating isolation layer 215 is embedded in the semiconductor layer 213.
  • the wiring area can be expanded without increasing the area of the semiconductor layer 213 in which the semiconductor element is formed, and the stability of power supply can be improved.
  • the through holes 224 in which the through electrodes 232 are embedded and the cavities 225 in which the embedded wirings 233 are embedded are collectively formed in the semiconductor layer 213, and the through electrodes 232 and the embedded wirings 233 can be collectively embedded in the semiconductor layer 213. Therefore, there is no need to separately provide a step of forming the through electrode 232 and a step of forming the embedded wiring 233, and an increase in the number of steps when forming the through electrode 232 and the embedded wiring 233 can be suppressed.
  • the projecting electrode 244 is provided at the position of the through electrode 232 on the back side of the SOI substrate.
  • a protruding electrode is provided at a position away from the through electrode 232 on the back surface side of the SOI substrate, and the through electrode 232 and the protruding electrode are connected via a back surface wiring.
  • FIG. 16 is a diagram showing a configuration example of a semiconductor device according to the third embodiment.
  • a is a cross-sectional view showing a configuration example of the semiconductor device 300 cut in the vertical direction
  • b is a rear view showing the configuration example of the semiconductor device 300
  • c is a cross-sectional view showing the configuration example of the semiconductor device 300 cut in the horizontal direction.
  • a in the same figure was cut at the position B1-B2 of b in the same figure.
  • c in the same figure was cut at the position of C1-C2 of a in the same figure.
  • a semiconductor device 300 includes a semiconductor chip 301 instead of the semiconductor chip 201 of the second embodiment described above.
  • Other configurations of the semiconductor device 300 of the third embodiment are the same as those of the semiconductor device 200 of the above-described second embodiment.
  • the semiconductor chip 301 includes a pad electrode 341, a protective film 342, a protruding electrode 344 and a rear wiring 346 instead of the pad electrode 241, protective film 242 and protruding electrode 244 of the second embodiment.
  • Other configurations of the semiconductor chip 301 of the third embodiment are the same as those of the semiconductor chip 201 of the above-described second embodiment.
  • a protective film 342 is formed on the back insulating film 218 .
  • a wiring trench 345 and an opening 343 are formed in the protective film 342 .
  • the wiring grooves 345 are formed at positions where the through electrodes 232 are exposed.
  • the opening 343 is formed at a position apart from the through electrode 232 in the horizontal direction of the semiconductor chip 301 .
  • a back wiring 346 is embedded in the wiring groove 345 and connected to the through electrode 232 .
  • a pad electrode 341 is embedded in the opening 343 and connected to a rear wiring 346 .
  • a projecting electrode 344 is formed on the pad electrode 341 .
  • the protruding electrodes 344 may be bump electrodes or pillar electrodes.
  • the material of the projecting electrodes 344, the pad electrodes 341, and the back wiring 346 is Cu, for example.
  • Cu as a material for the protruding electrodes 344, the pad electrodes 341 and the back wiring 346, the protruding electrodes 344, the pad electrodes 341 and the back wiring 346 can be formed based on electroplating.
  • the through electrodes 232 and the projecting electrodes 344 are connected via the back wiring 346 .
  • the embedded wiring 233 embedded in the semiconductor layer 213 is provided in the semiconductor chip 201 .
  • the embedded wiring embedded in the semiconductor layer 213 has a straight single structure.
  • FIG. 17 is a diagram showing a configuration example of a semiconductor device according to the fourth embodiment.
  • a in FIG. 4 is a cross-sectional view showing a configuration example of horizontally cutting the semiconductor layer 213 after the formation of the insulating isolation layer 415 .
  • b in the same figure is a cross-sectional view showing a configuration example of horizontally cutting the semiconductor layer 213 after forming the embedded wiring 433 .
  • c in the figure is a cross-sectional view showing an arrangement example of the through electrode 432 in b in the same figure.
  • an insulating separation layer 415 and embedded wiring 433 are formed in the semiconductor layer 213 .
  • An insulating isolation layer 415 can separate the semiconductor layer 213 into an inner side and an outer side.
  • the embedded wiring 433 is surrounded by an insulating isolation layer 415 .
  • the embedded wiring 433 can be embedded in the semiconductor layer 213 by removing the semiconductor layer 213 inside the insulating separation layer 415 .
  • a through electrode 432 is connected to the embedded wiring 433 .
  • the through electrode 432 can be arranged at a position surrounded by the insulating isolation layer 415 .
  • the embedded wiring 433 embedded in the semiconductor layer 213 has a single structure, thereby locally improving the stability of power supply.
  • the embedded wiring 433 embedded in the semiconductor layer 213 has a single structure.
  • the embedded wiring 433 embedded in the semiconductor layer 213 has a multi-structure.
  • FIG. 18 is a diagram showing a configuration example of a semiconductor device according to the fifth embodiment.
  • a in FIG. 4 is a cross-sectional view showing a configuration example of horizontally cutting the semiconductor layer 213 after the formation of the insulating separation layer 415 .
  • b in the same figure is a cross-sectional view showing a configuration example of horizontally cutting the semiconductor layer 213 after forming the embedded wiring 433 .
  • c in the figure is a cross-sectional view showing an arrangement example of the through electrode 432 in b in the same figure.
  • an insulating separation layer 415 and embedded wiring 433 are formed in the semiconductor layer 213 .
  • a plurality of insulating separation layers 415 are provided in a state of being separated from each other.
  • Each insulating isolation layer 415 can separate the semiconductor layer 213 into an inner side and an outer side.
  • An embedded wiring 433 is formed at a position surrounded by each insulating isolation layer 415 .
  • This figure shows an example in which only four embedded wirings 433 are provided in the semiconductor layer 213 .
  • a through electrode 432 is connected to each embedded wiring 433 .
  • Each through electrode 432 can be arranged at a position surrounded by each insulating separation layer 415 .
  • the embedded wiring 433 embedded in the semiconductor layer 213 by making the embedded wiring 433 embedded in the semiconductor layer 213 to have a multi-structure, it is possible to improve the stability of power supply while making the power supply voltages different from each other.
  • the embedded wiring 433 embedded in the semiconductor layer 213 has a straight single structure.
  • the embedded wiring embedded in the semiconductor layer 213 has a folded structure.
  • FIG. 19 is a diagram showing a configuration example of a semiconductor device according to the sixth embodiment.
  • a in FIG. 10 is a cross-sectional view showing an example of a configuration in which the semiconductor layer 213 after the insulating separation layer 515 is formed is horizontally cut.
  • b in the same figure is a cross-sectional view showing a configuration example of horizontally cutting the semiconductor layer 213 after forming the embedded wiring 533 .
  • c in the figure is a cross-sectional view showing an arrangement example of the through electrode 532 in b in the same figure.
  • an insulating separation layer 515 and embedded wiring 533 are formed in the semiconductor layer 213 .
  • the insulating separation layer 515 can have a folded structure while separating the semiconductor layer 213 into an inner side and an outer side.
  • the embedded wiring 533 is surrounded by an insulating separation layer 515 .
  • a through electrode 532 is connected to the embedded wiring 533 .
  • the through electrode 532 can be arranged at a position surrounded by the insulating isolation layer 515 .
  • the embedded wiring 533 embedded in the semiconductor layer 213 has a folded structure, thereby improving the stability of power supply over the entire surface of the semiconductor layer 213 .
  • the embedded wiring 433 embedded in the semiconductor layer 213 has a straight single structure.
  • the embedded wiring embedded in the semiconductor layer 213 is made to have a fishbone shape.
  • FIG. 20 is a diagram showing a configuration example of a semiconductor device according to the seventh embodiment.
  • a in FIG. 10 is a cross-sectional view showing an example of a configuration in which the semiconductor layer 213 after the insulating separation layer 615 is formed is cut in the horizontal direction.
  • b in the same figure is a cross-sectional view showing a configuration example of horizontally cutting the semiconductor layer 213 after forming the embedded wiring 633 .
  • c in the figure is a cross-sectional view showing an arrangement example of the through electrode 632 in b in the same figure.
  • an insulating separation layer 615 and embedded wiring 633 are formed in the semiconductor layer 213 .
  • the insulating isolation layer 615 can be fishbone shaped while separating the semiconductor layer 213 into an inner side and an outer side.
  • the embedded wiring 633 is surrounded by an insulating isolation layer 615 .
  • a through electrode 632 is connected to the embedded wiring 633 .
  • the through electrode 632 can be arranged at a position surrounded by the insulating separation layer 615 .
  • the embedded wiring 633 embedded in the semiconductor layer 213 has a fishbone shape.
  • the stability of power supply can be improved over the entire surface of the semiconductor layer 213, and the structure of the semiconductor layer 213 can be strengthened.
  • the embedded wiring 433 embedded in the semiconductor layer 213 has a straight single structure.
  • the embedded wiring embedded in the semiconductor layer 213 is formed in a mesh shape.
  • FIG. 21 is a diagram showing a configuration example of a semiconductor device according to the eighth embodiment.
  • a in FIG. 10 is a cross-sectional view showing an example of a configuration in which the semiconductor layer 213 after the insulating separation layer 715 is formed is cut in the horizontal direction.
  • b in the figure is a cross-sectional view showing a structural example of horizontally cutting the semiconductor layer 213 after forming the embedded wiring 733 .
  • c in the figure is a cross-sectional view showing an arrangement example of the through electrode 732 in b in the same figure.
  • an insulating separation layer 715 and embedded wiring 733 are formed in the semiconductor layer 213 .
  • the insulating separation layer 715 separates the semiconductor layer 213 into an inner portion, an outer portion, and an intermediate portion therebetween, and the semiconductor layer 213 in the intermediate portion can be made into a mesh shape, and the inner semiconductor layer 213 can be made into a plurality of isolated patterns.
  • the embedded wiring 733 is surrounded by an insulating isolation layer 715 .
  • a through electrode 732 is connected to the embedded wiring 733 .
  • the through electrode 732 can be arranged at a position surrounded by the insulating isolation layer 715 .
  • the embedded wiring 733 embedded in the semiconductor layer 213 has a mesh shape.
  • the stability of power supply can be improved over the entire surface of the semiconductor layer 213, and the structure of the semiconductor layer 213 can be strengthened.
  • semiconductor elements formed in the inner semiconductor layer 213 separated by the insulating separation layer 715 can be separated by the insulating separation layer 715 .
  • semiconductor chip 101 is provided with through electrode 132 which penetrates semiconductor substrate 111, intermediate insulating layer 112 and semiconductor layer 113 and is surrounded by side wall insulating film 114, intermediate insulating layer 112 and insulating separation layer 115.
  • the semiconductor chip 801 is provided with capacitive electrodes 833 and 835 embedded in the semiconductor layer 813 in addition to the through electrode 232 penetrating the semiconductor substrate 211 , the intermediate insulating layer 212 and the semiconductor layer 213 .
  • FIG. 22 is a diagram showing a configuration example of a semiconductor device according to the ninth embodiment.
  • a is a cross-sectional view showing a configuration example of the semiconductor device 800 cut in the vertical direction
  • b is a rear view showing the configuration example of the semiconductor device 800
  • c is a cross-sectional view showing the configuration example of the semiconductor device 800 cut in the horizontal direction.
  • a in the figure was cut at the position D1-D2 of b in the same figure.
  • c in the same figure was cut at the position of E1-E2 of a in the same figure.
  • a semiconductor device 800 includes a semiconductor chip 801 instead of the semiconductor chip 101 of the first embodiment described above.
  • Other configurations of the semiconductor device 800 of the ninth embodiment are the same as those of the semiconductor device 100 of the above-described first embodiment.
  • a semiconductor chip 801 comprises a semiconductor substrate 811 , an intermediate insulating layer 812 and a semiconductor layer 813 .
  • An intermediate insulating layer 812 is laminated on the semiconductor substrate 811
  • a semiconductor layer 813 is laminated on the intermediate insulating layer 812 .
  • an SOI substrate 810 can be used as a laminated structure of the semiconductor substrate 811 , the intermediate insulating layer 812 and the semiconductor layer 813 .
  • Semiconductor elements such as transistors are formed in the semiconductor layer 813 .
  • the semiconductor layer 813 is formed with an insulating separation layer 815 for insulating and separating a part of the semiconductor layer 813 .
  • the insulating isolation layer 815 can be formed so as to surround part of the semiconductor layer 813 and divide the semiconductor layer 813 .
  • the position of the semiconductor layer 813 surrounded by the insulating separation layer 815 can correspond to the formation position of each capacitive electrode 833 and 835 .
  • STI can be used for the insulating separation layer 815 .
  • the insulating isolation layer 815 penetrates the semiconductor layer 813 and reaches the intermediate insulating layer 812 .
  • a wiring layer 817 is formed on the semiconductor layer 813 .
  • Pad electrodes 830 and 831 and wiring are formed in the wiring layer 817 .
  • Pad electrodes 830 and 831 and wiring are embedded in insulating layer 840 .
  • a back surface insulating film 818 is formed on the back surface side of the semiconductor substrate 811 .
  • through holes 821 to 824 and 851 to 854 are formed in the rear insulating film 818, the semiconductor substrate 811, the intermediate insulating layer 812 and the semiconductor layer 813, respectively.
  • cavities 825 and 855 communicating with through holes 824 and 854 are formed in the semiconductor layer 813 .
  • the through holes 824 and the cavities 825 and the through holes 854 and the cavities 855 are formed at positions surrounded by the insulating isolation layer 815 .
  • Side wall insulating films 814 are formed on the side walls of the through holes 821 and 822 in the back surface insulating film 818 and the semiconductor substrate 811 .
  • a through electrode 832 is formed that penetrates the rear insulating film 818, the semiconductor substrate 811, the intermediate insulating layer 812 and the semiconductor layer 813 and is connected to the capacitor electrode 833.
  • through electrodes 834 are formed that penetrate through the rear insulating film 818 , the semiconductor substrate 811 , the intermediate insulating layer 812 and the semiconductor layer 813 and are connected to the capacitor electrodes 835 .
  • the through electrode 832 can be in contact with the pad electrode 830 and the through electrode 834 can be in contact with the pad electrode 831 .
  • a capacitor electrode 833 connected to the through electrode 832 is formed in the cavity 825
  • a capacitor electrode 835 connected to the through electrode 834 is formed in the cavity 855 .
  • the through electrodes 832 and 834 are surrounded by sidewall insulating films 814 .
  • the through electrode 832 and the capacitive electrode 833 and the through electrode 834 and the capacitive electrode 835 are surrounded by an insulating separation layer 815 .
  • the through electrodes 832 and 834 are insulated from the semiconductor layer 813 by the intermediate insulating layer 812 and the insulating separation layer 815 and insulated from the semiconductor substrate 811 by the intermediate insulating layer 812 and the sidewall insulating film 814 .
  • each capacitive electrode 833 and 835 is insulated from the semiconductor layer 813 by the insulating separation layer 815 and insulated from the semiconductor substrate 811 by the intermediate insulating layer 812 .
  • Capacitor electrodes 833 and 835 are insulated from each other by insulating separation layer 815 .
  • at least part of the capacitive electrodes 833 and 835 can face each other with the insulating separation layer 815 interposed therebetween.
  • the capacitor electrodes 833 and 835 can constitute a capacitor using the insulating separation layer 815 as a dielectric.
  • a protective film 841 is formed on the back insulating film 818 so as to cover the through electrodes 832 and 834 .
  • the material of the protective film 841 is SiN, for example.
  • 23 to 28 are diagrams showing an example of a method for manufacturing a semiconductor device according to the ninth embodiment.
  • 23 to 28 are cross-sectional views taken at the same position as a in FIG. 22, and b in FIGS.
  • an isolation layer 815 is formed on a semiconductor layer 813 of an SOI substrate 810, and a semiconductor element such as a transistor is formed on the semiconductor layer 813.
  • a wiring layer 817 is formed on the semiconductor layer 813, and the wiring layer 817 is bonded to the wiring layer 152 by a method such as hybrid bonding.
  • a back surface insulating film 818 is formed on the back surface side of the semiconductor substrate 811 by CVD. Further, a resist pattern 881 provided with openings 882 and 883 is formed on the back surface insulating film 818 by photolithography. The openings 882 and 883 can be arranged at the positions of the pad electrodes 830 and 831 when viewed from the back side of the SOI substrate 810 .
  • the resist pattern 881 By etching the rear insulating film 818 and the semiconductor substrate 811 using the resist pattern 881 as an etching mask, through holes 821 and 851 are formed in the rear insulating film 818 and through holes 822 and 852 are formed in the semiconductor substrate 811 .
  • the resist pattern 881 is removed.
  • a side wall insulating film 814 is formed by CVD, and the side wall insulating film 814 on the rear surface insulating film 818 is removed by etchback.
  • intermediate insulating layer 812 is etched using rear insulating film 818 and side wall insulating film 814 in which through holes 821 and 851 are formed as an etching mask, thereby forming through holes 823 and 853 in intermediate insulating layer 812 .
  • through holes 824 and 854 and cavities 825 and 855 are formed in the semiconductor layer 813 by etching the semiconductor layer 813 using the intermediate insulating layer 812 in which the through holes 823 and 853 are formed as an etching mask.
  • Isotropic etching can be used to form the through holes 824 and 854 and the cavities 825 and 855 .
  • the semiconductor layer 813 can be horizontally etched through the through holes 824 and 854, and cavities 825 and 855 communicating with the through holes 824 and 854 can be formed in the semiconductor layer 213.
  • the insulating separation layer 815 and the insulating layer 840 can be used as an etch stopper.
  • the back sides of the pad electrodes 830 and 831 are exposed by etching the insulating layer 840 on the back sides of the pad electrodes 830 and 831 through the through holes 821 to 824 and 851 to 854 .
  • through electrodes 832 connected to the pad electrodes 830 are formed in the through holes 821 to 824, and a capacitor electrode 833 connected to the through electrodes 832 is formed in the cavity 825.
  • a through electrode 834 connected to the pad electrode 831 is formed in the through holes 851 to 854 and a capacitor electrode 835 connected to the through electrode 834 is formed in the cavity 855 .
  • Plated layers can be used for the through electrodes 832 and 834 and the capacitor electrodes 833 and 835 .
  • the through electrodes 832 and 834 are planarized by CMP to expose the back insulating film 818 .
  • a protective film 841 is formed on the rear insulating film 818 by CVD so as to cover the through electrodes 832 and 834 .
  • the semiconductor substrate 151 is thinned from the back side by a method such as CMP. Then, a color filter 171 is formed on the back side of the semiconductor substrate 151 and an on-chip lens 172 is formed on the color filter 171 .
  • the capacitive electrodes 833 and 835 separated from each other by the insulating separation layer 815 are embedded in the semiconductor layer 813.
  • the capacitance can be increased without increasing the area of the semiconductor layer 813 in which the semiconductor element is formed, and the noise resistance can be improved.
  • the through holes 824 and 854 and the cavities 825 and 855 can be collectively formed in the semiconductor layer 813, and the through electrodes 832 and 834 and the capacitor electrodes 833 and 835 can be collectively embedded in the semiconductor layer 813. Therefore, there is no need to separately provide a step of forming the through electrodes 832 and 834 and a step of forming the capacitor electrodes 833 and 835, and an increase in the number of steps when forming the through electrodes 832 and 834 and the capacitor electrodes 833 and 835 can be suppressed.
  • the capacitor electrodes 833 and 835 may be locally formed in a partial region of the semiconductor layer 813 .
  • the through electrodes 132 in the first embodiment described above may be mixed in the semiconductor chip 801
  • the through electrodes 232 and the embedded wirings 233 in the second embodiment may be mixed in the semiconductor chip 801 .
  • the back wiring 133 and the pad electrode 134 in the first embodiment described above may be formed, or the pad electrode 241 and the projecting electrode 244 in the second embodiment described above may be formed.
  • the back wiring 346, the pad electrode 341 and the projecting electrode 344 in the third embodiment may be formed.
  • the present technology can also have the following configuration.
  • a semiconductor device comprising: an insulating film penetrating through the semiconductor substrate to reach the insulating layer and positioned between the semiconductor substrate and the through electrode.
  • a method of manufacturing a semiconductor device comprising: embedding a through-electrode surrounded by the insulating separation layer, the insulating layer and the insulating film in the first through-hole, the second through-hole and the third through-hole.
  • REFERENCE SIGNS LIST 100 semiconductor device 101, 102 semiconductor chip 110 SOI substrate 111, 151 semiconductor substrate 112 intermediate insulating layer 113 semiconductor layer 114 sidewall insulating film 115 insulating isolation layer 116 gate electrode 117, 152 wiring layer 118 back insulating film 119 protective film 121 to 124 through hole 125 opening 13
  • Reference Signs List 1 161 wiring 132 through electrode 133 rear wiring 130, 134 pad electrode 171 color filter 172 on-chip lens

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WO2025159072A1 (ja) * 2024-01-22 2025-07-31 ソニーセミコンダクタソリューションズ株式会社 電子デバイスおよび電子デバイスの製造方法

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