WO2023138219A1 - 一种存储器、时序控制方法及电子设备 - Google Patents

一种存储器、时序控制方法及电子设备 Download PDF

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WO2023138219A1
WO2023138219A1 PCT/CN2022/135129 CN2022135129W WO2023138219A1 WO 2023138219 A1 WO2023138219 A1 WO 2023138219A1 CN 2022135129 W CN2022135129 W CN 2022135129W WO 2023138219 A1 WO2023138219 A1 WO 2023138219A1
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memory
write
sfgt
lines
word line
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PCT/CN2022/135129
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English (en)
French (fr)
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焦慧芳
孙清清
李檀
应成伟
晁鑫
王敬元璋
范鲁明
闫鹏
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华为技术有限公司
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Publication of WO2023138219A1 publication Critical patent/WO2023138219A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the technical field of storage, and in particular to a memory, a timing control method, and an electronic device.
  • DRAM dynamic random access memory
  • CPU central processing unit
  • hard disks external memories
  • DRAM dynamic random access memory
  • transistor drive current is too small, leakage current increases; storage capacitors are getting smaller and smaller, resulting in shorter data retention time and increased power consumption; complex process, sharply rising costs, etc.
  • DRAM technology faces the above-mentioned bottleneck, it has been difficult to meet the market demand, so a new type of memory is urgently needed.
  • the present application provides a memory, a timing control method and an electronic device, which solve the problems faced by DRAM based on transistors and storage capacitors as storage units.
  • a memory in a first aspect, includes: a memory array, a plurality of sense amplifiers, and a plurality of write-back circuits, the memory array includes a plurality of rows and columns of semi-floating gate transistor SFGT memory cells, a plurality of first word lines, a plurality of write-back control lines, and a plurality of voltage lines; wherein, the SFGT memory cell has a control gate, a source and a drain, and the control gates of the SFGT memory cells belonging to the same row in the memory array share one of the first word lines in the plurality of first word lines, and the sources of the SFGT memory cells belonging to the same column are coupled and coupled
  • the point can be the first node, and the drains of the SFGT memory cells belonging to the same column are coupled and the coupling point can be the second node; the SFGT memory cells of the same column in the memory array also share one sense amplifier in the multiple sense amplifiers and one write-back circuit in the multiple write-back circuits; each write
  • the storage array of the memory includes multiple rows and multiple columns of SFGT memory cells, and the SFGT memory cells in the memory array are coupled with corresponding signal lines (i.e., word lines, write-back control lines and voltage lines, etc.), sense amplifiers, and write-back circuits according to the distribution of rows and columns, so that the memory can realize the functions of traditional DRAM. It has the advantages of fast operation speed, small unit area, high chip density, low operating voltage for data storage, and strong data retention ability.
  • the memory further includes a plurality of bit lines, and each first node is coupled to a bit line in the plurality of bit lines; each sense amplifier in the plurality of sense amplifiers includes a first end, and the first end of each sense amplifier is coupled to a bit line in the plurality of bit lines; each write-back circuit in the plurality of write-back circuits further includes a second end and a third end, the second end of each write-back circuit is coupled to a bit line in the plurality of bit lines, and the third end of each write-back circuit is coupled to the second node of the corresponding column.
  • the source of the SFGT storage unit can be coupled to the corresponding sense amplifier, so that when performing read and write operations, the data in the SFGT storage unit can be written into the sense amplifier through the source based on the control command of the traditional DRAM, and the data in the sense amplifier can be written back to the SFGT memory unit, so as to achieve compatibility with the controller and control commands of the traditional DRAM.
  • the memory further includes a plurality of bit lines, each second node is coupled to one of the plurality of bit lines, and each first node is coupled to a ground terminal; each of the plurality of sense amplifiers includes a first end; each of the plurality of write-back circuits further includes a second end and a third end, the first end of the sense amplifier shared by the same column is coupled to the second end of the write-back circuit, and the third end of each write-back circuit is coupled to the second node of the corresponding column.
  • the drain of the SFGT storage unit can be coupled to the corresponding sense amplifier, so that when performing read and write operations, based on the control instructions of the traditional DRAM, the data in the SFGT storage unit can be written into the sense amplifier through the drain, and the data in the sense amplifier can be written back to the SFGT memory unit, so as to achieve compatibility with the controller and control commands of the traditional DRAM.
  • each write-back circuit includes: a P-type metal oxide semiconductor PMOS transistor and an N-type metal oxide semiconductor NMOS transistor; wherein, the gate of the PMOS transistor is coupled to the gate of the NMOS transistor as the control terminal of the write-back circuit, one pole of the PMOS transistor is used as the second terminal of the write-back circuit, one pole of the NMOS transistor is used as a voltage terminal of the write-back circuit, and the other pole of the PMOS transistor is coupled to the other pole of the NMOS transistor as the third terminal of the write-back circuit.
  • one of the one pole and the other pole is a source, and the other is a drain.
  • a simple and effective write-back circuit through which data write-back can be realized, and at the same time, the memory can use a voltage-type sense amplifier with a smaller area to cache data, thereby further reducing the area of the memory and increasing storage density.
  • the SFGT memory cell further has a sub-gate, and the memory further includes a plurality of second word lines; wherein, the sub-gates of the SFGT memory cells belonging to the same row in the memory array share one second word line in the plurality of second word lines.
  • the read and write operations of the memory can be made more accurate by controlling the plurality of second word lines and the other signal lines.
  • the memory includes a first storage array and a second storage array that share the multiple sense amplifiers, a column of SFGT storage cells in the first storage array and a column of SFGT storage cells in the second storage array share one sense amplifier among the multiple sense amplifiers, and the first storage array and the second storage array respectively correspond to multiple independent write-back circuits.
  • a column of SFGT memory cells in the first memory array and a column of SFGT memory cells in the second memory array share a sense amplifier, so that the sense amplifier can use the voltage of the SFGT memory cells in another column as a reference when buffering data of the SFGT memory cells in one column, thereby avoiding the problem of separately setting the reference voltage, and reducing the area and cost.
  • the sense amplifier is a voltage type sense amplifier.
  • the memory can further reduce the area of the memory and increase the storage density by using a voltage-type sense amplifier with a small area to cache data.
  • the memory includes a dynamic random access memory (DRAM).
  • DRAM dynamic random access memory
  • the second aspect provides a timing control method, which is applied to the memory provided by the above-mentioned first aspect or any possible implementation of the first aspect.
  • the method includes: in the row activation phase, controlling the first word line corresponding to the SFGT memory cell of the target row to be at a high level, controlling the plurality of write-back control lines to be at a high level, controlling the multiple voltage lines to be at a high level and switching to a low level after a period of time, so as to complete two operations of row activation and erasing in the row activation phase; in the read-write phase, controlling the first word line to be at a low level, and controlling the plurality of write-back control lines to be at a low level , to achieve data read and write operations. Further, in the pre-charging stage, the first word line is controlled to be at a low level, and the plurality of write-back voltage lines and the plurality of voltage lines are controlled to be at a high level, so as to realize a pre-charging operation.
  • the two operations of row activation and erasing are completed by controlling the voltage of the corresponding signal line in the memory during the row activation phase, so as to complete the erasing operation that the SFGT storage unit needs to perform during the row activation phase, and at the same time, the corresponding read and write operations and precharge operations are completed by controlling the voltage of the corresponding signal line during the read and write phase and the precharge phase, so as to realize the read and write of the SFGT-based memory.
  • the operation flow of the controller for controlling the SFGT-based memory is consistent with the operation flow for controlling the traditional DRAM, thereby realizing compatibility with the controller and control instructions of the traditional DRAM, improving the operation performance and reducing the operation delay.
  • using the timing control method can also avoid the impact on the original function or structure of other hardware circuits related to the DRAM when the memory is used to replace the traditional DRAM, and reduce the cost and complexity of replacing the traditional DRAM.
  • the SFGT storage unit also has a sub-gate
  • the memory further includes a plurality of second word lines, and the sub-gates of the SFGT storage unit belonging to the same row in the memory array share one of the plurality of second word lines; the method also includes: in the row activation phase, controlling the second word line corresponding to the SFGT storage unit in the target row to be at a high level; in the read and write phase, controlling the second word line corresponding to the SFGT storage unit in the target row to be at a low level. Further, in the precharging stage, control the second word line corresponding to the SFGT memory cells in the target row to be at a high level.
  • the read and write operations of the memory can be made more accurate by controlling the plurality of second word lines and the other signal lines.
  • the corresponding voltage values when the first word line and the second word line are at a high level, the corresponding voltage values are positive, and when the first word line and the second word line are at a low level, the corresponding voltage values are negative; when the plurality of writeback control lines and the plurality of voltage lines are at a high level, the corresponding voltage values are positive, and when the plurality of writeback control lines and the plurality of voltage lines are at a low level, the corresponding voltage values are 0.
  • the above possible implementation manner can reduce the operating voltage of the memory during the read and write process, thereby reducing power consumption.
  • the corresponding voltage values of the first word line and the second word line are equal when they are at a high level.
  • the above possible implementation manner can reduce a set of voltage values in the row activation phase, thereby reducing corresponding voltage conversion and reducing power consumption.
  • the voltage values corresponding to the multiple voltage lines when the pre-charging phase is high level are lower than the voltage values corresponding to the multiple voltage lines when the row activation phase is high level.
  • the above possible implementation manner can reduce the operating voltage of the memory during the read and write process, thereby reducing power consumption.
  • a timing control method is provided, which is applied to the memory provided in the above-mentioned first aspect or any possible implementation of the first aspect.
  • the method includes: in the row activation phase, controlling the first word line corresponding to the SFGT memory cell of the target row to be at a high level, controlling the multiple write-back control lines to be at a low level and switching to a high level after a period of time, and controlling the multiple voltage lines to be at a low level when the multiple write-back control lines are at a high level, so as to complete two operations of row activation and erasing in the row activation phase; , controlling the plurality of write-back control lines to be low level, so as to realize data read and write operations.
  • the first word line is controlled to be at low level, and the multiple write-back control lines are controlled to be at low level, so as to realize the pre-charging operation.
  • the two operations of row activation and erasing are completed by controlling the voltage of the corresponding signal line in the memory during the row activation phase, so as to complete the erasing operation that the SFGT storage unit needs to perform during the row activation phase, and at the same time, the corresponding read and write operations and precharge operations are completed by controlling the voltage of the corresponding signal line during the read and write phase and the precharge phase, so as to realize the read and write of the SFGT-based memory.
  • the operation flow of the controller for controlling the SFGT-based memory is consistent with the operation flow for controlling the traditional DRAM, thereby realizing compatibility with the controller and control instructions of the traditional DRAM, improving the operation performance and reducing the operation delay.
  • using the timing control method can also avoid the impact on the original function or structure of other hardware circuits related to the DRAM when the memory is used to replace the traditional DRAM, and reduce the cost and complexity of replacing the traditional DRAM.
  • the SFGT memory cell also has a sub-gate
  • the memory also includes a plurality of second word lines
  • the sub-gates of the SFGT memory cells belonging to the same row in the memory array share one second word line among the plurality of second word lines
  • the method also includes: in the row activation phase, controlling the second word line corresponding to the SFGT memory cell in the target row to be at a high level; in the read/write phase, controlling the second word line corresponding to the SFGT memory cell in the target row to be at a low level;
  • the second word line corresponding to the SFGT memory cells in the target row is at high level.
  • the corresponding voltage values when the first word line and the second word line are at a high level, the corresponding voltage values are positive, and when the first word line and the second word line are at a low level, the corresponding voltage values are negative; when the plurality of writeback control lines and the plurality of voltage lines are at a high level, the corresponding voltage values are positive, and when the plurality of writeback control lines and the plurality of voltage lines are at a low level, the corresponding voltage values are 0.
  • the above possible implementation manner can reduce the operating voltage of the memory during the read and write process, thereby reducing power consumption.
  • the corresponding voltage values of the first word line and the second word line are equal when they are at a high level.
  • the above possible implementation manner can reduce the operating voltage of the memory during the read and write process, thereby reducing power consumption.
  • an electronic device in a fourth aspect, includes a processor and a memory, the memory includes a controller, and a storage array composed of a semi-floating gate transistor SFGT storage unit, the processor is used to send an access request to the storage array to the controller based on the DDR interface protocol, the controller is used to read and write data from the storage array according to the access request, and the controller is also used to erase the data in the SFGT storage unit in the storage array during the read and write process.
  • the processor is used to send an access request to the storage array to the controller based on the DDR interface protocol
  • the controller is used to read and write data from the storage array according to the access request
  • the controller is also used to erase the data in the SFGT storage unit in the storage array during the read and write process.
  • the original DDR storage array in the electronic device is replaced with a storage array composed of SFGT storage units.
  • the processor can still send an access request based on the DDR interface protocol to the controller in the memory, that is, the processor can still access the storage array composed of SFGT storage units through the controller based on the original DDR access method.
  • the controller can read and write data from the storage array, and execute the operation of erasing the data in the SFGT storage unit in the storage array during the read and write process, that is, the controller can read and write data from the storage array composed of SFGT storage units based on the original DDR access request and complete the required erase operation of the SFGT storage unit. Therefore, the electronic device can use a storage array composed of SFGT memory cells to cache data without affecting the function and architecture of the original processor, so that the electronic device has the advantages of fast read and write speed, small size, low read and write voltage, and strong data retention capabilities. At the same time, it can also reduce the cost and complexity of replacing the original DDR with a memory based on SFGT memory cells.
  • the memory further includes a sense amplifier SA, and the controller performs the following actions according to the access request: read the data in the SFGT storage unit of the target row to the SA; erase the data in the SFGT storage unit of the target row; output the target data in the SA, and write back the data in the SA to the SFGT storage unit of the target row, where the data in the SA includes the target data; or, write the target data into the SA, and write back the data in the SA to the target row in the SFGT storage unit.
  • SA sense amplifier
  • the controller is further configured to set the SFGT storage cells of the target row to a holding state, and precharge the bit line corresponding to the SFGT storage cells of the target row.
  • an electronic device includes a circuit board and a memory connected to the circuit board, where the memory includes the memory provided in the first aspect or any possible implementation manner of the first aspect.
  • an electronic device includes a controller and a memory, the controller is configured to control read and write operations of the memory, and the memory includes the memory provided in the first aspect or any possible implementation manner of the first aspect.
  • FIG. 1 is a schematic structural diagram of an electronic device provided in an embodiment of the present application.
  • Fig. 2 is a schematic structural diagram of a SFGT provided in the embodiment of the present application.
  • Fig. 3 is the operation flowchart of a kind of traditional DRAM provided by the embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a memory provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of another memory provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of another memory provided by the embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a voltage-type sense amplifier provided in an embodiment of the present application.
  • FIG. 8 is a timing control diagram of a memory provided by an embodiment of the present application.
  • FIG. 9 is a timing control diagram of another memory provided by the embodiment of the present application.
  • circuits or other components may be described or referred to as “operating" to perform one or more tasks.
  • "for” is used to imply structure by indicating that a circuit/component includes structure (eg, circuitry) that performs one or more tasks during operation. Accordingly, even when the specified circuit/component is not currently operational (eg, not turned on), the circuit/component may be said to be used to perform the task.
  • a circuit/component used with the phrase “for” includes hardware, such as a circuit to perform an operation, and the like.
  • At least one (unit) of a, b or c can represent: a, b, c, a and b, a and c, b and c or a, b and c, wherein a, b and c can be single or multiple.
  • words such as “first” and “second” do not limit the quantity and order.
  • the technical solutions of the present application can be applied to various electronic devices including memory, for example, the technical solutions of the present application can be applied to computers, tablet computers, notebook computers, mobile phones, netbooks, wearable devices, vehicle-mounted devices, or camera devices.
  • the electronic device in the present application may only include a memory, or may include a processor and a memory at the same time, and the processor may be a central processing unit (CPU), an artificial intelligence (AI) processor, a digital signal processor (digital signal processor) and a neural network processor, etc.
  • the electronic device may also include one or more of a plurality of modules such as a communication module, a sensor module, a display module, and an input-output module.
  • the embodiment of the present application does not specifically limit the structure of the electronic device.
  • FIG. 1 is a schematic structural diagram of an electronic device provided in an embodiment of the present application, and the electronic device may include a memory.
  • the electronic device may also include a CPU, a cache (cache), a controller, and the like.
  • the CPU, the cache, the controller and the memory can be integrated together, and the memory can be coupled to the cache through the controller, and coupled to the CPU through the cache.
  • the memory involved in the technical solution of the present application may include a dynamic random access memory (DRAM). Further, the DRAM may include synchronous dynamic random access memory (SDRAM), double data rate dynamic random access memory (DDR SRAM) and memory bus dynamic random access memory (rambus dynamic random access memory, RDRAM), etc. DDR SRAM may also be referred to as DRAM for short. DR. This embodiment of the present application does not list and describe them one by one.
  • SDRAM synchronous dynamic random access memory
  • DDR SRAM double data rate dynamic random access memory
  • RDRAM memory bus dynamic random access memory
  • DRAM is used as a memory for temporarily storing the calculation data of the processor and exchanging data with external memories such as hard disks.
  • DRAM dynamic random access memory
  • transistor drive current is too small, leakage current increases; storage capacitors are getting smaller and smaller, resulting in shorter data retention time and increased power consumption; complex processes, and sharply rising costs. Therefore, there is an urgent need for a new type of memory (also called a new type of DRAM) to replace the functions of the traditional DRAM.
  • an embodiment of the present application provides a memory and a timing control method of the memory, which are used to replace the functions of the traditional DRAM.
  • the memory can also achieve compatibility with the controller and control instructions of the traditional DRAM, that is, the controller and control instructions of the traditional DRAM can be used to implement the read and write operations of the memory, so as to avoid as far as possible the impact on the original functions or structures of other hardware circuits related to the DRAM when the memory is used to replace the traditional DRAM, thereby reducing the cost and complexity of replacing the traditional DRAM.
  • the memory provided in the embodiment of the present application is a new type of non-capacitor storage device, which uses a semi-floating gate transistor (SFGT) compatible with a complementary metal oxide semiconductor (CMOS) process as a memory unit, and has the advantages of fast operation speed, small unit area, high chip density, low operating voltage for data storage, and strong data retention capability.
  • SFGT semi-floating gate transistor
  • CMOS complementary metal oxide semiconductor
  • the SFGT includes a substrate (bulk), a source region and a drain region formed based on an n-type semiconductor material, a semi-floating gate (SFG) formed based on a p+ type semiconductor material, a control gate (CG) and a split gate (SG).
  • the source region is provided with a source (source, S), and the drain region is provided with a drain (drain, D). .
  • the source region, the drain region and the semi-floating gate SFG are located above the substrate, the semi-floating gate SFG is located between the source region and the drain region and the side of the semi-floating gate SFG away from the substrate covers part of the source region and the drain region, the control gate CG is located above the semi-floating gate SFG, and the sub-gate SG is located above the drain region D.
  • the SFGT may further include an isolation layer and an oxide layer, the isolation layer is used to isolate different SFGTs, and the oxide layer is used to isolate different parts inside the SFGT.
  • control gate CG and sub-gate SG can be connected together and merged into one gate (which can be called a control gate at this time), or can be two separate and independent gates.
  • control gate CG and the sub-gate SG are two independent gates as an example for illustration.
  • the SFGT writes data through the embedded tunneling transistor TFET formed by the semi-floating gate SFG, the drain region and the drain D, and performs the erasing operation through the PN junction formed by the semi-floating gate SFG and the drain region.
  • FIG. 2 shows the state when the SFGT writes “0”, and
  • FIG. 3 shows the state when the SFGT writes “0”, and
  • SFGT when SFGT is used as a storage unit, when reading/writing the SFGT storage unit, it is necessary to perform an erase (erase) (also referred to as/writing “0”) operation, a read operation, a program (program) (also referred to as writing “1”) operation and a hold operation on the SFGT storage unit.
  • the above operations are realized by setting the operating voltages of the control gate CG, the sub-gate SG and the drain D, and the corresponding operating voltages set when writing “1” and “0” are different.
  • FIG. 3 is an operation flowchart of performing read and write operations on a conventional DRAM.
  • ACT activate
  • read read
  • write write
  • PRE pre-charge
  • the activation operation is used to gate a certain word line (word line, WL) to read the data in the selected row into the sensor amplifier (sensor amplifier, SA); the read operation is used to output the corresponding target data in SA, and write back the data in SA to the corresponding row; the write operation is used to write the target data into SA, and write back the data in SA to the corresponding row; the precharge operation is used to turn off the gated WL, and precharge the bit line (BL).
  • word line word line
  • SA sensor amplifier
  • SA sensor amplifier
  • the read operation is used to output the corresponding target data in SA, and write back the data in SA to the corresponding row
  • the write operation is used to write the target data into SA, and write back the data in SA to the corresponding row
  • the precharge operation is used to turn off the gated WL, and precharge the bit line (BL).
  • the above multiple operations are respectively controlled by an activation command, a read command/write command, and a precharge command generated by the DRAM controller.
  • the data of the DRAM storage unit is all written from the drain of the corresponding transistor, and the corresponding operating voltage is the same when writing “1” and writing “0”.
  • FIG. 4 is a schematic structural diagram of a memory provided by an embodiment of the present application, and the memory may be a DRAM.
  • the memory includes: a memory array, multiple sense amplifiers and multiple write-back circuits.
  • the plurality of sense amplifiers can be used to buffer data in the storage array during the read-write process
  • the plurality of write-back circuits can be used to write back the data buffered in the plurality of sense amplifiers to the storage array during the read-write process.
  • the memory may include one storage array, or may include two storage arrays, and one storage array is taken as an example in FIG. 4 for illustration.
  • each column in the storage array corresponds to an inductive amplifier and a write-back circuit
  • the inductive amplifier is used for buffering the data of the corresponding column, and a separate reference line needs to be set to provide a reference voltage for the inductive amplifier.
  • each sense amplifier corresponds to a column in the two memory arrays, that is, each sense amplifier corresponds to two columns and the two columns are respectively located in different memory arrays.
  • the sense amplifier can use the voltage on the connection port corresponding to the other column as a reference voltage when buffering data in one of the columns, so that no additional reference voltage is required.
  • description will be made by taking the memory including two storage arrays as an example.
  • the memory includes a first storage array and a second storage array, and each storage array includes multiple rows and multiple columns of semi-floating gate transistor SFGT storage cells, multiple first word lines, multiple second word lines, multiple write-back control lines, and multiple voltage lines.
  • a plurality of first word lines in the first memory array are represented as WL11 to WL12, a plurality of second word lines are represented as WL21 to WL22, a plurality of write-back control lines are represented as CL1 to CL3, and a plurality of voltage lines are represented as VL1 to VL3; a plurality of first word lines in the second memory array are represented as WL13 to WL14, a plurality of second word lines are represented as WL23 to WL24, and a plurality of write-back control lines are represented as CL4 to CL6, A number of voltage lines are indicated as VL4 to VL6.
  • multiple sense amplifiers in the memory are denoted as SA1 to SA3
  • multiple write back circuits corresponding to the first storage array are denoted as WR1 to WR3
  • multiple write back circuits corresponding to the second storage array are denoted as WR4 to WR6.
  • multiple rows and multiple columns may refer to a logical relationship, specifically a logical "set” or "matrix".
  • multiple rows and multiple columns may or may not be present.
  • connection relationship of multiple SFGT storage units satisfies the connection relationship of SFGT storage units in the same row and the same column below, they can be regarded as belonging to the same row or the same column.
  • each SFGT storage unit has a control gate, a sub-gate, a source and a drain.
  • the control gates CG of the SFGT storage units belonging to the same row in the storage array share a first word line in the plurality of first word lines
  • the sub-gates SG of the SFGT storage units in the same row share a second word line in the plurality of second word lines.
  • the SFGT memory cells in the same column in each memory array also share one sense amplifier among the plurality of sense amplifiers and one write-back circuit among the plurality of write-back circuits.
  • Each of the multiple write-back circuits includes a control terminal and a voltage terminal, the control terminal of each write-back circuit is coupled to one of the multiple write-back control lines, and the voltage terminal of each write-back circuit is coupled to one of the multiple voltage lines.
  • the control terminal is used for receiving a control signal transmitted by a correspondingly coupled write-back control line, so that the write-back circuit realizes a write-back function in the process of reading and writing data based on the control signal.
  • the voltage terminal is used to receive the voltage transmitted by the correspondingly coupled voltage line, so as to provide a corresponding voltage for the write-back circuit during the process of reading and writing data.
  • each memory array includes 2 rows and 3 columns of SFGT memory cells, and the memory includes 3 sense amplifiers SA1 to SA3 and 6 write-back circuits WR1 to WR6 as an example for illustration, which does not limit the embodiment of the present application.
  • the memory may include more SFGT storage units, sense amplifiers and write-back circuits, which is not specifically limited in this embodiment of the present application.
  • control gate and the sub-gate of the SFGT memory cell can be combined into one gate, and the combined gate can be called a control gate.
  • the multiple first word lines and multiple second word lines in the above-mentioned memory can also be combined, and after the combination, only the multiple first word lines can be included, and the multiple second word lines can not be included.
  • each memory array also includes a plurality of bit lines, for example, the first memory array includes three bit lines and is represented as BL1 to BL3, and the second memory array includes three bit lines and is represented as BL4 to BL6.
  • each first node 1 in the same memory array is coupled to one bit line among the multiple bit lines, that is, the multiple bit lines in the same memory array are respectively coupled to multiple first nodes 1; or, each second node 2 in the same memory array is coupled to one bit line among the multiple bit lines, that is, the multiple bit lines in the same memory array are respectively coupled to multiple second nodes 2.
  • each sense amplifier in the plurality of sense amplifiers includes a first terminal 1, and the first end 1 of each sense amplifier is coupled to one of the plurality of bit lines;
  • each write-back circuit in the plurality of write-back circuits (for example, WR1 to WR3 in the first memory array, or WR4 to WR6 in the second memory array) further includes a second end 2 and a third end 3, and the second end 2 of each write-back circuit is connected to the plurality of bit lines (for example, BL1 to BL3, or BL4 to BL6), the third terminal 3 of each write-back circuit is coupled to the second node 2 of the corresponding column.
  • multiple bit lines of each storage array (for example, BL1 to BL3 of the first storage array, or BL4 to BL6 of the second storage array) are respectively coupled to multiple second nodes 2 of the storage array. At this time, as shown in FIG.
  • each sense amplifier in the plurality of sense amplifiers includes a first terminal 1
  • each write-back circuit in the plurality of write-back circuits further includes a second end 2 and a third end 3, and the first end 1 of the sense amplifier shared by the same column in each memory array is coupled to the second end 2 of the write-back circuit, and the third end 3 of each write-back circuit is coupled to the second node 2 of the corresponding column
  • Each first node 1 is coupled to the ground terminal (that is, multiple first nodes 1 are coupled to the ground terminal).
  • the sense amplifier in the embodiment of the present application may be a voltage-type sense amplifier, and the function of the voltage-type sense amplifier and the voltage-type sense amplifier in a traditional DRAM may be completely consistent.
  • the voltage-type sense amplifier may include four transistors T1 to T4, the gate of the transistor T1 and the gate of the transistor T2 are coupled to the node P0, the gate of the transistor T3 and the gate of the transistor T4 are coupled to the node P1, one pole of the transistor T1, one pole of the transistor T2 are coupled to the node P1, one pole of the transistor T3, one pole of the transistor T4 are coupled to the node P0, the other pole of the transistor T1 and the other pole of the transistor T3 are coupled to the node P2, and the other pole of the transistor T2 The other pole of transistor T4 is coupled to node P3.
  • the node P0 and the node P1 are respectively used as two first terminals 1 of the voltage-type sense amplifier for coupling and connection with the corresponding SFGT storage unit (for example, taking SA1 in FIG. 1 to T4 on and off.
  • One of the one and the other poles of each transistor is a source and the other is a drain.
  • the transistor T1 and the transistor T3 are NMOS transistors, and the transistor T2 and the transistor T4 are PMOS transistors.
  • the write-back circuit may include a PMOS transistor and an NMOS transistor.
  • the gate of the PMOS transistor is coupled to the gate of the NMOS transistor as the control terminal of the write-back circuit
  • one pole of the PMOS transistor is used as the second terminal 2 of the write-back circuit
  • one pole of the NMOS transistor is used as a voltage terminal of the write-back circuit
  • the other pole of the PMOS transistor is coupled to the other pole of the NMOS transistor as the third terminal 3 of the write-back circuit.
  • One source and the other of the one pole and the other pole of the PMOS transistor are drains; similarly, one source and the other of the one pole and the other pole of the NMOS transistor are drains.
  • the storage array of the memory includes SFGT memory cells in multiple rows and columns.
  • the SFGT memory cells in the memory array are coupled with corresponding signal lines (i.e., word lines, write-back control lines, voltage lines, and bit lines, etc.), sense amplifiers, and write-back circuits according to the distribution of rows and columns, so that the memory can realize the function of traditional DRAM.
  • signal lines i.e., word lines, write-back control lines, voltage lines, and bit lines, etc.
  • sense amplifiers i.e., sense amplifiers, and write-back circuits according to the distribution of rows and columns, so that the memory can realize the function of traditional DRAM.
  • Compared with traditional DRAM it has the advantages of fast operation speed, small unit area, high chip density, low operating voltage for data storage, and strong data retention ability.
  • the memory can use a voltage-type sense amplifier with a smaller area to buffer (or latch) data, thereby further reducing the area of the memory and increasing storage density.
  • the above mainly introduces the related structure of the memory provided by the embodiment of the present application.
  • the timing control method when using the traditional DRAM operation flow to read and write the memory is described below in combination with the memory shown in FIG. 5 and FIG. 6 .
  • the timing control method includes the following steps S11 - S13 .
  • the timing of different signal lines corresponding to the timing control method is shown in FIG. 7 .
  • control the first word line for example, WL11
  • control the multiple write-back control lines for example, CL1 to CL3
  • control the multiple voltage lines for example, VL1 to VL3 corresponding to the SFGT of the target row to be at a high level and switch to a low level after a period of time.
  • the method further includes: in the row activation phase, controlling the second word line (for example, WL21 ) corresponding to the SFGT memory cells in the target row to be at a high level.
  • the memory includes multiple first word lines and multiple second word lines as an example for description.
  • the controller of the memory can send an activation instruction (also called a row activation instruction) to the memory, and the activation instruction can carry the address of the target row; when the memory receives the activation instruction, the memory enters the row activation stage.
  • the row activation phase may include a first sub-phase and a second sub-phase, the first sub-phase is used to read the data in the SFGT memory cells of the target row into the sense amplifier corresponding to the target row, and the second sub-phase is used to erase the data in the SFGT memory cells of the target row.
  • the first word line and the second word line (for example, WL11 and WL21) corresponding to the SFGT memory cells of the target row are controlled to be high level
  • the multiple writeback control lines (for example, CL1 to CL3) corresponding to the SFGT of the target row are controlled to be high level
  • the multiple voltage lines (for example, VL1 to VL3) corresponding to the SFGT of the target row are controlled to be high level.
  • the first word line and the second word line (for example, WL11 and WL21) corresponding to the SFGT memory cells of the target row are controlled to be at a high level
  • the multiple write-back control lines (for example, CL1 to CL3) corresponding to the SFGTs of the target row are controlled to be at a high level
  • the multiple voltage lines (for example, VL1 to VL3) corresponding to the SFGTs of the target row are controlled to be at a low level.
  • the memory after receiving the activation instruction, the memory performs two operations of row activation and erasing in the row activation phase, so it can be understood that the activation command hides (or carries) an erase command, and then completes the erasing operation that the SFGT storage unit needs to perform in the row activation phase.
  • the controller the controller The operation process used to control the SFGT-based memory is consistent with the operation process used to control the traditional DRAM, thereby achieving compatibility with the controller and control commands of the traditional DRAM.
  • the corresponding voltage value when the first word line and the second word line are at a high level, the corresponding voltage value may be a positive value, for example, when the first word line WL11 is at a high level, the corresponding voltage value is 0.8V, and when the second word line WL21 is at a high level, the corresponding voltage value is 1V.
  • the corresponding voltage value can be a negative value.
  • the corresponding voltage value when the first word line WL11 is at low level, the corresponding voltage value is -2V, and when the second word line WL21 is at low level, the corresponding voltage value is -1.2V.
  • the write-back control line is at a high level, the corresponding voltage value is positive.
  • the corresponding voltage value is 1V.
  • the corresponding voltage value is 0, for example, when the write-back control lines CL1 to CL3 are at low level, the corresponding voltage value is 0V.
  • the corresponding voltage values are positive.
  • the corresponding voltage values are 1V or 0.5V.
  • the corresponding voltage value is 0V.
  • the voltage value corresponding to the first word line and the voltage value corresponding to the second word line may be equal or different.
  • the voltage value corresponding to the first word line is equal to the voltage value corresponding to the second word line (for example, the voltage values corresponding to the first word line WL11 and the second word line WL21 are both 1V)
  • the erasing of the second sub-stage can be made cleaner, and at the same time, the number of corresponding operating voltage groups can be reduced, power supply design can be simplified, voltage switching can be reduced, and operational performance can be improved.
  • the voltage value corresponding to the first word line may be smaller than the voltage value corresponding to the second word line, for example, the voltage value corresponding to the first word line WL11 is 0.8V, and the voltage value corresponding to the second word line WL21 is 1V.
  • the target row is the first row
  • the first word line corresponding to the three SFGT memory cells in the first row is WL11
  • the corresponding second word line is WL21
  • control WL11 to 0.8V control WL21 to 1V
  • control CL1 to CL3 to 1V control VL1 to VL3 to 1V for a period of time
  • switch to 0V for a period of time for example, 5ns.
  • the method further includes: controlling the second word line (for example, WL21 ) corresponding to the SFGT memory cells in the target row to be at low level during the read/write phase.
  • the memory includes multiple first word lines and multiple second word lines as an example for description.
  • the controller of the memory can send a read command or a write command to the memory, and the read command or the write command can carry the column address of the target SFGT storage unit.
  • control the first word line and the second word line for example, WL11 and WL21
  • control a plurality of write-back control lines for example, CL1 to CL3
  • control a plurality of voltage lines for example, VL1 to VL3 corresponding to the SFGT of the target row to be at any level (that is, control the plurality of voltage lines can be high level or low level ).
  • the memory receives a read command, through the above control, the data of the target SFGT storage unit in the sense amplifier corresponding to the target row can be output, and at the same time, the data of the target row in the sense amplifier can be written back into the SFGT storage unit corresponding to the target row. If the memory receives a write command, through the above control, the target data can be written into the sense amplifier corresponding to the target row, and the data of the target row in the sense amplifier can be written back into the SFGT storage unit corresponding to the target row.
  • the data of the target row in the sense amplifier when the data of the target row in the sense amplifier is written back into the SFGT storage unit corresponding to the target row, if the data of the target row includes “1” and “0” at the same time, all the data of the target row in the sense amplifier can be written into the corresponding SFGT storage unit through the operations corresponding to writing “1” and “0” respectively, or only “1” in the data of the target row can be selected to be written into the corresponding SFGT storage unit through the operation corresponding to writing “1”.
  • the method further includes: in the precharging phase, controlling the second word lines (for example, WL21 ) corresponding to the SFGT memory cells in the target row to be at a high level.
  • the memory includes multiple first word lines and multiple second word lines as an example for description.
  • the controller of the memory may send a precharging instruction to the memory.
  • control the first word line for example, WL11
  • the second word line for example, WL21
  • control a plurality of write-back control lines for example, CL1 to CL3
  • control a plurality of voltage lines for example, VL1 to VL3
  • Precharge a plurality of bit lines for example, BL1 to BL3 ) corresponding to the SFGT memory cells in the target row, so as to set the source S of the SFGT memory cells in the target row to quasi-static ground.
  • the voltage values corresponding to the multiple voltage lines when the pre-charging phase is high level are lower than the voltage values corresponding to the multiple voltage lines when the row activation phase is high level.
  • the corresponding voltage value of the plurality of voltage lines VL1 to VL3 in the row activation phase is 1V
  • the corresponding voltage value of the plurality of voltage lines VL1 to VL3 in the pre-charging phase is 0.5V.
  • the target row is the first row
  • the first word line corresponding to the three SFGT memory cells in the first row is WL11
  • the corresponding second word line is WL21
  • the timing control method includes the following steps S21 - S23 .
  • the timing of different signal lines corresponding to the timing control method is shown in FIG. 9 .
  • control the first word line for example, WL11
  • control the multiple write-back control lines for example, CL1 to CL3
  • control the multiple voltage lines at a low level when the multiple write-back control lines (for example, VL1 to VL3) corresponding to the SFGT of the target row are at a high level.
  • the method further includes: in the row activation phase, controlling the second word line (for example, WL21 ) corresponding to the SFGT memory cells in the target row to be at a high level.
  • the memory includes multiple first word lines and multiple second word lines as an example for description.
  • the controller of the memory can send an activation instruction (also called a row activation instruction) to the memory, and the activation instruction can carry the address of the target row; when the memory receives the activation instruction, the memory enters the row activation stage.
  • the row activation phase may include a first sub-phase and a second sub-phase, the first sub-phase is used to read the data in the SFGT memory cells of the target row into the sense amplifier corresponding to the target row, and the second sub-phase is used to erase the data in the SFGT memory cells of the target row.
  • the first word line and the second word line (for example, WL11 and WL21) corresponding to the SFGT memory cells of the target row are controlled to be at a high level
  • a plurality of writeback control lines (for example, CL1 to CL3) corresponding to the SFGT of the target row are controlled to be at a low level
  • a plurality of voltage lines (for example, VL1 to VL3) corresponding to the SFGT of the target row are controlled to be at any level (that is, the plurality of voltage lines can be controlled to be at a high level or at a low level).
  • the first word line and the second word line (for example, WL11 and WL21) corresponding to the SFGT memory cells of the target row are controlled to be at a high level
  • the multiple write-back control lines (for example, CL1 to CL3) corresponding to the SFGTs of the target row are controlled to be at a high level
  • the multiple voltage lines (for example, VL1 to VL3) corresponding to the SFGTs of the target row are controlled to be at a low level.
  • the memory after receiving the activation instruction, the memory performs two operations of row activation and erasing in the row activation phase, so it can be understood that the activation command hides (or carries) an erase command, and then completes the erasing operation that the SFGT storage unit needs to perform in the row activation phase.
  • the controller the controller The operation process used to control the SFGT-based memory is consistent with the operation process used to control the traditional DRAM, thereby achieving compatibility with the controller and control commands of the traditional DRAM.
  • the corresponding voltage value when the first word line and the second word line are at high level, can be a positive value, for example, when the first word line WL11 is at high level, the corresponding voltage value is 0.8V, and when the second word line WL21 is at high level, the corresponding voltage value is 1V.
  • the corresponding voltage value can be a negative value.
  • the corresponding voltage value when the first word line WL11 is at low level, the corresponding voltage value is -2V, and when the second word line W21 is at low level, the corresponding voltage value is -1.2V.
  • the write-back control line is at a high level, the corresponding voltage value is positive.
  • the corresponding voltage value when the write-back control lines CL1 to CL3 are at a high level, the corresponding voltage value is 1V.
  • the corresponding voltage value When the write-back control line is at low level, the corresponding voltage value is 0, that is, when the write-back control lines CL1 to CL3 are at low level, the corresponding voltage value is 0V.
  • the voltage line is at low level, the corresponding voltage value is 0, that is, when the voltage lines VL1 to VL3 are at low level, the corresponding voltage value is 0V.
  • the voltage value corresponding to the first word line and the voltage value corresponding to the second word line may be equal or different.
  • the voltage value corresponding to the first word line is equal to the voltage value corresponding to the second word line (for example, the voltage values corresponding to the first word line and the second word line (for example, WL11 and WL21) are both 1V)
  • the erasing of the second sub-stage can be made cleaner, and at the same time, the number of corresponding operating voltage groups can be reduced, power supply design can be simplified, voltage switching can be reduced, and operational performance can be improved.
  • the voltage value corresponding to the first word line may be smaller than the voltage value corresponding to the second word line, for example, the voltage value corresponding to the first word line WL11 is 0.8V, and the voltage value corresponding to the second word line WL21 is 1V.
  • the method further includes: controlling the second word line (for example, WL21 ) corresponding to the SFGT memory cells in the target row to be at a low level during the read/write phase.
  • the memory includes multiple first word lines and multiple second word lines as an example for description.
  • the controller of the memory may send a read command or a write command to the memory, and the read command or the write command may carry the column address of the target SFGT storage unit.
  • control the first word line and the second word line for example, WL11 and WL21
  • control the multiple write-back control lines for example, CL1 to CL3
  • control the multiple voltage lines for example, VL1 to VL3 corresponding to the SFGT of the target row to be at any level.
  • the memory receives a read command, through the above control, the data of the target SFGT storage unit in the sense amplifier corresponding to the target row can be output, and at the same time, the data of the target row in the sense amplifier can be written back into the SFGT storage unit corresponding to the target row. If the memory receives a write command, through the above control, the target data can be written into the sense amplifier corresponding to the target row, and the data of the target row in the sense amplifier can be written back into the SFGT storage unit corresponding to the target row.
  • the data of the target row in the sense amplifier is written back into the SFGT storage unit corresponding to the target row, if the data of the target row includes “1” and “0” at the same time, all the data of the target row can be written into the corresponding SFGT storage unit through the operations corresponding to writing “1” and “0” respectively, or only “1” in the data of the target row can be selected to be written into the corresponding SFGT storage unit through the operation corresponding to writing “1”.
  • the method further includes: in the precharging phase, controlling the second word lines (for example, WL21 ) corresponding to the SFGT memory cells in the target row to be at a high level.
  • the controller of the memory may send a precharging instruction to the memory.
  • control the first word line for example, WL11
  • the second word line for example, WL21
  • control a plurality of write-back control lines for example, CL1 to CL3
  • control a plurality of voltage lines for example, VL1 to VL3
  • Precharge a plurality of bit lines for example, BL1 to BL3 ) corresponding to the SFGT memory cells in the target row, so as to set the drain D of the SFGT memory cells in the target row to a read voltage
  • the read voltage may be 0.5V.
  • the target row is the first row
  • the first word line corresponding to the three SFGT memory cells in the first row is WL11
  • the corresponding second word line is WL21
  • two operations of row activation and erasing are completed by controlling the voltage of the corresponding signal line in the memory during the row activation phase, so as to complete the erasing operation that the SFGT memory cell needs to perform during the row activation phase, and at the same time, the corresponding read and write operations and precharge operations are completed by controlling the voltage of the corresponding signal line during the read and write phase and the precharge phase, so as to realize the read and write of the SFGT-based memory.
  • the operation flow of the controller for controlling the SFGT-based memory is consistent with the operation flow for controlling the traditional DRAM, thereby realizing compatibility with the controller and control instructions of the traditional DRAM, improving the operation performance and reducing the operation delay.
  • using the timing control method can also avoid the impact on the original function or structure of other hardware circuits related to the DRAM when the memory is used to replace the traditional DRAM, and reduce the cost and complexity of replacing the traditional DRAM.
  • an embodiment of the present application further provides an electronic device, the electronic device includes a processor and a memory, the memory includes a controller, and a storage array composed of semi-floating gate transistor SFGT storage units, the processor is used to send an access request to the storage array to the controller based on the DDR interface protocol, the controller is used to read and write data from the storage array according to the access request, and the controller is also used to erase the data in the SFGT storage unit in the storage array during the read and write process.
  • the original DDR storage array is replaced with a storage array composed of SFGT storage units.
  • the processor can still send an access request based on the DDR interface protocol to the controller in the memory, that is, the processor can still access the storage array composed of SFGT storage units through the controller based on the original DDR access method.
  • the controller can read and write data from the storage array, and execute the operation of erasing the data in the SFGT storage unit in the storage array during the read and write process, that is, the controller can read and write data from the storage array composed of SFGT storage units based on the original DDR access request and complete the required erase operation of the SFGT storage unit. Therefore, the electronic device can use a storage array composed of SFGT memory cells to cache data without affecting the function and architecture of the original processor, so that the electronic device has the advantages of fast read and write speed, small size, low read and write voltage, and strong data retention capabilities. At the same time, it can also reduce the cost and complexity of replacing the original DDR with a memory based on SFGT memory cells.
  • the memory also includes a sense amplifier SA, and the controller performs the following actions according to the access request: read the data in the SFGT storage unit of the target row to the SA; erase the data in the SFGT storage unit of the target row; output the target data in the SA, and write back the data in the SA to the SFGT storage unit of the target row, and the data in the SA includes the target data; .
  • SA sense amplifier
  • the controller is further configured to set the SFGT storage cells of the target row to a holding state, and precharge the bit line corresponding to the SFGT storage cells of the target row.
  • the embodiment of the present application also provides an electronic device, the electronic device includes a printed circuit board (printed circuit board, PCB) and a memory connected to the printed circuit board, and the memory may be any memory provided above.
  • the printed circuit board is used to provide electrical connections for the electronic components included in the memory.
  • the electronic device may be different types of user equipment or terminal devices such as computers, mobile phones, tablet computers, wearable devices, and vehicle-mounted devices; the electronic device may also be network devices such as base stations.
  • the electronic device may further include a packaging substrate, the packaging substrate is fixed on the printed circuit board PCB through solder balls, and the memory is fixed on the packaging substrate through solder balls.
  • the packaging substrate is used to package the memory.
  • an electronic device in another aspect of the present application, includes a controller and a memory, the controller is used to control reading and writing in the memory, and the memory can be any memory provided above.
  • an electronic device in another aspect of the present application, includes: a processor and a memory coupled to each other, where the memory is any memory provided above.
  • the electronic device further includes a cache and a controller.
  • the processor, the cache, the controller, and the memory may be integrated together, and the memory may be coupled to the cache through the controller, and coupled to the processor through the cache.

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Abstract

一种存储器、时序控制方法及电子设备，涉及存储技术领域，用于替代传统DRAM，同时兼容DRAM的控制指令，提升操作性能。该存储器中多行多列的SFGT存储单元按照行列分布与相应的信号线、感应放大器和回写电路相耦合。该时序控制方法包括：在行激活阶段，控制目标行的SFGT存储单元对应的第一字线为高电平，控制目标行的SFGT存储单元对应的多个回写控制线为高电平，控制目标行的SFGT存储单元对应的多个电压线为高电平且持续一段时间后转换为低电平，以在行激活阶段执行行激活和擦除两个操作；在读写阶段，控制目标行的SFGT存储单元对应的第一字线为低电平，控制目标行的SFGT存储单元对应的多个回写控制线为低电平，以实现数据的读写。

Description

一种存储器、时序控制方法及电子设备
本申请要求于2022年01月20日提交国家知识产权局、申请号为202210065884.3、申请名称为“一种存储器、时序控制方法及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及存储技术领域，尤其涉及一种存储器、时序控制方法及电子设备。
背景技术
在计算系统中，动态随机存取存储器(dynamic random access memory，DRAM)作为内存，用于暂存中央处理器(central processing unit，CPU)的运算数据，以及与硬盘等外部存储器交换的数据。传统的基于晶体管和存储电容作为存储单元的DRAM的发展面临前所未有的技术挑战，比如存在以下问题：晶体管驱动电流太小、漏电流增大；存储电容越来越小，导致数据保持时间缩短，功耗增加；工艺复杂，成本急剧上升等。由于传统的DRAM技术发展面临上述的瓶颈，已经难以满足市场需求，因此亟需一种新型的存储器。
发明内容
本申请提供一种存储器、时序控制方法及电子设备，解决了基于晶体管和存储电容作为存储单元的DRAM所面临的问题。
为达到上述目的，本申请采用如下技术方案：
第一方面，提供一种存储器，该存储器包括：存储阵列、多个感应放大器和多个回写电路，该存储阵列包括多行多列的半浮栅晶体管SFGT存储单元、多个第一字线、多个回写控制线和多个电压线；其中，该SFGT存储单元具有控制栅极、源极和漏极，该存储阵列中属于同一行的该SFGT存储单元的控制栅极共用该多个第一字线中的一个第一字线，属于同一列的该SFGT存储单元的源极相耦合且耦合点可以为第一节点，属于同一列的SFGT存储单元的漏极相耦合且耦合点可以为第二节点；该存储阵列中同一列的该SFGT存储单元还共用该多个感应放大器中的一个感应放大器、以及该多个回写电路中的一个回写电路；该多个回写电路中每个回写电路包括控制端和电压端，每个回写电路的控制端与该多个回写控制线中的一个回写控制线耦合，每个回写电路的电压端与该多个电压线中的一个电压线耦合；该多个感应放大器，用于在读写过程中缓存该存储阵列中的数据；该多个回写电路，用于在读写过程中将该多个感应放大器中缓存的数据对应回写到该存储阵列中。
上述技术方案中，该存储器的存储阵列包括多行多列的SFGT存储单元，该存储阵列中的SFGT存储单元按照行列分布与相应的信号线(即字线、回写控制线和电压线等)、感应放大器和回写电路相耦合，以使该存储器能够实现传统DRAM的功能，同时由于SFGT具有操作速度快、面积小、对数据存储时操作电压低、以及数据保持能力强等众多优点，从而基于该SFGT形成的存储器与传统DRAM相比，具有操作速度快、单元面积小、芯片密度高、对数据存储时操作电压低、以及数据保持能力强等优点。
在第一方面的一种可能的实现方式中，该存储器还包括多个位线，每个第一节点与该多个位线中的一个位线耦合；该多个感应放大器中的每个感应放大器包括第一端，每个感 应放大器的第一端与该多个位线中的一个位线耦合；该多个回写电路中的每个回写电路还包括第二端和第三端，每个回写电路的第二端与该多个位线中的一个位线耦合，每个回写电路的第三端与对应列的该第二节点耦合。上述可能的实现方式中，通过将每个第一节点与该多个位线中的一个位线耦合，可以使得SFGT存储单元的源极与对应的感应放大器耦合，从而在进行读写操作时，能够基于传统DRAM的控制指令，通过该源极将SFGT存储单元中的数据写入感应放大器，以及将感应放大器中的数据写回SFGT存储单元中，实现与传统DRAM的控制器和控制指令的兼容。
在第一方面的一种可能的实现方式中，该存储器还包括多个位线，每个第二节点与该多个位线中的一个位线耦合，每个该第一节点与接地端耦合；该多个感应放大器中的每个感应放大器包括第一端；该多个回写电路中的每个回写电路还包括第二端和第三端，同一列共用的感应放大器的第一端和回写电路的第二端耦合，每个回写电路的第三端与对应列的该第二节点耦合。上述可能的实现方式中，通过将每个第二节点与该多个位线中的一个位线耦合，可以使得SFGT存储单元的漏极与对应的感应放大器耦合，从而在进行读写操作时，能够基于传统DRAM的控制指令，通过该漏极将SFGT存储单元中的数据写入感应放大器，以及将感应放大器中的数据写回SFGT存储单元中，实现与传统DRAM的控制器和控制指令的兼容。
在第一方面的一种可能的实现方式中，每个回写电路包括：P型金属氧化半导体PMOS管和N型金属氧化半导体NMOS管；其中，该PMOS管的栅极和该NMOS管的栅极相耦合作为该回写电路的控制端，该PMOS管的一极作为该回写电路的第二端，该NMOS管的一极作为该回写电路的电压端，该PMOS管的另一极和该NMOS管的另一极相耦合作为该回写电路的第三端，该一极和该另一极中的一个为源极、另一个为漏极。上述可能的实现方式中，提供了一种简单有效的回写电路，通过该回写电路可以实现数据的回写，同时使得该存储器可以使用面积较小的电压型感应放大器进行数据的缓存，从而进一步降低该存储器的面积、提高存储密度。
在第一方面的一种可能的实现方式中，该SFGT存储单元还具有分栅极，该存储器还包括多个第二字线；其中，该存储阵列中属于同一行的该SFGT存储单元的分栅极共用该多个第二字线中的一个第二字线。上述可能的实现方式中，当该存储器中的SFGT存储单元还具有分栅极和多个第二字线时，通过控制该多个第二字线与上述其他信号线，可以使得该存储器的读写操作更准确。
在第一方面的一种可能的实现方式中，该存储器包括共有该多个感应放大器的第一存储阵列和第二存储阵列，第一存储阵列中的一列SFGT存储单元和第二存储阵列中的一列SFGT存储单元共有该多个感应放大器中的一个感应放大器，第一存储阵列和第二存储阵列分别对应独立的多个回写电路。上述可能的实现方式中，第一存储阵列中的一列SFGT存储单元和第二存储阵列中的一列SFGT存储单元共有一个感应放大器，这样该感应放大器在对一列在的SFGT存储单元进行数据缓存时可以使用另一列的SFGT存储单元的电压作为参考，从而避免了单独设置参考电压的问题，减小了面积和成本。
在第一方面的一种可能的实现方式中，该感应放大器为电压型感应放大器。上述可能的实现方式中，该存储器通过使用面积较小的电压型感应放大器进行数据的缓存，可以进一步降低该存储器的面积、提高存储密度。
在第一方面的一种可能的实现方式中，该存储器包括动态随机存取存储器DRAM。
第二方面，提供一种时序控制方法，应用于上述第一方面或第一方面的任一种可能的实现方式所提供的存储器中，该方法包括：在行激活阶段，控制目标行的SFGT存储单元对应的第一字线为高电平，控制该多个回写控制线为高电平，控制该多个电压线为高电平且持续一段时间后转换为低电平，以在行激活阶段完成行激活和擦除两个操作；在读写阶段，控制该第一字线为低电平，控制该多个回写控制线为低电平，以实现数据的读写操作。进一步的，在预充电阶段，控制该第一字线为低电平，控制该多个回写电压线和该多个电压线为高电平，以实现预充电操作。
上述技术方案中，通过在行激活阶段控制该存储器中相应的信号线的电压以完成行激活和擦除两个操作，以在行激活阶段完成SFGT存储单元需要执行的擦除操作，同时在读写阶段和预充电阶段通过控制相应的信号线的电压完成相应的读写操作和预充电操作，以实现对基于SFGT的存储器的读写。在整个时序控制过程中，对于控制器而言，该控制器用于控制基于SFGT的存储器的操作流程与用于控制传统DRAM的操作流程是一致性，进而实现与传统DRAM的控制器和控制指令的兼容，提升操作性能，降低操作时延。此外，使用该时序控制方法还可以避免使用该存储器替代传统DRAM时对DRAM相关的其他硬件电路的原有功能或结构造成影响，降低替代传统DRAM的成本和复杂度。
在第二方面的一种可能的实现方式中，该SFGT存储单元还具有分栅极，该存储器还包括多个第二字线，该存储阵列中属于同一行的该SFGT存储单元的分栅极共用该多个第二字线中的一个第二字线；该方法还包括：在该行激活阶段，控制该目标行的SFGT存储单元对应的第二字线为高电平；在该读写阶段，控制该目标行的SFGT存储单元对应的第二字线为低电平。进一步的，在该预充电阶段，控制该目标行的SFGT存储单元对应的第二字线为高电平。上述可能的实现方式中，当该存储器中的SFGT存储单元还具有分栅极和多个第二字线时，通过控制该多个第二字线与上述其他信号线，可以使得该存储器的读写操作更准确。
在第二方面的一种可能的实现方式中，该第一字线和该第二字线为高电平时对应的电压值为正值，该第一字线和该第二字线为低电平时对应的电压值为负值；该多个回写控制线和该多个电压线为高电平时对应的电压值为正值，该多个回写控制线和该多个电压线为低电平时对应的电压值为0。上述可能的实现方式，能够降低该存储器在读写过程中的操作电压，从而降低功耗。
在第二方面的一种可能的实现方式中，在该行激活阶段，该第一字线和该第二字线为高电平时对应的电压值相等。上述可能的实现方式，能够在行激活阶段减少一组电压值，从而减小相应的电压转换，降低功耗。
在第二方面的一种可能的实现方式中，该多个电压线在该预充电阶段为高电平时对应的电压值低于该多个电压线在该行激活阶段为高电平时对应的电压值。上述可能的实现方式，能够降低该存储器在读写过程中的操作电压，从而降低功耗。
在第二方面的一种可能的实现方式中，在该读写阶段，当该目标行在对应的感应放大器中的数据存在“1”和“0”时，仅从将该数据中的“1”对应写入该目标行的SFGT存储单元中。上述可能的实现方式，能够减少该存储器在读写过程中的操作电压的组数，同时避免写数据“0”时对相邻的存储单元中数据的影响。
第三方面，提供一种时序控制方法，应用于上述第一方面或第一方面的任一种可能的实现方式所提供的存储器中，该方法包括：在行激活阶段，控制目标行的SFGT存储单元对应的第一字线为高电平，控制该多个回写控制线为低电平且持续一段时间后转换为高电平，以及在该多个回写控制线为高电平时控制该多个电压线为低电平，以在行激活阶段完成行激活和擦除两个操作；在读写阶段，控制该第一字线低电平，控制该多个回写控制线为低电平，以实现数据的读写操作。进一步的，在预充电阶段，控制该第一字线为低电平，控制该多个回写控制线为低电平，以实现预充电操作。
上述技术方案中，通过在行激活阶段控制该存储器中相应的信号线的电压以完成行激活和擦除两个操作，以在行激活阶段完成SFGT存储单元需要执行的擦除操作，同时在读写阶段和预充电阶段通过控制相应的信号线的电压完成相应的读写操作和预充电操作，以实现对基于SFGT的存储器的读写。在整个时序控制过程中，对于控制器而言，该控制器用于控制基于SFGT的存储器的操作流程与用于控制传统DRAM的操作流程是一致性，进而实现与传统DRAM的控制器和控制指令的兼容，提升操作性能，降低操作时延。此外，使用该时序控制方法还可以避免使用该存储器替代传统DRAM时对DRAM相关的其他硬件电路的原有功能或结构造成影响，降低替代传统DRAM的成本和复杂度。
在第三方面的一种可能的实现方式中，该SFGT存储单元还具有分栅极，该存储器还包括多个第二字线，该存储阵列中属于同一行的该SFGT存储单元的分栅极共用该多个第二字线中的一个第二字线；该方法还包括：在该行激活阶段，控制该目标行的SFGT存储单元对应的第二字线为高电平；在该读写阶段，控制该目标行的SFGT存储单元对应的第二字线为低电平；在该预充电阶段，控制该目标行的SFGT存储单元对应的第二字线为高电平。上述可能的实现方式中，当该存储器中的SFGT存储单元还具有分栅极和多个第二字线时，通过控制该多个第二字线与上述其他信号线，可以使得该存储器的读写操作更准确。
在第三方面的一种可能的实现方式中，该第一字线和该第二字线为高电平时对应的电压值为正值，该第一字线和该第二字线为低电平时对应的电压值为负值；该多个回写控制线和该多个电压线为高电平时对应的电压值为正值，该多个回写控制线和该多个电压线为低电平时对应的电压值为0。上述可能的实现方式，能够降低该存储器在读写过程中的操作电压，从而降低功耗。
在第三方面的一种可能的实现方式中，在该行激活阶段，该第一字线和该第二字线为高电平时对应的电压值相等。上述可能的实现方式，能够降低该存储器在读写过程中的操作电压，从而降低功耗。
在第三方面的一种可能的实现方式中，在该读写阶段，当该目标行在对应的感应放大器中的数据存在“1”和“0”时，仅从将该数据中的“1”对应写入该目标行的SFGT存储单元中。上述可能的实现方式，能够减少该存储器在读写过程中的操作电压的组数，同时避免写数据“0”时对相邻的存储单元中数据的影响。
第四方面，提供一种电子设备，该电子设备包括处理器和存储器，该存储器中包括控制器，以及由半浮栅晶体管SFGT存储单元组成的存储阵列，该处理器用于基于DDR接口协议向该控制器发出针对该存储阵列的访问请求，该控制器用于根据该访问请求从该存储阵列中读写数据，该控制器还用于在读写过程中擦除该存储阵列中的SFGT存储单元中 的数据。
上述技术方案中，将该电子设备中原有DDR的存储阵列替换为由SFGT存储单元组成的存储阵列，此时无需改变该电子设备中处理器的架构和访问指令，该处理器仍可以向存储器中的控制器发送基于DDR接口协议的访问请求，即该处理器仍可以基于原有DDR的访问方式通过该控制器访问SFGT存储单元组成的存储阵列。当该控制器接收到该访问请求时，该控制器可以从该存储阵列中读写数据，以及执行读写过程中擦除该存储阵列中的SFGT存储单元中的数据的操作，即该控制器能够基于原有DDR的访问请求，从SFGT存储单元组成的存储阵列读写数据并完成SFGT存储单元所需的擦除操作。因此，该电子设备能够在不影响原有处理器的功能和架构的情况下，采用SFGT存储单元组成的存储阵列缓存数据，这样使得该电子设备具有读写速度快、体积小、读写电压低和数据保持能力强等优点，同时还能够降低将原有DDR替换为基于SFGT存储单元的存储器的成本和复杂度。
在第四方面的一种可能的实现方式中，该存储器中还包括感应放大器SA，该控制器根据该访问请求执行下述动作：将目标行的SFGT存储单元中的数据读取到该SA；擦除该目标行的SFGT存储单元中的数据；将该SA中的目标数据输出，并将该SA中的数据回写到该目标行的SFGT存储单元中，该SA中的数据包括该目标数据；或者，将目标数据写入该SA中，并将该SA中的数据回写到该目标行的SFGT存储单元中。
在第四方面的一种可能的实现方式中，在将该SA中的数据回写到该目标行的SFGT存储单元中之后，该控制器还用于将该目标行的SFGT存储单元设置为保持状态，并对该目标行的SFGT存储单元对应的位线进行预充电。
第五方面，提供一种电子设备，该电子设备包括电路板、以及与该电路板连接的存储器，该存储器包括第一方面或第一方面的任一种可能的实现方式所提供的存储器。
第六方面，提供一种电子设备，该电子设备包括控制器和存储器，该控制器用于控制该存储器的读写操作，该存储器包括第一方面或第一方面的任一种可能的实现方式所提供的存储器。
可以理解地，上述提供的任一种电子设备，其所能达到的有益效果可对应参考上文所提供的存储器和时序控制方法中的有益效果，此处不再赘述。
附图说明
图1为本申请实施例提供的一种电子设备的结构示意图；
图2为本申请实施例提供的一种SFGT的结构示意图；
图3为本申请实施例提供的一种传统DRAM的操作流程图；
图4为本申请实施例提供的一种存储器的结构示意图；
图5为本申请实施例提供的另一种存储器的结构示意图；
图6为本申请实施例提供的又一种存储器的结构示意图；
图7为本申请实施例提供的一种电压型感应放大器的结构示意图；
图8为本申请实施例提供的一种存储器的时序控制图；
图9为本申请实施例提供的另一种存储器的时序控制图。
具体实施方式
下文将详细论述各实施例的制作和使用。但应了解，本申请提供的许多适用发明概念 可实施在多种具体环境中。所论述的具体实施例仅仅说明用以实施和使用本说明和本技术的具体方式，而不限制本申请的范围。
除非另有定义，否则本文所用的所有科技术语都具有与本领域普通技术人员公知的含义相同的含义。
各电路或其它组件可描述为或称为“用于”执行一项或多项任务。在这种情况下，“用于”用来通过指示电路/组件包括在操作期间执行一项或多项任务的结构(例如电路系统)来暗指结构。因此，即使当指定的电路/组件当前不可操作(例如未打开)时，该电路/组件也可以称为用于执行该任务。与“用于”措辞一起使用的电路/组件包括硬件，例如执行操作的电路等。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。在本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，a和b，a和c，b和c或a、b和c，其中a、b和c可以是单个，也可以是多个。另外，在本申请的实施例中，“第一”、“第二”等字样并不对数量和次序进行限定。
需要说明的是，本申请中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
本申请的技术方案可以应用于包括存储器的各种电子设备中，比如，本申请的技术方案可以应用于计算机、平板电脑、笔记本电脑、手机、上网本、可穿戴设备、车载设备或者摄像设备等。本申请中的电子设备可以仅包括存储器，也可以同时包括处理器和存储器，该处理器可以为中央处理器(central processing unit，CPU)、人工智能(artificial intelligence，AI)处理器、数字信号处理器(digital signal processor)和神经网络处理器等。在实际应用中，该电子设备还可以包括通信模块、传感器模块、显示模块和输入输出模块等多个模块中的一个或者多个，本申请实施例对该电子设备的结构不作具体限制。
示例性的，图1为本申请实施例提供的一种电子设备的结构示意图，该电子设备可以包括存储器。可选的，该电子设备还可以包括CPU、缓存器(cache)和控制器等。其中，该CPU、缓存器、控制器和存储器可以集成在一起，存储器可以通过控制器与该缓存器耦合，以及通过该缓存器和该CPU相耦合。
本申请的技术方案所涉及的存储器可以包括动态随机存储器(dynamic random access memory，DRAM)。进一步，该DRAM可以包括同步动态随机存储器(synchronous dynamic random access memory，SDRAM)、双倍速率同步动态随机存储器(double data rate dynamic random access memory，DDR SRAM)和内存总线式动态随机存储器(rambus dynamic random access memory，RDRAM)等，DDR SRAM也可以简称为DDR。本申请实施例对此不再一一列举描述。
在电子设备中，DRAM作为内存，用于暂存处理器的运算数据、以及与硬盘等外部存储器交换的数据。而传统的基于晶体管和存储电容作为存储单元的DRAM的发展面临前所未有的技术挑战，比如存在以下问题：晶体管驱动电流太小、漏电流增大；存储电容越来越小，导致数据保持时间缩短，功耗增加；工艺复杂，成本急剧上升等。因此，亟需一种新型的存储器(也可以称为新型DRAM)来替代传统DRAM的功能。
基于此，本申请实施例提供一种存储器、以及该存储器的时序控制方法，用于替代传统DRAM的功能，同时该存储器还能够实现与传统DRAM的控制器和控制指令的兼容，即利用传统DRAM的控制器和控制指令可以实现对该存储器的读写操作，以尽可能避免使用该存储器替代传统DRAM时对DRAM相关的其他硬件电路的原有功能或结构造成影响，进而降低替代传统DRAM的成本和复杂度。本申请实施例提供的存储器是一种新型无电容的存储器件，采用与互补金属氧化物半导体(complementary metal oxide semiconductor，CMOS)工艺兼容的半浮栅晶体管(semi floating gate transistor，SFGT)作为存储单元，具有操作速度快、单元面积小、芯片密度高、对数据存储时操作电压低、以及数据保持能力强等优点。
下面对SFGT的结构和工作原理、以及传统DRAM的工作原理进行介绍说明。
图2为本申请实施例提供的一种SFGT的结构示意图，该SFGT包括衬底(bulk)、基于n-型半导体材料形成的源区和漏区、基于p+型半导体材料形成的半浮栅(semi floating gate，SFG)、控制栅极(control gate，CG)和分栅极(split gate，SG)，源区设置有源极(source，S)，漏区设置有漏极(drain，D)。其中，源区、漏区和半浮栅SFG均位于衬底上方，半浮栅SFG位于源区和漏区之间且半浮栅SFG远离衬底的一侧覆盖部分源区和漏区，控制栅极CG位于半浮栅SFG的上方，分栅极SG位于漏区D的上方。进一步的，该SFGT还可以包括隔离层和氧化层，该隔离层用于隔离不同的SFGT，该氧化层用于隔离该SFGT内部的不同部分。可选的，上述控制栅极CG和分栅极SG可以连接在一起合并为同一个栅极(此时可以称为控制栅极)，也可以是两个分开独立的栅极。图2中以控制栅极CG和分栅极SG是两个独立的栅极为例进行说明。
其中，SFGT通过半浮栅SFG、漏区和漏极D形成的嵌入式隧穿晶体管TFET进行数据的写入，通过半浮栅SFG和漏区形成的PN结进行擦除操作，图2中的(a)示出了SFGT写入“0”时的状态，图2中的(b)示出了SFGT写入“1”时的状态。当SFGT的半浮栅SFG上有较多空穴时，通过施加读偏置电压可以获取较大的漏源电流Ids，此时读取到数据“1”；当SFGT的半浮栅SFG上有较少空穴或者无空穴时，通过施加同样的读偏置电压可以获取较小的漏源电流Ids，此时读取到数据“0”。
具体的，将SFGT作为存储单元，对SFGT存储单元进行读\写时，需要对SFGT存储单元进行擦除(erase)(也可以称为/写入“0”)操作、读(read)操作、编程(program)(也可以称为写入“1”)操作和保持(hold)操作。上述操作都是通过设置控制栅极CG、分栅极SG和漏极D的操作电压来实现的，且写入“1”和写入“0”时对应设置的操作电压不同。
图3是对传统DRAM进行读写操作的操作流程图。如图3所示，在传统DRAM中，对DRAM存储单元进行读\写时，需要对DRAM存储单元进行激活(activate，ACT)操作、读(read)操作\写(write)操作、以及预充电(pre-charge，PRE)操作。其中，激活操作 用于选通某一字线(word line，WL)，以将选中行中的数据读取到感应放大器(sensor amplifier，SA)中；读操作用于输出SA中对应的目标数据，并将SA中的数据回写在对应的行中；写操作用于将目标数据写入SA，并将SA中的数据回写在对应的行中；预充电操作用于关断选通的WL，并对位线(bit line，BL)预充电。
其中，上述多个操作分别由DRAM控制器产生的激活指令、读指令\写指令、以及预充电指令来控制。此外，DRAM存储单元的数据都是从对应晶体管的漏极写入，写入“1”和写入“0”时对应设置的操作电压相同。
由上述内容可知，在利用基于SFGT的存储器来替代传统DRAM时，需要设计SFGT相应的存储器结构、以及利用传统DRAM的操作流程对该存储器进行读写操作时的时序控制方法，即需要提供一种基于SFGT的存储器和该控制器对应的时序控制方法。下面对该存储器和该时序控制方法进行详细介绍说明。
图4为本申请实施例提供的存储器的结构示意图，该存储器可以为DRAM。具体的，该存储器包括：存储阵列、多个感应放大器和多个回写电路。其中，多个感应放大器可用于在读写过程中缓存该存储阵列中的数据，该多个回写电路可用于在读写过程中将多个感应放大器中缓存的数据回写到该存储阵列中。
可选的，该存储器可以包括一个存储阵列，也可以包括两个存储阵列，图4中以一个存储阵列为例进行说明。当该存储器包括一个存储阵列时，该存储阵列中的每一列对应一个感应放大器和一个回写电路，该感应放大器用于缓存对应列的数据，且需要设置一个单独的参考线用于为该感应放大器提供参考电压。当该存储器包括两个存储阵列时，每个感应放大器在两个存储阵列中分别对应一列，即每个感应放大器对应两列且这两列分别位于不同的存储阵列，此时该感应放大器在缓存其中一列的数据时可以将另一列对应的连接端口上的电压作为参考电压，从而无需提供额外的参考电压。下面以该存储器包括两个存储阵列为例进行说明。
进一步的，参见图5和图6，该存储器包括第一存储阵列和第二存储阵列，每个存储阵列包括多行多列的半浮栅晶体管SFGT存储单元、多个第一字线、多个第二字线、多个回写控制线和多个电压线。图5和图6中，将第一存储阵列中的多个第一字线表示为WL11至WL12、多个第二字线表示为WL21至WL22、多个回写控制线表示为CL1至CL3、多个电压线表示为VL1至VL3；将第二存储阵列中的多个第一字线表示为WL13至WL14、多个第二字线表示为WL23至WL24、多个回写控制线表示为CL4至CL6、多个电压线表示为VL4至VL6。另外，将该存储器中的多个感应放大器表示为SA1至SA3，将第一存储阵列对应的多个回写电路表示为WR1至WR3，将第二存储阵列对应的多个回写电路表示为WR4至WR6。
其中，上述多行多列可以是指逻辑上的关系，具体可以是指逻辑上的一种“集合”或者“矩阵”，在实际物理排列上可以呈现多行多列，也可以不呈现多行多列。在实际应用中，只需多个SFGT存储单元的连接关系满足下文中关于同一行和同一列的SFGT存储单元的连接关系即可认为属于同一行或同一列。
另外，每个SFGT存储单元具有控制栅极、分栅极、源极和漏极，该存储阵列中属于同一行的SFGT存储单元的控制栅极CG共用该多个第一字线中的一个第一字线，属于同一行的SFGT存储单元的分栅极SG共用该多个第二字线中的一个第二字线，属于同一列 的SFGT存储单元的源极相耦合且耦合点可以为第一节点①，属于同一列的SFGT存储单元的漏极相耦合且耦合点可以为第二节点②。每个存储阵列中同一列的SFGT存储单元还共用该多个感应放大器中的一个感应放大器、以及该多个回写电路中的一个回写电路。该多个回写电路中每个回写电路包括控制端和电压端，每个回写电路的控制端与该多个回写控制线中的一个回写控制线耦合，每个回写电路的电压端与该多个电压线中的一个电压线耦合。所述控制端用于接收对应耦合的回写控制线传输的控制信号，以使回写电路基于该控制信号在数据读写过程中实现回写功能。所述电压端用于接收对应耦合的电压线传输的电压，以在数据读写过程中为回写电路提供相应的电压。
上述图5和图6中，仅以每个存储阵列包括2行3列的SFGT存储单元，该存储器包括3个感应放大器SA1至SA3和6个回写电路WR1至WR6为例进行说明，并不对本申请实施例构成限制。在实际应用中，该存储器可以包括更多数量的SFGT存储单元、感应放大器和回写电路，本申请实施例对此不作具体限制。
需要说明的是，上述SFGT存储单元的控制栅极和分栅极可以合并为一个栅极，且合并后的栅极可以称为控制栅极，此时上述存储器中的多个第一字线和多个第二字线也可以合并，合并后可以仅包括该多个第一字线，而不包括该多个第二字线。
进一步的，每个存储阵列还包括多个位线，比如，第一存储阵列包括三个位线且表示为BL1至BL3，第二存储阵列包括三个位线且表示为BL4至BL6。其中，同一存储阵列中的每个第一节点①与多个位线中的一个位线耦合，即同一存储阵列中的该多个位线分别与多个第一节点①耦合；或者，同一存储阵列中的每个第二节点②与多个位线中的一个位线耦合，即同一存储阵列中的该多个位线分别与多个第二节点②耦合。当同一存储阵列中的该多个位线分别与不同的节点耦合时，该多个感应放大器和对应的多个回写电路对应的耦合关系也会略有不同，下面分别通过图5和图6进行介绍说明。
在第一种可能的实施例中，每个存储阵列的多个位线分别与该存储阵列的多个第一节点①耦合。此时，如图5所示，该多个感应放大器(比如，SA1至SA3)中的每个感应放大器包括第一端1，每个感应放大器的第一端1与该多个位线中的一个位线耦合；该多个回写电路(比如，第一存储阵列中的WR1至WR3，或者第二存储阵列中的WR4至WR6)中的每个回写电路还包括第二端2和第三端3，每个回写电路的第二端2与该多个位线(比如，BL1至BL3、或BL4至BL6)中的一个位线耦合，每个回写电路的第三端3与对应列的第二节点②耦合。
在第二种可能的实施例中，每个存储阵列的多个位线(比如，第一存储阵列的BL1至BL3、或第二存储阵列的BL4至BL6)分别与该存储阵列的多个第二节点②耦合。此时，如图6所示，该多个感应放大器(比如，SA1至SA3)中的每个感应放大器包括第一端1，该多个回写电路(比如，第一存储阵列中的WR1至WR3，或者第二存储阵列中的WR4至WR6)中的每个回写电路还包括第二端2和第三端3，在每个存储阵列中同一列共用的感应放大器的第一端1和回写电路的第二端2耦合，每个回写电路的第三端3与对应列的第二节点②耦合，每个第一节点①与接地端耦合(即多个第一节点①与接地端耦合)。
进一步的，本申请实施例中的感应放大器可以为电压型感应放大器，且该电压型感应放大器与传统DRAM中的电压型感应放大器的功能可以完全一致。示例性的，如图7所示，该电压型感应放大器可以包括四个晶体管T1至T4，晶体管T1的栅极和晶体管T2的 栅极耦合于节点P0，晶体管T3的栅极和晶体管T4的栅极耦合于节点P1，晶体管T1的一极、晶体管T2的一极和节点P1耦合，晶体管T3的一极、晶体管T4的一极和节点P0耦合，晶体管T1的另一极和晶体管T3的另一极耦合于节点P2，晶体管T2的另一极和晶体管T4的另一极耦合于节点P3。其中，节点P0和节点P1分别作为该电压型感应放大器的两个第一端1，用于与对应的SFGT存储单元耦合连接(比如，以图5中的SA1为例，节点P0可用于连接BL1，节点P1可用于连接BL4；或者，以图6为例，节点P0可用于连接WR1的第二端2，节点P1可用于连接WR4的第二端2)，节点P2和节点P3为该电压型感应放大器的两个控制端，用于控制四个晶体管T1至T4的导通和关断。每个晶体管的一极和另一极中的一个为源极、另一个为漏极。可选的，晶体管T1和晶体管T3为N型金属氧化半导体NMOS管，晶体管T2和晶体管T4为P型金属氧化半导体PMOS管。
当该感应放大器为电压型感应放大器时，该回写电路可以包括一个PMOS管和一个NMOS管。其中，该PMOS管的栅极和该NMOS管的栅极相耦合作为该回写电路的控制端，该PMOS管的一极作为该回写电路的第二端2，该NMOS管的一极作为该回写电路的电压端，该PMOS管的另一极和该NMOS管的另一极相耦合作为该回写电路的第三端3。该PMOS管的一极和另一极中的一个源极、另一个为漏极；类似的，该NMOS管的一极和另一极中的一个源极、另一个为漏极。
本申请实施例提供的存储器中，该存储器的存储阵列包括多行多列的SFGT存储单元，该存储阵列中的SFGT存储单元按照行列分布与相应的信号线(即字线、回写控制线、电压线和位线等)、感应放大器和回写电路相耦合，以使该存储器能够实现传统DRAM的功能，同时由于SFGT具有操作速度快、面积小、对数据存储时操作电压低、以及数据保持能力强等众多优点，从而基于该SFGT形成的存储器与传统DRAM相比，具有操作速度快、单元面积小、芯片密度高、对数据存储时操作电压低、以及数据保持能力强等优点。此外，通过在该存储器中设置简单有效的回写电路，可以使得该存储器使用面积较小的电压型感应放大器进行数据的缓存(或锁存)，从而进一步降低该存储器的面积、提高存储密度。
上面主要介绍了本申请实施例提供的存储器的相关结构，下面结合图5和图6所示的存储器，对利用传统DRAM的操作流程对该存储器进行读写操作时的时序控制方法进行介绍说明。
在一种可能的实施例中，对于图4所示的存储器结构，该时序控制方法包括如下步骤S11-S13，该时序控制方法对应的不同信号线的时序如图7所示。
S11：在行激活阶段，控制目标行的SFGT存储单元对应的第一字线(比如，WL11)为高电平，控制该目标行的SFGT对应的多个回写控制线(比如，CL1至CL3)为高电平，控制该目标行的SFGT对应的多个电压线(比如，VL1至VL3)为高电平且持续一段时间后转换为低电平。可选的，当该存储器还包括上文所描述的多个第二字线时，该方法还包括：在行激活阶段，控制目标行的SFGT存储单元对应的第二字线(比如，WL21)为高电平。下面以该存储器同时包括多个第一字线和多个第二字线为例进行说明。
具体的，当需要对该存储器进行读写操作时，该存储器的控制器可以向该存储器发送激活指令(也可以称为行激活指令)，该激活指令中可以携带目标行的地址；当该存储器接收到该激活指令时，该存储器进入行激活阶段。其中，该行激活阶段可以包括第一子阶 段和第二子阶段，第一子阶段用于将目标行的SFGT存储器单元中的数据读取到目标行对应的感应放大器中，第二子阶段用于擦除目标行的SFGT存储器单元中的数据。在第一子阶段，控制目标行的SFGT存储单元对应的第一字线和第二字线(比如，WL11和WL21)为高电平，控制该目标行的SFGT对应的多个回写控制线(比如，CL1至CL3)为高电平，控制该目标行的SFGT对应的多个电压线(比如，VL1至VL3)为高电平。在第二子阶段，控制目标行的SFGT存储单元对应的第一字线和第二字线(比如，WL11和WL21)为高电平，控制该目标行的SFGT对应的多个回写控制线(比如，CL1至CL3)为高电平，控制该目标行的SFGT对应的多个电压线(比如，VL1至VL3)为低电平。
也即是，该存储器在接收到激活指令后，在行激活阶段执行了行激活和擦除两个操作，从而可以理解为该激活指令中隐藏(或携带)有擦除指令，进而在行激活阶段完成SFGT存储单元需要执行的擦除操作，而对于控制器而言，该控制器用于控制基于SFGT的存储器的操作流程与用于控制传统DRAM的操作流程是一致性，进而实现与传统DRAM的控制器和控制指令的兼容。
其中，当第一字线和第二字线为高电平时对应的电压值可以为正值，比如，第一字线WL11为高电平时对应的电压值为0.8V，第二字线WL21为高电平时对应的电压值为1V。当第一字线和第二字线为低电平时对应的电压值可以为负值，比如，第一字线WL11为低电平时对应的电压值为-2V，第二字线WL21为低电平时对应的电压值为-1.2V。当回写控制线为高电平时对应的电压值为正值，比如，回写控制线CL1至CL3为高电平时对应的电压值为1V。当回写控制线为低电平时对应的电压值为0，比如，回写控制线CL1至CL3为低电平时对应的电压值为0V。当电压线为高电平时对应的电压值为正值，比如，电压线VL1至VL3为高电平时对应的电压值为1V或者0.5V。当电压线为低电平时对应的电压值为0，比如，电压线VL1至VL3为低电平时对应的电压值为0V。
另外，在行激活阶段，第一字线和第二字线为高电平的情况下，此时该第一字线对应的电压值和该第二字线对应的电压值可以相等，也可以不等。当该第一字线对应的电压值和该第二字线对应的电压值相等(比如，该第一字线WL11和该第二字线WL21对应的电压值均为1V)时，可以使得第二子阶段的擦除更干净，同时还可以减少对应的操作电压组数，简化电源设计，减少电压切换，提升操作性能。当该第一字线对应的电压值和该第二字线对应的电压值不相等时，该第一字线对应的电压值可以小于该第二字线对应的电压值，比如，第一字线WL11对应的电压值为0.8V，第二字线WL21对应的电压值为1V。
示例性的，结合图5，如图8所示，假设目标行为第一行，且第一行的3个SFGT存储单元对应的第一字线为WL11、对应的第二字线为WL21，则在行激活阶段，控制WL11为0.8V，控制WL21为1V，控制CL1至CL3为1V，控制VL1至VL3为1V且持续一段时间后转换为0V并持续一段时间(比如持续5ns)。
S12：在读写阶段，控制该目标行的SFGT存储单元对应的第一字线(比如，WL11)为低电平，控制该目标行的SFGT对应的多个回写控制线(比如，CL1至CL3)为低电平。可选的，当该存储器还包括上文所描述的多个第二字线时，该方法还包括：在读写阶段，控制目标行的SFGT存储单元对应的第二字线(比如，WL21)为低电平。下面以该存储器同时包括多个第一字线和多个第二字线为例进行说明。
具体的，在读写阶段，该存储器的控制器可以向该存储器发送读指令或者写指令，该 读指令或者该写指令中可以携带目标SFGT存储单元的列地址。当该存储器接收到该读指令或者该写指令时，控制该目标行的SFGT存储单元对应的第一字线和第二字线(比如，WL11和WL21)为低电平，控制该目标行的SFGT对应的多个回写控制线(比如，CL1至CL3)为低电平，控制该目标行的SFGT对应的多个电压线(比如，VL1至VL3)为任意电平(即控制该多个电压线可以为高电平，也可以为低电平)。若该存储器接收到读指令，通过上述控制可以将目标行对应的感应放大器中目标SFGT存储单元的数据输出，同时将该感应放大器中目标行的数据回写入目标行对应的SFGT存储单元中。若该存储器接收到写指令，通过上述控制可以将目标数据写入目标行对应的感应放大器中，并将该感应放大器中目标行的数据回写入目标行对应的SFGT存储单元中。
示例性的，结合图5，如图8所示，假设目标行为第一行，且第一行的3个SFGT存储单元对应的第一字线为WL11、对应的第二字线为WL21，则在读写阶段，控制WL11为-2V，控制WL21为-1.2V，控制CL1至CL3为0V，控制VL1至VL3为任意电压(比如，控制VL1至VL3为0V或者1V)。
可选的，在将该感应放大器中目标行的数据回写入目标行对应的SFGT存储单元时，若该目标行的数据中同时包括“1”和“0”，可以分别通过写入“1”和写入“0”对应的操作将感应放大器中该目标行的所有数据写入对应的SFGT存储单元，也可以选择只通过写入“1”对应的操作将该目标行的数据中的“1”写入对应的SFGT存储单元。
S13：在预充电阶段，控制该目标行的SFGT存储单元对应的第一字线(比如，WL11)为低电平，控制该目标行的SFGT对应的多个回写控制线(比如，CL1至CL3)和该目标行的SFGT对应的多个电压线(比如，VL1至VL3)为高电平。可选的，当该存储器还包括上文所描述的多个第二字线时，该方法还包括：在预充电阶段，控制该目标行的SFGT存储单元对应的第二字线(比如，WL21)为高电平。下面以该存储器同时包括多个第一字线和多个第二字线为例进行说明。
具体的，在预充电阶段，该存储器的控制器可以向该存储器发送预充电指令。当该存储器接收到该预充电时，控制该目标行的SFGT存储单元对应的第一字线(比如，WL11)为低电平、第二字线(比如，WL21)为高电平，控制该目标行的SFGT对应的多个回写控制线(比如，CL1至CL3)为高电平，控制该目标行的SFGT对应的多个电压线(比如，VL1至VL3)为高电平，以将目标行设置为保持(hold)状态，并为该目标行的SFGT存储单元对应的多个位线(比如，BL1至BL3)预充电，以将该目标行的SFGT存储单元的源极S置为准静态地。
其中，该多个电压线在该预充电阶段为高电平时对应的电压值低于该多个电压线在该行激活阶段为高电平时对应的电压值。比如，该多个电压线VL1至VL3在该行激活阶段时对应的电压值为1V，该多个电压线VL1至VL3在该预充电阶段时对应的电压值为0.5V。
示例性的，结合图5，如图8所示，假设目标行为第一行，且第一行的3个SFGT存储单元对应的第一字线为WL11、对应的第二字线为WL21，则在预充电阶段，控制WL11为-2V，控制WL21为1V，控制CL1至CL3为1V，控制VL1至VL3为0.5V。
在另一种可能的实施例中，对于图6所示的存储器结构，该时序控制方法包括如下步骤S21-S23，该时序控制方法对应的不同信号线的时序如图9所示。
S21：在行激活阶段，控制目标行的SFGT存储单元对应的第一字线(比如，WL11) 为高电平，控制该目标行的SFGT对应的多个回写控制线(比如，CL1至CL3)为低电平且持续一段时间后转换为高电平，在该目标行的SFGT对应的多个回写控制线(比如，VL1至VL3)为高电平时控制该多个电压线为低电平。可选的，当该存储器还包括上文所描述的多个第二字线时，该方法还包括：在行激活阶段，控制该目标行的SFGT存储单元对应的第二字线(比如，WL21)为高电平。下面以该存储器同时包括多个第一字线和多个第二字线为例进行说明。
具体的，当需要对该存储器进行读写操作时，该存储器的控制器可以向该存储器发送激活指令(也可以称为行激活指令)，该激活指令中可以携带目标行的地址；当该存储器接收到该激活指令时，该存储器进入行激活阶段。其中，该行激活阶段可以包括第一子阶段和第二子阶段，第一子阶段用于将目标行的SFGT存储器单元中的数据读取到目标行对应的感应放大器中，第二子阶段用于擦除目标行的SFGT存储器单元中的数据。在第一子阶段，控制目标行的SFGT存储单元对应的第一字线和第二字线(比如，WL11和WL21)为高电平，控制该目标行的SFGT对应的多个回写控制线(比如，CL1至CL3)为低电平，控制该目标行的SFGT对应的多个电压线(比如，VL1至VL3)为任意电平(即控制该多个电压线可以为高电平，也可以为低电平)。在第二子阶段，控制目标行的SFGT存储单元对应的第一字线和第二字线(比如，WL11和WL21)为高电平，控制该目标行的SFGT对应的多个回写控制线(比如，CL1至CL3)为高电平，控制该目标行的SFGT对应的多个电压线(比如，VL1至VL3)为低电平。
也即是，该存储器在接收到激活指令后，在行激活阶段执行了行激活和擦除两个操作，从而可以理解为该激活指令中隐藏(或携带)有擦除指令，进而在行激活阶段完成SFGT存储单元需要执行的擦除操作，而对于控制器而言，该控制器用于控制基于SFGT的存储器的操作流程与用于控制传统DRAM的操作流程是一致性，进而实现与传统DRAM的控制器和控制指令的兼容。
其中，当第一字线和第二字线为高电平时对应的电压值可以为正值，比如，第一字线WL11为高电平时对应的电压值为0.8V，第二字线WL21为高电平时对应的电压值为1V。当第一字线和第二字线为低电平时对应的电压值可以为负值，比如，第一字线WL11为低电平时对应的电压值为-2V，第二字线W21为低电平时对应的电压值为-1.2V。当回写控制线为高电平时对应的电压值为正值，比如，回写控制线CL1至CL3为高电平时对应的电压值为1V。当回写控制线为低电平时对应的电压值为0，即回写控制线CL1至CL3为低电平时对应的电压值为0V。当电压线为低电平时对应的电压值为0，即电压线VL1至VL3为低电平时对应的电压值为0V。
另外，在行激活阶段，第一字线和第二字线为高电平的情况下，此时该第一字线对应的电压值和该第二字线对应的电压值可以相等，也可以不等。当该第一字线对应的电压值和该第二字线对应的电压值相等(比如，该第一字线和该第二字线(比如，WL11和WL21)对应的电压值均为1V)时，可以使得第二子阶段的擦除更干净，同时还可以减少对应的操作电压组数，简化电源设计，减少电压切换，提升操作性能。当该第一字线对应的电压值和该第二字线对应的电压值不相等时，该第一字线对应的电压值可以小于该第二字线对应的电压值，比如，第一字线WL11对应的电压值为0.8V，第二字线WL21对应的电压值为1V。
示例性的，结合图6，如图9所示，假设目标行为第一行，且第一行的3个SFGT存储单元对应的第一字线为WL11、对应的第二字线为WL21，则在行激活阶段，控制WL11为0.8V，控制WL21为1V，控制CL1至CL3为0V且持续一段时间后转换为1V并持续一段时间(比如持续5ns)，控制VL1至VL3为任意电压且在CL1至CL3为1V时控制VL1至VL3为0V。
S22：在读写阶段，控制该目标行的SFGT存储单元对应的第一字线(比如，WL11)为低电平，控制该目标行的SFGT对应的多个回写控制线(比如，CL1至CL3)为低电平。可选的，当该存储器还包括上文所描述的多个第二字线时，该方法还包括：在读写阶段，控制该目标行的SFGT存储单元对应的第二字线(比如，WL21)为低电平。下面以该存储器同时包括多个第一字线和多个第二字线为例进行说明。
具体的，在读写阶段，该存储器的控制器可以向该存储器发送读指令或者写指令，该读指令或者该写指令中可以携带目标SFGT存储单元的列地址。当该存储器接收到该读指令或者该写指令时，控制该目标行的SFGT存储单元对应的第一字线和第二字线(比如，WL11和WL21)为低电平，控制该目标行的SFGT对应的多个回写控制线(比如，CL1至CL3)为低电平，控制该目标行的SFGT对应的多个电压线(比如，VL1至VL3)为任意电平。若该存储器接收到读指令，通过上述控制可以将目标行对应的感应放大器中目标SFGT存储单元的数据输出，同时将该感应放大器中目标行的数据回写入目标行对应的SFGT存储单元中。若该存储器接收到写指令，通过上述控制可以将目标数据写入目标行对应的感应放大器中，并将该感应放大器中目标行的数据回写入目标行对应的SFGT存储单元中。
示例性的，结合图6，如图9所示，假设目标行为第一行，且第一行的3个SFGT存储单元对应的第一字线为WL11、对应的第二字线为WL21，则在读写阶段，控制WL11为-2V，控制WL21为-1.2V，控制CL1至CL3为0V，控制VL1至VL3为任意电平。
可选的，在将该感应放大器中目标行的数据回写入目标行对应的SFGT存储单元时，若该目标行的数据中同时包括“1”和“0”，可以分别通过写入“1”和写入“0”对应的操作将该目标行的所有数据写入对应的SFGT存储单元，也可以选择只通过写入“1”对应的操作将该目标行的数据中的“1”写入对应的SFGT存储单元。
S23：在预充电阶段，控制该目标行的SFGT存储单元对应的第一字线(比如，WL11)为低电平，控制该目标行的SFGT对应的多个回写控制线(比如，CL1至CL3)为低电平。可选的，当该存储器还包括上文所描述的多个第二字线时，该方法还包括：在预充电阶段，控制该目标行的SFGT存储单元对应的第二字线(比如，WL21)为高电平。
具体的，在预充电阶段，该存储器的控制器可以向该存储器发送预充电指令。当该存储器接收到该预充电时，控制该目标行的SFGT存储单元对应的第一字线(比如，WL11)为低电平、第二字线(比如，WL21)为高电平，控制该目标行的SFGT对应的多个回写控制线(比如，CL1至CL3)为低电平，控制该目标行的SFGT对应的多个电压线(比如，VL1至VL3)为任意电平，以将目标行设置为保持(hold)状态，并为该目标行的SFGT存储单元对应的多个位线(比如，BL1至BL3)预充电，以将该目标行的SFGT存储单元的漏极D置为读电压，比如，该读电压可以为0.5V。
示例性的，结合图6，如图9所示，假设目标行为第一行，且第一行的3个SFGT存 储单元对应的第一字线为WL11、对应的第二字线为WL21，则在预充电阶段，控制WL11为-2V，控制WL21为1V，控制CL1至CL3为0V，控制VL1至VL3为任意电平。
在本申请提供的时序控制方法中，通过在行激活阶段控制该存储器中相应的信号线的电压以完成行激活和擦除两个操作，以在行激活阶段完成SFGT存储单元需要执行的擦除操作，同时在读写阶段和预充电阶段通过控制相应的信号线的电压完成相应的读写操作和预充电操作，以实现对基于SFGT的存储器的读写。在整个时序控制过程中，对于控制器而言，该控制器用于控制基于SFGT的存储器的操作流程与用于控制传统DRAM的操作流程是一致性，进而实现与传统DRAM的控制器和控制指令的兼容，提升操作性能，降低操作时延。此外，使用该时序控制方法还可以避免使用该存储器替代传统DRAM时对DRAM相关的其他硬件电路的原有功能或结构造成影响，降低替代传统DRAM的成本和复杂度。
基于此，本申请实施例还提供一种电子设备，该电子设备包括处理器和存储器，该存储器中包括控制器，以及由半浮栅晶体管SFGT存储单元组成的存储阵列，该处理器用于基于DDR接口协议向该控制器发出针对该存储阵列的访问请求，该控制器用于根据该访问请求从该存储阵列中读写数据，该控制器还用于在读写过程中擦除该存储阵列中的SFGT存储单元中的数据。
本申请实施例提供的电子设备中，将原有DDR的存储阵列替换为由SFGT存储单元组成的存储阵列，此时无需改变该电子设备中处理器的架构和访问指令，该处理器仍可以向存储器中的控制器发送基于DDR接口协议的访问请求，即该处理器仍可以基于原有DDR的访问方式通过该控制器访问SFGT存储单元组成的存储阵列。当该控制器接收到该访问请求时，该控制器可以从该存储阵列中读写数据，以及执行读写过程中擦除该存储阵列中的SFGT存储单元中的数据的操作，即该控制器能够基于原有DDR的访问请求，从SFGT存储单元组成的存储阵列读写数据并完成SFGT存储单元所需的擦除操作。因此，该电子设备能够在不影响原有处理器的功能和架构的情况下，采用SFGT存储单元组成的存储阵列缓存数据，这样使得该电子设备具有读写速度快、体积小、读写电压低和数据保持能力强等优点，同时还能够降低将原有DDR替换为基于SFGT存储单元的存储器的成本和复杂度。
进一步的，该存储器中还包括感应放大器SA，该控制器根据该访问请求执行下述动作：将目标行的SFGT存储单元中的数据读取到该SA；擦除该目标行的SFGT存储单元中的数据；将该SA中的目标数据输出，并将该SA中的数据回写到该目标行的SFGT存储单元中，该SA中的数据包括该目标数据；或者，将目标数据写入该SA中，并将该SA中的数据回写到该目标行的SFGT存储单元中。
可选的，在将该SA中的数据回写到该目标行的SFGT存储单元中之后，该控制器还用于将该目标行的SFGT存储单元设置为保持状态，并对该目标行的SFGT存储单元对应的位线进行预充电。
在本申请的另一方面，本申请实施例还提供一种电子设备，该电子设备包括印刷电路板(printed circuit board，PCB)、以及与印刷电路板连接的存储器，该存储器可以为上文所提供的任一种存储器。其中，该印制电路板用于为该存储器中所包括的电子元器件提供电气连接。可选的，该电子设备可以为计算机、手机、平板电脑、可穿戴设备和车载设备 等不同类型的用户设备或者终端设备；该电子设备还可以为基站等网络设备。
可选的，该电子设备还可以包括封装基板，该封装基板通过焊球固定于印刷电路板PCB上，该存储器通过焊球固定于封装基板上。该封装基板用于封装该存储器。
在本申请的另一方面，还提供一种电子设备，该电子设备包括控制器和存储器，该控制器用于控制该存储器中的读写，该存储器可以为上文所提供的任一种存储器。
在本申请的另一方面，还提供一种电子设备，该电子设备包括：相互耦合的处理器和存储器，该存储器为上文所提供的任一种存储器。可选的，该电子设备还包括缓存器和控制器，该处理器、缓存器、该控制器和该存储器可以集成在一起，该存储器可以通过控制器与该缓存器耦合，以及通过该缓存器与该处理器耦合。
需要说明的是，上述关于该存储器和数据读写过程中不同信号线对应的时序控制的相关描述，均可对应援引到本申请所提供的电子设备中，具有描述可以参见上文所提供的存储器的相关描述，本申请实施例在此不再赘述。
最后应说明的是：以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (22)

  1. 一种存储器，其特征在于，所述存储器包括：存储阵列、多个感应放大器和多个回写电路，所述存储阵列包括多行多列的半浮栅晶体管SFGT存储单元、多个第一字线、多个回写控制线和多个电压线；
    其中，所述SFGT存储单元具有控制栅极、源极和漏极，所述存储阵列中属于同一行的所述SFGT存储单元的控制栅极共用所述多个第一字线中的一个第一字线，属于同一列的所述SFGT存储单元的源极相耦合，属于同一列的所述SFGT存储单元的漏极相耦合；
    所述存储阵列中同一列的所述SFGT存储单元还共用所述多个感应放大器中的一个感应放大器、以及所述多个回写电路中的一个回写电路；
    所述多个回写电路中每个回写电路包括控制端和电压端，每个回写电路的控制端与所述多个回写控制线中的一个回写控制线耦合，每个回写电路的电压端与所述多个电压线中的一个电压线耦合；
    所述多个感应放大器，用于在读写过程中缓存所述存储阵列中的数据；
    所述多个回写电路，用于将所述多个感应放大器中缓存的数据对应回写到所述存储阵列中。
  2. 根据权利要求1所述的存储器，其特征在于，所述存储器还包括多个位线，同一列的所述SFGT存储单元的源极还与所述多个位线中的一个位线耦合；
    所述多个感应放大器中的每个感应放大器包括第一端，每个感应放大器的第一端与所述多个位线中的一个位线耦合；
    所述多个回写电路中的每个回写电路还包括第二端和第三端，每个回写电路的第二端与所述多个位线中的一个位线耦合，每个回写电路的第三端与对应列的所述SFGT存储单元的漏极耦合。
  3. 根据权利要求1所述的存储器，其特征在于，所述存储器还包括多个位线，同一列的所述SFGT存储单元的漏极与所述多个位线中的一个位线耦合，同一列的所述SFGT存储单元的源极与接地端耦合；
    所述多个感应放大器中的每个感应放大器包括第一端；
    所述多个回写电路中的每个回写电路还包括第二端和第三端，同一列共用的感应放大器的第一端和回写电路的第二端耦合，每个回写电路的第三端与对应列的所述SFGT存储单元的漏极耦合。
  4. 根据权利要求2或3所述的存储器，其特征在于，每个回写电路包括：P型金属氧化半导体PMOS管和N型金属氧化半导体NMOS管；
    其中，所述PMOS管的栅极和所述NMOS管的栅极相耦合作为所述回写电路的控制端，所述PMOS管的一极作为所述回写电路的第二端，所述NMOS管的一极作为所述回写电路的电压端，所述PMOS管的另一极和所述NMOS管的另一极相耦合作为所述回写电路的第三端，所述一极和所述另一极中的一个为源极、另一个为漏极。
  5. 根据权利要求1-4任一项所述的存储器，其特征在于，所述SFGT存储单元还具有分栅极，所述存储器还包括多个第二字线；其中，
    所述存储阵列中属于同一行的所述SFGT存储单元的分栅极共用所述多个第二字线中 的一个第二字线。
  6. 根据权利要求1-5任一项所述的存储器，其特征在于，所述感应放大器为电压型感应放大器。
  7. 根据权利要求1-6任一项所述的存储器，其特征在于，所述存储器包括动态随机存取存储器DRAM。
  8. 根据权利要求2所述的存储器，其特征在于，所述存储器还包括控制模块，所述控制模块用于：
    在行激活阶段，控制目标行的SFGT存储单元对应的第一字线为高电平，控制所述多个回写控制线为高电平，控制所述多个电压线为高电平且持续一段时间后转换为低电平；
    在读写阶段，控制所述第一字线为低电平，控制所述多个回写控制线为低电平。
  9. 根据权利要求8所述的存储器，其特征在于，所述SFGT存储单元还具有分栅极，所述存储器还包括多个第二字线，所述存储阵列中属于同一行的所述SFGT存储单元的分栅极共用所述多个第二字线中的一个第二字线；所述控制模块还用于：
    在所述行激活阶段，控制所述目标行的SFGT存储单元对应的第二字线为高电平；
    在所述读写阶段，控制所述目标行的SFGT存储单元对应的第二字线为低电平。
  10. 根据权利要求9所述的存储器，其特征在于，所述控制模块还用于：
    在预充电阶段，控制所述第一字线为低电平，控制所述多个回写电压线和所述多个电压线为高电平；或者，
    在预充电阶段，控制所述第一字线为低电平，控制所述目标行的SFGT存储单元对应的第二字线为高电平，控制所述多个回写电压线和所述多个电压线为高电平。
  11. 根据权利要求10所述的存储器，其特征在于，所述多个电压线在所述预充电阶段为高电平时对应的电压值低于所述多个电压线在所述行激活阶段为高电平时对应的电压值。
  12. 根据权利要求3所述的存储器，其特征在于，所述存储器还包括控制模块，所述控制模块用于：
    在行激活阶段，控制目标行的SFGT存储单元对应的第一字线为高电平，控制所述多个回写控制线为低电平且持续一段时间后转换为高电平，以及在所述多个回写控制线为高电平时控制所述多个电压线为低电平；
    在读写阶段，控制所述第一字线为低电平，控制所述多个回写控制线为低电平。
  13. 根据权利要求12所述的存储器，其特征在于，所述SFGT存储单元还具有分栅极，所述存储器还包括多个第二字线，所述存储阵列中属于同一行的所述SFGT存储单元的分栅极共用所述多个第二字线中的一个第二字线；所述控制模块还用于：
    在所述行激活阶段，控制所述目标行的SFGT存储单元对应的第二字线为高电平；
    在所述读写阶段，控制所述目标行的SFGT存储单元对应的第二字线为低电平。
  14. 根据权利要求13所述的存储器，其特征在于，所述控制模块还用于：
    在预充电阶段，控制所述第一字线为低电平，控制所述多个回写控制线为低电平；或者，
    在预充电阶段，控制所述第一字线为低电平，控制所述目标行的SFGT存储单元对应的第二字线为高电平，控制所述多个回写控制线为低电平。
  15. 根据权利要求8-14任一项所述的存储器，其特征在于，所述第一字线和所述第二字线为高电平时对应的电压值为正值，所述第一字线和所述第二字线为低电平时对应的电压值为负值；
    所述多个回写控制线和所述多个电压线为高电平时对应的电压值为正值，所述多个回写控制线和所述多个电压线为低电平时对应的电压值为0。
  16. 根据权利要求8-15任一项所述的存储器，其特征在于，在所述行激活阶段，所述第一字线和所述第二字线为高电平时对应的电压值相等。
  17. 根据权利要求8-16任一项所述的存储器，其特征在于，在所述读写阶段，当所述目标行在对应的感应放大器中的数据存在“1”和“0”时，仅从将所述数据中的“1”对应写入所述目标行的SFGT存储单元中。
  18. 一种电子设备，其特征在于，所述电子设备包括电路板、以及与所述电路板连接的存储器，所述存储器包括权利要求1-17任一项所述的存储器。
  19. 一种电子设备，其特征在于，所述电子设备包括控制器和存储器，所述控制器用于控制所述存储器的读写操作，所述存储器包括权利要求1-17任一项所述的存储器。
  20. 一种电子设备，其特征在于，包括处理器和存储器，所述存储器中包括控制器，以及由半浮栅晶体管SFGT存储单元组成的存储阵列，所述处理器用于基于DDR接口协议向所述控制器发出针对所述存储阵列的访问请求，所述控制器用于根据所述访问请求从所述存储阵列中读写数据，所述控制器还用于在读写过程中擦除所述存储阵列中的SFGT存储单元中的数据。
  21. 根据权利要求20所述的电子设备，其特征在于，所述存储器中还包括感应放大器SA，所述控制器根据所述访问请求执行下述动作：
    将目标行的SFGT存储单元中的数据读取到所述SA；
    擦除所述目标行的SFGT存储单元中的数据；
    将所述SA中的目标数据输出，并将所述SA中的数据回写到所述目标行的SFGT存储单元中，所述SA中的数据包括所述目标数据；或者，将目标数据写入所述SA中，并将所述SA中的数据回写到所述目标行的SFGT存储单元中。
  22. 根据权利要求21所述的电子设备，其特征在于，在将所述SA中的数据回写到所述目标行的SFGT存储单元中之后，所述控制器还用于将所述目标行的SFGT存储单元设置为保持状态，并对所述目标行的SFGT存储单元对应的位线进行预充电。
PCT/CN2022/135129 2022-01-20 2022-11-29 一种存储器、时序控制方法及电子设备 WO2023138219A1 (zh)

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