WO2021168622A1 - 存储器、芯片及存储器的修复信息的保存方法 - Google Patents

存储器、芯片及存储器的修复信息的保存方法 Download PDF

Info

Publication number
WO2021168622A1
WO2021168622A1 PCT/CN2020/076467 CN2020076467W WO2021168622A1 WO 2021168622 A1 WO2021168622 A1 WO 2021168622A1 CN 2020076467 W CN2020076467 W CN 2020076467W WO 2021168622 A1 WO2021168622 A1 WO 2021168622A1
Authority
WO
WIPO (PCT)
Prior art keywords
state
circuit
memory
repair
power
Prior art date
Application number
PCT/CN2020/076467
Other languages
English (en)
French (fr)
Inventor
季秉武
王兴意
周云明
赵坦夫
胡楚华
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2020/076467 priority Critical patent/WO2021168622A1/zh
Priority to CN202080096797.3A priority patent/CN115104084A/zh
Priority to EP20921806.4A priority patent/EP4095694A4/en
Publication of WO2021168622A1 publication Critical patent/WO2021168622A1/zh
Priority to US17/894,233 priority patent/US12087380B2/en

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/025—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in signal lines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3275—Power saving in memory, e.g. RAM, cache
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G11C29/4401—Indication or identification of errors, e.g. for repair for self repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52—Protection of memory contents; Detection of errors in memory contents
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/789—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using non-volatile cells or latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/83—Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4072—Circuits for initialization, powering up or down, clearing memory or presetting
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/702—Masking faults in memories by using spares or by reconfiguring by replacing auxiliary circuits, e.g. spare voltage generators, decoders or sense amplifiers, to be used instead of defective ones
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
    • G11C5/144—Detection of predetermined disconnection or reduction of power supply, e.g. power down or power standby

Definitions

  • This application relates to the field of electronic technology, and in particular to a method for storing repair information of a memory, a chip, and the memory.
  • Random access memory such as static random access memory (SRAM) and dynamic random access memory (DRAM), etc.
  • RAM graphics processing unit
  • CPU central processing unit
  • DSP digital signal processing
  • FIG. 1 shows a schematic structural diagram of a random access memory 2.
  • the traditional random access memory 2 may include: a controller 20 and a processing module 40. Due to various reasons such as improper manufacturing process or operation, a certain row and/or a certain column in the random access memory 2 may fail, so that the bit cell of the random access memory 2 has defects or problems.
  • the repair information of the random access memory 2 that is, the address information and/or column address information of the failed storage unit, is usually stored in the eFuse or other non-volatile memory (for ease of description, the figure EFuse is used as an example in 1).
  • the repair information of the RAM 2 in the eFuse needs to be shifted into the controller 20 step by step through clock control.
  • the controller 20 can obtain the repair information of the RAM 2 from the eFuse, so as to prevent the processing module 40 from performing data read and write operations with the processor through the failed storage unit, so that the function of the RAM 2 The performance is normal, so that the processing module 40 can communicate with the processor smoothly (the two-way arrow is used for illustration in FIG. 1).
  • the chip carrying the processor can provide power supply to the RAM 2.
  • the controller 20 can obtain and maintain the repair information of the RAM 2 from the outside (ie, eFuse or other non-volatile memory).
  • the chip In order to achieve low power consumption, the chip often needs to switch between working mode and standby mode. In the working mode, the power supply is normally supplied, and the repair information can be obtained by the RAM 2; but in the standby mode, in order to reduce power consumption, the power supply will be powered off, and the repair information will be lost due to lack of power. After powering on again, the controller 20 needs to reload the repair information of the random access memory 2.
  • the present application provides a method for saving repair information of a memory, a chip, and a memory, which is used to realize that the repair information of the memory can be continuously saved by the memory, which is beneficial to obtain the repair information of the memory in a timely manner to smoothly realize the connection between the memory and the processor. Communication is also conducive to the effective power-down of the chip.
  • the present application provides a memory including: a repair circuit configured to receive a first signal from a processor, and determine according to the state of the first signal to supply power through the first power source or the second power source to save repair information , Where the repair information is the information of the failed storage unit in the memory, the first power supply is zero or high impedance when the system is powered off, and the second power supply is not zero when the system is powered off; the processing circuit is configured according to The repair information realizes the communication between the memory and the processor.
  • the repair circuit can be connected to the first power supply and the second power supply, wherein the first power supply is zero or high impedance when the system is powered down, and the second power supply is not zero when the system is powered down .
  • the repair circuit may receive the first signal from the processor, and based on the state of the first signal, supply power through the first power source or the second power source to save the repair information, avoiding the situation that the first power source cannot provide power.
  • the processing circuit realizes the communication between the memory and the processor according to the repair information of the memory. Among them, the repair information is the address information of the failed storage unit in the memory.
  • the repair circuit since the repair circuit is supplied by the first power source and the second power source, and the first power source will be powered down as the system is powered off, the second power source will not be affected by the power down of the system and can continue to supply power. Therefore, based on the indication of the level state of the first signal, the repair circuit can switch between the first power supply and the second power supply, and continuously provide power for acquiring and maintaining the repair information of the memory, so that the repair information of the memory can always be saved. It avoids the problem that the repair information cannot be saved due to power failure in the traditional technology, so that the processing circuit can timely and accurately obtain the repair information of the memory from the repair circuit, determine the failed storage unit in the memory, and realize the memory and chip.
  • the communication between the processors improves the efficiency and accuracy of data read and write operations between the memory and the processor, and also avoids the cumbersome and inefficient process due to the need to reproduce the loading and repair information in the traditional technology.
  • the repair circuit is time-consuming to reload and repair, so that even if the chip is powered off, it will not take up the time of data read and write operations due to reloading the repair information, which is conducive to the effective power-down of the chip, so that the processor and the processor can be successfully completed. Inter-communication.
  • the repair circuit is configured to store repair information through the first power supply when the state of the first signal is the first state; when the state of the first signal is the second state, use the second power supply Save the repair information; where the second state is different from the first state.
  • the first power supply or the second power supply can provide continuous power for the acquisition and maintenance of the repair information of the memory.
  • the first state is a low-level state and the second state is a high-level state; alternatively, the first state is a high-level state and the second state is a low-level state.
  • the repair circuit includes: a first circuit and a second circuit that are electrically connected, the second circuit is also electrically connected to the processing circuit; the first circuit is configured to receive the first information from the processor, and according to The state of the first signal controls the second circuit to supply power through the first power source or the second power source to maintain repair information. In this way, the first circuit can control the second circuit, and the repair information of the memory is always kept through the first power supply or the second power supply.
  • the first circuit is configured to control the second circuit to save repair information through the first power supply when the state of the first signal is the first state; the first circuit is also configured to When the signal state is the second state, the second circuit is controlled to save the repair information through the second power supply; wherein, the second state is different from the first state.
  • the first circuit includes: M inverters, a first PMOS tube, a first NMOS tube, a second PMOS tube, a third PMOS tube, and a second NMOS tube; where M is a positive integer , M inverters are connected in series, one end of the M inverters connected in series is configured to receive the first signal, and the other end of the M inverters connected in series is connected to the gate of the first PMOS transistor and the first NMOS
  • the gates of the tubes are electrically connected, the power supply terminal of each inverter and the source of the first PMOS tube are configured to receive the second power, the source of the first PMOS tube is electrically connected to the substrate, and the first PMOS tube
  • the drain of the first NMOS tube, the drain of the first NMOS tube, the gate and drain of the second NMOS tube, the gate of the second PMOS tube and the gate of the third PMOS tube are electrically connected, and the source of the first NMOS tube and the lining
  • the bottom electrode is electrically connected
  • the first circuit can provide the second circuit with power to obtain and maintain the repair information of the memory, and the power supply can be maintained at a higher voltage level, so that The repair information will not be lost.
  • the first circuit adopts the above-mentioned structure, which can use the least components to realize the safe switching of the power supply.
  • the body diode in the second NMOS tube is provided in the first circuit, the path from the first power source VDDP to the second power source VDDC will not be turned on, and the phenomenon of voltage backflow is prevented.
  • the drain of the second NMOS tube will not be directly electrically connected to the second power supply VDDC, avoiding the electrostatic discharge (Electro-Static discharge, ESD) caused by the direct connection between the two. )risk.
  • the first circuit is configured to control the second circuit to save repair information through the first power supply when the state of the first signal is the first state; the first circuit is also configured to When the signal state is the second state, the second circuit is controlled to save the repair information through the second power supply; wherein, the second state is different from the first state.
  • M when the first state is a low-level state and the second state is a high-level state, M is an odd number; when the first state is a high-level state, the second state is a low-level state When, M is an even number.
  • the size of the m-th inverter is smaller than the size of the m+1-th inverter, and m is taken all times greater than or equal to 1 and less than M, and m is a positive integer. In this way, the driving performance of the M inverters is improved, and the delay of the M inverters is reduced, so that the delay performance and the driving performance of the M inverters reach a balanced state.
  • the second circuit is configured to save repair information in advance. In this way, the repair circuit does not need to obtain the repair information of the memory from other modules of the memory, which saves the power to obtain the repair information of the memory.
  • the second circuit includes: N D flip-flops or N JK flip-flops, and N is a positive integer.
  • the processing circuit is powered by the first power source and the second power source. In doing so, there is no need to introduce a new power source. Through the power supply of the first power source and the second power source, both the repair circuit and the processing circuit can achieve normal operation.
  • the present application provides a chip, including: a power supply, a processor, and a memory in any one of the first aspect and the first aspect; wherein the power supply supplies the memory through the first power supply and the second power supply.
  • the processor sends a first signal to the memory, and the memory implements communication between the memory and the processor according to the repair information of the memory.
  • beneficial effects of the chips provided in the above-mentioned second aspect and the possible designs of the above-mentioned second aspect can refer to the beneficial effects brought by the above-mentioned first aspect and each possible implementation of the first aspect, which will not be omitted here. Go into details.
  • the present application provides a method for saving repair information of a memory, which is applied to a memory.
  • the memory includes: a repair circuit and a processing circuit; and the processing circuit is configured to implement communication between the memory and the processor according to the repair information.
  • the method includes: the repair circuit receives the first signal from the processor; the repair circuit determines according to the state of the first signal to supply power through the first power source or the second power source to save repair information, wherein the repair information is a failed storage unit in the memory
  • the first power supply is zero or high-impedance state when the system is powered down, and the second power supply is not zero when the system is powered down.
  • the repair circuit can be connected to the first power supply and the second power supply. It is not zero when the power is off.
  • the repair circuit may receive the first signal from the processor, and based on the state of the first signal, supply power through the first power source or the second power source to save the repair information, avoiding the situation that the first power source cannot provide power.
  • the processing circuit realizes the communication between the memory and the processor according to the repair information of the memory. Among them, the repair information is the information of the failed storage unit in the memory.
  • the repair circuit since the repair circuit is supplied by the first power source and the second power source, and the first power source will be powered down as the system is powered off, the second power source will not be affected by the power down of the system and can continue to supply power. Therefore, based on the indication of the level state of the first signal, the repair circuit can switch between the first power supply and the second power supply, and continuously provide power for acquiring and maintaining the repair information of the memory, so that the repair information of the memory can always be saved. It avoids the problem that the repair information cannot be saved due to power failure in the traditional technology, so that the processing circuit can timely and accurately obtain the repair information of the memory from the repair circuit, determine the failed storage unit in the memory, and realize the memory and chip.
  • the communication between the processors improves the efficiency and accuracy of data read and write operations between the memory and the processor, and also avoids the cumbersome and inefficient process due to the need to reproduce the loading and repair information in the traditional technology.
  • the repair circuit is time-consuming to reload and repair, so that even if the chip is powered off, it will not take up the time of data read and write operations due to reloading the repair information, which is conducive to the effective power-down of the chip, so that the processor and the processor can be successfully completed. Inter-communication.
  • the repair circuit determines to supply power through the first power source or the second power source to save the repair information according to the state of the first signal, including: when the state of the first signal is the first state, the repair circuit passes The first power supply saves the repair information; or, when the state of the first signal is the second state, the repair circuit saves the repair information through the second power supply; wherein the second state is different from the first state.
  • the first state is a low-level state and the second state is a high-level state; alternatively, the first state is a high-level state and the second state is a low-level state.
  • the repair information is information pre-stored in the repair circuit. In this way, the repair circuit saves the power to obtain repair information and saves the power consumption.
  • Figure 1 is a schematic structural diagram of a random access memory
  • FIG. 2 is a schematic structural diagram of a memory provided by an embodiment of the application.
  • FIG. 3 is a schematic structural diagram of a memory provided by an embodiment of the application.
  • FIG. 4 is a schematic circuit diagram of the first circuit in the repair circuit provided by an embodiment of the application.
  • FIG. 5 is a schematic circuit diagram of a second circuit in the repair circuit provided by an embodiment of the application.
  • FIG. 6 is a schematic structural diagram of a chip provided by an embodiment of the application.
  • FIG. 7 is a flowchart of a method for storing repair information of a memory provided by an embodiment of the application.
  • At least one refers to one or more, and “multiple” refers to two or more.
  • And/or describes the association relationship of the associated objects, indicating that there can be three relationships, for example, A and/or B, which can mean: A alone exists, A and B exist at the same time, and B exists alone, where A, B can be singular or plural.
  • the character “/” generally indicates that the associated objects before and after are in an “or” relationship.
  • the following at least one item (a) or similar expressions refers to any combination of these items, including any combination of a single item (a) or a plurality of items (a).
  • At least one of a alone, b alone or c alone can mean: a alone, b alone, c alone, a combination of a and b, a combination of a and c, a combination of b and c, or a combination of a, b and c, where a, b, and c can be single or multiple.
  • the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance.
  • the present application provides a storage method for memory, chip, and memory repair information.
  • the power of the repair information of the memory can be obtained and maintained in the first power source or the second power source through the state of the first signal, which can not only avoid the traditional technology
  • the problem that the repair information cannot be saved due to power failure allows the repair circuit in the memory to always save the repair signal of the memory, so that the processing circuit in the memory can obtain the repair information of the memory from the repair circuit in time to realize the relationship between the memory and the processor.
  • FIG. 2 is a schematic structural diagram of a memory provided by an embodiment of the application.
  • the memory 1 of the present application may include: a repair circuit 10 and a processing circuit 30 that are electrically connected.
  • the memory 1 involved in the present application may include, but is not limited to, a random access memory RAM such as SRAM or DRAM.
  • the repair circuit 10 can be connected to the first power supply (VDDP is used for illustration in FIG. 2).
  • the first power supply may be directly provided to the repair circuit 10 by the power supply in the chip (not shown in FIG. 2), or may be provided to the repair circuit 10 by the power supply in the chip through components such as a voltage divider. This application does not limit this.
  • the specific implementation form of the power supply can be found in the following content, which will not be repeated here.
  • the first power supply can be zero or in a high-impedance state when the system is powered off.
  • the power failure of the system involved in this application can be understood as a power failure of the power supply in the chip.
  • the power supply in the chip will be powered down, that is, the system will be powered down.
  • the first power supply will be powered down as the system is powered down.
  • the first power supply will be powered down to a voltage of 0V or close to 0V as the system is powered off, so that the repair circuit 10 cannot obtain the power to save the repair information of the memory 1 through the first power supply.
  • the first power supply will be in a high impedance state as the system is powered off. In this way, the first power supply cannot be connected to the repair circuit 10, resulting in that the repair circuit 10 cannot obtain the power to save the repair information of the memory 1 through the first power supply. .
  • the high-impedance state here can be understood as the impedance between the power supply in the chip and the repair circuit 10 is very large, so that the power supply in the chip cannot supply the first power to the repair circuit 10.
  • the repair information of the memory 1 is the information of the failed storage unit in the memory, such as the address information and/or column address information of the failed storage unit. This application does not limit the specific representation form of the repair information.
  • the repair information of the memory 1 may be pre-stored in the repair circuit 10, or may be obtained by the repair circuit 10 from other modules of the memory 1, which is not limited in this application.
  • the repair circuit 10 may obtain the repair information of the memory 1 from other modules of the memory 1.
  • the first power supply or the second power supply can provide the repair circuit 10 with power to maintain the repair information of the memory 1, which saves the power to obtain the repair information and saves power. Supply and consumption.
  • the repair circuit 10 can be connected to a second power supply (VDDC is used for illustration in FIG. 2).
  • VDDC is used for illustration in FIG. 2.
  • the second power source may be directly provided to the repair circuit 10 by the power module in the chip, or may be provided to the repair circuit 10 by the power module in the chip through components such as a voltage divider, which is not limited in this application.
  • the second power source may not be zero when the system is powered down. That is to say, the second power supply will not be powered down as the system is powered down, so that the repair circuit 10 can obtain the power to save the repair information of the memory 1 through the second power supply, and also enable the repair circuit 10 to keep the repair of the memory 1 information.
  • the second power supply can be maintained at a higher voltage level.
  • the first power source and the second power source may be powered by the same power source, or may be powered by different power sources, which is not limited in this application.
  • the specific implementation form of the power supply can be referred to the content described later, which will not be repeated here.
  • a power failure of the system ie, a power failure of the power supply in the chip
  • the power failure of the system will not affect the second power supply to continue to supply power to the repair circuit 10.
  • the voltage value of the first power source and the voltage value of the second power source may be equal or different, which is not limited in this application.
  • the repair circuit 10 needs to consume power to acquire and maintain the repair information of the memory 1 so as to save the repair information of the memory 1.
  • the second power supply can continue to maintain the power supply state.
  • the processor in the chip can usually detect the system power-down. Therefore, in this application, the processor in the chip (not shown in FIG. 2) can indicate the power supply status of the first power supply through the state of the first signal, such as whether the first power supply can supply power, or whether the first power supply occurs Power failure, or no need to be powered by the first power supply, etc.
  • the first signal may be a digital signal or an analog signal, and the first signal may be directly sent by the processor in the chip to the repair circuit 10, or may be indirectly sent to the repair circuit 10 by the processor in the chip through registers and other components. It is sent by circuit 10, which is not limited in this application.
  • the specific implementation form of the processor can be referred to the content described later, which will not be repeated here.
  • the repair circuit 10 may receive the first signal from the processor (indicated by SD in FIG. 2), so that the repair circuit 10 can avoid the first power supply from being zero or high impedance due to system power failure based on the first information. Therefore, it is ensured that the repair circuit 10 can continue to be supplied with power to obtain and maintain the repair information of the memory 1 through the first power supply or the second power supply.
  • the repair circuit 10 When the state of the first information indicates that power can be supplied through the first power source, the repair circuit 10 may be powered through the first power source or the second power source to save the repair information of the memory 1. Among them, in order to save power consumption, the repair circuit 10 may be powered by the first power source. When the state of the first signal indicates that the first power supply is powered down or does not require the first power supply for power supply (for example, the first power supply is used for other purposes), etc., the repair circuit 10 can pass the first power supply. The second power supply is used to supply power to save the repair information of the memory 1.
  • the repair circuit 10 may determine, based on the first state, that power can be supplied through the first power source at present, for example, the first power source does not appear to be powered down, so that it can pass the first power source.
  • the power supply or the second power supply supplies power to save the repair information.
  • the repair circuit 10 may be powered by the first power source.
  • the repair circuit 10 may determine based on the second state that power can not be supplied by the first power source at present, such as a power failure of the first power source or the current need not be performed by the first power source.
  • the second power supply can be used to supply power to save the repair information.
  • the second state is different from the first state.
  • This application does not limit the specific implementation form of the first state and the second state.
  • the first state is a low-level state and the second state is a high-level state; or, the first state is a high-level state and the second state is a low-level state.
  • the memory 1 further includes a processing circuit 30.
  • the processing circuit 30 constitutes the core circuit of the memory 1, and this application does not limit the specific implementation form of the processing circuit 30.
  • the processing circuit 30 may be composed of four parts: an input/output module, a mode selection module, a read-write control module, and a storage array module.
  • the input/output module is mainly used for data exchange between the memory 1 and the processor in the chip, and data transmission between the processing circuit 30 and the repair circuit 10.
  • the mode selection module is mainly used for operations such as verification, debugging, and control of the processing circuit 30.
  • the read-write control module is mainly used for reading or writing between the processors in the more than one chip of the memory.
  • the memory array module is mainly composed of multiple memory cells controlled by the word line address and the bit line address, and is used for the storage of the data array.
  • the processing circuit 30 can obtain the address information of the failed storage unit in the memory 1 and the address of the storage unit in the memory 1 that can be read and written through modules such as software programs. Information, and the processing circuit 30 can also obtain the repair information saved by the repair circuit 10 from the repair circuit 10.
  • the processing circuit 30 can match bit by bit whether the address information of the failed memory cell in the memory 1 is consistent with the repair information saved by the repair circuit 10. When it is determined that the address information of the failed storage unit in the memory 1 is consistent with the repair information, the processing circuit 30 can replace the repair information saved by the repair circuit 10 through the address information of the storage unit that can be read and written in the memory 1. When it is determined that the address information of the failed storage unit in the memory 1 is inconsistent with the repair information, the processing circuit 30 does not need to replace the repair information saved by the repair circuit 10.
  • the processing circuit 30 performs data read and write operations between the memory 1 and the processor in the chip according to the address information of the storage unit in the memory 1 that can be read and written. Communication between.
  • the traditional RAM 2 cannot continue to store the repair information of the RAM 2 when the power supply provided by the chip is powered down.
  • the repair circuit 10 can continuously provide power for acquiring and maintaining the repair information of the memory 1 through the first power supply or the second power supply through the indication of the state of the first signal, avoiding the situation that the first power supply may not be able to supply power.
  • the repair circuit 10 can always save the repair information of the memory 1, which is beneficial for the processing circuit 30 to obtain the repair information of the memory 1 from the repair circuit 10 in time, so that the processing circuit 30 can accurately determine the failed storage unit in the memory 1.
  • the efficiency and accuracy of data read and write operations between the memory 1 and the processor in the chip are improved.
  • the traditional random access memory 2 needs to reload the repair information before the memory 1 is used, which results in a cumbersome and inefficient process.
  • the repair circuit 10 does not need to reproduce the repair information of the load memory due to the continuous power supply of the first power supply or the second power supply, which reduces the time required for the repair circuit 10 to reload and repair, and avoids the chip even if the system is powered down. It will take up the time of data read and write operations due to reloading of the repair information, which is conducive to the effective power-down of the chip, and the data read and write operations between the memory 1 and the processor can be successfully completed.
  • the memory provided by the present application can be connected to the first power source and the second power source through a repair circuit, wherein the first power source is zero or in a high impedance state when the system is powered off, and the second power source is not zero when the system is powered off.
  • the repair circuit may receive the first signal from the processor, and based on the state of the first signal, supply power through the first power source or the second power source to save the repair information, avoiding the situation that the first power source cannot provide power.
  • the processing circuit realizes the communication between the memory and the processor according to the repair information of the memory. Among them, the repair information is the information of the failed storage unit in the memory.
  • the repair circuit since the repair circuit is supplied by the first power source and the second power source, and the first power source will be powered down as the system is powered off, the second power source will not be affected by the power down of the system and can continue to supply power. Therefore, based on the indication of the level state of the first signal, the repair circuit can switch between the first power supply and the second power supply, and continuously provide power for acquiring and maintaining the repair information of the memory, so that the repair information of the memory can always be saved. It avoids the problem that the repair information cannot be saved due to power failure in the traditional technology, so that the processing circuit can timely and accurately obtain the repair information of the memory from the repair circuit, determine the failed storage unit in the memory, and realize the memory and chip.
  • the communication between the processors improves the efficiency and accuracy of data read and write operations between the memory and the processor, and also avoids the cumbersome and inefficient process due to the need to reproduce the loading and repair information in the traditional technology.
  • the repair circuit is time-consuming to reload and repair, so that even if the chip is powered off, it will not take up the time of data read and write operations due to reloading the repair information, which is conducive to the effective power-down of the chip, so that the processor and the processor can be successfully completed. Inter-communication.
  • the repair circuit 10 may include multiple implementation forms. Based on the function of the repair circuit 10, optionally, based on the embodiment shown in FIG. 2, as shown in FIG. 3, the repair circuit 10 of the present application may include: a first circuit 11 and a second circuit 12 that are electrically connected, In addition, the second circuit 12 is also electrically connected to the processing circuit 30.
  • the first circuit 11 is used to connect to the first power source and the second power source, and to receive the first signal from the processor.
  • the second circuit 12 is used to store or store repair information. This application does not limit the specific implementation form of the first circuit 11 and the second circuit 12.
  • the second circuit 12 may store the repair information in advance, or may store the repair information through the transmission of the first circuit 11, which is not limited in this application.
  • the first circuit 11 may obtain the repair information of the memory 1 from other modules of the memory 1.
  • the second circuit 12 saves the repair information of the memory 1 in advance
  • the first circuit 11 does not need to obtain the repair information of the memory 1 from other modules of the memory 1, and only needs to provide the second circuit 12 with power to save the repair information of the memory 1. However, the power required to obtain the repair information of the memory 1 is saved.
  • the first circuit 11 can control the second circuit 12 to pass the first signal based on the state of the first signal.
  • the first power supply is still powered by the second power supply to save the repair information of the memory 1. Therefore, based on the electrical connection relationship between the second circuit 12 and the processing circuit 30, the processing circuit 30 can obtain the repair information of the memory 1 from the second circuit 12 to implement communication between the memory 1 and the processor.
  • the first circuit 11 may control the second circuit 12 to supply power through the first power source or the second power source to save the repair information.
  • the first circuit 11 may be powered by a first power source.
  • the first circuit 11 can control the second circuit 12 to supply power through the second power supply to save the repair information.
  • the first circuit 11 may include multiple implementation forms. Below, on the basis of the above-mentioned embodiment shown in FIG. 3 and in conjunction with FIG. 4, the specific structure of the first circuit 11 of the present application will be illustrated by an example.
  • the first circuit 11 of the present application may include: M inverters, a first PMOS tube, a first NMOS tube, a second PMOS tube, and a third PMOS tube. And the second NMOS tube.
  • the field effect transistor (Metal Oxide Semiconductor, MOS) tube includes: P-Metal-Oxide-Semiconductor (PMOS) tube and N-Metal-Oxide-Semiconductor (N-Metal-Oxide) tube -Semiconductor, NMOS) tube.
  • the first PMOS tube is represented by MP1
  • the first NMOS tube is represented by MN1
  • the second PMOS tube is represented by MP2
  • the third PMOS tube is represented by MP3
  • the second NMOS tube is represented by MN2.
  • M inverters are connected in series, one end of the M inverters connected in series is configured to receive the first signal, and the other end of the M inverters connected in series is connected to the gate of the first PMOS transistor.
  • the gates of the first NMOS transistors are electrically connected, the power supply terminal of each inverter and the source of the first PMOS transistor are configured to receive the second power supply, the source of the first PMOS transistor is electrically connected to the substrate electrode,
  • the drain of a PMOS tube, the drain of the first NMOS tube, the gate and drain of the second NMOS tube, the gate of the second PMOS tube and the gate of the third PMOS tube are electrically connected, and the source of the first NMOS tube
  • the electrode of the second PMOS transistor is electrically connected to the substrate electrode, the source of the second PMOS transistor is configured to receive the first power, the source of the second PMOS transistor is electrically connected to the substrate electrode, the drain of the second PMOS transistor and the The source is electrically connected, the source of the third PM
  • M is a positive integer, and this application does not limit the specific size of M.
  • M is an odd number, for example, M is 3.
  • M is an even number, for example, M is 4.
  • the sizes of the first PMOS tube, the first NMOS tube, the second PMOS tube, the third PMOS tube, and the second NMOS tube are set to be larger, so that the first PMOS tube, the first NMOS tube, and the second NMOS tube
  • the voltage loss consumed by the second PMOS tube, the third PMOS tube, and the second NMOS tube becomes smaller, thereby ensuring that sufficient power supply can be provided to the second circuit 12.
  • the first circuit 11 usually adopts a second PMOS tube and a third PMOS tube connected in series, the layout is simple and easy to design, and the layout space is also saved.
  • the first state is the low state
  • the second state is the high state
  • M is 3
  • the three inverters are INV1, INV2, and INV3 as an example.
  • INV1, INV2, and INV3 are illustrated.
  • the working process of the first circuit 11 and the second circuit 12 is as follows:
  • the second power supply VDDC supplies power to the three inverters (INV1, INV2, and INV3) and the first PMOS tube MP1, and the voltage of the node sd_n ( That is, the output terminal voltage of the inverter INV3, or the gate voltage of the first PMOS tube MP1 and the first NMOS tube MN1) is equal to the second power supply VDDC, the first PMOS tube MP1 is turned off, and the first NMOS tube MN1 is turned on ,
  • the voltage of the node sd_pp (that is, the drain voltage of the first PMOS tube MP1 and the first NMOS tube MN1, or the gate voltage of the second PMOS tube MP2 and the third PMOS tube MP3) is equal to the ground voltage VSS.
  • the first power supply VDDP supplies power to the second PMOS transistor, and both the second PMOS transistor MP2 and the third PMOS transistor MP3 are turned on. Therefore, the first power supply VDDP inputs the voltage VDD_COM to the second circuit 12 through the second PMOS transistor MP2 and the third PMOS transistor MP3.
  • the voltage VDD_COM is close to the voltage value of the first power source VDDP, that is, the second circuit 12 is The first power supply VDDP supplies power.
  • the second power supply VDDC supplies power to the three inverters (INV1, INV2, and INV3) and the first PMOS tube MP1, and the voltage of the node sd_n ( That is, the output terminal voltage of the inverter INV3, or the gate voltage of the first PMOS tube MP1 and the first NMOS tube MN1) is equal to the ground voltage VSS, the first PMOS tube MP1 is turned on, and the first NMOS tube MN1 is turned off,
  • the voltage of the node sd_pp (that is, the drain voltage of the first PMOS tube MP1 and the first NMOS tube MN1, or the gate voltage of the second PMOS tube MP2 and the third PMOS tube MP3) is equal to the second power supply VDDC.
  • the first power supply VDDP supplies power to the second PMOS tube. Since the voltage value of the first power supply VDDP is smaller than the voltage value of the second power supply VDDC (ie VDDP ⁇ VDDC), the second PMOS tube MP2 and the third PMOS tube MP3 are both disconnected . Based on the connection relationship between the second PMOS tube MP2 and the third PMOS tube MP3, the body diode in the second PMOS tube MP2 and the body diode in the third PMOS tube MP3 are connected in series, so that the voltage VDD_COM in the second circuit 12 reaches the first The path of the power supply VDDP will not be turned on to prevent the voltage from being reversed.
  • the second NMOS transistor MN2 Since the voltage of the node sd_n is equal to the ground voltage VSS, the second NMOS transistor MN2 is turned on. Since the gate G and the drain D of the second NMOS tube MN2 are connected together, and the substrate B (body) of the second NMOS tube MN2 is directly connected to the ground voltage VSS, the offset effect of the second NMOS tube MN2 is It is very weak, so that the threshold voltage V th and MMN2 of the second NMOS tube MN2 remain basically unchanged.
  • the voltage difference between MMN2 ie VDD_COM ⁇ VDDC-V th, MMN2
  • the second NMOS transistor MN2 is turned on, so that the voltage VDD_COM is close to the voltage difference between the second power supply VDDC and the threshold voltage V th of the second NMOS transistor MN2, MMN2 (ie VDDC-V th, MMN2 ), That is, the second circuit 12 is powered by the second power supply VDDC.
  • the second power supply VDDC can continue to supply power, the repair information of the memory 1 can always be stored in the second circuit 12. Therefore, the second power supply VDDC inputs the voltage VDD_COM to the second circuit 12 through the first PMOS transistor MP1 and the second NMOS transistor MN2.
  • the first circuit 11 can provide the second circuit 12 with power to acquire and maintain the repair information of the memory 1, and the power supply can be maintained at a higher voltage level, so that the repair Information will not be lost.
  • the first circuit 11 adopts the above-mentioned structure, and can use a minimum of components to realize safe switching of the power supply.
  • the body diode of the second NMOS tube is provided in the first circuit 11, the path from the first power source VDDP to the second power source VDDC will not be turned on, and the phenomenon of voltage backflow is prevented.
  • the drain of the second NMOS tube MN2 will not be directly electrically connected to the second power supply VDDC, which avoids the electrostatic discharge caused by the direct connection between the two. , ESD) risk.
  • the size of the mth inverter is smaller than the size of the m+1th inverter, m is greater than or equal to 1 and less than M, and m is a positive integer . That is to say, the size of M inverters can be increased step by step, that is, the size of the latter inverter is larger than the size of the previous inverter, which improves the driving performance of M inverters and reduces M inverters.
  • the delay of the phaser makes the delay performance and driving performance of the M inverters reach a balanced state.
  • the second circuit 12 may include multi-level registers in various implementation forms.
  • the second circuit 12 may include: N D flip-flops or N JK flip-flops, where N is a positive integer, where N is defined by the number of wordline addresses and bitline addresses of the memory 1. Determined by the number of bits.
  • N is a positive integer
  • N is defined by the number of wordline addresses and bitline addresses of the memory 1. Determined by the number of bits.
  • the Q terminal of the nth D flip-flop in the second circuit 12 is electrically connected to the D terminal of the n+1th D flip-flop, n is greater than or equal to 1 and less than N, and n is a positive integer .
  • the D terminal of the first D flip-flop in the second circuit 12 is electrically connected to the first circuit 11 for receiving repair information of the memory 1.
  • the RST reset terminal of each D flip-flop is electrically connected to form the RPRST reset terminal of the second circuit 12.
  • the processor in the chip is electrically connected to the RPRST reset terminal of the second circuit 12 (not shown in FIG. 5) for transmitting a reset signal, so that each D flip-flop is reset to the initial state based on the reset signal.
  • the CLK clock terminal of each D flip-flop is electrically connected together to form the RPCLK clock terminal of the second circuit 12.
  • the processor in the chip is electrically connected to the RPCLK clock end of the second circuit 12 (not shown in FIG. 5) for transmitting the signal of the clock cycle.
  • the RPRST reset terminal of the second circuit 12 is used to reset the N D flip-flops to the initial state.
  • each D flip-flop writes one bit of address information in the repair information in its corresponding clock cycle.
  • the second circuit 12 completes the process of saving the repair information.
  • the N D flip-flops are powered by the first power supply VDDP.
  • the state of the first signal is the second state, the N D flip-flops are switched from the first power source VDDP to the second power source VDDC.
  • the processing circuit 30 can implement data reading and writing operations between the memory 1 and the processor, the power supply requirement of the memory 1 mainly comes from the processing circuit 30, and a small part comes from the repair circuit 10.
  • the power supply demand of the processing circuit 30 mainly comes from the storage data array, and a small part comes from the data read and write operations. Therefore, in order to save power consumption, the processing circuit 30 is usually powered by two power sources to maintain the operation of the processing circuit 30.
  • the processing circuit 30 can be powered by the first power supply to realize the control of data read and write operations, and powered by the second power supply to realize the storage of the data array. And considering that the first power supply will be powered down as the system is powered down, and the second power supply will not be affected by the system power down and maintain power supply, the data array in the processing circuit 30 can still be stored, so that the memory 1 does not need to introduce new The power supply is reasonable, and the function of the memory 1 is realized by reasonable use of the power supply, which avoids the waste of resources.
  • FIG. 6 is a schematic structural diagram of a chip provided by an embodiment of the application.
  • the chip 100 of the present application may include: a power supply 3, a processor 5, and a memory 1.
  • this application does not limit the specific implementation form of the chip 100, and the chip 100 can be integrated in various electronic devices such as TVs, mobile phones, notebooks, or wearable devices, or can be set separately. limited.
  • the chip 100 can also communicate with external devices, such as receiving user instructions or transmitting data.
  • the power supply 3 supplies the first power and the second power to the memory 1, so that the repair circuit 10 in the memory 1 can provide continuous power for acquiring and maintaining the repair information of the random access memory 1, so that the memory 1 can always save and repair information.
  • the power supply 3 can also enable the processing circuit 30 in the memory 1 to work normally.
  • the power supply 3 may be a single power supply or multiple power supplies.
  • the power supply 3 may be built into the chip 100 or externally inserted into the chip 100, and the specific implementation form of the power supply 3 is not limited in this application.
  • the processor 5 may send a first signal to the repair circuit 10 in the memory 1, so that the repair circuit 10 in the memory 1 can supply power through the first power source or the second power source according to the state of the first signal to save Repair information of storage 1. And based on the electrical connection between the memory 1 and the processor 5 (indicated by a bidirectional arrow in FIG. 5), the processing circuit 30 in the memory 1 can implement communication between the memory 1 and the processor 5 according to the repair information.
  • the processor 5 may include components such as GPU, CPU, or DSP that can perform data read and write operations in the memory 1.
  • the memory 1 may be used to execute the technical solutions of the embodiments shown in FIG. 2 to FIG. 5, and its implementation principles and technical effects are similar, and will not be repeated here.
  • the power supply 3 can also supply power to the processor 5 (not shown in Figure 6) to maintain the normal operation of the processor 5, and can also supply power to other modules in the chip 100 (not shown in Figure 6).
  • the application is not limited.
  • the chip provided in this application can be applied to implement the technical solutions of the memory in the embodiments of FIG. 2 to FIG.
  • FIG. 7 is a flowchart of a method for storing repair information of a memory provided by an embodiment of the application.
  • the method for saving repair information of the memory of the present application can be applied to the memory as shown in FIG. 2 to FIG. 6 to implement the operation corresponding to the repair circuit in any of the foregoing embodiments.
  • the memory includes: repair circuit and processing circuit. Among them, the processing circuit can implement communication between the memory and the processor according to the repair information.
  • the method for saving repair information of the memory provided by the present application may include:
  • the repair circuit receives a first signal from the processor.
  • the repair circuit determines according to the state of the first signal to supply power through the first power source or the second power source to save repair information, where the repair information is information of a failed storage unit in the memory.
  • the repair circuit has power supply inputs for the first power supply and the second power supply.
  • the first power source is zero or in a high impedance state when the system is powered down, that is, the first power source may be powered down as the system is powered down.
  • the second power source is not zero when the system is powered down, that is, the second power source will not be affected by the power down of the system and can continue to supply power. Therefore, the repair circuit can be powered by the first power source or the second power source based on the indication of the state of the first signal to save the repair information of the memory.
  • the repair circuit can switch the power supply input of the first power supply and the second power supply through the indication of the state of the first signal, so that the repair information of the memory can be continuously saved, which is beneficial to the processing circuit to obtain timely and accurately from the repair circuit
  • the repair information to the memory determines the failed storage unit in the memory, which improves the efficiency and accuracy of data read and write operations between the memory and the processor. At the same time, it also reduces the time for reloading and repairing the repair circuit, so that even if the chip is powered off, it will not occupy the time of data read and write operations due to reloading and repair, which is conducive to the effective power-down of the chip and the smooth completion of the memory. Data read and write operations with the processor.
  • the repair circuit in S102 determines according to the state of the first signal to supply power through the first power source or the second power source to save the repair information, which may include:
  • the repair circuit When the state of the first signal is the first state, the repair circuit saves the repair information through the first power source; or, when the state of the first signal is the second state, the repair circuit saves the repair information through the second power source; wherein, the second The state is different from the first state.
  • the method may further include: when the state of the first signal is the first state, the repair circuit may determine that the first power supply is in a power supply state, that is, the first power supply is not currently powered off.
  • the repair circuit may determine that the first power supply is in a power-down state, that is, the first power supply may be currently powered off, or the repair circuit may determine to stop saving repair information through the first power supply, That is, currently it is not necessary to use the first power supply to supply power to the repair circuit.
  • the first state is a low-level state and the second state is a high-level state; alternatively, the first state is a high-level state and the second state is a low-level state.
  • the repair information is information pre-stored in the repair circuit.
  • the storage method for storing repair information of the memory provided by the present application can be applied to implement the technical solutions of the memory in the embodiments of FIG. 2 to FIG.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Power Sources (AREA)

Abstract

本申请提供一种存储器、芯片及存储器的修复信息的保存方法。该存储器包括：修复电路，被配置为从处理器接收第一信号，以及根据第一信号的状态确定通过第一电源或第二电源来进行供电以保存修复信息，其中，修复信息为存储器中失效的存储单元的信息，第一电源在系统掉电时为零或呈高阻态，第二电源在系统掉电时不为零；处理电路，被配置为根据修复信息实现存储器和处理器之间的通信。从而，使得存储器的修复信息可以持续被保存。

Description

存储器、芯片及存储器的修复信息的保存方法 技术领域
本申请涉及电子技术领域，尤其涉及一种存储器、芯片及存储器的修复信息的保存方法。
背景技术
随机存储器(random access memory，RAM)如静态随机存储器(static random access memory，SRAM)和动态随机存储器(dynamic random access memory，DRAM)等，是与图形处理器(graphics processing unit，GPU)/中央处理器(central processing unit，CPU)/数字信号处理(digital signal processing，DSP)器等处理器直接交换数据的内部存储器，通常作为操作系统或其他正在运行中的程序的临时数据存储介质。
图1示出了一种随机存储器2的结构示意图。如图1所示，传统的随机存储器2可以包括：控制器(controller)20和处理模块40。由于制作工艺或者操作不当等各种原因会导致该随机存储器2中的某一行和/或某一列失效，使得该随机存储器2的存储单元(bit cell)存在缺陷或问题。传统技术中，通过专业程序测试，通常将随机存储器2的修复信息，即失效的存储单元的地址信息和/或列地址信息，存储到eFuse或其他非易失性存储器中(为了便于说明，图1中采用eFuse进行举例示意)。在该随机存储器2被使用之前，需要将eFuse中该随机存储器2的修复信息通过时钟控制逐位移入到控制器20中。在该随机存储器2被使用时，控制器20可以从eFuse中获取该随机存储器2的修复信息，避免处理模块40通过失效的存储单元与处理器进行数据读写操作，使得该随机存储器2的功能表现正常，以便处理模块40能够与处理器顺利实现通信(图1中采用双向箭头进行示意)。
综上，对含有失效存储单元的随机存储器2，提供高效可靠的修复信息至关重要。携带有处理器的芯片可以向随机存储器2提供供电电源，该供电电源持续期间，控制器20能够从外部(即eFuse或其他非易失性存储器)获取和维持随机存储器2的修复信息。为了实现低功耗，该芯片经常需要在工作模式和在待机模式之间进行切换。在工作模式下，该供电电源正常供给，修复信息能够被该随机存储器2获取；但在待机模式下，为了降低功耗，该供电电源会掉电，修复信息会因为无电源而丢失。重新上电后，控制器20需要重新加载(reload)该随机存储器2的修复信息。所以，反复的模式切换会导致反复的信息加载，此过程繁琐且低效。例如，在现有GPU的应用中，特别是帧间掉电的场景，重新加载修复信息的耗时，不仅会占用帧间间隔时间，还无法满足某些帧间协议或者无法实现有效掉电。
因此，如何保存存储器的修复信息是现亟需解决的问题。
发明内容
本申请提供一种存储器、芯片及存储器的修复信息的保存方法，用于实现存储器的修复信息能够被存储器持续保存，有利于通过及时地获取存储器的修复信息，顺利实现存储器与处理器之间的通信，还有利于芯片实现有效掉电。
第一方面，本申请提供一种存储器，包括：修复电路，被配置为从处理器接收第一信号，以及根据第一信号的状态确定通过第一电源或第二电源来进行供电以保存修复信息，其中，修复信息为存储器中失效的存储单元的信息，第一电源在系统掉电时为零或呈高阻态，第二电源在系统掉电时不为零；处理电路，被配置为根据修复信息实现存储器和处理器之间的通信。
通过第一方面提供的存储器，修复电路可以接入第一电源和第二电源，其中，第一电源在系统掉电时为零或呈高阻态，第二电源在系统掉电时不为零。修复电路可以从处理器接收第一信号，并基于该第一信号的状态，通过第一电源或者第二电源来进行供电以保存修复信息，规避了第一电源无法提供电能的情况。处理电路根据存储器的修复信息实现存储器和处理器之间的通信。其中，修复信息为存储器中失效的存储单元的地址信息。本申请中，由于修复电路有第一电源和第二电源的供给，且第一电源会随着系统掉电而发生掉电，第二电源不会收到系统掉电的影响，能够持续供电。因此，修复电路基于第一信号的电平状态的指示，可以在第一电源和第二电源之间切换，持续为获取和维持存储器的修复信息提供电源，使得存储器的修复信息能够一直被保存，避免了传统技术中由于电源掉电而无法保存修复信息的问题，使得处理电路能够及时且准确地从修复电路中获取到存储器的修复信息，确定出存储器中失效的存储单元，实现存储器与芯片中的处理器之间的通信，提高了存储器与处理器进行数据读写操作的效率和准确率，也避免了传统技术中由于需要重现加载修复信息而导致过程繁琐且低效的问题，降低了修复电路重新加载修复的耗时，使得芯片即使存在系统掉电也不会由于重新加载修复信息而占用数据读写操作的时间，有利于芯片实现有效掉电，以便顺利完成处理器与处理器之间的通信。
在一种可能的设计中，修复电路，被配置为在第一信号的状态为第一状态时，通过第一电源保存修复信息；在第一信号的状态为第二状态时，通过第二电源保存修复信息；其中，第二状态与第一状态不同。这样做，便可通过第一电源或者第二电源为存储器的修复信息的获取和维持提供持续的电能。
在一种可能的设计中，第一状态为低电平状态，第二状态为高电平状态；或者，第一状态为高电平状态，第二状态为低电平状态。
在一种可能的设计中，修复电路包括：电连接的第一电路和第二电路，第二电路还与处理电路电连接；第一电路，被配置为从处理器接收第一信息，以及根据第一信号的状态控制第二电路通过第一电源或第二电源来进行供电以保持修复信息。这样做，第一电路便可控制第二电路，通过第一电源或者第二电源一直保存储器的修复信息。
在一种可能的设计中，第一电路，被配置为在第一信号的状态为第一状态时，控制第二电路通过第一电源保存修复信息；第一电路，还被配置为在第一信号的状态为第二状态时，控制第二电路通过第二电源保存修复信息；其中，第二状态与第一状态不同。
在一种可能的设计中，第一电路包括：M个反相器、第一PMOS管、第一NMOS管、第二PMOS管、第三PMOS管和第二NMOS管；其中，M为正整数，M个反相器串联连接，串联连接的M个反相器的一端被配置为接收第一信号，串联连接的M个反相器的另 一端与第一PMOS管的栅极和第一NMOS管的栅极均电连接，每个反相器的供电端以及第一PMOS管的源极被配置为接收第二电源，第一PMOS管的源极和衬底极电连接，第一PMOS管的漏极、第一NMOS管的漏极、第二NMOS管的栅极和漏极、第二PMOS管的栅极以及第三PMOS管的栅极电连接，第一NMOS管的源极和衬底极电连接，第二PMOS管的源极被配置为接收第一电源，第二PMOS管的源极和衬底极电连接，第二PMOS管的漏极以及第三PMOS管的源极电连接，第三PMOS管的源极和衬底极电连接，第三PMOS管的漏极以及第二NMOS管的源极均与第二电路电连接，每个反相器的接地端、第一NMOS管的源极以及第二NMOS管的衬底极均接地，且第一电源的电压值小于第二电源的电压值。
本申请中，无论第一信号的电平状态如何发生改变，第一电路均可以向第二电路提供获取和维持存储器的修复信息的电能，且供电电源能够维持在一个较高的电压水平，使得修复信息不会丢失。
并且，第一电路采用上述结构，可以利用最少的元器件，实现电源的安全切换。一方面，由于第一电路中设置有第二NMOS管中的体二极管，使得第一电源VDDP到第二电源VDDC的通路不会导通，防止电压反灌现象。另一方面，由于第一PMOS管的存在，使得第二NMOS管的漏极不会与第二电源VDDC直接电连接，避免了两者直接相连所带来的静电释放(Electro-Static discharge，ESD)风险。
在一种可能的设计中，第一电路，被配置为在第一信号的状态为第一状态时，控制第二电路通过第一电源保存修复信息；第一电路，还被配置为在第一信号的状态为第二状态时，控制第二电路通过第二电源保存修复信息；其中，第二状态与第一状态不同。
在一种可能的设计中，当第一状态为低电平状态，第二状态为高电平状态时，M为奇数；当第一状态为高电平状态，第二状态为低电平状态时，M为偶数。
在一种可能的设计中，第m个反相器的尺寸小于第m+1个反相器的尺寸，m取遍大于等于1且小于M，m为正整数。这样做，提升了M个反相器的驱动性能，降低了M个反相器的延迟，使得M个反相器的延迟性能和驱动性能达到平衡状态。
在一种可能的设计中，第二电路，被配置为预先保存修复信息。这样做，修复电路便无需从存储器的其他模块中获取存储器的修复信息，节省了获取存储器的修复信息的电能。在一种可能的设计中，第二电路包括：N个D触发器或者N个JK触发器，N为正整数。
在一种可能的设计中，处理电路由第一电源和第二电源供电。这样做，无需引入新的电源，通过第一电源和第二电源的供电，修复电路和处理电路均可以实现正常工作。
第二方面，本申请提供一种芯片，包括：供电源、处理器和第一方面及第一方面任一种可能的设计中的存储器；其中，供电电源通过第一电源和第二电源向存储器供电，处理器向存储器发送第一信号，且存储器根据存储器的修复信息实现存储器与处理器进行的通信。
上述第二方面以及上述第二方面的各可能的设计中所提供的芯片，其有益效果可以参见上述第一方面和第一方面的各可能的实施方式所带来的有益效果，在此不再赘述。
第三方面，本申请提供一种存储器的修复信息的保存方法，应用于存储器，存储器包括：修复电路和处理电路；处理电路，被配置为根据修复信息实现存储器和处理器之间的通信。
该方法包括：修复电路从处理器接收第一信号；修复电路根据第一信号的状态确定通过第一电源或第二电源来进行供电以保存修复信息，其中，修复信息为存储器中失效的存储单元的信息，第一电源在系统掉电时为零或呈高阻态，第二电源在系统掉电时不为零。
通过第三方面提供的存储器的修复信息的保存方法，修复电路可以接入第一电源和第二电源，其中，第一电源在系统掉电时为零或呈高阻态，第二电源在系统掉电时不为零。修复电路可以从处理器接收第一信号，并基于该第一信号的状态，通过第一电源或者第二电源来进行供电以保存修复信息，规避了第一电源无法提供电能的情况。处理电路根据存储器的修复信息实现存储器和处理器之间的通信。其中，修复信息为存储器中失效的存储单元的信息。本申请中，由于修复电路有第一电源和第二电源的供给，且第一电源会随着系统掉电而发生掉电，第二电源不会收到系统掉电的影响，能够持续供电。因此，修复电路基于第一信号的电平状态的指示，可以在第一电源和第二电源之间切换，持续为获取和维持存储器的修复信息提供电源，使得存储器的修复信息能够一直被保存，避免了传统技术中由于电源掉电而无法保存修复信息的问题，使得处理电路能够及时且准确地从修复电路中获取到存储器的修复信息，确定出存储器中失效的存储单元，实现存储器与芯片中的处理器之间的通信，提高了存储器与处理器进行数据读写操作的效率和准确率，也避免了传统技术中由于需要重现加载修复信息而导致过程繁琐且低效的问题，降低了修复电路重新加载修复的耗时，使得芯片即使存在系统掉电也不会由于重新加载修复信息而占用数据读写操作的时间，有利于芯片实现有效掉电，以便顺利完成处理器与处理器之间的通信。
在一种可能的设计中，修复电路根据第一信号的状态确定通过第一电源或第二电源来进行供电以保存修复信息，包括：修复电路在第一信号的状态为第一状态时，通过第一电源保存修复信息；或者，修复电路在第一信号的状态为第二状态时，通过第二电源保存修复信息；其中，第二状态与第一状态不同。
在一种可能的设计中，第一状态为低电平状态，第二状态为高电平状态；或者，第一状态为高电平状态，第二状态为低电平状态。
在一种可能的设计中，修复信息为预先保存在修复电路中的信息。这样做，修复电路便省去了获取修复信息的电能，节省了电能的消耗。
附图说明
图1为一种随机存储器的结构示意图；
图2为本申请一实施例提供的存储器的结构示意图；
图3为本申请一实施例提供的存储器的结构示意图；
图4为本申请一实施例提供的修复电路中第一电路的电路示意图；
图5为本申请一实施例提供的修复电路中第二电路的电路示意图；
图6为本申请一实施例提供的芯片的结构示意图；
图7为本申请一实施例提供的存储器的修复信息的保存方法的流程图。
附图说明标记：
2—随机存储器；20—控制器；40—处理模块；
1—存储器；10—修复电路；11—第一电路；12—第二电路；
30—处理电路；100—芯片；3—供电电源；5—处理器。
具体实施方式
本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，单独a，单独b或单独c中的至少一项(个)，可以表示：单独a，单独b，单独c，组合a和b，组合a和c，组合b和c，或组合a、b和c，其中a，b，c可以是单个，也可以是多个。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性。
本申请提供一种存储器、芯片及存储器的修复信息的保存方法，可通过第一信号的状态，在第一电源或第二电源中获取和维持存储器的修复信息的电能，不仅可以避免传统技术中由于电源掉电而无法保存修复信息的问题，使得存储器中的修复电路能够一直保存存储器的修复信号，使得存储器中的处理电路能够及时从修复电路中获取存储器的修复信息，实现存储器与处理器之间的通信，以便提高存储器与芯片中的处理器之间数据读写操作的效率和准确率，还可以避免传统技术中由于需要重新加载修复信息而导致过程繁琐且低效的问题，能够降低修复电路重新加载修复的耗时，使得芯片即使存在系统掉电也不会由于重新加载修复信息而占用数据读写操作的时间，有利于芯片实现有效的系统掉电，以便顺利完成处理器与处理器之间的通信。
下面，结合图2，对本申请的存储器的具体结构进行详细说明。
图2为本申请一实施例提供的存储器的结构示意图。如图2所示，本申请的存储器1可以包括：电连接的修复电路10和处理电路30。
其中，本申请所涉及的存储器1可以包括但不限于为SRAM或者DRAM等随机存储器RAM。
本申请中，修复电路10可以接入第一电源(图2中采用VDDP进行示意)。其中，第一电源可以由芯片中的供电电源(图2中未示出)直接向修复电路10提供的，也可以由芯片中的供电电源通过分压器等元器件向修复电路10提供的，本申请对此不做限定。另外，该供电电源的具体实现形式可参见后述内容，此处不做赘述。
并且，第一电源可以在系统掉电时为零或者呈高阻态。其中，本申请涉及的系统掉电可以理解为芯片中的供电电源发生掉电。例如，在待机模式下，为了降低功耗，芯片中的供电电源会发生掉电，即系统掉电。
也就是说，第一电源会随着系统掉电而掉电。
即，第一电源会随着系统掉电而掉电至0V电压或者接近于0V电压，导致修复电路10通过第一电源无法获取到保存存储器1的修复信息的电能。
或者，第一电源会随着系统掉电而呈高阻态，这样，第一电源便无法接入到修复电路10，导致修复电路10通过第一电源无法获取到保存存储器1的修复信息的电能。此处的高阻态可以理解为在芯片中的供电电源与修复电路10之间的阻抗非常大，使得芯片中的供电电源无法向修复电路10供给第一电源。
其中，存储器1的修复信息为存储器中失效的存储单元的信息，如失效的存储单元的地址信息和/或列地址信息，本申请对修复信息的具体表示形式不做限定。
另外，存储器1的修复信息可以预先保存在修复电路10中，也可以由修复电路10从存储器1的其他模块中获取，本申请对此不做限定。当存储器1的修复信息未预先存储在修复电路10中时，修复电路10可以从存储器1的其他模块中获取存储器1的修复信息。当存储器1的修复信息预先存储在修复电路10中时，第一电源或者第二电源便可向修复电路10提供维持存储器1的修复信息的电能，省去了获取修复信息的电能，节省了电能的供给和消耗。
本申请中，修复电路10可以接入第二电源(图2中采用VDDC进行示意)。其中，第二电源可以由芯片中的电源模块直接向修复电路10提供的，也可以由芯片中的电源模块通过分压器等元器件向修复电路10提供的，本申请对此不做限定。
并且，第二电源可以在系统掉电时不为零。也就是说，第二电源不会随着系统掉电而掉电，使得修复电路10通过第二电源可以获取到保存存储器1的修复信息的电能，也使得修复电路10能够一直保存存储器1的修复信息。通常，第二电源可以维持在一个较高的电压值水平。
其中，第一电源和第二电源可以同一供电电源供电，也可以由不同的供电电源供电，本申请的对此不做限定。且该供电电源的具体实现形式可参见后述内容，此处不做赘述。
综上，系统掉电(即芯片中的供电电源发生掉电)可以影响或者阻止第一电源继续向修复电路10供电，而系统掉电并不会影响第二电源继续向修复电路10供电。另外，第一电源的电压值与第二电源的电压值可以相等，也可以不等，本申请对此不做限定。
本领域技术人员可以理解，修复电路10需要消耗电能来获取和维持存储器1的修复信息，以保存存储器1的修复信息。基于前述内容，在修复电路10为获取和维持存储器1的修复信息提供电能的整个过程中，由于第一电源可能会由于系统掉电而无法维持供电的现象，而第二电源可以持续保持供电状态，完全不用考虑系统掉电对第二电源的影响，且芯片中的处理器通常可以检测到系统掉电。因此，本申请中，芯片中的处理器(图2中未进行示意)可以通过第一信号的状态来表示第一电源的供电情况，如第一电源是否能够供电，或者，第一电源是否发生掉电，或者，不需要由第一电源供电等。
其中，该第一信号可以为数字信号或者模拟信号，且该第一信号可以为芯片中的处理器直接向修复电路10发送的，也可以为芯片中的处理器通过寄存器等元器件间接向修复电路10发送的，本申请对此不做限定。另外，该处理器的具体实现形式可参见后述内容，此处不做赘述。
本申请中，修复电路10可以从处理器接收第一信号(图2中采用SD进行示意)，使得修复电路10基于该第一信息能够规避第一电源由于系统掉电而为零或者呈高阻态的现象，从而确保修复电路10通过第一电源或者第二电源能够持续被供给到获取和维持存储器1的修复信息的电能。
在第一信息的状态表示能够通过第一电源进行供电的情况时，修复电路10可以通过第一电源或者第二电源来进行供电，以保存存储器1的修复信息。其中，为了节省功耗，修复电路10可以通过第一电源进行供电。在第一信号的状态表示第一电源发生掉电或者不需要第一电源进行供电(如将第一电源挪为他用)等无法通过第一电源进行供电的情况 时，修复电路10可以通过第二电源来进行供电，以保存存储器1的修复信息。
其中，本申请对第一信息的具体状态不做限定。可选地，在第一信号的状态为第一状态时，修复电路10可以基于第一状态确定出当前能够通过第一电源进行供电，如第一电源未出现掉电现象等，从而通过第一电源或者第二电源进行供电，来保存修复信息。其中，为了节省功耗，修复电路10可以通过第一电源进行供电。在第一信号的电平状态为第二状态时，修复电路10可以基于第二状态确定出当前无法通过第一电源进行供电，如第一电源出现掉电现象或者当前不需要通过第一电源进行供电，便可通过第二电源进行供电，来保存修复信息。
其中，第二状态与第一状态不同。本申请对第一状态和第二状态的具体实现形式不做限定。可选地，第一状态为低电平状态，第二状态为高电平状态；或者，第一状态为高电平状态，第二状态为低电平状态。
本申请中，存储器1还包括处理电路30。处理电路30构成存储器1的核心电路，本申请对处理电路30的具体实现形式不做限定。例如，处理电路30可以由输入/输出模块、模式选择模块、读写控制模块、存储阵列模块四个部分组成。其中，输入/输出模块主要用于存储器1与芯片中的处理器之间的数据交换以及处理电路30与修复电路10之间的数据传输。模式选择模块主要用于处理电路30的验证、调试和控制等操作。读写控制模块主要用于存储器1余芯片中的处理器之间的读取或者写入。存储阵列模块主要由字线地址和位线地址所控制的多个存储单元构成，用于数据阵列的存储。
本申请中，为了判断修复电路10中保存的修复信息是否失效，处理电路30可以通过软件程序等模块获得存储器1中失效的存储单元的地址信息以及存储器1中可读写操作的存储单元的地址信息，并且处理电路30还可以从修复电路10中获取修复电路10所保存的修复信息。
进而，处理电路30可以逐位匹配存储器1中失效的存储单元的地址信息与修复电路10所保存的修复信息是否一致。在确定存储器1中失效的存储单元的地址信息与修复信息一致时，处理电路30可以通过存储器1中可读写操作的存储单元的地址信息，对修复电路10所保存的修复信息进行替换。在确定存储器1中失效的存储单元的地址信息与修复信息不一致时，处理电路30无需对修复电路10所保存的修复信息进行替换。
从而，基于处理电路30与芯片中的处理器之间的电连接，处理电路30根据存储器1中可读写操作的存储单元的地址信息，通过数据读写操作，进行存储器1与芯片中处理器之间的通信。
图1中，传统的随机存储器2在芯片所提供的供电电源发生掉电时，无法继续保存该随机存储器2的修复信息。而本申请中，修复电路10通过第一信号的状态的指示，可以通过第一电源或者第二电源为获取和维持存储器1的修复信息持续提供电能，避免了第一电源可能无法供电的情况，使得修复电路10能够一直保存存储器1的修复信息，有利于处理电路30及时地从修复电路10中获取到存储器1的修复信息，使得处理电路30可以准确地确定出存储器1中失效的存储单元，提高了存储器1与芯片中的处理器之间数据读写操作的效率和准确率。
与此同时，传统的随机存储器2在存储器1被使用之前需要重现加载修复信息，导致过程繁琐且低效。本申请中，修复电路10由于第一电源或者第二电源的持续供电而无需 重现加载存储器的修复信息，降低了修复电路10重新加载修复的耗时，规避了芯片即使存在系统掉电也不会由于重新加载修复信息而占用数据读写操作的时间，有利于芯片实现有效掉电，能够顺利完成存储器1与处理器之间的数据读写操作。
本申请提供的存储器，通过修复电路可以接入第一电源和第二电源，其中，第一电源在系统掉电时为零或呈高阻态，第二电源在系统掉电时不为零。修复电路可以从处理器接收第一信号，并基于该第一信号的状态，通过第一电源或者第二电源来进行供电以保存修复信息，规避了第一电源无法提供电能的情况。处理电路根据存储器的修复信息实现存储器和处理器之间的通信。其中，修复信息为存储器中失效的存储单元的信息。本申请中，由于修复电路有第一电源和第二电源的供给，且第一电源会随着系统掉电而发生掉电，第二电源不会收到系统掉电的影响，能够持续供电。因此，修复电路基于第一信号的电平状态的指示，可以在第一电源和第二电源之间切换，持续为获取和维持存储器的修复信息提供电源，使得存储器的修复信息能够一直被保存，避免了传统技术中由于电源掉电而无法保存修复信息的问题，使得处理电路能够及时且准确地从修复电路中获取到存储器的修复信息，确定出存储器中失效的存储单元，实现存储器与芯片中的处理器之间的通信，提高了存储器与处理器进行数据读写操作的效率和准确率，也避免了传统技术中由于需要重现加载修复信息而导致过程繁琐且低效的问题，降低了修复电路重新加载修复的耗时，使得芯片即使存在系统掉电也不会由于重新加载修复信息而占用数据读写操作的时间，有利于芯片实现有效掉电，以便顺利完成处理器与处理器之间的通信。
下面，结合具体的实施例，对本申请的存储器1的具体实现结构进行举例说明。
本申请中，修复电路10可以包括多种实现形式。基于修复电路10的功能，可选地，在图2所示实施例的基础上，如图3所示，本申请的修复电路10可以包括：电连接的第一电路11和第二电路12，且第二电路12还与处理电路30电连接。
其中，第一电路11用于接入第一电源和第二电源，以及从处理器接收第一信号。第二电路12用于存储或者存放修复信息。本申请对第一电路11和第二电路12的具体实现形式不做限定。
需要说明的是，第二电路12可以预先保存修复信息，也可以通过第一电路11的传输保存修复信息，本申请对此不做限定。其中，当第二电路12未预先保存保存存储器1的修复信息时，第一电路11可以从存储器1的其他模块中获取存储器1的修复信息。当第二电路12预先保存存储器1的修复信息时，第一电路11无需从存储器1的其他模块中获取存储器1的修复信息，只需向第二电路12提供保存存储器1的修复信息的电能便可，节省了获取存储器1的修复信息的电能。
综上，基于第一电路11和第二电路12的电连接关系，为了实现存储器1的修复信息的获取和维持，第一电路11基于第一信号的状态，可以控制第二电路12是通过第一电源还是通过第二电源来进行供电，以保存存储器1的修复信息。从而，基于第二电路12与处理电路30的电连接关系，处理电路30可以从第二电路12中获取存储器1的修复信息，实现存储器1与处理器之间的通信。
可选地，在第一信号的状态为第一状态时，第一电路11可以控制第二电路12通过第一电源或者第二电源进行供电，来保存修复信息。其中，为了节省功耗，第一电路11可以通过第一电源进行供电。在第一信号的电平状态为第二状态时，第一电路11可以控制 第二电路12通过第二电源进行供电，来保存修复信息。
本申请中，第一电路11可以包括多种实现形式。下面，在上述图3所示实施例的基础上，结合图4，对本申请的第一电路11的具体结构进行举例示意。
在一种可行的实现方式中，如图4所示，本申请的第一电路11可以包括：M个反相器、第一PMOS管、第一NMOS管、第二PMOS管、第三PMOS管和第二NMOS管。其中，场效应管(Metal Oxide Semiconductor，MOS)管包括：P型金属-氧化物-半导体(P-Metal-Oxide-Semiconductor，PMOS)管和N型金属-氧化物-半导体(N-Metal-Oxide-Semiconductor，NMOS)管。
为了便于说明，图4中，第一PMOS管采用MP1进行示意，第一NMOS管采用MN1进行示意，第二PMOS管采用MP2进行示意，第三PMOS管采用MP3进行示意，第二NMOS管采用MN2进行示意。
本申请中，M个反相器串联连接，串联连接的M个反相器的一端被配置为接收第一信号，串联连接的M个反相器的另一端与第一PMOS管的栅极和第一NMOS管的栅极均电连接，每个反相器的供电端以及第一PMOS管的源极被配置为接收第二电源，第一PMOS管的源极和衬底极电连接，第一PMOS管的漏极、第一NMOS管的漏极、第二NMOS管的栅极和漏极、第二PMOS管的栅极以及第三PMOS管的栅极电连接，第一NMOS管的源极和衬底极电连接，第二PMOS管的源极被配置为接收第一电源，第二PMOS管的源极和衬底极电连接，第二PMOS管的漏极以及第三PMOS管的源极电连接，第三PMOS管的源极和衬底极电连接，第三PMOS管的漏极以及第二NMOS管的源极均与第二电路12电连接，每个反相器的接地端、第一NMOS管的源极以及第二NMOS管的衬底极均接地。
其中，M为正整数，本申请对M的具体大小不做限定。基于上述连接方式，当第一状态为低电平状态，第二状态为高电平状态时，M为奇数，如M为3。当第一状态为高电平状态，第二状态为低电平状态时，M为偶数，如M为4。
本申请中，第一PMOS管、第一NMOS管、第二PMOS管、第三PMOS管和第二NMOS管各自的尺寸会设置的较大些，使得第一PMOS管、第一NMOS管、第二PMOS管、第三PMOS管和第二NMOS管各自消耗的电压损失变小，从而确保能够向第二电路12提供充足的供电。
另外，除了采用第二PMOS管与第三PMOS管串联连接之外，本申请中，第一电路11中还可以采用三个或者三个以上的PMOS管串联连接。一般情况下，考虑到电路版图实现时的复杂性，第一电路11通常采用第二PMOS管与第三PMOS管串联连接，布局简单且容易设计，还节省了布局空间。
为了便于说明，图4中，以第一状态为低电平状态，第二状态为高电平状态，M为3，3个反相器分别为INV1、INV2和INV3为例，对第一电路11的具体结构进行示意。进一步地，第一电路11和第二电路12的工作过程如下：
当第一信号的状态为第一状态(即低电平状态)时，第二电源VDDC向三个反相器(INV1、INV2和INV3)和第一PMOS管MP1供电，结点sd_n的电压(即反相器INV3的输出端电压，或者，第一PMOS管MP1和第一NMOS管MN1管的栅极电压)等于第二电源VDDC，第一PMOS管MP1断开，第一NMOS管MN1导通，结点sd_pp的电压(即第一PMOS管MP1和第一NMOS管MN1的漏极电压，或者，第二PMOS管MP2和 第三PMOS管MP3的栅极电压)等于接地电压VSS。
第一电源VDDP向第二PMOS管供电，第二PMOS管MP2和第三PMOS管MP3皆导通。从而，第一电源VDDP通过第二PMOS管MP2和第三PMOS管MP3向第二电路12输入电压VDD_COM。
其中，由于第二PMOS管MP2和第三PMOS管MP3的尺寸较大，且第二电路12的电流消耗较小，因此，电压VDD_COM接近于第一电源VDDP的电压值，即第二电路12由第一电源VDDP供电。
当第一信号的状态为第二状态(即高电平状态)时，第二电源VDDC向三个反相器(INV1、INV2和INV3)和第一PMOS管MP1供电，结点sd_n的电压(即反相器INV3的输出端电压，或者，第一PMOS管MP1和第一NMOS管MN1管的栅极电压)等于接地电压VSS，第一PMOS管MP1导通，第一NMOS管MN1断开，结点sd_pp的电压(即第一PMOS管MP1和第一NMOS管MN1的漏极电压，或者，第二PMOS管MP2和第三PMOS管MP3的栅极电压)等于第二电源VDDC。
第一电源VDDP向第二PMOS管供电，由于第一电源VDDP的电压值小于第二电源VDDC的电压值(即VDDP＜VDDC)，因此，第二PMOS管MP2和第三PMOS管MP3皆断开。基于第二PMOS管MP2和第三PMOS管MP3的连接关系，第二PMOS管MP2中的体二极管和第三PMOS管MP3中的体二极管串联连接，使得第二电路12中的电压VDD_COM到第一电源VDDP的通路不会导通，防止电压反灌。
由于结点sd_n的电压等于接地电压VSS，因此，第二NMOS管MN2导通。又由于第二NMOS管MN2的栅极G和漏极D连接在一起，且第二NMOS管MN2的衬底极B(body)直接连接接地电压VSS上，这样第二NMOS管MN2的衬偏效应很弱，使得第二NMOS管MN2的阈值电压V th，MMN2基本维持不变。从而，当电压VDD_COM由于第二电路12的内部电能消耗而降低至小于第二电源VDDC与第二NMOS管MN2的阈值电压V th， MMN2两者的电压差值(即VDD_COM<VDDC-V th，MMN2)时，第二NMOS管MN2导通，使得电压VDD_COM接近于第二电源VDDC与第二NMOS管MN2的阈值电压V th，MMN2两者的电压差值(即VDDC-V th，MMN2)，即第二电路12由第二电源VDDC供电，由于第二电源VDDC能够持续供电，存储器1的修复信息可以一直保存第二电路12中。从而，第二电源VDDC通过第一PMOS管MP1和第二NMOS管MN2向第二电路12输入电压VDD_COM。
综上，无论第一信号的状态如何发生改变，第一电路11均可以向第二电路12提供获取和维持存储器1的修复信息的电能，且电源能够维持在一个较高的电压水平，使得修复信息不会丢失。
另外，第一电路11采用上述结构，可以利用最少的元器件，实现电源的安全切换。一方面，由于第一电路11中设置有第二NMOS管中的体二极管，使得第一电源VDDP到第二电源VDDC的通路不会导通，防止电压反灌现象。另一方面，由于第一PMOS管MP1的存在，使得第二NMOS管MN2的漏极不会与第二电源VDDC直接电连接，避免了两者直接相连所带来的静电释放(Electro-Static discharge，ESD)风险。
考虑到反相器的延迟性能和驱动性能，可选地，第m个反相器的尺寸小于第m+1个反相器的尺寸，m取遍大于等于1且小于M，m为正整数。也就是说，M个反相器的尺寸 可以逐级增大，即后一个反向器的尺寸大于前一个反相器的尺寸，提升了M个反相器的驱动性能，降低了M个反相器的延迟，使得M个反相器的延迟性能和驱动性能达到平衡状态。
本申请中，第二电路12可以包括多种实现形式的多级寄存器。可选地，第二电路12可以包括：N个D触发器或者N个JK触发器，N为正整数，其中，N由存储器1的字线(wordline)地址位数和位线(bitline)地址位数决定的。下面，在上述图3或图4所示实施例的基础上，结合图5，对本申请的第二电路12的具体结构进行举例示意。为了便于说明，图5中，第二电路12以N个D触发器为例进行示意。
如图5所示，第二电路12中的第n个D触发器的Q端与第n+1个D触发器的D端电连接，n取遍大于等于1且小于N，n为正整数。且第二电路12中的第1个D触发器的D端与第一电路11电连接，用于接收存储器1的修复信息。
每个D触发器的RST复位端电连接在一起，构成第二电路12的RPRST复位端。且芯片中的处理器与第二电路12的RPRST复位端电连接(图5中未进行示意)，用于传输复位信号，使得各个D触发器基于该复位信号复位至初始状态。每个D触发器的CLK时钟端电连接在一起，构成第二电路12的RPCLK时钟端。且芯片中的处理器与第二电路12的RPCLK时钟端电连接(图5中未进行示意)，用于传输时钟周期的信号。
在N个D触发器被写入存储器1的修复信息之前，通过第二电路12的RPRST复位端，使得N个D触发器复位至初始状态。通过第二电路12的RPCLK时钟端的控制，每个D触发器在各自对应的时钟周期内写入修复信息中的一位地址信息。从而，第二电路12完成保存修复信息的过程。
本申请中，当第一信号的状态为第一状态时，N个D触发器由第一电源VDDP供电。当第一信号的状态为第二状态时，N个D触发器由第一电源VDDP切换至第二电源VDDC供电。
另外，由于处理电路30可以实现存储器1与处理器之间的数据读写操作，因此，存储器1的供电需求主要来源于处理电路30，小部分是来源于修复电路10。而处理电路30的供电需求主要来源于存储数据阵列，小部分来源于制数据读写操作。因此，为了节省功耗，处理电路30通常由两个电源进行供电，以维持处理电路30的工作。
基于上述内容，本申请中，处理电路30可以通过第一电源进行供电，来实现数据读写操作的控制，并通过第二电源进行供电，来实现数据阵列的存储。且考虑到第一电源会随着系统掉电而掉电，第二电源不会受到系统掉电的影响而维持供电，处理电路30中的数据阵列仍能实现存储，使得存储器1无需再引入新的电源，合理利用电源实现存储器1的功能，避免了资源的浪费。
示例性地，本申请还提供一种芯片。图6为本申请一实施例提供的芯片的结构示意图。如图6所示，本申请的芯片100可以包括：供电电源3、处理器5以及存储器1。
其中，本申请对芯片100的具体实现形式不做限定，且该芯片100可以集成在如电视、手机、笔记本或者可穿戴设备等各种电子设备中，也可以单独设置，本申请对此不做限定。另外，该芯片100还可以与外部设备进行通信，如接收用户指令或者传输数据等。
本申请中，供电电源3向存储器1供给第一电源和第二电源，使得存储器1中的修复电路10能够为获取和维持随机存储器1的修复信息提供持续的电能，使得存储器1能够 一直保存修复信息。另外，供电电源3还可以使得存储器1中的处理电路30能够正常工作。
其中，本申请对供电电源3的具体实现形式不做限定。例如，供电电源3可以为单电源或者多电源等。该供电电源3可以为内置在芯片100中，也可以外插于芯片100，本申请对供电电源3的具体实现形式不做限定。
本申请中，处理器5可以向存储器1中的修复电路10发送第一信号，使得存储器1中的修复电路10可以根据第一信号的状态，通过第一电源或者第二电源进行供电，来保存存储器1的修复信息。且基于存储器1和处理器5的电连接(图5中采用双向箭头进行示意)，存储器1中的处理电路30根据修复信息，可以实现存储器1和处理器5之间的通信。
其中，处理器5可以包括为如GPU、CPU或者DSP等能够在存储器1中进行数据读写操作的元器件。存储器1可以用于执行图2-图5所示实施例的技术方案，其实现原理和技术效果类似，此处不再赘述。
另外，供电电源3还可以向处理器5供电(图6中未进行示意)，以维持处理器5的正常工作，还可以向芯片100中的其他模块供电(图6中未进行示意)，本申请对此不做限定。
本申请提供的芯片，可以应用于执行图2-图5实施例中存储器的技术方案，其实现原理和技术效果类似，此处不再赘述。
示例性地，本申请还提供一种存储器的修复信息的保存方法。图7为本申请一实施例提供的存储器的修复信息的保存方法的流程图。本申请的存储器的修复信息的保存方法可以应用于如图2-图6所示的存储器，用于实现上述任一实施例中对应于修复电路的操作。其中。存储器包括：修复电路和和处理电路。其中，处理电路可以根据修复信息实现存储器和处理器之间的通信。
如图7所示，本申请提供的存储器的修复信息的保存方法可以包括：
S101、修复电路从处理器接收第一信号。
S102、修复电路根据第一信号的状态确定通过第一电源或第二电源来进行供电以保存修复信息，其中，修复信息为存储器中失效的存储单元的信息。
本申请中，修复电路有第一电源和第二电源的供电输入。且第一电源在系统掉电时为零或呈高阻态，即第一电源可随着系统掉电而发生掉电。第二电源在系统掉电时不为零，即第二电源不会受到系统掉电的影响而能够持续供电。从而，修复电路可以基于第一信号的状态的指示，通过第一电源或者第二电源进行供电，来保存存储器的修复信息。
这样做，修复电路通过第一信号的状态的指示，可以切换第一电源和第二电源的供电输入，使得存储器的修复信息可以持续被保存，有利于处理电路及时且准确地从修复电路中获取到存储器的修复信息，确定出存储器中失效的存储单元，提高了存储器与处理器进行数据读写操作的效率和准确率。同时，还降低了修复电路重新加载修复的耗时，使得芯片即使存在系统掉电也不会由于重新加载修复而占用数据的读写操作的时间，有利于芯片实现有效掉电，能够顺利完成存储器与处理器之间的数据读写操作。
在一些实施例中，S102中的修复电路根据第一信号的状态确定通过第一电源或第二电源来进行供电以保存修复信息，可以+包括：
修复电路在第一信号的状态为第一状态时，通过第一电源保存修复信息；或者，修复电路在第一信号的状态为第二状态时，通过第二电源保存修复信息；其中，第二状态与第一状态不同。
在一些实施例中，该方法还可以包括：在第一信号的状态为第一状态时，修复电路可以确定第一电源处于供电状态，即第一电源当前未出现掉电现象。在第一信号的状态为第二状态时，修复电路可以确定第一电源处于掉电状态，即第一电源当前可能出现掉电现象，或者，修复电路可以确定停止通过第一电源保存修复信息，即当前不需要采用第一电源向修复电路供电。
在一些实施例中，第一状态为低电平状态，第二状态为高电平状态；或者，第一状态为高电平状态，第二状态为低电平状态。
在一些实施例中，修复信息为预先保存在修复电路中的信息。
本申请提供的存储器的修复信息的保存方法，可以应用于执行图2-图6实施例中存储器的技术方案，其实现原理和技术效果类似，此处不再赘述。

Claims (16)

  1. 一种存储器，其特征在于，包括：
    修复电路，被配置为从处理器接收第一信号，以及根据所述第一信号的状态确定通过第一电源或第二电源来进行供电以保存修复信息，其中，所述修复信息为存储器中失效的存储单元的信息，所述第一电源在系统掉电时为零或呈高阻态，所述第二电源在所述系统掉电时不为零；
    处理电路，被配置为根据所述修复信息实现所述存储器和所述处理器之间的通信。
  2. 根据权利要求1所述的存储器，其特征在于，
    所述修复电路，被配置为在所述第一信号的状态为第一状态时，通过所述第一电源保存所述修复信息；在所述第一信号的状态为第二状态时，通过所述第二电源保存所述修复信息；其中，所述第二状态与所述第一状态不同。
  3. 根据权利要求2所述的存储器，其特征在于，
    所述第一状态为低电平状态，所述第二状态为高电平状态；或者，
    所述第一状态为高电平状态，所述第二状态为低电平状态。
  4. 根据权利要求1-3任一项所述的存储器，其特征在于，所述修复电路包括：电连接的第一电路和第二电路，所述第二电路还与处理电路电连接；
    所述第一电路，被配置为从所述处理器接收第一信息，以及根据所述第一信号的状态控制所述第二电路通过所述第一电源或所述第二电源来进行供电以保持所述修复信息。
  5. 根据权利要求4所述的存储器，其特征在于，所述第一电路包括：M个反相器、第一PMOS管、第一NMOS管、第二PMOS管、第三PMOS管和第二NMOS管；
    其中，M为正整数，所述M个反相器串联连接，串联连接的M个反相器的一端被配置为接收所述第一信号，串联连接的M个反相器的另一端与所述第一PMOS管的栅极和所述第一NMOS管的栅极均电连接，每个反相器的供电端以及所述第一PMOS管的源极被配置为接收所述第二电源，所述第一PMOS管的源极和衬底极电连接，所述第一PMOS管的漏极、所述第一NMOS管的漏极、所述第二NMOS管的栅极和漏极、所述第二PMOS管的栅极以及所述第三PMOS管的栅极电连接，所述第一NMOS管的源极和衬底极电连接，所述第二PMOS管的源极被配置为接收所述第一电源，所述第二PMOS管的源极和衬底极电连接，所述第二PMOS管的漏极以及所述第三PMOS管的源极电连接，所述第三PMOS管的源极和衬底极电连接，所述第三PMOS管的漏极以及所述第二NMOS管的源极均与所述第二电路电连接，每个反相器的接地端、所述第一NMOS管的源极以及所述第二NMOS管的衬底极均接地，且所述第一电源的电压值小于所述第二电源的电压值。
  6. 根据权利要求4或5所述的存储器，其特征在于，
    所述第一电路，被配置为在所述第一信号的状态为第一状态时，控制所述第二电路通过所述第一电源保存所述修复信息；
    所述第一电路，还被配置为在所述第一信号的状态为第二状态时，控制所述第二电路通过所述第二电源保存所述修复信息；
    其中，所述第二状态与所述第一状态不同。
  7. 根据权利要求6所述的存储器，其特征在于，
    当所述第一状态为低电平状态，所述第二状态为高电平状态时，M为奇数；
    当所述第一状态为高电平状态，所述第二状态为低电平状态时，M为偶数。
  8. 根据权利要求7所述的存储器，其特征在于，第m个反相器的尺寸小于第m+1个反相器的尺寸，m取遍大于等于1且小于M，m为正整数。
  9. 根据权利要求4-8任一项所述的存储器，其特征在于，所述第二电路，被配置为预先保存所述修复信息。
  10. 根据权利要求4-9任一项所述的存储器，其特征在于，所述第二电路包括：N个D触发器或者N个JK触发器，N为正整数。
  11. 根据权利要求4-10任一项所述的存储器，其特征在于，
    所述处理电路由所述第一电源和所述第二电源供电。
  12. 一种芯片，其特征在于，包括：供电源、处理器和如权利要求1-11任一项所述的存储器；
    其中，所述供电电源通过第一电源和第二电源向所述存储器供电，所述处理器向所述存储器发送第一信号，且所述存储器根据所述存储器的修复信息实现所述存储器与所述处理器进行的通信。
  13. 一种存储器的修复信息的保存方法，其特征在于，应用于所述存储器，所述存储器包括：修复电路和处理电路；所述处理电路，被配置为根据所述修复信息实现所述存储器和所述处理器之间的通信；
    所述方法包括：
    所述修复电路从处理器接收第一信号；
    所述修复电路根据所述第一信号的状态确定通过第一电源或第二电源来进行供电以保存修复信息，其中，所述修复信息为所述存储器中失效的存储单元的信息，所述第一电源在系统掉电时为零或呈高阻态，所述第二电源在所述系统掉电时不为零。
  14. 根据权利要求13所述的方法，其特征在于，所述修复电路根据所述第一信号的状态确定通过第一电源或第二电源来进行供电以保存修复信息，包括：
    所述修复电路在所述第一信号的状态为第一状态时，通过所述第一电源保存所述修复信息；或者，
    所述修复电路在所述第一信号的状态为第二状态时，通过所述第二电源保存所述修复信息；
    其中，所述第二状态与所述第一状态不同。
  15. 根据权利要求14所述的方法，其特征在于，
    所述第一状态为低电平状态，所述第二状态为高电平状态；或者，
    所述第一状态为高电平状态，所述第二状态为低电平状态。
  16. 根据权利要求13-15任一项所述的方法，其特征在于，
    所述修复信息为预先保存在所述修复电路中的信息。
PCT/CN2020/076467 2020-02-24 2020-02-24 存储器、芯片及存储器的修复信息的保存方法 WO2021168622A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
PCT/CN2020/076467 WO2021168622A1 (zh) 2020-02-24 2020-02-24 存储器、芯片及存储器的修复信息的保存方法
CN202080096797.3A CN115104084A (zh) 2020-02-24 2020-02-24 存储器、芯片及存储器的修复信息的保存方法
EP20921806.4A EP4095694A4 (en) 2020-02-24 2020-02-24 MEMORY, CHIP AND MEMORY REPAIR INFORMATION STORAGE METHOD
US17/894,233 US12087380B2 (en) 2020-02-24 2022-08-24 Memory, chip, and method for storing repair information of memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/076467 WO2021168622A1 (zh) 2020-02-24 2020-02-24 存储器、芯片及存储器的修复信息的保存方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/894,233 Continuation US12087380B2 (en) 2020-02-24 2022-08-24 Memory, chip, and method for storing repair information of memory

Publications (1)

Publication Number Publication Date
WO2021168622A1 true WO2021168622A1 (zh) 2021-09-02

Family

ID=77491718

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/076467 WO2021168622A1 (zh) 2020-02-24 2020-02-24 存储器、芯片及存储器的修复信息的保存方法

Country Status (4)

Country Link
US (1) US12087380B2 (zh)
EP (1) EP4095694A4 (zh)
CN (1) CN115104084A (zh)
WO (1) WO2021168622A1 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114083913A (zh) * 2021-11-02 2022-02-25 珠海艾派克微电子有限公司 一种芯片、耗材盒及数据传输方法
WO2023217186A1 (zh) * 2022-05-13 2023-11-16 华为技术有限公司 一种片上系统及相关系统上电恢复方法
CN117637013A (zh) * 2024-01-25 2024-03-01 合肥兆芯电子有限公司 电源控制装置与电源测试系统

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050132255A1 (en) * 2003-11-26 2005-06-16 Tran Tam M. Low-power SRAM E-fuse repair methodology
CN101995905A (zh) * 2009-08-17 2011-03-30 英业达股份有限公司 计算机
CN106356097A (zh) * 2016-08-25 2017-01-25 浙江宇视科技有限公司 一种防止数据丢失的保护方法和装置
CN109614153A (zh) * 2018-11-06 2019-04-12 西安中兴新软件有限责任公司 多核芯片及系统
CN110109708A (zh) * 2019-04-25 2019-08-09 深圳忆联信息系统有限公司 一种控制器NandBoot机制的方法及其系统

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5831467A (en) * 1991-11-05 1998-11-03 Monolithic System Technology, Inc. Termination circuit with power-down mode for use in circuit module architecture
JP2002184181A (ja) * 2000-03-24 2002-06-28 Mitsubishi Electric Corp 半導体記憶装置
JP4865018B2 (ja) * 2009-09-08 2012-02-01 株式会社東芝 半導体集積回路
US8937845B2 (en) * 2012-10-31 2015-01-20 Freescale Semiconductor, Inc. Memory device redundancy management system

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050132255A1 (en) * 2003-11-26 2005-06-16 Tran Tam M. Low-power SRAM E-fuse repair methodology
CN101995905A (zh) * 2009-08-17 2011-03-30 英业达股份有限公司 计算机
CN106356097A (zh) * 2016-08-25 2017-01-25 浙江宇视科技有限公司 一种防止数据丢失的保护方法和装置
CN109614153A (zh) * 2018-11-06 2019-04-12 西安中兴新软件有限责任公司 多核芯片及系统
CN110109708A (zh) * 2019-04-25 2019-08-09 深圳忆联信息系统有限公司 一种控制器NandBoot机制的方法及其系统

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4095694A4 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114083913A (zh) * 2021-11-02 2022-02-25 珠海艾派克微电子有限公司 一种芯片、耗材盒及数据传输方法
WO2023217186A1 (zh) * 2022-05-13 2023-11-16 华为技术有限公司 一种片上系统及相关系统上电恢复方法
CN117637013A (zh) * 2024-01-25 2024-03-01 合肥兆芯电子有限公司 电源控制装置与电源测试系统
CN117637013B (zh) * 2024-01-25 2024-04-30 合肥兆芯电子有限公司 电源控制装置与电源测试系统

Also Published As

Publication number Publication date
CN115104084A (zh) 2022-09-23
US12087380B2 (en) 2024-09-10
EP4095694A4 (en) 2022-12-14
EP4095694A1 (en) 2022-11-30
US20220406393A1 (en) 2022-12-22

Similar Documents

Publication Publication Date Title
WO2021168622A1 (zh) 存储器、芯片及存储器的修复信息的保存方法
US6597620B1 (en) Storage circuit with data retention during power down
US6256252B1 (en) Memory-embedded semiconductor integrated circuit device having low power consumption
JP3902909B2 (ja) 低消費電力型ダイナミックランダムアクセスメモリ
US7730232B2 (en) Data transfer method and system
US5696729A (en) Power reducing circuit for synchronous semiconductor device
US9230636B2 (en) Apparatus for dual purpose charge pump
US7852693B2 (en) Apparatus for and method of current leakage reduction in static random access memory arrays
US9202555B2 (en) Write word-line assist circuitry for a byte-writeable memory
JP5209083B2 (ja) 半導体装置
CN111902871A (zh) 用于耦合存储器装置中的数据线的设备及方法
TWI404074B (zh) 核心電源電壓之供應方法、記憶體陣列電路及積體電路
JP7002783B1 (ja) 記憶装置及びその操作方法
US9047981B2 (en) Bit-flipping in memories
US20110205787A1 (en) Dual-rail sram with independent read and write ports
JP4463680B2 (ja) 半導体メモリのワード線ラッチ
US7505354B2 (en) Word line voltage control circuit for memory devices
US7227793B2 (en) Voltage translator for multiple voltage operations
CN108616268B (zh) 一种基于磁性隧道结的状态保持电源门控单元
US20230063400A1 (en) Low_powered memory device and method of controlling power of the same
US6735143B2 (en) System for reducing power consumption in memory devices
US20120206970A1 (en) Semiconductor memory device
CN116599013A (zh) 针对sram中虚拟存储单元的esd保护电路和方法
EP1818831B1 (en) Data transfer method and system
JP3981056B2 (ja) 低消費電力型メモリ回路およびその使用方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20921806

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2020921806

Country of ref document: EP

Effective date: 20220823

NENP Non-entry into the national phase

Ref country code: DE