WO2023217186A1 - 一种片上系统及相关系统上电恢复方法 - Google Patents

一种片上系统及相关系统上电恢复方法 Download PDF

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Publication number
WO2023217186A1
WO2023217186A1 PCT/CN2023/093266 CN2023093266W WO2023217186A1 WO 2023217186 A1 WO2023217186 A1 WO 2023217186A1 CN 2023093266 W CN2023093266 W CN 2023093266W WO 2023217186 A1 WO2023217186 A1 WO 2023217186A1
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Prior art keywords
target
processing unit
memory
repair information
target processing
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PCT/CN2023/093266
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English (en)
French (fr)
Inventor
王腾
孙伟
赵坦夫
汪浩
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华为技术有限公司
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Publication of WO2023217186A1 publication Critical patent/WO2023217186A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G06F15/7842—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers)
    • G06F15/7846—On-chip cache and off-chip main memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0727—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a storage system, e.g. in a DASD or network based storage system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0793—Remedial or corrective actions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit

Definitions

  • the present application relates to the field of electronic circuit technology, and in particular to a system on a chip and a related system power-on recovery method.
  • SOC System on Chip
  • SOC refers to the technology of integrating a complete system on a single chip and grouping all or part of the necessary electronic circuits. That is, the central processing unit, modem and demodulation can be integrated on one chip. Processing unit, image signal processing unit, video encoding and decoding unit, digital signal processing unit and other processing units, as well as memory module, power supply and other modules.
  • SOC System on Chip
  • each processing unit on the SOC can be powered off in the idle state, and then powered on when it needs to work, avoiding the need for the processing unit to be idle and not powered off. The problem is that it still consumes a lot of power under the condition.
  • the processing unit when the processing unit is powered on again, it needs to be powered on and restored (for example, the processing unit needs to repair bad pixels in the internal memory after being powered on) before it can start working normally.
  • the processing unit In some application scenarios such as high frame rate games, virtual reality technology (Virtual Reality, VR) or new wearable devices, the longer the power-on and recovery time of the processing unit will limit the usage scenarios of each processing unit when it is idle and powered off. Affect user experience.
  • the technical problem to be solved by the embodiments of the present application is to provide a power-on recovery method for a system-on-chip and related systems to shorten the recovery time after the system is powered on.
  • an implementation example of this application provides a system-on-chip, which is characterized in that the system-on-chip includes N processing units, and a target processing unit among the N processing units includes a plurality of first memories, and the plurality of first memories
  • the first memories are all volatile memories
  • the target processing unit is any one of the N processing units, where N and M are integers greater than 0, where the target processing unit is used to: internally Target repair information is stored in the target storage area, and the target repair information is the information of the failed first memory among the plurality of first memories; when the target processing unit switches from the first mode to the second mode, Read the target repair information from the target storage area, and repair bad pixels on the plurality of first memories; wherein, in the first mode, the target processing unit removes the target storage area Some or all other components are in a power-off state, and the target storage area is in a power-on state; in the second mode, the entire target processing unit is in a power-on state.
  • a target storage area is added or divided inside each processing unit in the on-chip system, which is specifically used to store the target repair information of each processing unit itself, and the target storage area is configured as
  • the target storage area can still be powered on, so that after each processing unit is powered on again, it can directly repair bad pixels in the memory based on the internal target repair information without having to go outside the processing unit.
  • Obtaining the corresponding target repair information greatly shortens the memory fault repair time after the processing unit is powered on.
  • a target storage area inside the unit which is specially used to store the target repair information of the processing unit itself (that is, the information related to the first memory that fails inside the processing unit), and the target storage area is used when the processing unit is powered off. It is still in the power-on state (for example, setting a separate power supply for the target storage area), so that the target repair information stored in the target storage area is not lost when the processing unit is powered off. Furthermore, when the processing unit is powered off and then powered on again, since the target storage area is always powered on (that is, the target repair information stored in the target storage area is not lost), the processing unit can be powered off internally.
  • the processing unit in the embodiment of the present invention when the processing unit in the embodiment of the present invention is powered on again, the processing unit can directly repair the bad pixels of the first memory based on the internally stored target repair information, without needing to obtain the target repair information from outside the processing unit, reducing the need for This reduces the time for the processing unit to repair memory faults, so that the processing unit can resume normal operation more quickly and shorten the system power-on recovery time.
  • the system-on-chip further includes a second memory, the second memory is a non-volatile memory; the second memory is used to: store each processing in the N processing units The target repair information for the unit.
  • a hardware test can be performed on each processing unit to obtain the target repair information of each processing unit, and then the target repair information of each processing unit can be stored in the first Among the two memories, since the second memory is a non-volatile memory (that is, data will not be lost after power off), therefore when the second memory is in a power off state, the target repair information of each processing unit will not be lost. Further, when the processing unit is powered on, if there is no target repair information in the target storage area inside the processing unit, its own target repair information can be obtained from the second memory outside the processing unit, and then the processing unit can repair based on the target.
  • Target repair Information is used to repair memory bad pixels, and the target repair information can also be stored in the target storage area, so that when the processing unit is powered on again, the processing unit can directly repair bad pixels in the memory based on the internally stored target repair information without the need for The target repair information is then obtained from outside the processing unit, which reduces the time it takes for the processing unit to repair memory faults, so that the processing unit can resume normal operation more quickly and shorten the system power-on recovery time.
  • the system-on-chip further includes a third memory, and the third memory is a volatile memory; when the system-on-chip switches from a power-off state to a power-on state, the third memory
  • the memory is also configured to: read the target repair information of the target processing unit from the second memory and store it.
  • the third memory may be a static random access memory (SRAM), that is, a volatile memory.
  • SRAM static random access memory
  • the third memory may be used to switch from the second memory to the power-on state.
  • the target processing unit is further configured to: if the target repair information does not exist in the target storage area, obtain the target of the target processing unit from the third memory. Repair information and store it in the internal target storage area.
  • the target processing unit needs to obtain its own target repair information from the outside, that is, it can obtain its own target repair information from a third memory outside the target processing unit. Obtain its own target repair information, and then the target processing unit can repair bad memory pixels based on the target repair information.
  • the target repair information can also be stored in the target storage area, so that when the target processing unit is powered on again, the target processing unit The unit can directly repair bad pixels of the memory based on the internally stored target repair information, without needing to obtain the target repair information from outside the target processing unit. This reduces the time it takes for the target processing unit to repair bad pixels in the memory, so that the target processing unit can be more efficient. Quickly resume normal operation, shortening system power-on recovery time.
  • the target processing unit further includes a first register; the target processing unit is specifically configured to use the first register as the target storage area to store the target repair information.
  • a first register is added inside the target processing unit as a target storage area, specifically used to store the target repair information of the target processing unit, and the first register remains when the target processing unit is in an idle power-off state.
  • the target repair information stored in the first register is not lost when the target processing unit is idle and powered off. Therefore, when the target processing unit is powered on again, the target processing unit can directly repair the bad pixels of the first memory based on the target repair information stored in the first register, without needing to obtain the target repair information from outside the target processing unit, which reduces This shortens the time for the target processing unit to repair bad memory pixels, so that the target processing unit can resume normal operation more quickly and shorten the system power-on recovery time.
  • the first register is powered through a dedicated power domain so that when some or all components in the target processing unit except the first register are in a power-off state, the first register is in the power-on state, or the first register is powered by the normally-on power domain of the target processing unit such that when some components in the target processing unit except the first register are in the power-off state, the first register One register is in power-on state.
  • some or all components in the target processing unit except the first register can be powered on and off by the first power domain, and the first register in the target processing unit can be powered on and off by other power domains.
  • the target processing unit can be powered off by disconnecting the first power domain to save power, but the first register remains in the powered on state so that the stored target repair information is not lost.
  • the target processing unit can directly repair the bad pixels of the first memory based on the target repair information stored in the first register, without needing to obtain the target repair information from outside the target processing unit. This reduces the time it takes for the target processing unit to repair bad memory pixels, so that the target processing unit can resume normal operation more quickly and shorten the system power-on recovery time.
  • the target processing unit further includes a decoding module, and the target processing unit is further configured to: obtain the target repair information from the first register through the decoding module, and Decoding configuration is performed on the plurality of first memories based on the target repair information.
  • the target processing unit when the target processing unit is powered on again, the target processing unit can directly configure multiple first memories in the target processing unit through the decoding module based on the target repair information stored in the first register to avoid the target The processing unit uses the failed first memory. Since the target processing unit no longer needs to obtain target repair information from outside the target processing unit after it is powered on again, the time it takes for the target processing unit to repair memory bad pixels is reduced, so that the target processing unit can resume normal operation more quickly, shortening the system Power recovery time.
  • the target processing unit is specifically configured to: use the plurality of first memories as the target storage areas to store the target repair information, and the plurality of first memories pass the target
  • the normally-on power domain supply of the processing unit causes the plurality of first memories to be in a powered-on state when some components in the target processing unit except for the plurality of first memories are in a powered-off state.
  • a target storage area is divided among multiple first memories inside the target processing unit, which is specifically used to store the target repair information of the target processing unit, and this storage area is in an idle power-off state when the target processing unit is idle. is still powered on when the target processing unit is idle, so that the target repair information stored in the storage area is powered off when the target processing unit is idle. Time is not lost. Therefore, when the target processing unit is powered on again, the target processing unit can directly repair the bad pixels of the first memory based on the target repair information stored in the plurality of first memories, without needing to obtain the target repair information from outside the target processing unit. , reducing the time for the target processing unit to repair bad memory pixels, so that the target processing unit can resume normal operation more quickly and shorten the system power-on recovery time.
  • the target processing unit includes a second register, and the target processing unit is further configured to: after the target processing unit switches from the first mode to the second mode, The target repair information is obtained from the plurality of first memories through the second register and stored.
  • a second register in order to facilitate subsequent decoding of the target repair information, can be added to the target processing unit, and the second register is also in a power-off state when the target processing unit is powered off.
  • the second register can obtain the target repair information from the first memory and store it.
  • the target processing unit further includes a decoding module, and the target processing unit is further configured to: obtain the target repair information from the second register through the decoding module, and Decoding configuration is performed on the plurality of first memories based on the target repair information.
  • the target processing unit when the target processing unit is powered on again, can configure multiple first memories in the target processing unit through the decoding module based on the target repair information in the second register to avoid target processing.
  • the unit uses the first memory that failed. Since the target processing unit no longer needs to obtain target repair information from outside the target processing unit after it is powered on again, the time it takes for the target processing unit to repair memory bad pixels is reduced, so that the target processing unit can resume normal operation more quickly, shortening the system Power recovery time.
  • the target processing unit further includes a backup memory; the target processing unit is specifically configured to: based on the target repair information, determine the failed first memory through the decoding module ;Isolate dead pixels on the failed first memory and enable the backup memory.
  • the target processing unit when the target processing unit is powered on again, the target processing unit can directly determine the failed first memory among the plurality of first memories through the decoding module based on the target repair information stored in the target storage area, and The failed first memory is isolated from dead pixels, and then the backup memory is enabled to prevent the target processing unit from using the failed first memory, causing system abnormalities.
  • the target processing unit since the target processing unit no longer needs to obtain target repair information from outside the target processing unit after it is powered on again, the time it takes for the target processing unit to repair bad memory pixels is reduced, so that the target processing unit can resume normal operation more quickly, shortening System power-on recovery time.
  • the present application provides a system power-on recovery method, which is characterized in that it is applied to a system-on-chip.
  • the system-on-chip includes N processing units, and the target processing unit among the N processing units includes a plurality of third processing units.
  • the method includes: The target processing unit stores target repair information in an internal target storage area, where the target repair information is the information of the failed first memory among the plurality of first memories; when the target processing unit starts from the first memory, After the mode is switched to the second mode, the target processing unit reads the target repair information from the target storage area, and repairs bad pixels on the plurality of first memories; wherein, in the first mode In the second mode, some or all components of the target processing unit except the target storage area are in a power-off state, and the target storage area is in a power-on state; in the second mode, the entire target processing unit In power-on state.
  • the system-on-chip further includes a second memory, and the second memory is a non-volatile memory; the method further includes: storing the N processing units through the second memory The target repair information of each processing unit in .
  • the system-on-chip further includes a third memory, and the third memory is a volatile memory; when the system-on-chip switches from a power-off state to a power-on state, the method also It includes: reading the target repair information of the target processing unit from the second memory through the third memory and storing it.
  • the method further includes: if the target repair information does not exist in the target storage area, obtaining the data of the target processing unit from the third memory through the target processing unit.
  • the target repair information is stored in the internal target storage area.
  • the target processing unit further includes a first register; and storing the target repair information in an internal target storage area through the target processing unit includes: using the first register as The target storage area stores the target repair information.
  • the first register is powered through a dedicated power domain so that when some or all components in the target processing unit except the first register are in a power-off state, the first register is in the power-on state, or the first register is powered by the normally-on power domain of the target processing unit such that when some components in the target processing unit except the first register are in the power-off state, the first register One register is in power-on state.
  • the target processing unit further includes a decoding module
  • the method further includes: obtaining the target from the first register through the decoding module in the target processing unit. Repair information, and decode and configure the plurality of first memories based on the target repair information.
  • storing the target repair information in an internal target storage area through the target processing unit includes: using the plurality of first memories as the target storage areas to store the target repair information.
  • Information the plurality of first memories are powered by the normally-on power domain of the target processing unit, so that when some components in the target processing unit except the plurality of first memories are in a power-off state, the plurality of first memories are powered off.
  • the first memory is in the power-on state.
  • the target processing unit includes a second register
  • the method further includes: after the target processing unit switches from the first mode to the second mode, through the The second register obtains the target repair information from the plurality of first memories and stores it.
  • the target processing unit further includes a decoding module
  • the method further includes: obtaining the target from the second register through the decoding module in the target processing unit. Repair information, and decode and configure the plurality of first memories based on the target repair information.
  • the target processing unit further includes a spare memory; repairing bad pixels on the plurality of first memories includes: based on the target repair information, determining through the decoding module The first memory that has failed; performs dead pixel isolation on the first memory that has failed, and enables the backup memory.
  • the present application provides a computer storage medium, which is characterized in that the computer storage medium stores a computer program, and when the computer program is executed by a processor, the method described in any one of the above second aspects is implemented.
  • embodiments of the present application provide an electronic device, which includes a processor.
  • the processor is configured to support the electronic device in implementing corresponding functions in a system power-on recovery method provided in the second aspect.
  • the electronic device may also include a memory coupled to the processor that stores necessary program instructions and data for the electronic device.
  • the electronic device may also include a communication interface for the electronic device to communicate with other devices or communication networks.
  • the present application provides a chip system, which includes a processor and is used to support an electronic device to implement the functions involved in the above-mentioned second aspect, for example, generating or processing the functions involved in the above-mentioned system power-on recovery method. Information.
  • the chip system further includes a memory, and the memory is used to store necessary program instructions and data of the electronic device.
  • the chip system may be composed of chips, or may include chips and other discrete devices.
  • the present application provides a computer program, characterized in that the computer program includes instructions.
  • the computer program When the computer program is executed by the computer, the computer is caused to execute the method described in any one of the above third aspects.
  • Figure 1 is a schematic structural diagram of a system-on-chip provided by an embodiment of the present invention.
  • Figure 2 is a schematic diagram of an on-chip system provided by an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of an on-chip system with a second memory provided by an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of an on-chip system with a third memory provided by an embodiment of the present invention.
  • Figure 5 is a schematic diagram of the internal structure of a processing unit provided by an embodiment of the present invention.
  • Figure 6 is a schematic diagram of the internal structure of a target processing unit provided by an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of the internal structure of another target processing unit provided by an embodiment of the present invention.
  • Figure 8 is a schematic diagram of power-on recovery of a target processing unit provided by an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of power-on recovery of another target processing unit provided by an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of the internal structure of another target processing unit provided by an embodiment of the present invention.
  • Figure 11 is a schematic diagram of power-on recovery of another target processing unit provided by an embodiment of the present invention.
  • Figure 12 is a schematic diagram of a system power-on recovery process provided by an embodiment of the present invention.
  • Figure 13 is a flow chart of a system power-on recovery method provided by an embodiment of the present invention.
  • an embodiment means that a particular feature, structure or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application.
  • the appearances of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those skilled in the art understand, both explicitly and implicitly, that the embodiments described herein may be combined with other embodiments.
  • FIG. 1 is a schematic structural diagram of a system on chip provided by an embodiment of the present invention.
  • a system on chip (SOC) refers to a complete system integrated on a single chip, which provides all or part of the necessary electronics.
  • the system-on-chip 10 generally includes a processor 100, an on-chip memory module 101, a built-in self-healing module 102, peripheral component circuits, etc., and the system-on-a-chip 10 can be built into various electronic devices, such as servers, personal computers, tablets, mobile phones, etc. Various devices such as personal digital assistants and smart wearable devices. specifically,
  • the processor 100 can run an operating system, a file system or an application program, etc., to control multiple hardware or software components connected to the processor 100, and can process various data and perform operations.
  • the processor 100 may include one or more processing units (also called processing cores).
  • the processor 100 may include a central processing unit (Central Processing Unit, CPU), a modem processing unit, and a graphics processing unit. , GPU), image signal processing unit (image signal processor, ISP), video codec unit, digital signal processing unit (digital signal processor, DSP), baseband processing unit and neural network processing unit (neural-network processing unit, NPU), etc.
  • CPU Central Processing Unit
  • ISP image signal processor
  • video codec unit digital signal processing unit
  • DSP digital signal processor
  • NPU neural-network processing unit
  • different processing units can be independent devices or integrated in one or more devices.
  • Each processing unit (such as a CPU) in the processor 100 can load the instructions or data stored in the on-chip storage module 101 into the memory inside the processing unit, and transfer the instructions or data that need to be calculated to the computing unit for calculation. After the operation is completed, the computing unit temporarily stores the results in the internal memory, and stores instructions or data that require long-term storage into the on-chip storage module 101 .
  • the on-chip storage module 101 stores the repair information of the memory of each processing unit in the plurality of processing units
  • each processing unit (such as a CPU) in the processor 100 can store the repair information in the on-chip storage module 101. The information is loaded into the processing unit and the memory is repaired.
  • the repair information of one or more memories stored in the on-chip storage module 101 is unchangeable and unerasable.
  • each processing unit such as a CPU
  • the memory inside each processing unit can be used to temporarily store operation data in the processing unit (such as a CPU), and to interact with the on-chip storage module 101 or other external memories, and can be used as temporary data for the operating system or other running programs. storage media.
  • the operating system running on the CPU transfers the data that needs to be calculated from the internal memory to the computing unit for calculation. When the calculation is completed, the calculation unit transmits the results and temporarily stores them in the internal memory.
  • the memory inside the processing unit may include static random access memory (Static Random Access Memory, SRAM), where the static random access memory may include single-port static random access memory and dual-port static random access memory.
  • the on-chip storage module 101 is a power-off non-volatile memory, and its stored content will not be lost after power is off.
  • the on-chip storage module 101 can be used for long-term storage of instructions and data involved in the operation of the processor 100, such as repair information, startup programs, operating systems, application programs and data of the internal memory of each processing unit (such as CPU) involved in this application. . Because the processing unit in the processor 100 cannot directly read the instructions and data in the on-chip storage module 101, nor can it directly write instructions or data to the on-chip storage module 101.
  • a processing unit such as a CPU
  • executes a read (or load) command it actually temporarily loads the content to be read (including instructions and/or data) stored in the on-chip storage module 101 into the internal memory. Then the CPU reads it from the internal memory; when executing a write (i.e., store) command, the CPU actually first temporarily writes the data to be stored (including instructions and/or data) into the internal memory. Then it is stored from the internal memory to the on-chip storage module 101 .
  • the on-chip storage module 101 may include Flash memory (for example, NAND flash memory, NOR flash memory, etc.), universal flash memory (universal flash storage, UFS), embedded multimedia card eMMC, universal flash memory storage multi-chip package uMCP memory, embedded multimedia card and more. Chip package one or more of eMCP memory, solid state drive (SSD), etc.
  • the on-chip memory module 101 may also include a one-time programmable memory (eFuse), which may be specifically used to store repair information of the memory of each processing unit in the processor 100, so that the stored repair information of one or more memories cannot be used. Changes are also not erasable.
  • eFuse one-time programmable memory
  • the built-in self-repair module 102 is located outside the processor 100 and may include a static random access memory (SRAM), which may be used to read the repair information of the memory inside each processing unit (such as a CPU) from the on-chip storage module 101 and store it. , so that each processing unit can directly obtain the repair information of its own internal memory from the built-in self-repair module 102 when it is powered on.
  • SRAM static random access memory
  • the memory inside each processing unit will have unavoidable failures during the production process. Therefore, backup memory can be designed during production. When the memory fails, the backup memory can be used to maintain normal operation. Before using the system-on-chip 10 for the first time, the hardware needs to be tested first.
  • the failed memory can be marked to obtain repair information, and the repair information can be stored in the on-chip storage. In module 101 (this information will not be lost after the SOC is powered off). After each processing unit is powered on, it needs to repair the bad pixels of the memory so that the processing unit (such as the CPU) can resume normal operation. That is, each processing unit needs to first obtain the repair information of its own internal memory, so as to store the memory based on the repair information. Failed storage is isolated and can be associated to a backup memory to use.
  • the processing unit (such as CPU) cannot directly read the data in the on-chip memory module 101 after power-on, and before the processing unit obtains the repair information of the internal memory, in order to avoid loading the data into the failed memory, the processing The unit will not directly use the internal memory, so the repair information of the internal memory of all processing units can be read from the on-chip storage module 101 through the built-in self-repair module 102 and stored, so that each processing unit can directly access the memory after power-on.
  • the built-in self-repair module 102 obtains the repair information of the respective memory, and then repairs the bad pixels of the memory based on the repair information.
  • a storage module can be added or divided in the processing unit.
  • the storage module is used to store the repair information of the internal memory, and the repair information will not be lost after the processing unit is powered off (that is, the processing unit is powered off). After power-on, the repair information is still stored inside the processing unit), so when the processing unit is powered on again, the processing unit can directly repair the bad pixels of the memory based on the stored repair information, without needing to obtain the repair information from outside the processing unit. The time required for the processing unit to repair memory faults is reduced, so that the processing unit can resume normal operation more quickly and the system power-on recovery time is shortened.
  • system-on-chip 10 in FIG. 1 is only some exemplary implementations provided by the embodiment of the present invention.
  • the structure of the system-on-chip 10 in the embodiment of the present invention includes but is not limited to the above implementations.
  • Figure 2 is a schematic diagram of an on-chip system provided by an embodiment of the present invention.
  • the system on a chip in the embodiment of the present application will be described in detail below with reference to Figure 2.
  • the system-on-chip 20 includes: N processing units 201.
  • the target processing unit among the N processing units includes a plurality of first memories, and the plurality of first memories are all volatile memories.
  • the target processing unit is any one of the N processing units, and N is an integer greater than 0.
  • the system-on-chip 20 in FIG. 2 may include part or all of the functions of the system-on-chip 10 in FIG. 1, and the N processing units 201 may include all or part of the functions of the processing units of the processor 100 in FIG. 1. . in,
  • the target processing unit is configured to store target repair information in an internal target storage area, where the target repair information is information about a failed first memory among the plurality of first memories.
  • the system-on-chip 20 may include one or more processing units, and the processing units may be a central processing unit (CPU), a modem processing unit, a graphics processing unit (GPU), an image signal processing unit (ISP), a video encoder Decoding unit, digital signal processing unit (DSP), baseband processing unit and neural network processing unit (NPU), etc.
  • Each processing unit may include multiple first memories, and the number of first memories inside each processing unit may be the same or different, which is not limited here.
  • the first memory is usually a power-off volatile memory, and the contents stored therein will be lost when the power is off.
  • the function of the first memory is to temporarily store the operation data (such as the operation results of the computing unit in the CPU) in the processing unit (such as the CPU), and to interact with the on-chip storage module or other external memory. It can be used as an operating system or other running A storage medium for temporary data of programs in a program. Since the first memory inside each processing unit will have unavoidable failures during the production process, the hardware needs to be tested before the system-on-chip 20 is powered on for the first time. If a certain first memory is found during the hardware test, If a memory fails, the first memory that failed can be marked to obtain the target repair information.
  • the operation data such as the operation results of the computing unit in the CPU
  • the processing unit such as the CPU
  • a target storage area can be added or divided inside the target processing unit (such as CPU), which is specially used to store the target repair information of the target processing unit, and the target repair information is stored after the target processing unit is powered off. It will not be lost, that is, after the target processing unit is powered off, the target repair information is still stored inside the target processing unit.
  • the target processing unit such as CPU
  • the target processing unit is also configured to: when the target processing unit switches from the first mode to the second mode, read the target repair information from the target storage area and perform operations on the plurality of first memories. Dead pixel repair; wherein, in the first mode, some or all components in the target processing unit except the target storage area are in a power-off state, and the target storage area is in a power-on state; in the In the second mode, the entire target processing unit is in the upper power status.
  • the first mode of the target processing unit can be understood as that the target processing unit is in an idle power-off state, but the target storage area inside the target processing unit is not powered off, and components such as the computing unit in the target processing unit are all in a power-off state.
  • the target storage area is still powered on, or the computing unit and other components in the target processing unit are powered off, but the target storage area and some devices (such as clock units, etc.) are still powered on, so that the target storage
  • the target repair information stored in the area will not be lost when the target processing unit is idle and powered off;
  • the second mode of the target processing unit can be understood as the target processing unit is in a working power-on state, that is, the computing unit and other components in the target processing unit are all powered on. state.
  • Switching the target processing unit from the first mode to the second mode can be understood as switching the target processing unit from an idle power-off state to a working power-on state.
  • a target storage area is added or divided inside the target processing unit, which is specially used to store the target repair information of the target processing unit, and the target storage area remains when the target processing unit is in an idle power-off state. In the power-on state, the target repair information stored in the target storage area is not lost when the target processing unit is idle and powered off.
  • the target processing unit can directly repair the bad pixels of the first memory based on the internally stored target repair information, without needing to obtain the target repair information from outside the target processing unit, which reduces the number of targets.
  • the time it takes for the processing unit to repair bad memory pixels allows the target processing unit to resume normal operation more quickly, shortening the system power-on recovery time.
  • the system-on-chip 20 further includes a second memory, the second memory is a non-volatile memory; the second memory is used to: store each of the N processing units The target repair information of the processing unit. Specifically, before the system-on-chip 20 is powered on for the first time, a hardware test can be performed on each processing unit to obtain the target repair information of each processing unit, and then the target repair information of each processing unit can be stored in the second memory. , since the second memory is a non-volatile memory (that is, data will not be lost after power-off), therefore when the second memory is in a power-off state, the target repair information of each processing unit will not be lost.
  • the target repair information of one or more memories stored in the second memory is unchangeable and unerasable.
  • the processing unit when the processing unit is powered on, if the target repair information is not stored in the target storage area inside the processing unit, its own target repair information can be obtained from the second memory outside the processing unit, and then the processing unit can obtain the target repair information based on the target.
  • the repair information is used to repair bad pixels in the memory, and the target repair information can also be stored in the target storage area, so that when the processing unit is powered on again, the processing unit can directly repair the bad pixels in the memory based on the internally stored target repair information. There is no need to obtain the target repair information from outside the processing unit, which reduces the time for the processing unit to repair memory faults, so that the processing unit can resume normal operation more quickly and shorten the system power-on recovery time.
  • Figure 3 is a schematic diagram of an on-chip system with a second memory provided by an embodiment of the present invention.
  • the on-chip memory module 202 of the on-chip system 20 is the second memory mentioned in the embodiment of the present invention.
  • the processor 200 of the system-on-chip 20 may include a CPU and a GPU (two processing units are taken as an example in Figure 3).
  • the target processing unit may be a CPU or a GPU; the CPU may include one or more first memories, The GPU may also include one or more first memories; the on-chip storage module 202 stores target repair information of the CPU and target repair information of the GPU.
  • the CPU When the CPU is powered on, if the target repair information of the CPU is not stored in the target storage area inside the CPU, the CPU can obtain its own target repair information from the on-chip storage module 202 outside the CPU, and perform memory damage based on the target repair information. point repair, and at the same time, the target repair information can also be stored in the target storage area inside the CPU, so that when the CPU is powered on again, the CPU can directly repair the bad pixels of the memory based on the internally stored target repair information without having to retrieve it from the CPU. Obtaining target repair information externally reduces the time it takes for the CPU to repair memory bad pixels. The CPU can resume normal work more quickly, shortening the system power-on recovery time.
  • the system-on-chip 20 further includes a third memory, and the third memory is a volatile memory; when the system-on-chip switches from a power-off state to a power-on state, the third memory
  • the third memory is used to: read the target repair information of the target processing unit from the second memory and store it.
  • the third memory may be a static random access memory (SRAM), that is, a volatile memory.
  • SRAM static random access memory
  • the third memory may be used to read from the second memory.
  • the target repair information of each processing unit is obtained and stored, so that when the target repair information is not stored in the target storage area inside the processing unit, the processing unit can obtain its own target repair information from an external third memory.
  • the data in the non-volatile memory is first loaded into the volatile memory, and then the processing unit retrieves the data from the volatile memory. Reading target data can reduce the time it takes for the processing unit to read data from the outside.
  • Figure 4 is a schematic diagram of a system-on-chip with a third memory provided by an embodiment of the present invention.
  • the built-in self-healing module 203 of the system-on-chip 20 in the figure can be the third memory mentioned in the embodiment of the present invention.
  • the processor 200 of the system-on-chip 20 may include a CPU and a GPU (two processing units are taken as an example in Figure 3); in the CPU
  • One or more first memories may be included, and the GPU may also include one or more first memories;
  • the on-chip storage module 202 stores the target repair information of the CPU and the target repair information of the GPU.
  • the target repair information of the CPU and the target repair information of the GPU stored in the on-chip storage module 202 can first be loaded into the built-in self-healing module 203 to reduce the time for the CPU or GPU to read data from the outside.
  • the target processing unit as a CPU as an example, when the CPU is powered on, if the target repair information of the CPU is not stored in the target storage area inside the CPU, the CPU can obtain it from the built-in self-repair module 203 outside the CPU. own target repair information, and perform memory bad pixel repair based on the target repair information.
  • the target repair information can also be stored in the target storage area inside the CPU, so that when the CPU is powered on again, the CPU can directly based on the internally stored
  • the target repair information is used to repair bad pixels in the memory without obtaining the target repair information from outside the CPU, which reduces the time for the CPU to repair bad pixels in the memory, so that the CPU can resume normal work more quickly and shorten the system power-on recovery time.
  • the target processing unit is further configured to: if the target repair information does not exist in the target storage area, obtain the target of the target processing unit from the third memory. Repair information and store it in the internal target storage area. Specifically, if there is no target repair information in the target storage area in the target processing unit, the target processing unit needs to obtain its own target repair information from the outside, that is, it can obtain its own target repair information from a third memory outside the target processing unit. information, and then the target processing unit can repair memory bad pixels based on the target repair information.
  • the target repair information can also be stored in the target storage area, so that when the target processing unit is powered on again, the target processing unit can directly use the internal
  • the stored target repair information is used to repair bad pixels in the memory, without the need to obtain the target repair information from outside the target processing unit, which reduces the time it takes for the target processing unit to repair bad pixels in the memory, so that the target processing unit can resume normal operation more quickly. , shortening the system power-on recovery time.
  • the target processing unit when the CPU is powered on, if the target repair information of the CPU is not stored in the target storage area inside the CPU, the CPU can automatically retrieve it from the built-in memory outside the CPU.
  • the repair module 203 obtains its own target repair information, and performs repair of memory bad pixels based on the target repair information.
  • the target repair information can also be stored in the target storage area inside the CPU, so that when the CPU is powered on again, the CPU can Repair the memory's bad pixels directly based on the internally stored target repair information, without having to obtain the target repair information from outside the CPU. This reduces the time it takes the CPU to repair the memory's bad pixels, so that the CPU can resume normal work more quickly and shorten the system time. Power-on recovery time.
  • FIG. 5 is a schematic diagram of the internal structure of a processing unit provided by an embodiment of the present invention.
  • Each processing unit in the figure can include one or more SRAMs, and each SRAM is divided or allocated a target storage area to store its own repair information.
  • the number of SRAMs can be adjusted according to application requirements, which will not be discussed here. Specific limitations.
  • the plurality of first memories mentioned above may constitute an SRAM in the processing unit, and the target repair information may also represent the repair information of the SRAM. Since the work flow of each SRAM in the processing unit is similar, in this embodiment of the present invention, one SRAM is taken as an example for detailed description, and the work flow of other SRAMs will not be repeated.
  • the target processing unit further includes a first register; the target processing unit is specifically configured to use the first register as the target storage area to store the target repair information.
  • a first register is added inside the target processing unit as a target storage area, specifically used to store the target repair information of the target processing unit, and the first register is still powered on when the target processing unit is in an idle power-off state. status, so that the target repair information stored in the first register is not lost when the target processing unit is idle and powered off.
  • the target processing unit can directly repair the bad pixels of the first memory based on the target repair information stored in the first register, without needing to obtain the target repair information from outside the target processing unit. This reduces the time it takes for the target processing unit to repair bad memory pixels, so that the target processing unit can resume normal operation more quickly and shorten the system power-on recovery time.
  • the first register is powered through a dedicated power domain so that when some or all components in the target processing unit except the first register are in a power-off state, the first register is in the power-on state, or the first register is powered by the normally-on power domain of the target processing unit such that when some components in the target processing unit except the first register are in the power-off state, the first register One register is in power-on state.
  • some or all components in the target processing unit except the first register may be powered on and off controlled by the first power domain, and the first register in the target processing unit may be powered on and off controlled by other power domains.
  • the target processing unit When the target processing unit is in an idle state, the target processing unit can be powered off by disconnecting the first power domain to save power, but the first register remains in the powered-on state so that the stored target repair information is not lost. Further, when the target processing unit is powered on again, the target processing unit can directly repair the bad pixels of the first memory based on the target repair information stored in the first register, without needing to obtain the target repair information from outside the target processing unit. This reduces the time it takes for the target processing unit to repair bad memory pixels, so that the target processing unit can resume normal operation more quickly and shorten the system power-on recovery time.
  • Figure 6 is a schematic diagram of the internal structure of a target processing unit provided by an embodiment of the present invention.
  • the target processing unit includes four first memories, namely C0, C1, C2 and C3; C4 is Spare memory; the first register is the target storage area, and the first register can be a reserved register; some or all components in the target processing unit except the first register can be powered on and off controlled by the first power domain VDDP, and the first power supply domain VDDP in the target processing unit can be used to control power on and off.
  • a register can control power on and off by the dedicated power domain VDD_ret and VDDP together.
  • the reserved register adopts a dual power supply structure and VDD_ret remains powered.
  • This type of register adds save and restore functions based on the ordinary register functions.
  • the save port pulse signal causes the Q terminal data to be saved to the latch in the internal VDD_ret power domain; the restore port pulse signal causes the data registered in the VDD_ret power domain to return to the Q terminal, and both operations are completed at the nanosecond level. .
  • the target repair information in order to save power consumption, before powering off VDDP and VDDC, first save the target repair information to the latch in the VDD_ret domain, and then quickly complete the target repair information and restore it to the Q terminal before the target processing unit is required to work, so that the target processing After the unit is powered on again, the target repair information can be obtained from the retention register.
  • Figure 7 is a schematic diagram of the internal structure of another target processing unit provided by an embodiment of the present invention.
  • the target processing unit includes 4 first memories, namely C0, C1, C2 and C3; C4 is the spare memory; the first register is the target storage area, and the first register can be composed of the VDDC domain register; except Some or all components other than the first register and the plurality of first memories may be powered on and off controlled by the first power domain VDDP, and the first register and the plurality of first memories may be powered on and off controlled by the second power domain VDDC.
  • VDDP is powered off, and components such as the computing unit in the target processing unit are powered off, but VDDC is not powered off so that the target repair information stored in the first register is not lost.
  • the first register may be composed of a VDDC domain register and a level converter.
  • the level converter mainly completes the normal transmission function of signals between the VDDP and VDDC power supplies.
  • the device in Figure 7 can be applied to scenarios where the digital logic circuit is powered off but the data in the first memory needs to be saved; compared to the device in Figure 6 above, the first register reduces save and restore operations, further reducing the number of operations of the target processing unit.
  • the power-on recovery time is long, but VDDC needs to remain powered.
  • the target processing unit further includes a decoding module, and the target processing unit is further configured to: obtain the target repair information from the first register through the decoding module, and Decoding configuration is performed on the plurality of first memories based on the target repair information. Specifically, when the target processing unit is powered on again, the target processing unit can directly configure multiple first memories in the target processing unit through the decoding module based on the target repair information stored in the first register, so as to avoid the use of the target processing unit. The first memory to fail.
  • the target processing unit no longer needs to obtain target repair information from outside the target processing unit after it is powered on again, the time it takes for the target processing unit to repair memory bad pixels is reduced, so that the target processing unit can resume normal operation more quickly, shortening the system Power recovery time.
  • Figure 8 is a schematic diagram of power-on recovery of a target processing unit provided by an embodiment of the present invention.
  • the target processing unit includes four first memories, namely C0, C1, C2 and C3.
  • C1 is the failed memory
  • C4 is the backup memory
  • the first register is the target storage area.
  • the decoding module obtains the target repair information from the first register and decodes it, and obtains that C1 is the faulty memory.
  • 0111 can be sent to the first memory in the target processing unit, and then C1 is isolated through the selector, and then the backup memory C4 can be enabled to prevent the target processing unit from using the failed first memory.
  • Figure 9 is a schematic diagram of another target processing unit power-on recovery provided by an embodiment of the present invention.
  • the target processing unit includes four first memories, namely C0, C1, C2 and C3, where C1 is the failed memory; C4 is the backup memory; the first register is the target storage area.
  • the decoding module obtains the target repair information from the first register and decodes it, and obtains that C1 is the faulty memory.
  • 0111 can be sent to the first memory in the target processing unit, and then C1 is isolated through the selector, and then the backup memory C4 can be enabled to prevent the target processing unit from using the failed first memory.
  • the target processing unit is specifically configured to: use the plurality of first memories as the target storage areas to store the target repair information, and the plurality of first memories pass the target
  • the normally-on power domain supply of the processing unit causes the plurality of first memories to be in a powered-on state when some components in the target processing unit except for the plurality of first memories are in a powered-off state.
  • a target storage area is divided among the plurality of first memories inside the target processing unit, which is specially used to store the target repair information of the target processing unit, and the storage area is still on when the target processing unit is in an idle power-off state. power state, so that the target repair information stored in the storage area is not lost when the target processing unit is idle and powered off.
  • the target processing unit can directly repair the bad pixels of the first memory based on the target repair information stored in the plurality of first memories, without needing to obtain the target repair information from outside the target processing unit. , reducing the time for the target processing unit to repair bad memory pixels, so that the target processing unit can resume normal operation more quickly and shorten the system power-on recovery time.
  • Figure 10 is a schematic diagram of the internal structure of another target processing unit provided by an embodiment of the present invention.
  • the target processing unit includes 4 first memories, namely C0, C1, C2 and C3; C4 is the spare memory; C0', C1', C2' and C3' are divided target storage areas; in the target processing unit Some or all components except the first memory can be powered on and off controlled by VDDP, and the first memory in the target processing unit can be powered on and off controlled by VDDC.
  • VDDP is powered off, and components such as the computing unit in the target processing unit are powered off, but VDDC is not powered off so that the target repair information stored in the first memory is not lost.
  • SRAM is a device with extremely high area utilization.
  • the above-mentioned device in Figure 6 and the above-mentioned device in Figure 7 may lead to an increase in the ineffective area of the SRAM, thereby leading to a serious waste of SoC resources. Therefore, the above-mentioned device of FIG. 10 directly uses multiple first memories to store target repair information, which has less impact on the area.
  • the target processing unit includes a second register
  • the target processing unit is further configured to: after the target processing unit switches from the first mode to the second mode,
  • the target repair information is obtained from the plurality of first memories through the second register and stored.
  • a second register can be added to the target processing unit, and the second register is also in a power-off state when the target processing unit is powered off.
  • the second register can obtain the target repair information from the first memory and store it.
  • the second register first obtains the target repair information from C0', C1', C2' and C3' and saves it so that the subsequent decoding module can process the target repair information. Decode.
  • the target processing unit further includes a decoding module, and the target processing unit is further configured to: obtain the target repair information from the second register through the decoding module, and Decoding configuration is performed on the plurality of first memories based on the target repair information.
  • the target processing unit can configure multiple first memories in the target processing unit through the decoding module based on the target repair information in the second register, so as to avoid the use of the target processing unit. Faulty first memory. Since the target processing unit no longer needs to obtain target repair information from outside the target processing unit after it is powered on again, the time it takes for the target processing unit to repair memory bad pixels is reduced, so that the target processing unit can resume normal operation more quickly, shortening the system Power recovery time.
  • Figure 11 is a schematic diagram of another target processing unit power-on recovery provided by an embodiment of the present invention.
  • the target processing unit includes four first memories, namely C0, C1, C2 and C3. , where C1 is the failed memory; C4 is the backup memory; C0', C1', C2' and C3' are the divided target storage areas.
  • the second register first reads the target repair information from C0', C1', C2' and C3' and stores it, and then the decoding module obtains the target repair information from the second register and performs decoding. code, it is obtained that C1 is the faulty memory. Further, 0111 can be sent to the first memory in the target processing unit, and then C1 is isolated through the selector, and then the backup memory C4 can be enabled to prevent the target processing unit from using the failed first memory.
  • the target processing unit further includes a backup memory; the target processing unit is specifically configured to: based on the target repair information, determine the failed first memory through the decoding module ;Isolate dead pixels on the failed first memory and enable the backup memory. Specifically, when the target processing unit is powered on again, the target processing unit can directly determine the failed first memory among the plurality of first memories based on the target repair information stored in the target storage area through the decoding module, and save the failed first memory. The first memory is isolated from dead pixels, and then the backup memory is enabled to prevent the target processing unit from using the failed first memory, causing system abnormalities.
  • Figure 12 is a schematic diagram of a system power-on recovery process provided by an embodiment of the present invention.
  • a module ie, a processing unit
  • the module is first powered on, and then it is determined whether It is a boot scenario. If not, the processing unit directly obtains the local target repair information from the target storage area and inputs it into the SRAM. After the module completes the recovery of the configuration information, it starts to work normally; if it is, it can obtain its own target repair from the on-chip storage module. information, and serially input the target repair information into each SRAM of the module. After the module completes the configuration, it starts to work normally and needs to be configured at the same time. The setting information is saved and the target repair information is stored inside the processing unit.
  • a target storage area is added or divided inside the target processing unit, which is specially used to store the target repair information of the target processing unit, and the target storage area is still in the idle power-off state when the target processing unit is idle.
  • the power-on state is such that the target repair information stored in the target storage area is not lost when the target processing unit is idle and powered off. Therefore, when the target processing unit is powered on again, the target processing unit can directly repair the bad pixels of the first memory based on the internally stored target repair information, without needing to obtain the target repair information from outside the target processing unit, which reduces the number of targets.
  • the time it takes for the processing unit to repair bad memory pixels allows the target processing unit to resume normal operation more quickly, shortening the system power-on recovery time.
  • Figure 13 is a flow chart of a system power-on recovery method provided by an embodiment of the present invention. This method is applicable to the system-on-chip in Figure 2 and devices including the system-on-chip.
  • the method may include the following steps S301 to S302.
  • the on-chip system includes N processing units.
  • a target processing unit among the N processing units includes a plurality of first memories.
  • the plurality of first memories are all volatile memories.
  • the target processing unit is the Any one of the N processing units, N and M are integers greater than 0.
  • Step S301 Use the target processing unit to store target repair information in an internal target storage area, where the target repair information is information about a failed first memory among the plurality of first memories.
  • Step S302 After the target processing unit switches from the first mode to the second mode, the target processing unit reads the target repair information from the target storage area, and performs repair on the plurality of first memories. Bad pixel repair.
  • the target processing unit in the first mode, some or all components in the target processing unit except the target storage area are in a power-off state, and the target storage area is in a power-on state; in the In the second mode, the entire target processing unit is in a powered-on state.
  • the system-on-chip further includes a second memory, and the second memory is a non-volatile memory; the method further includes: storing the N processing units through the second memory The target repair information of each processing unit in .
  • the system-on-chip further includes a third memory, and the third memory is a volatile memory; when the system-on-chip switches from a power-off state to a power-on state, the method also It includes: reading the target repair information of the target processing unit from the second memory through the third memory and storing it.
  • the method further includes: if the target repair information does not exist in the target storage area, obtaining the data of the target processing unit from the third memory through the target processing unit.
  • the target repair information is stored in the internal target storage area.
  • the target processing unit further includes a first register; and storing the target repair information in an internal target storage area through the target processing unit includes: using the first register as The target storage area stores the target repair information.
  • the first register is powered through a dedicated power domain so that when some or all components in the target processing unit except the first register are in a power-off state, the first register is in the power-on state, or the first register is powered by the normally-on power domain of the target processing unit such that when some components in the target processing unit except the first register are in the power-off state, the first register One register is in power-on state.
  • the target processing unit further includes a decoding module
  • the method further includes: obtaining the target from the first register through the decoding module in the target processing unit. Repair information, and decode and configure the plurality of first memories based on the target repair information.
  • storing the target repair information in an internal target storage area through the target processing unit includes: using the plurality of first memories as the target storage areas to store the target repair information.
  • Information the plurality of first memories are powered by the normally-on power domain of the target processing unit, so that when some components in the target processing unit except the plurality of first memories are in a power-off state, the plurality of first memories are powered off.
  • the first memory is in the power-on state.
  • the target processing unit includes a second register
  • the method further includes: after the target processing unit switches from the first mode to the second mode, through the The second register obtains the target repair information from the plurality of first memories and stores it.
  • the target processing unit further includes a decoding module
  • the method further includes: obtaining the target from the second register through the decoding module in the target processing unit. Repair information, and decode and configure the plurality of first memories based on the target repair information.
  • the target processing unit further includes a spare memory; repairing bad pixels on the plurality of first memories includes: based on the target repair information, determining through the decoding module The first memory that has failed; performs dead pixel isolation on the first memory that has failed, and enables the backup memory.
  • the recovery time after the processing unit is powered on can be shortened.
  • the present application provides a computer storage medium, which is characterized in that the computer storage medium stores a computer program, and when the computer program is executed by a processor, any one of the above system power-on recovery methods is implemented.
  • An embodiment of the present application provides an electronic device.
  • the electronic device includes a processor.
  • the processor is configured to support the electronic device to implement corresponding functions in any of the above system power-on recovery methods.
  • the electronic device may also include a memory coupled to the processor that stores necessary program instructions and data for the electronic device.
  • the electronic device may also include a communication interface for the electronic device to communicate with other devices or communication networks.
  • the present application provides a chip system.
  • the chip system includes a processor and is used to support an electronic device to implement the above-mentioned functions, for example, generate or process information involved in the above-mentioned system power-on recovery method.
  • the chip system further includes a memory, and the memory is used to store necessary program instructions and data of the electronic device.
  • the chip system may be composed of chips, or may include chips and other discrete devices.
  • the present application provides a computer program, which is characterized in that the computer program includes instructions that, when the computer program is executed by a computer, cause the computer to execute the above-mentioned system power-on recovery method.
  • the disclosed device can be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the above units is only a logical function division. In actual implementation, there may be other divisions.
  • multiple units or components may be combined or integrated. to another system, or some features can be ignored, or not implemented.
  • the coupling or direct coupling or communication connection between each other shown or discussed may be through some interfaces, and the indirect coupling or communication connection of the devices or units may be in electrical or other forms.
  • the units described above as separate components may or may not be physically separated.
  • the components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application can be integrated into one processing unit, each unit can exist physically alone, or two or more units can be integrated into one unit.
  • the above integrated units can be implemented in the form of hardware or software functional units.
  • the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium.
  • the technical solution of the present application is essentially or contributes to the existing technology, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , including several instructions to cause a computer device (which can be a personal computer, a server or a network device, etc., specifically a processor in a computer device) to execute all or part of the steps of the above methods in various embodiments of the present application.
  • a computer device which can be a personal computer, a server or a network device, etc., specifically a processor in a computer device
  • the aforementioned storage media may include: U disk, mobile hard disk, magnetic disk, optical disk, read-only memory (Read-Only Memory, abbreviation: ROM) or random access memory (Random Access Memory, abbreviation: RAM), etc.
  • U disk mobile hard disk
  • magnetic disk magnetic disk
  • optical disk read-only memory
  • read-only memory Read-Only Memory
  • RAM random access memory

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Abstract

本申请实施例公开了一种片上系统及相关系统上电恢复方法，其特征在于，所述片上系统包括N个处理单元，所述N个处理单元中的目标处理单元包括多个第一存储器，其中，所述目标处理单元用于：在内部的目标存储区域中存储目标修复信息，所述目标修复信息为多个第一存储器中出现故障的第一存储器的信息；当目标处理单元从第一模式切换到第二模式后，从目标存储区域读取目标修复信息，并对多个第一存储器进行坏点修复；其中，在第一模式下，目标处理单元中除目标存储区域以外的部分或全部部件处于下电状态，且目标存储区域处于上电状态；在第二模式下，目标处理单元整体处于上电状态。采用本发明实施例可以缩短处理单元上电后的恢复时间。

Description

一种片上系统及相关系统上电恢复方法
本申请要求于2022年05月13日提交中国专利局、申请号为202210519490.0、申请名称为“一种片上系统及相关系统上电恢复方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电子电路技术领域，尤其涉及一种片上系统及相关系统上电恢复方法。
背景技术
片上系统(System on Chip，SOC)，是指在单个芯片上集成一个完整的系统，对所有或部分必要的电子电路进行包分组的技术，即可以在一个芯片上集成中央处理单元、调制解调处理单元、图像信号处理单元、视频编解码单元、数字信号处理单元等多种处理单元，以及存储器模块、电源等模块。随着SOC的广泛应用，为降低SOC的功耗，SOC上的每个处理单元在空闲状态下可以进行下电操作，需要工作时再进行上电操作，避免了处理单元在空闲且未下电的状态下依旧消耗大量电能的问题。但当处理单元再次上电后，需要先进行上电恢复(如处理单元上电后需要先进行内部存储器的坏点修复)，然后才能开始正常工作。在一些面向高帧率的游戏，虚拟现实技术(Virtual Reality，VR)或新型穿戴设备等应用场景下，处理单元的上电恢复时间越长，则会限制各处理单元空闲下电的使用场景，影响用户体验。
因此，如何提供一种片上系统及相关的上电恢复方法，以缩短处理单元上电后的恢复时间，是亟待解决的问题。
发明内容
本申请实施例所要解决的技术问题在于，提供一种片上系统及相关系统上电恢复方法，以缩短系统上电后的恢复时间。
第一方面，本申请实施案例提供一种片上系统，其特征在于，所述片上系统包括N个处理单元，所述N个处理单元中的目标处理单元包括多个第一存储器，所述多个第一存储器均为易失性存储器，所述目标处理单元为所述N个处理单元中的任意一个处理单元，N、M为大于0的整数，其中，所述目标处理单元用于：在内部的目标存储区域中存储目标修复信息，所述目标修复信息为所述多个第一存储器中出现故障的第一存储器的信息；当所述目标处理单元从第一模式切换到第二模式后，从所述目标存储区域读取所述目标修复信息，并对所述多个第一存储器进行坏点修复；其中，在所述第一模式下，所述目标处理单元中除所述目标存储区域以外的部分或全部部件处于下电状态，且所述目标存储区域处于上电状态；在所述第二模式下，所述目标处理单元整体处于上电状态。
在本发明实施例中，通过在片上系统内部的每个处理单元内部都新增或划分一个目标存储区域，专门用于存储每个处理单元自身的目标修复信息，且将该目标存储区域配置为当处理单元下电时，该目标存储区域依旧可以处于上电状态，以使得每个处理单元重新上电后可以直接基于内部的目标修复信息进行存储器的坏点修复，而无需从处理单元外部去获取相应的目标修复信息，大大地缩短了处理单元上电后的存储器故障修复时间。具体地，在处理单 元的内部增加或划分一个目标存储区域，专门用于存储处理单元自身的目标修复信息(即为处理单元内部出现故障的第一存储器的相关信息)，且该目标存储区域在处理单元下电时依旧处于上电状态(例如为目标存储区域设置单独的供电电源)，以使得目标存储区域存储的目标修复信息在处理单元下电时不丢失。进一步地，当处理单元下电之后又重新上电时，由于目标存储区域一直处于上电状态(即存储在该目标存储区域中的目标修复信息未丢失)，因此处理单元可从内部未下电的目标存储区域中直接获得自身的目标修复信息，而无需再从外部的存储模块获取对应的目标修复信息。而在现有技术中，处理单元每次下电后，由于处理单元未对目标修复信息进行存储，因此当处理单元再次上电时，需要向处理单元外部的存储模块获取自身的目标修复信息，导致处理单元上电后的存储器故障修复时间过长的问题。综上，在本发明实施例中的处理单元重新上电时，处理单元可以直接基于内部存储的目标修复信息进行第一存储器的坏点修复，而无需再从处理单元外部获取目标修复信息，减少了处理单元进行存储器故障修复的时间，从而处理单元能够更加快速地恢复正常工作，缩短了系统上电恢复时间。
在一种可能的实现方式中，所述片上系统还包括第二存储器，所述第二存储器为非易失性存储器；所述第二存储器用于：存储所述N个处理单元中每个处理单元的所述目标修复信息。
在本发明实施例中，片上系统首次上电使用前，可对每个处理单元都进行硬件测试得到每个处理单元的目标修复信息，然后可将每个处理单元的目标修复信息都存储在第二存储器中，由于该第二存储器为非易失性存储器(即下电后数据不会丢失)，因此在第二存储器处于下电状态时，各个处理单元的目标修复信息也不会丢失。进一步地，当处理单元上电后，若处理单元内部的目标存储区域中没有目标修复信息，则可以从处理单元外部的第二存储器中获取自身的目标修复信息，进而处理单元可以基于该目标修复信息进行存储器坏点修复，同时还可以将该目标修复信息存储至目标存储区域，以使得处理单元再次上电时，处理单元可以直接基于内部存储的目标修复信息进行存储器的坏点修复，而无需再从处理单元外部获取该目标修复信息，减少了处理单元进行存储器故障修复的时间，从而处理单元能够更加快速地恢复正常工作，缩短了系统上电恢复时间。
在一种可能的实现方式中，所述片上系统还包括第三存储器，所述第三存储器为易失性存储器；当所述片上系统从下电状态切换为上电状态时，所述第三存储器还用于：从所述第二存储器读取所述目标处理单元的所述目标修复信息并进行存储。
在本发明实施例中，第三存储器可以为静态随机存取存储器(SRAM)，即易失性存储器，当片上系统从下电状态切换为上电状态时，该第三存储器可用于从第二存储器中读取每个处理单元的目标修复信息并进行存储，以便于在处理单元内部的目标存储区中没有目标修复信息时，处理单元能够从外部的第三存储器中获取到自身的目标修复信息。由于处理单元访问非易失性存储器的速度远小于访问易失性存储器的速度，因此将非易失性存储器中的数据先加载至易失性存储器中，然后处理单元再从易失性存储器中读取目标数据，能够降低处理单元从外部读取数据的时间。
在一种可能的实现方式中，所述目标处理单元还用于：若所述目标存储区域中不存在所述目标修复信息，则从所述第三存储器获取所述目标处理单元的所述目标修复信息，并存储至内部的所述目标存储区域中。
在本发明实施例中，若目标处理单元中的目标存储区域中不存在目标修复信息，则目标处理单元需要从外部获取自身的目标修复信息，即可以从目标处理单元外部的第三存储器中 获取自身的目标修复信息，进而目标处理单元可以基于该目标修复信息进行存储器坏点修复，同时还可以将该目标修复信息存储至目标存储区域，以使得在目标处理单元再次上电时，目标处理单元可以直接基于内部存储的目标修复信息进行存储器的坏点修复，而无需再从目标处理单元外部获取该目标修复信息，减少了目标处理单元进行存储器坏点修复的时间，从而目标处理单元能够更加快速地恢复正常工作，缩短了系统上电恢复时间。
在一种可能的实现方式中，所述目标处理单元中还包括第一寄存器；所述目标处理单元具体用于：将所述第一寄存器作为所述目标存储区域存储所述目标修复信息。
在本发明实施例中，目标处理单元的内部增加一个第一寄存器作为目标存储区域，专门用于存储目标处理单元的目标修复信息，且该第一寄存器在目标处理单元处于空闲下电状态时依旧处于上电状态，以使得第一寄存器存储的目标修复信息在目标处理单元处于空闲下电时不丢失。因此，在该目标处理单元重新上电时，目标处理单元可以直接基于第一寄存器存储的目标修复信息进行第一存储器的坏点修复，而无需再从目标处理单元外部获取该目标修复信息，减少了目标处理单元进行存储器坏点修复的时间，从而目标处理单元能够更加快速地恢复正常工作，缩短了系统上电恢复时间。
在一种可能的实现方式中，所述第一寄存器通过专用电源域供电使得在所述目标处理单元中除所述第一寄存器以外的部分或全部部件处于下电状态时，所述第一寄存器处于上电状态，或者所述第一寄存器通过所述目标处理单元的常开电源域供电使得在所述目标处理单元中除所述第一寄存器以外的部分部件处于下电状态时，所述第一寄存器处于上电状态。
在本发明实施例中，目标处理单元中除第一寄存器以外的部分或全部部件可以由第一电源域来控制上下电，目标处理单元中第一寄存器可由其他电源域来控制上下电。在目标处理单元处于空闲状态时，可以通过断开第一电源域使得目标处理单元处于下电状态以节约电能，但第一寄存器一直保持在上电状态以使得存储的目标修复信息不丢失。进一步地，在该目标处理单元重新上电时，目标处理单元可以直接基于第一寄存器存储的目标修复信息进行第一存储器的坏点修复，而无需再从目标处理单元外部获取该目标修复信息，减少了目标处理单元进行存储器坏点修复的时间，从而目标处理单元能够更加快速地恢复正常工作，缩短了系统上电恢复时间。
在一种可能的实现方式中，所述目标处理单元中还包括译码模块，所述目标处理单元还用于：通过所述译码模块从所述第一寄存器获取所述目标修复信息，并基于所述目标修复信息对所述多个第一存储器进行译码配置。
在本发明实施例中，目标处理单元重新上电时，目标处理单元可以直接基于第一寄存器存储的目标修复信息通过译码模块对目标处理单元中的多个第一存储器进行配置，以避免目标处理单元使用出现故障的第一存储器。由于目标处理单元重新上电后无需再从目标处理单元外部获取目标修复信息，因此减少了目标处理单元进行存储器坏点修复的时间，从而目标处理单元能够更加快速地恢复正常工作，缩短了系统上电恢复时间。
在一种可能的实现方式中，所述目标处理单元具体用于：将所述多个第一存储器作为所述目标存储区域存储所述目标修复信息，所述多个第一存储器通过所述目标处理单元的常开电源域供电使得在所述目标处理单元中除所述多个第一存储器以外的部分部件处于下电状态时，所述多个第一存储器处于上电状态。
在本发明实施例中，在目标处理单元内部的多个第一存储器中划分一个目标存储区域，专门用于存储目标处理单元的目标修复信息，且该存储区域在目标处理单元处于空闲下电状态时依旧处于上电状态，以使得存储区域存储的目标修复信息在目标处理单元处于空闲下电 时不丢失。因此，在该目标处理单元重新上电时，目标处理单元可以直接基于多个第一存储器存储的目标修复信息进行第一存储器的坏点修复，而无需再从目标处理单元外部获取该目标修复信息，减少了目标处理单元进行存储器坏点修复的时间，从而目标处理单元能够更加快速地恢复正常工作，缩短了系统上电恢复时间。
在一种可能的实现方式中，所述目标处理单元中包括第二寄存器，所述目标处理单元还用于：当所述目标处理单元从所述第一模式切换到所述第二模式后，通过所述第二寄存器从所述多个第一存储器中获取所述目标修复信息并进行存储。
在本发明实施例中，为便于后续对目标修复信息进行译码，可以在目标处理单元中增加一个第二寄存器，且目标处理单元下电该第二寄存器也处于下电状态。当目标处理单元再次上电时，第二寄存器可以从第一存储器获取目标修复信息并进行存储。
在一种可能的实现方式中，所述目标处理单元中还包括译码模块，所述目标处理单元还用于：通过所述译码模块从所述第二寄存器获取所述目标修复信息，并基于所述目标修复信息对所述多个第一存储器进行译码配置。
在本发明实施例中，目标处理单元重新上电时，目标处理单元可以基于第二寄存器中的目标修复信息通过译码模块对目标处理单元中的多个第一存储器进行配置，以避免目标处理单元使用出现故障的第一存储器。由于目标处理单元重新上电后无需再从目标处理单元外部获取目标修复信息，因此减少了目标处理单元进行存储器坏点修复的时间，从而目标处理单元能够更加快速地恢复正常工作，缩短了系统上电恢复时间。
在一种可能的实现方式中，所述目标处理单元还包括备用存储器；所述目标处理单元具体用于：基于所述目标修复信息，通过所述译码模块确定所述出现故障的第一存储器；对所述出现故障的第一存储器进行坏点隔离，并启用所述备用存储器。
在本发明实施例中，在目标处理单元重新上电时，目标处理单元可以直接基于目标存储区域存储的目标修复信息通过译码模块确定多个第一存储器中出现故障的第一存储器，并将出现故障的第一存储器进行坏点隔离，然后启用备用存储器，以避免目标处理单元使用出现故障的第一存储器，导致系统异常。同时，由于目标处理单元重新上电后无需再从目标处理单元外部获取目标修复信息，因此减少了目标处理单元进行存储器坏点修复的时间，从而目标处理单元能够更加快速地恢复正常工作，缩短了系统上电恢复时间。
第二方面，本申请提供了一种系统上电恢复方法，其特征在于，应用于片上系统，所述片上系统包括N个处理单元，所述N个处理单元中的目标处理单元包括多个第一存储器，所述多个第一存储器均为易失性存储器，所述目标处理单元为所述N个处理单元中的任意一个处理单元，N、M为大于0的整数，所述方法包括：通过所述目标处理单元在内部的目标存储区域中存储目标修复信息，所述目标修复信息为所述多个第一存储器中出现故障的第一存储器的信息；当所述目标处理单元从第一模式切换到第二模式后，通过所述目标处理单元从所述目标存储区域读取所述目标修复信息，并对所述多个第一存储器进行坏点修复；其中，在所述第一模式下，所述目标处理单元中除所述目标存储区域以外的部分或全部部件处于下电状态，且所述目标存储区域处于上电状态；在所述第二模式下，所述目标处理单元整体处于上电状态。
在一种可能的实现方式中，所述片上系统还包括第二存储器，所述第二存储器为非易失性存储器；所述方法还包括：通过所述第二存储器存储所述N个处理单元中每个处理单元的所述目标修复信息。
在一种可能的实现方式中，所述片上系统还包括第三存储器，所述第三存储器为易失性存储器；当所述片上系统从下电状态切换为上电状态时，所述方法还包括：通过所述第三存储器从所述第二存储器读取所述目标处理单元的所述目标修复信息并进行存储。
在一种可能的实现方式中，所述方法还包括：若所述目标存储区域中不存在所述目标修复信息，则通过所述目标处理单元从所述第三存储器获取所述目标处理单元的所述目标修复信息，并存储至内部的所述目标存储区域中。
在一种可能的实现方式中，所述目标处理单元中还包括第一寄存器；所述通过所述目标处理单元在内部的目标存储区域中存储目标修复信息，包括：将所述第一寄存器作为所述目标存储区域存储所述目标修复信息。
在一种可能的实现方式中，所述第一寄存器通过专用电源域供电使得在所述目标处理单元中除所述第一寄存器以外的部分或全部部件处于下电状态时，所述第一寄存器处于上电状态，或者所述第一寄存器通过所述目标处理单元的常开电源域供电使得在所述目标处理单元中除所述第一寄存器以外的部分部件处于下电状态时，所述第一寄存器处于上电状态。
在一种可能的实现方式中，所述目标处理单元中还包括译码模块，所述方法还包括：通过所述目标处理单元中的所述译码模块从所述第一寄存器获取所述目标修复信息，并基于所述目标修复信息对所述多个第一存储器进行译码配置。
在一种可能的实现方式中，所述通过所述目标处理单元在内部的目标存储区域中存储目标修复信息，包括：将所述多个第一存储器作为所述目标存储区域存储所述目标修复信息，所述多个第一存储器通过所述目标处理单元的常开电源域供电使得在所述目标处理单元中除所述多个第一存储器以外的部分部件处于下电状态时，所述多个第一存储器处于上电状态。
在一种可能的实现方式中，所述目标处理单元中包括第二寄存器，所述方法还包括：当所述目标处理单元从所述第一模式切换到所述第二模式后，通过所述第二寄存器从所述多个第一存储器中获取所述目标修复信息并进行存储。
在一种可能的实现方式中，所述目标处理单元中还包括译码模块，所述方法还包括；通过所述目标处理单元中的所述译码模块从所述第二寄存器获取所述目标修复信息，并基于所述目标修复信息对所述多个第一存储器进行译码配置。
在一种可能的实现方式中，所述目标处理单元还包括备用存储器；所述对所述多个第一存储器进行坏点修复，包括：基于所述目标修复信息，通过所述译码模块确定所述出现故障的第一存储器；对所述出现故障的第一存储器进行坏点隔离，并启用所述备用存储器。
第三方面，本申请提供了一种计算机存储介质，其特征在于，所述计算机存储介质存储有计算机程序，该计算机程序被处理器执行时实现上述第二方面任意一项所述的方法。
第四方面，本申请实施例提供一种电子设备，该电子设备中包括处理器，处理器被配置为支持该电子设备实现第二方面提供的一种系统上电恢复方法中相应的功能。该电子设备还可以包括存储器，存储器用于与处理器耦合，其保存该电子设备必要的程序指令和数据。该电子设备还可以包括通信接口，用于该电子设备与其他设备或通信网络通信。
第五方面，本申请提供了一种芯片系统，该芯片系统包括处理器，用于支持电子设备实现上述第二方面中所涉及的功能，例如，生成或处理上述系统上电恢复方法中所涉及的信息。在一种可能的设计中，所述芯片系统还包括存储器，所述存储器，用于保存电子设备必要的程序指令和数据。该芯片系统，可以由芯片构成，也可以包含芯片和其他分立器件。
第六方面，本申请提供一种计算机程序，其特征在于，所述计算机程序包括指令，当所述计 算机程序被计算机执行时，使得所述计算机执行上述第三方面中任意一项所述的方法。
附图说明
图1为本发明实施例提供的一种片上系统的结构示意图。
图2为本发明实施例提供的一种片上系统示意图。
图3为本发明实施例提供的一种具有第二存储器的片上系统的示意图。
图4为本发明实施例提供的一种具有第三存储器的片上系统的示意图。
图5为本发明实施例提供的一种处理单元内部结构示意图。
图6为本发明实施例提供的一种目标处理单元内部结构示意图。
图7为本发明实施例提供的另一种目标处理单元内部结构示意图。
图8为本发明实施例提供的一种目标处理单元上电恢复示意图。
图9为本发明实施例提供的另一种目标处理单元上电恢复示意图。
图10为本发明实施例提供的又一种目标处理单元内部结构示意图。
图11为本发明实施例提供的又一种目标处理单元上电恢复示意图。
图12为本发明实施例提供的一种系统上电恢复流程示意图。
图13是本发明实施例提供的一种系统上电恢复方法的流程图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例进行描述。
本申请的说明书和权利要求书及所述附图中的术语“第一”、“第二”、“第三”和“第四”等是用于区别不同对象，而不是用于描述特定顺序。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
基于上述，本发明实施例提供一种片上系统。请参见图1，图1为本发明实施例提供的一种片上系统的结构示意图，片上系统(System on Chip，SOC)是指在单个芯片上集成一个完整的系统，对所有或部分必要的电子电路进行包分组的技术。片上系统10一般可以包括处理器100、片上存储模块101、内置自修复模块102和外围部件电路等，且片上系统10可内置于各种电子设备中，如服务器、个人计算机、平板电脑、手机、个人数字助理、智能穿戴设备等各类设备。具体地，
处理器100，可运行操作系统、文件系统或应用程序等，以控制连接到处理器100的多个硬件或软件元件，并且可处理各种数据并执行操作。处理器100可以包括一个或多个处理单元(也可称处理核)，例如：处理器100可以包括中央处理单元(Central Processing Unit，CPU)、调制解调处理单元、图形处理单元(graphics processing unit，GPU)、图像信号处理单元(image signal processor，ISP)、视频编解码单元、数字信号处理单元(digital signal processor， DSP)、基带处理单元和神经网络处理单元(neural-network processing unit，NPU)等中的一个或多个。其中，不同的处理单元可以是独立的器件，也可以集成在一个或多个器件中。处理器100中的每个处理单元(如CPU)可将片上存储模块101中存储的指令或数据加载到处理单元内部的存储器中，并把需要运算的指令或数据调到计算单元中进行运算，当运算完成后计算单元再将结果临时存储在内部的存储器中，并将需要长期存储的指令或数据存储至片上存储模块101中。此外，若片上存储模块101中存储了多个处理单元中每个处理单元的存储器的修复信息，那么处理器100中的每个处理单元(如CPU)可将片上存储模块101中所存储的修复信息加载至处理单元内部并进行存储器的坏点修复。可选的，片上存储模块101存储的一个或多个存储器的修复信息是不可更改且不可擦除的。
需要说明的是，每个处理单元(如CPU)内部的存储器通常为掉电易失性存储器，断电时会丢失其上存储的内容。每个处理单元内部的存储器都可用于暂时存放处理单元(如CPU)中的运算数据，以及与片上存储模块101或其他外部存储器交互数据，可作为操作系统或其他正在运行中的程序的临时数据的存储媒介。例如，运行于CPU上的操作系统把需要运算的数据从内部的存储器调到计算单元中进行运算，当运算完成后计算单元再将结果传送出来并临时存储在内部的存储器中。处理单元内部的存储器可以包括静态随机存取存储器(Static Random Access Memory，SRAM)，其中，静态随机存取存储器又可包括单端口静态随机存取存储器以及双端口静态随机存取存储器。
片上存储模块101，为掉电非易失性存储器，断电后其存储的内容不会丢失。片上存储模块101可用于长期存储处理器100运行所涉及的指令和数据，如本申请涉及的每个处理单元(如CPU)内部的存储器的修复信息、启动程序、操作系统、应用程序和数据等。由于处理器100中的处理单元不能直接读取片上存储模块101中的指令和数据，也不能直接向片上存储模块101写入指令或数据。因此，处理单元(如CPU)在执行读(或加载)命令时，实际上是将存储在片上存储模块101中的待读内容(包括指令和/或数据)先临时加载至内部的存储器中，然后再由CPU从内部的存储器中读出；而在执行写(即存储)命令时，实际上是由CPU先将待存储数据(包括指令和/或数据)临时写入至内部的存储器中，然后再从内部的存储器存储至片上存储模块101中。片上存储模块101可以包括Flash闪存(例如，NAND闪存、NOR闪存等)、通用闪存存储器(universal flash storage，UFS)、嵌入式多媒体卡eMMC、通用闪存存储多芯片封装uMCP存储器、嵌入式多媒体卡多芯片封装eMCP存储器、固态驱动器(SSD)等中的一个或多个。片上存储模块101还可以包括一次性可编程存储器(eFuse)，该eFuse可专门用于存储处理器100中每个处理单元的存储器的修复信息，以使得存储的一个或多个存储器的修复信息不可更改也不可擦除。
内置自修复模块102，位于处理器100外部，可以包括静态随机存取存储器(SRAM)，可用于从片上存储模块101中读取每个处理单元(如CPU)内部的存储器的修复信息并进行存储，以便于各个处理单元上电时能够再从内置自修复模块102直接获取到各自内部的存储器的修复信息。每个处理单元内部的存储器在生产过程中会出现无法避免的故障，因此在生产时可以设计备用存储器，当存储器出现故障时可以使用备用的存储器来维持正常工作。在首次使用片上系统10前，需要先对硬件进行测试，若在硬件测试中发现某个存储器出现故障，则可以将出现故障的存储器进行标记得到修复信息，并且可以将该修复信息存储至片上存储模块101中(SOC下电后该信息也不会丢失)。每个处理单元上电后，需要进行存储器的坏点修复，进而处理单元(如CPU)才能恢复正常工作，即每个处理单元都需要先获取各自内部的存储器的修复信息，从而基于修复信息将出现故障的存储器进行隔离并可将其关联至备 用的存储器进行使用。由于上电后处理单元(如CPU)无法直接读取片上存储模块101中的数据，且在处理单元未获取到内部的存储器的修复信息前，为避免将数据加载到出现故障的存储器中，处理单元也不会直接使用内部的存储器，因此可通过内置自修复模块102先从片上存储模块101中读取所有处理单元内部的存储器的修复信息并进行存储，从而各个处理单元上电后可以直接从内置自修复模块102获取到各自的存储器的修复信息，然后可基于该修复信息进行存储器的坏点修复。在本发明实施例中，可在处理单元中增加或划分一个存储模块，该存储模块用于存储内部的存储器的修复信息，且在该处理单元下电后修复信息不会丢失(即处理单元下电后，修复信息依旧存储在处理单元内部)，因此该处理单元再次上电时，处理单元可以直接基于存储的修复信息进行存储器的坏点修复，而无需再从处理单元外部获取该修复信息，减少了处理单元进行存储器故障修复的时间，从而处理单元能够更加快速地恢复正常工作，缩短了系统上电恢复时间。
可以理解的是，图1中的片上系统10的结构只是本发明实施例提供的一些示例性的实施方式，本发明实施例中的片上系统10的结构包括但不仅限于以上实现方式。
下面结合本发明实施例中的附图对本发明实施例进行描述。
请参见图2，图2为本发明实施例提供的一种片上系统示意图，下面将结合附图2对本申请实施例中的片上系统进行详细描述。如图2所示，该片上系统20包括：N个处理单元201，所述N个处理单元中的目标处理单元包括多个第一存储器，所述多个第一存储器均为易失性存储器，所述目标处理单元为所述N个处理单元中的任意一个处理单元，N为大于0的整数。需要说明的是，图2中的片上系统20可以包括上述图1中片上系统10的部分或全部功能，N个处理单元201可以包括上述图1中的处理器100的处理单元的全部或部分功能。其中，
所述目标处理单元用于：在内部的目标存储区域中存储目标修复信息，所述目标修复信息为所述多个第一存储器中出现故障的第一存储器的信息。具体地，片上系统20中可以包括一个或多个处理单元，处理单元可以为中央处理单元(CPU)、调制解调处理单元、图形处理单元(GPU)、图像信号处理单元(ISP)、视频编解码单元、数字信号处理单元(DSP)、基带处理单元和神经网络处理单元(NPU)等。在每个处理单元的内部可包括多个第一存储器，且每个处理单元内部的第一存储器的数量可以相同，也可以不同，在此不作限定。第一存储器通常为掉电易失性存储器，断电时会丢失其上存储的内容。第一存储器的作用是暂时存放处理单元(如CPU)中的运算数据(如CPU中计算单元的运算结果)，以及与片上的存储模块或其他外部存储器交互数据，可作为操作系统或其他正在运行中的程序的临时数据的存储媒介。由于每个处理单元内部的第一存储器在生产过程中会出现无法避免的故障，因此在对片上系统20首次上电使用前，需要先对硬件进行测试，若在硬件测试中发现某个第一存储器出现故障，则可以将出现故障的第一存储器进行标记得到目标修复信息。在本发明实施例中，可在目标处理单元(如CPU)的内部增加或划分一个目标存储区域，专门用于存储目标处理单元的目标修复信息，且在该目标处理单元下电后目标修复信息不会丢失，即目标处理单元下电后，目标修复信息依旧存储在目标处理单元的内部。
所述目标处理单元还用于：当所述目标处理单元从第一模式切换到第二模式后，从所述目标存储区域读取所述目标修复信息，并对所述多个第一存储器进行坏点修复；其中，在所述第一模式下，所述目标处理单元中除所述目标存储区域以外的部分或全部部件处于下电状态，且所述目标存储区域处于上电状态；在所述第二模式下，所述目标处理单元整体处于上 电状态。具体地，目标处理单元的第一模式可以理解为目标处理单元处于空闲下电状态，但目标处理单元内部的目标存储区域未下电，如目标处理单元中的计算单元等部件都处于下电状态，但目标存储区域依旧处于上电状态，或是目标处理单元中的计算单元等部件处于下电状态，但目标存储区域和部分器件(如时钟单元等)依旧处于上电状态，以使得目标存储区域存储的目标修复信息在目标处理单元空闲下电时不丢失；目标处理单元的第二模式可以理解为目标处理单元处于工作上电状态，即目标处理单元中的计算单元等部件都处于上电状态。目标处理单元从第一模式切换到第二模式可以理解为目标处理单元从空闲下电状态切换为工作上电状态。由于每个处理单元从第一模式切换至第二模式后，还需要对第一存储器进行坏点修复，进而处理单元(如CPU)才能恢复正常工作，即每个处理单元在重新上电后，都需要先确定出现故障的第一存储器，然后才能开始正常运算，以避免将运算结果存储至出现故障的第一存储器中导致处理单元出现异常的问题。在本发明实施例中，由于在目标处理单元的内部增加或划分一个目标存储区域，专门用于存储目标处理单元的目标修复信息，且该目标存储区域在目标处理单元处于空闲下电状态时依旧处于上电状态，以使得目标存储区域存储的目标修复信息在目标处理单元处于空闲下电时不丢失。因此，在该目标处理单元重新上电时，目标处理单元可以直接基于内部存储的目标修复信息进行第一存储器的坏点修复，而无需再从目标处理单元外部获取该目标修复信息，减少了目标处理单元进行存储器坏点修复的时间，从而目标处理单元能够更加快速地恢复正常工作，缩短了系统上电恢复时间。
在一种可能的实现方式中，所述片上系统20还包括第二存储器，所述第二存储器为非易失性存储器；所述第二存储器用于：存储所述N个处理单元中每个处理单元的所述目标修复信息。具体地，在片上系统20首次上电使用前，可对每个处理单元都进行硬件测试得到每个处理单元的目标修复信息，然后可将每个处理单元的目标修复信息都存储在第二存储器中，由于该第二存储器为非易失性存储器(即下电后数据不会丢失)，因此在第二存储器处于下电状态时，各个处理单元的目标修复信息也不会丢失。可选的，第二存储器中存储的一个或多个存储器的目标修复信息是不可更改且不可擦除的。进一步地，当处理单元上电后，若处理单元内部的目标存储区域中没有存储目标修复信息，则可以从处理单元外部的第二存储器中获取自身的目标修复信息，进而处理单元可以基于该目标修复信息进行存储器坏点修复，同时还可以将该目标修复信息存储至目标存储区域，以使得在处理单元再次上电时，处理单元可以直接基于内部存储的目标修复信息进行存储器的坏点修复，而无需再从处理单元外部获取该目标修复信息，减少了处理单元进行存储器故障修复的时间，从而处理单元能够更加快速地恢复正常工作，缩短了系统上电恢复时间。
例如，如图3所示，图3为本发明实施例提供的一种具有第二存储器的片上系统的示意图，图中片上系统20的片上存储模块202为本发明实施例提及的第二存储器(可以具有上述图1中的片上存储模块101的部分或全部功能)，可以为一次性可编程存储器(eFuse)。片上系统20的处理器200中可以包括CPU和GPU(图3中以两个处理单元为例)，目标处理单元可以为CPU，也可以为GPU；CPU中可以包括一个或多个第一存储器，GPU中也可以包括一个或多个第一存储器；片上存储模块202中存储了CPU的目标修复信息和GPU的目标修复信息。在CPU上电时，若CPU内部的目标存储区域中没有存储CPU的目标修复信息，则CPU可以从CPU外部的片上存储模块202中获取自身的目标修复信息，并基于该目标修复信息进行存储器坏点修复，同时还可以将该目标修复信息存储至CPU内部的目标存储区域中，以便CPU再次上电时，CPU可以直接基于内部存储的目标修复信息进行存储器的坏点修复，而无需再从CPU外部获取目标修复信息，减少了CPU进行存储器坏点修复的时间，从 而CPU能够更加快速地恢复正常工作，缩短了系统上电恢复时间。
在一种可能的实现方式中，所述片上系统20还包括第三存储器，所述第三存储器为易失性存储器；当所述片上系统从下电状态切换为上电状态时，所述第三存储器用于：从所述第二存储器读取所述目标处理单元的所述目标修复信息并进行存储。具体地，第三存储器可以为静态随机存取存储器(SRAM)，即易失性存储器，当片上系统20从下电状态切换为上电状态时，该第三存储器可用于从第二存储器中读取每个处理单元的目标修复信息并进行存储，以便于在处理单元内部的目标存储区中没有存储目标修复信息时，处理单元能够从外部的第三存储器中获取到自身的目标修复信息。由于处理单元访问非易失性存储器的速度远小于访问易失性存储器的速度，因此将非易失性存储器中的数据先加载至易失性存储器中，然后处理单元再从易失性存储器中读取目标数据，能够降低处理单元从外部读取数据的时间。
例如，如图4所示，图4为本发明实施例提供的一种具有第三存储器的片上系统的示意图，图中片上系统20的内置自修复模块203可以为本发明实施例提及的第三存储器(可以具有上述图1中的内置自修复模块102的部分或全部功能)，片上系统20的处理器200中可以包括CPU和GPU(图3中以两个处理单元为例)；CPU中可以包括一个或多个第一存储器，GPU中也可以包括一个或多个第一存储器；片上存储模块202中存储了CPU的目标修复信息和GPU的目标修复信息。在片上系统20上电时，可先将片上存储模块202中存储的CPU的目标修复信息和GPU的目标修复信息先加载至内置自修复模块203，以降低CPU或GPU从外部读取数据的时间。进一步地，以目标处理单元为CPU为例进行说明，在CPU上电时，若CPU内部的目标存储区域中没有存储CPU的目标修复信息，则CPU可以从CPU外部的内置自修复模块203中获取自身的目标修复信息，并基于该目标修复信息进行存储器坏点修复，同时还可以将该目标修复信息存储至CPU内部的目标存储区域中，以便CPU再次上电时，CPU可以直接基于内部存储的目标修复信息进行存储器的坏点修复，而无需再从CPU外部获取目标修复信息，减少了CPU进行存储器坏点修复的时间，从而CPU能够更加快速地恢复正常工作，缩短了系统上电恢复时间。
在一种可能的实现方式中，所述目标处理单元还用于：若所述目标存储区域中不存在所述目标修复信息，则从所述第三存储器获取所述目标处理单元的所述目标修复信息，并存储至内部的所述目标存储区域中。具体地，若目标处理单元中的目标存储区域中不存在目标修复信息，则目标处理单元需要从外部获取自身的目标修复信息，即可以从目标处理单元外部的第三存储器中获取自身的目标修复信息，进而目标处理单元可以基于该目标修复信息进行存储器坏点修复，同时还可以将该目标修复信息存储至目标存储区域，以使得在目标处理单元再次上电时，目标处理单元可以直接基于内部存储的目标修复信息进行存储器的坏点修复，而无需再从目标处理单元外部获取该目标修复信息，减少了目标处理单元进行存储器坏点修复的时间，从而目标处理单元能够更加快速地恢复正常工作，缩短了系统上电恢复时间。
例如，如图4所示，以目标处理单元为CPU为例进行说明，在CPU上电时，若CPU内部的目标存储区域中没有存储CPU的目标修复信息，则CPU可以从CPU外部的内置自修复模块203中获取自身的目标修复信息，并基于该目标修复信息进行存储器坏点修复，同时还可以将该目标修复信息存储至CPU内部的目标存储区域中，以便CPU再次上电时，CPU可以直接基于内部存储的目标修复信息进行存储器的坏点修复，而无需再从CPU外部获取目标修复信息，减少了CPU进行存储器坏点修复的时间，从而CPU能够更加快速地恢复正常工作，缩短了系统上电恢复时间。
需要说明的是，如图5所示，图5为本发明实施例提供的一种处理单元内部结构示意图， 图中每个处理单元中可以包括一个或多个SRAM，且为每个SRAM都划分或分配了一个目标存储区域用于存储自身的修复信息，SRAM的数量可以根据应用需求进行调整，在此不作具体限定。需要强调的是，上述提及的多个第一存储器可以组成处理单元中的一个SRAM，目标修复信息也可以表示该SRAM的修复信息。由于处理单元中的每个SRAM工作流程相似，因此在本发明实施例中以一个SRAM为例进行详细说明，其他SRAM的工作流程不再重复赘述。
在一种可能的实现方式中，所述目标处理单元中还包括第一寄存器；所述目标处理单元具体用于：将所述第一寄存器作为所述目标存储区域存储所述目标修复信息。具体地，在目标处理单元的内部增加一个第一寄存器作为目标存储区域，专门用于存储目标处理单元的目标修复信息，且该第一寄存器在目标处理单元处于空闲下电状态时依旧处于上电状态，以使得第一寄存器存储的目标修复信息在目标处理单元处于空闲下电时不丢失。进一步地，在该目标处理单元重新上电时，目标处理单元可以直接基于第一寄存器存储的目标修复信息进行第一存储器的坏点修复，而无需再从目标处理单元外部获取该目标修复信息，减少了目标处理单元进行存储器坏点修复的时间，从而目标处理单元能够更加快速地恢复正常工作，缩短了系统上电恢复时间。
在一种可能的实现方式中，所述第一寄存器通过专用电源域供电使得在所述目标处理单元中除所述第一寄存器以外的部分或全部部件处于下电状态时，所述第一寄存器处于上电状态，或者所述第一寄存器通过所述目标处理单元的常开电源域供电使得在所述目标处理单元中除所述第一寄存器以外的部分部件处于下电状态时，所述第一寄存器处于上电状态。具体地，目标处理单元中除第一寄存器以外的部分或全部部件可以由第一电源域来控制上下电，目标处理单元中第一寄存器可由其他电源域来控制上下电。在目标处理单元处于空闲状态时，可以通过断开第一电源域使得目标处理单元下电以节约电能，但第一寄存器一直保持在上电状态以使得存储的目标修复信息不丢失。进一步地，在该目标处理单元重新上电时，目标处理单元可以直接基于第一寄存器存储的目标修复信息进行第一存储器的坏点修复，而无需再从目标处理单元外部获取该目标修复信息，减少了目标处理单元进行存储器坏点修复的时间，从而目标处理单元能够更加快速地恢复正常工作，缩短了系统上电恢复时间。
例如，如图6所示，图6为本发明实施例提供的一种目标处理单元内部结构示意图，图中目标处理单元包括4个第一存储器，分别为C0、C1、C2和C3；C4为备用存储器；第一寄存器为目标存储区域，第一寄存器可以为保留寄存器；目标处理单元中除第一寄存器以外的部分或全部部件可以由第一电源域VDDP来控制上下电，目标处理单元中第一寄存器可由专用电源域VDD_ret和VDDP一起来控制上下电。当目标处理单元处于空闲状态时，VDDP下电，目标处理单元中的计算单元和第一存储器等部件下电，但VDD_ret不下电，以使得第一寄存器存储的目标修复信息不丢失。
需要说明的是，保留寄存器采用双电源结构且VDD_ret保持一直有电，该类寄存器在普通寄存器功能基础上增加了保存(save)和恢复(restore)功能。save端口脉冲信号使得其Q端数据保存至其内部VDD_ret电源域的锁存器中；restore端口脉冲信号使得VDD_ret电源域寄存的数据返回到Q端，且这两个操作都在纳秒时长等级完成。因此，为节省功耗将VDDP和VDDC下电前，先保存目标修复信息至VDD_ret域的锁存器中，再需要目标处理单元工作前先快速完成目标修复信息恢复到Q端，以使得目标处理单元重新上电后能够从保留寄存器中获取到目标修复信息。
又例如，如图7所示，图7为本发明实施例提供的另一种目标处理单元内部结构示意图， 图中目标处理单元包括4个第一存储器，分别为C0、C1、C2和C3；C4为备用存储器；第一寄存器为目标存储区域，第一寄存器可以由VDDC域寄存器组成；目标处理单元中除第一寄存器和多个第一存储器以外的部分或全部部件可以由第一电源域VDDP来控制上下电，第一寄存器和多个第一存储器可以由第二电源域VDDC来控制上下电。当目标处理单元处于空闲状态时，VDDP下电，目标处理单元中的计算单元等部件下电，但VDDC不下电，以使得第一寄存器存储的目标修复信息不丢失。
需要说明的是，第一寄存器可以由VDDC域寄存器和电平转换器组成，电平转换器主要完成信号在VDDP和VDDC两电源之间正常传输功能。该图7的装置可应用于数字逻辑电路下电但第一存储器内数据需保存的场景；相较于上述图6的装置第一寄存器减少了save和restore的操作，进一步减少了目标处理单元的上电恢复时长，但需VDDC保持一直有电。
在一种可能的实现方式中，所述目标处理单元中还包括译码模块，所述目标处理单元还用于：通过所述译码模块从所述第一寄存器获取所述目标修复信息，并基于所述目标修复信息对所述多个第一存储器进行译码配置。具体地，在目标处理单元重新上电时，目标处理单元可以直接基于第一寄存器存储的目标修复信息通过译码模块对目标处理单元中的多个第一存储器进行配置，以避免目标处理单元使用出现故障的第一存储器。由于目标处理单元重新上电后无需再从目标处理单元外部获取目标修复信息，因此减少了目标处理单元进行存储器坏点修复的时间，从而目标处理单元能够更加快速地恢复正常工作，缩短了系统上电恢复时间。
例如，如图8所示，图8为本发明实施例提供的一种目标处理单元上电恢复示意图，图中假设目标处理单元包括4个第一存储器，分别为C0、C1、C2和C3，其中C1为出现故障的存储器；C4为备用存储器；第一寄存器为目标存储区域。当目标处理单元重新上电后，译码模块从第一寄存器中获取目标修复信息并进行译码，得到C1为出现故障的存储器。进一步地，可向目标处理单元中的第一存储器发送0111，然后通过选择器将C1进行隔离，然后可以启用备用存储器C4，以避免目标处理单元使用出现故障的第一存储器。
又例如，如图9所示，图9为本发明实施例提供的另一种目标处理单元上电恢复示意图，图中假设目标处理单元包括4个第一存储器，分别为C0、C1、C2和C3，其中C1为出现故障的存储器；C4为备用存储器；第一寄存器为目标存储区域。当目标处理单元重新上电后，译码模块从第一寄存器中获取目标修复信息并进行译码，得到C1为出现故障的存储器。进一步地，可向目标处理单元中的第一存储器发送0111，然后通过选择器将C1进行隔离，然后可以启用备用存储器C4，以避免目标处理单元使用出现故障的第一存储器。
在一种可能的实现方式中，所述目标处理单元具体用于：将所述多个第一存储器作为所述目标存储区域存储所述目标修复信息，所述多个第一存储器通过所述目标处理单元的常开电源域供电使得在所述目标处理单元中除所述多个第一存储器以外的部分部件处于下电状态时，所述多个第一存储器处于上电状态。具体地，在目标处理单元内部的多个第一存储器中划分一个目标存储区域，专门用于存储目标处理单元的目标修复信息，且该存储区域在目标处理单元处于空闲下电状态时依旧处于上电状态，以使得存储区域存储的目标修复信息在目标处理单元处于空闲下电时不丢失。因此，在该目标处理单元重新上电时，目标处理单元可以直接基于多个第一存储器存储的目标修复信息进行第一存储器的坏点修复，而无需再从目标处理单元外部获取该目标修复信息，减少了目标处理单元进行存储器坏点修复的时间，从而目标处理单元能够更加快速地恢复正常工作，缩短了系统上电恢复时间。
例如，如图10所示，图10为本发明实施例提供的又一种目标处理单元内部结构示意图， 图中目标处理单元包括4个第一存储器，分别为C0、C1、C2和C3；C4为备用存储器；C0’、C1’、C2’和C3’为被划分的目标存储区域；目标处理单元中除第一存储器以外的部分或全部部件可以由VDDP来控制上下电，目标处理单元中第一存储器可由VDDC来控制上下电。当目标处理单元处于空闲状态时，VDDP下电，目标处理单元中的计算单元等部件下电，但VDDC不下电，以使得第一存储器中存储的目标修复信息不丢失。
需要说明的是，SRAM是一种面积利用率极高的器件，上述图6的装置和上述图7的装置都有可能导致SRAM的无效面积增加，进而导致SoC资源的严重浪费。因此，上述图10的装置直接利用多个第一存储器来存储目标修复信息，对面积影响较小。
在一种可能的实现方式中，所述目标处理单元中包括第二寄存器，所述目标处理单元还用于：当所述目标处理单元从所述第一模式切换到所述第二模式后，通过所述第二寄存器从所述多个第一存储器中获取所述目标修复信息并进行存储。具体地，为便于后续对目标修复信息进行译码，可以在目标处理单元中增加一个第二寄存器，且目标处理单元下电该第二寄存器也处于下电状态。当目标处理单元再次上电时，第二寄存器可以从第一存储器获取目标修复信息并进行存储。例如，如图10所示，当目标处理单元再次上电后，第二寄存器先从C0’、C1’、C2’和C3’中获取目标修复信息并保存，以便后续译码模块对目标修复信息进行译码。
在一种可能的实现方式中，所述目标处理单元中还包括译码模块，所述目标处理单元还用于：通过所述译码模块从所述第二寄存器获取所述目标修复信息，并基于所述目标修复信息对所述多个第一存储器进行译码配置。具体地，在目标处理单元重新上电时，目标处理单元可以基于第二寄存器中的目标修复信息通过译码模块对目标处理单元中的多个第一存储器进行配置，以避免目标处理单元使用出现故障的第一存储器。由于目标处理单元重新上电后无需再从目标处理单元外部获取目标修复信息，因此减少了目标处理单元进行存储器坏点修复的时间，从而目标处理单元能够更加快速地恢复正常工作，缩短了系统上电恢复时间。
例如，如图11所示，图11为本发明实施例提供的又一种目标处理单元上电恢复示意图，图中假设目标处理单元包括4个第一存储器，分别为C0、C1、C2和C3，其中C1为出现故障的存储器；C4为备用存储器；C0’、C1’、C2’和C3’为被划分的目标存储区域。当目标处理单元重新上电后，第二寄存器先从C0’、C1’、C2’和C3’中读取目标修复信息并存储，然后译码模块从第二寄存器中获取目标修复信息并进行译码，得到C1为出现故障的存储器。进一步地，可向目标处理单元中的第一存储器发送0111，然后通过选择器将C1进行隔离，然后可以启用备用存储器C4，以避免目标处理单元使用出现故障的第一存储器。
在一种可能的实现方式中，所述目标处理单元还包括备用存储器；所述目标处理单元具体用于：基于所述目标修复信息，通过所述译码模块确定所述出现故障的第一存储器；对所述出现故障的第一存储器进行坏点隔离，并启用所述备用存储器。具体地，在目标处理单元重新上电时，目标处理单元可以直接基于目标存储区域存储的目标修复信息通过译码模块确定多个第一存储器中出现故障的第一存储器，并将出现故障的第一存储器进行坏点隔离，然后启用备用存储器，以避免目标处理单元使用出现故障的第一存储器，导致系统异常。
例如，如图12所示，图12为本发明实施例提供的一种系统上电恢复流程示意图，图中当检测到模块(即处理单元)需要工作时，首先为模块上电，然后判断是否为开机场景，若否，则处理单元直接从目标存储区域中获取本地的目标修复信息输入SRAM内，在模块完成配置信息恢复后开始正常工作；若是，则可从片上存储模块获取自身的目标修复信息，并将目标修复信息串行输入到模块的各SRAM内，在模块完成配置后开始正常工作，同时需要配 置信息保存，将目标修复信息存储在处理单元内部。
通过本发明实施例，由于在目标处理单元的内部增加或划分一个目标存储区域，专门用于存储目标处理单元的目标修复信息，且该目标存储区域在目标处理单元处于空闲下电状态时依旧处于上电状态，以使得目标存储区域存储的目标修复信息在目标处理单元处于空闲下电时不丢失。因此，在该目标处理单元重新上电时，目标处理单元可以直接基于内部存储的目标修复信息进行第一存储器的坏点修复，而无需再从目标处理单元外部获取该目标修复信息，减少了目标处理单元进行存储器坏点修复的时间，从而目标处理单元能够更加快速地恢复正常工作，缩短了系统上电恢复时间。
上述详细阐述了本发明实施例的片上系统，下面提供了本发明实施例的相关方法。
请参见图13，图13是本发明实施例提供的一种系统上电恢复方法的流程图，该方法适用于上述图2中的一种片上系统以及包含所述片上系统的设备。该方法可以包括以下步骤S301-步骤S302。所述片上系统包括N个处理单元，所述N个处理单元中的目标处理单元包括多个第一存储器，所述多个第一存储器均为易失性存储器，所述目标处理单元为所述N个处理单元中的任意一个处理单元，N、M为大于0的整数。详细描述如下：
步骤S301：通过所述目标处理单元在内部的目标存储区域中存储目标修复信息，所述目标修复信息为所述多个第一存储器中出现故障的第一存储器的信息。
步骤S302：当所述目标处理单元从第一模式切换到第二模式后，通过所述目标处理单元从所述目标存储区域读取所述目标修复信息，并对所述多个第一存储器进行坏点修复。
具体地，其中，在所述第一模式下，所述目标处理单元中除所述目标存储区域以外的部分或全部部件处于下电状态，且所述目标存储区域处于上电状态；在所述第二模式下，所述目标处理单元整体处于上电状态。
在一种可能的实现方式中，所述片上系统还包括第二存储器，所述第二存储器为非易失性存储器；所述方法还包括：通过所述第二存储器存储所述N个处理单元中每个处理单元的所述目标修复信息。
在一种可能的实现方式中，所述片上系统还包括第三存储器，所述第三存储器为易失性存储器；当所述片上系统从下电状态切换为上电状态时，所述方法还包括：通过所述第三存储器从所述第二存储器读取所述目标处理单元的所述目标修复信息并进行存储。
在一种可能的实现方式中，所述方法还包括：若所述目标存储区域中不存在所述目标修复信息，则通过所述目标处理单元从所述第三存储器获取所述目标处理单元的所述目标修复信息，并存储至内部的所述目标存储区域中。
在一种可能的实现方式中，所述目标处理单元中还包括第一寄存器；所述通过所述目标处理单元在内部的目标存储区域中存储目标修复信息，包括：将所述第一寄存器作为所述目标存储区域存储所述目标修复信息。
在一种可能的实现方式中，所述第一寄存器通过专用电源域供电使得在所述目标处理单元中除所述第一寄存器以外的部分或全部部件处于下电状态时，所述第一寄存器处于上电状态，或者所述第一寄存器通过所述目标处理单元的常开电源域供电使得在所述目标处理单元中除所述第一寄存器以外的部分部件处于下电状态时，所述第一寄存器处于上电状态。
在一种可能的实现方式中，所述目标处理单元中还包括译码模块，所述方法还包括：通过所述目标处理单元中的所述译码模块从所述第一寄存器获取所述目标修复信息，并基于所述目标修复信息对所述多个第一存储器进行译码配置。
在一种可能的实现方式中，所述通过所述目标处理单元在内部的目标存储区域中存储目标修复信息，包括：将所述多个第一存储器作为所述目标存储区域存储所述目标修复信息，所述多个第一存储器通过所述目标处理单元的常开电源域供电使得在所述目标处理单元中除所述多个第一存储器以外的部分部件处于下电状态时，所述多个第一存储器处于上电状态。
在一种可能的实现方式中，所述目标处理单元中包括第二寄存器，所述方法还包括：当所述目标处理单元从所述第一模式切换到所述第二模式后，通过所述第二寄存器从所述多个第一存储器中获取所述目标修复信息并进行存储。
在一种可能的实现方式中，所述目标处理单元中还包括译码模块，所述方法还包括；通过所述目标处理单元中的所述译码模块从所述第二寄存器获取所述目标修复信息，并基于所述目标修复信息对所述多个第一存储器进行译码配置。
在一种可能的实现方式中，所述目标处理单元还包括备用存储器；所述对所述多个第一存储器进行坏点修复，包括：基于所述目标修复信息，通过所述译码模块确定所述出现故障的第一存储器；对所述出现故障的第一存储器进行坏点隔离，并启用所述备用存储器。
通过本发明实施例提供的方法，可以缩短处理单元上电后的恢复时间。
本申请提供了一种计算机存储介质，其特征在于，所述计算机存储介质存储有计算机程序，该计算机程序被处理器执行时实现上述任意一种系统上电恢复方法。
本申请实施例提供一种电子设备，该电子设备中包括处理器，处理器被配置为支持该电子设备实现上述任意一种系统上电恢复方法中相应的功能。该电子设备还可以包括存储器，存储器用于与处理器耦合，其保存该电子设备必要的程序指令和数据。该电子设备还可以包括通信接口，用于该电子设备与其他设备或通信网络通信。
本申请提供了一种芯片系统，该芯片系统包括处理器，用于支持电子设备实现上述所涉及的功能，例如，生成或处理上述一种系统上电恢复方法中所涉及的信息。在一种可能的设计中，所述芯片系统还包括存储器，所述存储器，用于保存电子设备必要的程序指令和数据。该芯片系统，可以由芯片构成，也可以包含芯片和其他分立器件。
本申请提供一种计算机程序，其特征在于，所述计算机程序包括指令，当所述计算机程序被计算机执行时，使得所述计算机执行上述一种系统上电恢复方法。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
需要说明的是，对于前述的各方法实施例，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本申请并不受所描述的动作顺序的限制，因为依据本申请，某些步骤可能可以采用其他顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例均属于优选实施例，所涉及的动作和模块并不一定是本申请所必须的。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置，可通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如上述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性或其它的形式。
上述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
上述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以为个人计算机、服务器或者网络设备等，具体可以是计算机设备中的处理器)执行本申请各个实施例上述方法的全部或部分步骤。其中，而前述的存储介质可包括：U盘、移动硬盘、磁碟、光盘、只读存储器(Read-Only Memory，缩写：ROM)或者随机存取存储器(Random Access Memory，缩写：RAM)等各种可以存储程序代码的介质。
以上所述，以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (24)

  1. 一种片上系统，其特征在于，所述片上系统包括N个处理单元，所述N个处理单元中的目标处理单元包括多个第一存储器，所述多个第一存储器均为易失性存储器，所述目标处理单元为所述N个处理单元中的任意一个处理单元，N为大于0的整数，其中，
    所述目标处理单元用于：
    在内部的目标存储区域中存储目标修复信息，所述目标修复信息为所述多个第一存储器中出现故障的第一存储器的信息；
    当所述目标处理单元从第一模式切换到第二模式后，从所述目标存储区域读取所述目标修复信息，并对所述多个第一存储器进行坏点修复；其中，在所述第一模式下，所述目标处理单元中除所述目标存储区域以外的部分或全部部件处于下电状态，且所述目标存储区域处于上电状态；在所述第二模式下，所述目标处理单元整体处于上电状态。
  2. 如权利要求1所述系统，其特征在于，所述片上系统还包括第二存储器，所述第二存储器为非易失性存储器；所述第二存储器用于：
    存储所述N个处理单元中每个处理单元的所述目标修复信息。
  3. 如权利要求2所述的系统，其特征在于，所述片上系统还包括第三存储器，所述第三存储器为易失性存储器；当所述片上系统从下电状态切换为上电状态时，所述第三存储器用于：
    从所述第二存储器读取所述目标处理单元的所述目标修复信息并进行存储。
  4. 如权利要求3所述的系统，其特征在于，所述目标处理单元还用于：
    若所述目标存储区域中不存在所述目标修复信息，则从所述第三存储器获取所述目标处理单元的所述目标修复信息，并存储至内部的所述目标存储区域中。
  5. 如权利要求1-4任意一项所述系统，其特征在于，所述目标处理单元中还包括第一寄存器；所述目标处理单元具体用于：
    将所述第一寄存器作为所述目标存储区域存储所述目标修复信息。
  6. 如权利要求5所述系统，其特征在于，所述第一寄存器通过专用电源域供电使得在所述目标处理单元中除所述第一寄存器以外的部分或全部部件处于下电状态时，所述第一寄存器处于上电状态，或者所述第一寄存器通过所述目标处理单元的常开电源域供电使得在所述目标处理单元中除所述第一寄存器以外的部分部件处于下电状态时，所述第一寄存器处于上电状态。
  7. 如权利要求5或6所述的系统，其特征在于，所述目标处理单元中还包括译码模块，所述目标处理单元还用于：
    通过所述译码模块从所述第一寄存器获取所述目标修复信息，并基于所述目标修复信息对所述多个第一存储器进行译码配置。
  8. 如权利要求1-4任意一项所述系统，其特征在于，所述目标处理单元具体用于：
    将所述多个第一存储器作为所述目标存储区域存储所述目标修复信息，所述多个第一存储器通过所述目标处理单元的常开电源域供电使得在所述目标处理单元中除所述多个第一存储器以外的部分部件处于下电状态时，所述多个第一存储器处于上电状态。
  9. 如权利要求8所述的系统，其特征在于，所述目标处理单元中包括第二寄存器，所述目标处理单元还用于：
    当所述目标处理单元从所述第一模式切换到所述第二模式后，通过所述第二寄存器从所述多个第一存储器中获取所述目标修复信息并进行存储。
  10. 如权利要求9所述的系统，其特征在于，所述目标处理单元中还包括译码模块，所述目标处理单元还用于：
    通过所述译码模块从所述第二寄存器获取所述目标修复信息，并基于所述目标修复信息对所述多个第一存储器进行译码配置。
  11. 如权利要求7或10所述的系统，其特征在于，所述目标处理单元还包括备用存储器；所述目标处理单元具体用于：
    基于所述目标修复信息，通过所述译码模块确定所述出现故障的第一存储器；
    对所述出现故障的第一存储器进行坏点隔离，并启用所述备用存储器。
  12. 一种系统上电恢复方法，其特征在于，应用于片上系统，所述片上系统包括N个处理单元，所述N个处理单元中的目标处理单元包括多个第一存储器，所述多个第一存储器均为易失性存储器，所述目标处理单元为所述N个处理单元中的任意一个处理单元，N、M为大于0的整数，所述方法包括：
    通过所述目标处理单元在内部的目标存储区域中存储目标修复信息，所述目标修复信息为所述多个第一存储器中出现故障的第一存储器的信息；
    当所述目标处理单元从第一模式切换到第二模式后，通过所述目标处理单元从所述目标存储区域读取所述目标修复信息，并对所述多个第一存储器进行坏点修复；其中，在所述第一模式下，所述目标处理单元中除所述目标存储区域以外的部分或全部部件处于下电状态，且所述目标存储区域处于上电状态；在所述第二模式下，所述目标处理单元整体处于上电状态。
  13. 如权利要求12所述方法，其特征在于，所述片上系统还包括第二存储器，所述第二存储器为非易失性存储器；所述方法还包括：
    通过所述第二存储器存储所述N个处理单元中每个处理单元的所述目标修复信息。
  14. 如权利要求13所述的方法，其特征在于，所述片上系统还包括第三存储器，所述第三存储器为易失性存储器；当所述片上系统从下电状态切换为上电状态时，所述方法还包括：
    通过所述第三存储器从所述第二存储器读取所述目标处理单元的所述目标修复信息并进行存储。
  15. 如权利要求14所述的方法，其特征在于，所述方法还包括：
    若所述目标存储区域中不存在所述目标修复信息，则通过所述目标处理单元从所述第三存储器获取所述目标处理单元的所述目标修复信息，并存储至内部的所述目标存储区域中。
  16. 如权利要求12-15任意一项所述方法，其特征在于，所述目标处理单元中还包括第一寄存器；所述通过所述目标处理单元在内部的目标存储区域中存储目标修复信息，包括：
    将所述第一寄存器作为所述目标存储区域存储所述目标修复信息。
  17. 如权利要求16所述方法，其特征在于，所述第一寄存器通过专用电源域供电使得在所述目标处理单元中除所述第一寄存器以外的部分或全部部件处于下电状态时，所述第一寄存器处于上电状态，或者所述第一寄存器通过所述目标处理单元的常开电源域供电使得在所述目标处理单元中除所述第一寄存器以外的部分部件处于下电状态时，所述第一寄存器处于上电状态。
  18. 如权利要求16或17所述的方法，其特征在于，所述目标处理单元中还包括译码模块，所述方法还包括：
    通过所述目标处理单元中的所述译码模块从所述第一寄存器获取所述目标修复信息，并基于所述目标修复信息对所述多个第一存储器进行译码配置。
  19. 如权利要求12-15任意一项所述方法，其特征在于，所述通过所述目标处理单元在内部的目标存储区域中存储目标修复信息，包括：
    将所述多个第一存储器作为所述目标存储区域存储所述目标修复信息，所述多个第一存储器通过所述目标处理单元的常开电源域供电使得在所述目标处理单元中除所述多个第一存储器以外的部分部件处于下电状态时，所述多个第一存储器处于上电状态。
  20. 如权利要求19所述的方法，其特征在于，所述目标处理单元中包括第二寄存器，所述方法还包括：
    当所述目标处理单元从所述第一模式切换到所述第二模式后，通过所述第二寄存器从所述多个第一存储器中获取所述目标修复信息并进行存储。
  21. 如权利要求20所述的方法，其特征在于，所述目标处理单元中还包括译码模块，所述方法还包括；
    通过所述目标处理单元中的所述译码模块从所述第二寄存器获取所述目标修复信息，并基于所述目标修复信息对所述多个第一存储器进行译码配置。
  22. 如权利要求20或21所述的方法，其特征在于，所述目标处理单元还包括备用存储器；所述对所述多个第一存储器进行坏点修复，包括：
    基于所述目标修复信息，通过所述译码模块确定所述出现故障的第一存储器；
    对所述出现故障的第一存储器进行坏点隔离，并启用所述备用存储器。
  23. 一种计算机存储介质，其特征在于，所述计算机存储介质存储有计算机程序，该计算机程序被处理器执行时实现上述权利要求12-22中任意一项所述的方法。
  24. 一种计算机程序，其特征在于，所述计算机程序包括指令，当所述计算机程序被计算机或处理器执行时，使得所述计算机或处理器执行如权利要求12-22中任意一项所述的方法。
PCT/CN2023/093266 2022-05-13 2023-05-10 一种片上系统及相关系统上电恢复方法 WO2023217186A1 (zh)

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WO2021168622A1 (zh) * 2020-02-24 2021-09-02 华为技术有限公司 存储器、芯片及存储器的修复信息的保存方法
CN113608930A (zh) * 2021-08-24 2021-11-05 厦门紫光展锐科技有限公司 系统芯片和电子设备
KR20220040202A (ko) * 2020-09-23 2022-03-30 삼성전기주식회사 플래쉬리스 ois 드라이버 회로 및 ois 장치

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US20050132255A1 (en) * 2003-11-26 2005-06-16 Tran Tam M. Low-power SRAM E-fuse repair methodology
WO2021168622A1 (zh) * 2020-02-24 2021-09-02 华为技术有限公司 存储器、芯片及存储器的修复信息的保存方法
CN112083791A (zh) * 2020-09-15 2020-12-15 南方电网数字电网研究院有限公司 芯片功耗优化方法、装置、计算机设备和存储介质
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