WO2023127023A1 - Dispositif semi-conducteur au carbure de silicium, dispositif de conversion d'énergie électrique, et procédé de production de dispositif semi-conducteur au carbure de silicium - Google Patents

Dispositif semi-conducteur au carbure de silicium, dispositif de conversion d'énergie électrique, et procédé de production de dispositif semi-conducteur au carbure de silicium Download PDF

Info

Publication number
WO2023127023A1
WO2023127023A1 PCT/JP2021/048577 JP2021048577W WO2023127023A1 WO 2023127023 A1 WO2023127023 A1 WO 2023127023A1 JP 2021048577 W JP2021048577 W JP 2021048577W WO 2023127023 A1 WO2023127023 A1 WO 2023127023A1
Authority
WO
WIPO (PCT)
Prior art keywords
schottky
silicon carbide
trench
semiconductor device
carbide semiconductor
Prior art date
Application number
PCT/JP2021/048577
Other languages
English (en)
Japanese (ja)
Inventor
基 吉田
貴亮 富永
裕 福井
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP2022558572A priority Critical patent/JP7275407B1/ja
Priority to PCT/JP2021/048577 priority patent/WO2023127023A1/fr
Publication of WO2023127023A1 publication Critical patent/WO2023127023A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes

Definitions

  • the present disclosure relates to a trench gate silicon carbide semiconductor device, a method for manufacturing the same, and a power converter using the trench gate silicon carbide semiconductor device.
  • MOSFET Metal-Oxide-Semiconductor Field-Effect-Transistor
  • SBD Schottky Barrier Diode
  • the cost can be reduced compared to attaching a freewheeling diode to the switching element externally.
  • SiC silicon carbide
  • a trench-gate MOSFET having a structure in which a gate electrode is embedded in a trench formed in a semiconductor layer has a structure in which a gate electrode is formed on the surface of the semiconductor layer to the extent that a channel can be formed on the side wall of the trench.
  • the channel width density can be improved compared to the planar MOSFET with the MOSFET, thereby reducing the on-resistance. Therefore, a semiconductor device having a structure in which an SBD is built in a trench gate type MOSFET has been developed (for example, Patent Document 1 below).
  • the Schottky trench in which the Schottky electrode of the SBD is formed is filled with Al forming part of the source electrode together with the Schottky electrode. ing.
  • the SBD-embedded trench-type MOSFET having such a configuration is operated at a high temperature of 150° C. or higher (especially 175° C. or higher), the Al in the Schottky trench is deformed, causing a cavity to be formed in the Schottky trench. .
  • the thermal conductivity becomes non-uniform near the cavity, and heat is generated locally called a “hot spot”, which leads to further deformation of Al and the formation of the Schottky electrode. Delamination may occur.
  • the present disclosure has been made to solve the problems described above, and an object thereof is to provide a silicon carbide semiconductor device capable of preventing formation of voids in Schottky trenches due to high-temperature operation.
  • a silicon carbide semiconductor device includes a first conductivity type drift layer, a second conductivity type body region formed on the drift layer, and a first conductivity type body region formed in a surface layer portion of the body region.
  • a gate trench formed in the semiconductor layer and penetrating the source region and the body region to reach the drift layer; and a gate trench formed on an inner surface of the gate trench.
  • a layer ;
  • FIG. 1 is a cross-sectional view of a silicon carbide semiconductor device according to a first embodiment
  • FIG. 1 is a plan view of a silicon carbide semiconductor device according to a first embodiment
  • FIG. FIG. 4 is a cross-sectional view showing a manufacturing process of the silicon carbide semiconductor device according to the first embodiment
  • FIG. 4 is a cross-sectional view showing a manufacturing process of the silicon carbide semiconductor device according to the first embodiment
  • FIG. 4 is a cross-sectional view showing a manufacturing process of the silicon carbide semiconductor device according to the first embodiment
  • FIG. 4 is a cross-sectional view showing a manufacturing process of the silicon carbide semiconductor device according to the first embodiment
  • FIG. 4 is a cross-sectional view showing a manufacturing process of the silicon carbide semiconductor device according to the first embodiment
  • FIG. 4 is a cross-sectional view showing a manufacturing process of the silicon carbide semiconductor device according to the first embodiment
  • FIG. 4 is a cross-sectional view showing a manufacturing process of the silicon carbide semiconductor device according to the first embodiment;
  • FIG. 4 is a cross-sectional view showing a manufacturing process of the silicon carbide semiconductor device according to the first embodiment;
  • FIG. 4 is a cross-sectional view showing a manufacturing process of the silicon carbide semiconductor device according to the first embodiment;
  • FIG. 4 is a cross-sectional view showing a manufacturing process of the silicon carbide semiconductor device according to the first embodiment;
  • FIG. 4 is a cross-sectional view showing a manufacturing process of the silicon carbide semiconductor device according to the first embodiment;
  • 1 is a cross-sectional view of a silicon carbide semiconductor device according to a first embodiment;
  • FIG. 9 is a cross-sectional view of a silicon carbide semiconductor device according to a second embodiment
  • FIG. 11 is a cross-sectional view showing a manufacturing process of a silicon carbide semiconductor device according to a second embodiment
  • FIG. 10 is a diagram of a power converter according to Embodiment 3;
  • the first conductivity type is n-type and the second conductivity type is p-type.
  • FIG. 1 is a cross-sectional view of a trench type silicon carbide MOSFET with built-in Schottky barrier diode (also called “SiC trench MOSFET with built-in SBD”), which is a silicon carbide semiconductor device according to a first embodiment.
  • FIG. 1 shows a cross-section of a portion of an active region formed with a MOSFET and an SBD in a chip of an SBD-embedded SiC trench MOSFET.
  • 2 is a plan view of the SBD-embedded SiC trench MOSFET shown in FIG.
  • FIG. 2 shows a planar structure at a depth slightly shallower than the bottom of the gate trench in which the gate electrode of the MOSFET is buried and the Schottky trench in which the Schottky electrode 71 of the SBD is buried.
  • the silicon carbide semiconductor device according to the first embodiment is formed using a semiconductor substrate 10 made of n-type low-resistance silicon carbide.
  • the main surface on the upper side of the semiconductor substrate 10 in FIG. 1 is called “first main surface 11", and the main surface on the lower side is called “second main surface 12".
  • a drift layer 20 made of n-type silicon carbide is formed on the first main surface 11 of the semiconductor substrate 10 .
  • Body region 30 made of p-type silicon carbide is formed on drift layer 20 .
  • a source region 40 made of n-type silicon carbide and a contact region 35 made of p-type silicon carbide having an impurity peak concentration higher than that of the body region 30 are selected in the surface layer portion of the body region 30 . is formed
  • gate trenches 91 and Schottky trenches 92 are formed alternately and in parallel. A lower end of gate trench 91 and a lower end of Schottky trench 92 are located in drift layer 20 .
  • Source region 40 is arranged in the surface layer portion of body region 30 adjacent to gate trench 91 .
  • Contact region 35 is arranged in the surface layer portion of body region 30 between gate trench 91 and Schottky trench 92 .
  • gate trench 91 is formed in a region where source region 40 is formed, penetrates source region 40 and body region 30 , and reaches drift layer 20 .
  • Schottky trench 92 is formed in a region where source region 40 is not formed, penetrates body region 30 and reaches drift layer 20 .
  • a gate insulating film 50 made of silicon oxide is formed on the inner surface (that is, side surfaces and bottom surface) of the gate trench 91 .
  • a gate electrode 60 made of low resistance polycrystalline silicon having a high impurity concentration is formed on gate insulating film 50 in gate trench 91 .
  • a Schottky electrode 71 that is Schottky-connected to the drift layer 20 is formed on the inner surface of the Schottky trench 92 .
  • the Schottky electrode 71 is made of a metal containing Ti as a main component.
  • the thickness of the Schottky electrode 71 is 50 nm or more and 500 nm or less, and is preferably uniform.
  • the Schottky electrode 71 only needs to be made of a metal containing Ti as a main component at least at a portion in contact with the semiconductor layer 1 (that is, the inner surface of the Schottky trench 92). Therefore, the Schottky electrode 71 may have a laminated structure in which a layer made of another metal is laminated on a metal layer containing Ti as a main component, for example.
  • a p-type first protection region 31 is formed in the drift layer 20 at the bottom of the gate trench 91 .
  • a p-type second protection region 32 is formed in the drift layer 20 at the bottom of the Schottky trench 92 .
  • the first protection region 31 and the second protection region 32 are assumed to have the same depth and the same impurity concentration.
  • the gate trench 91 and the Schottky trench 92 are formed continuously in their longitudinal direction (the depth direction in FIG. 1).
  • p-type first connection regions 33 are formed at regular intervals in the longitudinal direction of the gate trench 91 in the portion of the drift layer 20 along the gate trench 91 .
  • p-type second connection regions 34 are formed at regular intervals in the longitudinal direction of the Schottky trench 92 in the portion of the drift layer 20 along the Schottky trench 92 .
  • the first connection region 33 electrically connects between the first protection region 31 and the body region 30
  • the second connection region 34 electrically connects between the second protection region 32 and the body region 30 . do. Since FIG. 1 is a cross section of a portion where the first connection region 33 and the second connection region 34 are not formed, the first connection region 33 and the second connection region 34 are not shown in FIG.
  • An interlayer insulating film 55 made of silicon oxide is formed on the semiconductor layer 1 so as to cover the gate electrode 60 .
  • Interlayer insulating film 55 is formed with openings exposing contact region 35 , source region 40 and Schottky trench 92 .
  • An ohmic electrode 70 ohmic-connected to the contact region 35 and the source region 40 is formed on the contact region 35 and the source region 40 exposed from the interlayer insulating film 55 .
  • Schottky electrode 71 extends not only on the inner surface of Schottky electrode 71 but also on interlayer insulating film 55 and ohmic electrode 70 , and source electrode 80 extends on ohmic electrode 70 . formed. Therefore, source electrode 80 is electrically connected to source region 40 and contact region 35 via ohmic electrode 70 and Schottky electrode 71 .
  • a drain electrode 82 is formed on the second main surface 12 of the semiconductor substrate 10 via a back surface ohmic electrode (not shown). Drain electrode 82 is electrically connected to semiconductor substrate 10 .
  • the source electrode 80 is composed of a metal having a higher recrystallization temperature than Al.
  • Metals having a higher recrystallization temperature than Al include metals containing Cu, Ni, Ag, or Pd as a main component.
  • a part of the source electrode 80 is laminated on the Schottky electrode 71 in the Schottky trench 92 and buried in the Schottky trench 92 together with the Schottky electrode 71 .
  • a portion of the source electrode 80 formed on the Schottky electrode 71 in the Schottky trench 92, that is, a layer made of a metal having a higher recrystallization temperature than Al is referred to as a "high recrystallization temperature metal layer 81".
  • the recrystallization temperature In general, when a metal such as Al is heated to a certain temperature, it suddenly softens and the deformed crystal recrystallizes. Further, if the material is heated further, the crystal grains grow and the grains become coarse. Generally, the larger the particle size, the lower the strength of the material, and the more likely it is to be deformed or cracked by external stress, resulting in lower reliability as an electrode material. The temperature during this recrystallization is defined as the recrystallization temperature.
  • the upper temperature limit of the Al material is said to be 150°C. exceeds 150.degree.
  • the Schottky electrode 71 in the Schottky trench 92 is filled with the high recrystallization temperature metal layer 81 having a higher recrystallization temperature than Al, the operating temperature is 150.degree. is suppressed, the deformation of Al is suppressed, and the formation of voids in the Schottky trench 92 is suppressed. Therefore, occurrence of defects such as peeling of Schottky electrode 71 is suppressed, and a highly reliable silicon carbide semiconductor device can be obtained.
  • FIG. 3 to 12 show cross-sections of the silicon carbide semiconductor device in the middle of manufacturing according to the first embodiment, and correspond to the cross-sections shown in FIG.
  • a semiconductor substrate 10 made of n-type low-resistance silicon carbide having a 4H polytype and a (0001) plane in which the first main surface 11 is inclined by 1° or more in the ⁇ 11-20> direction is prepared.
  • n-type silicon carbide having an impurity concentration of 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 17 cm ⁇ 3 or less is formed on the semiconductor substrate 10 by a chemical vapor deposition (CVD) method. is epitaxially grown to a thickness of 5 ⁇ m or more and 50 ⁇ m or less.
  • the upper surface of the grown drift layer 20 is also the (0001) plane inclined by 1° or more toward the ⁇ 11-20> direction, like the first main surface 11 .
  • ions of Al which is a p-type impurity
  • the depth of Al ion implantation is set to about 0.5 ⁇ m or more and 3 ⁇ m or less within a range not exceeding the thickness of the drift layer 20 .
  • the impurity concentration of ion-implanted Al is in the range of 1 ⁇ 10 17 cm ⁇ 3 or more and 1 ⁇ 10 19 cm ⁇ 3 or less, which is higher than the impurity concentration of the drift layer 20 .
  • the region into which Al is ion-implanted in this step becomes the body region 30 .
  • an implantation mask such as a photoresist having an opening in the region where the source region 40 is to be formed is formed, and N (nitrogen), which is an n-type impurity, is ion-implanted.
  • N nitrogen
  • the impurity concentration of the implanted N is set to exceed the p-type impurity concentration of the body region 30 within a range of 1 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 21 cm ⁇ 3 or less.
  • the region exhibiting the n-type becomes the source region 40 .
  • the implantation mask is removed.
  • Al is added to the formation region of the contact region 35 so that the impurity concentration is higher than that of the body region 30 in the range of 1 ⁇ 10 19 cm ⁇ 3 or more and 1 ⁇ 10 21 cm ⁇ 3 or less. Ion implantation. The region into which Al is implanted in this step becomes the contact region 35 . Through the steps up to this point, the structure shown in FIG. 3 is obtained.
  • a resist mask is formed to partially open the region where the source region 40 is formed, and a gate trench 91 penetrating the source region 40 and the body region 30 to reach the drift layer 20 is formed by dry etching.
  • a resist mask is formed to partially open the region where the source region 40 is not formed, and a Schottky trench 92 that penetrates the body region 30 and reaches the drift layer 20 is formed by dry etching.
  • the gate trenches 91 and the Schottky trenches 92 are formed so that the longitudinal direction is the ⁇ 11-20> direction.
  • the trench sidewalls of gate trench 91 and Schottky trench 92 are formed perpendicular to first main surface 11 of semiconductor substrate 10 (or the surface of semiconductor layer 10), the trench sidewalls of gate trench 91 and Schottky trench 92 are perpendicular to each other.
  • the longitudinal sidewalls are the (1-100) plane and the (-1100) plane.
  • the longitudinal sidewalls of gate trench 91 and Schottky trench 92 form an angle in the range of 80° or more and 90° or less with respect to first main surface 11 of semiconductor substrate 10 .
  • the sidewalls of the gate trench 91 and the Schottky trench 92 in the longitudinal direction are inclined at an angle of 10° or less from the (1-100) plane or the (-1100) plane. Further, when gate trench 91 and Schottky trench 92 are continuous in the longitudinal direction, gate trench 91 and Schottky trench 92 extend along the ⁇ 11-20> direction.
  • gate trench 91 and the formation of the Schottky trench 92 may be performed simultaneously in the same dry etching process. In that case, gate trench 91 and Schottky trench 92 are formed to have the same depth.
  • p-type impurity ions are implanted into the drift layer 20 at the bottom of the gate trench 91 and the Schottky trench 92 to form the first protection region 31 and the second protection region 32 .
  • the p-type impurity concentration of the first protection region 31 and the second protection region 32 may be in the range of 1 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 20 cm ⁇ 3 or less.
  • the resist mask used in the dry etching process for forming the gate trench 91 and the Schottky trench 92 can be used as an implantation mask.
  • the first protection region 31 and the second protection region 32 can also be formed at the same time in the same ion implantation process. After ion implantation, the resist mask is removed.
  • a resist mask is formed with openings at the locations where the first connection region 33 and the second connection region 34 shown in FIG. A connection region 34 is formed.
  • the p-type impurity concentration of the first connection region 33 and the second connection region 34 may be in the range of 1 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 20 cm ⁇ 3 or less. After ion implantation, the resist mask is removed.
  • annealing is performed at a temperature of 1300° C. to 1900° C. for 30 seconds to 1 hour in an inert gas atmosphere such as argon (Ar) gas using a heat treatment apparatus.
  • This annealing electrically activates the implanted N and Al ions.
  • a silicon oxide film 93 having a thickness of 10 nm or more and 300 nm or less is formed as shown in FIG. .
  • the silicon oxide film 93 may be formed by the CVD method.
  • a conductive polycrystalline silicon film 94 having a thickness of 300 nm or more and 2000 nm or less is formed on the silicon oxide film 93 by low pressure CVD. Then, by removing the silicon oxide film 93 and the polycrystalline silicon film 94 on the surface of the semiconductor layer 1 by etch back, as shown in FIG. 93 and polycrystalline silicon film 94 are left. Silicon oxide film 93 and polycrystalline silicon film 94 remaining in gate trench 91 become gate insulating film 50 and gate electrode 60, respectively.
  • an interlayer insulating film 55 made of silicon oxide having a thickness of 500 nm or more and 3000 nm or less is formed by low pressure CVD. Then, the interlayer insulating film 55 is patterned to remove the interlayer insulating film 55 on the source regions 40, the contact regions 35 and the Schottky trenches 92, as shown in FIG. Furthermore, the polycrystalline silicon film 94 in the Schottky trench 92 is removed by wet etching using an alkaline etchant such as an alkaline developer.
  • a metal such as Ni is deposited on the semiconductor layer 1 and annealed to form an ohmic electrode 70 made of silicide on the source region 40 and the contact region 35, as shown in FIG.
  • the silicon oxide film 93 in the Schottky trench 92 is removed by wet etching using hydrofluoric acid or the like. At this time, the surface layer portion of the interlayer insulating film 55 is also removed. Also, the natural oxide film on the surface of the ohmic electrode 70 can be removed.
  • a Schottky electrode 71 made of a metal containing Ti as a main component is formed on the inner surface of the Schottky trench 92, the ohmic electrode 70 and the interlayer insulating film 55 by sputtering.
  • an inert gas such as Ar
  • the Schottky electrode 71 and the drift layer 20 are Schottky-connected.
  • a source electrode 80 made of metal having a higher recrystallization temperature than Al is formed on the Schottky electrode 71 .
  • part of the source electrode 80 is filled in the Schottky trench 92 as the semiconductor layer 18 .
  • the source electrode 80 and the high recrystallization temperature metal layer 81 are preferably formed by electroless plating. By using the electroless plating method, the filling of the Schottky trench 92 with the high recrystallization temperature metal layer 81 can be improved, and filling defects due to cavities in the Schottky trench 92 during the manufacturing process can be prevented.
  • a back surface ohmic electrode (not shown) and a drain electrode 82 are formed on the second main surface 12 of the semiconductor substrate 10 to complete the semiconductor device having the structure shown in FIG.
  • the method for manufacturing a silicon carbide semiconductor device According to the method for manufacturing a silicon carbide semiconductor device according to the present embodiment, formation of voids in Schottky trench 92 during the manufacturing process is prevented, and the operating temperature of the completed silicon carbide semiconductor device is 150.degree. It also prevents the formation of voids in Schottky trench 92 due to stress when . Therefore, occurrence of defects such as peeling of Schottky electrode 71 is suppressed, and a highly reliable silicon carbide semiconductor device can be obtained.
  • FIG. 13 is a cross-sectional view of an SBD-embedded SiC trench MOSFET, which is a silicon carbide semiconductor device according to the second embodiment. Similar to FIG. 1, FIG. 13 shows a cross section of a part of an active region formed with a MOSFET and an SBD in a chip of an SBD-embedded SiC trench MOSFET.
  • the seed layer 72 is provided on the Schottky electrode 71 before forming the high recrystallization temperature metal layer 81, and is formed between the Schottky electrode 71 and the high recrystallization temperature metal layer 81 when forming the high recrystallization temperature metal layer 81 by plating. It works to improve adhesion with the metal layer 81 . Therefore, in the present embodiment, improvement in adhesion between Schottky electrode 71 and high recrystallization temperature metal layer 81 can be expected.
  • a seed layer 72 made of a metal containing Al as a main component is formed by sputtering or the like, as shown in FIG.
  • the seed layer 72 preferably has a thickness of 100 nm or more and 1 ⁇ m or less.
  • a source electrode 80 made of a metal having a higher recrystallization temperature than Al is formed on the seed layer 72 .
  • part of the source electrode 80 is filled in the Schottky trench 92 as the semiconductor layer 18 .
  • the source electrode 80 and the high recrystallization temperature metal layer 81 are preferably formed by electroless plating.
  • Embodiments 1 and 2 an example has been described in which the portion of semiconductor layer 1 adjacent to the upper end of Schottky trench 92 is p-type body region 30, but an n-type low resistance region is formed in that portion.
  • the body region 30 and the source region 40 are formed by ion implantation in the first and second embodiments, they may be formed by another method such as an epitaxial method.
  • body region 30 is formed in the entire surface layer portion of drift layer 20 , but body region 30 may be formed in part of the upper layer portion of drift layer 20 .
  • Schottky trench 92 does not necessarily have to penetrate body region 30 as long as its lower end is located in drift layer 20 . That is, Schottky trench 92 may be formed in a region where body region 30 is not formed.
  • the first protection region 31 and the second protection region 32 are provided under the trench, but the first protection region 31 and the second protection region 32 may be omitted. In that case, the first connection region 33 and the second connection region 34 may also be omitted.
  • the p-type impurity may be boron (B) or gallium (Ga).
  • Phosphorus (P) may be used as the n-type impurity instead of nitrogen (N).
  • the gate insulating film 50 is not necessarily an oxide film such as SiO 2 , and may be an insulating film other than an oxide film, or a combination of an insulating film other than an oxide film and an oxide film.
  • the crystal structure, plane orientation of the main surface, off-angle, and each implantation condition of the semiconductor substrate 10 were specifically shown, but these are merely examples, and are shown above. Examples are not limiting.
  • the semiconductor device has a structure in which the drain electrode 82 is formed on the back surface of the semiconductor substrate 10, that is, a so-called vertical MOSFET with an SBD built therein.
  • a so-called lateral MOSFET with an SBD built therein such as a RESURF (REduced SURface Field) MOSFET in which the drain electrode 82 is formed on the front surface of the drift layer 20.
  • RESURF REduced SURface Field
  • the switching element in which the SBD is built is not limited to a MOSFET, and may be, for example, an insulated gate bipolar transistor (IGBT), a MOSFET or IGBT having a superjunction structure.
  • the present embodiment applies the silicon carbide semiconductor devices according to the first and second embodiments described above to a power converter.
  • the present disclosure is not limited to a specific power converter, a case where the present disclosure is applied to a three-phase inverter will be described below as a third embodiment.
  • FIG. 15 is a block diagram showing the configuration of a power conversion system to which the power conversion device according to this embodiment is applied.
  • the power conversion system shown in FIG. 15 is composed of a power supply 100, a power converter 200, and a load 300.
  • the power supply 100 is a DC power supply and supplies DC power to the power converter 200 .
  • the power supply 100 can be composed of various things, for example, it can be composed of a DC system, a solar battery, a storage battery, or it can be composed of a rectifier circuit or an AC/DC converter connected to an AC system. good too.
  • power supply 100 may be configured by a DC/DC converter that converts DC power output from the DC system into predetermined power.
  • the power conversion device 200 is a three-phase inverter connected between the power supply 100 and the load 300 , converts the DC power supplied from the power supply 100 into AC power, and supplies the AC power to the load 300 .
  • the power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, and a drive circuit 202 that outputs a drive signal for driving each switching element of the main conversion circuit 201. , and a control circuit 203 that outputs a control signal for controlling the drive circuit 202 to the drive circuit 202 .
  • the drive circuit 202 turns off each normally-off switching element by setting the voltage of the gate electrode and the voltage of the source electrode 80 to the same potential.
  • the load 300 is a three-phase electric motor driven by AC power supplied from the power converter 200 .
  • the load 300 is not limited to a specific application, but is an electric motor mounted on various electrical equipment, such as a hybrid vehicle, an electric vehicle, a railroad vehicle, an elevator, or an electric motor for an air conditioner.
  • the main conversion circuit 201 includes a switching element and a freewheeling diode (not shown). By switching the switching element, the DC power supplied from the power supply 100 is converted into AC power and supplied to the load 300 .
  • the main conversion circuit 201 is a two-level three-phase full bridge circuit, and has six switching elements and It can consist of six freewheeling diodes in anti-parallel.
  • a silicon carbide semiconductor device manufactured by the method for manufacturing a silicon carbide semiconductor device according to any one of the first and second embodiments described above is applied to each switching element of main conversion circuit 201 .
  • each upper and lower arm forms each phase (U phase, V phase, W phase) of the full bridge circuit.
  • Output terminals of the upper and lower arms, that is, three output terminals of the main conversion circuit 201 are connected to the load 300 .
  • the drive circuit 202 generates a drive signal for driving the switching element of the main converter circuit 201 and supplies it to the control electrode of the switching element of the main converter circuit 201 .
  • a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrode of each switching element.
  • the driving signal is a voltage signal (ON signal) equal to or higher than the threshold voltage of the switching element, and when maintaining the switching element in the OFF state, the driving signal is a voltage equal to or less than the threshold voltage of the switching element. signal (off signal).
  • the control circuit 203 controls the switching elements of the main conversion circuit 201 so that the desired power is supplied to the load 300 . Specifically, based on the power to be supplied to the load 300, the time (on time) during which each switching element of the main conversion circuit 201 should be in the ON state is calculated. For example, the main conversion circuit 201 can be controlled by PWM control that modulates the ON time of the switching element according to the voltage to be output. Then, a control command (control signal) is output to the drive circuit 202 so that an ON signal is output to the switching element that should be in the ON state at each time point, and an OFF signal is output to the switching element that should be in the OFF state. The drive circuit 202 outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element according to this control signal.
  • the silicon carbide semiconductor device according to the first and second embodiments is applied as the switching element of the main conversion circuit 201, the electric power with low loss and high-speed switching reliability is improved.
  • a conversion device can be implemented.
  • the present disclosure is not limited to this, and can be applied to various power converters.
  • a two-level power conversion device is used, but a three-level or multi-level power conversion device may be used. You can apply it.
  • the present disclosure can be applied to a DC/DC converter or an AC/DC converter when power is supplied to a DC load or the like.
  • the power conversion device to which the present disclosure is applied is not limited to the case where the above-described load is an electric motor. It can also be used as a device, and can also be used as a power conditioner for a photovoltaic power generation system, an electric storage system, or the like.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Ce dispositif semi-conducteur au carbure de silicium comprend : une tranchée (91) de grille qui est formée dans une couche semi-conductrice (1) et qui pénètre à travers une région de source (40) et une région de corps (30) pour atteindre une couche de dérive (20) ; et une tranchée de Schottky (92) qui est formée dans la couche semi-conductrice (1) de telle sorte que son extrémité inférieure est située dans la couche de dérive (20). La tranchée (91) de grille comporte : un film d'isolation (50) de grille qui est formé sur la surface interne de la tranchée (91) de grille ; et une électrode (60) de grille qui est formée sur le film d'isolation (50) de grille dans la tranchée (91) de grille. La tranchée de Schottky (92) comporte : une électrode de Schottky (71) qui est formée sur la surface interne de la tranchée de Schottky (92) et qui est connectée par effet Schottky à la couche de dérive (20) ; et une couche métallique (81) à haute température de recristallisation qui est formée sur l'électrode de Schottky (71) dans la tranchée de Schottky (92) et qui est formée d'un métal ayant une température de recristallisation supérieure à celle de Al.
PCT/JP2021/048577 2021-12-27 2021-12-27 Dispositif semi-conducteur au carbure de silicium, dispositif de conversion d'énergie électrique, et procédé de production de dispositif semi-conducteur au carbure de silicium WO2023127023A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2022558572A JP7275407B1 (ja) 2021-12-27 2021-12-27 炭化珪素半導体装置、電力変換装置および炭化珪素半導体装置の製造方法
PCT/JP2021/048577 WO2023127023A1 (fr) 2021-12-27 2021-12-27 Dispositif semi-conducteur au carbure de silicium, dispositif de conversion d'énergie électrique, et procédé de production de dispositif semi-conducteur au carbure de silicium

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2021/048577 WO2023127023A1 (fr) 2021-12-27 2021-12-27 Dispositif semi-conducteur au carbure de silicium, dispositif de conversion d'énergie électrique, et procédé de production de dispositif semi-conducteur au carbure de silicium

Publications (1)

Publication Number Publication Date
WO2023127023A1 true WO2023127023A1 (fr) 2023-07-06

Family

ID=86332454

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2021/048577 WO2023127023A1 (fr) 2021-12-27 2021-12-27 Dispositif semi-conducteur au carbure de silicium, dispositif de conversion d'énergie électrique, et procédé de production de dispositif semi-conducteur au carbure de silicium

Country Status (2)

Country Link
JP (1) JP7275407B1 (fr)
WO (1) WO2023127023A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117293191A (zh) * 2023-11-24 2023-12-26 山东大学 一种版图结构、半导体器件和其制造方法
CN117673158A (zh) * 2024-01-31 2024-03-08 深圳天狼芯半导体有限公司 碳化硅mosfet及其制备方法、芯片

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000040742A (ja) * 1998-06-22 2000-02-08 Stmicroelectronics Inc ダマスク方法による銀メタリゼ―ション
JP2009170861A (ja) * 2008-01-11 2009-07-30 Young Joo Oh 金属キャパシタ及びその製造方法
JP2010129585A (ja) * 2008-11-25 2010-06-10 Toyota Motor Corp 半導体装置の製造方法
JP2010251719A (ja) * 2009-03-23 2010-11-04 Fuji Electric Systems Co Ltd 半導体装置の製造方法
WO2014156791A1 (fr) * 2013-03-29 2014-10-02 富士電機株式会社 Dispositif semi-conducteur et procédé de fabrication de dispositif semi-conducteur
WO2021014570A1 (fr) * 2019-07-23 2021-01-28 三菱電機株式会社 Dispositif à semi-conducteur au carbure de silicium, dispositif de conversion de puissance et procédé de fabrication de dispositif à semi-conducteur au carbure de silicium
JP2021180294A (ja) * 2020-05-15 2021-11-18 株式会社デンソー 半導体装置およびその製造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6168370B2 (ja) * 2015-12-17 2017-07-26 ローム株式会社 ＳｉＣ電界効果トランジスタ
JP6584966B2 (ja) * 2016-01-12 2019-10-02 株式会社東芝 半導体装置、半導体装置の製造方法、インバータ回路、駆動装置、車両、及び昇降機

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000040742A (ja) * 1998-06-22 2000-02-08 Stmicroelectronics Inc ダマスク方法による銀メタリゼ―ション
JP2009170861A (ja) * 2008-01-11 2009-07-30 Young Joo Oh 金属キャパシタ及びその製造方法
JP2010129585A (ja) * 2008-11-25 2010-06-10 Toyota Motor Corp 半導体装置の製造方法
JP2010251719A (ja) * 2009-03-23 2010-11-04 Fuji Electric Systems Co Ltd 半導体装置の製造方法
WO2014156791A1 (fr) * 2013-03-29 2014-10-02 富士電機株式会社 Dispositif semi-conducteur et procédé de fabrication de dispositif semi-conducteur
WO2021014570A1 (fr) * 2019-07-23 2021-01-28 三菱電機株式会社 Dispositif à semi-conducteur au carbure de silicium, dispositif de conversion de puissance et procédé de fabrication de dispositif à semi-conducteur au carbure de silicium
JP2021180294A (ja) * 2020-05-15 2021-11-18 株式会社デンソー 半導体装置およびその製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117293191A (zh) * 2023-11-24 2023-12-26 山东大学 一种版图结构、半导体器件和其制造方法
CN117293191B (zh) * 2023-11-24 2024-03-08 山东大学 一种版图结构、半导体器件和其制造方法
CN117673158A (zh) * 2024-01-31 2024-03-08 深圳天狼芯半导体有限公司 碳化硅mosfet及其制备方法、芯片

Also Published As

Publication number Publication date
JP7275407B1 (ja) 2023-05-17
JPWO2023127023A1 (fr) 2023-07-06

Similar Documents

Publication Publication Date Title
JP6490305B2 (ja) 半導体装置および電力変換装置
US11984492B2 (en) Silicon carbide semiconductor device, power converter, and method of manufacturing silicon carbide semiconductor device
US20200194554A1 (en) Silicon carbide semiconductor device, power converter, method of manufacturing silicon carbide semiconductor device, and method of manufacturing power converter
JP6735950B1 (ja) 炭化珪素半導体装置、電力変換装置および炭化珪素半導体装置の製造方法
JP7042898B2 (ja) 炭化珪素半導体装置、電力変換装置および炭化珪素半導体装置の製造方法
JP7275407B1 (ja) 炭化珪素半導体装置、電力変換装置および炭化珪素半導体装置の製造方法
CN111466032A (zh) 碳化硅半导体装置以及电力变换装置
JP6991370B2 (ja) 半導体装置及び電力変換装置
JP7138770B2 (ja) 炭化珪素半導体装置、電力変換装置および炭化珪素半導体装置の製造方法
WO2022168240A1 (fr) Dispositif à semi-conducteur au carbure de silicium et dispositif de conversion de puissance
JP6873273B2 (ja) 炭化珪素半導体装置および電力変換装置
JP7370476B2 (ja) 炭化珪素半導体装置の製造方法、炭化珪素半導体装置および電力変換装置
JP6947338B1 (ja) 炭化珪素半導体装置および電力変換装置の製造方法
JP7004117B1 (ja) 炭化珪素半導体装置および電力変換装置
JP7127748B2 (ja) 炭化珪素半導体装置、電力変換装置および炭化珪素半導体装置の製造方法
JP7094439B2 (ja) 炭化珪素半導体装置および電力変換装置
WO2022264212A1 (fr) Dispositif à semi-conducteur au carbure de silicium et convertisseur de puissance électrique utilisant un dispositif à semi-conducteur au carbure de silicium
WO2022190269A1 (fr) Dispositif à semi-conducteur au carbure de silicium, son procédé de fabrication et dispositif de conversion de puissance
JP7332812B2 (ja) 炭化珪素半導体装置および電力変換装置
WO2024038504A1 (fr) Dispositif à semi-conducteur au carbure de silicium, dispositif de conversion de puissance électrique, et procédé de production de dispositif à semi-conducteur au carbure de silicium
WO2023281669A1 (fr) Dispositif à semi-conducteur au carbure de silicium et convertisseur de puissance électrique utilisant un dispositif à semi-conducteur au carbure de silicium
JP2023008566A (ja) 半導体装置及び電力変換装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 2022558572

Country of ref document: JP

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21969907

Country of ref document: EP

Kind code of ref document: A1