WO2023125145A1 - 具有结型场板的dmos器件及其制造方法 - Google Patents

具有结型场板的dmos器件及其制造方法 Download PDF

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WO2023125145A1
WO2023125145A1 PCT/CN2022/140340 CN2022140340W WO2023125145A1 WO 2023125145 A1 WO2023125145 A1 WO 2023125145A1 CN 2022140340 W CN2022140340 W CN 2022140340W WO 2023125145 A1 WO2023125145 A1 WO 2023125145A1
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trench
layer
polysilicon layer
doped
doped polysilicon
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PCT/CN2022/140340
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English (en)
French (fr)
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林峰
许超奇
陈淑娴
李春旭
卢丽
刘斯扬
孙伟锋
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无锡华润上华科技有限公司
东南大学
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Priority to EP22914399.5A priority Critical patent/EP4369382A1/en
Publication of WO2023125145A1 publication Critical patent/WO2023125145A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66704—Lateral DMOS transistors, i.e. LDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode

Definitions

  • the invention relates to the technical field of semiconductor devices, in particular to a DMOS device with a junction field plate and a manufacturing method thereof.
  • Double-diffused Metal-Oxide-Semiconductor (DMOS) device is a typical and widely used high-voltage power semiconductor device.
  • DMOS devices increase the low-doped drift region between the source and drain, so that most of the voltage falls on the low-doped drift region, thereby improving the withstand voltage capability of the device, so that it can be used as a power MOS device in integrated circuits .
  • DMOS devices can be divided into two types: lateral (horizontal) double-diffused MOS (Lateral Double-diffused MOS, LDMOS) and vertical (vertical) double-diffused MOS (Vertical Double-diffused MOS, VDMOS).
  • LDMOS device is a radio frequency power device with great market demand and broad development prospects.
  • LDMOS devices are also widely used in radio frequency amplifiers, such as HF (High Frequency, high frequency), VHF (Very High Frequency, very high frequency ) and UHF (Ultra High Frequency, Ultra High Frequency) communication systems, pulse radar, industrial, scientific and medical applications, avionics and other fields.
  • HF High Frequency, high frequency
  • VHF Very High Frequency, very high frequency
  • UHF Ultra High Frequency, Ultra High Frequency
  • LDMOS devices have high breakdown voltage (Breakdown Voltage, BV, also known as withstand voltage) and low on-resistance (Specific on-Resistance, Rdson).
  • BV Barrier Down Voltage
  • Rdson Specific on-Resistance
  • the object of the present invention is to provide a DMOS device with a junction field plate and a manufacturing method thereof, so as to solve the problem that the existing DMOS device cannot effectively increase the withstand voltage or reduce the on-resistance.
  • the present invention provides a method for manufacturing a DMOS device with a junction field plate, the method for manufacturing a DMOS device with a junction field plate includes:
  • first doped polysilicon layer with a first conductivity type on the semiconductor substrate, the first doped polysilicon layer covering the surface of the semiconductor substrate and the first trench;
  • the second doped polysilicon layer includes a first sub-doped layer with the second conductivity type and a second sub-doped layer with the first conductivity type located on the first sub-doped layer;
  • a first lead-out structure electrically connected to the source region, a second lead-out structure electrically connected to the drain region and the third sub-doped layer, and a third lead-out structure electrically connected to the gate are formed.
  • providing a semiconductor substrate in which a first trench is formed includes: the semiconductor substrate is further formed with a a second groove connected to the first groove;
  • the forming a first doped polysilicon layer with a first conductivity type on the semiconductor substrate, where the first doped polysilicon layer covers the semiconductor substrate and the surface of the first trench, includes: the first a doped polysilicon layer also covers the surface of the second trench;
  • the second doped polysilicon layer includes a first sub-doped layer with a second conductivity type and a second sub-doped layer with a first conductivity type located on the first sub-doped layer, including: A part of the bottom surface of the second trench forms the second doped polysilicon layer;
  • the performing a heat treatment process so that the second doped polysilicon layer in the first trench extends toward the side of the first trench includes: making the second doped polysilicon layer in the second trench the second doped polysilicon layer extends toward the side of the second trench;
  • a third doping process is performed to form a drain region on the surface of the semiconductor substrate and A third sub-doped layer having a second conductivity type is formed on the surface of the first doped polysilicon layer, and the second doped polysilicon layer and the first doped polysilicon layer on the sides of the first trench are and the third sub-doped layer as a junction field plate, before the first sub-doped layer on the side of the first trench is used as a gate, it also includes: removing the side of the second trench The first doped polysilicon layer, the second doped polysilicon layer in the second trench serves as a gate extraction layer, and the gate extraction layer is connected to the gate; and
  • the formation of the first lead-out structure electrically connecting the source region, the second lead-out structure electrically connecting the drain region and the third sub-doped layer, and the third lead-out structure electrically connecting the gate includes: The third lead-out structure is electrically connected to the gate by being connected to the gate lead-out layer.
  • the first conductivity type is P-type
  • the second conductivity type is N-type
  • the A first doped polysilicon layer having a first conductivity type comprising:
  • the doping concentration of the first doped polysilicon layer is 4E14atom/cm ⁇ 3 to 1E16atom/cm ⁇ 3
  • the thickness of the first doped polysilicon layer is 0.15 ⁇ m to 0.35 ⁇ m.
  • the first conductivity type is P-type
  • the second conductivity type is N-type
  • the polysilicon layer performs a first doping process and a second doping process, including:
  • the first doping process is doped with phosphorus ions at a doping concentration of 1E17atom/cm -3 to 1E18atom/cm -3 ;
  • the second doping process is doping with indium ions at a doping concentration of 1E20atom/cm -3 cm ⁇ 3 ⁇ 1E21 atom/cm ⁇ 3 .
  • the heat treatment process is performed so that the second doped polysilicon layer in the first trench
  • the sides of the trench extend and also include:
  • the diffusion rate of dopant ions in the first doping process is greater than the diffusion rate of dopant ions in the second doping process, so that the first sub-doped layer in the first trench moves toward the first trench
  • the extension length of the side of the groove is longer than the extension length of the second sub-doped layer to the side of the first trench, and the first sub-doped layer in the second trench extends to the second
  • the extension length of the side of the trench is longer than the extension length of the second sub-doped layer to the side of the second trench.
  • the heat treatment process is performed so that the second doped polysilicon layer in the first trench
  • the sides of the trench extend and also include:
  • the second doped polysilicon layer on the surface of the semiconductor substrate also covers part of the side surfaces of the first trench and part of the side surfaces of the second trench.
  • the removing part of the second doped polysilicon layer to expose part of the bottom surface of the first trench includes:
  • the first patterned photoresist layer fills the second trench and extends to cover a part of the second doped polysilicon layer on the semiconductor substrate, exposing the first trench and another part of the second doped polysilicon layer on the semiconductor substrate;
  • the first conductivity type is P-type
  • the second conductivity type is N-type
  • the first trench The bottom forms a body region and a source region located within the body region, comprising:
  • An N-type doping process is performed on part of the body region to form the source region in the body region.
  • the first doped polysilicon layer on the side of the second trench is removed, and the The second doped polysilicon layer is used as a gate extraction layer, and the gate extraction layer is connected to the gate, including:
  • the first doped polysilicon layer on the side of the second trench is removed by dry etching process.
  • the present invention also provides a DMOS device with a junction field plate, the DMOS device with a junction field plate comprising:
  • the bottom of the groove, the second doped polysilicon layer includes a first sub-doped layer and a second sub-doped layer on the first sub-doped layer; formed on the sidewall of the first trench
  • the third sub-doped layer, the third sub-doped layer is closer to the top of the first trench than the first doped polysilicon layer; the first sub-doped in the first trench Layer as a gate, the first doped polysilicon layer, the second doped polysilicon layer and the third sub-doped layer in the first trench as a junction field plate, wherein the first A doped polysilicon layer is of the first conductivity type, the first sub-doped layer is of the second conductivity type, the second sub-doped layer is of the first conductivity type, and the third sub-d
  • a second trench communicating with the first trench is further formed in the semiconductor substrate, and the second doped polysilicon layer also covers The bottom surface of the second trench, the second doped polysilicon layer in the second trench serves as a gate extraction layer, the gate extraction layer is connected to the gate, and the third extraction structure
  • the electrical connection with the gate is realized by connecting with the gate lead-out layer.
  • the DMOS device with a junction field plate in the first trench, from the bottom of the first trench to the notch of the first trench, the The second doped polysilicon layer, the first doped polysilicon layer and the third sub-doped layer are sequentially in contact with each other and cover side surfaces of the first trench.
  • the second sub-doped layer is located in the first sub-doped layer, and in the first trench, the first The bottom surface of the doped polysilicon layer is in contact with both the first sub-doped layer and the second sub-doped layer.
  • the second trench in the first direction, communicates with the first trench; in the second direction, the second trench A groove is spaced apart from the first groove, and the first direction and the second direction are perpendicular.
  • the body region surrounds the bottom of the first trench.
  • the drain region is on the surface of the semiconductor substrate, and the source region is in the semiconductor substrate at the bottom of the first trench, and the gate is at the bottom of the first trench.
  • the horizontal withstand voltage of LDMOS is changed to the vertical withstand voltage, so that the size of the entire device can be reduced, the on-resistance can be reduced, and the contradictory relationship between withstand voltage and on-resistance can be greatly optimized.
  • a junction field plate structure is formed in the DMOS device, thereby improving the effect of reducing the surface resistance (Resurf), and at the same time, due to the existence of the junction field plate structure, the trench depth in the DMOS device can be reduced. Small, thereby reducing the aspect ratio of the device, thereby improving the feasibility of increasing the withstand voltage gear. Furthermore, the source region and the drain region in the DMOS device are drawn out on the same surface, so that the manufacturing process of the CMOS device can be compatible.
  • the second doped polysilicon layer includes a first sub-doped layer and a second sub-doped layer located on the first sub-doped layer, the first sub-doped layer and the second sub-doped layer
  • the layers are of different conductivity types, so that in the case of an N-type gate, the P-type doped layer can also be directly connected to the gate potential, thereby improving the efficiency of the junction field plate.
  • FIG. 1 to 11 are schematic structural views of devices formed in a method for manufacturing a DMOS device with a junction field plate according to an embodiment of the present invention
  • FIG. 12 is a schematic top view of the second doped polysilicon layer in the DMOS device with a junction field plate described in FIG. 11;
  • Fig. 13 and Fig. 14 are working schematic diagrams of the junction field plate in the embodiment of the present invention.
  • the core idea of the present invention is to provide a DMOS device with a junction field plate and its manufacturing method.
  • the drain region is on the surface of the semiconductor substrate, and the source region is in the semiconductor substrate at the bottom of the first trench.
  • the position of the bottom of a trench changes from the horizontal withstand voltage of LDMOS to the vertical withstand voltage, so that the size of the entire device can be reduced, the on-resistance can be reduced, and the contradictory relationship between the withstand voltage and on-resistance can be greatly optimized.
  • a junction field plate structure is formed in the DMOS device, thereby improving the effect of reducing the surface resistance (Resurf), and at the same time, due to the existence of the junction field plate structure, the trench depth in the DMOS device can be reduced.
  • the source region and the drain region in the DMOS device are drawn out on the same surface, so that the manufacturing process of the CMOS device can be compatible.
  • the second doped polysilicon layer includes a first sub-doped layer and a second sub-doped layer located on the first sub-doped layer, the first sub-doped layer and the second sub-doped layer
  • the layers are of different conductivity types, so that in the case of an N-type gate, the P-type doped layer can also be directly connected to the gate potential, thereby improving the efficiency of the junction field plate.
  • the DMOS device with a junction field plate and the manufacturing method thereof provided in the present application may be an N-type DMOS device, or it may be a P-type DMOS device.
  • an N-type DMOS device is taken as an example for a detailed description. According to the detailed description of the N-type DMOS device, those skilled in the art can obtain a P-type DMOS device and its manufacturing method accordingly. Let me repeat.
  • FIG. 1 to FIG. 12 are schematic structural diagrams of devices formed in the method of manufacturing a DMOS device with a junction field plate according to an embodiment of the present invention.
  • a semiconductor substrate 100 is provided, and a first trench 102 and a second trench 104 are formed in the semiconductor substrate 100 .
  • a semiconductor substrate 100 is provided first, and then, a doping process is performed on the semiconductor substrate 100 to form a drift region 106 in the semiconductor substrate 100, wherein the drift region 106 can use any known A process is formed.
  • a first hard mask layer 108 is formed on the surface of the semiconductor substrate 100, and the first hard mask layer 108 may specifically be a laminated structure, for example, the first hard mask layer
  • the mask layer 108 may be an ONO (oxide-SIN-oxide, oxide layer-nitride layer-oxide layer) three-layer stack structure.
  • the first hard mask layer 108 has been patterned to expose part of the surface of the semiconductor substrate 100 .
  • an etching process may be performed on the exposed semiconductor substrate 100 to form the first trench 102 and the second trench 104 .
  • the first trench 102 and the second trench 104 are respectively located on both sides of the drift region 106, that is, the drift region 106 is formed in the first trench 102 and the second trench 104 in the semiconductor substrate 100 .
  • a first dielectric layer (the first dielectric layer is not shown in FIG. 1 ) is formed on the semiconductor substrate 100, and the first dielectric layer covers the semiconductor substrate 100, the first trench 102 and the surface of the second trench 104 .
  • the first dielectric layer may be an oxide layer, a nitride layer, or the like.
  • a first doped polysilicon layer 110 is formed on the semiconductor substrate 100 , the first doped polysilicon layer 110 covers the surface of the semiconductor substrate 100 and the surface of the first groove 102 and the surface of the second trench 104 .
  • the first doped polysilicon layer 110 covers the upper surface of the first hard mask layer 108, the side surfaces and the bottom surface of the first trench 102 and the second trench The sides and bottom of the groove 104. That is, in the embodiment of the present application, the first doped polysilicon layer 110 covers the first dielectric layer.
  • the thickness of the first doped polysilicon layer 110 is 0.15 ⁇ m ⁇ 0.35 ⁇ m, for example, the thickness of the first doped polysilicon layer 110 may be 0.18 ⁇ m, 0.20 ⁇ m, 0.25 ⁇ m, 0.27 ⁇ m or 0.33 ⁇ m wait.
  • the first doped polysilicon layer 110 can be formed specifically as follows: a polysilicon layer (not shown in FIG. 2 ) is formed on the semiconductor substrate 100, and a P-type doping process to form the first doped polysilicon layer 110 .
  • the doping concentration of the first doped polysilicon layer is 4E14atom/cm -3 to 1E16atom/cm -3 , for example, 8E14atom/cm -3 , 1E15atom/cm -3 , 5E15atom/cm -3 or 9E15atom /cm -3 and so on;
  • the dopant ions can be, for example, boron (B) and so on.
  • an N-type doping process and a P-type doping process are performed on the first doped polysilicon layer 110, so that the surface of the semiconductor substrate 100 and the part of the first trench 102
  • the bottom surface and part of the bottom surface of the second trench 104 form a second doped polysilicon layer 112
  • the second doped polysilicon layer 112 includes a first sub-doped layer 114a and is located on the first sub-doped layer 114a.
  • the second sub-doped layer 114b is the first sub-doped layer 114a is N-type
  • the second sub-doped layer 114b is P-type.
  • the second sub-doped layer 114b is heavily doped, that is, the first doped polysilicon layer 110 is a lightly doped P-type conductive layer, and the The second sub-doped layer 114b is a heavily doped P-type conductive layer.
  • a common implantation process can be used to perform doping on the entire semiconductor substrate 100 , thereby reducing the process cost.
  • the first doped polysilicon layer 110 at the bottom of the first trench 102 and covering the sides of the first trench 102 and the bottom of the second trench 104 and covering the second trench 104 Due to the blocking effect of the first doped polysilicon layer 110 on the side of the first doped polysilicon layer 110, when the N-type doping process and the P-type doping process are performed on the first doped polysilicon layer 110 , usually remains as the first doped polysilicon layer 110 .
  • the N-type dopant ions are phosphorus ions
  • the doping concentration is 1E17atom/cm -3 to 1E18atom/cm -3 , for example, the doping concentration is 2E17atom/cm -3 , 4E17atom/cm -3 , 5E17atom/cm -3 3 or 7E17atom/cm -3 etc.
  • the P-type dopant ions are indium ions, and the doping concentration is 1E20atom/cm -3 to 1E21atom/cm -3 , for example, the doping concentration is 2E20atom/cm -3 , 3E20atom/cm -3 , 5E20atom/cm -3 or 8E20atom /cm -3 etc. That is, here, the heavily doped second sub-doped layer 114b is formed.
  • a heat treatment process is performed on the second doped polysilicon layer 112 , the second doped polysilicon layer on the bottom surface of the first trench 102 and the bottom surface of the second trench 104
  • the dopant ions in 112 diffuse into the first doped polysilicon layer 110, so that the second doped polysilicon layer 112 on the bottom surface of the first trench 102 faces toward the side of the first trench 102.
  • the heat treatment process is an annealing process.
  • the heat treatment process may also be other high temperature treatment processes.
  • the diffusion rate of N-type dopant ions is faster than the diffusion rate of P-type dopant ions, so that the first sub-doped layer 114a in the first trench 102 moves toward the first sub-doped layer 114a.
  • the extension length of the side of a trench 102 is longer than the extension length of the second sub-doped layer 114b to the side of the first trench 102 and the first sub-doping in the second trench 104
  • the extension length of the layer 114 a to the side of the second trench 104 is longer than the extension length of the second sub-doped layer 114 b to the side of the second trench 104 .
  • the bottom wall and the sidewall of the second sub-doped layer 114b in the first trench 102 may also be covered by the first sub-doped layer. Surrounded by the layer 114a, the bottom wall and the sidewall of the second sub-doped layer 114b in the second trench 104 are surrounded by the first sub-doped layer 114a.
  • bottom wall is equivalent to the term “bottom surface”
  • side wall is equivalent to the term “side”
  • surface is usually only such an expression
  • Bottom wall and the term “bottom surface” and the term “side wall” and the term “side surface” are often used interchangeably, so this expression is also used in the terms of this application.
  • first sub-doped layer 114a in the first trench 102 extends to the side of the first trench 102, so that the first sub-doped layer 114a covers the first trench The entire bottom surface of the groove 102; the second sub-doped layer 114b in the first groove 102 extends to the side of the first groove 102 but does not touch the side of the first groove 102 , so that the second sub-doped layer 114b is located in the first sub-doped layer 114a.
  • the first sub-doped layer 114a in the second trench 104 extends to the side of the second trench 104, so that the first sub-doped layer 114a covers the entire bottom surface of the second trench 104; the second sub-doped layer 114b in the second trench 104 extends toward the side of the second trench 104 but does not overlap with the second The sides of the trenches 104 are in contact, so that the second sub-doped layer 114b is located in the first sub-doped layer 114a.
  • the surface of the semiconductor substrate 100 (here specifically, the surface of the first hard mask layer 108
  • the dopant ions in the second doped polysilicon layer 112 on the surface) diffuse into the first doped polysilicon layer 110, so that the second doped polysilicon layer 112 on the surface of the semiconductor substrate 100 diffuses toward the
  • the side surfaces of the first trench 102 and the second trench 104 extend, and cover part of the sides of the first trench 102 and part of the sides of the second trench 104 . That is, the second doped polysilicon layer 112 on the surface of the semiconductor substrate 100 extends to cover the top (side) of the first trench 102 and the top (side) of the second trench 104 .
  • the first sub-doped layer 114a in the second doped polysilicon layer 112 covering the upper surface of the semiconductor substrate 100 faces the side of the first trench 102 and the side of the second groove 104 , and cover a part of the side of the first groove 102 near the top and a part of the side of the second groove 104 near the top.
  • the gate further includes a first dielectric layer (first dielectric layer not shown in Figure 5).
  • the first doped layer 114a in the first trench 102 serves as the gate 122a, that is, if the reference numeral 114a and the appended
  • the figure 122a may point to the same structure; at the same time, in the following, due to the need of expression, the first doped layer 114a and the gate 122a in the first trench 102 may appear at the same time, Both are required to implement different instructions.
  • removing part of the second doped polysilicon layer 112 on the bottom surface of the first trench 102 includes: forming a first patterned photoresist layer 116, the The first patterned photoresist layer 116 fills the second trench 104 and extends to cover a part of the second doped polysilicon layer 112 on the semiconductor substrate 100 (that is, covers the area close to the second trench 104 Part of the second doped polysilicon layer 112), exposing the first trench 102 and another part of the second doped polysilicon layer 112 on the semiconductor substrate 100 (that is, exposing part of the second doped polysilicon layer 112 of the groove 102); the second doped polysilicon layer 112 on the exposed bottom surface of the first trench 102 (here, the bottom surface of the first trench 102 The second doped polysilicon layer 112 close to the side of the first trench 102 is not exposed because it is covered with the first doped polysilicon layer 110 (refer to FIG.
  • part of the second doped polysilicon layer 112 on the bottom surface of the first trench 102 and part of the second doped polysilicon layer 112 on the semiconductor substrate 100 may be removed by a dry etching process, thus, the semiconductor substrate 100 at the bottom of the first trench 100 and the upper surface of the first doped polysilicon layer 110 in the first trench 100 are exposed.
  • the exposed second doped polysilicon layer 112 on the bottom surface of the first trench 102 and the exposed first doped polysilicon layer 112 on the semiconductor substrate 100 After performing an etching process on the second doped polysilicon layer 112, the first hard mask layer 108 at the edge of the notch of the first trench 102 and the semiconductor substrate 100 on a part of the bottom surface of the first trench 102 are exposed, And keep the first doped polysilicon layer 110 on the side of the first trench 102 and the second doped polysilicon layer 112 on the side of the first trench 102 .
  • the second doped polysilicon layer 112 on the side of the first trench 102 may be located on the side of the first trench 102 , and the second doped polysilicon layer 112 on the upper and lower parts of the first doped polysilicon layer 110 may be located on the side of the first trench 102 .
  • Doped polysilicon layer 112 (the second doped polysilicon layer 112 located on the side of the first trench 102 and on the top of the first doped polysilicon layer 110 is not shown in FIG. 5 );
  • the second doped polysilicon layer 112 on the side of a trench 102 may also be located on the side of the first trench 102, and only the second doped polysilicon layer 112 located at the lower part of the first doped polysilicon layer 110 Layer 112.
  • a body region 118 and a source region 120 located in the body region 118 are formed in the semiconductor substrate 100 at the bottom of the first trench 102 .
  • a P-type doping process may be performed on the semiconductor substrate 100 at the bottom of the first trench 102 to form the body in the semiconductor substrate 100 at the bottom of the first trench 102.
  • the body region 118 may only be in adjacent contact with the bottom surface of the first trench 102; the body region 118 may also surround the bottom of the first trench 102, that is, the body region 118 is both in contact with the
  • the bottom surface of the first trench 102 is in adjacent contact and also in adjacent contact with part of the side surfaces of the first trench 102 .
  • an N-type doping process is performed on part of the body region 118 to form the source region 120 in the body region 118 .
  • the first sub-doped layer 114a is in contact with the source region 120, that is, the source region 120 extends to directly below the first sub-doped layer 114a so as to be connected to the first The sub-doped layers 114a are in contact with each other.
  • the upper surface of the first doped polysilicon layer 110 in the first trench 102 is also doped with N-type ions.
  • the first patterned photoresist layer 116 is removed.
  • the first doped polysilicon layer 110 on the side of the second trench 104 is removed, and the second The doped polysilicon layer 112 serves as the gate extraction layer 122b.
  • the second doped polysilicon layer 112 in the second trench 104 serves as the gate lead-out layer 122b, that is, if the reference numeral 112 appears in the drawing at the same time and reference numeral 122b, both may point to the same structure; meanwhile, in the following, due to the need of expression, the second doped polysilicon layer 112 in the second trench 104 and the gate lead-out layer 122b May appear at the same time, are required to implement different instructions.
  • the second hard mask layer 124 extends to cover the second doped polysilicon layer 112 on the surface of the semiconductor substrate 100 .
  • the material of the second hard mask layer 124 is a stack structure of oxide layer-nitride layer-oxide layer.
  • part of the second doped polysilicon layer 112 on the semiconductor substrate 100 is also removed.
  • the polysilicon layer 112 also exposes part of the first hard mask layer 108 , so here, the second hard mask layer 124 also covers the exposed part of the first hard mask layer 108 .
  • a part of the second hard mask layer 124 is removed by wet or dry etching to expose the second doped polysilicon layer 112 on the surface of the semiconductor substrate 100 . That is, here, the second hard mask layer 124 on the surface of the semiconductor substrate 100 is removed, and the second hard mask layer 124 in the first trench 102 and the second trench 104 remains, Thus, the second doped polysilicon layer 112 on the surface of the semiconductor substrate 100 is exposed.
  • the second doped polysilicon layer 112 on the surface of the semiconductor substrate 100 is removed by a dry etching process.
  • the first hard mask layer 108 on the surface of the semiconductor substrate 100 is exposed.
  • the first doped polysilicon layer 110 and the The second hard mask layer 124 in the second trench 104 is described. In other embodiments of the present application, for the structure shown in FIG.
  • the heteropolysilicon layer 112 In the case of the heteropolysilicon layer 112, after the second doped polysilicon layer 112 on the surface of the semiconductor substrate 100 is removed by a dry etching process, what is exposed is located on the side of the first trench 102, and The second doped polysilicon layer 112 on the top of the first doped polysilicon layer 110 (on the side of the first trench 102, and the second doped polysilicon layer on the top of the first doped polysilicon layer 110 layer 112 is not shown in FIG. 8 ) and the second hard mask layer 124 within the first trench 102 .
  • a second patterned photoresist layer 126 is formed, and the second patterned photoresist layer 126 covers the first trench 102 and exposes the semiconductor substrate 100 surface.
  • the second patterned photoresist layer 126 covers the second hard mask layer 124 and the first doped polysilicon layer 110 in the first trench 102 .
  • the second patterned photoresist layer 126 may also cover the second hard mask layer 124 in the first trench 102 and the The second doped polysilicon layer 112 is on the side of the groove 102 and located on the top of the first doped polysilicon layer 110 .
  • the second doped polysilicon layer 112 remaining in the second trench 104 serves as the gate lead-out layer 122b.
  • the second patterned photoresist layer 126 is removed.
  • the extraction of the gate 122a can be facilitated through the gate extraction layer 122b, thereby simplifying the process and improving the quality and reliability of the DMOS device.
  • the gate lead-out layer 122b may not be formed, and correspondingly, the second trench 104 does not need to be formed, and the first doped polysilicon layer 110, the second trench 104 do not need to be formed therein. Doped polysilicon layer 112 and the like.
  • it further includes filling the second hard mask layer 124 again in the second trench 104 to fill up the second trench 104 .
  • a chemical mechanical polishing (CMP) process is performed on the semiconductor substrate 100 to remove the second patterned photoresist layer 126 and the first hard mask layer 108 on the surface of the semiconductor substrate 100, exposing The semiconductor substrate 100 and the upper surface of the first doped polysilicon layer 110 are exposed.
  • CMP chemical mechanical polishing
  • what is exposed may also be the semiconductor substrate 100 and the second doped polysilicon layer 112 ( The second doped polysilicon layer 112 located on the side of the first trench 102 and on the top of the first doped polysilicon layer 110 is not shown in FIG. 9 ).
  • the second patterned photoresist layer 126 and the first hard mask layer 108 can also be respectively removed through two-step processes, for example, the second patterned photoresist layer 126 can be removed through a stripping process first. The adhesive layer 126, and then the first hard mask layer 108 is removed by a chemical mechanical polishing process.
  • a doping process is performed on the semiconductor substrate 100 and the first doped polysilicon layer 110 to form a drain region 128 on the surface of the semiconductor substrate 100 and to form a drain region 128 on the first doped polysilicon layer.
  • a third sub-doped layer 130 is formed on the surface of the trench 110 , so that a junction field plate 132 is formed on the side of the first trench 102 .
  • the first sub-doped layer 114a on the bottom side of the first trench 102 serves as a device gate, and is connected with the second sub-doped layer 114b on the side of the first trench 102 ,
  • the combination of the first doped polysilicon layer 110 and the third sub-doped layer 130 serves as a junction field plate 132 .
  • the drain region 128 is located in the semiconductor substrate 100 between the first trench 102 and the second trench 104 .
  • first lead-out structure 134 electrically connected to the source region 120
  • second lead-out structure 136 electrically connected to the drain region 128, and a third lead-out structure electrically connected to the gate lead-out layer 122b.
  • structure 138 wherein the second lead-out structure 136 is also electrically connected to the third sub-doped layer 130 .
  • the third lead-out structure 138 is electrically connected to the gate 122a by being connected to the gate lead-out layer 122b.
  • a second dielectric layer 140 can be formed, and the second dielectric layer 140 covers the semiconductor substrate 100 and the second hard mask layer 124;
  • the second hard mask layer 124 performs an etching process to form a first opening (not shown in FIG. 11 ) exposing the source region 120, a second opening exposing the drain region 128 and the third sub-doped layer 130.
  • the conductive layer is filled to form the first lead-out structure 134 , the second lead-out structure 136 and the third lead-out structure 138 .
  • the first opening, the second opening and the third opening may be formed through different etching steps, for example, the second opening may be formed through a shallow hole etching step, and the first opening And the third opening may be formed by a deep hole etching step.
  • an embodiment of the present application also provides a DMOS device with a junction field plate.
  • the DMOS device with a junction field plate includes: a semiconductor substrate 100, the semiconductor substrate 100 is formed with a first trench 102; a first doped polysilicon layer 110 and a second doped polysilicon layer 112 formed on the sidewall of the first trench 102, and the second doped polysilicon layer 112 is relatively
  • the first doped polysilicon layer 110 is close to the bottom of the first trench 102
  • the second doped polysilicon layer 112 includes a first sub-doped layer 114a and a doped layer on the first sub-doped layer 114a.
  • the second sub-doped layer 114b; the third sub-doped layer 130 formed on the sidewall of the first trench 102, the third sub-doped layer 130 is closer to the first doped polysilicon layer 110
  • the top of the first trench 102; the first sub-doped layer 114a in the first trench 102 serves as a gate 122a, and the first doped polysilicon layer in the first trench 102 110.
  • the second doped polysilicon layer 112 and the third sub-doped layer 130 form a junction field plate 132, wherein the first doped polysilicon layer 110 is P-type, and the first sub-doped Layer 114a is N-type, the second sub-doped layer 114b is P-type, and the third sub-doped layer 130 is N-type; formed in the semiconductor substrate 100 at the bottom of the first trench 102
  • the second lead-out structure 136 of the region 128 is electrically connected to the third lead-out structure 138 of the gate 122a, wherein the second lead-out structure 136 is also electrically connected to the third sub-doped layer 130 .
  • the DMOS device with a junction field plate further includes a second trench 104 communicating with the first trench 102 .
  • FIG. 12 is a schematic cross-sectional top view of the DMOS device with a junction field plate described in FIG. 11 along the line AA'.
  • the second groove 104 communicates with the first groove 102; in the second direction Y, the second groove 104 is spaced apart from the first groove 102, and the first direction X perpendicular to the second direction Y. That is, the first groove 102 and the second groove 104 form a "day"-shaped groove.
  • the second doped polysilicon layer 112 also covers the bottom surface of the second trench 104, the second doped polysilicon layer 112 in the second trench 104 serves as a gate lead-out layer 122b, and the gate
  • the lead-out layer 122b is connected to the gate 122a, and the third lead-out structure 138 is electrically connected to the gate 122a by being directly connected to the gate lead-out layer 122b.
  • the second sub-doped layer 114b is located in the first sub-doped layer 114a, and in the first trench 102, the bottom surface of the first doped polysilicon layer 110 and Both the first sub-doped layer 114a and the second sub-doped layer 114b are in contact with each other.
  • the DMOS device with a junction field plate further includes: a drift region 106 formed in the semiconductor substrate 100 between the first trench 102 and the second trench 104 .
  • the drain region 128 is located in the semiconductor substrate 100 between the first trench 102 and the second trench 104 . Furthermore, the drain region 128 is located in the drift region 106 .
  • the first trench 102 , the drift region 106 and the second trench 104 are arranged along the second direction Y.
  • the first doped polysilicon layer 110 is a doped polysilicon layer with a doping concentration of 4E14 atom/cm -3 to 1E16 atom/cm -3 , and the thickness of the first doped polysilicon layer 110 is 0.15 ⁇ m to 0.35 ⁇ m.
  • the first sub-doped layer 114a is a doped polysilicon layer, and the doping ions are phosphorus ions with a doping concentration of 1E17atom/cm -3 ⁇ 1E18atom/cm -3 ; the second sub-doped layer 114b is a doped
  • the impurity polysilicon layer and the doping ions are indium ions and the doping concentration is 1E20atom/cm -3 -1E21atom/cm -3 .
  • the drain region 128 is on the surface of the semiconductor substrate 100, and the source region 120 is on the bottom of the first trench 102.
  • the gate 122a is at the bottom of the first trench 102, so the lateral withstand voltage of LDMOS is changed to the vertical withstand voltage, so that the size of the entire device can be reduced, the on-resistance can be reduced, and the withstand voltage and on-resistance relationship.
  • a junction field plate 132 is formed in the DMOS device, thereby improving the effect of reducing the surface resistance (Resurf), and at the same time, due to the existence of the junction field plate 132, the trench depth in the DMOS device can be reduced. Small, thereby reducing the aspect ratio of the device trench, thereby improving the feasibility of increasing the withstand voltage gear. In other words, the withstand voltage range of the DMOS device can be further improved without increasing the aspect ratio of the trench, and without losing the current capability of the device. Furthermore, the source region 120 and the drain region 128 in the DMOS device are drawn out on the same surface, so that the manufacturing process of the CMOS device can be compatible.
  • the second doped polysilicon layer 112 includes a first sub-doped layer 114a and a second sub-doped layer 114b located on the first sub-doped layer 114a, the first sub-doped layer 114a and the The conductivity types of the second sub-doped layer 114 b are different, so that in the case of an N-type gate, the P-type doped layer can also be directly connected to the potential of the gate 122 , thereby improving the efficiency of the junction field plate 132 .
  • a communication groove is provided on the side of the second groove 104 and the first groove 102, so that the first sub-doped layer 114a and the second sub-doped layer 114a in the second groove 104
  • the doped layer 114b is electrically connected to the first sub-doped layer 114a and the second sub-doped layer 114b in the first trench 102 .
  • the second sub-doped layer 114 b in the second trench 104 and the second sub-doped layer 114 b in the first trench 102 are directly added to the first doped polysilicon layer 110 in the first trench 102 . That is to say, while adding the gate voltage to the gate structure in the first trench 102, the gate voltage is also directly added to the first doped polysilicon layer 110 in the first trench 102, without additionally breaking down the PN junction to The first doped polysilicon layer 110 within the first trench 102 conducts the gate voltage.
  • the P-type doped layer can also be directly connected to the gate potential, thereby improving the switching capability of the gate and the efficiency of the junction field plate.
  • the first trench 102 and the second trench 104 form a "day"-shaped trench.
  • the shaped structure includes a comb tooth part and a comb handle connected to the comb tooth part.
  • FIG. 13 and FIG. 14 are working schematic diagrams of the junction field plate in the embodiment of the present invention.
  • the first doped polysilicon layer 110 in the junction field plate 132 will have a positive charge, so that the drift region 106 will accumulate more electrons, and the drift region 106 will accumulate more electrons.
  • the resistance of 106 is reduced, so that the current capability is improved.
  • FIG. 13 when the gate voltage is greater than the threshold voltage, the first doped polysilicon layer 110 (in the junction field plate 132) will have a positive charge, so that the drift region 106 will accumulate more electrons, and the drift region 106 will accumulate more electrons. The resistance of 106 is reduced, so that the current capability is improved.
  • the drain region 128 undergoes PN junction reverse bias, and the potential in the first doped polysilicon layer 110 (in the junction field plate 132 )
  • the wire can adjust the potential lines of the drift region 106, so that the potential lines of the drift region 106 can be more evenly distributed in the drift region 106, thereby achieving the effect of increasing the withstand voltage.

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Abstract

本发明提供了一种具有结型场板的DMOS器件及其制造方法，漏区在半导体基底的表面，源区在第一沟槽的底部的半导体基底中，栅极在第一沟槽的底部，由此实现了纵向耐压，可以缩小整个器件的尺寸，降低导通电阻，极大的优化了耐压和导通电阻的关系。结型场板使得降低表面电阻的效果得到了提升，同时DMOS器件中的沟槽深度可以减小，从而减小了器件的深宽比，进而提高了提升耐压档位的可行性。所述DMOS器件中的源区和漏区均在同一表面引出，从而可以兼容CMOS器件的制造工艺。第二掺杂多晶硅层包括导电类型不同的第一子掺杂层和第二子掺杂层，由此，在N型栅极的情况下，P型掺杂层也能够直接连接栅极电位，提高了结型场板的功效。

Description

具有结型场板的DMOS器件及其制造方法
相关申请的交叉引用
本申请要求于2021年12月31日提交中国专利局，申请号为2021116820195，申请名称为“具有结型场板的DMOS器件及其制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体器件技术领域，特别涉及一种具有结型场板的DMOS器件及其制造方法。
背景技术
双扩散金属氧化物半导体(Double-diffused Metal-Oxide-Semiconductor，DMOS)器件是一种较典型且应用较为广泛的高压功率半导体器件。DMOS器件通过在源漏之间增加低掺杂的漂移区，使得电压绝大部分落在低掺杂漂移区上，从而提高了器件的耐压能力，使其可作为集成电路中的功率MOS器件。根据结构的不同，DMOS器件可分为横向(水平)双扩散MOS(Lateral Double-diffused MOS，LDMOS)和垂直(纵向)双扩散MOS(Vertical Double-diffused MOS，VDMOS)两种。
LDMOS器件是一种市场需求大、发展前景广的射频功率器件。在射频无线通信领域，基站和长距离发射机几乎全部使用硅基LDMOS器件；此外，LDMOS器件还广泛应用于射频放大器，如HF(High Frequency，高频)、VHF(Very High Frequency，甚高频)和UHF(Ultra High Frequency，超高频)通信系统、脉冲雷达、工业、科学和医疗应用、航空电子等领域。由于LDMOS器件具有高增益、高线性、高耐压、高输出功率和易与CMOS工艺兼容等优点，硅基LDMOS器件已成为射频半导体功率器件的一个新热点。
LDMOS器件的关键是实现高击穿电压(Breakdown Voltage，BV，亦称为耐压)和低导通电阻(Specific on-Resistance，Rdson)。现有技术中，只能通过增加漂移区尺寸来实现高击穿电压，这不仅使LDMOS器件的芯片面积 增加、成本增大；更为严重的是，器件的导通电阻Rdson与耐压BV的关系可以表示为：Rdson∝BV 2.5，即，增加漂移区尺寸会使得导通电阻增大，从而导致功耗急剧增加，且器件开关速度也随之降低。
因此，如何缓解耐压和导通电阻之间的矛盾，有效提高耐压或者降低导通电阻，成了本领域技术人员亟待解决的一个难题。
发明内容
本发明的目的在于提供一种具有结型场板的DMOS器件及其制造方法，以解决现有中的DMOS器件不能有效的提高耐压或者降低导通电阻的问题。
为解决上述技术问题，本发明提供一种具有结型场板的DMOS器件的制造方法，所述具有结型场板的DMOS器件的制造方法包括：
提供半导体基底，所述半导体基底中形成有第一沟槽；
在所述半导体基底上形成具有第一导电类型的第一掺杂多晶硅层，所述第一掺杂多晶硅层覆盖所述半导体基底和所述第一沟槽的表面；
对所述第一掺杂多晶硅层执行第一掺杂工艺和第二掺杂工艺，以在所述半导体基底的表面和所述第一沟槽的部分底面形成第二掺杂多晶硅层，所述第二掺杂多晶硅层包括具有第二导电类型的第一子掺杂层和位于所述第一子掺杂层上的具有第一导电类型的第二子掺杂层；
执行热处理工艺，以使得所述第一沟槽内的所述第二掺杂多晶硅层向所述第一沟槽的侧面延伸；
去除部分所述第二掺杂多晶硅层，露出所述第一沟槽的部分底面；
在所述第一沟槽的底部形成体区以及位于所述体区内的源区；
执行第三掺杂工艺，以在所述半导体基底的表面形成漏区并在所述第一掺杂多晶硅层的表面形成具有第二导电类型的第三子掺杂层，所述第一沟槽的侧面的所述第二掺杂多晶硅层、所述第一掺杂多晶硅层和所述第三子掺杂层作为结型场板，所述第一沟槽的侧面的所述第一子掺杂层作为栅极；以及
形成电连接所述源区的第一引出结构、电连接所述漏区和所述第三子掺杂层的第二引出结构和电连接所述栅极的第三引出结构。
可选的，在所述的具有结型场板的DMOS器件的制造方法中，所述提供半导体基底，所述半导体基底中形成有第一沟槽，包括：所述半导体基底中还形成有与所述第一沟槽连通的第二沟槽；
所述在所述半导体基底上形成具有第一导电类型的第一掺杂多晶硅层，所述第一掺杂多晶硅层覆盖所述半导体基底和所述第一沟槽的表面，包括：所述第一掺杂多晶硅层还覆盖所述第二沟槽的表面；
所述对所述第一掺杂多晶硅层执行第一掺杂工艺和第二掺杂工艺，以在所述半导体基底的表面和所述第一沟槽的部分底面形成第二掺杂多晶硅层，所述第二掺杂多晶硅层包括具有第二导电类型的第一子掺杂层和位于所述第一子掺杂层上的具有第一导电类型的第二子掺杂层，包括：还在所述第二沟槽的部分底面形成所述第二掺杂多晶硅层；
所述执行热处理工艺，以使得所述第一沟槽内的所述第二掺杂多晶硅层向所述第一沟槽的侧面延伸，包括：以使得所述第二沟槽内的所述第二掺杂多晶硅层向所述第二沟槽的侧面延伸；
在所述在所述第一沟槽的底部形成体区以及位于所述体区内的源区之后，在所述执行第三掺杂工艺，以在所述半导体基底的表面形成漏区并在所述第一掺杂多晶硅层的表面形成具有第二导电类型的第三子掺杂层，所述第一沟槽的侧面的所述第二掺杂多晶硅层、所述第一掺杂多晶硅层和所述第三子掺杂层作为结型场板，所述第一沟槽的侧面的所述第一子掺杂层作为栅极之前，还包括：去除所述第二沟槽的侧面的所述第一掺杂多晶硅层，所述第二沟槽内的所述第二掺杂多晶硅层作为栅极引出层，所述栅极引出层与所述栅极连接；以及
所述形成电连接所述源区的第一引出结构、电连接所述漏区和所述第三子掺杂层的第二引出结构和电连接所述栅极的第三引出结构，包括：所述第三引出结构通过与所述栅极引出层连接以实现与所述栅极电连接。
可选的，在所述的具有结型场板的DMOS器件的制造方法中，所述第一导电类型为P型，所述第二导电类型为N型，所述在所述半导体基底上形成具有第一导电类型的第一掺杂多晶硅层，包括：
在所述半导体基底上形成多晶硅层；以及
对所述多晶硅层执行P型掺杂工艺，以形成所述第一掺杂多晶硅层；
其中，所述第一掺杂多晶硅层的掺杂浓度为4E14atom/cm -3～1E16atom/cm -3，所述第一掺杂多晶硅层的厚度为0.15μm～0.35μm。
可选的，在所述的具有结型场板的DMOS器件的制造方法中，所述第一导电类型为P型，所述第二导电类型为N型，所述对所述第一掺杂多晶硅层执行第一掺杂工艺和第二掺杂工艺，包括：
所述第一掺杂工艺掺杂的是磷离子，掺杂浓度为1E17atom/cm -3～1E18atom/cm -3；所述第二掺杂工艺掺杂的是铟离子，掺杂浓度为1E20atom/cm -3～1E21atom/cm -3。
可选的，在所述的具有结型场板的DMOS器件的制造方法中，所述执行热处理工艺，以使得所述第一沟槽内的所述第二掺杂多晶硅层向所述第一沟槽的侧面延伸，还包括：
第一掺杂工艺的掺杂离子的扩散速度大于第二掺杂工艺的掺杂离子的扩散速度，以使得所述第一沟槽内的所述第一子掺杂层向所述第一沟槽的侧面的延伸长度较所述第二子掺杂层向所述第一沟槽的侧面的延伸长度长以及所述第二沟槽内的所述第一子掺杂层向所述第二沟槽的侧面的延伸长度较所述第二子掺杂层向所述第二沟槽的侧面的延伸长度长。
可选的，在所述的具有结型场板的DMOS器件的制造方法中，所述执行热处理工艺，以使得所述第一沟槽内的所述第二掺杂多晶硅层向所述第一沟槽的侧面延伸，还包括：
所述半导体基底表面的所述第二掺杂多晶硅层还覆盖所述第一沟槽的部分侧面和所述第二沟槽的部分侧面。
可选的，在所述的具有结型场板的DMOS器件的制造方法中，所述去除部分所述第二掺杂多晶硅层，露出所述第一沟槽的部分底面，包括：
形成第一图形化的光刻胶层，所述第一图形化的光刻胶层填充所述第二沟槽并延伸覆盖所述半导体基底上的一部分所述第二掺杂多晶硅层，暴露出 所述第一沟槽以及所述半导体基底上的另一部分所述第二掺杂多晶硅层；以及
对所述第一沟槽内的部分所述第二掺杂多晶硅层以及所述半导体基底上的暴露出的所述第二掺杂多晶硅层执行刻蚀工艺，以去除所述第一沟槽内的部分所述第二掺杂多晶硅层以及所述半导体基底上的暴露出的所述第二掺杂多晶硅层。
可选的，在所述的具有结型场板的DMOS器件的制造方法中，所述第一导电类型为P型，所述第二导电类型为N型，所述在所述第一沟槽的底部形成体区以及位于所述体区内的源区，包括：
对所述第一沟槽的底部的所述半导体基底执行P型掺杂工艺，以在所述第一沟槽的底部的所述半导体基底中形成所述体区；以及
对部分所述体区执行N型掺杂工艺，以在所述体区内形成所述源区。
可选的，在所述的具有结型场板的DMOS器件的制造方法中，所述去除所述第二沟槽的侧面的所述第一掺杂多晶硅层，所述第二沟槽内的所述第二掺杂多晶硅层作为栅极引出层，所述栅极引出层与所述栅极连接，包括：
在所述第一沟槽和所述第二沟槽内填充硬掩膜层，所述硬掩膜层延伸覆盖所述半导体基底表面的所述第二掺杂多晶硅层；
利用湿法或者干法刻蚀工艺去除部分所述硬掩膜层，以暴露出所述半导体基底表面的所述第二掺杂多晶硅层；
利用干法刻蚀工艺去除所述半导体基底表面的所述第二掺杂多晶硅层；
形成第二图形化的光刻胶层，所述第二图形化的光刻胶层覆盖所述第一沟槽内的所述硬掩膜层以及所述第一掺杂多晶硅层；以及
利用干法刻蚀工艺去除所述第二沟槽的侧面的所述第一掺杂多晶硅层。
本发明还提供一种具有结型场板的DMOS器件，所述具有结型场板的DMOS器件包括：
半导体基底，所述半导体基底中形成有第一沟槽；
形成于所述第一沟槽的侧壁上的第一掺杂多晶硅层以及第二掺杂多晶硅层，所述第二掺杂多晶硅层较所述第一掺杂多晶硅层靠近所述第一沟槽的底 部，所述第二掺杂多晶硅层包括第一子掺杂层和位于所述第一子掺杂层上的第二子掺杂层；形成于所述第一沟槽的侧壁上的第三子掺杂层，所述第三子掺杂层较所述第一掺杂多晶硅层靠近所述第一沟槽的顶部；所述第一沟槽内的所述第一子掺杂层作为栅极，所述第一沟槽内的所述第一掺杂多晶硅层、所述第二掺杂多晶硅层以及所述第三子掺杂层作为结型场板，其中，所述第一掺杂多晶硅层为第一导电类型，所述第一子掺杂层为第二导电类型，所述第二子掺杂层为第一导电类型，所述第三子掺杂层为第二导电类型；
形成于所述第一沟槽的底部的所述半导体基底中的体区以及位于所述体区内的源区；
形成于所述半导体基底表面的漏区；以及
电连接所述源区的第一引出结构、电连接所述漏区和所述第三子掺杂层的第二引出结构和电连接所述栅极的第三引出结构。
可选的，在所述的具有结型场板的DMOS器件中，所述半导体基底中还形成有与所述第一沟槽连通的第二沟槽，所述第二掺杂多晶硅层还覆盖所述第二沟槽的底面，所述第二沟槽内的所述第二掺杂多晶硅层作为栅极引出层，所述栅极引出层与所述栅极连接，所述第三引出结构通过与所述栅极引出层连接以实现与所述栅极电连接。
可选的，在所述的具有结型场板的DMOS器件中，所述第一沟槽内，从所述第一沟槽的底部向所述第一沟槽的槽口的方向，所述第二掺杂多晶硅层、所述第一掺杂多晶硅层以及所述第三子掺杂层依次相邻接触并覆盖于所述第一沟槽的侧面。
可选的，在所述的具有结型场板的DMOS器件中，所述第二子掺杂层位于所述第一子掺杂层内，在所述第一沟槽内，所述第一掺杂多晶硅层的底面和所述第一子掺杂层以及所述第二子掺杂层均相接。
可选的，在所述的具有结型场板的DMOS器件中，在第一方向上，所述第二沟槽与所述第一沟槽连通；在第二方向上，所述第二沟槽与所述第一沟槽相间隔，所述第一方向和所述第二方向相垂直。
可选的，在所述的具有结型场板的DMOS器件中，所述体区包围所述第 一沟槽的底部。
在本发明提供的具有结型场板的DMOS器件及其制造方法中，漏区在半导体基底的表面，而源区在第一沟槽的底部的半导体基底中，栅极在第一沟槽的底部位置，由此相对于LDMOS的横向耐压改为了纵向耐压，从而可以缩小整个器件的尺寸，降低导通电阻，极大的优化了耐压和导通电阻的矛盾关系。进一步的，所述DMOS器件中形成有结型场板结构，由此降低表面电阻(Resurf)的效果得到了提升，同时，由于结型场板结构的存在，DMOS器件中的沟槽深度可以减小，从而减小了器件的深宽比，进而提高了提升耐压档位的可行性。更进一步的，所述DMOS器件中的源区和漏区均在同一表面引出，从而可以兼容CMOS器件的制造工艺。此外，第二掺杂多晶硅层包括第一子掺杂层和位于所述第一子掺杂层上的第二子掺杂层，所述第一子掺杂层和所述第二子掺杂层分别为不同的导电类型，由此，在N型栅极的情况下，P型掺杂层也能够直接连接栅极电位，从而提高了结型场板的功效。
附图说明
图1～图11是执行本发明实施例的具有结型场板的DMOS器件的制造方法中所形成的器件的结构示意图；
图12是图11所述的具有结型场板的DMOS器件中第二掺杂多晶硅层的俯视示意图；
图13和图14是本发明实施例中结型场板的工作示意图。
其中，附图标记说明如下：
100-半导体基底；102-第一沟槽；104-第二沟槽；106-漂移区；108-第一硬掩膜层；110-第一掺杂多晶硅层；112-第二掺杂多晶硅层；114a-第一子掺杂层；114b-第二子掺杂层；116-第一图形化的光刻胶层；118-体区；120-源区；122a-栅极；122b-栅极引出层；124-第二硬掩膜层；126-第二图形化的光刻胶层；128-漏区；130-第三子掺杂层；132-结型场板；134-第一引出结构；136-第二引出结构；138-第三引出结构；140-第二介质层。
具体实施方式
为使本发明的目的、优点和特征更加清楚，以下结合附图和具体实施例对本发明提出的具有结型场板的DMOS器件及其制造方法作进一步详细说明。根据下面说明，本发明的优点和特征将更清楚。
需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。此外，附图所展示的结构往往是实际结构的一部分。特别的，各附图需要展示的侧重点不同，有时会采用不同的比例。
此外，在本发明的用语中，“第一”、“第二”等用语仅起到区分各结构/步骤的作用，并不说明这些结构/步骤之间有前后顺序关系。
本发明的核心思想在于，提供一种具有结型场板的DMOS器件及其制造方法，漏区在半导体基底的表面，而源区在第一沟槽的底部的半导体基底中，栅极在第一沟槽的底部位置，由此相对于LDMOS的横向耐压改为了纵向耐压，从而可以缩小整个器件的尺寸，降低导通电阻，极大的优化了耐压和导通电阻的矛盾关系。进一步的，所述DMOS器件中形成有结型场板结构，由此降低表面电阻(Resurf)的效果得到了提升，同时，由于结型场板结构的存在，DMOS器件中的沟槽深度可以减小，从而减小了器件的深宽比，进而提高了提升耐压档位的可行性。更进一步的，所述DMOS器件中的源区和漏区均在同一表面引出，从而可以兼容CMOS器件的制造工艺。此外，第二掺杂多晶硅层包括第一子掺杂层和位于所述第一子掺杂层上的第二子掺杂层，所述第一子掺杂层和所述第二子掺杂层分别为不同的导电类型，由此，在N型栅极的情况下，P型掺杂层也能够直接连接栅极电位，从而提高了结型场板的功效。
在本申请提供的具有结型场板的DMOS器件及其制造方法中，具体可以为N型DMOS器件，也可以为P型DMOS器件。在本申请具体实施例中，以N型DMOS器件为例作详细描述，根据对于N型DMOS器件的详细描述，本领域技术人员可以相应得到P型DMOS器件及其制造方法，本申请对此不再赘述。
请参考图1至图12，其为执行本发明实施例的具有结型场板的DMOS器件的制造方法中所形成的器件的结构示意图。
如图1所示，在本申请实施例中，首先，提供一半导体基底100，所述半导体基底100中形成有第一沟槽102和第二沟槽104。具体的，先提供一半导体基底100，接着，对所述半导体基底100执行掺杂工艺，以在所述半导体基底100中形成漂移区106，其中，所述漂移区106可采用已知的任何一种工艺形成。在本申请实施例中，接着，在所述半导体基底100的表面形成第一硬掩膜层108，所述第一硬掩膜层108具体可以为一叠层结构，例如，所述第一硬掩膜层108可以是一ONO(oxide-SIN-oxide，氧化层-氮化层-氧化层)的三层叠层结构。所述第一硬掩膜层108经过了图形化工艺，以暴露出部分的所述半导体基底100的表面。接着可通过对暴露出的所述半导体基底100执行刻蚀工艺，以形成所述第一沟槽102和所述第二沟槽104。所述第一沟槽102和所述第二沟槽104分别位于所述漂移区106的两侧，也即，所述漂移区106形成于所述第一沟槽102和所述第二沟槽104之间的所述半导体基底100中。进一步的，所述半导体基底100上形成有第一介质层(第一介质层在图1中未示出)，所述第一介质层覆盖所述半导体基底100、所述第一沟槽102和所述第二沟槽104的表面。所述第一介质层具体可以为氧化层、氮化层等。
接着，请参考图2，在所述半导体基底100上形成第一掺杂多晶硅层110，所述第一掺杂多晶硅层110覆盖所述半导体基底100的表面、所述第一沟槽102的表面和所述第二沟槽104的表面。具体的，在本申请实施例中，所述第一掺杂多晶硅层110覆盖所述第一硬掩膜层108的上表面、所述第一沟槽102的侧面和底面以及所述第二沟槽104的侧面和底面。即在本申请实施例中，所述第一掺杂多晶硅层110覆盖所述第一介质层。
优选的，所述第一掺杂多晶硅层110的厚度为0.15μm～0.35μm，例如，所述第一掺杂多晶硅层110的厚度可以为0.18μm、0.20μm、0.25μm、0.27μm或者0.33μm等。
在本申请实施例中，所述第一掺杂多晶硅层110具体可通过如下方式形成：在所述半导体基底100上形成多晶硅层(图2中未示出)，对所述多晶硅 层执行P型掺杂工艺，以形成所述第一掺杂多晶硅层110。优选的，所述第一掺杂多晶硅层的掺杂浓度为4E14atom/cm -3～1E16atom/cm -3，例如可以为8E14atom/cm -3、1E15atom/cm -3、5E15atom/cm -3或者9E15atom/cm -3等；所述掺杂离子例如可以为硼(B)等。
接着，如图3所示，对所述第一掺杂多晶硅层110执行N型掺杂工艺和P型掺杂工艺，以在所述半导体基底100的表面、所述第一沟槽102的部分底面和所述第二沟槽104的部分底面形成第二掺杂多晶硅层112，所述第二掺杂多晶硅层112包括第一子掺杂层114a和位于所述第一子掺杂层114a上的第二子掺杂层114b。相应的，所述第一子掺杂层114a为N型，所述第二子掺杂层114b为P型。进一步的，相对于所述第一掺杂多晶硅层110，所述第二子掺杂层114b为重掺杂，即所述第一掺杂多晶硅层110为轻掺杂P型导电层，所述第二子掺杂层114b为重掺杂P型导电层。在本申请实施例中，可以采用普遍注入工艺对整个半导体基底100执行掺杂，由此可以降低工艺成本。其中，在所述第一沟槽102底部并且覆盖所述第一沟槽102侧面的所述第一掺杂多晶硅层110以及在所述第二沟槽104底部并且覆盖所述第二沟槽104侧面的所述第一掺杂多晶硅层110由于其上的第一掺杂多晶硅层110的阻挡作用，在对所述第一掺杂多晶硅层110执行N型掺杂工艺和P型掺杂工艺中，通常保持为所述第一掺杂多晶硅层110。
优选的，N型掺杂离子为磷离子，掺杂浓度为1E17atom/cm -3～1E18atom/cm -3，例如，掺杂浓度为2E17atom/cm -3、4E17atom/cm -3、5E17atom/cm -3或者7E17atom/cm -3等。P型掺杂离子为铟离子，掺杂浓度为1E20atom/cm -3～1E21atom/cm -3，例如，掺杂浓度为2E20atom/cm -3、3E20atom/cm -3、5E20atom/cm -3或者8E20atom/cm -3等。即在此，形成了重掺杂的第二子掺杂层114b。
接着，如图4所示，对所述第二掺杂多晶硅层112执行热处理工艺，所述第一沟槽102的底面和所述第二沟槽104的底面的所述第二掺杂多晶硅层112中的掺杂离子向所述第一掺杂多晶硅层110中扩散，以使得所述第一沟槽102的底面的所述第二掺杂多晶硅层112向所述第一沟槽102的侧面延伸，以 及所述第二沟槽104的底面的所述第二掺杂多晶硅层112向所述第二沟槽104的侧面延伸。在本申请的实施例中，热处理工艺为退火工艺。在本申请的其他实施例中，热处理工艺也可以为其他高温处理工艺。
在本申请实施例中，N型掺杂离子的扩散速度较P型掺杂离子的扩散速度快，以使得所述第一沟槽102内的所述第一子掺杂层114a向所述第一沟槽102的侧面的延伸长度较所述第二子掺杂层114b向所述第一沟槽102的侧面的延伸长度长以及所述第二沟槽104内的所述第一子掺杂层114a向所述第二沟槽104的侧面的延伸长度较所述第二子掺杂层114b向所述第二沟槽104的侧面的延伸长度长。在本申请的其他实施例中，执行热处理工艺后，也可以是所述第一沟槽102内的所述第二子掺杂层114b的底壁及侧壁均被所述第一子掺杂层114a包围，所述第二沟槽104内的所述第二子掺杂层114b的底壁及侧壁均被所述第一子掺杂层114a包围。
其中，在本申请的用语中，用语“底壁”和用语“底面”等同，用语“侧壁”和用语“侧面”等同，盖因用语“表面”通常仅为此一种表达方式，而用语“底壁”和用语“底面”、用语“侧壁”和用语“侧面”通常均被混用，故而在本申请的用语中亦沿用了这一表达方式。
进一步的，所述第一沟槽102内的所述第一子掺杂层114a延伸至所述第一沟槽102的侧面，从而使得所述第一子掺杂层114a覆盖所述第一沟槽102的整个底面；所述第一沟槽102内的所述第二子掺杂层114b向所述第一沟槽102的侧面延伸但并不与所述第一沟槽102的侧面相接，从而使得所述第二子掺杂层114b位于所述第一子掺杂层114a内。
相应的，在本申请实施例中，所述第二沟槽104内的所述第一子掺杂层114a延伸至所述第二沟槽104的侧面，从而使得所述第一子掺杂层114a覆盖所述第二沟槽104的整个底面；所述第二沟槽104内的所述第二子掺杂层114b向所述第二沟槽104的侧面延伸但并不与所述第二沟槽104的侧面相接，从而使得所述第二子掺杂层114b位于所述第一子掺杂层114a内。
请继续参考图4，在本申请实施例中，在对所述第二掺杂多晶硅层112执行热处理工艺中，所述半导体基底100表面(在此具体为所述第一硬掩膜层 108的表面)的所述第二掺杂多晶硅层112中的掺杂离子向所述第一掺杂多晶硅层110中扩散，以使得所述半导体基底100表面的所述第二掺杂多晶硅层112向所述第一沟槽102的侧面和所述第二沟槽104的侧面延伸，并覆盖所述第一沟槽102的部分侧面和所述第二沟槽104的部分侧面。即所述半导体基底100表面的所述第二掺杂多晶硅层112延伸覆盖了所述第一沟槽102顶部(侧面)和所述第二沟槽104顶部(侧面)。
具体的，在本申请实施例中，覆盖所述半导体基底100的上表面的所述第二掺杂多晶硅层112中的所述第一子掺杂层114a向所述第一沟槽102的侧面和所述第二沟槽104的侧面延伸，并覆盖所述第一沟槽102靠近顶部的部分侧面以及所述第二沟槽104靠近顶部的部分侧面。
接着，如图5所示，去除所述第一沟槽102的底面的部分所述第二掺杂多晶硅层112。保留所述第一沟槽102底面上靠近所述第一沟槽102侧面的所述第二掺杂多晶硅层112，其中，保留的(剩余的)所述第一子掺杂层114a作为栅极122a。在本申请的实施例中，所述栅极还包括保留的(剩余的)所述第一子掺杂层114a与所述第一沟槽102表面之间的第一介质层(第一介质层在图5中未示出)。
需说明的是，从图5开始，所述第一沟槽102内的所述第一掺杂层114a作为了所述栅极122a，即，如果附图中同时出现了附图标记114a和附图标记122a，两者可能指向了同一结构；同时，在下文中，由于表达的需要，所述第一沟槽102内的所述第一掺杂层114a以及所述栅极122a可能会同时出现，均为实现不同的说明所需要。
请继续参考图5，在本申请实施例中，去除所述第一沟槽102的底面的部分所述第二掺杂多晶硅层112包括：形成第一图形化的光刻胶层116，所述第一图形化的光刻胶层116填充所述第二沟槽104并延伸覆盖所述半导体基底100上的一部分所述第二掺杂多晶硅层112(即覆盖靠近所述第二沟槽104的部分所述第二掺杂多晶硅层112)，暴露出所述第一沟槽102以及所述半导体基底100上的另一部分所述第二掺杂多晶硅层112(即暴露出靠近所述第一沟槽102的部分所述第二掺杂多晶硅层112)；对暴露出的所述第一沟槽102的 底面的所述第二掺杂多晶硅层112(在此，所述第一沟槽102底面上靠近所述第一沟槽102侧面的所述第二掺杂多晶硅层112，由于其上覆盖有第一掺杂多晶硅层110(可相应参考图5)，故而未被暴露出)以及暴露出的所述半导体基底100上的所述第二掺杂多晶硅层112执行刻蚀工艺，以去除所述第一沟槽102的底面的部分所述第二掺杂多晶硅层112以及所述半导体基底100上的部分所述第二掺杂多晶硅层112。
在此，可以采用干法刻蚀工艺去除所述第一沟槽102的底面的部分所述第二掺杂多晶硅层112以及所述半导体基底100上的部分所述第二掺杂多晶硅层112，从而暴露出所述第一沟槽100底部的所述半导体基底100以及所述第一沟槽100内的所述第一掺杂多晶硅层110的上表面。在本申请的其他实施例中，也可以是，对暴露出的所述第一沟槽102的底面的所述第二掺杂多晶硅层112以及暴露出的所述半导体基底100上的所述第二掺杂多晶硅层112执行刻蚀工艺后，露出所述第一沟槽102的槽口边缘的所述第一硬掩膜层108和所述第一沟槽102的部分底面的半导体基底100，并保留所述第一沟槽102的侧面的第一掺杂多晶硅层110和所述第一沟槽102的侧面的所述第二掺杂多晶硅层112。所述第一沟槽102的侧面的所述第二掺杂多晶硅层112可以是位于所述第一沟槽102的侧面的，且位于第一掺杂多晶硅层110上部和下部的所述第二掺杂多晶硅层112(位于所述第一沟槽102的侧面的，且位于第一掺杂多晶硅层110上部的所述第二掺杂多晶硅层112在图5中未示出)；所述第一沟槽102的侧面的所述第二掺杂多晶硅层112也可以是位于所述第一沟槽102的侧面的，且仅位于第一掺杂多晶硅层110下部的所述第二掺杂多晶硅层112。
接着，如图6所示，在所述第一沟槽102的底部的所述半导体基底100中形成体区118以及位于所述体区118内的源区120。具体的，首先可以对所述第一沟槽102的底部的所述半导体基底100执行P型掺杂工艺，以在所述第一沟槽102的底部的所述半导体基底100中形成所述体区118。所述体区118可以仅与所述第一沟槽102的底面相邻接触；所述体区118也可以包围所述第一沟槽102的底部，也即所述体区118既与所述第一沟槽102的底面相 邻接触又与所述第一沟槽102的部分侧面相邻接触。接着，对部分所述体区118执行N型掺杂工艺，以在所述体区118内形成所述源区120。在本申请实施例中，所述第一子掺杂层114a与所述源区120相接，即所述源区120延伸至所述第一子掺杂层114a正下方从而与所述第一子掺杂层114a相接。在执行N型掺杂工艺形成所述源区120的同时，所述第一沟槽102内的所述第一掺杂多晶硅层110的上表面也会被掺杂N型离子。在本申请实施例中，形成所述体区118和源区120之后，去除所述第一图形化的光刻胶层116。
在本申请实施例中，接着，如图8所示，去除所述第二沟槽104的侧面的所述第一掺杂多晶硅层110，所述第二沟槽104的底部的所述第二掺杂多晶硅层112作为栅极引出层122b。
需说明的是，从图8开始，所述第二沟槽104内的所述第二掺杂多晶硅层112作为所述栅极引出层122b，即，如果附图中同时出现了附图标记112和附图标记122b，两者可能指向了同一结构；同时，在下文中，由于表达的需要，所述第二沟槽104内的所述第二掺杂多晶硅层112以及所述栅极引出层122b可能会同时出现，均为实现不同的说明所需要。
具体的，首先，如图7所示，在所述第一沟槽102和所述第二沟槽104内填充第二硬掩膜层124(为了与之前的第一硬掩膜层108相区别，在此称为第二硬掩膜层124)，所述第二硬掩膜层124延伸覆盖所述半导体基底100表面的所述第二掺杂多晶硅层112。在此，所述第二硬掩膜层124的材质为氧化层-氮化层-氧化层的叠层结构。在本申请实施例中，在去除所述第一沟槽102的底面的部分所述第二掺杂多晶硅层112的过程中，还去除了所述半导体基底100上的部分所述第二掺杂多晶硅层112并暴露出了部分所述第一硬掩膜层108，因而在此，所述第二硬掩膜层124还覆盖暴露出的部分所述第一硬掩膜层108。
接着，如图8所示，利用湿法或者干法刻蚀工艺去除部分所述第二硬掩膜层124，以暴露出所述半导体基底100表面的所述第二掺杂多晶硅层112。即在此，去除所述半导体基底100表面的所述第二硬掩膜层124，保留所述第一沟槽102和所述第二沟槽104内的所述第二硬掩膜层124，从而暴露出所述 半导体基底100表面的所述第二掺杂多晶硅层112。
请继续参考图8，接着，利用干法刻蚀工艺去除所述半导体基底100表面的所述第二掺杂多晶硅层112。在此，暴露出所述半导体基底100表面的所述第一硬掩膜层108。在本申请实施例中，去除所述半导体基底100表面的所述第二掺杂多晶硅层112之后，还暴露出了所述第二沟槽104内的所述第一掺杂多晶硅层110和所述第二沟槽104内的所述第二硬掩膜层124。在本申请的其他实施例中，对于在执行刻蚀工艺得到图5所示结构中，在所述第一沟槽102侧壁且位于第一掺杂多晶硅层110上部保留有所述第二掺杂多晶硅层112的情形，利用干法刻蚀工艺去除所述半导体基底100表面的所述第二掺杂多晶硅层112后，则暴露出的是位于所述第一沟槽102的侧面的，且位于第一掺杂多晶硅层110上部的所述第二掺杂多晶硅层112(位于所述第一沟槽102的侧面的，且位于第一掺杂多晶硅层110上部的所述第二掺杂多晶硅层112在图8中未示出)和所述第一沟槽102内的所述第二硬掩膜层124。
接着，继续参考图8，形成第二图形化的光刻胶层126，所述第二图形化的光刻胶层126覆盖所述第一沟槽102，露出所述半导体基底100表面的所述第一硬掩膜层108和所述第二沟槽104。在本申请实施例中，所述第二图形化的光刻胶层126覆盖所述第一沟槽102内的所述第二硬掩膜层124以及所述第一掺杂多晶硅层110。在本申请的其他实施例中，也可以是所述第二图形化的光刻胶层126覆盖所述第一沟槽102内的所述第二硬掩膜层124以及位于所述第一沟槽102的侧面的，且位于第一掺杂多晶硅层110上部的所述第二掺杂多晶硅层112。接着，利用干法刻蚀工艺去除所述第二沟槽104的侧面的所述第一掺杂多晶硅层110，保留所述第二沟槽104的底部的所述第二掺杂多晶硅层112，所述第二沟槽104内保留的所述第二掺杂多晶硅层112作为所述栅极引出层122b。在本申请实施例中，形成所述栅极引出层122b之后，去除所述第二图形化的光刻胶层126。
在本申请实施例中，通过所述栅极引出层122b可以便于所述栅极122a的引出，从而简化工艺，提高所述DMOS器件的质量与可靠性。在本申请的其他实施例中，也可以不制作所述栅极引出层122b，则相应的，无需形成所 述第二沟槽104，更无需在其中形成第一掺杂多晶硅层110、第二掺杂多晶硅层112等。
请参考图9，在本申请实施例中，进一步的，还包括在所述第二沟槽104内再次填充第二硬掩膜层124，以填满所述第二沟槽104。接着，对所述半导体基底100执行化学机械研磨(CMP)工艺，以去除所述第二图形化的光刻胶层126和所述半导体基底100表面的所述第一硬掩膜层108，暴露出所述半导体基底100以及所述第一掺杂多晶硅层110的上表面。在本申请的其他实施例中，暴露出的也可以是所述半导体基底100以及所述第一沟槽102内的位于第一掺杂多晶硅层110上部的所述第二掺杂多晶硅层112(位于所述第一沟槽102的侧面的，且位于第一掺杂多晶硅层110上部的所述第二掺杂多晶硅层112在图9中未示出)。其中，所述第二图形化的光刻胶层126和所述第一硬掩膜层108也可以通过两步工艺分别去除，例如，可以先通过剥离工艺去除所述第二图形化的光刻胶层126，再通过化学机械研磨工艺去除所述第一硬掩膜层108。
接着请参考图10，对所述半导体基底100和所述第一掺杂多晶硅层110执行掺杂工艺，以在所述半导体基底100的表面形成漏区128并在所述第一掺杂多晶硅层110的表面形成第三子掺杂层130，从而在所述第一沟槽102的侧面形成结型场板132。也即，所述第一沟槽102的底部侧面的所述第一子掺杂层114a既作为器件栅极，又与所述第一沟槽102的侧面的所述第二子掺杂层114b、所述第一掺杂多晶硅层110和所述第三子掺杂层130组合作为结型场板132。其中，所述漏区128位于所述第一沟槽102和所述第二沟槽104之间的所述半导体基底100中。
如图11所示，接着，形成电连接所述源区120的第一引出结构134、电连接所述漏区128的第二引出结构136和电连接所述栅极引出层122b的第三引出结构138，其中，所述第二引出结构136还电连接所述第三子掺杂层130。在本申请实施例中，所述第三引出结构138通过与所述栅极引出层122b连接以实现与所述栅极122a电连接。具体的，可以形成一第二介质层140，所述第二介质层140覆盖所述半导体基底100以及所述第二硬掩膜层124；接着， 对所述第二介质层140以及所述第二硬掩膜层124执行刻蚀工艺，以形成暴露出所述源区120的第一开口(图11中未示出)、暴露出所述漏区128和第三子掺杂层130的第二开口(图11中未示出)以及暴露出所述栅极引出层122b的第三开口(图11中未示出)；接着，在所述第一开口、第二开口以及第三开口中填充导电层，从而形成所述第一引出结构134、第二引出结构136以及第三引出结构138。进一步的，所述第一开口、所述第二开口和所述第三开口可以通过不同的刻蚀步骤形成，例如，所述第二开口可以通过浅孔刻蚀步骤形成，所述第一开口和所述第三开口可以通过深孔刻蚀步骤形成。
请继续参考图11，相应的，本申请实施例还提供了一种具有结型场板的DMOS器件，具体的，所述具有结型场板的DMOS器件包括：半导体基底100，所述半导体基底100中形成有第一沟槽102；形成于所述第一沟槽102的侧壁上的第一掺杂多晶硅层110以及第二掺杂多晶硅层112，所述第二掺杂多晶硅层112较所述第一掺杂多晶硅层110靠近所述第一沟槽102的底部，所述第二掺杂多晶硅层112包括第一子掺杂层114a和位于所述第一子掺杂层114a上的第二子掺杂层114b；形成于所述第一沟槽102的侧壁上的第三子掺杂层130，所述第三子掺杂层130较所述第一掺杂多晶硅层110靠近所述第一沟槽102的顶部；所述第一沟槽102内的所述第一子掺杂层114a作为栅极122a，所述第一沟槽102内的所述第一掺杂多晶硅层110、所述第二掺杂多晶硅层112以及所述第三子掺杂层130构成结型场板132，其中，所述第一掺杂多晶硅层110为P型，所述第一子掺杂层114a为N型，所述第二子掺杂层114b为P型，所述第三子掺杂层130为N型；形成于所述第一沟槽102的底部的所述半导体基底100中的体区118以及位于所述体区118内的源区120；形成于所述半导体基底100表面的漏区128；以及电连接所述源区120的第一引出结构134、电连接所述漏区128的第二引出结构136和电连接所述栅极122a的第三引出结构138，其中，所述第二引出结构136还电连接所述第三子掺杂层130。
本申请的其他实施例中，从所述第一沟槽102的底部向所述第一沟槽102的槽口的方向，依次相邻接触并覆盖于所述第一沟槽102的侧面的所述第二 掺杂多晶硅层112、所述第一掺杂多晶硅层110以及所述第三子掺杂层130构成结型场板132。
本申请的其他实施例中，进一步的，所述具有结型场板的DMOS器件还包括与所述第一沟槽102连通的第二沟槽104。相应的，请参考图12，其为图11所述的具有结型场板的DMOS器件沿AA’线的剖面俯视示意图，如图12所示，在本申请实施例中，在第一方向X上，所述第二沟槽104与所述第一沟槽102连通；在第二方向Y上，所述第二沟槽104与所述第一沟槽102相间隔，所述第一方向X与所述第二方向Y相垂直。即，所述第一沟槽102和所述第二沟槽104组成了类似“日”字型沟槽。所述第二掺杂多晶硅层112还覆盖所述第二沟槽104的底面，所述第二沟槽104内的所述第二掺杂多晶硅层112作为栅极引出层122b，所述栅极引出层122b与所述栅极122a连接，所述第三引出结构138通过与所述栅极引出层122b直接连接以实现与所述栅极122a电连接。
在本申请实施例中，所述第二子掺杂层114b位于所述第一子掺杂层114a内，在所述第一沟槽102内，所述第一掺杂多晶硅层110的底面和所述第一子掺杂层114a以及所述第二子掺杂层114b均相接。
进一步的，所述具有结型场板的DMOS器件还包括：形成于所述第一沟槽102和所述第二沟槽104之间的所述半导体基底100中的漂移区106。所述漏区128位于所述第一沟槽102和所述第二沟槽104之间的所述半导体基底100中。更进一步的，所述漏区128位于所述漂移区106内。在此，所述第一沟槽102、所述漂移区106和所述第二沟槽104沿着所述第二方向Y排布。
优选的，所述第一掺杂多晶硅层110为掺杂的多晶硅层并且掺杂浓度为4E14atom/cm -3～1E16atom/cm -3，所述第一掺杂多晶硅层110的厚度为0.15μm～0.35μm。所述第一子掺杂层114a为掺杂的多晶硅层并且掺杂离子为磷离子以及掺杂浓度为1E17atom/cm -3～1E18atom/cm -3；所述第二子掺杂层114b为掺杂的多晶硅层并且掺杂离子为铟离子以及掺杂浓度为1E20atom/cm -3～1E21atom/cm -3。
综上所述，在本发明提供的具有结型场板的DMOS器件及其制造方法中， 漏区128在半导体基底100的表面，而源区120在第一沟槽102的底部的半导体基底100中，栅极122a在第一沟槽102的底部，由此相对于LDMOS的横向耐压改为了纵向耐压，从而可以缩小整个器件的尺寸，降低导通电阻，极大的优化了耐压和导通电阻的关系。进一步的，所述DMOS器件中形成有结型场板132，由此降低表面电阻(Resurf)的效果得到了提升，同时，由于结型场板132的存在，DMOS器件中的沟槽深度可以减小，从而减小了器件沟槽的深宽比，进而提高了提升耐压档位的可行性。也即，无需提高沟槽的深宽比就能实现DMOS器件的耐压档位的进一步提升，也不用会损失器件电流能力。更进一步的，所述DMOS器件中的源区120和漏区128均在同一表面引出，从而可以兼容CMOS器件的制造工艺。此外，第二掺杂多晶硅层112包括第一子掺杂层114a和位于所述第一子掺杂层114a上的第二子掺杂层114b，所述第一子掺杂层114a和所述第二子掺杂层114b的导电类型不同，由此，在N型栅极的情况下，P型掺杂层也能够直接连接栅极122电位，从而提高了结型场板132的功效。
进一步的，在此通过所述第二沟槽104与所述第一沟槽102在侧面设有连通沟槽，使得所述第二沟槽104内的第一子掺杂层114a和第二子掺杂层114b与所述第一沟槽102内的第一子掺杂层114a和第二子掺杂层114b电连接。这就使得栅极电压通过所述第三引出结构138添加至所述第二沟槽104内的第一子掺杂层114a和第二子掺杂层114b后，栅极电压可以通过所述第二沟槽104内第二子掺杂层114b和第一沟槽102内第二子掺杂层114b直接添加至第一沟槽102内的第一掺杂多晶硅层110。也即向第一沟槽102内的栅极结构添加栅极电压的同时，也直接对第一沟槽102内的第一掺杂多晶硅层110添加栅极电压，无需额外通过击穿PN结向第一沟槽102内的第一掺杂多晶硅层110传导栅极电压。由此，在N型栅极的情况下，P型掺杂层也能够直接连接栅极电位，从而提高了栅极的开关能力以及结型场板的功效。在本申请实施例中，图12的俯视示意图中，在所述半导体基底100所在平面内，所述第一沟槽102和所述第二沟槽104组成类似“日”字型沟槽。在本申请的其他实施例中，图12的俯视示意图中，在所述半导体基底100所在平面内，所 述第一沟槽102和所述第二沟槽104也可以组成梳状型结构，梳状型结构包括梳齿部和连接所述梳齿部的梳柄部。
进一步的，请参考图13和图14，其为本发明实施例中结型场板的工作示意图。如图13所示，当栅极电压大于阈值电压时，(结型场板132中的)第一掺杂多晶硅层110会有正电荷，从而使得漂移区106会积累更多的电子，漂移区106电阻下降，从而使得电流能力得到了提升。如图14所示，当栅极电压等于0并且漏区电压大于0时，漏区128发生PN结反偏，而通过(结型场板132中的)第一掺杂多晶硅层110中的电势线可以调整漂移区106的电势线，让漂移区106的电势线能够更加均匀的分部在漂移区106，从而达到增加耐压的效果。
上述描述仅是对本发明较佳实施例的描述，并非对本发明范围的任何限定，本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰，均属于权利要求书的保护范围。

Claims (15)

  1. 一种具有结型场板的DMOS器件的制造方法，其特征在于，所述具有结型场板的DMOS器件的制造方法包括：
    提供半导体基底，所述半导体基底中形成有第一沟槽；
    在所述半导体基底上形成具有第一导电类型的第一掺杂多晶硅层，所述第一掺杂多晶硅层覆盖所述半导体基底和所述第一沟槽的表面；
    对所述第一掺杂多晶硅层执行第一掺杂工艺和第二掺杂工艺，以在所述半导体基底的表面和所述第一沟槽的部分底面形成第二掺杂多晶硅层，所述第二掺杂多晶硅层包括具有第二导电类型的第一子掺杂层和位于所述第一子掺杂层上的具有第一导电类型的第二子掺杂层；
    执行热处理工艺，以使得所述第一沟槽内的所述第二掺杂多晶硅层向所述第一沟槽的侧面延伸；
    去除部分所述第二掺杂多晶硅层，露出所述第一沟槽的部分底面；
    在所述第一沟槽的底部形成体区以及位于所述体区内的源区；
    执行第三掺杂工艺，以在所述半导体基底的表面形成漏区并在所述第一掺杂多晶硅层的表面形成具有第二导电类型的第三子掺杂层，所述第一沟槽的侧面的所述第二掺杂多晶硅层、所述第一掺杂多晶硅层和所述第三子掺杂层作为结型场板，所述第一沟槽的侧面的所述第一子掺杂层作为栅极；以及
    形成电连接所述源区的第一引出结构、电连接所述漏区和所述第三子掺杂层的第二引出结构和电连接所述栅极的第三引出结构。
  2. 如权利要求1所述的具有结型场板的DMOS器件的制造方法，其特征在于，所述提供半导体基底，所述半导体基底中形成有第一沟槽，包括：所述半导体基底中还形成有与所述第一沟槽连通的第二沟槽；
    所述在所述半导体基底上形成具有第一导电类型的第一掺杂多晶硅层，所述第一掺杂多晶硅层覆盖所述半导体基底和所述第一沟槽的表面，包括：所述第一掺杂多晶硅层还覆盖所述第二沟槽的表面；
    所述对所述第一掺杂多晶硅层执行第一掺杂工艺和第二掺杂工艺，以在 所述半导体基底的表面和所述第一沟槽的部分底面形成第二掺杂多晶硅层，所述第二掺杂多晶硅层包括具有第二导电类型的第一子掺杂层和位于所述第一子掺杂层上的具有第一导电类型的第二子掺杂层，包括：还在所述第二沟槽的部分底面形成所述第二掺杂多晶硅层；
    所述执行热处理工艺，以使得所述第一沟槽内的所述第二掺杂多晶硅层向所述第一沟槽的侧面延伸，包括：以使得所述第二沟槽内的所述第二掺杂多晶硅层向所述第二沟槽的侧面延伸；
    在所述在所述第一沟槽的底部形成体区以及位于所述体区内的源区之后，在所述执行第三掺杂工艺，以在所述半导体基底的表面形成漏区并在所述第一掺杂多晶硅层的表面形成具有第二导电类型的第三子掺杂层，所述第一沟槽的侧面的所述第二掺杂多晶硅层、所述第一掺杂多晶硅层和所述第三子掺杂层作为结型场板，所述第一沟槽的侧面的所述第一子掺杂层作为栅极之前，还包括：去除所述第二沟槽的侧面的所述第一掺杂多晶硅层，所述第二沟槽内的所述第二掺杂多晶硅层作为栅极引出层，所述栅极引出层与所述栅极连接；以及
    所述形成电连接所述源区的第一引出结构、电连接所述漏区和所述第三子掺杂层的第二引出结构和电连接所述栅极的第三引出结构，包括：所述第三引出结构通过与所述栅极引出层连接以实现与所述栅极电连接。
  3. 如权利要求1或2所述的具有结型场板的DMOS器件的制造方法，其特征在于，所述第一导电类型为P型，所述第二导电类型为N型，所述在所述半导体基底上形成具有第一导电类型的第一掺杂多晶硅层，包括：
    在所述半导体基底上形成多晶硅层；以及
    对所述多晶硅层执行P型掺杂工艺，以形成所述第一掺杂多晶硅层；
    其中，所述第一掺杂多晶硅层的掺杂浓度为4E14atom/cm -3～1E16atom/cm -3，所述第一掺杂多晶硅层的厚度为0.15μm～0.35μm。
  4. 如权利要求1或2所述的具有结型场板的DMOS器件的制造方法，其特征在于，所述第一导电类型为P型，所述第二导电类型为N型，所述对所 述第一掺杂多晶硅层执行第一掺杂工艺和第二掺杂工艺，包括：
    所述第一掺杂工艺掺杂的是磷离子，掺杂浓度为1E17atom/cm -3～1E18atom/cm -3；所述第二掺杂工艺掺杂的是铟离子，掺杂浓度为1E20atom/cm -3～1E21atom/cm -3。
  5. 如权利要求2所述的具有结型场板的DMOS器件的制造方法，其特征在于，所述执行热处理工艺，以使得所述第一沟槽内的所述第二掺杂多晶硅层向所述第一沟槽的侧面延伸，还包括：
    第一掺杂工艺的掺杂离子的扩散速度大于第二掺杂工艺的掺杂离子的扩散速度，以使得所述第一沟槽内的所述第一子掺杂层向所述第一沟槽的侧面的延伸长度较所述第二子掺杂层向所述第一沟槽的侧面的延伸长度长以及所述第二沟槽内的所述第一子掺杂层向所述第二沟槽的侧面的延伸长度较所述第二子掺杂层向所述第二沟槽的侧面的延伸长度长。
  6. 如权利要求2所述的具有结型场板的DMOS器件的制造方法，其特征在于，所述执行热处理工艺，以使得所述第一沟槽内的所述第二掺杂多晶硅层向所述第一沟槽的侧面延伸，还包括：
    所述半导体基底表面的所述第二掺杂多晶硅层还覆盖所述第一沟槽的部分侧面和所述第二沟槽的部分侧面。
  7. 如权利要求2所述的具有结型场板的DMOS器件的制造方法，其特征在于，所述去除部分所述第二掺杂多晶硅层，露出所述第一沟槽的部分底面，包括：
    形成第一图形化的光刻胶层，所述第一图形化的光刻胶层填充所述第二沟槽并延伸覆盖所述半导体基底上的一部分所述第二掺杂多晶硅层，暴露出所述第一沟槽以及所述半导体基底上的另一部分所述第二掺杂多晶硅层；以及
    对所述第一沟槽内的部分所述第二掺杂多晶硅层以及所述半导体基底上的暴露出的所述第二掺杂多晶硅层执行刻蚀工艺，以去除所述第一沟槽内的部分所述第二掺杂多晶硅层以及所述半导体基底上的暴露出的所述第二掺杂多晶硅层。
  8. 如权利要求1或2所述的具有结型场板的DMOS器件的制造方法，其特征在于，所述第一导电类型为P型，所述第二导电类型为N型，所述在所述第一沟槽的底部形成体区以及位于所述体区内的源区，包括：
    对所述第一沟槽的底部的所述半导体基底执行P型掺杂工艺，以在所述第一沟槽的底部的所述半导体基底中形成所述体区；以及
    对部分所述体区执行N型掺杂工艺，以在所述体区内形成所述源区。
  9. 如权利要求2所述的具有结型场板的DMOS器件的制造方法，其特征在于，所述去除所述第二沟槽的侧面的所述第一掺杂多晶硅层，所述第二沟槽内的所述第二掺杂多晶硅层作为栅极引出层，所述栅极引出层与所述栅极连接，包括：
    在所述第一沟槽和所述第二沟槽内填充硬掩膜层，所述硬掩膜层延伸覆盖所述半导体基底表面的所述第二掺杂多晶硅层；
    利用湿法或者干法刻蚀工艺去除部分所述硬掩膜层，以暴露出所述半导体基底表面的所述第二掺杂多晶硅层；
    利用干法刻蚀工艺去除所述半导体基底表面的所述第二掺杂多晶硅层；
    形成第二图形化的光刻胶层，所述第二图形化的光刻胶层覆盖所述第一沟槽内的所述硬掩膜层以及所述第一掺杂多晶硅层；以及
    利用干法刻蚀工艺去除所述第二沟槽的侧面的所述第一掺杂多晶硅层。
  10. 一种具有结型场板的DMOS器件，其特征在于，所述具有结型场板的DMOS器件包括：
    半导体基底，所述半导体基底中形成有第一沟槽；
    形成于所述第一沟槽的侧壁上的第一掺杂多晶硅层以及第二掺杂多晶硅层，所述第二掺杂多晶硅层较所述第一掺杂多晶硅层靠近所述第一沟槽的底部，所述第二掺杂多晶硅层包括第一子掺杂层和位于所述第一子掺杂层上的第二子掺杂层；形成于所述第一沟槽的侧壁上的第三子掺杂层，所述第三子掺杂层较所述第一掺杂多晶硅层靠近所述第一沟槽的顶部；所述第一沟槽内的所述第一子掺杂层作为栅极，所述第一沟槽内的所述第一掺杂多晶硅层、所述第二掺杂多晶硅层以及所述第三子掺杂层作为结型场板，其中，所述第 一掺杂多晶硅层为第一导电类型，所述第一子掺杂层为第二导电类型，所述第二子掺杂层为第一导电类型，所述第三子掺杂层为第二导电类型；
    形成于所述第一沟槽的底部的所述半导体基底中的体区以及位于所述体区内的源区；
    形成于所述半导体基底表面的漏区；以及
    电连接所述源区的第一引出结构、电连接所述漏区和所述第三子掺杂层的第二引出结构和电连接所述栅极的第三引出结构。
  11. 如权利要求10所述的具有结型场板的DMOS器件，其特征在于，所述半导体基底中还形成有与所述第一沟槽连通的第二沟槽，所述第二掺杂多晶硅层还覆盖所述第二沟槽的底面，所述第二沟槽内的所述第二掺杂多晶硅层作为栅极引出层，所述栅极引出层与所述栅极连接，所述第三引出结构通过与所述栅极引出层连接以实现与所述栅极电连接。
  12. 如权利要求10或11所述的具有结型场板的DMOS器件，其特征在于，所述第一沟槽内，从所述第一沟槽的底部向所述第一沟槽的槽口的方向，所述第二掺杂多晶硅层、所述第一掺杂多晶硅层以及所述第三子掺杂层依次相邻接触并覆盖于所述第一沟槽的侧面。
  13. 如权利要求10或11所述的具有结型场板的DMOS器件，其特征在于，所述第二子掺杂层位于所述第一子掺杂层内，在所述第一沟槽内，所述第一掺杂多晶硅层的底面和所述第一子掺杂层以及所述第二子掺杂层均相接。
  14. 如权利要求11所述的具有结型场板的DMOS器件，其特征在于，在第一方向上，所述第二沟槽与所述第一沟槽连通；在第二方向上，所述第二沟槽与所述第一沟槽相间隔，所述第一方向和所述第二方向相垂直。
  15. 如权利要求10或11所述的具有结型场板的DMOS器件，其特征在于，所述体区包围所述第一沟槽的底部。
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JPH07130996A (ja) * 1993-06-30 1995-05-19 Toshiba Corp 高耐圧半導体素子
US7005352B2 (en) * 2001-03-21 2006-02-28 Fuji Electric Co., Inc. Trench-type MOSFET having a reduced device pitch and on-resistance
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CN111725071A (zh) * 2020-07-20 2020-09-29 西安电子科技大学 一种硅基结型积累层和缓冲层横向双扩散场效应晶体管及其制作方法

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JPH07130996A (ja) * 1993-06-30 1995-05-19 Toshiba Corp 高耐圧半導体素子
US7005352B2 (en) * 2001-03-21 2006-02-28 Fuji Electric Co., Inc. Trench-type MOSFET having a reduced device pitch and on-resistance
JP2006108514A (ja) * 2004-10-07 2006-04-20 Fuji Electric Holdings Co Ltd 半導体装置およびその製造方法
CN109192667A (zh) * 2018-09-18 2019-01-11 深圳市心版图科技有限公司 一种功率器件终端结构及其制作方法
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