WO2023108754A1 - 阵列基板及显示面板 - Google Patents

阵列基板及显示面板 Download PDF

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Publication number
WO2023108754A1
WO2023108754A1 PCT/CN2021/140458 CN2021140458W WO2023108754A1 WO 2023108754 A1 WO2023108754 A1 WO 2023108754A1 CN 2021140458 W CN2021140458 W CN 2021140458W WO 2023108754 A1 WO2023108754 A1 WO 2023108754A1
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WIPO (PCT)
Prior art keywords
electrode
conductive channel
hole
insulating layer
array substrate
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Ceased
Application number
PCT/CN2021/140458
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English (en)
French (fr)
Inventor
李观标
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TCL China Star Optoelectronics Technology Co Ltd
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TCL China Star Optoelectronics Technology Co Ltd
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Application filed by TCL China Star Optoelectronics Technology Co Ltd filed Critical TCL China Star Optoelectronics Technology Co Ltd
Priority to US17/623,594 priority Critical patent/US12027529B2/en
Publication of WO2023108754A1 publication Critical patent/WO2023108754A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6728—Vertical TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/431—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate

Definitions

  • the present application relates to the field of display technology, in particular to an array substrate and a display panel.
  • the quality design of thin film transistor devices is particularly important.
  • the above-mentioned technical solution is beneficial to reduce the occupied area of the thin film transistor device on the substrate and increase the aperture ratio of the pixel; conduction current.
  • the above-mentioned technical solution has the following technical defects: since the gate of the thin film transistor and the vertical channel structure are designed on the same horizontal plane, the active layer is closely attached to the glass substrate, which will be easily affected by the backlight, making the leakage of the thin film transistor The current increases sharply, and it is difficult for the thin film transistor to be completely turned off.
  • the present application provides an array substrate and a display panel to solve the technical problem of large leakage current of the existing array substrate.
  • an array substrate which includes:
  • the first gate electrode is disposed on the substrate
  • the first insulating layer is disposed on the first gate electrode, and the first insulating layer is provided with a first through hole;
  • the first electrode is disposed on the first insulating layer
  • the second insulating layer is disposed on the first insulating layer and covers the first electrode, and the second insulating layer is provided with a second through hole and a third through hole, the second insulating layer is provided with a second through hole and a third through hole, and the first through hole communicates with the second through hole;
  • the second gate electrode is disposed in the first through hole and the second through hole, and connected to the first gate electrode;
  • the first conductive channel is disposed in the third through hole and connected to the first electrode;
  • the second electrode is disposed on the second insulating layer and connected to the first conductive channel;
  • the orthographic projection of the first electrode on the substrate covers the orthographic projection of the first conductive channel on the substrate.
  • the first gate electrode and the second gate electrode are arranged vertically to each other.
  • the array substrate further includes a first connection electrode, the first conductive channel is provided with a fourth through hole, and the first connection electrode is disposed in the fourth through hole , one end of the first connection electrode is connected to the first electrode.
  • the first surface of the first electrode is attached and connected to the first surface of the first conductive channel.
  • the array substrate further includes a second conductive channel
  • the second insulating layer is provided with a fifth through hole
  • the second conductive channel is arranged on the fifth In the through hole
  • the second conductive channel is connected to the first conductive channel
  • the second conductive channel is located between the first electrode and the second gate electrode, and the second conductive channel The channel is insulated from the second gate electrode.
  • one end of the second conductive channel is connected to the first electrode.
  • the other end of the second conductive channel is connected to the second electrode.
  • the first conductive channel and the second conductive channel are stacked.
  • the array substrate further includes a second connection electrode, the second connection electrode is set on the first conductive channel, and the second electrode is set on the second On the connecting electrode, the orthographic projection of the second grid electrode in the layer extending direction covers the orthographic projection of the second connecting electrode in the layer extending direction.
  • the first surface of the second conductive channel is connected to the first surface of the second connection electrode.
  • the second surface of the second conductive channel is connected to the first surface of the second electrode.
  • the second electrode covers the second conductive channel.
  • the first conductive channel is an oxide semiconductor material
  • the first insulating layer and the second insulating layer are inorganic insulating materials.
  • the second conductive channel is an oxide semiconductor material.
  • the present application further provides a display panel, which includes the above-mentioned array substrate, and further includes a pixel electrode, the pixel electrode is disposed on the second electrode, and the pixel electrode is connected to the second electrode.
  • a passivation layer is also included, the passivation layer is located between the pixel electrode and the second electrode, and the pixel electrode passes through the passivation layer on the passivation layer.
  • the hole is connected to the second electrode.
  • the present application also provides an array substrate, which includes:
  • the first gate electrode is disposed on the substrate
  • the first insulating layer is disposed on the first gate electrode, and the first insulating layer is provided with a first through hole;
  • the first electrode is disposed on the first insulating layer
  • the second insulating layer is disposed on the first insulating layer and covers the first electrode, and the second insulating layer is provided with a second through hole and a third through hole, the second insulating layer is provided with a second through hole and a third through hole, and the first through hole communicates with the second through hole;
  • the second gate electrode is disposed in the first through hole and the second through hole, and connected to the first gate electrode;
  • the first conductive channel is disposed in the third through hole and connected to the first electrode;
  • the second electrode is disposed on the second insulating layer and connected to the first conductive channel;
  • an orthographic projection of the first electrode on the substrate covers an orthographic projection of the first conductive channel on the substrate;
  • the first electrode is a source electrode
  • the second electrode is a drain electrode
  • the first gate electrode and the second gate electrode are arranged vertically to each other.
  • the array substrate further includes a first connection electrode, the first conductive channel is provided with a fourth through hole, and the first connection electrode is disposed in the fourth through hole , one end of the first connection electrode is connected to the first electrode.
  • the first surface of the first electrode is attached and connected to the first surface of the first conductive channel.
  • the array substrate further includes a second conductive channel
  • the second insulating layer is provided with a fifth through hole
  • the second conductive channel is arranged on the fifth In the through hole
  • the second conductive channel is connected to the first conductive channel
  • the second conductive channel is located between the first electrode and the second gate electrode, and the second conductive channel The channel is insulated from the second gate electrode.
  • one end of the second conductive channel is connected to the first electrode.
  • the other end of the second conductive channel is connected to the second electrode.
  • the first conductive channel and the second conductive channel are stacked.
  • the array substrate further includes a second connection electrode, the second connection electrode is set on the first conductive channel, and the second electrode is set on the second On the connecting electrode, the orthographic projection of the second grid electrode in the layer extending direction covers the orthographic projection of the second connecting electrode in the layer extending direction.
  • the first surface of the second conductive channel is connected to the first surface of the second connection electrode.
  • the second surface of the second conductive channel is connected to the first surface of the second electrode.
  • the second electrode covers the second conductive channel.
  • the first conductive channel is an oxide semiconductor material
  • the first insulating layer and the second insulating layer are inorganic insulating materials.
  • the second conductive channel is an oxide semiconductor material.
  • the present application further provides a display panel, which includes the above-mentioned array substrate, and further includes a pixel electrode, the pixel electrode is disposed on the second electrode, and the pixel electrode is connected to the second electrode.
  • a passivation layer is also included, the passivation layer is located between the pixel electrode and the second electrode, and the pixel electrode passes through the passivation layer on the passivation layer.
  • the hole is connected to the second electrode.
  • the present application provides an array substrate and a display panel, wherein the array substrate includes: a substrate; a first gate electrode disposed on the substrate; a first insulating layer disposed on the substrate.
  • the first gate electrode, and the first insulating layer is provided with a first through hole; the first electrode, the first electrode is arranged on the first insulating layer; the second insulating layer, the second insulating layer layer is disposed on the first insulating layer and covers the first electrode, and the second insulating layer is provided with a second through hole and a third through hole, and the first through hole is connected to the second through hole
  • the hole is connected; the second gate electrode is arranged in the first through hole and the second through hole, and is connected with the first gate electrode; the first conductive channel, the first A conductive channel is arranged in the third through hole and connected to the first electrode; a second electrode is arranged on the second insulating layer and connected to the first conductive channel track connection; wherein, the orthographic projection of the first electrode on the substrate covers
  • the first grid electrode can block the backlight illumination, thereby preventing the backlight illumination from affecting the first conductive channel. channel, and reduce the leakage current of the array substrate.
  • FIG. 1 is a schematic diagram of a first structure of an array substrate provided by the present application.
  • FIG. 2 is a second structural schematic diagram of the array substrate provided by the present application.
  • FIG. 3 is a schematic diagram of a third structure of the array substrate provided by the present application.
  • FIG. 4 is a schematic diagram of a fourth structure of the array substrate provided by the present application.
  • FIG. 5 is a schematic diagram of a fifth structure of the array substrate provided by the present application.
  • FIG. 6 is a schematic diagram of a display panel provided by the present application.
  • the present application provides an array substrate and a display panel, which will be described in detail below. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments of the present application.
  • FIG. 1 is a schematic diagram of the first structure of the array substrate provided by the present application.
  • the present application provides an array substrate 100, which includes a substrate 10, a first gate electrode 20, a first insulating layer 30, a first electrode 40, a second insulating layer 50, a first conductive channel 60, a second gate electrode 70 and the second electrode 80 .
  • the first electrode 40 and the second electrode 80 in the above-mentioned array substrate provided in this application are equivalent to the source electrode or drain electrode in the prior art, and in specific implementation, the first electrode 40 can be used as the source electrode , the second electrode 80 is used as a drain electrode, and the second electrode 80 can also be used as a source electrode, and the first electrode 40 is used as a drain electrode, which is not limited here. That is, the first electrode 40 is a source electrode, and the second electrode 80 is a drain electrode; or the first electrode 40 is a drain electrode, and the second electrode 80 is a source electrode.
  • the first gate electrode 20 is disposed on the substrate 10, the first insulating layer 30 is disposed on the first gate electrode 20, and the first insulating layer 30 is provided with a first through hole, the first The electrode 40 is disposed on the first insulating layer 30; the second insulating layer 50 is disposed on the first insulating layer 30 and covers the first electrode 40, and the second insulating layer 50 is provided with a second through hole and a third through hole, the first through hole communicates with the second through hole; the second gate electrode 70 is disposed in the first through hole and the second through hole, and connected to the first gate electrode 20 .
  • the first conductive channel 60 is disposed in the third through hole and connected to the first electrode 40; the second electrode 80 is disposed on the second insulating layer 50 and connected to the first electrode 40.
  • a conductive channel 60 is connected; wherein, the orthographic projection of the first electrode 20 on the substrate 10 covers the orthographic projection of the first conductive channel 60 on the substrate 10 .
  • the present application by setting the extension direction of the second gate electrode 70 in the same direction as the extension direction of the first conductive channel 60, the length of the second gate electrode 70 in the vertical direction can be controlled, thereby increasing the length of the first conductive channel 60.
  • the conduction current of the array substrate device is increased.
  • the present application also utilizes the orthographic projection of the first grid electrode 20 on the substrate 10 to cover the orthographic projection of the first conductive channel 60 on the substrate 10, the first grid electrode 20 can block backlight illumination, thereby The influence of backlight illumination on the first conductive channel 60 is avoided, and the leakage current of the array substrate 100 is reduced.
  • the first gate electrode 20 and the second gate electrode 70 are arranged perpendicular to each other, specifically, the first gate electrode 20 is arranged horizontally, and the second gate electrode 70 is arranged vertically. set up.
  • FIG. 6 is a schematic diagram of the display panel provided by this application.
  • This application also provides a display panel 1000, which includes the above-mentioned array substrate 100 provided by this application.
  • a display panel 1000 which includes the above-mentioned array substrate 100 provided by this application.
  • this display panel please refer to the above-mentioned Embodiments of the array substrate are not repeated here.
  • the display panel 1000 further includes a pixel electrode 200 disposed on the second electrode 80 , and the pixel electrode 200 is connected to the second electrode 80 .
  • the display panel 1000 further includes a passivation layer 300, the passivation layer 300 is located between the pixel electrode 200 and the second electrode 80, and the pixel electrode 200 passes through the passivation layer 300 The via hole on the top is connected to the second electrode 80 .
  • the above-mentioned array substrate provided in the present application can be applied to liquid crystal display panels, OLED display devices, or other organic electroluminescent devices, which is not limited here.
  • FIG. 2 is a schematic diagram of a second structure of the array substrate provided by the present application.
  • the array substrate 100 further includes a first connection electrode 41, a fourth through hole is provided on the first conductive channel 60, and the first connection electrode 41 Arranged in the fourth through hole, one end of the first connection electrode 41 is connected to the first electrode 40 .
  • the overlapping length of the second gate electrode 70 and the first electrode 40 and the first connection electrode 41 can be increased, thereby increasing the on-state current of the array substrate 100 .
  • the orthographic projection of the first electrode 40 on the substrate 10 is staggered from the orthographic projection of the first grid electrode 20 on the substrate 10 .
  • the first connecting electrodes 41 and the first electrodes 40 are arranged perpendicularly to each other.
  • the first surface of the first electrode 40 is attached to and connected to the first surface of the first conductive channel 60 .
  • the connection area between the conductive channel and the first electrode 40 can be further increased, and the connection stability between the conductive channel of the array substrate 100 and the first electrode 40 can be improved.
  • FIG. 3 is a schematic diagram of a third structure of the array substrate provided by the present application.
  • the array substrate further includes a second conductive channel 90, the second insulating layer 50 is provided with a fifth through hole, and the second conductive channel 90 is arranged on the In the fifth through hole, the second conductive channel 90 is connected to the first conductive channel 60, and the second conductive channel 90 is located between the first electrode 40 and the second gate electrode 70 Between, the second conductive channel 90 is insulated from the second gate electrode 70 .
  • the insulation effect between the first gate electrode 70 and the first electrode 40 can be strengthened, thereby avoiding the second gate electrode 70 short circuit with the first electrode 40 .
  • one end of the second conductive channel 90 is connected to the first electrode 40 .
  • the side surface of the lower end of the second conductive channel 90 is connected to the first electrode 40, which can further increase the connection area between the conductive channel and the first electrode 40, and can improve the connection between the conductive channel of the array substrate 100 and the first electrode 40. Connection stability between electrodes 40.
  • the other end of the second conductive channel 90 is connected to the second electrode 80 .
  • the upper end surface of the second conductive channel 90 is connected to the second electrode 80, which can further increase the connection area between the conductive channel and the second electrode 80, and can improve the connection between the conductive channel of the array substrate 100 and the second electrode 80. Connection stability between electrodes 80.
  • first conductive channel 60 and the second conductive channel 90 are stacked in sequence.
  • the stacked arrangement of the first conductive channel 60 and the second conductive channel 90 can reduce the occupied space while maximizing the contact area of the first conductive channel 60 and the second conductive channel 90 .
  • the array substrate 100 provided by the present application may be an oxide array substrate, and the first conductive channel 60 and the second conductive channel 90 of the array substrate 100 may be made of, for example, InGaZnO, InGa Oxide semiconductor materials such as tin oxide oxide, indium zinc oxide, etc.
  • the first insulating layer 30 and the second insulating layer 50 in the array substrate device may include silicon dioxide, silicon nitride, silicon oxynitride, oxide Aluminum, titanium oxide and other inorganic insulating materials.
  • the array substrate 100 provided by the present application can also be a low-temperature polysilicon array substrate, that is, the first conductive channel 60 and the second conductive channel 90 of the array substrate 100 can be made of amorphous silicon, polycrystalline silicon or microcrystalline silicon. Materials.
  • the first insulating layer 30 and the second insulating layer 50 in the array substrate device may be organic insulating materials such as resin-based insulating materials and acrylic-based insulating materials.
  • FIG. 4 is a schematic diagram of a fourth structure of the array substrate provided by the present application.
  • the array substrate 100 further includes a second connection electrode 81, the second connection electrode 81 is provided on the first conductive channel 60, and the second The electrode 80 is disposed on the second connecting electrode 81 , and the orthographic projection of the second grid electrode 70 in the layer extending direction covers the orthographic projection of the second connecting electrode 81 in the layer extending direction.
  • the second connection electrode 81 by adding the second connection electrode 81, and covering the orthographic projection of the second connection electrode 81 in the layer extension direction of the second grid electrode 70 in the layer extension direction, the second grid electrode 70 and the second grid electrode 70 can be increased.
  • the overlapping length of the two connecting electrodes 81 can increase the on-state current of the array substrate 100 .
  • FIG. 5 is a schematic diagram of a fifth structure of the array substrate provided in the present application.
  • the array substrate 100 further includes a first connection electrode 41, a fourth through hole is provided on the first conductive channel 60, and the first connection electrode 41 Arranged in the fourth through hole, one end of the first connection electrode 41 is connected to the first electrode 40 .
  • the overlapping length of the second gate electrode 70 and the first electrode 40 and the first connection electrode 41 can be increased, thereby increasing the on-state current of the array substrate 100 .
  • the array substrate 100 further includes a second conductive channel 90, the second insulating layer 50 is provided with a fifth through hole, and the second conductive channel 90 is arranged on the fifth through hole.
  • the second conductive channel 90 is connected to the first conductive channel 60, and the second conductive channel 90 is located between the first electrode 40 and the second gate electrode 70, so The second conductive channel 90 is insulated from the second gate electrode 70 .
  • the insulation effect between the second gate electrode 70 and the first electrode 40 can be strengthened, thereby avoiding the second gate electrode 70 short circuit with the first electrode 40 .
  • the second conductive channel 90 is located between the first connection electrode 41 and the second gate electrode 70 .
  • first conductive channel 60 and the second conductive channel 90 are stacked in sequence.
  • the stacked arrangement of the first conductive channel 60 and the second conductive channel 90 can reduce the occupied space while maximizing the contact area of the first conductive channel 60 and the second conductive channel 90 .
  • one end of the second conductive channel 90 is connected to the first electrode 40 .
  • the other end of the first connecting electrode 41 is connected to one end of the second conductive channel 90 , so that one end of the second conductive channel 90 is connected to the first electrode 40 .
  • the other end of the second conductive channel 90 is connected to the second electrode 80 .
  • the upper end surface of the second conductive channel 90 is connected to the second electrode 80 .
  • the first electrode 40 is connected to the first conductive channel 60 through the first connecting electrode 41, which can increase the connection area between the first electrode 40, the second electrode 80 and the conductive channel, and improve the connection between the electrodes and the conductive channel. connection stability.
  • the orthographic projection of the first electrode 40 on the substrate 10 is staggered from the orthographic projection of the first grid electrode 20 on the substrate 10 .
  • the first surface of the first electrode 40 is attached to and connected to the first surface of the first conductive channel 60 .
  • the connection area between the conductive channel and the first electrode 40 can be further increased, and the connection stability between the conductive channel of the array substrate 100 and the first electrode 40 can be improved.
  • the array substrate 100 also includes a second connection electrode 81, the second connection electrode 81 is set on the first conductive channel 60, and the second electrode 80 is set on the second connection electrode 81 , the orthographic projection of the second gate electrode 70 in the layer extending direction covers the orthographic projection of the second connecting electrode 81 in the layer extending direction.
  • the second connection electrode 81 by adding the second connection electrode 81, and covering the orthographic projection of the second connection electrode 81 in the layer extension direction of the second grid electrode 70 in the layer extension direction, the second grid electrode 70 and the second grid electrode 70 can be increased.
  • the overlapping length of the two connecting electrodes 81 can increase the on-state current of the array substrate 100 .
  • the first surface of the second conductive channel 90 is connected to the first surface of the second connection electrode 71 .
  • the second surface of the second conductive channel 90 is connected to the first surface of the second electrode 80 .
  • the connection area between the conductive channel and the second electrode 80 can be further increased, and the connection stability between the conductive channel of the array substrate 100 and the second electrode 80 can be improved.
  • the first surface and the second surface of the second conductive channel 90 are adjacent and perpendicular to each other.
  • the second electrode 80 covers the second conductive channel 90 .
  • the exposure of the second conductive channel 90 can be avoided, and the arrangement of insulating layers can be reduced.

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  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本申请公开一种阵列基板及显示面板，其中阵列基板包括：基板、第一栅电极、第一绝缘层、第一电极、第二栅电极、第一导电沟道和第二电极。本申请通过利用第一栅电极在基板上的正投影覆盖第一导电沟道在基板上的正投影，而降低阵列基板的漏电电流。

Description

阵列基板及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种阵列基板及显示面板。
 背景技术
在面板制造过程中，薄膜晶体管器件的品质设计尤为重要。现已有一种将薄膜晶体管器件中源漏电极形成的水平沟道结构变更为垂直沟道结构，并将薄膜晶体管的栅极与垂直沟道结构设置在同一水平面上的技术方案。上述的技术方案一方面有利于减少薄膜晶体管器件在基板的占用面积，提高像素开口率，另一方面可以通过控制栅极在垂直方向的长度，实现增加垂直沟道的长度，从而提升薄膜晶体管器件的导通电流。
但是上述的技术方案存在以下技术缺陷：由于将薄膜晶体管的栅极与垂直沟道结构设计在同一水平面上，有源层紧贴着玻璃基板，这样会容易受到背光光照影响，使得薄膜晶体管的漏电电流剧增，薄膜晶体管难以彻底关闭。
 技术问题
本申请提供一种阵列基板及显示面板，以解决现有阵列基板的漏电电流大的技术问题。
 技术解决方案
第一方面，本申请提供一种阵列基板，其包括：
基板；
第一栅电极，所述第一栅电极设置在所述基板上；
第一绝缘层，所述第一绝缘层设置在所述第一栅电极上，且所述第一绝缘层设有第一通孔；
第一电极，所述第一电极设置在所述第一绝缘层上；
第二绝缘层，所述第二绝缘层设置在所述第一绝缘层上，并覆盖所述第一电极，且所述第二绝缘层设有第二通孔以及第三通孔，所述第一通孔与所述第二通孔连通；
第二栅电极，所述第二栅电极设置在所述第一通孔以及所述第二通孔内，并与所述第一栅电极连接；
第一导电沟道，所述第一导电沟道设置在所述第三通孔内，并与所述第一电极连接；
第二电极，所述第二电极设置在所述第二绝缘层上，并与所述第一导电沟道连接；其中，
所述第一电极在所述基板上的正投影覆盖所述第一导电沟道在所述基板上的正投影。
可选的，在本申请一些实施例中，所述第一栅电极与所述第二栅电极相互垂直设置。
可选的，在本申请一些实施例中，所述阵列基板还包括第一连接电极，所述第一导电沟道上设有第四通孔，所述第一连接电极设置在第四通孔内，所述第一连接电极的一端与所述第一电极连接。
可选的，在本申请一些实施例中，所述第一电极的第一面与所述第一导电沟道的第一面相贴合连接。
可选的，在本申请一些实施例中，所述阵列基板还包括第二导电沟道，所述第二绝缘层设有第五通孔，所述第二导电沟道设置在所述第五通孔内，所述第二导电沟道与所述第一导电沟道连接，且所述第二导电沟道位于所述第一电极与所述第二栅电极之间，所述第二导电沟道与所述第二栅电极相绝缘。
可选的，在本申请一些实施例中，所述第二导电沟道的一端与所述第一电极连接。
可选的，在本申请一些实施例中，所述第二导电沟道的另一端与所述第二电极连接。
可选的，在本申请一些实施例中，所述第一导电沟道和第二导电沟道层叠设置。
可选的，在本申请一些实施例中，所述阵列基板还包括第二连接电极，所述第二连接电极设在所述第一导电沟道上，所述第二电极设在所述第二连接电极上，所述第二栅电极在层面延伸方向的正投影覆盖所述第二连接电极在层面延伸方向的正投影。
可选的，在本申请一些实施例中，所述第二导电沟道的第一面与所述第二连接电极的第一面连接。
可选的，在本申请一些实施例中，所述第二导电沟道的第二面与所述第二电极的第一面连接。
可选的，在本申请一些实施例中，所述第二电极覆盖在所述第二导电沟道上。
可选的，在本申请一些实施例中，所述第一导电沟道为氧化物半导体材料，所述第一绝缘层和第二绝缘层为无机绝缘材料。
可选的，在本申请一些实施例中，所述第二导电沟道为氧化物半导体材料。
相应的，本申请还提供一种显示面板，其包括上述的阵列基板，还包括像素电极，所述像素电极设在所述第二电极上，所述像素电极与所述第二电极连接。
可选的，在本申请一些实施例中，还包括钝化层，所述钝化层位于所述像素电极与所述第二电极之间，所述像素电极通过所述钝化层上的过孔与所述第二电极连接。
本申请还提供一种阵列基板，其包括：
基板；
第一栅电极，所述第一栅电极设置在所述基板上；
第一绝缘层，所述第一绝缘层设置在所述第一栅电极上，且所述第一绝缘层设有第一通孔；
第一电极，所述第一电极设置在所述第一绝缘层上；
第二绝缘层，所述第二绝缘层设置在所述第一绝缘层上，并覆盖所述第一电极，且所述第二绝缘层设有第二通孔以及第三通孔，所述第一通孔与所述第二通孔连通；
第二栅电极，所述第二栅电极设置在所述第一通孔以及所述第二通孔内，并与所述第一栅电极连接；
第一导电沟道，所述第一导电沟道设置在所述第三通孔内，并与所述第一电极连接；
第二电极，所述第二电极设置在所述第二绝缘层上，并与所述第一导电沟道连接；其中，
所述第一电极在所述基板上的正投影覆盖所述第一导电沟道在所述基板上的正投影；
所述第一电极为源电极，所述第二电极为漏电极。
可选的，在本申请一些实施例中，所述第一栅电极与所述第二栅电极相互垂直设置。
可选的，在本申请一些实施例中，所述阵列基板还包括第一连接电极，所述第一导电沟道上设有第四通孔，所述第一连接电极设置在第四通孔内，所述第一连接电极的一端与所述第一电极连接。
可选的，在本申请一些实施例中，所述第一电极的第一面与所述第一导电沟道的第一面相贴合连接。
可选的，在本申请一些实施例中，所述阵列基板还包括第二导电沟道，所述第二绝缘层设有第五通孔，所述第二导电沟道设置在所述第五通孔内，所述第二导电沟道与所述第一导电沟道连接，且所述第二导电沟道位于所述第一电极与所述第二栅电极之间，所述第二导电沟道与所述第二栅电极相绝缘。
可选的，在本申请一些实施例中，所述第二导电沟道的一端与所述第一电极连接。
可选的，在本申请一些实施例中，所述第二导电沟道的另一端与所述第二电极连接。
可选的，在本申请一些实施例中，所述第一导电沟道和第二导电沟道层叠设置。
可选的，在本申请一些实施例中，所述阵列基板还包括第二连接电极，所述第二连接电极设在所述第一导电沟道上，所述第二电极设在所述第二连接电极上，所述第二栅电极在层面延伸方向的正投影覆盖所述第二连接电极在层面延伸方向的正投影。
可选的，在本申请一些实施例中，所述第二导电沟道的第一面与所述第二连接电极的第一面连接。
可选的，在本申请一些实施例中，所述第二导电沟道的第二面与所述第二电极的第一面连接。
可选的，在本申请一些实施例中，所述第二电极覆盖在所述第二导电沟道上。
可选的，在本申请一些实施例中，所述第一导电沟道为氧化物半导体材料，所述第一绝缘层和第二绝缘层为无机绝缘材料。
可选的，在本申请一些实施例中，所述第二导电沟道为氧化物半导体材料。
相应的，本申请还提供一种显示面板，其包括上述的阵列基板，还包括像素电极，所述像素电极设在所述第二电极上，所述像素电极与所述第二电极连接。
可选的，在本申请一些实施例中，还包括钝化层，所述钝化层位于所述像素电极与所述第二电极之间，所述像素电极通过所述钝化层上的过孔与所述第二电极连接。
 有益效果
本申请提供一种阵列基板及显示面板，其中阵列基板包括：基板；第一栅电极，所述第一栅电极设置在所述基板上；第一绝缘层，所述第一绝缘层设置在所述第一栅电极上，且所述第一绝缘层设有第一通孔；第一电极，所述第一电极设置在所述第一绝缘层上；第二绝缘层，所述第二绝缘层设置在所述第一绝缘层上，并覆盖所述第一电极，且所述第二绝缘层设有第二通孔以及第三通孔，所述第一通孔与所述第二通孔连通；第二栅电极，所述第二栅电极设置在所述第一通孔以及所述第二通孔内，并与所述第一栅电极连接；第一导电沟道，所述第一导电沟道设置在所述第三通孔内，并与所述第一电极连接；第二电极，所述第二电极设置在所述第二绝缘层上，并与所述第一导电沟道连接；其中，述第一电极在所述基板上的正投影覆盖所述第一导电沟道在所述基板上的正投影。本申请通过利用第一栅电极在所述基板上的正投影覆盖所述第一导电沟道在所述基板上的正投影，第一栅电极可以遮挡背光光照，从而避免背光光照对第一导电沟道的影响，而降低阵列基板的漏电电流。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请提供的阵列基板的第一结构示意图；
图2为本申请提供的阵列基板的第二结构示意图；
图3为本申请提供的阵列基板的第三结构示意图；
图4为本申请提供的阵列基板的第四结构示意图；
图5为本申请提供的阵列基板的第五结构示意图；
图6为本申请提供的显示面板的示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“上”、“下”、“前”、“后”、“左”、“右”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
本申请提供一种阵列基板及显示面板，以下进行详细说明。需要说明的是，以下实施例的描述顺序不作为对本申请实施例优选顺序的限定。
请参阅图1，图1是本申请提供的阵列基板的第一结构示意图。本申请提供一种阵列基板100，其包括基板10、第一栅电极20、第一绝缘层30、第一电极40、第二绝缘层50、第一导电沟道60、第二栅电极70和第二电极80。
具体地，在本申请提供的上述阵列基板中的第一电极40和第二电极80等同于现有技术中的源电极或漏电极，在具体实施时，可以将第一电极40作为源电极使用，第二电极80作为漏电极使用，也可以将第二电极80作为源电极使用，第一电极40作为漏电极使用，在此不做限定。也即是，所述第一电极40为源电极，所述第二电极80为漏电极；或所述第一电极40为漏电极，所述第二电极80为源电极。
其中，第一栅电极20设在所述基板10上，所述第一绝缘层30设置在所述第一栅电极20上，且所述第一绝缘层30设有第一通孔，第一电极40设在所述第一绝缘层30上；所述第二绝缘层50设置在所述第一绝缘层30上，并覆盖所述第一电极40，且所述第二绝缘层50设有第二通孔以及第三通孔，所述第一通孔与所述第二通孔连通；所述第二栅电极70设置在所述第一通孔以及所述第二通孔内，并与所述第一栅电极20连接。
所述第一导电沟道60设置在所述第三通孔内，并与所述第一电极40连接；所述第二电极80设置在所述第二绝缘层50上，并与所述第一导电沟道60连接；其中，所述第一电极20在所述基板10上的正投影覆盖所述第一导电沟道60在所述基板10上的正投影。
本申请通过将第二栅电极70的延伸方向与第一导电沟道60的延伸方向相同设置，可以控制第二栅电极70在垂直方向的长度，而实现增加第一导电沟道60的长度，从而提升阵列基板器件的导通电流。另外，本申请还利用第一栅电极20在所述基板10上的正投影覆盖所述第一导电沟道60在所述基板10上的正投影，第一栅电极20可以遮挡背光光照，从而避免背光光照对第一导电沟道60的影响，而降低阵列基板100的漏电电流。
在一些实施例中，为了提高加工效率，降低材料成本，第一栅电极20与第二栅电极70相互垂直设置，具体地，第一栅电极20为水平设置，第二栅电极70为竖向设置。
另外，请参考图6，图6为是本申请提供的显示面板的示意图，本申请还提供了一种显示面板1000，其包括本申请提供的上述阵列基板100，该显示面板的实施可以参见上述阵列基板的实施例，重复之处不再赘述。
其中，显示面板1000还包括像素电极200，所述像素电极200设在所述第二电极80上，所述像素电极200与所述第二电极80连接。
在一些实施例中，显示面板1000还包括钝化层300，所述钝化层300位于所述像素电极200与所述第二电极80之间，所述像素电极200通过所述钝化层300上的过孔与所述第二电极80连接。
具体地，本申请提供的上述阵列基板可以应用于液晶显示面板，也可以应用于OLED 显示器件，还可以应用于其他有机电致发光器件中，在此不做限定。
请参阅图2，图2是本申请提供的阵列基板的第二结构示意图。本实施例与图1提供的阵列基板不同的是，所述阵列基板100还包括第一连接电极41，所述第一导电沟道60上设有第四通孔，所述第一连接电极41设置在第四通孔内，所述第一连接电极41的一端与所述第一电极40连接。
通过设有第一连接电极41的方式，可以增加第二栅电极70和第一电极40、第一连接电极41的重叠长度，从而提高阵列基板100的开态电流。
其中，在一些实施例中，第一电极40在基板10上的正投影与第一栅电极20在基板10上的正投影相错开。另外，所述第一连接电极41与所述第一电极40相互垂直设置。
另外，一些实施例中，所述第一电极40的第一面与所述第一导电沟道60的第一面相贴合连接。可以进一步地增加导电沟道与第一电极40的连接面积，能提高阵列基板100的导电沟道与第一电极40之间的连接稳定性。
请参阅图3，图3是本申请提供的阵列基板的第三结构示意图。本实施例与图1提供的阵列基板不同的是，阵列基板还包括第二导电沟道90，所述第二绝缘层50设有第五通孔，所述第二导电沟道90设置在所述第五通孔内，所述第二导电沟道90与所述第一导电沟道60连接，且所述第二导电沟道90位于所述第一电极40与所述第二栅电极70之间，所述第二导电沟道90与所述第二栅电极70相绝缘。
通过将第二导电沟道90设在第一电极40与所述第二栅电极70之间，可以加强第一栅电极70与第一电极40之间的绝缘效果，从而避免第二栅电极70与第一电极40之间短路。
在一些实施例中，所述第二导电沟道90的一端与所述第一电极40连接。具体地，第二导电沟道90的下端的侧面与所述第一电极40连接，可以进一步地增加导电沟道与第一电极40的连接面积，能提高阵列基板100的导电沟道与第一电极40之间的连接稳定性。
在一些实施例中，所述第二导电沟道90的另一端与所述第二电极80连接。具体地，第二导电沟道90的上端的端面与所述第二电极80连接，可以进一步地增加导电沟道与第二电极80的连接面积，能提高阵列基板100的导电沟道与第二电极80之间的连接稳定性。
另外，在一些实施例中，所述第一导电沟道60和第二导电沟道90依次层叠设置。层叠设置的第一导电沟道60和第二导电沟道90可以降低占有空间，同时可以将第一导电沟道60和第二导电沟道90的接触面积最大化。
进一步地，在具体实施时，本申请提供的阵列基板100可以是氧化物阵列基板，阵列基板100的第一导电沟道60和第二导电沟道90可以为诸如铟镓锌氧化物、铟镓锡氧化物氧化、铟锌氧化物等的氧化物半导体材料，对应地，阵列基板器件中的第一绝缘层30和第二绝缘层50可以包括二氧化硅、氮化硅、氮氧化硅、氧化铝、氧化钛等无机绝缘材料。
当然，在具体实施时，本申请提供的阵列基板100还可以低温多晶硅阵列基板，即阵列基板100的第一导电沟道60和第二导电沟道90可以为非晶硅、多晶硅或微晶硅材料，对应地，阵列基板器件中的第一绝缘层30和第二绝缘层50可以为树脂系绝缘材料、亚克力系绝缘材料等有机绝缘材料。
请参阅图4，图4是本申请提供的阵列基板的第四结构示意图。本实施例与图1提供的阵列基板不同的是，所述阵列基板100还包括第二连接电极81，所述第二连接电极81设在所述第一导电沟道60上，所述第二电极80设在所述第二连接电极81上，所述第二栅电极70在层面延伸方向的正投影覆盖所述第二连接电极81在层面延伸方向的正投影。
本申请通过增设第二连接电极81，而且将第二栅电极70在层面延伸方向的正投影覆盖所述第二连接电极81在层面延伸方向的正投影，这样可以增加第二栅电极70和第二连接电极81的重叠长度，从而提高阵列基板100的开态电流。
请参阅图5，图5是本申请提供的阵列基板的第五结构示意图。本实施例与图1提供的阵列基板不同的是，所述阵列基板100还包括第一连接电极41，所述第一导电沟道60上设有第四通孔，所述第一连接电极41设置在第四通孔内，所述第一连接电极41的一端与所述第一电极40连接。
通过设有第一连接电极41的方式，可以增加第二栅电极70和第一电极40、第一连接电极41的重叠长度，从而提高阵列基板100的开态电流。
进一步地，在一些实施例中，阵列基板100还包括第二导电沟道90，所述第二绝缘层50设有第五通孔，所述第二导电沟道90设置在所述第五通孔内，所述第二导电沟道90与所述第一导电沟道60连接，且所述第二导电沟道90位于所述第一电极40与所述第二栅电极70之间，所述第二导电沟道90与所述第二栅电极70相绝缘。
通过将第二导电沟道90设在第一电极40与所述第二栅电极70之间，可以加强第二栅电极70与第一电极40之间的绝缘效果，从而避免第二栅电极70与第一电极40之间短路。
进一步，所述第二导电沟道90位于所述第一连接电极41与所述第二栅电极70之间。
另外，在一些实施例中，所述第一导电沟道60和第二导电沟道90依次层叠设置。层叠设置的第一导电沟道60和第二导电沟道90可以降低占有空间，同时可以将第一导电沟道60和第二导电沟道90的接触面积最大化。
进一步地，在一些实施例中，所述第二导电沟道90的一端与所述第一电极40连接。具体地，所述第一连接电极41的另一端与所述第二导电沟道90的一端连接，这样可以实现第二导电沟道90的一端与所述第一电极40连接。
另外，所述第二导电沟道90的另一端与所述第二电极80连接。具体地，第二导电沟道90的上端的端面与所述第二电极80连接。而且第一电极40通过第一连接电极41与第一导电沟道60连接，可以增大第一电极40、第二电极80与导电沟道之间的连接面积，提高电极与导电沟道之间的连接稳定性。
其中，在一些实施例中，第一电极40在基板10上的正投影与第一栅电极20在基板10上的正投影相错开。
另外，一些实施例中，所述第一电极40的第一面与所述第一导电沟道60的第一面相贴合连接。可以进一步地增加导电沟道与第一电极40的连接面积，能提高阵列基板100的导电沟道与第一电极40之间的连接稳定性。
再进一步地，所述阵列基板100还包括第二连接电极81，所述第二连接电极81设在所述第一导电沟道60上，所述第二电极80设在所述第二连接电极81上，所述第二栅电极70在层面延伸方向的正投影覆盖所述第二连接电极81在层面延伸方向的正投影。
本申请通过增设第二连接电极81，而且将第二栅电极70在层面延伸方向的正投影覆盖所述第二连接电极81在层面延伸方向的正投影，这样可以增加第二栅电极70和第二连接电极81的重叠长度，从而提高阵列基板100的开态电流。
其中，在一些实施例中，所述第二导电沟道90的第一面与所述第二连接电极71的第一面连接。所述第二导电沟道90的第二面与所述第二电极80的第一面连接。可以进一步地增加导电沟道与第二电极80的连接面积，能提高阵列基板100的导电沟道与第二电极80之间的连接稳定性。其中，第二导电沟道90的第一面和第二面相邻且相互垂直。
而且，所述第二电极80覆盖在所述第二导电沟道90上。可以避免第二导电沟道90裸露，并减少绝缘层的设置。
以上对本申请实施例所提供的一种阵列基板及显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上，本说明书内容不应理解为对本申请的限制。

Claims (19)

  1. 一种阵列基板，其包括：
    基板；
    第一栅电极，所述第一栅电极设置在所述基板上；
    第一绝缘层，所述第一绝缘层设置在所述第一栅电极上，且所述第一绝缘层设有第一通孔；
    第一电极，所述第一电极设置在所述第一绝缘层上；
    第二绝缘层，所述第二绝缘层设置在所述第一绝缘层上，并覆盖所述第一电极，且所述第二绝缘层设有第二通孔以及第三通孔，所述第一通孔与所述第二通孔连通；
    第二栅电极，所述第二栅电极设置在所述第一通孔以及所述第二通孔内，并与所述第一栅电极连接；
    第一导电沟道，所述第一导电沟道设置在所述第三通孔内，并与所述第一电极连接；
    第二电极，所述第二电极设置在所述第二绝缘层上，并与所述第一导电沟道连接；其中，
    所述第一电极在所述基板上的正投影覆盖所述第一导电沟道在所述基板上的正投影。
  2. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括第一连接电极，所述第一导电沟道上设有第四通孔，所述第一连接电极设置在第四通孔内，所述第一连接电极的一端与所述第一电极连接。
  3. 根据权利要求2所述的阵列基板，其中，所述第一电极的第一面与所述第一导电沟道的第一面相贴合连接。
  4. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括第二导电沟道，所述第二绝缘层设有第五通孔，所述第二导电沟道设置在所述第五通孔内，所述第二导电沟道与所述第一导电沟道连接，且所述第二导电沟道位于所述第一电极与所述第二栅电极之间，所述第二导电沟道与所述第二栅电极相绝缘。
  5. 根据权利要求4所述的阵列基板，其中，所述第二导电沟道的一端与所述第一电极连接；
    和/或，所述第二导电沟道的另一端与所述第二电极连接。
  6. 根据权利要求4所述的阵列基板，其中，所述第一导电沟道和第二导电沟道层叠设置。
  7. 根据权利要求4所述的阵列基板，其中，所述阵列基板还包括第二连接电极，所述第二连接电极设在所述第一导电沟道上，所述第二电极设在所述第二连接电极上，所述第二栅电极在层面延伸方向的正投影覆盖所述第二连接电极在层面延伸方向的正投影。
  8. 根据权利要求7所述的阵列基板，其中，所述第二导电沟道位于所述第二连接电极与所述第二栅电极之间。
  9. 根据权利要求8所述的阵列基板，其中，所述第二电极覆盖在所述第二导电沟道上。
  10. 一种显示面板，其中，包括阵列基板，还包括像素电极，所述像素电极设在所述第二电极上，所述像素电极与所述第二电极连接；
    所述阵列基板包括：
    基板；
    第一栅电极，所述第一栅电极设置在所述基板上；
    第一绝缘层，所述第一绝缘层设置在所述第一栅电极上，且所述第一绝缘层设有第一通孔；
    第一电极，所述第一电极设置在所述第一绝缘层上；
    第二绝缘层，所述第二绝缘层设置在所述第一绝缘层上，并覆盖所述第一电极，且所述第二绝缘层设有第二通孔以及第三通孔，所述第一通孔与所述第二通孔连通；
    第二栅电极，所述第二栅电极设置在所述第一通孔以及所述第二通孔内，并与所述第一栅电极连接；
    第一导电沟道，所述第一导电沟道设置在所述第三通孔内，并与所述第一电极连接；
    第二电极，所述第二电极设置在所述第二绝缘层上，并与所述第一导电沟道连接；其中，
    所述第一电极在所述基板上的正投影覆盖所述第一导电沟道在所述基板上的正投影。
  11. 一种阵列基板，其包括：
    基板；
    第一栅电极，所述第一栅电极设置在所述基板上；
    第一绝缘层，所述第一绝缘层设置在所述第一栅电极上，且所述第一绝缘层设有第一通孔；
    第一电极，所述第一电极设置在所述第一绝缘层上；
    第二绝缘层，所述第二绝缘层设置在所述第一绝缘层上，并覆盖所述第一电极，且所述第二绝缘层设有第二通孔以及第三通孔，所述第一通孔与所述第二通孔连通；
    第二栅电极，所述第二栅电极设置在所述第一通孔以及所述第二通孔内，并与所述第一栅电极连接；
    第一导电沟道，所述第一导电沟道设置在所述第三通孔内，并与所述第一电极连接；
    第二电极，所述第二电极设置在所述第二绝缘层上，并与所述第一导电沟道连接；其中，
    所述第一电极在所述基板上的正投影覆盖所述第一导电沟道在所述基板上的正投影；
    所述第一电极为源电极，所述第二电极为漏电极。
  12. 根据权利要求11所述的阵列基板，其中，所述阵列基板还包括第一连接电极，所述第一导电沟道上设有第四通孔，所述第一连接电极设置在第四通孔内，所述第一连接电极的一端与所述第一电极连接。
  13. 根据权利要求12所述的阵列基板，其中，所述第一电极的第一面与所述第一导电沟道的第一面相贴合连接。
  14. 根据权利要求11所述的阵列基板，其中，所述阵列基板还包括第二导电沟道，所述第二绝缘层设有第五通孔，所述第二导电沟道设置在所述第五通孔内，所述第二导电沟道与所述第一导电沟道连接，且所述第二导电沟道位于所述第一电极与所述第二栅电极之间，所述第二导电沟道与所述第二栅电极相绝缘。
  15. 根据权利要求14所述的阵列基板，其中，所述第二导电沟道的一端与所述第一电极连接；
    和/或，所述第二导电沟道的另一端与所述第二电极连接。
  16. 根据权利要求14所述的阵列基板，其中，所述第一导电沟道和第二导电沟道层叠设置。
  17. 根据权利要求14所述的阵列基板，其中，所述阵列基板还包括第二连接电极，所述第二连接电极设在所述第一导电沟道上，所述第二电极设在所述第二连接电极上，所述第二栅电极在层面延伸方向的正投影覆盖所述第二连接电极在层面延伸方向的正投影。
  18. 根据权利要求17所述的阵列基板，其中，所述第二导电沟道位于所述第二连接电极与所述第二栅电极之间。
  19. 根据权利要求18所述的阵列基板，其中，所述第二电极覆盖在所述第二导电沟道上。
PCT/CN2021/140458 2021-12-17 2021-12-22 阵列基板及显示面板 Ceased WO2023108754A1 (zh)

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