WO2023108446A1 - 一种屏蔽栅半导体器件结构制备方法及屏蔽栅半导体器件结构 - Google Patents

一种屏蔽栅半导体器件结构制备方法及屏蔽栅半导体器件结构 Download PDF

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WO2023108446A1
WO2023108446A1 PCT/CN2021/138151 CN2021138151W WO2023108446A1 WO 2023108446 A1 WO2023108446 A1 WO 2023108446A1 CN 2021138151 W CN2021138151 W CN 2021138151W WO 2023108446 A1 WO2023108446 A1 WO 2023108446A1
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Prior art keywords
oxide layer
source
trench
polysilicon
trenches
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PCT/CN2021/138151
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English (en)
French (fr)
Inventor
乐双申
何增谊
张立波
吴兴敏
袁晴雯
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上海韦尔半导体股份有限公司
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Priority to JP2023548787A priority Critical patent/JP2024506363A/ja
Priority to KR1020247001285A priority patent/KR20240019360A/ko
Publication of WO2023108446A1 publication Critical patent/WO2023108446A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

Definitions

  • the embodiments of the present application belong to the technical field of integrated circuit technology, and in particular relate to a method for preparing a shielded gate semiconductor device structure and a shielded gate semiconductor device structure.
  • the on-resistance and parasitic capacitance of a power MOSFET are contradictory parameters.
  • the area of the silicon chip must be increased; the increase in the area of the silicon chip leads to an increase in the parasitic capacitance. Therefore, for a certain area of silicon chip, Only by adopting new process technology can the parasitic capacitance be reduced, shielding technology shield gate semiconductor device (Shield Gate Trench MOSFET) solves the contradiction between on-resistance and parasitic capacitance very well.
  • the other parts are standard power MOSFETs using Trench technology.
  • the gate is divided into upper and lower parts.
  • the lower part is shielded with some special materials, and the lower part is connected to the upper part of the gate internally.
  • the shielding layer of the lower part of the gate is connected to the source, thereby reducing the parasitic Miller capacitance of the drain gate, greatly reducing the duration of the Miller plateau during the switching process, and reducing the switching loss.
  • this structure changes the shape of the internal electric field and further changes the traditional triangular electric field into a more compressed trapezoidal electric field, which can further reduce the thickness of the epitaxial layer, reduce the on-resistance, and reduce the thermal resistance.
  • the trench must be etched deeper, and the thickness of the oxide layer at the bottom of the trench is relatively thick; the higher the device voltage, the deeper the depth of the trench and the oxide layer at the bottom of the trench The thicker the thickness, this will lead to the number of oxygen atoms reaching the bottom of the trench during the process of growing the thermal oxide layer in the deep trench.
  • the difference in crystallographic orientation at the bottom of the trench results in a thinner oxide layer at the bottom corners. In this way, the difference between the thickness of the oxide layer on the top of the semiconductor material between the trenches and the thickness of the oxide layer at the corners of the trenches is large, which brings great troubles to product design and subsequent processes.
  • the oxide layer at the bottom of the trench is first thermally oxidized to grow the first oxide layer, and then a second oxide layer is deposited to solve this problem.
  • the oxide layer of the source polysilicon lead-out region will also be etched together when the thick oxide layer is etched.
  • the gate polysilicon will enter the pits when the gate polysilicon is deposited, the subsequent process cannot completely remove the gate polysilicon in the pits, and there is a gate-source short circuit
  • the embodiments of the present application provide a method for preparing a shielded gate semiconductor device structure and a shielded gate semiconductor device structure.
  • the embodiment of the present application provides a method for manufacturing a shielded gate semiconductor device, the method comprising:
  • a fourth oxide layer is formed on the upper surface of the semiconductor material layer, the exposed surface of the trench in the cell region, the exposed surface of the trench in the source lead-out region, and the exposed surface of the source polysilicon;
  • the first oxide layer is formed by thermal growth
  • the second oxide layer is formed by chemical vapor deposition.
  • the total thickness of the first oxide layer and the second oxide layer is between 1000A-8000A, and the ratio of the thickness of the first oxide layer to the thickness of the second oxide layer is between 0.2-1.8.
  • the etching rate of the first oxide layer is lower than the etching rate of the second oxide layer.
  • the cell region trench After the etching removes the surface of the semiconductor material layer, the first oxide layer and the second oxide layer in the cell region trench and the source lead-out region trench, the cell region trench
  • the height difference between the top of the remaining source polysilicon and the top and bottom of the second oxide layer in the trench of the corresponding cell region is between 5000A and 15000A, and the top of the remaining source polysilicon in the trench of the source lead-out region is the same as the second oxide layer in the trench of the corresponding source lead-out region.
  • the height difference between the top and the bottom of the dioxide layer is 3000A ⁇ 12000A.
  • the etching removes the semiconductor material layer between the trenches, and after part of the source polysilicon in the trenches in the cell region and the trenches in the source lead-out region, the remaining source polysilicon in the trenches in the cell region
  • the height difference from the top of the polysilicon to the top and bottom of the second oxide layer is between 500A and 1500A, and the height difference between the top of the remaining source polysilicon in the trench of the source lead-out region and the top and bottom of the second oxide layer is between 0A and 1000A.
  • the thickness of the semiconductor material layer between the grooves is etched and removed between 3000A and 10000A.
  • the third oxide layer is grown at a temperature of 950°C to 1100°C with a thickness of 200A to 1000A
  • the fourth oxide layer is grown at a temperature of 950°C to 1100°C with a thickness of 200A to 1200A.
  • the embodiment of the present application provides a method for manufacturing a shielded gate semiconductor device structure, by adding the following steps between the process of source polysilicon deposition and gate polysilicon oxidation: etching to remove semiconductor The surface of the material layer, the first oxide layer and the second oxide layer in the groove of the cell region and the source lead-out region; etching and removal of the semiconductor material layer between the grooves, the groove of the cell region and the source lead-out region Part of the source polysilicon in the trench; the third oxide layer is formed on the upper surface of the semiconductor material layer, the exposed surface of the trench in the cell area, the exposed surface of the trench in the source lead-out area, and the exposed surface of the source polysilicon, and then the third oxide layer is removed On the upper surface of the semiconductor material layer, the exposed surface of the trench in the cell region, the exposed surface of the trench in the source lead-out region, and the exposed surface of the source polysilicon respectively form a fourth oxide layer; depositing gate polysilicon, etching and removing
  • the embodiment of the present application removes the gate polysilicon by etching until the gate polysilicon in the trench of the source lead-out region is completely etched, which can avoid the problem that the gate polysilicon in the source lead-out region remains on the sidewall of the trench in the source lead-out region, and avoid Risk of gate-to-source short circuit, improving yield and reliability.
  • the embodiment of the present application also provides a shielded gate semiconductor device structure, which is prepared and obtained by the above-mentioned preparation method, and the structure includes:
  • the cell area groove, the inner surface of the lower part of the cell area groove is provided with the second oxide layer and the first oxide layer in sequence from the outside to the inside, and the fourth oxide layer is provided on the inner surface of the upper part of the cell area groove.
  • the source polysilicon is arranged in the space surrounded by the oxide layer, and the gate polysilicon is arranged in the space surrounded by the fourth oxide layer.
  • the top surface of the source polysilicon is provided with a fourth oxide layer, and the gate polysilicon covers the top of the source polysilicon. surface;
  • a trench in the source lead-out region, the inner surface of the trench in the source lead-out region is provided with a first oxide layer and a second oxide layer, and the space surrounded by the second oxide layer is provided with source polysilicon, and the top surface of the source polysilicon is provided with a fourth oxide layer;
  • the top of the second oxide layer in the trench of the cell region and the trench of the source lead-out region is lower than the top of the first oxide layer.
  • the total thickness of the first oxide layer and the second oxide layer is between 1000A-8000A.
  • the thickness of the fourth oxide layer is between 200 ⁇ and 1200 ⁇ .
  • the shielded gate semiconductor device structure provided by the second aspect has the same beneficial effects as the method for manufacturing a shielded gate semiconductor device structure provided by the first aspect, and will not be repeated here.
  • FIG. 1 is a schematic structural diagram of a shielded gate semiconductor device prepared by a preparation process of the prior art
  • FIG. 2 is a flowchart of a method for manufacturing a shielded gate semiconductor device provided in an embodiment of the present application
  • Figure 3-12 is a schematic structural diagram corresponding to each process step of the embodiment of the present application.
  • FIG. 13 is a schematic diagram of a device structure including a shielded gate semiconductor device structure according to an embodiment of the present application.
  • FIG. 1 is a shielded gate semiconductor device structure prepared by the prior art preparation process.
  • the specific preparation method steps of the shielded gate semiconductor device structure shown in FIG. 1 are as follows:
  • Step S01 First, photolithographically etch on the epitaxial layer to form a plurality of cell region trenches and source lead-out region trenches, and then sequentially form cell region trenches and the inner surface of the source lead-out region trenches from outside to inside the second oxide layer and the first oxide layer;
  • Step S02 depositing source polysilicon in the grooves of the cell region and the source lead-out region, and then etching the source polysilicon on the surface of the semiconductor material layer until no source polysilicon remains on the surface of the semiconductor material layer.
  • the source polysilicon is photolithographically etched to remove the photoresist;
  • Step S03 etching and removing the surface of the semiconductor material layer, the first oxide layer and the second oxide layer in the cell region trenches and the source lead-out region trenches;
  • Step S04 forming a third oxide layer on the upper surface of the semiconductor material layer, the exposed surface of the trench in the cell region, the exposed surface of the trench in the source lead-out region, and the exposed surface of the source polysilicon, and then removing the third oxide layer;
  • Step S05 forming a fourth oxide layer on the upper surface of the semiconductor material layer, the exposed surface of the trench in the cell region, the exposed surface of the trench in the source lead-out region, and the exposed surface of the source polysilicon;
  • Step S06 depositing gate polysilicon in the trench of the cell region and the trench of the source lead-out region;
  • Step S07 etching the gate polysilicon on the surface of the semiconductor material layer.
  • the shielded gate semiconductor device has both the cell region and the source lead-out region, when the total thickness of the first oxide layer and the second oxide layer exceeds 1000A, and the second oxide layer occupies When the total thickness is higher, due to the faster etching rate of the second oxide layer, when the first oxide layer and the second oxide layer are etched, the first oxide layer and the second oxide layer in the source lead-out region It will also be etched together, so pits 21 will be generated on the side walls of the trenches in the source lead-out region, and will be deposited into the pits 21 when the gate polysilicon is deposited, and the gate in the pits 21 cannot be completely removed by subsequent processes. Polysilicon, so there is a higher risk of gate and source short circuits, which leads to uncontrollable yield risks and unavoidable reliability risks of shielded gate semiconductor devices.
  • FIG. 2 is a method for fabricating a shielded gate semiconductor device structure provided by an embodiment of the present application. The method includes:
  • Step S21 forming a second oxide layer and a first oxide layer sequentially from outside to inside on the inner surface of the trench in the cell region and the trench in the source lead-out region;
  • Step S22 depositing source polysilicon in the spaces surrounded by the second oxide layer in the trenches of the cell region and the trenches of the source lead-out region;
  • Step S23 etching and removing the source polysilicon on the surface of the semiconductor material layer and selectively etching and removing part of the source polysilicon located in the space above the trench in the cell region;
  • Step S24 etching and removing the surface of the semiconductor material layer, the first oxide layer and the second oxide layer in the cell region trenches and the source lead-out region trenches;
  • Step S25 etching and removing the semiconductor material layer between the trenches, part of the source polysilicon in the trenches in the cell region and the trenches in the source lead-out region;
  • Step S26 forming a third oxide layer on the upper surface of the semiconductor material layer, the exposed surface of the trench in the cell region, the exposed surface of the trench in the source lead-out region, and the exposed surface of the source polysilicon, and then removing the third oxide layer;
  • Step S27 forming a fourth oxide layer on the upper surface of the semiconductor material layer, the exposed surface of the trench in the cell region, the exposed surface of the trench in the source lead-out region, and the exposed surface of the source polysilicon;
  • Step S28 depositing gate polysilicon in the trenches of the cell region and the trenches of the source lead-out region;
  • Step S29 etching and removing the gate polysilicon on the surface of the semiconductor material layer, and selectively etching and removing the gate polysilicon located in the trench of the source lead-out region until no gate polysilicon remains in the trench of the source lead-out region.
  • the process of forming the cell region trench 32 and the source lead-out region 31 trench on the semiconductor material layer 33 is a process well-known to those skilled in the art, and will not be repeated here.
  • the semiconductor material layer It can be the substrate 33 or the epitaxial layer 33.
  • the cell region trench 32 and the source lead-out region trench 31 are formed by photolithography directly on the semiconductor material layer 33, the cell region trench 32 is formed by a thermal growth process.
  • first oxide layer 35 and second oxide layer 34 are called thick oxide layers, and the total thickness of first oxide layer 35 and second oxide layer 34 is between 1000A-8000A, the thickness of first oxide layer 35 and the thickness of second oxide layer 34
  • the ratio of is between 0.2 and 1.8, and generally the number of trenches 32 in the cell region is more than that of the trenches 31 in the source lead-out region.
  • the spaces formed by the second oxide layer 34 in the trenches 32 of the cell region and the trenches 31 of the source lead-out region respectively correspond to the deposition of source polysilicon 41, and then the source polysilicon 41 is Etch back until the top of the source polysilicon 41 is not higher than the top of the trench, that is to say, etch back the source polysilicon 41 on the surface of the polysemiconductor material layer 33 so that there is no source polysilicon 41 on the surface of the semiconductor material layer 33 .
  • photoresist 61 is placed on the source lead-out region, and the source polysilicon 41 in the upper space of the trench 32 in the cell area is photoetched, and part of the source polysilicon 41 is left in the cell area. In the trench 32, the photoresist 61 is subsequently removed.
  • the first oxide layer 35 and the second oxide layer 34 located in the upper space of the cell region trench 32 and the source lead-out region 31 and the surface of the semiconductor material layer 33 are removed by etching, because the first oxide layer
  • the etching rate of 35 is lower than the etching rate of the second oxide layer 34.
  • the top of the first oxide layer is higher than the top of the second oxide layer 34, and the first oxide layer located in the trench 32 of the cell area is removed by etching.
  • the height difference between the top of the remaining source polysilicon 41 in the trench 32 in the cell region and the top and bottom of the second oxide layer 34 in the trench 32 in the corresponding cell region is between 5000A and 15000A
  • the source The height difference between the top of the remaining source polysilicon 41 in the trench 31 of the lead-out region and the top and bottom of the second oxide layer 34 in the trench 31 of the corresponding source lead-out region is between 3000A and 12000A.
  • the semiconductor material layer 33 between the trenches is removed by etching, part of the source polysilicon in the trench 32 in the cell region and the trench 31 in the source lead-out region, and the source polysilicon in the trench 32 in the cell region
  • the height difference between the top of the polysilicon 41 and the top and bottom of the second oxide layer 34 is between 500A and 1500A
  • the height difference between the top of the source polysilicon and the top and bottom of the second oxide layer in the trench of the source lead-out area is between 0A and 1000A.
  • the etched-back thickness of the semiconductor layer 33 between the trenches is between 3000A and 10000A, and the thickness of the etched-back semiconductor layer 33 between the trenches depends specifically on the distance from the bottom of the second oxide layer 34 in the trench 32 in the source lead-out region to the semiconductor layer 33 between the trenches. Depends on height difference.
  • the source A third oxide layer (not shown) is formed on the exposed surface of the pole polysilicon 41, and then the third oxide layer (not shown) is removed.
  • the third oxide layer (not shown) can process the morphology of the surface it contacts and improve the The purity of the contact surface, the thickness of the third oxide layer is 200A ⁇ 1000A, and the process temperature is between 950°C ⁇ 1100°C.
  • a fourth oxide layer 91 is re-formed on the inner surface of the groove 31 and the top of the source polysilicon 41.
  • the thickness of the fourth oxide layer 91 is 200A-1200A, and the process temperature is between 950°C-1100°C.
  • the gate polysilicon 10 is deposited in the upper space of the trench 32 in the cell region.
  • the process of depositing the polysilicon 10 is a well-known technique in the art, and will not be repeated here.
  • the gate polysilicon 10 is etched back until no gate polysilicon 10 remains on the surface of the semiconductor material layer 33, and the thickness of the remaining gate polysilicon 93 in the trench 31 of the source lead-out region is 0A. Between -5000A.
  • photoresist 12 is applied, and the remaining gate polysilicon 93 in the upper part of the trench 31 in the source extraction region is photolithographically etched until the remaining portion of the trench 31 in the source extraction region The gate polysilicon 93 is completely etched, and then the photoresist 12 is removed. At this time, the remaining gate polysilicon 93 is not left in the trench 31 of the source lead-out area.
  • the gate polysilicon is removed by etching until the source lead-out area
  • the gate polysilicon in the trench is completely etched, which can avoid the problem that the gate polysilicon in the source lead-out region remains on the side wall of the trench in the source lead-out region, avoid the risk of gate-source short circuit, and improve yield and reliability.
  • the structure of the shielded gate semiconductor device prepared through the above process steps in the embodiment of the present application is shown in Figure 12.
  • the structure of the shielded gate semiconductor device includes:
  • the cell area groove 32, the inner surface of the lower part of the cell area groove 31 is provided with the second oxide layer 34 and the first oxide layer 35 sequentially from outside to inside, and the upper part of the inner surface of the cell area groove 31 is provided with a fourth oxide layer.
  • Oxide layer 91, the source polysilicon 41 is arranged in the space surrounded by the second oxide layer 34, the gate polysilicon 10 is arranged in the space surrounded by the fourth oxide layer 91, and the top surface of the source polysilicon 41 is provided with a fourth An oxide layer 41, the gate polysilicon 10 covers the top surface of the source polysilicon 41;
  • the trench 31 in the source lead-out region, the inner surface of the trench 31 in the source lead-out region is provided with a first oxide layer 35 and a second oxide layer 34, and the space surrounded by the second oxide layer 34 is provided with source polysilicon, 41, and the source A fourth oxide layer 91 is provided on the top surface of the polysilicon 41;
  • the top of the second oxide layer 34 in the cell region trench 32 and the source lead-out region trench 31 is lower than the top of the first oxide layer 35, and the total thickness of the first oxide layer 35 and the second oxide layer 34 is at 1000 ⁇ . Between -8000A, the thickness of the fourth oxide layer 91 is between 200A ⁇ 1200A.
  • a layer of oxide layer 16 is formed on the surface of the entire semiconductor material layer 33, ion implantation is performed sequentially and advanced to form a well 13, photolithography and an implanted region 14 is formed in the well 13, and dielectric layers 15 and 20 are deposited to form, photolithography Contact holes 17 and 18 are formed by etching, and ions are implanted and activated in the contact holes 17 and 18, and then multiple layers of metal are deposited in the contact holes 17 and 18 to form extraction electrodes, and finally a device with a shielded gate semiconductor device structure is formed.
  • the embodiment of the present application provides a shielded gate semiconductor device structure to avoid the problem that the gate polysilicon in the source lead-out region remains on the sidewall of the trench in the source lead-out region, avoid the risk of gate-source short circuit, and improve yield and reliability.

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Abstract

本申请实施例提供了一种屏蔽栅半导体器件结构制备方法及屏蔽栅半导体器件结构，通过在源极多晶硅淀积到栅极多晶硅氧化这段工艺之间采用增加以下步骤：刻蚀去除位于元胞区沟槽中上部空间及半导体材料层表面的第一氧化层，第二氧化层及沟槽之间部分半导体材料层；刻蚀去除栅极多晶硅直到源极引出区沟槽内剩余栅极多晶硅厚度到达预设厚度；选择性刻蚀去除位于源极引出区沟槽中剩余栅极多晶硅直到源极引出区沟槽中无栅极多晶硅残留，随后去除光刻胶，本申请实施例通过刻蚀去除栅极多晶硅直到源极引出区沟槽中的栅极多晶硅刻蚀完全，可以避免源极引出区栅极多晶硅在源极引出区沟槽侧壁残留的问题，避免栅极源极短路的风险，提高良率和可靠性。

Description

一种屏蔽栅半导体器件结构制备方法及屏蔽栅半导体器件结构 技术领域
本申请各实施例属于集成电路工艺技术领域，特别是涉及一种屏蔽栅半导体器件结构制备方法及屏蔽栅半导体器件结构。
 背景技术
功率MOSFET的导通电阻和寄生电容是一个相互矛盾的参数，为了减小导通电阻，就必须增加硅片面积；硅片面积增加，又导致寄生电容的增加，因此对于一定的面积硅片，只有采用新的工艺技术，才能减小寄生电容，屏蔽技术屏蔽栅半导体器件（Shield Gate Trench MOSFET）很好的解决了导通电阻和寄生电容之间的矛盾。
除了栅极结构，其它的部分就是标准的采用Trench工艺的功率MOSFET，栅极被分割成上下两个部分，下部分用一些特殊的材料屏蔽起来，下部分在内部和上部分栅极相连，而下部分栅极的屏蔽层被连接到源极，从而减小漏极栅极寄生米勒电容，极大的减小了开关过程中米勒平台的持续时间，降低了开关损耗。同时，这种结构由于改变了内部电场的形态，将传统的三角形电场进一步的变为更为压缩的梯形电场，可以进一步减小外延层的厚度，降低导通电阻，减小热阻。
但是根据屏蔽栅半导体器件器件的特殊性，沟槽必须刻蚀较深，同时沟槽底部的氧化层厚度也比较厚；器件电压越高，沟槽的深度就越深同时沟槽底部的氧化层厚度就越厚，这样就会导致深沟槽内生长热氧化层的过程中氧原子到达沟槽底部的数量没有表面的多，导致越靠近沟槽底部氧化层的厚度就越薄，而且由于沟槽底部晶向的差异会导致底部转角处的氧化层更加薄。这样就会得到沟槽之间的半导体材料顶部的氧化层厚度与沟槽转角处的氧化层厚度差异大，给产品设计和后续的工艺带来比较大的困扰。
为了解决上述技术问题，如图1所示，现有技术中将沟槽底部的氧化层采用先热氧化生长第一氧化层，然后再淀积一层第二氧化层的方法来解决此问题，但是当厚氧化层的厚度超过预设厚度时，而且第二氧化层占总氧化层厚度越高的情况下，在厚氧化层刻蚀时源极多晶硅引出区的氧化层也会被一起刻蚀，且在源极引出区的沟槽侧壁产生凹坑，在栅极多晶硅淀积时栅极多晶硅会进入凹坑，后续工艺无法彻底去除凹坑中的栅极多晶硅，存在栅极源极短路的风险就越高，导致良率风险不可控。
 技术解决方案
本申请实施例为了部分解决或者缓解现有技术中的技术问题，本申请实施例提供了一种屏蔽栅半导体器件结构制备方法及屏蔽栅半导体器件结构。
本申请实施例为部分解决或缓解现有技术的技术问题而采用的一个技术方案是：本申请实施例提供了一种屏蔽栅半导体器件制备方法，所述方法包括：
在元胞区沟槽和源极引出区沟槽内表面分别从外到内依次形成第二氧化层和第一氧化层；
在元胞区沟槽和源极引出区沟槽中第二氧化层包围形成的空间分别沉积源极多晶硅；
刻蚀去除半导体材料层表面的源极多晶硅并选择性刻蚀去除位于元胞区沟槽上部空间的部分源极多晶硅；
刻蚀去除半导体材料层表面，元胞区沟槽和源极引出区沟槽中的第一氧化层和第二氧化层；
刻蚀去除沟槽之间的半导体材料层，元胞区沟槽及源极引出区沟槽中部分源极多晶硅；
在半导体材料层上表面，元胞区沟槽裸露表面，源极引出区沟槽裸露表面，源极多晶硅裸露表面分别形成第三氧化层，随后去除第三氧化层；
在半导体材料层上表面，元胞区沟槽裸露表面，源极引出区沟槽裸露表面，源极多晶硅裸露表面分别形成第四氧化层；
在元胞区沟槽和源极引出区沟槽中沉积栅极多晶硅；
刻蚀去除半导体材料层表面的栅极多晶硅，并选择性刻蚀去除位于源极引出区沟槽中栅极多晶硅直到源极引出区沟槽中无栅极多晶硅残留。
作为本申请的一优选实施例，第一氧化层通过热生长形成，第二氧化层通过化学气相沉积法形成。
作为本申请的一优选实施例，第一氧化层和第二氧化层的总厚度处于1000A-8000A之间，且第一氧化层厚度与第二氧化层厚度的比值处于0.2~1.8之间。
作为本申请的一优选实施例，第一氧化层的刻蚀速率小于第二氧化层的刻蚀速率。
作为本申请的一优选实施例，所述刻蚀去除半导体材料层表面，元胞区沟槽和源极引出区沟槽中的第一氧化层和第二氧化层后，元胞区沟槽中剩余源极多晶硅顶端与对应元胞区沟槽中第二氧化层顶端底部高度差处于5000A~15000A之间，源极引出区沟槽中剩余源极多晶硅顶端与对应源极引出区沟槽中第二氧化层顶端底部的高度差处于3000A~12000A。
作为本申请的一优选实施例，所述刻蚀去除沟槽之间的半导体材料层，元胞区沟槽及源极引出区沟槽中部分源极多晶硅后，元胞区沟槽中剩余源极多晶硅顶部到第二氧化层顶端底部高度差处于500A~1500A之间，源极引出区沟槽中剩余源极多晶硅顶部到第二氧化层顶端底部高度差处于0A~1000A之间。
作为本申请的一优选实施例，刻蚀去除沟槽之间的半导体材料层的厚度处于3000A~10000A之间。
作为本申请的一优选实施例，在温度950℃~1100℃生长200A~1000A厚度的第三氧化层，在温度950℃~1100℃生长200A~1200A厚度的第四氧化层。
与现有技术相比，本申请实施例提供了一种屏蔽栅半导体器件结构的制备方法，通过在源极多晶硅淀积到栅极多晶硅氧化这段工艺之间采用增加以下步骤：刻蚀去除半导体材料层表面，元胞区沟槽和源极引出区沟槽中的第一氧化层和第二氧化层；刻蚀去除沟槽之间的半导体材料层，元胞区沟槽及源极引出区沟槽中部分源极多晶硅；在半导体材料层上表面，元胞区沟槽裸露表面，源极引出区沟槽裸露表面，源极多晶硅裸露表面分别形成第三氧化层，随后去除第三氧化层；在半导体材料层上表面，元胞区沟槽裸露表面，源极引出区沟槽裸露表面，源极多晶硅裸露表面分别形成第四氧化层；在元胞区沟槽和源极引出区沟槽中沉积栅极多晶硅，刻蚀去除半导体材料层表面的栅极多晶硅，并选择性刻蚀去除位于源极引出区沟槽中栅极多晶硅直到源极引出区沟槽中无栅极多晶硅残留。本申请实施例通过刻蚀去除栅极多晶硅直到源极引出区沟槽中的栅极多晶硅刻蚀完全，可以避免源极引出区栅极多晶硅在源极引出区沟槽侧壁残留的问题，避免栅极源极短路的风险，提高良率和可靠性。
第二方面，本申请实施例还提供了一种屏蔽栅半导体器件结构，通过上述所述的制备方法制备获取，所述结构包括：
元胞区沟槽，元胞区沟槽下部分内表面从外到内依次设置有第二氧化层和第一氧化层，元胞区沟槽上部分内表面设置有第四氧化层，在第二氧化层围成的空间中设置有源极多晶硅，在第四氧化层围成的空间中设置有栅极多晶硅，源极多晶硅顶端表面设置有第四氧化层，栅极多晶硅覆盖源极多晶硅顶端表面；
源极引出区沟槽，源极引出区沟槽内表面设置有第一氧化层和第二氧化层且第二氧化层围成的空间设置有源极多晶硅，源极多晶硅顶端表面设置有第四氧化层；
其中，在元胞区沟槽和源极引出区沟槽中的第二氧化层顶端低于第一氧化层顶端。
作为本申请的一优选实施例，第一氧化层和第二氧化层的总厚度处于1000A-8000A之间。
作为本申请的一优选实施例，第四氧化层的厚度处于200A~1200A之间。
与现有技术相比，第二方面提供的屏蔽栅半导体器件结构与第一方面提供的一种屏蔽栅半导体器件结构制备方法的有益效果相同，在此不再赘述。
 附图说明
此处所说明的附图用来提供对本申请的进一步理解，构成本申请的一部分，本申请的示意性实施例及其说明用于解释本申请，并不构成对本申请的不当限定。后文将参照附图以示例性而非限制性的方式详细描述本申请的一些具体实施例。附图中相同的附图标记标示了相同或类似的部件或部分，本领域技术人员应该理解的是，这些附图未必是按比例绘制的，在附图中：
图1为通过现有技术的制备工艺制备的屏蔽栅半导体器件结构示意图；
图2为本申请实施例提供的屏蔽栅半导体器件的制备方法的流程图；
图3-12为本申请实施例每个工艺流程步骤对应的结构示意图；
图13为本申请实施例包含屏蔽栅半导体器件结构的器件结构示意图。
 本发明的实施方式
为了使本技术领域的人员更好地理解本申请方案，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分的实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都应当属于本申请保护的范围。
如图1所示，图1为通过现有技术制备工艺制备的屏蔽栅半导体器件结构，图1所示的屏蔽栅半导体器件结构的具体制备方法步骤如下：
步骤S01，首先在外延层上光刻刻蚀形成多个元胞区沟槽和源极引出区沟槽，随后在元胞区沟槽和源极引出区沟槽内表面从外到内依次形成第二氧化层和第一氧化层；
步骤S02，元胞区沟槽和源极引出区沟槽中沉积源极多晶硅，随后对半导体材料层表面的源极多晶硅进行一次刻蚀直到半导体材料层表面无源极多晶硅残留，对元胞区源极多晶硅进行光刻刻蚀，去除光刻胶；
步骤S03，刻蚀去除半导体材料层表面，元胞区沟槽和源极引出区沟槽中的第一氧化层和第二氧化层；
步骤S04，在半导体材料层上表面，元胞区沟槽裸露表面，源极引出区沟槽裸露表面，源极多晶硅裸露表面分别形成第三氧化层，随后去除第三氧化层；
步骤S05，在半导体材料层上表面，元胞区沟槽裸露表面，源极引出区沟槽裸露表面，源极多晶硅裸露表面分别形成第四氧化层；
步骤S06，在元胞区沟槽和源极引出区沟槽中沉积栅极多晶硅；
步骤S07，对半导体材料层表面的栅极多晶硅进行刻蚀。
从上述工艺流程上可以看出，由于屏蔽栅半导体器件中既有元胞区又有源极引出区，当第一氧化层和第二氧化层的总厚度超过1000A时，而且第二氧化层占总厚度越高的情况下，由于第二氧化层的刻蚀速率较快，在对第一氧化层和第二氧化层进行刻蚀时，源极引出区的第一氧化层和第二氧化层也会被一起刻蚀，所以在源极引出区的沟槽侧壁会产生凹坑21，在栅极多晶硅淀积时会沉积进凹坑21，后续工艺无法彻底去除凹坑21中的栅极多晶硅，所以存在栅极和源极短路的风险就越高，进而导致屏蔽栅半导体器件良率风险不可控同时可靠性风险不可避免的问题出现。
如图2所示，图2为本申请实施例提供的一种屏蔽栅半导体器件结构制备方法，所述方法包括：
步骤S21，在元胞区沟槽和源极引出区沟槽内表面分别从外到内依次形成第二氧化层和第一氧化层；
步骤S22，在元胞区沟槽和源极引出区沟槽中第二氧化层包围形成的空间分别沉积源极多晶硅；
步骤S23，刻蚀去除半导体材料层表面的源极多晶硅并选择性刻蚀去除位于元胞区沟槽上部空间的部分源极多晶硅；
步骤S24，刻蚀去除半导体材料层表面，元胞区沟槽和源极引出区沟槽中的第一氧化层和第二氧化层；
步骤S25，刻蚀去除沟槽之间的半导体材料层，元胞区沟槽及源极引出区沟槽中部分源极多晶硅；
步骤S26，在半导体材料层上表面，元胞区沟槽裸露表面，源极引出区沟槽裸露表面，源极多晶硅裸露表面分别形成第三氧化层，随后去除第三氧化层；
步骤S27，在半导体材料层上表面，元胞区沟槽裸露表面，源极引出区沟槽裸露表面，源极多晶硅裸露表面分别形成第四氧化层；
步骤S28，在元胞区沟槽和源极引出区沟槽中沉积栅极多晶硅；
步骤S29，刻蚀去除半导体材料层表面的栅极多晶硅，并选择性刻蚀去除位于源极引出区沟槽中栅极多晶硅直到源极引出区沟槽中无栅极多晶硅残留。
参考图2和图3，在半导体材料层33上形成元胞区沟槽32和源极引出区31沟槽的工艺都是本领域技术人员比较熟知的工艺，在此不再赘述，半导体材料层可以为衬底33或外延层33，当直接在半导体材料层33上进行光刻刻蚀形成元胞区沟槽32和源极引出区沟槽31后，通过热生长工艺在元胞区沟槽32和源极引出区沟槽31内表面先生成一层第一氧化层35，随后再通过化学气相沉积工艺在第一氧化层35的外表面形成一层第二氧化层34，其中，第一氧化层35和第二氧化层34被称作厚氧化层，且第一氧化层35和第二氧化层34的总厚度处于1000A-8000A之间，第一氧化层35厚度与第二氧化层34厚度的比值处于0.2~1.8之间，一般元胞区沟槽32数量都比源极引出区沟槽31多。
参考图2，图4和图5，在元胞区沟槽32和源极引出区沟槽31中第二氧化层34包围形成的空间分别对应沉积源极多晶硅41，随后对源极多晶硅41进行回刻直到源极多晶硅41顶端不高于沟槽顶部，也就是说多半导体材料层33表面的源极多晶硅41进行回刻，以使半导体材料层33表面无源极多晶硅41。
参考图2和图6所示，在源极引出区上光刻胶61，对元胞区沟槽32中上部空间的源极多晶硅41进行光刻，并留部分源极多晶硅41至元胞区沟槽32中，随后去除光刻胶61。
参考图2和图7，刻蚀去除位于元胞区沟槽32和源极引出区31中上部空间及半导体材料层33表面的第一氧化层35和第二氧化层34，由于第一氧化层35的刻蚀速率小于第二氧化层34的刻蚀速率，刻蚀完成后第一氧化层顶端高于第二氧化层34顶端，刻蚀去除位于元胞区沟槽32中的第一氧化层35和第二氧化层34后，元胞区沟槽32中的剩余源极多晶硅41顶端与对应元胞区沟槽32中第二氧化层34顶端底部高度差处于5000A~15000A之间，源极引出区沟槽31内剩余源极多晶硅41顶端与对应源极引出区沟槽31中第二氧化层34顶端底部的高度差处于3000A~12000A。
参考图1和图8所示，刻蚀去除沟槽之间的半导体材料层33，元胞区沟槽32及源极引出区沟槽31中部分源极多晶硅，元胞区沟槽32内源极多晶硅41顶部到第二氧化层34顶端底部高度差处于500A~1500A之间，源极引出区沟槽内源极多晶硅顶部到第二氧化层顶端底部高度差处于0A~1000A之间，沟槽之间半导体层33回刻厚度处于3000A~10000A之间，沟槽之间半导体层33回刻厚度具体视源极引出区沟槽32内第二氧化层34底部到沟槽之间半导体层33的高度差情况而定。
参考图2和图9所示，在图8的基础上在半导体材料层33表面，在半导体材料层33上表面，元胞区沟槽32裸露表面，源极引出区沟槽31裸露表面，源极多晶硅41裸露表面分别形成第三氧化层（未示出），随后去除第三氧化层（未示出），第三氧化层（未示出）可以处理其所接触表面的形貌及提高所接触表面的纯度，第三氧化层厚度为200A~1000A，工艺温度处于950℃~1100℃之间。
随后去除第三氧化层（未示出）后，在第三氧化层（未示出）所在的位置，即：在半导体材料层33表面，元胞区沟槽32内表面，源极引出区沟槽31内表面和源极多晶硅41顶端重新形成一层第四氧化层91，第四氧化层91厚度为200A~1200A，工艺温度处于950℃~1100℃之间。
参考图2和图10所示，在元胞区沟槽32上部空间中沉积栅极多晶硅10，沉积多晶硅10的工艺是本领域熟知技术，再此不再赘述。
参考图2和图11所示，对栅极多晶硅10进行回刻，直到半导体材料层33表面上无栅极多晶硅10残留，所述源极引出区沟槽31内剩余栅极多晶硅93厚度处于0A-5000A之间。
参考图2和图12，在图11的基础上上光刻胶12，对源极引出区沟槽31上部空间剩余栅极多晶硅93进行光刻刻蚀，直到源极引出区沟槽31的剩余栅极多晶硅93刻蚀完全，随后去除光刻胶12，此时将源极引出区沟槽31中不在残留剩余栅极多晶硅93，本申请实施例通过刻蚀去除栅极多晶硅直到源极引出区沟槽中的栅极多晶硅刻蚀完全，可以避免源极引出区栅极多晶硅在源极引出区沟槽侧壁残留的问题，避免栅极源极短路的风险，提高良率和可靠性。
本申请实施例通过上述工艺步骤制备的屏蔽栅半导体器件结构如图12所示，屏蔽栅半导体器件结构包括：
元胞区沟槽32，元胞区沟槽31下部分内表面从外到内依次设置有第二氧化层34和第一氧化层35，元胞区沟槽31上部分内表面设置有第四氧化层91，在第二氧化层34围成的空间中设置有源极多晶硅41，在第四氧化层91围成的空间中设置有栅极多晶硅10，源极多晶硅41顶端表面设置有第四氧化层41，栅极多晶硅10覆盖源极多晶硅41顶端表面；
源极引出区沟槽31，源极引出区沟槽31内表面设置有第一氧化层35和第二氧化层34，且第二氧化层34围成的空间设置有源极多晶硅,41，源极多晶硅41顶端表面设置有第四氧化层91；
其中，在元胞区沟槽32和源极引出区沟槽31中的第二氧化层34顶端低于第一氧化层35顶端，第一氧化层35和第二氧化层34的总厚度处于1000A-8000A之间，第四氧化层91的厚度处于200A~1200A之间。
随后，在整个半导体材料层33表面形成一层氧化层16，依次进行离子注入并推进形成阱13，光刻并在阱13中形成注入区14，淀积形成介质层15和20，光刻刻蚀形成接触孔17和18，在接触孔17和18中注入离子并激活，随后接触孔17和18中沉积多层金属形成引出电极，最终形成了具有屏蔽栅半导体器件结构器件。
本申请实施例提供屏蔽栅半导体器件结构避免源极引出区栅极多晶硅在源极引出区沟槽侧壁残留的问题，避免栅极源极短路的风险，提高良率和可靠性。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (10)

  1. 一种屏蔽栅半导体器件制备方法，其特征在于，所述方法包括：
    在元胞区沟槽和源极引出区沟槽内表面分别从外到内依次形成第二氧化层和第一氧化层；
    在元胞区沟槽和源极引出区沟槽中第二氧化层包围形成的空间分别沉积源极多晶硅；
    刻蚀去除半导体材料层表面的源极多晶硅并选择性刻蚀去除位于元胞区沟槽上部空间的部分源极多晶硅；
    刻蚀去除半导体材料层表面，元胞区沟槽和源极引出区沟槽中的第一氧化层和第二氧化层；
    刻蚀去除沟槽之间的半导体材料层，元胞区沟槽及源极引出区沟槽中部分源极多晶硅；
    在半导体材料层上表面，元胞区沟槽裸露表面，源极引出区沟槽裸露表面，源极多晶硅裸露表面分别形成第三氧化层，随后去除第三氧化层；
    在半导体材料层上表面，元胞区沟槽裸露表面，源极引出区沟槽裸露表面，源极多晶硅裸露表面分别形成第四氧化层；
    在元胞区沟槽和源极引出区沟槽中沉积栅极多晶硅；
    刻蚀去除半导体材料层表面的栅极多晶硅，并选择性刻蚀去除位于源极引出区沟槽中栅极多晶硅直到源极引出区沟槽中无栅极多晶硅残留。
  2. 如权利要求1所述的一种屏蔽栅半导体器件制备方法，其特征在于，第一氧化层通过热生长形成，第二氧化层通过化学气相沉积法形成。
  3. 如权利要求1所述的一种屏蔽栅半导体器件制备方法，其特征在于，第一氧化层和第二氧化层的总厚度处于1000A-8000A之间，且第一氧化层厚度与第二氧化层厚度的比值处于0.2~1.8之间。
  4. 如权利要求1至3任一项所述的一种屏蔽栅半导体器件结构制备方法，其特征在于，第一氧化层的刻蚀速率小于第二氧化层的刻蚀速率。
  5. 如权利要求1所述的一种屏蔽栅半导体器件制备方法，其特征在于，所述刻蚀去除半导体材料层表面，元胞区沟槽和源极引出区沟槽中的第一氧化层和第二氧化层后，元胞区沟槽中剩余源极多晶硅顶端与对应元胞区沟槽中第二氧化层顶端底部高度差处于5000A~15000A之间，源极引出区沟槽中剩余源极多晶硅顶端与对应源极引出区沟槽中第二氧化层顶端底部的高度差处于3000A~12000A。
  6. 如权利要求1所述的一种屏蔽栅半导体器件制备方法，其特征在于，所述刻蚀去除沟槽之间的半导体材料层，元胞区沟槽及源极引出区沟槽中部分源极多晶硅后，元胞区沟槽中剩余源极多晶硅顶部到第二氧化层顶端底部高度差处于500A~1500A之间，源极引出区沟槽中剩余源极多晶硅顶部到第二氧化层顶端底部高度差处于0A~1000A之间。
  7. 如权利要求1所述的一种屏蔽栅半导体器件制备方法，其特征在于，刻蚀去除沟槽之间的半导体材料层的厚度处于3000A~10000A之间。
  8. 如权利要求1，5-7任一项所述的一种屏蔽栅半导体器件结构制备方法，其特征在于，在温度950℃~1100℃生长200A~1000A厚度的第三氧化层，在温度950℃~1100℃生长200A~1200A厚度的第四氧化层。
  9. 一种屏蔽栅半导体器件结构，其特征在于，通过如权利要求1至9所述的制备方法制备获取，所述结构包括：
    元胞区沟槽，元胞区沟槽下部分内表面从外到内依次设置有第二氧化层和第一氧化层，元胞区沟槽上部分内表面设置有第四氧化层，在第二氧化层围成的空间中设置有源极多晶硅，在第四氧化层围成的空间中设置有栅极多晶硅，源极多晶硅顶端表面设置有第四氧化层，栅极多晶硅覆盖源极多晶硅顶端表面；
    源极引出区沟槽，源极引出区沟槽内表面设置有第一氧化层和第二氧化层且第二氧化层围成的空间设置有源极多晶硅，源极多晶硅顶端表面设置有第四氧化层；
    其中，在元胞区沟槽和源极引出区沟槽中的第二氧化层顶端低于第一氧化层顶端。
  10. 如权利要求9所述的一种屏蔽栅半导体器件结构，其特征在于，第一氧化层和第二氧化层的总厚度处于1000A-8000A之间。
PCT/CN2021/138151 2021-12-13 2021-12-15 一种屏蔽栅半导体器件结构制备方法及屏蔽栅半导体器件结构 WO2023108446A1 (zh)

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