WO2023103041A1 - 显示面板及其制备方法 - Google Patents

显示面板及其制备方法 Download PDF

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Publication number
WO2023103041A1
WO2023103041A1 PCT/CN2021/139183 CN2021139183W WO2023103041A1 WO 2023103041 A1 WO2023103041 A1 WO 2023103041A1 CN 2021139183 W CN2021139183 W CN 2021139183W WO 2023103041 A1 WO2023103041 A1 WO 2023103041A1
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WO
WIPO (PCT)
Prior art keywords
binding
substrate
area
display panel
metal layer
Prior art date
Application number
PCT/CN2021/139183
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English (en)
French (fr)
Inventor
赵斌
肖军城
林晓丹
Original Assignee
惠州华星光电显示有限公司
Tcl华星光电技术有限公司
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Application filed by 惠州华星光电显示有限公司, Tcl华星光电技术有限公司 filed Critical 惠州华星光电显示有限公司
Priority to US17/622,884 priority Critical patent/US20240038775A1/en
Publication of WO2023103041A1 publication Critical patent/WO2023103041A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body

Definitions

  • the invention relates to the field of display devices, in particular to a display panel and a preparation method thereof.
  • the existing side wire technology mainly uses silver paste silicone printing, but the resolution of the silver paste is not high, it is easy to lead to the connection between the traces, the yield rate is low, and the traces need to be separated by laser scribing. Moreover, the process stability of silver paste printing is not high, and the deployment of silver paste and the waiting time between process nodes (Queue Time, Q-Time), cleaning of mold residual silver paste, etc. Once there is an error in process control, it is easy to cause poor printing. At the same time, the adhesion of the silver paste is also closely related to the side grinding process of the glass substrate, and the glass side grinding will bring a great risk of breaking the substrate.
  • the purpose of the present invention is to provide a display panel and a preparation method to solve the problem of low stability of the silver paste silicone printing process in the prior art, low yield of the prepared side wires and the risk of fragmentation caused by glass side grinding wait.
  • the present invention provides a display panel, the display panel has a first binding area and a second binding area connected to the first binding area.
  • the display panel includes a substrate and a bonding wiring layer.
  • the thickness of the substrate in the second binding area is smaller than the thickness of the substrate in the first binding area.
  • the bonding wiring layer is disposed on the surface of the substrate in the first bonding area and the second bonding area. A side of the binding wiring layer away from the first binding area is located on the same plane as a side of the substrate away from the first binding area.
  • the substrate includes a main body and an extension.
  • the body portion is located in the first binding region.
  • the extension part is connected to the main body part and is located in the second binding region.
  • the thickness of the extension part is smaller than the thickness of the main part.
  • a surface of the main body part away from the binding wiring layer and a surface of the extension part away from the binding wiring layer are located on the same plane.
  • the bonding wiring layer includes a first metal layer and a second metal layer.
  • the first metal layer is disposed on the main body, and extends from the main body to cover the extension portion, and the second metal layer is disposed on a surface of the first metal layer away from the substrate superior.
  • the thickness of the first metal layer is smaller than the thickness of the second metal layer.
  • the sum of the thicknesses of the main body part and the first metal layer is smaller than the sum of the thicknesses of the extension part, the first metal layer and the second metal layer.
  • the material of the bonding wiring layer includes copper.
  • the display panel also has a display area, and the display area is set on a side of the first binding area away from the second binding area.
  • the display panel also includes a thin film transistor and a chip-on-chip film.
  • the thin film transistor is arranged on the substrate and located in the display area.
  • the chip-on-film extends from a surface of the extension portion away from the binding trace to a surface of the binding trace away from the main body.
  • one end of the bonding wiring layer located in the first bonding region is electrically connected to the thin film transistor.
  • the bonding wiring layer is located on a side far away from the first bonding region and is electrically connected to the COF.
  • the display panel further includes a light emitting device disposed on the thin film transistor.
  • the present invention also provides a method for preparing a display panel, which includes the following steps:
  • a substrate is provided, the substrate has a first binding region, a second binding region and a cutout region, the cutout region is connected to the second binding region, and the second binding region is away from the side of the cutout region Connected to the first binding area, the boundary between the excision area and the second binding area is a cutting line; a groove is opened on the substrate, and the cutting line is located in the groove ; forming a binding wiring layer on the substrate, the binding wiring layer covering the first binding area, the second binding area and the cut-out area and filling the groove; along the The cutting line cuts the substrate and the binding wiring layer, and removes the substrate and the binding wiring layer in the cut-off area.
  • the step of forming the bonding wiring layer on the substrate includes the following steps: forming a first metal layer on the substrate by deposition; forming a second metal layer on the first metal layer by electroplating layer.
  • the first metal layer evenly covers the groove wall and groove bottom of the groove, and the depth of the groove is smaller than the film thickness of the second metal layer.
  • the materials of the first metal layer and the second metal layer contain copper.
  • the step of forming the bonding wiring layer on the substrate further includes the following steps: forming a photoresist layer on the first metal layer; removing the photoresist layer after preparing the second metal layer and the first metal layer covered by the photoresist layer.
  • the following steps are: coating a photoresist material on a surface of the first metal layer away from the photoresist layer; The material is cured and patterned to form a photoresist layer that shields part of the first metal layer.
  • the step of cutting the substrate and the binding wiring layer along the cutting line includes: turning over the substrate, turning a surface of the substrate away from the binding wiring layer toward the cutting instrument; The cutting process separates the substrate and the bonding wire layer in the cut-off area from the substrate and the bonding wire layer in the second bonding area along the cutting line.
  • the preparation method of the display panel further includes the following steps: the substrate also has a display area, the display area is set on the side of the first binding area away from the second binding area, A thin film transistor is formed on the substrate in the display area; a surface of the substrate away from the binding wiring layer and a surface of the binding wiring away from the first binding area are covered crystal film.
  • the manufacturing method of the display panel further includes the following step: forming a light emitting device on the thin film transistor.
  • the advantages of the present invention are: the display panel and its preparation method provided in the present invention do not need to adopt the silver paste printing process, thereby solving the problems of poor process stability and yield caused by the silver paste printing process, and avoiding The risk of fragmentation caused by glass side grinding is eliminated.
  • FIG. 1 is a schematic diagram of a layered structure of a display panel in an embodiment of the present invention
  • FIG. 2 is a schematic flow diagram of a method for preparing a display panel in an embodiment of the present invention
  • FIG. 3 is a schematic diagram of the layered structure of the substrate after step S10 in the embodiment of the present invention.
  • FIG. 4 is a schematic diagram of the layered structure of the display panel after step S20 in the embodiment of the present invention.
  • FIG. 5 is a schematic diagram of the layered structure of the display panel after step S30 in the embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a layered structure of a display panel in step S40 in an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of the layered structure of the display panel after step S40 in the embodiment of the present invention.
  • FIG. 8 is a schematic diagram of a layered structure of a display panel in step S50 in an embodiment of the present invention.
  • Display panel 1 first binding area 1A;
  • Photoresist layer 30 is a photoresist layer.
  • An embodiment of the present invention provides a display panel 1, which is used to provide a display screen for an electronic device.
  • the display panel 1 has a first binding area 1A, a second binding area 1B and a display area 1C.
  • the second binding area 1B is connected to one side of the first binding area 1A
  • the display area 1C is connected to the side of the first binding area 1A away from the second binding area 1B .
  • the display panel 1 includes a substrate 10 and a bonding wiring layer 20 .
  • the substrate 10 is a rigid substrate 10, and its material may be glass, quartz, or the like.
  • the substrate 10 includes a main body 11 and an extension 12 .
  • the main body part 11 covers the first binding area 1A and the display area 1C.
  • the extension part 12 covers the second binding area 1B and is connected to one side of the main body part 11 .
  • the thickness of the main body part 11 is greater than the thickness of the extension part 12, and the bottom surface of the extension part 12 (that is, the surface of the extension part 12 away from the binding wiring layer 20) is closely aligned with the main body
  • the bottom surface of the body part 11 (that is, the surface of the body part 11 away from the binding wiring layer 20) is located on the same plane, so that the side of the body part 11 facing the extension part 12 is exposed, and at the same time, the The bottom surface of the substrate 10 is flush, which is convenient for pasting the external driver on the bottom surface of the substrate 10 .
  • the bonding wiring layer 20 is arranged on the main body 11 in the first bonding area 1A, and extends from the main body 11 to cover the second bonding area 1B. on the extension 12.
  • a side 23 of the binding wiring layer 20 away from the main body 11 (that is, away from the first binding area 1A) and the extension part 12 are away from the main body 11 (that is, away from the first binding area 1A).
  • a side surface 13 of the region 1A) is located on the same plane, so that a conductive structure is formed on the side surface of the substrate 10 .
  • binding wiring layer 20 located in the first binding area 1A is electrically connected to the display device in the display area 1C, and the binding wiring layer 20 is located at one end of the side surface of the substrate 10 It is electrically connected to an external driver, and the external driver is connected to the display device through the bonding wiring layer 20, so as to transmit display signals to the display area 1C.
  • the bonding wiring layer 20 includes a first metal layer 21 and a second metal layer 22 .
  • the first metal layer 21 is disposed on the main body 11 and extends from the top surface of the main body 11 in the first binding region 1A along the direction of the main body 11 toward the extension 12.
  • the side extends to cover the top surface of the extension part 12 .
  • the second metal layer 22 is disposed on a surface of the first metal layer 21 away from the substrate 10 .
  • the thickness of the first metal layer 21 is smaller than the thickness of the second metal layer 22, and the extension part 12, the first metal layer 21 and the second
  • the sum of the thicknesses of the metal layer 22 is greater than the sum of the thicknesses of the main body 11 and the first metal layer 21 in the first binding area 1A, so that the second metal layer 22 in the second binding area 1B can It is connected with the second metal layer 22 in the first binding region 1A.
  • the display devices of the display panel 1 include several thin film transistors and light emitting devices.
  • the thin film transistor array is arranged on the main body 11 to form an array substrate, and is electrically connected to the bonding wiring layer 20 in the first bonding area 1A through signal wiring.
  • the light emitting devices are arranged on the array substrate and electrically connected with the thin film transistors.
  • the light emitting device can be OLED (Organic Light Emitting Diode), Mini LED (Mini Light Emitting Diode), Micro LED (miniature light emitting diode), etc.
  • the externally driven display signal is transmitted to the array substrate through the bonding wiring 20, and the thin film transistor in the array substrate controls the light-emitting device in each pixel unit to be turned on or off according to the display signal, thereby Control the display and change of the screen image.
  • the external drive includes a chip on film (Chip On Film, COF).
  • the chip-on-film is disposed on a surface of the substrate 10 away from the thin film transistor, and from the bottom surface of the extension part 12 (that is, the surface of the extension part 12 away from the bonding wiring layer 20 ) Extending to cover the side 23 of the bonding wiring layer 20 (that is, the surface of the bonding wiring layer 20 away from the first bonding area 1A), through the bonding wiring layer 20 and the film
  • the transistors are electrically connected.
  • an IC (Integrated Circuit) chip and a flexible printed circuit board (Flexible Printed Circuit Board, FPC) are provided in the chip-on-chip.
  • the flexible circuit board is covered on the substrate 10, and extends from the bottom surface of the extension part 12 of the substrate to the side surface 23 of the binding wiring layer 20, and is electrically connected to the binding wiring layer 20 .
  • the IC chip is disposed on the flexible circuit board and also located on the bottom surface of the substrate 10 .
  • the IC chip is used to send display signals, and the display signals are sequentially transmitted to the thin film transistors of the array substrate through the flexible circuit board and the bonding wiring layer 20 .
  • the chip-on-chip film uses a soft additional circuit board (ie, a flexible circuit board) as a carrier for packaging chips, and connects the chip (ie, an IC chip) with an array substrate circuit to transmit display signals to the display panel 1 .
  • the side 23 of the binding wiring layer 20 is flush with the panel of the substrate 10, so that the external drive can be electrically connected to the array substrate on the side of the display panel 1, thereby greatly reducing the display
  • the width of the frame of the panel 1, and the area of the display area 1C is enlarged to increase the screen-to-body ratio, realize narrow frame display, and improve user experience.
  • a method for preparing the display panel 1 is also adopted, which is used to prepare the above-mentioned display panel 1 .
  • the flow chart of the method for preparing the display panel 1 is shown in Figure 2, which includes the following steps:
  • Step S10) Forming grooves 14 on a substrate 10:
  • a substrate 10 is prepared, and a cutting line is set on the substrate 10 , and the cutting line is shown by a dotted line in FIG. 3 .
  • One side of the cutting line is the cutting area 1D, and the other side of the cutting line is the second binding area 1B of the display panel 1 .
  • a groove 14 is opened on the surface of the substrate 10 by a laser, the groove 14 extends from the second binding area 1B to the cut-off area 1D, and the cutting line is located in the groove 14 .
  • Step S20 Forming the first metal layer 21 on the substrate 10:
  • a metal thin film is deposited on the surface of the substrate 10 with grooves 14 by physical vapor deposition (PVD) to form the first metal layer 21, and the first metal layer 21 is uniform. It covers the first binding area 1A, the second binding area 1B, the display area 1C and the cut-out area 1D.
  • the metal thin film is a copper thin film.
  • Step S30) Forming a photoresist layer 30 on the first metal layer 21:
  • a layer of photoresist material is coated on a surface of the first metal layer 21 away from the substrate 10 , and the layer of photoresist material is cured and patterned by a yellow light process to form a shielding part.
  • the photoresist layer 30 of the first metal layer 21 is coated on a surface of the first metal layer 21 away from the substrate 10 , and the layer of photoresist material is cured and patterned by a yellow light process to form a shielding part.
  • Step S40 Forming the second metal layer 22 on the first metal layer 21:
  • a layer of copper metal is prepared on the exposed first metal layer 21 by an electroplating process to form the second metal layer 22 , and the second metal layer 22 fills the groove 14 .
  • the photoresist layer 30 in the display area 1C and the first metal layer 21 covered by the photoresist layer 30 are removed by an etchant, leaving the second metal layer 22 and the The first metal layer 21 covered by the second metal layer 22 , the second metal layer 22 and the first metal layer 21 are combined to form the bonding wiring layer 20 .
  • Step S50 Removing the substrate 10 and the bonding wiring layer 20 in the cut-off area 1D:
  • the substrate 10 is turned over, the bottom surface of the substrate 10 away from the binding wiring layer 20 faces the cutting instrument, and the cutting area 1D is cut along the cutting line by a laser cutting process.
  • the substrate 10 and the bonding wiring layer 20 are separated from the substrate 10 and the bonding wiring layer 20 in the second bonding area 1B, and the substrate 10 and the binding wiring layer 20 in the cut-off area 1D are removed, Form the display panel 1 as shown in FIG. 1, and make the side 23 of the bonding wiring layer 20 away from the first bonding area 1A and the side 23 of the extension part 12 away from the first bonding area 1A
  • One side 13 is located on the same plane, and a conductive structure is formed on the side of the display panel 1 .
  • Step S60 Prepare the array substrate and light emitting device:
  • a TFT Thin Film Transistor (thin film transistor) process to prepare thin film transistors and signal wires connecting the thin film transistors and the bonding wire layer 20 .
  • a light-emitting device electrically connected to the thin film transistor is formed on a surface of the array substrate away from the substrate through an OLED process or a process such as mass transfer.
  • a chip-on-chip film is provided, and the chip-on-chip film includes a flexible circuit board and an IC chip arranged on the flexible circuit board. Attach one end of the flexible circuit board to the side 13 of the extension part 12 away from the main part 11, and extend from the side 13 to the side 23 of the binding wiring layer 20 away from the main part 11, The flexible circuit board is electrically connected to the binding wiring layer 20 . The end of the flexible circuit board away from the binding wiring layer 20 is fixed on the bottom surface of the substrate 10 to complete the binding of the chip-on-film.
  • the display panel and its preparation method provided in the embodiment of the present invention prepare a brand-new side binding structure through a new preparation process, without using the silver paste printing process, thus solving the problems caused by the silver paste printing process Problems such as poor stability and low yield also avoid the risk of fragmentation caused by glass side grinding.
  • the bonding wiring layer in the embodiment of the present invention adopts an electroplating process, which can improve the use range of the electroplating equipment and make full use of the production equipment.

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示面板（1）及其制备方法。显示面板（1）包括：基板（10），第一绑定区（1A）和第二绑定区（1B），第二绑定区(1B)中的基板（10）厚度小于第一绑定区（1A）中的基板（10）厚度；设于第一绑定区（1A）和第二绑定区（1B）中的基板（10）的表面上的绑定走线层（20）。绑定走线层（20）远离第一绑定区（1A）的一侧面与基板（10）远离第一绑定区（1A）的一侧面位于同一平面上。

Description

显示面板及其制备方法 技术领域
本发明涉及显示设备领域，特别是一种显示面板及其制备方法。
 背景技术
随着小间距Mini LED直显技术推进，信号走线之间的间距也越来越小。当间距＜0.5mm时，则需要启用Side Bonding（侧面绑定）工艺或Back Bonding（背面绑定）工艺将显示面板的显示区与外界驱动连接。目前这两种Bonding 技术最大的瓶颈在于面板的侧面印刷的导电走线。
现有的侧面导线技术主要用银浆硅胶印刷，然而银浆的解析度不高，容易导致走线与走线之间连接，良率低，还需要通过激光刻线将走线分离。并且银浆印刷的工艺稳定度不高，银浆的调配、工艺节点之间的等待时间(Queue Time，Q-Time)、模具残留银浆的清洗等工艺管控一旦出现差错，便容易造成印刷不良。同时，银浆附着力还与玻璃基板的侧磨工艺具有很大关系，而玻璃侧磨会给基板带来很大的破片风险。
 技术问题
本发明的目的是提供一种显示面板及制备方法，以解决现有技术中通过银浆硅胶印刷工艺的稳定性不高、所制备的侧面导线良率低以及玻璃侧磨所带来的破片风险等。
 技术解决方案
为实现上述目的，本发明提供一种显示面板，所述显示面板具有一第一绑定区以及与所述第一绑定区连接的第二绑定区。所述显示面板包括基板和绑定走线层。所述第二绑定区中的基板额厚度小于所述第一绑定区中的基板的厚度。所述绑定走线层设于所述第一绑定区和所述第二绑定区中的所述基板的表面上。所述绑定走线层远离所述第一绑定区的一侧面与所述基板远离所述第一绑定区的一侧面位于同一平面上。
进一步地，所述基板包括主体部和延伸部。所述主体部位于第一绑定区中。所述延伸部与所述主体部连接，并位于所述第二绑定区中。
进一步地，所述延伸部的厚度小于所述主体部的厚度。
进一步地，所述主体部的远离所述绑定走线层的一表面与所述延伸部远离所述绑定走线层的一表面位于同一平面上。
进一步地，所述绑定走线层包括第一金属层和第二金属层。所述第一金属层设于所述主体部上，并从所述主体部延伸覆盖至所述延伸部上，所述第二金属层设于所述第一金属层远离所述基板的一表面上。
进一步地，所述第一金属层的厚度小于所述第二金属层的厚度。
进一步地，所述主体部和所述第一金属层的厚度总和小于所述延伸部、所述第一金属层和所述第二金属层的厚度总和。
进一步地，所述绑定走线层的材料中包括铜。
进一步地，所述显示面板还具有一显示区，所述显示区设于所述第一绑定区远离所述第二绑定区的一侧。
所述显示面板还包括薄膜晶体管和覆晶薄膜。所述薄膜晶体管设于所述基板上，并位于所述显示区内。所述覆晶薄膜从所述延伸部远离所述绑定走线的一表面延伸至所述绑定走线远离所述主体部的一表面上。
进一步地，所述绑定走线层位于所述第一绑定区中的一端与所述薄膜晶体管电连接。所述绑定走线层位于远离所述第一绑定区的一侧面与所述覆晶薄膜电连接。
进一步地，所述显示面板还包括发光器件，所述发光器件设于所述薄膜晶体管上。
本发明中还提供一种显示面板的制备方法，所述制备方法中包括以下步骤：
提供一基板，所述基板具有第一绑定区、第二绑定区和切除区，所述切除区与第二绑定区相连，所述第二绑定区远离所述切除区的一侧与所述第一绑定区连接，所述切除区与所述第二绑定区之间的分界线为切割线；在所述基板上开设凹槽，所述切割线位于所述凹槽中；在所述基板上形成绑定走线层，所述绑定走线层覆盖所述第一绑定区、所述第二绑定区及所述切除区并填充所述凹槽；沿所述切割线切割所述基板和所述绑定走线层，去除所述切除区中的所述基板与所述绑定走线层。
进一步地，在所述基板上形成所述绑定走线层步骤中包括以下步骤：在所述基板上通过沉积形成第一金属层；在所述第一金属层上通过电镀工艺形成第二金属层。
进一步地，所述第一金属层均匀覆盖在所述凹槽的槽壁和槽底上，所述凹槽的深度小于所述第二金属层的膜层厚度。
进一步地，所述第一金属层和所述第二金属层的材料中含有铜。
进一步地，在所述基板上形成所述绑定走线层步骤中还包括以下步骤：在所述第一金属层上形成光阻层；制备所述第二金属层后去除所述光阻层以及所述光阻层所覆盖的第一金属层。
进一步地，在所述第一金属层上形成所述光阻层步骤中以下步骤：在所述第一金属层远离所述光阻层的一表面上涂布光阻材料；将所述光阻材料固化以及图案化，形成遮挡部分所述第一金属层的光阻层。
进一步地，沿切割线切割所述基板和所述绑定走线层步骤中包括：将所述基板翻面，将所述基板远离所述绑定走线层的一表面朝向切割器械；通过激光切割工艺沿所述切割线将所述切除区中的基板和绑定走线层与所述第二绑定区中的基板和绑定走线层分离。
进一步地，所述显示面板的制备方法中还包括以下步骤：所述基板还具有一显示区，所述显示区设于所述第一绑定区远离所述第二绑定区的一侧，在所述显示区内的基板上形成薄膜晶体管；在所述基板远离所述绑定走线层的一表面和所述绑定走线远离所述第一绑定区的一表面上贴覆覆晶薄膜。
进一步地，所述显示面板的制备方法中还包括以下步骤：在所述薄膜晶体管上形成发光器件。
 有益效果
本发明的优点是：本发明中所提供的一种显示面板及其制备方法，无需采用银浆印刷工艺，从而解决了银浆印刷工艺所带来的工艺稳定性差、良率等问题，也规避了玻璃侧磨所带来的破片风险。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例中显示面板的层状结构示意图；
图2为本发明实施例中显示面板制备方法的流程示意图；
图3为本发明实施例中步骤S10后基板的层状结构示意图；
图4为本发明实施例中步骤S20后显示面板的层状结构示意图；
图5为本发明实施例中步骤S30后显示面板的层状结构示意图；
图6为本发明实施例中步骤S40中显示面板的层状结构示意图；
图7为本发明实施例中步骤S40后显示面板的层状结构示意图；
图8为本发明实施例中步骤S50中显示面板的层状结构示意图。
图中部件表示如下：
显示面板1；第一绑定区1A；
第二绑定区1B；显示区1C；
基板10；主体部11；
延伸部12；延伸部远离所述主体部的侧面13；
绑定走线层20；第一金属层21；
第二金属层22；绑定走线层远离主体部的侧面23；
切除区1D；凹槽14；
光阻层30。
 本发明的实施方式
以下参考说明书附图介绍本发明的优选实施例，证明本发明可以实施，所述发明实施例可以向本领域中的技术人员完整介绍本发明，使其技术内容更加清楚和便于理解。本发明可以通过许多不同形式的发明实施例来得以体现，本发明的保护范围并非仅限于文中提到的实施例。
本发明实施例中提供了一种显示面板1，所述显示面板1用于为电子装提供显示画面。如图1所示，所述显示面板1具有一第一绑定区1A、一第二绑定区1B以及一显示区1C。所述第二绑定区1B与所述第一绑定区1A的一侧相连，所述显示区1C则与所述第一绑定区1A远离所述第二绑定区1B的一侧相连。
所述显示面板1中包括一基板10和一绑定走线层20。
所述基板10为硬性基板10，其材料可以为玻璃、石英等。所述基板10包括一主体部11和一延伸部12。所述主体部11覆盖所述第一绑定区1A和所述显示区1C。所述延伸部12覆盖所述第二绑定区1B，并与所述主体部11的一侧连接。其中，所述主体部11的厚度大于所述延伸部12的厚度，并且所述延伸部12的底面（即所述延伸部12远离所述绑定走线层20的一表面）与所述主体部11（即所述主体部11远离所述绑定走线层20的一表面）的底面位于同一平面上，使所述主体部11朝向所述延伸部12的部分侧面裸露，同时使所述基板10的底面齐平，便于在所述基板10的底面上贴覆外接驱动。
所述绑定走线层20中排布了若干走线，所述走线等距排布在所述基板10的边缘。如图1所示，所述绑定走线层20设于所述第一绑定区1A中的主体部11上，并从所述主体部11延伸覆盖至所述第二绑定区1B中的延伸部12上。所述绑定走线层20远离所述主体部11(即远离所述第一绑定区1A)的一侧面23与所述延伸部12远离所述主体部11(即远离所述第一绑定区1A)的一侧面13位于同一平面上，从而在所述基板10的侧面形成导电结构。所述绑定走线层20位于所述第一绑定区1A中的一端与所述显示区1C中的显示器件电连接，而所述绑定走线层20位于所述基板10侧面的一端与外接驱动电连接，所述外界驱动通过所述绑定走线层20与所述显示器件连接，从而向所述显示区1C传输显示信号。
具体的，所述绑定走线层20包括一第一金属层21以及一第二金属层22。所述第一金属层21设于所述主体部11上，并从所述主体部11位于所述第一绑定区1A中的顶面顺着所述主体部11朝向所述延伸部12的侧面延伸覆盖至所述延伸部12的顶面上。所述第二金属层22设于所述第一金属层21远离所述基板10的一表面上。具体的，所述第一金属层21的厚度小于所述第二金属层22的厚度，所述第二绑定区1B中所述延伸部12、所述第一金属层21和所述第二金属层22的厚度总和大于所述第一绑定区1A中所述主体部11和所述第一金属层21的厚度总和，使所述第二绑定区1B中的第二金属层22能与所述第一绑定区1A中的第二金属层22连接。
在所述显示区1C中，所述显示面板1的显示器件包括若干薄膜晶体管和发光器件。所述薄膜晶体管阵列排布在所述主体部11上，形成阵列基板，并通过信号走线与位于第一绑定区1A中的绑定走线层20电连接。所述发光器件排布在所述阵列基板上，并与所述薄膜晶体管电连接。所述发光器件可以为OLED（有机发光二极管）、Mini LED（迷你发光二极管）、Micro LED（微型发光二极管）等。所述外界驱动的显示信号通过所述绑定走线20传输至所述阵列基板中，所述阵列基板中的薄膜晶体管根据所述显示信号控制每一像素单元中发光器件的开启或关闭，从而控制画面图像的显示及变化。
所述外界驱动包括覆晶薄膜（Chip On Film，COF）。所述覆晶薄膜设于所述基板10远离所述薄膜晶体管的一表面上，并从所述延伸部12的底面（即所述延伸部12远离所述绑定走线层20的一表面）延伸覆盖至所述绑定走线层20的侧面23（即所述绑定走线层20远离第一绑定区1A的一表面）上，通过所述绑定走线层20与所述薄膜晶体管电连接。具体的，所述覆晶薄膜中设有IC（集成电路）芯片和柔性电路板（Flexible Printed Circuit Board，FPC）。所述柔性电路板覆于所述基板10上，并从所述基板的延伸部12的底面延伸至所述绑定走线层20的侧面23上，与所述绑定走线层20电连接。所述IC芯片设于所述柔性电路板上，同时还位于所述基板10的底面上。所述IC芯片用于发送显示信号，所述显示信号依次通过所述柔性电路版、所述绑定走线层20传输至所述阵列基板的薄膜晶体管上。所述覆晶薄膜通过软质附加电路板（即柔性电路板）作为封装芯片的载体，将芯片（即IC芯片）与阵列基板电路连接，为所述显示面板1输送显示信号。
所述绑定走线层20的侧面23与所述基板10的面板齐平，从而使所述外接驱动可以在所述显示面板1的侧面与所述阵列基板电连接，进而大大减少所述显示面板1的边框宽度，并扩大所述显示区1C的面积，提高屏占比，实现窄边框显示，提高用户的体验感。
本发明实施例中还通过了一种显示面板1的制备方法，用以制备如上所述的显示面板1。具体的，所述显示面板1制备方法的流程如图2所示，其包括以下步骤：
步骤S10）在一基板10上形成凹槽14：
如图3所示，准备一基板10，在所述基板10上设定切割线，所述切割线如图3中虚线所示。所述切割线的一侧为切除区1D，所述切割线的另一侧为所述显示面板1的第二绑定区1B。在所述基板10的表面上通过激光开设凹槽14，所述凹槽14从所述第二绑定区1B延伸至所述切除区1D，所述切割线在位于所述凹槽14中。
步骤S20）在所述基板10上形成第一金属层21：
如图4所示，通过物理气相沉积法（PVD）在所述基板10开设凹槽14的一表面上沉积一层金属薄膜，形成所述第一金属层21，所述第一金属层21均匀覆盖在第一绑定区1A、第二绑定区1B、显示区1C以及切除区1D。其中，所述金属薄膜为铜薄膜。
步骤S30）在所述第一金属层21上形成光阻层30：
如图5所示，在所述第一金属层21远离所述基板10的一表面上涂布一层光阻材料，并通过黄光制程将该层光阻材料固化以及图案化，形成遮挡部分第一金属层21的光阻层30。
步骤S40）在所述第一金属层21上形成第二金属层22：
如图6所示，通过电镀工艺在裸露的第一金属层21上制备一层铜金属，形成所述第二金属层22，所述第二金属层22填充所述凹槽14。如图7所示，通过刻蚀液将所述显示区1C中的光阻层30以及所述光阻层30所覆盖的第一金属层21去除，留下所述第二金属层22以及所述第二金属层22所覆盖的第一金属层21，所述第二金属层22和所述第一金属层21组合形成绑定走线层20。
步骤S50）去除所述切除区1D中的基板10和绑定走线层20：
如图8所示，将所述基板10翻面，将所述基板10远离所述绑定走线层20的底面朝向切割器械，利用激光切割工艺沿所述切割线将所述切除区1D中的基板10和绑定走线层20与所述第二绑定区1B中的基板10和绑定走线层20分离，去除所述切除区1D中的基板10和绑定走线层20，形成如图1所示的显示面板1，并使所述绑定走线层20远离所述第一绑定区1A的一侧面23与所述延伸部12远离所述第一绑定区1A的一侧面13位于同一平面上，在所述显示面板1的侧面上形成导电结构。
步骤S60）制备阵列基板和发光器件：
所述显示区1C内的基板10的一表面上通过TFT（Thin Film Transistor，薄膜晶体管）工艺制备薄膜晶体管以及连接所述薄膜晶体管和所述绑定走线层20的信号走线。通过OLED制程或通过巨量转移等工艺在所述阵列基板远离所述基板的一表面上形成与所述薄膜晶体管电连接的发光器件。
步骤S70）绑定覆晶薄膜：
提供一覆晶薄膜，所述覆晶薄膜中包括柔性电路板以及设置在所述柔性电路板的IC芯片。将所述柔性电路板的一端贴覆在所述延伸部12远离所述主体部11的侧面13上，并从侧面13延伸至所述绑定走线层20远离主体部11的侧面23上，使所述柔性电路板与所述绑定走线层20电连接。将所述柔性电路板远离所述绑定走线层20的一端固定在所述基板10的底面上，完成所述覆晶薄膜的绑定。
本发明实施例中所提供的显示面板及其制备方法，通过全新的制备工艺制备了一种全新的侧面绑定结构，无需采用银浆印刷工艺，从而解决了银浆印刷工艺所带来的工艺稳定性差、良率低等问题，也规避了玻璃侧磨所带来的破片风险。同时，本发明实施例中的绑定走线层采用电镀工艺，能够提升电镀设备的使用范围，充分利用生产设备。
虽然在本文中参照了特定的实施方式来描述本发明，但是应该理解的是，这些实施例仅仅是本发明的原理和应用的示例。因此应该理解的是，可以对示例性的实施例进行许多修改，并且可以设计出其他的布置，只要不偏离所附权利要求所限定的本发明的精神和范围。应该理解的是，可以通过不同于原始权利要求所描述的方式来结合不同的从属权利要求和本文中所述的特征。还可以理解的是，结合单独实施例所描述的特征可以使用在其他所述实施例中。

Claims (20)

  1. 一种显示面板，其具有一第一绑定区以及与所述第一绑定区连接的第二绑定区；
    所述显示面板包括：
    基板，所述第二绑定区中的基板的厚度小于所述第一绑定区中的基板的厚度；
    绑定走线层，设于所述第一绑定区和所述第二绑定区中的所述基板的表面上；
    所述绑定走线层远离所述第一绑定区的一侧面与所述基板远离所述第一绑定区的一侧面位于同一平面上。
  2. 如权利要求1所述的显示面板，其中，
    所述基板包括：
    主体部，位于第一绑定区中；
    延伸部，与所述主体部连接，并位于所述第二绑定区中。
  3. 如权利要求2所述的显示面板，其中，所述延伸部的厚度小于所述主体部的厚度。
  4. 如权利要求2所述的显示面板，其中，
    所述主体部的远离所述绑定走线层的一表面与所述延伸部远离所述绑定走线层的一表面位于同一平面上。
  5. 如权利要求2所述的显示面板，其中，所述绑定走线层包括：
    第一金属层，设于所述主体部上，并从所述主体部延伸至所述延伸部上；
    第二金属层，设于所述第一金属层远离所述基板的一表面上。
  6. 如权利要求5所述的显示面板，其中，所述第一金属层的厚度小于所述第二金属层的厚度。
  7. 如权利要求5所述的显示面板，其中，
    所述主体部和所述第一金属层的厚度总和小于所述延伸部、所述第一金属层和所述第二金属层的厚度总和。
  8. 如权利要求1所述的显示面板，其中，所述绑定走线层的材料中包括铜。
  9. 如权利要求2所述的显示面板，其还具有一显示区，设于所述第一绑定区远离所述第二绑定区的一侧；
    所述显示面板还包括：
    薄膜晶体管，设于所述基板上，并位于所述显示区内；
    覆晶薄膜，从所述延伸部远离所述绑定走线层的一表面延伸至所述绑定走线层远离所述第一绑定区的一表面上。
  10. 如权利要求9所述的显示面板，其中，
    所述绑定走线层位于所述第一绑定区中的一端与所述薄膜晶体管电连接；
    所述绑定走线层位于远离所述第一绑定区的一侧面与所述覆晶薄膜电连接。
  11. 如权利要求9所述的显示面板，其还包括发光器件，所述发光器件设于所述薄膜晶体管上。
  12. 一种显示面板的制备方法，其包括以下步骤：
    提供一基板，所述基板具有第一绑定区、第二绑定区和切除区，所述切除区与第二绑定区相连，所述第二绑定区远离所述切除区的一侧与所述第一绑定区连接；
    在所述基板上开设凹槽；
    在所述基板上形成绑定走线层，所述绑定走线层覆盖所述第一绑定区、所述第二绑定区及所述切除区并填充所述凹槽；
    沿切割线切割所述基板和所述绑定走线层，其中所述切割线为所述切除区与所述第二绑定区之间的分界线，并位于所述凹槽中；
    去除所述切除区中的所述基板与所述绑定走线层。
  13. 如权利要求12所述的显示面板的制备方法，其中，在所述基板上形成所述绑定走线层步骤中包括以下步骤：
    在所述基板上通过沉积形成第一金属层；
    在所述第一金属层上通过电镀工艺形成第二金属层。
  14. 如权利要求13所述的显示面板的制备方法，其中，所述第一金属层均匀覆盖在所述凹槽的槽壁和槽底上，所述凹槽的深度小于所述第二金属层的膜层厚度。
  15. 如权利要求13所述的显示面板的制备方法，其中，所述第一金属层和所述第二金属层的材料中含有铜。
  16. 如权利要求13所述的显示面板的制备方法，其中，在所述基板上形成所述绑定走线层步骤中还包括以下步骤：
    在所述第一金属层上形成光阻层；
    制备所述第二金属层后去除所述光阻层以及所述光阻层所覆盖的第一金属层。
  17. 如权利要求16所述的显示面板的制备方法，其中，在所述第一金属层上形成所述光阻层步骤中以下步骤：
    在所述第一金属层远离所述光阻层的一表面上涂布光阻材料；
    将所述光阻材料固化以及图案化，形成遮挡部分所述第一金属层的光阻层。
  18. 如权利要求12所述的显示面板的制备方法，沿切割线切割所述基板和所述绑定走线层步骤中包括：
    将所述基板翻面，将所述基板远离所述绑定走线层的一表面朝向切割器械；
    通过激光切割工艺沿所述切割线将所述切除区中的基板和绑定走线层与所述第二绑定区中的基板和绑定走线层分离。
  19. 如权利要求12所述的显示面板的制备方法，其还包括以下步骤：
    所述基板还具有一显示区，所述显示区设于所述第一绑定区远离所述第二绑定区的一侧，在所述显示区内的基板上形成薄膜晶体管；
    在所述基板远离所述绑定走线层的一表面和所述绑定走线远离所述第一绑定区的一表面上贴覆覆晶薄膜。
  20. 如权利要求19所述的显示面板的制备方法，其还包括以下步骤：
    在所述薄膜晶体管上形成发光器件。
PCT/CN2021/139183 2021-12-09 2021-12-17 显示面板及其制备方法 WO2023103041A1 (zh)

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