WO2023100754A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2023100754A1
WO2023100754A1 PCT/JP2022/043496 JP2022043496W WO2023100754A1 WO 2023100754 A1 WO2023100754 A1 WO 2023100754A1 JP 2022043496 W JP2022043496 W JP 2022043496W WO 2023100754 A1 WO2023100754 A1 WO 2023100754A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor device
terminal
terminal portions
surface portion
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2022/043496
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
幸太 伊勢
光俊 齊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to CN202280079326.0A priority Critical patent/CN118355490A/zh
Priority to JP2023564928A priority patent/JPWO2023100754A1/ja
Priority to DE112022005309.7T priority patent/DE112022005309T5/de
Publication of WO2023100754A1 publication Critical patent/WO2023100754A1/ja
Priority to US18/652,315 priority patent/US20240282690A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

Definitions

  • the present disclosure relates to semiconductor devices.
  • Patent Document 1 discloses an example of a conventional semiconductor device.
  • the semiconductor device disclosed in the document includes a semiconductor element, leads and sealing resin.
  • a semiconductor element is supported by leads.
  • the sealing resin covers part of the leads and the semiconductor element.
  • a lead has a plurality of terminal portions.
  • Each terminal portion includes a portion exposed from the sealing resin, and is joined with a joining material such as solder when mounted on a circuit board, for example.
  • the lead has a configuration in which it is covered with a plating layer in place.
  • the tip of each terminal portion has an exposed cut surface formed by cutting a metal plate (lead frame) used for manufacturing a semiconductor device, for example, and is not covered with the plating layer.
  • the cut surface of the tip of the terminal portion is inferior in wettability to solder compared to the plating layer. This can lead to deterioration in mounting reliability of the semiconductor device on the circuit board.
  • metal burrs are generated at the tip of the terminal portion during cutting, and if the metal burr protrudes from the tip of the terminal portion, the mounting reliability of the semiconductor device may be lowered.
  • An object of the present disclosure is to provide a semiconductor device that is improved over conventional semiconductor devices.
  • an object of the present disclosure is to provide a semiconductor device suitable for suppressing deterioration in mounting reliability.
  • a semiconductor device provided by the first aspect of the present disclosure includes leads, a semiconductor element, and a sealing resin.
  • the lead includes a die pad having a first surface facing one side in the thickness direction, and a plurality of terminal portions.
  • the semiconductor element is mounted on the first surface of the lead.
  • the sealing resin covers the semiconductor element, at least a portion of the die pad, and a portion of each of the plurality of terminal portions.
  • the lead includes a base material and a metal layer covering a portion of the base material.
  • the base material has a first terminal extension portion forming at least one of the plurality of terminal portions. The first terminal extension is exposed from the sealing resin and extends in a first direction perpendicular to the thickness direction.
  • the first terminal extension portion includes a first end face portion facing the first direction and a first side wall facing the second direction orthogonal to the thickness direction and the first direction.
  • the first side wall includes a first side surface portion located closer to the first end surface portion in the first direction, a second side surface portion located closer to the sealing resin in the first direction, and a and a third side portion positioned between the first side portion and the second side portion.
  • the metal layer is provided at a position that covers the first end face portion, the first side face portion and the second side face portion and avoids the third side face portion.
  • FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present disclosure
  • FIG. 2 is a bottom view of the semiconductor device shown in FIG. 1.
  • FIG. 3 is a plan view of the semiconductor device shown in FIG. 1 (see through the sealing resin).
  • 4 is a right side view of the semiconductor device shown in FIG. 1.
  • FIG. 5 is a left side view of the semiconductor device shown in FIG. 1.
  • FIG. 6 is a cross-sectional view taken along line VI-VI of FIG. 3.
  • FIG. 7 is a cross-sectional view along line VII-VII of FIG.
  • FIG. 8 is a cross-sectional view along line VIII-VIII of FIG. 9 is an enlarged view of the vicinity of the first terminal portion in FIG. 1.
  • FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present disclosure
  • FIG. 2 is a bottom view of the semiconductor device shown in FIG. 1.
  • FIG. 3 is a plan view of the semiconductor device shown in FIG. 1
  • FIG. 10 is an enlarged view of the vicinity of the second terminal portion in FIG. 1.
  • FIG. 11 is a right side view of FIG. 9.
  • FIG. 12 is a left side view of FIG. 9.
  • FIG. 13 is a right side view of FIG. 10.
  • FIG. 14 is a left side view of FIG. 10.
  • FIG. 15 is a cross-sectional view along line XV-XV of FIG. 9.
  • FIG. 16 is a cross-sectional view taken along line XVI--XVI of FIG. 9.
  • FIG. 17 is a cross-sectional view along line XVII-XVII of FIG. 10.
  • FIG. 18 is a fragmentary plan view showing part of a lead frame used in manufacturing the semiconductor device shown in FIG. 1.
  • FIG. 18 is a fragmentary plan view showing part of a lead frame used in manufacturing the semiconductor device shown in FIG. 1.
  • FIG. 19 is a plan view showing a semiconductor device according to a first modification of the first embodiment
  • FIG. 20 is an enlarged view of the vicinity of the first terminal portion in FIG. 19.
  • FIG. 21 is an enlarged view of the vicinity of the second terminal portion in FIG. 19.
  • FIG. 22 is a fragmentary plan view showing part of a lead frame used in manufacturing the semiconductor device shown in FIG. 19.
  • FIG. 23 is a plan view showing a semiconductor device according to a second modification of the first embodiment;
  • FIG. 24 is an enlarged view of the vicinity of the first terminal portion in FIG. 23.
  • FIG. 25 is an enlarged view of the vicinity of the second terminal portion in FIG. 23.
  • FIG. 26 is a fragmentary plan view showing part of a lead frame used in manufacturing the semiconductor device shown in FIG. 23.
  • FIG. 27 is a plan view showing a semiconductor device according to a second embodiment of the present disclosure
  • FIG. 28 is a bottom view of the semiconductor device shown in FIG. 27.
  • FIG. FIG. 29 is a plan view of the semiconductor device shown in FIG. 27 (see through the sealing resin).
  • 30 is a right side view of the semiconductor device shown in FIG. 27.
  • FIG. 31 is a left side view of the semiconductor device shown in FIG. 27.
  • FIG. 32 is a cross-sectional view taken along line XXXII-XXXII of FIG. 29.
  • FIG. 33 is a cross-sectional view taken along line XXXIII-XXXIII of FIG. 29.
  • FIG. 34 is a cross-sectional view taken along line XXIV-XXXIV of FIG. 29.
  • FIG. 35 is an enlarged view of the vicinity of the second terminal portion in FIG. 27.
  • FIG. 36 is a plan view showing a semiconductor device according to a modification of the second embodiment;
  • FIG. 37 is a cross-sectional view taken along line XXXVII-XXXVII of FIG. 36.
  • FIG. 38 is a cross-sectional view taken along line XXXVIII-XXXVIII of FIG. 36.
  • FIG. 39 is an enlarged view of the vicinity of the second terminal portion in FIG. 36.
  • FIG. 40 is a fragmentary plan view showing part of a lead frame used in manufacturing the semiconductor device shown in FIG. 36.
  • FIG. 40 is a fragmentary plan view showing part of a lead frame used in manufacturing the semiconductor device shown in FIG. 36.
  • a certain entity A is formed on a certain entity B” and “a certain entity A is formed on a certain entity B” mean “a certain entity A is formed on a certain entity B”. It includes "being directly formed in entity B” and “being formed in entity B while another entity is interposed between entity A and entity B”.
  • ⁇ an entity A is placed on an entity B'' and ⁇ an entity A is located on an entity B'' mean ⁇ an entity A is located on an entity B.'' It includes "directly placed on B” and "some entity A is placed on an entity B while another entity is interposed between an entity A and an entity B.”
  • ⁇ an object A is located on an object B'' means ⁇ an object A is adjacent to an object B and an object A is positioned on an object B. and "the thing A is positioned on the thing B while another thing is interposed between the thing A and the thing B".
  • ⁇ an object A overlaps an object B when viewed in a certain direction'' means ⁇ an object A overlaps all of an object B'' and ⁇ an object A overlaps an object B.'' It includes "overlapping a part of a certain thing B".
  • FIG. A semiconductor device A10 includes a plurality of leads 1A, 1B, 1C, a semiconductor element 2, an insulating portion 3, a metal lamination portion 4, a conductive member 5, conductive bonding materials 61, 62, 63, and a sealing resin 7.
  • FIG. 1 is a plan view showing the semiconductor device A10.
  • FIG. 2 is a bottom view showing the semiconductor device A10.
  • FIG. 3 is a plan view showing the semiconductor device A10.
  • FIG. 4 is a right side view showing the semiconductor device A10.
  • FIG. 7 is a cross-sectional view along line VII-VII of FIG.
  • FIG. 8 is a cross-sectional view along line VIII-VIII of FIG.
  • FIG. 9 is a partially enlarged view of FIG. 1 (an enlarged view of the periphery of a first terminal portion 13, which will be described later).
  • FIG. 10 is a partially enlarged view of FIG.
  • FIG. 11 is a right side view of FIG. 9.
  • FIG. 12 is a left side view of FIG. 9.
  • FIG. 13 is a right side view of FIG. 10.
  • FIG. 14 is a left side view of FIG. 10.
  • FIG. 15 is a cross-sectional view along line XV-XV of FIG. 9.
  • FIG. 16 is a cross-sectional view taken along line XVI--XVI of FIG. 9.
  • FIG. 17 is a cross-sectional view along line XVII-XVII of FIG. 10.
  • FIG. 3 is transparent through the sealing resin 7 for convenience of understanding.
  • the thickness direction of the semiconductor element 2 is called "thickness direction z”.
  • a direction perpendicular to the thickness direction z is called a “first direction x”.
  • a direction orthogonal to both the thickness direction z and the first direction x is called a “second direction y”.
  • the semiconductor device A10 has a rectangular shape (or a substantially rectangular shape) when viewed in the thickness direction z.
  • the size of the semiconductor device A10 is not particularly limited.
  • each of the leads 1A to 1C includes a base material 101 and a metal layer 102 (see FIGS. 6 to 8).
  • the constituent material of base material 101 is not particularly limited, and is made of, for example, copper (Cu) or nickel (Ni), or an alloy thereof.
  • the metal layer 102 partially covers the base material 101 , and in this embodiment, the metal layer 102 covers most of the base material 101 .
  • Metal layer 102 is, for example, a plated layer formed on the surface of base material 101 .
  • a constituent material of the plating layer is not particularly limited, and is made of an alloy containing Sn as a main component, for example.
  • the lead 1A is spaced apart from the lead 1B and the lead 1C in the first direction x.
  • the leads 1B and 1C are arranged in the second direction y.
  • the leads 1A-1C are spaced apart from each other when viewed in the thickness direction z.
  • the size in the thickness direction z view is the largest for the lead 1A and the smallest for the lead 1C.
  • the lead 1A has a die pad 12 and a plurality of (four in this embodiment) first terminal portions 13.
  • the die pad 12 has, for example, a rectangular shape when viewed in the thickness direction z.
  • Die pad 12 has a first surface 121 and a back surface mounting portion 122 .
  • the first surface 121 faces one side in the thickness direction z
  • the back mounting portion 122 faces the side opposite to the first surface 121 (the other side in the thickness direction z).
  • a semiconductor element 2 is mounted on the first surface 121 .
  • the back mounting portion 122 is exposed from the sealing resin 7 .
  • the back mounting portion 122 is a portion that is joined with a joining material such as solder when the semiconductor device A10 is mounted on a circuit board (not shown).
  • the plurality of first terminal portions 13 are located on one side of the die pad 12 in the first direction x (right side in FIG. 6). Each of the plurality of first terminal portions 13 is connected to one side of the die pad 12 in the first direction x and extends in one side of the first direction x. The plurality of first terminal portions 13 are arranged at intervals in the second direction y. Each first terminal portion 13 is an example of a "terminal portion" that extends in a direction perpendicular to the thickness direction z (the first direction x in the illustrated example) as a longitudinal direction. Each of the plurality of first terminal portions 13 has a back surface mounting portion 131 . The back mounting portion 131 faces the other side in the thickness direction z (lower side in FIG. 6). The back mounting portion 131 is exposed from the sealing resin 7 . The back surface mounting portion 131 is a portion that is joined with a joining material such as solder when the semiconductor device A10 is mounted on a circuit board (not shown).
  • the lead 1B has a pad portion 14, a plurality of (three in this embodiment) second terminal portions 15 and a plurality of (three in this embodiment) bent portions 16.
  • FIG. The pad portion 14 is located on one side (upper side in FIG. 6) in the thickness direction z with respect to the plurality of second terminal portions 15 . Also, the pad portion 14 is located inside the plurality of second terminal portions 15 in the first direction x.
  • the plurality of second terminal portions 15 are positioned on the other side in the first direction x (left side in FIG. 6) with respect to the die pad 12 of the lead 1A. Each of the plurality of second terminal portions 15 extends to the other side in the first direction x. The plurality of second terminal portions 15 are arranged at intervals in the second direction y. Each of the second terminal portions 15 is an example of a "terminal portion" that extends in a direction orthogonal to the thickness direction z (the first direction x in the illustrated example) as a longitudinal direction. Each of the plurality of second terminal portions 15 has a back surface mounting portion 151 . The back mounting portion 151 faces the other side in the thickness direction z (lower side in FIG. 6).
  • the back mounting portion 151 is exposed from the sealing resin 7 .
  • the back surface mounting portion 151 is a portion that is joined with a joining material such as solder when the semiconductor device A10 is mounted on a circuit board (not shown).
  • the plurality of bent portions 16 connect the pad portion 14 and the plurality of second terminal portions 15 respectively, and have a bent shape when viewed in the second direction y.
  • the lead 1C has a pad portion 17, a second terminal portion 18 and a bent portion 19.
  • the pad portion 17 is located on one side (upper side in FIG. 7) in the thickness direction z with respect to the second terminal portion 18 . Also, the pad portion 17 is located inside the second terminal portion 18 in the first direction x.
  • the second terminal portion 18 is located on the other side in the first direction x (left side in FIG. 7) with respect to the die pad 12 of the lead 1A.
  • the second terminal portion 18 extends to the other side in the first direction x.
  • the plurality of second terminal portions 15 of the lead 1B and the second terminal portions 18 of the lead 1C are spaced apart in the second direction y.
  • the second terminal portion 18 is an example of a “terminal portion” that extends in a direction orthogonal to the thickness direction z (the first direction x in the illustrated example) as a longitudinal direction.
  • the second terminal portion 18 has a back surface mounting portion 181 .
  • the back mounting portion 181 faces the other side in the thickness direction z (lower side in FIG. 7).
  • the back mounting portion 181 is exposed from the sealing resin 7 .
  • the back surface mounting portion 181 is a portion that is joined with a joining material such as solder when the semiconductor device A10 is mounted on a circuit board (not shown).
  • the bent portion 19 connects the pad portion 17 and the second terminal portion 18 and has a bent shape when viewed in the second direction y.
  • the base material 101 forming the leads 1A to 1C has first terminal extension portions 103.
  • the base material 101 of each of the leads 1A-1C has a first terminal extension portion 103.
  • a base material 101 of the lead 1A is provided with a plurality of first terminal extension portions 103 corresponding to the plurality of first terminal portions 13, respectively.
  • each first terminal extension portion 103 is a portion forming the corresponding first terminal portion 13 .
  • a base material 101 of the lead 1B is provided with a plurality of first terminal extension portions 103 corresponding to the plurality of second terminal portions 15, respectively.
  • each first terminal extension portion 103 is a portion forming a second terminal portion 15 corresponding thereto.
  • a base material 101 of the lead 1 ⁇ /b>C is provided with a first terminal extension portion 103 corresponding to the second terminal portion 18 .
  • the first terminal extension portion 103 is a portion forming the second terminal portion 18 .
  • Each first terminal extension 103 is exposed from the sealing resin 7 and extends in a direction perpendicular to the thickness direction z (first direction x in this embodiment).
  • the first terminal extension portion 103 includes a first end portion 104 , a first side wall 105 and a second side wall 115 .
  • the first end surface portion 104 is located at the tip in the direction (first direction x) in which the first terminal extension portion 103 extends, and faces the first direction x.
  • the first end surface portion 104 is a flat surface facing the first direction x.
  • the first terminal extension portion 103 forming the first terminal portion 13 the first end surface portion 104 faces one side in the first direction x.
  • the first terminal extension portion 103 constituting the second terminal portion 15 (18) the first end face portion 104 faces the other side in the first direction x.
  • the first side wall 105 faces a direction (second direction y in this embodiment) orthogonal to the direction (first direction x) in which the first terminal extension 103 extends when viewed in the thickness direction z. In this embodiment, the first sidewall 105 faces one side in the second direction y. As shown in FIGS. 9, 10, 11 and 13, the first side wall 105 has a first side portion 106, a second side portion 107 and a third side portion .
  • the first side surface portion 106 is positioned closer to the first end surface portion 104 in the first direction x.
  • the second side surface portion 107 is positioned closer to the sealing resin 7 in the first direction x.
  • the third side portion 108 is located between the first side portion 106 and the second side portion 107 in the first direction x.
  • the first side portion 106 and the second side portion 107 are located on the other side of the third side portion 108 in the second direction y (the left side in FIGS. 9 and 10).
  • the first side surface portion 106 is located on the other side in the second direction y as it separates from the third side surface portion 108 in the first direction x, and has a recessed arc shape when viewed in the thickness direction z.
  • the second side surface portion 107 has a second side surface first portion 107a and a second side surface second portion 107b.
  • the second side surface first portion 107a is a flat surface facing one side in the second direction y (the right side in FIGS. 9 and 10).
  • the second side surface second portion 107b is connected to both the second side surface first portion 107a and the third side surface portion 108, and is located on the other side in the second direction y as it moves away from the third side surface portion 108 in the first direction x. .
  • the second side surface second portion 107b has a recessed arc shape when viewed in the thickness direction z.
  • the third side surface portion 108 is a flat surface facing one side in the second direction y (right side in FIGS. 9 and 10).
  • the metal layer 102 is formed on the first end surface portion 104, the first side surface portion 106 and the third side surface portion . It covers the two side parts 107 .
  • the metal layer 102 is provided at a position avoiding the third side portion 108 , and the third side portion 108 is not covered with the metal layer 102 .
  • the third side surface portion 108 is a cut surface formed by cutting a metal plate (lead frame) used for manufacturing a semiconductor device, for example, and the surface of the base material 101 is exposed. In FIGS. 11 and 13, the cut surfaces formed by cutting the lead frames are hatched.
  • the length of each part of the first side wall 105 in the first direction x has the following relationship. As shown in FIGS. 11 and 13, a first dimension L1, which is the length of the first side portion 106 in the first direction x, corresponds to a second dimension L2, which is the length of the second side portion 107 in the first direction x. is smaller than Also, the ratio of the length L11 of the third side wall 108 in the first direction x to the length L10 of the first side wall 105 in the first direction x is in the range of 0.25 to 0.7 times.
  • the second side wall 115 faces the side opposite to the first side wall 105 in the second direction y. In this embodiment, the second side wall 115 faces the other side in the second direction y. As shown in FIGS. 9, 10, 12 and 14, the second side wall 115 has a fourth side portion 116, a fifth side portion 117 and a sixth side portion 118. As shown in FIGS. The fourth side surface portion 116 is positioned closer to the first end surface portion 104 in the first direction x. The fifth side surface portion 117 is positioned closer to the sealing resin 7 in the first direction x. The third side portion 108 is positioned between the fourth side portion 116 and the fifth side portion 117 in the first direction x.
  • the fourth side portion 116 and the fifth side portion 117 are located on one side of the sixth side portion 118 in the second direction y (the right side in FIGS. 9 and 10).
  • the fourth side surface portion 116 is located on one side in the second direction y as it separates from the sixth side surface portion 118 in the first direction x, and has a recessed arc shape when viewed in the thickness direction z.
  • the fifth side portion 117 has a fifth side first portion 117a and a fifth side second portion 117b.
  • the fifth side first portion 117a is a flat surface facing the other side in the second direction y (left side in FIGS. 9 and 10).
  • the fifth side second part 117b connects to both the fifth side first part 117a and the sixth side part 118, and is located on one side in the second direction y as it moves away from the sixth side part 118 in the first direction x. .
  • the fifth side second portion 117b has a recessed arc shape when viewed in the thickness direction z.
  • the sixth side surface portion 118 is a flat surface facing the other side in the second direction y (left side in FIGS. 9 and 10).
  • the metal layer 102 covers the fourth side portion 116 and the fifth side portion 117 of the second side wall 115 (the fourth side portion 116, the fifth side portion 117 and the sixth side portion 118).
  • the metal layer 102 is provided at a position avoiding the sixth side surface portion 118 , and the sixth side surface portion 118 is not covered with the metal layer 102 .
  • Sixth side surface portion 118 is a cut surface formed by cutting a metal plate (lead frame) used for manufacturing a semiconductor device, for example, and the surface of base material 101 is exposed. In FIGS. 12 and 14, the cut surfaces formed by cutting the lead frames are hatched.
  • the length of each part of the second side wall 115 in the first direction x has the following relationship. As shown in FIGS. 12 and 14, a third dimension L3, which is the length of the fourth side surface portion 116 in the first direction x, corresponds to a fourth dimension L4, which is the length of the fifth side surface portion 117 in the first direction x. is smaller than Also, the ratio of the length L13 of the sixth side wall 118 in the first direction x to the length L12 of the second side wall 115 in the first direction x is in the range of 0.25 to 0.7 times.
  • the metal layer 102 covers the first terminal extension portion 103 except for the third side portion 108 and the sixth side portion 118 .
  • the metal layer 102 includes a first end face portion 104 , a first side wall portion 106 connected to the first end face portion 104 , a first side face portion 106 of a first side wall 105 connected to the first end face portion 104 , and a first end face portion 104 and the fourth side surface portion 116 of the second side wall 115 leading to the second side wall 115 .
  • FIG. 18 is a plan view showing a part of a lead frame used in manufacturing the semiconductor device A10.
  • the lead frame 9 before cutting is indicated by an imaginary line (double-dot chain line).
  • the entire surface of the base material of the lead frame 9 is covered with a metal layer.
  • the lead frame 9 has a bar-shaped portion 91 extending in the second direction y, intersecting the middle of each of the plurality of first terminal portions 13 in the first direction x.
  • the bar-shaped portion 91 is formed with a plurality of recesses 911 to 914 each.
  • the concave portion 911 has a semicircular shape corresponding to the first side surface portion 106 of the first terminal extension portion 103 .
  • the concave portion 912 has a semicircular shape corresponding to the second side surface second portion 107 b of the first terminal extension portion 103 .
  • the concave portion 913 has a semicircular shape corresponding to the fourth side surface portion 116 of the first terminal extension portion 103 .
  • the concave portion 914 has a semicircular shape corresponding to the fifth side second portion 117 b of the first terminal extension portion 103 .
  • the center of the recesses 911, 912 in the second direction y is cut along the xz plane formed by the first direction x and the thickness direction z, and the recesses 913, 914 are cut in the second direction. Cut the center of y along the xz plane.
  • the plurality of first terminal extension portions 103 are formed with the third side portion 108 and the sixth side portion 118 serving as cut surfaces (surfaces of the base material 101).
  • the formation of the first terminal extension portions 103 (the third side surface portion 108 and the sixth side surface portion 118) in the plurality of second terminal portions 15 and the second terminal portions 18 is the same as that described above. The same method as in the case of the plurality of first terminal portions 13 is used.
  • the semiconductor element 2 is an element that exhibits the electrical functions of the semiconductor device A10.
  • the type of the semiconductor element 2 is not particularly limited, and in this embodiment, the semiconductor element 2 is configured as a transistor. As shown in FIGS. 3 and 6 to 8, the semiconductor element 2 has an element body 20, a first electrode 21, a second electrode 22 and a third electrode .
  • the element body 20 has a rectangular shape when viewed in the thickness direction z.
  • the element body 20 has an element main surface 201 and an element back surface 202 .
  • the element main surface 201 and the element back surface 202 face opposite sides in the thickness direction z.
  • the element main surface 201 faces the same side as the first surface 121 of the die pad 12 in the thickness direction z. Therefore, the element rear surface 202 faces the first surface 121 .
  • the first electrode 21 and the third electrode 23 are arranged on the main surface 201 of the element.
  • the second electrode 22 is arranged on the element back surface 202 .
  • the constituent material of the first electrode 21, the second electrode 22 and the third electrode 23 is, for example, one of copper and aluminum (Al), or an alloy thereof.
  • the first electrode 21 is the source electrode
  • the second electrode 22 is the drain electrode
  • the third electrode 23 is the gate electrode.
  • the first electrode 21 covers most of the element principal surface 201 .
  • the first electrode 21 is arranged in a region of the rectangular element main surface 201 excluding the peripheral edge and one corner (lower right corner in FIG. 3).
  • the first electrode 21 has a first electrode pad portion 212 .
  • the first electrode pad portion 212 is located inside the insulating portion 3 when viewed in the thickness direction z.
  • the third electrode 23 is arranged at one corner (lower right corner in FIG. 3) of the element main surface 201 .
  • the second electrode 22 covers the entire surface (or substantially the entire surface) of the element back surface 202 .
  • the second electrode 22 is electrically joined to the first surface 121 (die pad 12) via a conductive joint material 62.
  • the conductive bonding material 62 electrically connects the die pad 12 and the second electrode 22 .
  • Conductive bonding material 62 is, for example, solder.
  • the semiconductor device A10 includes a wire 65.
  • the wire 65 is electrically joined to the third electrode 23 and the pad portion 17 of the lead 1C.
  • a wire 65 electrically connects the third electrode 23 and the lead 1C.
  • the insulating portion 3 is arranged over the first electrode 21 and the element main surface 201. As shown in FIG. The insulating portion 3 has an annular shape overlapping with the outer peripheral edge of the first electrode 21 when viewed in the thickness direction z. The outer edge of the insulating portion 3 is positioned near the outer edge of the element main surface 201 when viewed in the thickness direction z. In the first electrode 21 , a region positioned inside the inner edge of the insulating portion 3 when viewed in the thickness direction z serves as the first electrode pad portion 212 .
  • the insulating portion 3 has, for example, a structure in which a plurality of insulating layers are laminated.
  • the insulating portion 3 has a structure in which an upper insulating layer made of a resin material is laminated on a lower insulating layer made of nitride, for example.
  • nitrides forming the lower insulating layer include SiN, SiON and SiO 2 .
  • the resin material forming the upper insulating layer include polyimide resin.
  • the metal laminate portion 4 is arranged over the first electrode 21 and the insulating portion 3, and has a structure in which, for example, a plurality of metal layers are laminated.
  • Metal lamination portion 4 has, for example, a structure in which a metal layer containing titanium (Ti), a metal layer containing nickel, and a metal layer containing silver (Ag) are laminated in this order.
  • the conducting member 5 is joined to the first electrode 21 of the semiconductor element 2 and the lead 1B.
  • the conducting member 5 is made of a metal plate.
  • the metal in question is copper or a copper alloy.
  • the conductive member 5 is a metal plate that is punched or bent.
  • the conducting member 5 has an element-side joint portion 51 , a lead-side joint portion 52 and an intermediate portion 53 .
  • the element-side joint portion 51, the lead-side joint portion 52, and the intermediate portion 53 are appropriately bent and connected when viewed in the second direction y.
  • the element-side joint portion 51 is joined to the first electrode pad portion 212 of the first electrode 21 via the conductive joint material 61 .
  • the conductive bonding material 61 conductively bonds the element-side bonding portion 51 (the conductive member 5 ) and the first electrode pad portion 212 .
  • Conductive bonding material 61 is, for example, solder.
  • the element-side joint portion 51 is formed with a projecting portion 511 and a recessed portion 512.
  • the protruding portion 511 protrudes downward (the other side in the thickness direction z) from the lower surface of the element-side joint portion 51 (the surface facing the element main surface 201).
  • two protrusions 511 are spaced apart in the first direction x, and each protrusion 511 extends in the second direction y with a constant width.
  • the recessed portion 512 is a portion partially recessed upward (one side in the thickness direction z) from the lower surface of the element-side joint portion 51 .
  • two recesses 512 are spaced apart in the second direction y, and each recess 512 extends in the first direction x with a constant width.
  • the protruding portion 511 is pressed against the first electrode pad portion 212 and a sufficient amount of the conductive joining material 61 is formed around the protruding portion 511 . exist. Thereby, the electrical connection between the element-side joint portion 51 and the first electrode pad portion 212 is properly maintained.
  • a recess 512 is provided on the lower surface of the element-side joint portion 51 . Thereby, even if there is a void in the conductive bonding material 61 , the void can be accommodated in the concave portion 512 . Therefore, voids in the conductive bonding material 61 can be suppressed.
  • a through-hole may be formed through the element-side joint portion 51 in the thickness direction z to suppress voids.
  • the lead-side joint portion 52 is joined to the pad portion 14 of the lead 1B via a conductive joint material 63.
  • the conductive bonding material 63 electrically connects the lead-side bonding portion 52 (the conductive member 5) and the pad portion 14 (the lead 1B).
  • Conductive bonding material 63 is, for example, solder.
  • the lead-side joint portion 52 has a convex portion positioned on the other side (lower side in the figure) in the thickness direction z than the surroundings. When the pad section 14 and the lead-side joint section 52 are joined together, the convex section is pressed against the pad section 14 and a sufficient amount of the conductive joint material 63 exists around the convex section. Thereby, the conduction between the lead-side joint portion 52 and the pad portion 14 is properly maintained.
  • the intermediate portion 53 is positioned between the element-side joint portion 51 and the lead-side joint portion 52 in the first direction x.
  • the intermediate portion 53 is connected to both the element-side joint portion 51 and the lead-side joint portion 52 .
  • a plurality of wires may be electrically connected to the first electrode 21 and the pad portion 14 of the lead 1B.
  • the semiconductor device of the present disclosure may be configured without the insulating portion 3 and the metal lamination portion 4 .
  • the encapsulating resin 7 partially covers the leads 1A, 1B and 1C, the semiconductor element 2, the insulating portion 3, the metal laminate portion 4, the conductive member 5, and the wires 65. More specifically, the sealing resin 7 seals at least a portion of the die pad 12 in the lead 1A, a plurality of second terminal portions 15, a portion of each of the plurality of second terminal portions 15 and the second terminal portion 18. covering. Sealing resin 7 is made of, for example, black epoxy resin.
  • the sealing resin 7 has a resin main surface 71, a resin back surface 72 and resin side surfaces 73 to 76.
  • the resin main surface 71 and the resin back surface 72 face opposite sides in the thickness direction z.
  • the resin main surface 71 faces one side in the thickness direction z, and faces the same side as the element main surface 201 and the first surface 121 .
  • the resin back surface 72 faces the other side in the thickness direction z, and faces the same side as the element back surface 202 and the back surface mounting portion 122 .
  • Each of the resin side surfaces 73 to 76 is connected to the resin main surface 71 and the resin back surface 72 and is sandwiched between the resin main surface 71 and the resin back surface 72 in the thickness direction z.
  • the resin side surface 73 and the resin side surface 74 face opposite sides in the first direction x.
  • the resin side surface 73 faces one side in the first direction x, and the resin side surface 74 faces the other side in the first direction x.
  • the resin side surface 75 and the resin side surface 76 face opposite sides in the second direction y.
  • the resin side surface 75 faces one side in the second direction y, and the resin side surface 76 faces the other side in the second direction y. As shown in FIG.
  • each of the plurality of first terminal portions 13 protrudes from the resin side surface 73 .
  • a part of each of the plurality of second terminal portions 15 and the second terminal portions 18 protrudes from the resin side surface 74 .
  • the resin side surfaces 73 to 76 are each slightly inclined with respect to the thickness direction z.
  • the shape of the sealing resin 7 shown in FIGS. 1, 2, and 4 to 8 is an example. The shape of the sealing resin 7 is not limited to the illustrated shape.
  • each of the leads 1A to 1C includes a base material 101 and a metal layer 102 covering the base material 101.
  • the base material 101 has first terminal extension portions 103 that configure the first terminal portion 13, the second terminal portion 15, and the second terminal portion 18, respectively.
  • the first terminal extension portion 103 is exposed from the sealing resin 7 and extends in the first direction x, and includes a first end face portion 104 facing the first direction x and a first side wall 105 facing the second direction y. ,including.
  • the first side wall 105 has a first side portion 106 , a second side portion 107 and a third side portion 108 .
  • the first side surface portion 106 is positioned closer to the first end surface portion 104 in the first direction x and is connected to the first end surface portion 104 .
  • the second side surface portion 107 is positioned closer to the sealing resin 7 .
  • the third side portion 108 is located between the first side portion 106 and the second side portion 107 .
  • the metal layer 102 is provided at a position that covers the first end face portion 104 , the first side face portion 106 and the second side face portion 107 and avoids the third side face portion 108 .
  • the first end surface portion 104 that is the tip portion of the first terminal extension portion 103 and the first side surface portion 106 of the first side wall 105 connected to the first end surface portion 104 are formed from the metal layer 102 .
  • metal burrs are not generated by cutting the lead frame 9 during the manufacture of the semiconductor device A10. This prevents metal burrs generated by cutting the lead frame 9 from protruding from the tips of the first terminal portion 13 , the second terminal portion 15 and the second terminal portion 18 . Therefore, for example, when the semiconductor device A10 is mounted on a circuit board, it is possible to suppress deterioration in mounting reliability.
  • the metal layer 102 covers the periphery of the tip portion of the first terminal extension portion 103 (the first end surface portion 104 and the first side surface portion 106).
  • the metal layer 102 is a plated layer and has better wettability to solder than the base material 101 . Therefore, when the semiconductor device A10 is soldered to a circuit board, the tip surfaces of the first terminal portion 13, the second terminal portion 15, and the second terminal portion 18 and the side surfaces connected thereto are covered with solder. As a result, the mounting strength of the semiconductor device A10 can be increased, and the mounting reliability of the semiconductor device A10 can be improved.
  • the first terminal extension 103 includes a second side wall 115 .
  • the second side wall 115 faces the side opposite to the first side wall 105 in the second direction y (the other side in the second direction y).
  • the second side wall 115 has a fourth side portion 116 , a fifth side portion 117 and a sixth side portion 118 .
  • the fourth side surface portion 116 is positioned closer to the first end surface portion 104 in the first direction x and is connected to the first end surface portion 104 .
  • the fifth side surface portion 117 is positioned closer to the sealing resin 7 .
  • the sixth side portion 118 is located between the fourth side portion 116 and the fifth side portion 117 .
  • the metal layer 102 is provided at a position that covers the fourth side portion 116 and the fifth side portion 117 and avoids the sixth side portion 118 .
  • the first end surface portion 104 which is the tip portion of the first terminal extension portion 103, the first side surface portion 106 of the first side wall 105 connected to the first end surface portion 104, and the first end surface portion Since the fourth side wall portion 116 of the second side wall 115 connected to 104 is covered with the metal layer 102, metal burrs are not generated by cutting the lead frame 9 during the manufacture of the semiconductor device A10.
  • metal burrs generated by cutting the lead frame 9 are prevented from protruding from the tips of the first terminal portion 13, the second terminal portion 15, and the second terminal portion 18 more accurately. Therefore, for example, when the semiconductor device A10 is mounted on a circuit board, it is possible to further suppress deterioration in mounting reliability.
  • the ratio of the length L11 in the first direction x of the third side wall 108 to the length L10 in the first direction x of the first side wall 105, and the ratio of the length L11 in the first direction x of the second side wall 115 to the length L12 in the first direction x of the sixth side wall The ratio of the length L13 of 118 in the first direction x is 0.25 to 0.7 times, which is relatively small.
  • the areas of the third side portion 108 and the sixth side portion 118, which are the cut surfaces of the lead frame 9 can be reduced.
  • the load when cutting the lead frame 9 can be reduced, and the occurrence of metal burrs can be suppressed. This is more preferable for suppressing deterioration in mounting reliability of the semiconductor device A10.
  • the first side portion 106 and the second side portion 107b are located on the other side in the second direction y as they move away from the third side portion 108 in the first direction x.
  • the fourth side surface portion 116 and the fifth side surface second portion 117b are located on one side in the second direction y as they are separated from the sixth side surface portion 118 in the first direction x.
  • Such a shape is formed by cutting the center of the constricted recesses 911 and 912 and the center of the constricted recesses 913 and 914 in the lead frame 9 . As a result, the load at the time of cutting the lead frame 9 can be further reduced, and the occurrence of metal burrs can be further suppressed. This is more preferable for suppressing deterioration in mounting reliability of the semiconductor device A10.
  • the mounting strength of the semiconductor device A10 can be further increased.
  • FIG. 19 to 21 show a semiconductor device A11 according to a first modification of the first embodiment.
  • FIG. 19 is a plan view showing the semiconductor device A11.
  • FIG. 20 is a partially enlarged view of FIG. 19 (an enlarged view around the first terminal portion 13).
  • FIG. 20 is a partially enlarged view of FIG. 19 (an enlarged view of the periphery of the second terminal portions 15 and 18).
  • elements identical or similar to those of the semiconductor device A10 of the above embodiment are assigned the same reference numerals as those of the above embodiment, and description thereof will be omitted as appropriate.
  • the configurations of the first side walls 105 and the second side walls 115 are the same as those of the above embodiments. is different from In this modification, the first side surface portion 106 and the second side surface portion 107 have a stepped shape on the other side in the second direction y with respect to the third side surface portion 108 . Similarly, the fourth side portion 116 and the fifth side portion 117 have a stepped shape on one side of the sixth side portion 118 in the second direction y.
  • FIG. 22 is a plan view showing a part of a lead frame used in manufacturing the semiconductor device A10.
  • the lead frame 9 before cutting is indicated by an imaginary line (double-dot chain line).
  • the entire surface of the base material of the lead frame 9 is covered with a metal layer.
  • the lead frame 9 has a bar-shaped portion 91 extending in the second direction y, intersecting the middle of each of the plurality of first terminal portions 13 in the first direction x.
  • the width of the bar-shaped portion 91 in the first direction x is relatively small.
  • the bar-shaped portion 91 of the lead frame 9 is cut along the xz plane in the vicinity of the first side portion 106 and the second side portion 107 and in the vicinity of the fourth side portion 116 and the fifth side portion 117 .
  • the plurality of first terminal extension portions 103 are formed with the third side portion 108 and the sixth side portion 118 serving as cut surfaces (surfaces of the base material 101).
  • the formation of the first terminal extension portions 103 (the third side surface portion 108 and the sixth side surface portion 118) in the plurality of second terminal portions 15 and the second terminal portions 18 is the same as that described above. The same method as in the case of the plurality of first terminal portions 13 is used.
  • the first end surface portion 104 that is the tip portion of the first terminal extension portion 103 and the first side surface portion 106 of the first side wall 105 connected to the first end surface portion 104 are Since it is covered with the metal layer 102, metal burrs are not generated by cutting the lead frame 9 when manufacturing the semiconductor device A10. This prevents metal burrs generated by cutting the lead frame 9 from protruding from the tips of the first terminal portion 13 , the second terminal portion 15 and the second terminal portion 18 . Therefore, for example, when the semiconductor device A11 is mounted on a circuit board, it is possible to suppress deterioration in mounting reliability. In addition, within the range of the configuration similar to that of the semiconductor device A10 of the above embodiment, the same effects as those of the above embodiment can be obtained.
  • FIG. 23 to 25 show a semiconductor device A12 according to a second modification of the first embodiment.
  • FIG. 23 is a plan view showing the semiconductor device A12.
  • FIG. 24 is a partially enlarged view of FIG. 23 (an enlarged view of the periphery of the first terminal portion 13).
  • FIG. 25 is a partially enlarged view of FIG. 23 (an enlarged view of the periphery of the second terminal portions 15 and 18).
  • the configurations of the first side walls 105 and the second side walls 115 are the same as those of the above embodiments. is different from In this modified example, the second side surface portion 107 has a stepped shape on the other side in the second direction y with respect to the third side surface portion 108 . Similarly, the fifth side portion 117 has a stepped shape on one side in the second direction y with respect to the sixth side portion 118 .
  • FIG. 26 is a plan view showing a part of a lead frame used in manufacturing the semiconductor device A10.
  • the lead frame 9 before cutting is indicated by an imaginary line (double-dot chain line).
  • the entire surface of the base material of the lead frame 9 is covered with a metal layer.
  • the lead frame 9 has a bar-shaped portion 91 extending in the second direction y, intersecting the middle of each of the plurality of first terminal portions 13 in the first direction x.
  • the bar-shaped portion 91 is formed with a plurality of recesses 911 and 913 each.
  • the concave portion 911 has a semicircular shape corresponding to the first side surface portion 106 of the first terminal extension portion 103 .
  • the concave portion 913 has a semicircular shape corresponding to the fourth side surface portion 116 of the first terminal extension portion 103 .
  • the center of the recess 911 in the second direction y is cut along the xz plane, and the center of the recess 913 in the second direction y is cut along the xz plane.
  • the plurality of first terminal extension portions 103 are formed with the third side portion 108 and the sixth side portion 118 serving as cut surfaces (surfaces of the base material 101).
  • first terminal extension portions 103 (the third side surface portion 108 and the sixth side surface portion 118) in the plurality of second terminal portions 15 and the second terminal portions 18 is the same as that described above. The same method as in the case of the plurality of first terminal portions 13 is used.
  • the first end surface portion 104 that is the tip portion of the first terminal extension portion 103 and the first side surface portion 106 of the first side wall 105 connected to the first end surface portion 104 are Since it is covered with the metal layer 102, metal burrs are not generated by cutting the lead frame 9 when manufacturing the semiconductor device A10. This prevents metal burrs generated by cutting the lead frame 9 from protruding from the tips of the first terminal portion 13 , the second terminal portion 15 and the second terminal portion 18 . Therefore, for example, when the semiconductor device A12 is mounted on a circuit board, it is possible to suppress deterioration in mounting reliability. In addition, within the range of the configuration similar to that of the semiconductor device A10 of the above embodiment, the same effects as those of the above embodiment can be obtained.
  • a semiconductor device A20 includes a plurality of leads 1A, 1C, 1D, a semiconductor element 2, conductive bonding materials 61, 62, 64, and a sealing resin 7.
  • FIG. 1 A semiconductor device A20 includes a plurality of leads 1A, 1C, 1D, a semiconductor element 2, conductive bonding materials 61, 62, 64, and a sealing resin 7.
  • FIG. 27 is a plan view showing the semiconductor device A20.
  • FIG. 28 is a bottom view showing the semiconductor device A20.
  • FIG. 29 is a plan view showing the semiconductor device A20.
  • FIG. 30 is a right side view showing the semiconductor device A20.
  • FIG. 31 is a left side view of the semiconductor device A20.
  • 32 is a cross-sectional view taken along line XXXII-XXXII of FIG. 29.
  • FIG. 33 is a cross-sectional view taken along line XXXIII-XXXIII of FIG. 29.
  • FIG. 34 is a cross-sectional view taken along line XXXIV-XXXIV of FIG. 29.
  • FIG. FIG. 35 is a partially enlarged view of FIG. 27 (an enlarged view of the periphery of second terminal portions 18 and 192, which will be described later). It should be noted that FIG. 29 is transparent through the sealing resin 7 for convenience of understanding.
  • the semiconductor device A20 of this embodiment includes two semiconductor elements 2, and various modifications have been made accordingly.
  • the two semiconductor elements 2 are arranged in pairs on one side in the second direction y (right side in FIG. 29) and the other side in the second direction y (left side in FIG. 29).
  • the semiconductor element 2 leads 1A, 1C and 1D, and conductive bonding materials 61, 62 and 64 are arranged on one side and the other side in the second direction y, respectively.
  • each semiconductor element 2 is, for example, a power semiconductor chip having a switching function such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). It is used as
  • the lead 1A has a die pad 12 and a plurality of (two in this embodiment) first terminal portions 13. As shown in FIG. In this embodiment, the configuration of each of the plurality of first terminal portions 13 is substantially the same as that of the first terminal portion 13 of the semiconductor device A10 according to the first embodiment. Therefore, the base material 101 of the lead 1A is provided with a plurality of first terminal extension portions 103 corresponding to the plurality of first terminal portions 13, respectively. Although detailed illustration is omitted, the first terminal extension portion 103 includes a first end face portion 104 , a first side wall 105 and a second side wall 115 .
  • the first side wall 105 has a first side portion 106, a second side portion 107 and a third side portion 108, as shown in FIGS. 9 and 11 referring to the semiconductor device A10.
  • the second side wall 115 has a fourth side portion 116, a fifth side portion 117 and a sixth side portion 118 as shown in FIGS. 9 and 12 with reference to the semiconductor device A10.
  • the formation of the first terminal extension portions 103 (the third side surface portion 108 and the sixth side surface portion 118) in the plurality of first terminal portions 13 is similar to the formation of the plurality of first terminal portions 108 in the semiconductor device A10. The same method as for the one-terminal portion 13 is used.
  • the lead 1C has a pad portion 17 and a second terminal portion 18. As shown in FIGS. The pad portion 17 is located inside the second terminal portion 18 in the first direction x. The pad portion 17 is bonded to the third electrode 23 of the semiconductor element 2 via the conductive bonding material 64 . The conductive bonding material 64 conductively bonds the pad portion 17 (the lead 1C) and the third electrode 23 .
  • the second terminal portion 18 is positioned on the other side in the first direction x (left side in FIG. 32) with respect to the die pad 12 of the lead 1A. In this embodiment, the second terminal portion 18 is exposed from the sealing resin 7 and extends to the other side in the first direction x while bending halfway.
  • the lead 1D has an element-side joint portion 191, a second terminal portion 192 and an intermediate portion 193.
  • the element-side joint portion 191 is joined to the first electrode 21 via the conductive joint material 61 .
  • the conductive bonding material 61 electrically connects the element-side bonding portion 191 (lead 1D) and the first electrode 21 .
  • the element-side joint portion 191 is formed with a projecting portion 191a.
  • the protruding portion 191a protrudes downward (the other side in the thickness direction z) from the lower surface of the element-side joint portion 191 (the surface facing the element main surface 201).
  • two protrusions 191a are spaced apart in the first direction x, and each protrusion 191a extends in the second direction y with a constant width.
  • the second terminal portion 192 is located on the other side in the first direction x (left side in FIG. 333) with respect to the die pad 12 of the lead 1A.
  • the second terminal portion 192 is exposed from the sealing resin 7 and extends to the other side in the first direction x while being bent in the middle.
  • the second terminal portion 192 is an example of a “terminal portion” that extends in a direction orthogonal to the thickness direction z (the first direction x in the illustrated example) as a longitudinal direction.
  • the second terminal portion 192 has a back surface mounting portion 194 .
  • the back mounting portion 194 faces the other side in the thickness direction z (lower side in FIG. 33).
  • the back surface mounting portion 194 is a portion that is joined with a joining material such as solder when the semiconductor device A20 is mounted on a circuit board (not shown).
  • the second terminal portion 18 of the lead 1C and the second terminal portion 192 of the lead 1D are spaced apart in the second direction y.
  • the two second terminal portions 18 of the two leads 1C and the two second terminal portions 192 of the two leads 1D are alternately spaced apart in the second direction y.
  • the intermediate portion 193 is positioned between the element-side joint portion 191 and the second terminal portion 192 in the first direction x.
  • the intermediate portion 193 is connected to both the element-side joint portion 191 and the second terminal portion 192 .
  • each of the second terminal portion 18 and the second terminal portion 192 includes a first side wall 105 and a second side wall 115, as shown in FIGS.
  • the configurations of the first side wall 105 and the second side wall 115 are different from those of the first embodiment.
  • the third side surface portion 108 and the sixth side surface portion 118 are provided on the curved portions of the second terminal portions 18 and 192 .
  • the first side surface portion 106 and the second side surface portion 107 have a stepped shape on the other side in the second direction y with respect to the third side surface portion 108 .
  • the fourth side portion 116 and the fifth side portion 117 have a stepped shape on one side of the sixth side portion 118 in the second direction y.
  • each of the second terminal portions 18 and 192 has a first tip surface 119 instead of the first end surface portion 104 of the semiconductor device A10 of the above embodiment.
  • the first tip surface 119 is positioned at the tip in the direction (first direction x) in which the second terminal portions 18 and 192 extend, and faces one side in the first direction x.
  • the first tip surface 119 is not covered with the metal layer 102 .
  • First tip surface 119 is a cut surface formed by cutting a metal plate (lead frame) used for manufacturing a semiconductor device, for example, and the surface of base material 101 is exposed.
  • the semiconductor device A20 of the present embodiment in each of the plurality of first terminal portions 13, the first end surface portion 104 which is the tip portion of the first terminal extension portion 103 and the first end surface portion 104 connected to the first end surface portion 104 Since the first side surface portion 106 of the first side wall 105 is covered with the metal layer 102, metal burrs are not generated by cutting the lead frame during the manufacture of the semiconductor device A20. This prevents metal burrs generated by cutting the lead frame from protruding from the tip of the first terminal portion 13 . Therefore, for example, when the semiconductor device A20 is mounted on a circuit board, deterioration in mounting reliability can be suppressed.
  • the metal layer 102 covers the periphery of the tip portion of the first terminal extension portion 103 (the first end surface portion 104 and the first side surface portion 106).
  • the metal layer 102 is a plated layer and has better wettability to solder than the base material 101 . Therefore, when the semiconductor device A20 is soldered to a circuit board, the tip surface of the first terminal portion 13 and the side surface connected thereto are covered with solder. As a result, the mounting strength of the semiconductor device A20 can be increased, and the mounting reliability of the semiconductor device A20 can be improved.
  • the same effects as those of the above embodiment can be obtained.
  • FIG. 36 to 39 show a semiconductor device A21 according to a modification of the second embodiment.
  • FIG. 36 is a plan view showing the semiconductor device A21.
  • 37 is a cross-sectional view taken along line XXXVII-XXXVII of FIG. 36.
  • FIG. 38 is a cross-sectional view taken along line XXXVIII-XXXVIII of FIG. 36.
  • FIG. 39 is a partially enlarged view of FIG. 36 (an enlarged view of the periphery of the second terminal portions 18 and 192). It should be noted that FIG. 36 is transparent through the sealing resin 7 for convenience of understanding.
  • the base material 101 forming the leads 1C and 1D has first terminal extension portions 103.
  • FIG. in this modification, the base material 101 of each of the leads 1C and 1D has a first terminal extension portion 103.
  • a base material 101 of the lead 1 ⁇ /b>C is provided with a first terminal extension portion 103 corresponding to the second terminal portion 18 .
  • the first terminal extension portion 103 is a portion forming the second terminal portion 18 .
  • a first terminal extension portion 103 is provided corresponding to the second terminal portion 192 on the base material 101 of the lead 1D.
  • the first terminal extension portion 103 is a portion forming the second terminal portion 192 .
  • Each first terminal extension portion 103 in the second terminal portion 18 and the second terminal portion 192 is exposed from the sealing resin 7 and extends in a direction perpendicular to the thickness direction z (first direction x in this embodiment) as a whole. extends to Here, "the first terminal extension portion 103 as a whole extends in the first direction x" means that even when a part of the first terminal extension portion 103 includes a bent shape as in the present modification, It means that the one-terminal extension portion 103 as a whole extends in the first direction x.
  • Each first terminal extension 103 in the second terminal portion 18 and the second terminal portion 192 includes a first end face portion 104 , a first side wall 105 and a second side wall 115 .
  • each first terminal extension portion 103 of the second terminal portion 18 and the second terminal portion 192 the configurations of the first side wall 105 and the second side wall 115 are different from those of the first embodiment.
  • the third side surface portion 108 and the sixth side surface portion 118 are provided at the bent portion of the first terminal extension portion 103 .
  • the first side surface portion 106 and the second side surface portion 107 have a stepped shape on the other side in the second direction y with respect to the third side surface portion 108 .
  • the fourth side portion 116 and the fifth side portion 117 have a stepped shape on one side of the sixth side portion 118 in the second direction y.
  • FIG. 40 is a plan view showing a part of a lead frame used in manufacturing the semiconductor device A21.
  • the lead frame 9 before cutting is indicated by an imaginary line (double-dot chain line).
  • the entire surface of the base material of the lead frame 9 is covered with a metal layer.
  • the lead frame 9 has a bar-shaped portion 91 extending in the second direction y, intersecting the middle of each of the plurality of second terminal portions 18 and the plurality of second terminal portions 192 in the first direction x.
  • the width of the bar-shaped portion 91 in the first direction x is relatively small.
  • the bar-shaped portion 91 of the lead frame 9 is cut along the xz plane in the vicinity of the first side portion 106 and the second side portion 107 and in the vicinity of the fourth side portion 116 and the fifth side portion 117 .
  • the plurality of first terminal extension portions 103 are formed with the third side portion 108 and the sixth side portion 118 serving as cut surfaces (surfaces of the base material 101).
  • the tip portion of the first terminal extension portion 103 is Since the first end face portion 104 and the first side face portion 106 of the first side wall 105 connected to the first end face portion 104 are covered with the metal layer 102, the lead frame 9 is cut when manufacturing the semiconductor device A21. There is no metal burr caused by This prevents metal burrs generated by cutting the lead frame 9 from protruding from the tips of the first terminal portion 13 , the second terminal portion 18 and the second terminal portion 192 . Therefore, for example, when the semiconductor device A21 is mounted on a circuit board, deterioration in mounting reliability can be suppressed.
  • the metal layer 102 covers the periphery of the tip portion of the first terminal extension portion 103 (the first end surface portion 104 and the first side surface portion 106).
  • the metal layer 102 is a plated layer and has better wettability to solder than the base material 101 . Therefore, when the semiconductor device A21 is soldered to the circuit board, the tip surfaces and the side surfaces connected thereto of the first terminal portion 13, the second terminal portion 18, and the second terminal portion 192 are covered with solder. As a result, the mounting strength of the semiconductor device A21 can be increased, and the mounting reliability of the semiconductor device A21 can be improved.
  • the same effects as those of the above embodiment can be obtained.
  • the semiconductor device according to the present disclosure is not limited to the above-described embodiments.
  • the specific configuration of each part of the semiconductor device according to the present disclosure can be changed in various ways.
  • all of the plurality of terminal portions (the plurality of first terminal portions 13, the plurality of second terminal portions 15, and the second terminal portion 18) have the first terminal extension portion 103.
  • the present disclosure is not limited to this.
  • Some of the plurality of terminal portions may have the first terminal extension portion.
  • each terminal portion located at four corners of the semiconductor device when viewed in the thickness direction has the first terminal extension portion. may be configured.
  • Appendix 1 a lead including a die pad having a first surface facing one side in the thickness direction and a plurality of terminal portions; a semiconductor element mounted on the first surface; a sealing resin that covers at least a portion of the semiconductor element, the die pad, and a portion of each of the plurality of terminal portions; the lead includes a base material and a metal layer covering a portion of the base material; the base material has a first terminal extension portion that constitutes at least one of the plurality of terminal portions; The first terminal extension portion is exposed from the sealing resin and extends in a first direction orthogonal to the thickness direction, and is configured to have a first end face portion facing the first direction, the thickness direction and the a first sidewall facing a second direction orthogonal to the first direction; The first side wall includes a first side surface portion located closer to the first end surface portion in the first direction, a second side surface portion located closer to the sealing resin in the first direction, and a a third side portion located between the
  • Appendix 2 The semiconductor device according to Appendix 1, wherein each of the plurality of terminal portions extends in the first direction.
  • Appendix 3. The plurality of terminal portions includes a plurality of first terminal portions, Each of the plurality of first terminal portions is positioned on one side of the die pad in the first direction, extends in the one side of the first direction, and is spaced apart in the second direction. 3.
  • the semiconductor device according to appendix 2. Appendix 4.
  • Appendix 3 The semiconductor device according to appendix 3, wherein each of the plurality of first terminal portions is connected to one side of the die pad in the first direction. Appendix 5.
  • the plurality of terminal portions includes a plurality of second terminal portions, Each of the plurality of second terminal portions is positioned on the other side in the first direction with respect to the die pad, extends in the other side in the first direction, and is spaced apart in the second direction. 5.
  • the semiconductor device according to appendix 4. Appendix 6. Among the plurality of first terminal portions, those located at one side end and the other side end in the second direction, and among the plurality of second terminal portions located at one side end and the other side end in the second direction. 6.
  • Appendix 7. 7.
  • Appendix 9. The semiconductor device according to appendix 8, wherein the first side portion is located on the other side in the second direction as the distance from the third side portion increases in the first direction.
  • the second side surface portion is connected to a second side surface first portion that is a flat surface facing one side in the second direction, the second side surface first portion and the third side surface portion, and in the first direction 10.
  • the semiconductor device according to any one of appendices 1 to 10, wherein a first dimension in the first direction of the first side portion is smaller than a second dimension in the first direction of the second side portion.
  • Appendix 12. Any one of appendices 1 to 11, wherein a ratio of the length of the third side wall in the first direction to the length of the first side wall in the first direction is in the range of 0.25 to 0.7 times.
  • the semiconductor device according to . Appendix 13.
  • the first terminal extension includes a second side wall facing the side opposite to the first side wall in the second direction;
  • the second side wall includes a fourth side portion positioned closer to the first end face portion in the first direction, a fifth side portion positioned closer to the sealing resin in the first direction, and a a sixth side portion located between the fourth side portion and the fifth side portion; 13.
  • Appendix 14. 14 The semiconductor device according to appendix 13, wherein the sixth side portion is a flat surface facing the other side in the second direction. Appendix 15. 15.
  • Appendix 16. 16 The semiconductor device according to appendix 15, wherein the fourth side portion is located on one side in the second direction as the distance from the sixth side portion increases in the first direction.
  • the fifth side portion is connected to a fifth side first portion which is a flat surface facing the other side of the second direction, the fifth side first portion and the sixth side portion, and is connected to the first side portion and the sixth side portion in the first direction.
  • the semiconductor device according to appendix 15 or 16 further comprising a fifth side second portion located on one side in the second direction as the distance from the sixth side portion increases. Appendix 18. 18.

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
PCT/JP2022/043496 2021-12-03 2022-11-25 半導体装置 Ceased WO2023100754A1 (ja)

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JP2023564928A JPWO2023100754A1 (https=) 2021-12-03 2022-11-25
DE112022005309.7T DE112022005309T5 (de) 2021-12-03 2022-11-25 Halbleiterbauteil
US18/652,315 US20240282690A1 (en) 2021-12-03 2024-05-01 Semiconductor device

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008106339A (ja) * 2006-10-27 2008-05-08 Renesas Technology Corp 半導体装置の製造方法
JP2014093431A (ja) * 2012-11-05 2014-05-19 Renesas Electronics Corp 半導体装置およびその製造方法
JP2017037898A (ja) * 2015-08-07 2017-02-16 新光電気工業株式会社 リードフレーム、半導体装置及びリードフレームの製造方法
JP2019125768A (ja) * 2018-01-15 2019-07-25 ローム株式会社 半導体装置、および半導体装置の製造方法
WO2021199635A1 (ja) * 2020-03-30 2021-10-07 ローム株式会社 半導体装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6721346B2 (ja) 2016-01-27 2020-07-15 ローム株式会社 半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008106339A (ja) * 2006-10-27 2008-05-08 Renesas Technology Corp 半導体装置の製造方法
JP2014093431A (ja) * 2012-11-05 2014-05-19 Renesas Electronics Corp 半導体装置およびその製造方法
JP2017037898A (ja) * 2015-08-07 2017-02-16 新光電気工業株式会社 リードフレーム、半導体装置及びリードフレームの製造方法
JP2019125768A (ja) * 2018-01-15 2019-07-25 ローム株式会社 半導体装置、および半導体装置の製造方法
WO2021199635A1 (ja) * 2020-03-30 2021-10-07 ローム株式会社 半導体装置

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US20240282690A1 (en) 2024-08-22

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