CN101257008B - 半导体装置 - Google Patents
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Abstract
本发明在将多个半导体芯片安装到引线架上的半导体装置中,减小其平面尺寸及厚度而实现小型化。通过将第一岛区域(12)的背面与第二岛区域(13)的表面至少局部重叠而配置,使第一岛区域上的第一半导体芯片与所述第二岛区域背面的第二半导体芯片重叠。因此,能够将平面的占有面积减小到比两芯片的平面面积小。另外,与第二半导体芯片(20)连接的金属细线由于向背侧延伸,故能够将半导体装置的厚度也减薄。
Description
技术领域
本发明涉及一种半导体装置。
背景技术
通常,使用有引线架的半导体装置配置有岛区域、一端设置在岛区域周围的多根引线,并且在岛区域之上设置有半导体芯片,由金属细线将所述半导体芯片的接合焊盘与所述引线的一端连接(例如,专利文献1)。另外,以使所述多根引线的另一端露出的方式,由绝缘性树脂将所述岛区域、所述多根引线、半导体芯片以及多根金属细线密封。在此,在多根引线中,将被所述绝缘性树脂密封的部分称为内引线,将从绝缘性树脂露出的部分称为外引线,根据需要而将该外引线折曲,通过焊接等将所述引线的另一端安装在印刷电路板等上。
另外,也实现了在岛区域上层积多个芯片而构成的叠层型半导体装置。其是在主芯片上层积尺寸比主芯片尺寸小的副芯片的结构,由金属细线也将主芯片与副芯片电连接。
专利文献1:(日本)特开2007-5569号公报
上述那样的半导体装置可利用目前的轻薄短小的技术而实现小型化。但是,由于副芯片表面与主芯片的表面相比,配置在距离岛区域表面更高的位置上,因此若由金属细线与副芯片表面之上连接,则金属细线的顶部变得更高,具有半导体装置的厚度、即封装的厚度增加的问题。
发明内容
因此,本发明的目的在于提供一种半导体装置,不增大封装的厚度即可安装多个芯片。
本发明的半导体装置,内设有层积配置的第一半导体芯片及第二半导体芯片,其特征在于,所述第一半导体芯片固定在第一岛区域的上表面,所述第二半导体芯片固定在第二岛区域的下表面,所述第一岛区域和所述第二岛区域位于所述第一半导体芯片与所述第二半导体芯片之间,并且二者分开配置。
根据本发明,通过将第一岛区域的背面与第二岛区域的表面至少局部重叠而配置,使第一岛区域上的第一半导体芯片与所述第二岛区域背面的第二半导体芯片重叠。
因此,能够将平面的占有面积减少到小于两芯片的平面面积。而且,由于第二半导体芯片的金属细线向背面侧延伸,故也可以减小半导体装置的厚度。
附图说明
图1是说明本发明的半导体装置的剖面图。
图2是说明本发明的半导体装置的平面图。
图3是说明本发明的半导体装置所采用的第一引线架的图。
图4是说明本发明的半导体装置所采用的第二引线架的图。
图5是说明本发明的半导体装置的平面图。
图6是说明本发明的半导体装置所采用的第一引线架的图。
图7是说明本发明的半导体装置所采用的第二引线架的图。
图8是表示本发明的半导体装置的图,图8A是剖面图,图8B是平面图,图8C是剖面图。
附图标记说明
10:第一引线架;11:第二引线架;12:第一岛区域;13:第二岛区域;14:第一引线;15:第二引线;16:引线;17:第一半导体芯片;18:金属细线;19:引线;20:第二半导体芯片;21:第一接合部;22:第二接合部;31:连接部;33:第二连接部;35:连接部;37:连接部;40:绝缘性树脂;50:半导体装置;52:连接部;54:引线;55:吊线;56:金属细线;57:吊线;58:金属细线;60:电极;62:电极
具体实施方式
参照附图说明本发明的实施方式。图1是半导体装置的剖面图,图2是半导体装置的平面图,图3、图4是半导体装置的分解图。
首先,在说明图1及图2所示的本发明的半导体装置之前,参照图3及图4进行说明。简单地说明,本发明是将图3的第一引线架10和图4的第二引线架11重叠的结构,例如,第一引线架10的第一岛区域12和第二引线架11的第二岛区域13至少局部重叠。另外,若形成其他的表现方式,则第一引线架10的第一引线14和第二引线架11的第二引线15至少局部重叠。
具体地,参照图3说明第一引线架10。首先,该第一引线架10由第一岛区域12、一端与该第一岛区域12成为一体且另一端向左侧延伸的至少一根(在此为两根)引线16、位于第一岛区域12附近且一端位于岛区域的右侧边、另一端向右侧延伸的至少一根第一引线14(在此为两根)构成。在此,向第一岛区域12的左右各延伸有两根引线。另外,第一引线14的一端被加工成矩形,将该一端活用作第一接合部21。
另外,在第一岛区域12的表面设置有第一半导体芯片17,将第一半导体芯片17上面形成的电极(在纸面上在圆中描画斜线的部分)与第一引线14的第一接合部21电连接。在此,采用了金属细线18,但也可以由金属板等进行连接。
另一方面,参照图4说明第二引线架11。该第二引线架11的基本形状与第一引线架10相同,由第二岛区域13、一端与该第二岛区域13成为一体且另一端向左侧延伸的至少一根引线19、位于第二岛区域13附近且一端位于该岛区域的右侧边、另一端向右侧延伸的至少一根第二引线15构成。在此,向第二岛区域13的左右各延伸有两根引线。另外,在第二岛区域13的背面设置有第二半导体芯片20,将第二半导体芯片20上的电极(纸面上在圆中描画斜线的部分)与第二引线15的第二接合部22电连接。在此,采用了金属细线18,但也可以由金属板等进行连接。另外,第二引线15的一端被加工成矩形,将该一端活用作第二接合部22。
(第一实施方式)
参照图1、图2具体说明第一实施方式。该半导体装置是使参照图3及图4说明的第一引线架10和第二引线架11局部重叠的结构。即,位于图1上侧的岛区域相当于图3的第一岛区域12,位于图1下侧的岛区域相当于图4的第二岛区域13。在此,为了将第一岛区域12与第二岛区域13电绝缘,需要使二者分离距离L。
该分离距离L至少需要为50μm。现有的半导体装置是将图3和图4所示的引线架直接横向配置的结构。为了进行安装,而需要有将第一岛区域12和第二岛区域13直接相加的面积。但是,本发明如图2所示,由于将第一岛区域12的背面与第二岛区域13的表面至少局部重叠,能够将平面上看到的岛区域的占有面积也缩小。
另一方面,第一引线14的背面和第二引线15的表面,与岛区域同样地至少分离约50μm。参照图1及图2,第一引线14、第二引线15的结构如下。即,从第一接合部21向下倾斜而设有第一倾斜部30,在该倾斜部30的端部水平地设有第一连接部31。另外,从第二接合部22向下倾斜而设有第二倾斜部32,在该倾斜部32的端部水平地设有第二连接部33。
另外,引线16、19也同样地,与第一岛区域12一体构成的引线设有自此向下倾斜的倾斜部34,在该倾斜部34的端部设有连接部35。另外,与第二岛区域13一体构成的引线37设有自此向下倾斜的倾斜部36,在该倾斜部36的端部设有连接部37。
如前所述,在本发明中,第一岛区域12与第二岛区域13以距离L分离开来,还设有以该分离距离或与该分离距离接近的距离分离开的第一接合部21、第二接合部22。另外,只要使自此延伸的倾斜部和连接部、从第一岛区域12、第二岛区域13向左延伸的倾斜部和连接部相互不接触而配置即可。
另外,由绝缘性树脂40将第一引线架10、第二引线架11密封。并且在该绝缘性树脂40的背面使连接部31、33、35、37的背面露出。
如以上说明,第一岛区域12的背面和第二岛区域13的表面在纵向上离开距离L,并且第一岛区域12和第二岛区域13至少局部重叠,因此,能够将平面上看到的岛区域的占有面积减少。位于第二岛区域13的倾斜部向斜下方延伸,在该延伸部分可配置第二半导体芯片20、金属细线,因而无需另外设置相应的厚度,具有半导体装置的厚度也可减薄的特点。
参照图1,第一半导体芯片17的下表面与第二半导体芯片20的上表面的距离L11被设定为,比第一岛区域12的厚度与第二岛区域13的厚度相加后的长度要长。
具体地,第一岛区域12的厚度(L12)和第二岛区域13的厚度(L13)相加后的长度例如为1mm左右,第一半导体芯片17的下表面与第二半导体芯片20的上表面的距离L11设定为比1.05mm长。由此,在半导体装置的狭小空间中,即使内设有安装于岛区域上的多个半导体芯片,也能够防止半导体芯片经由岛区域而彼此短路。
(第二实施方式)
接着,说明第二实施方式。第一实施方式中仅对岛区域的重叠进行了说明,在本实施方式中,也包含第一接合部21与第二接合部22重叠的情况。
通常,接合部(接合端子)由于利用金属细线进行连接,故接合工具的头部必须与接合部抵接。因此,相邻的两个接合部的间隔需要至少为规定的距离。但是,在本发明的半导体装置中,例如第一接合部21和相邻的第二接合部22为表面与背面的关系,故而能够使其之间的距离比所述规定的距离还小。因此,第一接合部21和第二接合部22可至少使局部重叠。在本实施方式中,在第一引线14彼此之间的中央部附近配置有第二引线15。
具体地,使用图3进行说明。第一引线14的宽度约0.1mm,第一接合部21的尺寸(宽度)为0.2~0.25mm。因此,若例如第一接合部21的一边宽度为0.25mm,则第一接合部21的端部从第一引线14的中心突出0.125mm、即从第一引线14的上下侧边突出0.025mm。并且,第一引线14彼此分离的距离为0.25mm,第一接合部21的下侧边与相邻的接合部的上侧边之间的距离为0.1mm。该情况与图4所示的相同。
因此,返回图1进行说明,图3和图4的引线架正好为以下的结构。即,在两根第一引线14之间配置第二引线15。因此,第一接合部21和第二接合部22局部重叠而配置。
以上,与第一实施方式不同之处仅为接合部重叠这一方面,其他与第一实施方式相同,因此省略其说明。
(第三实施方式)
以下,参照图5、图6及图7说明本实施方式。图5是表示本实施方式的半导体装置的平面图,图6是取出第一引线架而表示的平面图,图7是取出第二引线架而表示的平面图。
在上述实施方式中,内置的元件为分立型的晶体管,在本实施方式中,在半导体装置中内设有形成多个电极的IC。因此,在本实施方式中,所使用的引线架为IC规格的引线架。即,图6及图7所示的引线架中,由于载置有上表面设有多个接合焊盘的半导体芯片,故引线架中也包含与接合焊盘的个数对应的多个引线。
参照图5,具有多个引线的引线架重合。与上述实施方式相同,在第一岛区域12的表面安装有第一半导体芯片17,经由金属细线与各自的第一引线14连接。另外,在第二岛区域13的背面安装有第二半导体芯片20,经由金属细线与第二引线15电连接。并且,在第一引线14、14之间配置第二引线15而构成。另外,附图标记55、57所示的部位是与上述的各岛区域连接并导出外部的吊线,具有在制造工序的中途阶段机械地支承各岛区域的功能。
另外,在此,附图中省略了设有的绝缘性树脂40。
如图5可知,第一岛区域12的表面与第二岛区域13的背面至少局部重叠,因此可减小平面上岛区域的占有面积。
另外,由于引线也将与金属细线的连接点表背面交替地设置,故与上述实施方式相同,能够将引线彼此重叠一部分。
在附图中虽然省略了图示,但各引线使倾斜部、接合部向斜下方延伸,故在其空间中设有第二半导体芯片20以及与其连接的金属细线,故而能够相应地抑制厚度。
在此,图5中从两岛区域一体导出的两根吊线从一个侧边(纸面上的左侧侧边)向外部导出。在此,也可以将从一个岛区域导出外部的吊线设置在左侧,将从另一个岛区域导出外部的吊线设置在右侧。
(第四实施方式)
参照图8说明本实施方式的半导体装置50的结构。图8(A)是半导体装置50的剖面图,图8(B)是从上方看到的图8(A)所示的半导体装置50的平面图,图8(C)是图8(B)的C-C′线剖面图。在本实施方式中,与上述的其他实施方式重复的部分标注相同的附图标记并省略其说明。
半导体装置50的结构与图1所示的半导体装置基本相同,不同点在于:第一岛区域12和第二岛区域13配置在平面上不同的位置(参照图8(B))。换句话说,第一岛区域12和第二岛区域13在平面上不重叠配置。而且,参照图8(C),第一岛区域12和第二岛区域13在厚度方向上错开而使二者至少局部重叠配置。在此,岛区域位于平面上的不同位置是指:在图8(B)所示的配置中,岛区域彼此在平面上不重合。另外,在厚度方向上重叠,参照图8(C),是指岛区域彼此在纸面的纵向上重叠。
另外,说明第一岛区域12和第二岛区域13在厚度方向上的位置关系,二者不配置在同一平面上。因此,参照图8(C),第一岛区域12的上表面及第二岛区域13的下表面在厚度方向上突出。
参照图8(A)说明半导体装置50的结构。半导体装置50将多个半导体芯片树脂密封而构成。在外观上,半导体装置50具有大致立方体形状或大致长方体形状,上表面和下表面是相互平行的平坦面,侧面成为上部比下部更向内侧倾斜的倾斜面。并且,由与内置的半导体芯片电连接的引线的端部构成的连接部31,从将整体一体地密封的绝缘性树脂40的侧面下部导出外部。另外,连接部31的下表面与绝缘性树脂40的下表面位于同一平面上。半导体装置50的安装可通过将连接部31上附着的焊锡膏加热融化的回流工序而进行。
半导体装置50的具体结构为:首先将多个半导体元件(第一半导体芯片17以及第二半导体芯片20)重叠而内置。参照图8(A)及图8(B),第一半导体芯片17固定在第一岛区域12的上表面上,第二半导体芯片20固定在第二岛区域13的下表面上。因此,第一半导体芯片17和第二半导体芯片20在半导体装置50的厚度方向上,其载置方向相反。
参照图8(A),固定在第一岛区域12上表面的第一半导体芯片17经由金属细线58与第一引线14的接合部14A的上表面连接。另外,固定在第二岛区域13下表面的第二半导体芯片20经由金属细线56与第二引线15的接合部的下表面连接。在此,关于第一引线14和第二引线15,可以将二者局部重叠而配置。由此,能够缩小半导体装置50的平面面积。
参照图8(B),配置在第一岛区域12上表面的第一半导体芯片不仅跨越第一岛区域12的上方,而且跨越至相邻的第二岛区域13的上方而重叠配置。由此,能够不限制第一岛区域12的大小而配置大型的第一半导体芯片17。在此,第一半导体芯片17的形状呈横向(岛区域排列的方向)上具有长边的长方形。另外,第二半导体芯片20也同样,固定在第二岛区域13下表面的第二半导体芯片20与第二岛区域13及第一岛区域12重叠而配置。在此,无需使两半导体芯片都跨越两个岛区域而配置,仅使某一个半导体芯片跨越两个岛区域配置即可。
另外,参照图8(A),第一引线14由上表面与金属细线58连接的接合部14A、与该接合部14A连接并朝向外侧向下方倾斜的连接部52、从绝缘性树脂40向外部露出且下表面位于绝缘性树脂40下表面的同一平面上的连接部31构成。该结构对于第二引线15也同样,但在第二引线15中,接合部的下表面与金属细线连接。
参照图8(B),设有从第一岛区域12向外部导出的两根引线54,并且设有也从第二岛区域13向外部导出的两根引线54。在纸面上,从绝缘性树脂40的上侧侧边导出的引线54、从下侧侧边导出外部的第一引线14及第二引线15上下对称地配置。由此,能够提高回流工序中半导体装置50的安装性。
参照图8(C),第一岛区域12和第二岛区域13在厚度方向上错开而配置,并且相对于厚度方向局部重叠。在此,第一岛区域12在绝缘性树脂40的内部稍稍靠上方配置。第二岛区域13比第一岛区域12更靠下方配置。在此,二者可以部分重叠,也可以完全不重叠。
在此,作为一例,第一岛区域12及第二岛区域13的厚度例如为0.5mm左右。二者重叠的厚度L1比该厚度小、例如为0.2mm左右。第一岛区域12的下表面与第二半导体芯片20的上表面分离开的距离L2为0.3mm左右。另外,第一半导体芯片17的下表面与第二岛区域13的上表面分离开的距离L3为0.3mm左右。
通过使第一岛区域12和第二岛区域13在厚度方向上部分重叠,而能够在将半导体装置50的厚度减薄的同时,确保岛区域与半导体芯片的绝缘。例如,与在一个岛区域的上下主表面上安装有两个半导体芯片的情况相比,半导体装置50减薄岛区域彼此在厚度方向上重叠的长度量(L1)。
另外,在第一岛区域12的上表面配置有第一半导体芯片17,背面及侧面通过将整体密封的绝缘性树脂40覆盖。另外,在第二岛区域13的下表面固定第二半导体芯片20,上表面以及侧面由绝缘性树脂40覆盖。另外,通过将第一岛区域12及第二岛区域13错开配置,第一岛区域12与第二岛区域20分离开,第二岛区域13与第一半导体芯片17分离开。因此,即使在小型的半导体装置50中层积内置比较大型的半导体芯片,也能够防止半导体芯片与岛区域的短路。
在本实施方式中,在第一岛区域12的下表面与第二岛区域20的上表面的间隙、第二岛区域13的上表面与第一半导体芯片17的下表面的间隙中填充有绝缘性树脂40。在此,若难以将含有填充剂的绝缘性树脂40填充到该间隙中,则在树脂密封工序之前,在该间隙中填充流动性优良的树脂材料(例如填充剂混入量较少的树脂)即可。另外,也可以在上述间隙中填充由环氧树脂等构成的粘接剂。
参照图8(A),第一半导体芯片17例如是MOSFET,在上表面设有栅极以及源极,背面构成漏极。并且,上表面的电极(栅极和源极各自)经由金属细线58分别与第一引线14连接,背面固定在第一岛区域12的上表面。另一方面,第二半导体芯片20例如是MOSFET,在纸面上,上表面的漏极固定在第二岛区域13的下表面。另外,第二半导体芯片20下表面的电极经由金属细线56与第二引线15接合部的下表面连接。这些半导体芯片若为背面流通过电流的结构,则通过导电性粘接材料或共晶接合而固定在各自要安装的岛区域的主表面上。另外,若这些半导体芯片的背面无需导通,则也可以使用绝缘性的粘接剂将半导体芯片安装在岛区域上。
参照图8(B),在本实施方式中,将半导体芯片的接合焊盘(电极)与载置半导体芯片的岛区域重叠设置。具体地,第一半导体芯片17的电极60(连接金属细线58的位置)在平面上位于第一岛区域12的内部。由此,在形成金属细线58时,即使由接合工具对电极60施加接合能量(按压力、振动力、加热),该部分的第一半导体芯片17也被第一岛区域12牢固地支承。因此,通过由接合工具施加的接合能量,能够抑制第一半导体芯片17被破坏的问题。该情况在第二半导体芯片20也同样,设于第二半导体芯片20上的电极62与第二岛区域13重叠而设置。
作为在半导体装置的内部层积多个半导体芯片的方法,有在一块岛区域的上表面及下表面两面上背靠背地层积两个半导体芯片的方法。但是,若为该方法,则层积的半导体芯片在需要将背面导通的情况下,二者会经由岛区域而短路。在本实施方式中,参照图8(C),设置相互分离开的两个岛区域,二者在厚度方向上错开而配置。由此,流过电流的一个岛区域的背面可与安装在另一个岛区域上的半导体芯片绝缘。
通常,在半导体装置中内设两个半导体芯片时,将各自的半导体芯片载置在独立的岛区域上而将其层积。因此,两个岛区域以及半导体芯片在厚度方向上层积,故不能够避免层积所导致的厚度增加。在本实施方式中,参照图8(C),将固定各个半导体芯片的第一岛区域12及第二岛区域13在厚度方向上重叠。由此,能够抑制半导体芯片层积所导致的厚度增加,将封装的厚度减薄。
Claims (3)
1.一种半导体装置,其内设有层积配置的第一半导体芯片及第二半导体芯片,其特征在于,
所述第一半导体芯片固定在第一岛区域的上表面,
所述第二半导体芯片固定在第二岛区域的下表面,
所述第一岛区域和所述第二岛区域位于所述第一半导体芯片与所述第二半导体芯片之间且二者分开配置。
2.如权利要求1所述的半导体装置,其特征在于,所述第一岛区域和所述第二岛区域俯视看重叠配置,并且所述第一岛区域的厚度与所述第二岛区域的厚度相加之后的长度,比所述第一半导体芯片的下表面与所述第二半导体芯片的上表面分开的距离短。
3.如权利要求1所述的半导体装置,其特征在于,所述第一岛区域及所述第二岛区域俯视看配置在不同的位置,并且所述第一半导体芯片的下表面与所述第二半导体芯片的上表面分开的距离,比所述第一岛区域的厚度与所述第二岛区域的厚度相加之后的长度短。
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JP050583/07 | 2007-02-28 | ||
JP2007050583A JP2007294884A (ja) | 2006-03-29 | 2007-02-28 | 半導体装置 |
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CN101257008A CN101257008A (zh) | 2008-09-03 |
CN101257008B true CN101257008B (zh) | 2010-06-16 |
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CN2007101618105A Expired - Fee Related CN101257008B (zh) | 2007-02-28 | 2007-09-24 | 半导体装置 |
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US6380624B1 (en) * | 2000-10-10 | 2002-04-30 | Walsin Advanced Electronics Ltd. | Stacked integrated circuit structure |
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US5148243A (en) * | 1985-06-25 | 1992-09-15 | Hewlett-Packard Company | Optical isolator with encapsulation |
US6261865B1 (en) * | 1998-10-06 | 2001-07-17 | Micron Technology, Inc. | Multi chip semiconductor package and method of construction |
KR100636776B1 (ko) | 1998-10-14 | 2006-10-20 | 가부시키가이샤 히타치세이사쿠쇼 | 반도체 장치 및 그 제조 방법 |
KR100361079B1 (ko) | 2001-01-18 | 2002-11-23 | 주식회사 바른전자 | 초박형 적층 반도체 칩 패키지 및 이에 사용되는 리드프레임 |
US6744121B2 (en) | 2001-04-19 | 2004-06-01 | Walton Advanced Electronics Ltd | Multi-chip package |
JP4282392B2 (ja) * | 2003-07-11 | 2009-06-17 | 株式会社東芝 | 光半導体装置及びその製造方法 |
JP2007005569A (ja) | 2005-06-24 | 2007-01-11 | Matsushita Electric Ind Co Ltd | リードフレームおよび半導体装置および切断装置および切断方法 |
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- 2007-09-24 CN CN2007101618105A patent/CN101257008B/zh not_active Expired - Fee Related
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US6380624B1 (en) * | 2000-10-10 | 2002-04-30 | Walsin Advanced Electronics Ltd. | Stacked integrated circuit structure |
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KR20080079979A (ko) | 2008-09-02 |
US7554183B2 (en) | 2009-06-30 |
US20080203582A1 (en) | 2008-08-28 |
CN101257008A (zh) | 2008-09-03 |
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