WO2023098298A9 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2023098298A9
WO2023098298A9 PCT/CN2022/124631 CN2022124631W WO2023098298A9 WO 2023098298 A9 WO2023098298 A9 WO 2023098298A9 CN 2022124631 W CN2022124631 W CN 2022124631W WO 2023098298 A9 WO2023098298 A9 WO 2023098298A9
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WIPO (PCT)
Prior art keywords
partition
display substrate
partition part
layer
sub
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PCT/CN2022/124631
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English (en)
French (fr)
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WO2023098298A1 (zh
Inventor
尚庭华
张毅
刘庭良
杨慧娟
马宏伟
周洋
齐琦
秦成杰
张微
文平
王本莲
龙跃
黄炜赟
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Publication of WO2023098298A1 publication Critical patent/WO2023098298A1/zh
Publication of WO2023098298A9 publication Critical patent/WO2023098298A9/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks

Definitions

  • Embodiments of the present disclosure relate to a display substrate and a display device.
  • OLED organic light-emitting diode
  • organic light-emitting diode display devices have been widely used in various electronic products, ranging from smart bracelets, smart watches, smartphones, tablets and other electronic products to large laptops, desktop computers, televisions and other electronic products. Therefore, the market demand for active matrix organic light-emitting diode display devices is also increasingly strong.
  • Embodiments of the present disclosure provide a display substrate and a display device.
  • An embodiment of the present disclosure provides a display substrate, including: a substrate substrate including a hole area, a display area, and a frame area located between the hole area and the display area; a plurality of sub-pixels located in the display area,
  • the sub-pixel includes a light-emitting element, the light-emitting element has a light-emitting area, the light-emitting element includes a first electrode, a light-emitting functional layer, and a second electrode, the second electrode is located away from the liner of the light-emitting functional layer.
  • the first electrode is located on the side of the light-emitting functional layer close to the base substrate.
  • the light-emitting functional layer includes a plurality of sub-functional layers; a first partition structure is located in the display area, and includes a stacked first partition part and a second partition part, the first partition part is located on a side of the second partition part close to the base substrate; and a second partition structure is located in the frame area , and includes a stacked third partition part and a fourth partition part, the third partition part is located on the side of the fourth partition part close to the base substrate; the second partition part has a first protrusion part, the first protrusion part protrudes relative to the first partition part, at least one sub-functional layer of the light-emitting functional layer is disconnected at the first protrusion part, and the fourth partition part has a second protrusion part, the second protruding part protrudes relative to the third partition part, and at least one sub-functional layer of the light-emitting functional layer is disconnected at the second protruding part; the first partition structure surrounds the light-emitting function layer. area; the second partition structure is
  • the second electrode is continuous at the first protrusion, and the first partition structure is arranged in an annular shape.
  • the first partition structure is annular and is continuously arranged.
  • the first partition structure has a gap
  • the first electrode has a main body part and a connecting part
  • the orthographic projection of the main body part on the base substrate is consistent with the light emitting
  • the orthographic projections of the areas on the base substrate overlap
  • the connecting portion is located at the notch.
  • the display substrate further includes an encapsulation layer.
  • the encapsulation layer includes a first encapsulation layer, a second encapsulation layer and a third encapsulation layer.
  • the first encapsulation layer, the second encapsulation layer The first packaging layer and the third packaging layer are arranged in sequence, the first packaging layer is closer to the base substrate than the third packaging layer, and the first packaging layer and the third packaging layer have stacked contact portions ,
  • the second partition structure is provided as a plurality, and the orthographic projection of one of the plurality of second partition structures on the base substrate overlaps with the orthographic projection of the second encapsulation layer on the base substrate. , an orthographic projection of another one of the plurality of second partition structures on the base substrate overlaps an orthographic projection of the stacked contact portion on the base substrate.
  • the display substrate further includes a barrier dam located in the frame area, and the second partition structure includes two second partition structures located on both sides of the barrier dam. .
  • the thickness of the second partition part is greater than the thickness of the first partition part.
  • the ratio of the thickness of the first partition part to the second partition part is greater than or equal to 0.25 and less than or equal to 1.
  • a size of the first partition part in a direction perpendicular to the base substrate is smaller than a size of the third partition part in a direction perpendicular to the base substrate.
  • the second partition part and the fourth partition part are located on the same layer.
  • the first partition structure and the second partition structure have the same layer structure.
  • the number of film layers included in the first partition portion is less than or equal to the number of film layers included in the third partition portion.
  • the material of the first partition structure includes a conductive material
  • the material of the second partition structure includes a conductive material
  • the conductive material includes metal and conductive metal oxide.
  • the second partition part and the fourth partition part are located on the same layer, and the third partition part includes a part located on the same layer as the first partition part.
  • the material of the first partition structure includes an inorganic insulating material
  • the material of the second partition structure includes an inorganic insulating material
  • the first partition part and the second partition part are made of different materials
  • the third partition part and the fourth partition part are made of different materials
  • the first partition part is made of different materials.
  • the material of the second partition part and the third partition part is the same
  • the material of the second partition part and the fourth partition part is the same.
  • the material of the first partition part and the third partition part includes an organic material
  • the material of the second partition part and the fourth partition part includes an inorganic insulating material
  • the material of the first partition part and the third partition part includes an organic insulating material
  • the material of the second partition part and the fourth partition part includes a conductive material
  • the material of the first partition part includes an organic insulating material
  • the material of the second partition part includes an organic insulating material
  • the material of the third partition part includes an inorganic insulating material
  • the material of the fourth partition part includes conductive material.
  • the first partition part and the second partition part are an integral structure.
  • the second partition structure includes two sub-partition structures, and the second protrusions of the two sub-partition structures are arranged oppositely.
  • the second partition structure is provided in plurality, the second partition structure further includes a fifth partition part, the material of the fifth partition part includes a conductive material, and a plurality of third partition structures are provided.
  • the fifth partition part of the two partition structures is an integrated structure, and a plurality of fourth partition parts are arranged sequentially around the hole area.
  • the display substrate further includes a conductive structure, and the orthographic projection of the conductive structure on the substrate substrate intersects with the orthographic projection of the first partition structure on the substrate substrate.
  • the conductive structure includes a data line or a power line.
  • the first partition structure is T-shaped.
  • the partition structure includes at least one partition substructure, and the orthographic projection of the at least one partition substructure on the substrate at least surrounds the light-emitting area and is on the substrate. One-half of the orthographic projection on the substrate.
  • An embodiment of the present disclosure also provides a display device, including any of the above display substrates.
  • Figure 1 is a schematic diagram of a light emitting element.
  • Figure 2 is a schematic diagram of a display substrate.
  • Figure 3 is a schematic diagram of a display substrate.
  • FIG. 4 is a schematic cross-sectional view of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 5A is an enlarged view of the first partition structure in FIG. 4 .
  • FIG. 5B is an enlarged view of the second partition structure in FIG. 4 .
  • FIGS. 6A to 6D are flow charts of the manufacturing method of the display substrate shown in FIG. 4 .
  • FIG. 7 is a schematic cross-sectional view of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 8A is an enlarged view of the first partition structure in FIG. 7 .
  • FIG. 8B is an enlarged view of the second partition structure in FIG. 7 .
  • 9A to 9C are flow charts of the manufacturing method of the display substrate shown in FIG. 7 .
  • FIG. 10 is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 11A is a schematic cross-sectional view of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 11B is a schematic cross-sectional view of another display substrate according to an embodiment of the present disclosure.
  • FIG. 11C is a schematic cross-sectional view of another display substrate according to an embodiment of the present disclosure.
  • FIG. 12A is a flow chart of manufacturing a display substrate according to an embodiment of the present disclosure.
  • FIG. 12B is a flow chart of manufacturing a display substrate according to an embodiment of the present disclosure.
  • FIG. 13 is a schematic plan view of a plurality of second partition structures in a display substrate according to an embodiment of the present disclosure.
  • FIG. 14 is a schematic plan view of the first partition structure and the first electrode in the display substrate shown in FIG. 10 .
  • FIG. 15 is a schematic plan view of the first partition structure and the conductive structure in the display substrate shown in FIG. 11A or 11B.
  • FIG. 16 is a schematic plan view of the first partition structure in the display substrate shown in FIG. 10 .
  • FIG. 17 is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 18A is a schematic cross-sectional view of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 18B is a schematic cross-sectional view of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 18C is a schematic cross-sectional view of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 19A is a flow chart of manufacturing a display substrate according to an embodiment of the present disclosure.
  • FIG. 19B is a flow chart of manufacturing a display substrate according to an embodiment of the present disclosure.
  • FIG. 20 is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 21 is a flow chart of manufacturing the display substrate shown in FIG. 20 .
  • FIG. 22 is a plan view of the second partition structure in the frame area of the display substrate shown in FIG. 20 .
  • FIG. 23 is a plan view of the first partition structure in the display area of the display substrate provided by an embodiment of the present disclosure.
  • FIG. 24 is a plan view of the first partition structure in the display area of the display substrate provided by an embodiment of the present disclosure.
  • FIG. 25A is a schematic plan view of another display substrate according to an embodiment of the present disclosure.
  • FIG. 25B is a schematic plan view of another display substrate according to an embodiment of the present disclosure.
  • FIG. 26 is a schematic diagram of a light-emitting element in a display substrate according to an embodiment of the present disclosure.
  • Figure 27 is a schematic diagram of a pixel circuit and a light-emitting element in a display substrate.
  • FIG. 28 is a schematic diagram of a display device provided by an embodiment of the present disclosure.
  • one light-emitting layer in the light-emitting element in the OLED display substrate can be replaced with two light-emitting layers, and a charge generation layer (CGL) is added between the two light-emitting layers, using N /P-CGL as a heterojunction, connects two light-emitting device structures in series to form a double-stack design, forming a Tandem structure.
  • the display substrate of the Tandem structure realizes dual light-emitting devices in series, which greatly reduces the luminescence under the same luminous intensity.
  • the light-emitting current of the component increases the life of the light-emitting component, which is conducive to the development and mass production of new high-life technologies such as automotive applications.
  • the tandem structure display device has the advantages of long life, low power consumption, and high brightness.
  • FIG. 1 is a schematic diagram of a light emitting element.
  • FIG. 1(a) is a schematic diagram of a general light-emitting element.
  • Figure 1(b) is a schematic diagram of a light-emitting element with a Tandem structure. As shown in Figure 1(b), the charge generation layers (CGL) between different light-emitting elements in the Tandem structure are connected.
  • CGL charge generation layers
  • Figure 1 shows a first electrode E1, a second electrode E2, a hole transport layer HTL, an electron transport layer ETL, an optical coupling layer CPL, an anti-reflection layer ARL, a P-type doped charge generation layer P-CGL, and an N-type Doped charge generation layer N-CGL, luminescent layer R, luminescent layer G, luminescent layer B.
  • the luminescent layer R includes two sub-layers containing luminescent material r1 and luminescent material r2 respectively
  • the luminescent layer G includes two sub-layers containing luminescent material g1 and luminescent material g2 respectively
  • the luminescent layer B includes luminescent material b1 and luminescent material b2.
  • the luminescent material r1 and the luminescent material r2 are two different materials that emit red light
  • the luminescent material g1 and the luminescent material g2 are two different materials that emit green light
  • the luminescent material b1 and the luminescent material b2 are two different materials that emit blue light. s material.
  • FIG. 2 is a schematic diagram of a display substrate.
  • the display substrate includes planarization layer PLN1, planarization layer PLN2, pixel defining layer PDL, electrode E1, light-emitting functional layer FL, electrode E2, and encapsulation layer EPS.
  • Figure 1 shows the light-emitting element EM01 and the light-emitting element EM02.
  • the charge generation layer (CGL) of the light-emitting element EM01 and the light-emitting element EM02 can be an integrated structure and manufactured using an opening mask.
  • crosstalk between adjacent sub-pixels refers to a situation where a light-emitting element that should not emit light emits light.
  • the desired situation is that the light-emitting element EM01 emits light, but the light-emitting element EM02 does not emit light, but due to the conductivity of the charge generation layer, the light-emitting element EM02 also emits light, thereby forming crosstalk.
  • Figure 3 is a schematic diagram of a display substrate.
  • the display substrate includes a hole area R2, a display area R1, and a frame area R3 located between the hole area R2 and the display area R1.
  • the hole area R2 is circular.
  • the embodiment of the present disclosure takes the shape of the hole region R2 as a circle as an example for description, but the hole region R2 can also adopt other suitable shapes and is not limited to a circle.
  • the location of the hole area R2 is not limited to that shown in the figure, and can be set as needed. For example, some gate lines, some data lines and other conductive lines are wrapped around the hole area R2 to form the frame area R3.
  • the solution of opening holes in the screen when using the solution of opening holes in the screen, at least part of the structure in the hole area R2 is removed. That is, the solution of opening holes in the screen requires sacrificing part of the display area to form the hole area. For example, all structures in the hole region R2 of the display substrate are removed. For example, after forming the encapsulation layer, drilling is performed to remove the portion of the display substrate located in the hole region R2.
  • the sensor may be partially disposed in the hole area R2, or may be entirely disposed in the hole area R2.
  • sensors include cameras.
  • a partition structure can be provided in the frame area R3 to isolate the light-emitting functional layer of the light-emitting element and prevent water and oxygen from entering the display area R1 along the light-emitting functional layer around the hole area R2.
  • a partition structure can be provided in the display area.
  • the display substrate provided by the embodiment of the present disclosure has a first partition structure in the display area R2 to improve the reliability of the display substrate, and a second partition structure in the frame area R3 to reduce or avoid crosstalk.
  • FIG. 4 is a schematic cross-sectional view of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 5A is an enlarged view of the first partition structure in FIG. 4 .
  • FIG. 5B is an enlarged view of the second partition structure in FIG. 4 .
  • FIGS. 6A to 6D are flow charts of the manufacturing method of the display substrate shown in FIG. 4 .
  • the display substrate DP1 includes: a base substrate BS, a plurality of sub-pixels SP, a first partition structure 11 and a second partition structure 12 .
  • the base substrate BS includes a hole area R2, a display area R1, and a frame area R3 located between the hole area R2 and the display area R1.
  • a plurality of sub-pixels SP are located on the main surface SF0 of the base substrate BS.
  • the sub-pixels SP include a light-emitting element EMC, and the light-emitting element EMC has a light-emitting area R0.
  • the light-emitting element EMC includes a first electrode E1, a light-emitting functional layer FL, and a second electrode E2.
  • the second electrode E2 is located on the side of the light-emitting functional layer FL away from the base substrate BS.
  • the first electrode E1 is located on The side of the light-emitting functional layer FL close to the base substrate BS includes a plurality of sub-functional layers.
  • the first electrode E1 is made of conductive material.
  • the material of the first electrode E1 includes metal and conductive metal oxide.
  • the first electrode E1 adopts a structure in which indium tin oxide (ITO), silver (Ag), and indium tin oxide (ITO) are stacked. The material and structure of the first electrode E1 can be set as needed.
  • the second electrode E2 is made of conductive material.
  • the material of the second electrode E2 includes metal or alloy.
  • the material of the second electrode E2 includes Mg/Ag alloy. The material and structure of the second electrode E2 can be set as needed.
  • the second electrodes E2 of different sub-pixels are electrically connected to facilitate providing the same voltage signal.
  • the first partition structure 11 is located in the display area R1.
  • the first partition structure 11 is located between the light-emitting areas R0 of adjacent sub-pixels SP, and includes a stacked first partition part 11a and a second partition part 11a.
  • the first partition part 11a is located on the side of the second partition part 11b close to the base substrate BS; the second partition part 11b has a protrusion part PR1, and the protrusion part PR1 protrudes relative to the first partition part 11a.
  • the protrusion part PR1 protrudes with respect to at least a part of the 1st partition part 11a.
  • the protruding portion PR1 protrudes relative to the side of the first partition portion 11a close to the second partition portion 11b, and at least one sub-functional layer of the light-emitting functional layer FL is disconnected at the protruding portion PR1.
  • the direction from the first electrode E1 to the second electrode E2 is the direction Z.
  • the first partition structure 11 has a protruding portion PR1 which facilitates partitioning at least one sub-functional layer of the light-emitting functional layer FL.
  • disconnection of an element at protrusion PR1 includes disconnection at the side of protrusion PR1.
  • the second partition structure 12 is located in the frame area R3 and includes a stacked third partition part 13 and a fourth partition part 14 .
  • the third partition part 13 is located close to the lining of the fourth partition part 14 .
  • the fourth partition part 14 has a protruding part PR2, which protrudes relative to the third partition part 13, and at least one sub-functional layer of the light-emitting functional layer FL is disconnected at the protruding part PR2.
  • the protrusion portion PR2 protrudes with respect to the side of the third partition portion 13 close to the fourth partition portion 14 .
  • the display substrate includes a buffer layer BF, an insulating layer GI1, an insulating layer GI2, an insulating layer ILD, a planarization layer PLN, a pixel defining pattern PDL, and a spacer PS.
  • the spacer PS is configured to support the fine metal mask when fabricating the light emitting layer.
  • the pixel defining pattern PDL includes a plurality of openings OPN configured to define the light emitting area R0 of the sub-pixel SP and configured to expose at least a portion of the first electrode E1 .
  • FIG. 4 also shows the thin film transistor T0.
  • the thin film transistor T0 includes a gate electrode GE, an active layer CV, a source electrode Ea, and a drain electrode Eb.
  • the first electrode E1 is connected to the drain electrode Eb.
  • the source electrode Ea and the drain electrode Eb of the thin film transistor may be identical in structure and interchangeable in name.
  • FIG 4 also shows the first plate Ca and the second plate Cb of the capacitor C0.
  • the capacitor C0 may be the storage capacitor Cst mentioned later, but is not limited thereto.
  • Figure 4 also shows the encapsulation layer EPS.
  • the encapsulation layer EPS includes a first encapsulation layer EPS1, a second encapsulation layer EPS2, and a third encapsulation layer EPS3.
  • the first encapsulation layer EPS1 and the third encapsulation layer EPS3 are inorganic layers and can be formed using a chemical vapor deposition (CVD) process.
  • the second encapsulation layer EPS2 is an organic layer and can be formed using an inkjet printing process.
  • the thickness of the second encapsulation layer EPS2 is greater than the thickness of the first encapsulation layer EPS1.
  • the thickness of the second encapsulation layer EPS2 is greater than the thickness of the third encapsulation layer EPS3.
  • the first encapsulation layer EPS1 and the third encapsulation layer EPS3 are in contact, forming a stacked contact portion CP.
  • the thickness of the second partition part 11b is greater than the thickness of the first partition part 11a, it is more conducive to the encapsulation of the encapsulation layer EPS.
  • the thickness difference between the two partition parts of the partition structure is small, it is more conducive to the encapsulation of the encapsulation layer EPS and the encapsulation effect is improved.
  • the thickness ratio of the first partition part 11a and the second partition part 11b is greater than or equal to 0.25 and less than or equal to 1, it is more conducive to encapsulation of the encapsulation layer EPS.
  • FIGS 4 and 5B also show barrier dam 17.
  • the barrier dam 17 includes a sub-dam 171 and a sub-dam 172 .
  • the sub-dam 171 and the planarization layer PLN are located on the same layer and are formed from the same film layer using the same patterning process.
  • the sub-dam 172 and the pixel defining pattern PDL are located on the same layer and are formed from the same film layer using the same patterning process.
  • the display substrate includes two second partition structures 12 : a partition structure 121 and a partition structure 122 .
  • the partition structures 121 and 122 are respectively arranged on both sides of the barrier dam 17 .
  • the size of the barrier dam 17 in the direction perpendicular to the base substrate BS (direction Z) is larger than the size of the second partition structure 12 in the direction perpendicular to the base substrate BS.
  • Figures 4 and 5B only show two second partition structures 12. It should be noted that three or more second partition structures 12 can also be provided.
  • the orthographic projection of the partition structure 121 on the base substrate BS overlaps with the orthographic projection of the second encapsulation layer EPS2 on the base substrate BS.
  • the orthographic projection of the partition structure 121 on the base substrate BS The projection and the orthographic projection of the stack contact CP on the base substrate BS overlap.
  • 4 and 5B illustrate by taking the orthographic projection of a second partition structure 12 on the base substrate BS and the orthographic projection of the second encapsulation layer EPS2 on the base substrate BS as an example to illustrate, but it is not limited thereto.
  • the orthographic projection of the plurality of second partition structures 12 on the base substrate BS overlaps with the orthographic projection of the second encapsulation layer EPS2 on the base substrate BS.
  • 4 and 5B illustrate by taking the overlap of the orthographic projection of a second partition structure 12 on the base substrate BS and the orthographic projection of the stacked contact portion CP on the base substrate BS as an example, but it is not limited thereto.
  • the orthographic projection of the plurality of second partition structures 12 on the base substrate BS overlaps with the orthographic projection of the stacked contact portion CP on the base substrate BS.
  • At least one second partition structure 12 is provided on the left side of the barrier dam 17.
  • 3-7 second partition structures 12 are provided on the left side of the barrier dam 17.
  • at least one second partition structure 12 is provided on the right side of the barrier dam 17 .
  • 3-7 second partition structures 12 are provided on the right side of the barrier dam 17 .
  • the orthographic projection of the partition structure 122 on the base substrate BS does not overlap with the orthographic projection of the second encapsulation layer EPS2 on the base substrate BS.
  • the first conductive pattern layer LY1 includes a gate electrode GE and a first plate Ca
  • the second conductive pattern layer LY2 includes a second plate Cb
  • the third conductive pattern layer LY3 includes a source electrode Ea and a drain electrode Eb.
  • the third conductive pattern layer LY3 may include a plurality of sub-layers arranged in a stack.
  • the third conductive pattern layer LY3 may include a stacked structure of three sub-layers of Ti/Al/Ti.
  • the first partition part 11a may be a metal layer, for example, a Mo layer.
  • the thickness of the first partition part 11a is Since the material of the first partition part 11a is a metal material, for example, metal Mo, and the thickness is small, it is beneficial for the first partition structure 11 to isolate the light-emitting functional layer FL and not isolate the second electrode E2, which is beneficial to maintaining the continuity of the second electrode E2. , which is beneficial to improving the uniformity of luminescence of the display substrate.
  • the thickness of the first partition part 11a is smaller than the thickness of the second partition part 11b.
  • the third partition part 13 includes a sub-layer 131 and a sub-layer 132 .
  • the sub-layer 131 may be located on the same layer as the source electrode Ea and the drain electrode Eb of the thin film transistor.
  • the sub-layer 132 may be located on the same layer as the first partition part 11a.
  • the material of the first partition part 11 a includes Mo
  • the material of the third partition part 13 includes Mo, Al, and Ti.
  • the third partition part 13 includes a part located on the same layer as the first partition part 11a. That is, the third partition part 13 includes the sub-layer 132 located on the same layer as the first partition part 11a.
  • the second partition part 11 b and the fourth partition part 14 are located on the same layer.
  • the second partition part 11b and the fourth partition part 14 may both be located on the same layer as the first electrode E1.
  • the thickness of the third partition part 13 of the second partition structure 12 is greater than the thickness of the first partition part 11a of the first partition structure 11, so that in the frame area R3 near the hole area R2, the light-emitting functional layer FL and The second electrodes E2 are all cut off, thereby cutting off the luminescent material between the display area and the hole, preventing water and oxygen around the hole from entering the display area R1 along the luminescent material, thereby increasing the service life of the luminescent element.
  • the display substrate further includes a pixel circuit PXC.
  • the pixel circuit PXC is configured to drive the light-emitting element EMC to emit light.
  • the first electrode E1 passes through a via hole penetrating the planarization layer PLN.
  • V0 is connected to the pixel circuit PXC.
  • the plurality of sub-pixels SP include sub-pixel SP1 and sub-pixel SP2.
  • Sub-pixel SP1 and sub-pixel SP2 are two adjacent sub-pixels.
  • the number of sub-pixels provided on the display substrate is not limited to that shown in the figure and can be determined as needed.
  • the number of sub-functional layers included in the light-emitting functional layer FL can be set as needed.
  • the first partition structure can be provided between adjacent sub-pixels, and at least one of the multiple sub-functional layers in the light-emitting functional layer can be disconnected at the position where the partition structure is located. Turn on, increasing the resistance of the sub-functional layer with higher conductivity in the light-emitting functional layer FL, thereby reducing or preventing the crosstalk between adjacent sub-pixels caused by the film layer with higher conductivity in multiple sub-functional layers, reducing or preventing Crosstalk occurs when light-emitting elements emit light.
  • the first partition structure 11 is formed after the first electrode E1 is formed, without changing the backplane structure of the display substrate. Moreover, the first partition structure 11 is disposed between the first electrodes E1 of the light-emitting elements, so that the first partition structure 11 has a larger installation space, which is convenient for installing the first partition structures 11 of different structures.
  • the material of the first partition structure 11 and the material of the second partition structure 12 shown in Figure 4 are both conductive materials.
  • the first partition structure 11 can isolate organic light-emitting materials and can be disposed between adjacent sub-pixels in the display area.
  • FIG. 6A to 6D illustrate a method of manufacturing the display substrate DP1.
  • the manufacturing method of display substrate DP1 includes the following steps.
  • the manufacturing method of the display substrate includes: forming a buffer layer BF on the base substrate, then forming an active layer CV on the buffer layer BF, and forming an insulating layer GI1 on the active layer CV.
  • the gate electrode GE and the first electrode plate Ca are formed on the insulating layer GI1
  • the insulating layer GI2 is formed on the gate electrode GE and the first electrode plate Ca
  • the second electrode plate Cb is formed on the insulating layer GI2
  • the second electrode plate Cb is formed on the insulating layer GI1.
  • An insulating layer ILD is formed on the insulating layer ILD
  • a source electrode Ea, a drain electrode Eb, and an intermediate sublayer 1310 are formed on the insulating layer ILD.
  • a planarization layer PLN is formed on the source electrode Ea and the drain electrode Eb, a sub-dam 171 is formed in the frame area, an intermediate layer 11aa is formed in the display area, and an intermediate sub-layer 1320 is formed in the frame area.
  • the first electrode E1 and the second partition part 11b are formed in the display area, and the fourth partition part 14 is formed in the frame area; the pixel defining pattern PDL and the spacer PS are formed in the display area, and in the frame area Sub-dam 172 is formed.
  • the middle layer 11aa, the middle sub-layer 1310 and the middle sub-layer 1320 are etched to form the first isolation part 11a and the third isolation part 13.
  • FIG. 7 is a schematic cross-sectional view of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 8A is an enlarged view of the first partition structure in FIG. 7 .
  • FIG. 8B is an enlarged view of the second partition structure in FIG. 7 .
  • 9A to 9C are flow charts of the manufacturing method of the display substrate shown in FIG. 7 .
  • the difference between the display substrate DP2 shown in FIG. 7 and the display substrate DP1 shown in FIG. 4 is that both the first partition structure 11 and the second partition structure 12 shown in FIG. 7 are inorganic insulation structures.
  • the first partition structure 11 includes a first partition part 11a and a second partition part 11b. Both the first partition part 11a and the second partition part 11b are made of inorganic insulating materials.
  • the second partition structure 12 includes a third partition part 13 and a fourth partition part 14 .
  • the third partition part 13 includes a sub-layer 131 and a sub-layer 132 .
  • Both the third partition part 13 (sub-layer 131 and the sub-layer 132) and the fourth partition part 14 are made of inorganic insulating materials.
  • the inorganic insulating material used in the first partition part 11a, the second partition part 11b, the third partition part 13 and the fourth partition part 14 includes at least one of SiOx, SiNy and SiOxNy.
  • the first partition structure 11 is T-shaped
  • the second partition structure 12 includes a T-shaped portion.
  • first partition structure 11 is not limited to a T-shape. In other embodiments, the first partition structure 11 may also be in an I-shape, or may adopt other suitable shapes.
  • the second partition structure 12 may be T-shaped or I-shaped. Of course, other suitable shapes may also be adopted.
  • FIG. 9A to 9C illustrate a method of manufacturing the display substrate DP2.
  • the manufacturing method of the display substrate includes the following steps.
  • a buffer layer BF is formed on the base substrate, an active layer CV is formed on the buffer layer BF, and an insulating layer GI1 is formed on the active layer CV.
  • the gate electrode GE and the first electrode plate Ca are formed on the insulating layer GI1
  • the insulating layer GI2 is formed on the gate electrode GE and the first electrode plate Ca
  • the second electrode plate Cb is formed on the insulating layer GI2
  • the second electrode plate Cb is formed on the insulating layer GI1.
  • An insulating layer ILD and an intermediate sub-layer 1310 are formed on the insulating layer ILD, and a source electrode Ea and a drain electrode Eb are formed on the insulating layer ILD.
  • a planarization layer PLN is formed on the source electrode Ea and the drain electrode Eb and a sub-dam 171 is formed in the frame area; an intermediate layer 11aa is formed in the display area and an intermediate sub-layer 1320 is formed in the frame area; and in the display area
  • the second partition part 11b is formed, and the fourth partition part 14 is formed in the frame area; the first electrode E1 is formed in the display area; the pixel defining pattern PDL is formed in the display area and the sub-dam 172 is formed in the frame area; and the spacer PS is formed.
  • the middle layer 11aa, the middle sub-layer 1310 and the middle sub-layer 1320 are etched to form the first isolation part 11a and the third isolation part 13.
  • the first partition part 11 a and the second partition part 11 b use different inorganic insulating materials to facilitate the formation of the first partition structure 11 with protruding parts.
  • the third partition part 13 and the fourth partition part 14 use different inorganic insulating materials to facilitate the formation of the second partition structure 12 with protruding parts.
  • the first partition part 11 a and the sub-layer 132 of the third partition part 13 are located on the same layer, and the second partition part 11 b and the fourth partition part 14 are located on the same layer.
  • the thickness of the first partition 11a using inorganic insulating material is The thickness of the sub-layer 132 of the third partition part 13 using inorganic insulating material is
  • the sub-layer 131 and the insulating layer ILD are located on the same layer.
  • the sub-layer 132 is set inwardly relative to the sub-layer 131 and the fourth isolation part 14 to facilitate isolation of the light-emitting functional layer FL and the second electrode E2.
  • the barrier dam 17 is provided on the insulating layer ILD.
  • the display substrate DP2 shown in Figure 7 can refer to that shown in Figure 4 Description of the display substrate DP1.
  • FIG. 10 is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 11A is a schematic cross-sectional view of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 11B is a schematic cross-sectional view of another display substrate according to an embodiment of the present disclosure.
  • FIG. 11C is a schematic cross-sectional view of another display substrate according to an embodiment of the present disclosure.
  • FIG. 12A is a flow chart of manufacturing a display substrate according to an embodiment of the present disclosure.
  • FIG. 12B is a flow chart of manufacturing a display substrate according to an embodiment of the present disclosure.
  • FIG. 13 is a schematic plan view of a plurality of second partition structures in a display substrate according to an embodiment of the present disclosure.
  • FIG. 14 is a schematic plan view of the first partition structure and the first electrode in the display substrate shown in FIG. 10 .
  • FIG. 15 is a schematic plan view of the first partition structure and the conductive structure in the display substrate shown in FIG. 11A or 11B.
  • FIG. 16 is a schematic plan view of the first partition structure in the display substrate shown in FIG. 10 .
  • the display substrate DP3 includes a first partition structure 11 and a second partition structure 12.
  • the first partition structure 11 is located in the display area R1 and between adjacent sub-pixels SP.
  • the second partition structure 12 is located in the frame area R3.
  • the first partition structure 11 includes a first partition part 11a and a second partition part 11b.
  • the first partition part 11a and the planarization layer PLN are located on the same layer and are made of organic materials.
  • the second partition part 11b is located on the same layer as the first electrode E1 and is made of conductive material.
  • the second partition structure 12 includes a third partition part 13 and a fourth partition part 14.
  • the third partition part 13 is located on the same layer as the planarization layer PLN and is made of organic materials.
  • the fourth partition part 14 is located on the same layer as the first electrode E1 and is made of conductive material.
  • the thickness of the first partition part 11 a is greater than the thickness of the second partition part 11 b
  • the thickness of the third partition part 13 is greater than the thickness of the fourth partition part 14 .
  • the light-emitting functional layer FL is interrupted at the first partition structure 11 to avoid or reduce crosstalk during light emission; the light-emitting functional layer FL is interrupted at the second partition structure 12 , preventing water and oxygen around the holes from entering the display area R1 along the luminescent material, thereby improving the service life of the luminescent element.
  • the second electrode E2 is continuous everywhere without being interrupted, so that the second electrode E2 has a smaller resistance, which is beneficial to improving the uniformity of light emission of the display substrate.
  • the patterning process can also be adjusted so that the second electrode E2 is blocked at the second partition structure 12 to further improve the packaging effect.
  • the second electrode E2 is disconnected at the second partition structure 12 and is not disconnected at the first partition structure 11 , that is, it is continuous at the first partition structure 11 .
  • the shape or size of the first partition part 11a can also be adjusted so that the second electrode E2 is disconnected at the first partition structure 11, and the shape or size of the third partition part 13 can be adjusted so that the second electrode E2 is disconnected at the first partition structure 11.
  • the second partition structure was disconnected at 12 places.
  • the first partition structure 11 may be provided with a gap, and the second electrodes E2 of adjacent sub-pixels may be connected to each other at the gap to facilitate application of the same signal.
  • a secondary mask can also be used to add auxiliary connection electrodes to connect the second electrodes E2 of different sub-pixels, or the light coupling layer CPL (as shown in Figure 1) can be made conductive. That is, the second electrodes E2 of different sub-pixels are connected through the conductive light coupling layer CPL.
  • the inorganic layer in the encapsulation layer is produced using chemical vapor deposition (CVD).
  • the display substrate DP32 or the display substrate DP33 further includes a conductive structure 50 , and the orthographic projection of the conductive structure 50 on the substrate substrate BS is the same as that of the third substrate DP31 .
  • the orthographic projection of a partition structure 11 on the substrate BS overlaps.
  • the protective layer 55 covers the conductive structure 50 to prevent the conductive structure 50 from being exposed and causing signal short circuit.
  • the protective layer 55 can be made of inorganic insulating material.
  • the material of the protective layer 55 may be the same as the material of the passivation layer.
  • the second partition part 11b has a protruding part PR1, and the protruding part PR1 protrudes relative to the first partition part 11a, so that the light-emitting functional layer FL is at the protruding part. Disconnected at PR1.
  • the protruding portion PR1 protrudes relative to the central constriction of the first partition portion 11a.
  • the area of the orthogonal projection of the first partition part 11 a on the base substrate BS gradually decreases and then gradually increases.
  • the fourth partition part 14 has a protruding part PR2 , and the protruding part PR2 protrudes relative to the third partition part 13 , so that the light-emitting functional layer FL is at the protruding part. Disconnected at PR2.
  • the protruding portion PR2 protrudes relative to the central constriction of the first partition portion 11a.
  • the area of the orthogonal projection of the third partition portion 13 on the base substrate BS gradually decreases and then gradually increases.
  • a connection part 61 is provided between the first partition part 11a and the planarization layer PLN in the display area, and the planarization layer PLN and the first partition part 11a are connected through the connection part 61.
  • the thickness of the connecting portion 61 is smaller than the thickness of the planarization layer PLN, and the thickness of the connecting portion 61 is smaller than the thickness of the first partition portion 11 a.
  • the thickness of the planarization layer PLN is equal to the thickness of the first partition part 11a.
  • the planarization layer PLN, the first partition part 11a, and the connection part 61 have an integrated structure. Therefore, the top of the conductive structure 50 can be covered with more planarization material to prevent signal short circuit.
  • the manufacturing method of the display substrate includes the following steps.
  • Step S11 Form a planarization film PLF on the insulating layer ILD; form the first electrode E1, the second isolation portion 11b, and the fourth isolation portion 14 on the planarization film PLF; and form the pixel defining pattern PDL.
  • Step S12 Form a photoresist pattern PT1.
  • Step S13 Pattern the planarization film PLF using the photoresist pattern PT1 as a mask.
  • Step S14 peel off the photoresist pattern PT1 to form the first partition structure 11 and the second partition structure 12.
  • step S13 patterning the planarization film PLF includes a dry etching process.
  • the area where the first partition structure 11 is located is covered with the pixel definition intermediate pattern PDL0.
  • the first partition structure The area where 11 is located is first etched with the pixel definition intermediate pattern PDL0, and then the planarization film PLF is etched, so that when the etching process is completed, the planarization layer PLN remains above the conductive structure 50, preventing the conductive structure 50 from being exposed to avoid short signal catch.
  • the display substrate includes four second partition structures 12 .
  • Figure 13 shows the second partition structure 121, the second partition structure 122, the second partition structure 123 and the second partition structure 124.
  • the number of second partition structures 12 included in the display substrate is not limited to that shown in the figure.
  • the conductive structure 50 includes the data line DT or the power line PL1.
  • the data line DT extends in the direction Y
  • the power line PL1 extends in the direction Y.
  • the data lines DT or the power lines PL1 are arranged in the direction X.
  • Figure 16 shows the first electrode E1 and the first partition structure 11.
  • the first partition structure 11 is in a mesh shape and includes a plurality of openings 110 , and the first electrode E1 is located in the openings 110 .
  • Each opening 110 may correspond to one sub-pixel.
  • the first partition structure 11 surrounds the light-emitting area R0. In the plan view, the first partition structure 11 is located outside the light-emitting area R0 and is spaced apart from the light-emitting area R0.
  • FIG. 17 is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 18A is a schematic cross-sectional view of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 18B is a schematic cross-sectional view of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 18C is a schematic cross-sectional view of another display substrate provided by an embodiment of the present disclosure.
  • Figure 19A is a flow chart of manufacturing a display substrate according to an embodiment of the present disclosure.
  • FIG. 19B is a flow chart of manufacturing a display substrate according to an embodiment of the present disclosure.
  • FIG. 17 shows the display substrate DP41
  • FIG. 18A shows the display substrate DP42
  • FIG. 18B shows the display substrate DP43
  • FIG. 18C shows the display substrate DP44.
  • the display substrate DP41 shown in FIG. 17 has the second partition part 11 b of the first partition structure 11 made of inorganic insulating material, and the fourth partition part 14 of the second partition structure 12 is made of inorganic material.
  • the insulating material, the second isolation part 11b and the fourth isolation part 14 are all located in the passivation layer PVX.
  • the display substrate DP42 shown in FIG. 18A has the second partition part 11 b of the first partition structure 11 made of inorganic insulating material, and the fourth partition part 14 of the second partition structure 12 is made of inorganic material.
  • the insulating material, the second isolation part 11b and the fourth isolation part 14 are all located in the passivation layer PVX.
  • the second partition part 11 b of the first partition structure 11 is made of inorganic insulating material
  • the fourth partition part 14 of the second partition structure 12 is made of inorganic material.
  • the insulating material, the second isolation part 11b and the fourth isolation part 14 are all located in the passivation layer PVX.
  • the second partition part 11 b of the first partition structure 11 is made of inorganic insulating material
  • the fourth partition part 14 of the second partition structure 12 is made of inorganic material.
  • the insulating material, the second isolation part 11b and the fourth isolation part 14 are all located in the passivation layer PVX.
  • a passivation layer PVX, a first electrode E1 , and a pixel defining pattern PDL are sequentially formed on the planarization film PLF.
  • the passivation layer PVX includes the second partition portion 11 b and the fourth partition portion 14 . The remaining steps may refer to the description of Figure 12A.
  • a passivation layer PVX, a first electrode E1 , and a pixel defining pattern PDL are sequentially formed on the planarization film PLF.
  • the passivation layer PVX includes the second partition portion 11 b and the fourth partition portion 14 . The remaining steps may refer to the description of Figure 12B.
  • plan view of the second partition structure 12 in the display substrate DP4 shown in FIGS. 17 and 18A to 18C can be referred to FIG. 13
  • plan view of the first partition structure 11 in the display substrate DP4 can also be referred to FIGS. 14 to 18C .
  • Figure 16 the plan view of the second partition structure 12 in the display substrate DP4 shown in FIGS. 17 and 18A to 18C .
  • the first partition structure 11 is made of insulating material
  • the second partition structure 12 is made of insulating material
  • the first partition part 11a and the third partition part 13 Organic insulating materials are used, and inorganic insulating materials are used for the second partition part 11b and the fourth partition part 14.
  • inorganic insulating materials include SiOx, SiNy, or SiOxNy.
  • the organic insulating material includes resin, but is not limited thereto.
  • the organic insulating material includes one or a combination of acrylic, polyethylene terephthalate, polyimide, polyamide, polycarbonate, epoxy resin, etc.
  • the second partition part 11b and the fourth partition part 14 may also be made of metal materials or conductive metal oxides.
  • FIG. 20 is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 21 is a flow chart of manufacturing the display substrate shown in FIG. 20 .
  • FIG. 22 is a plan view of the second partition structure in the frame area of the display substrate shown in FIG. 20 .
  • FIG. 23 is a plan view of the first partition structure in the display area of the display substrate provided by an embodiment of the present disclosure.
  • FIG. 24 is a plan view of the first partition structure in the display area of the display substrate provided by an embodiment of the present disclosure. 23 and 24 may be plan views of the first partition structure in the display substrate shown in FIG. 20 .
  • first partition structure 11 and the second partition structure 12 are different.
  • the first partition structure 11 and the second partition structure 12 are made of different materials and have different structures.
  • the first partition part 11a and the second partition part 11b are both made of organic insulating materials, and the first partition part 11a and the second partition part 11b are an integrated structure.
  • the first partition part 11a and the second partition part 11b are located on the same layer as the pixel defining pattern PDL.
  • the third partition part 13 is located on the same layer as the insulating layer ILD and is made of inorganic insulating material.
  • the fourth partition part 14 is located on the same layer as the first electrode E1 and is made of conductive material. Make.
  • the light-emitting functional layer FL is partitioned by the first partition structure 11 and includes a portion located on the first partition structure 11 and another portion spaced apart from the portion. Because the light-emitting functional layer FL is blocked by the first partition structure 11, crosstalk is avoided when the display substrate emits light.
  • the second electrode E2 is partitioned at the position where the first partition structure 11 is provided, forming a portion located on the first partition structure 11 and another portion spaced apart from the portion.
  • the light-emitting functional layer FL is partitioned by the second partition structure 12 , including a part located on the second partition structure 12 and another part separated from the part to avoid water and oxygen along the luminescent material around the hole area. Entering the display area will help improve the life of the light-emitting components.
  • the second electrode E2 is partitioned at the position where the second partition structure 12 is provided, forming a part located on the second partition structure 12 and another part separated from the part.
  • the manufacturing method of the display substrate DP5 includes the following steps.
  • Step 101 Form the conductive part 61, the insulating film ILL and the planarization layer PLN in sequence.
  • Step 102 Form a passivation layer PVX.
  • Step 103 Form the first electrode E1 and the fourth partition part 14.
  • Step 104 Form a pixel defining pattern PDL.
  • Step 105 Dry-etch the passivation layer PVX and the insulating film ILL using the pixel defining pattern PDL and the fourth isolation portion 14 as masks, respectively, to form an intermediate passivation layer PVX0 and an intermediate insulating layer ILL0.
  • Step 106 Wet etch the intermediate passivation layer PVX0 and the intermediate insulation layer ILL0 to form the first isolation structure 11 and the second isolation structure 12.
  • the conductive portion 61 may be located on the same layer as the gate electrode of the thin film transistor.
  • the second partition structure 12 includes two sub-partition structures 12S, and the protrusions PR2 of the two sub-partition structures 12S are arranged oppositely.
  • the display substrate shown in Figure 20 can effectively realize the compatibility of the first partition structure, the second partition structure and the Tandem process.
  • the first partition structure 11 and the second partition structure 12 in the display substrate DP5 shown in FIG. 20 include parts formed by simultaneous etching, and the process compatibility is good.
  • Figure 22 shows four second partition structures 12.
  • the second partition structure 12 is arranged in an annular shape around the hole area R2.
  • the orthographic projection of the second partition structure 12 on the base substrate overlaps with the orthographic projection of the conductive portion 61 on the base substrate.
  • the orthographic projection of the second partition structure 12 on the base substrate completely falls within the orthographic projection of the conductive portion 61 on the base substrate.
  • the first partition structure 11 is disposed outside the light-emitting area R0 of the light-emitting element.
  • the first partition structure 11 has a gap 1101 . Therefore, the first partition structure 11 is an annular structure with a gap 1101 .
  • the light-emitting functional layers of adjacent sub-pixels are continuous at the gap 1101
  • the second electrodes of the light-emitting elements are continuous at the gap 1101.
  • the first electrode E1 has a main body part E11 and a connection part E12.
  • the orthographic projection of the main body part E11 on the base substrate overlaps with the orthographic projection of the light-emitting area R0 on the base substrate.
  • the connection part E12 is configured To connect to other components.
  • the connection portion E12 is connected to the thin film transistor T0.
  • the orthographic projection of the connection portion E12 on the base substrate overlaps with the orthographic projection of the via hole V0 on the base substrate.
  • the connection portion E12 is located at the notch 1101.
  • the display substrate includes a first sub-pixel 201 , a second sub-pixel 202 , a third sub-pixel 203 and a fourth sub-pixel 204 .
  • one of the first sub-pixel 201 and the third sub-pixel 203 is a blue sub-pixel
  • the other one of the first sub-pixel 201 and the third sub-pixel 203 is a red sub-pixel
  • the second sub-pixel 202 and the fourth sub-pixel are 204 may be sub-pixels of the same color, for example, both are green sub-pixels.
  • the emission colors of the first sub-pixel 201, the second sub-pixel 202, the third sub-pixel 203 and the fourth sub-pixel 204 can be determined as needed.
  • the first sub-pixel 201, the second sub-pixel 202, the third sub-pixel 203 and the fourth sub-pixel 204 form a repeating unit, and the second sub-pixel 202 and the fourth sub-pixel 204 are located in the first sub-pixel.
  • the openings of the first partition structure 11 outside the second sub-pixel 202 and the first partition structure 11 outside the fourth sub-pixel 204 are in the same direction, and the first sub-pixel 201
  • the first partition structure 11 on the outside and the first partition structure 11 on the outside of the third sub-pixel 203 have the same opening direction.
  • the openings of the first partition structure 11 outside the second sub-pixel 202 and the first partition structure 11 outside the fourth sub-pixel 204 face the first partition structure 11 and the third partition structure 11 outside the first sub-pixel 201 .
  • the openings of the first partition structure 11 outside the sub-pixel 203 have different opening directions.
  • the openings of the first partition structure 11 outside the second sub-pixel 202 and the first partition structure 11 outside the fourth sub-pixel 204 face the first partition structure 11 and the third partition structure 11 outside the first sub-pixel 201 .
  • the openings of the first partition structure 11 outside the sub-pixel 203 face the opposite direction.
  • the openings of the first partition structure 11 outside the second sub-pixel 202 and the first partition structure 11 outside the fourth sub-pixel 204 both face upward.
  • the first partition structure 11 outside the first sub-pixel 201 and The openings of the first partition structure 11 outside the third sub-pixel 203 all face downward.
  • the first partition structure 11 is located at one corner of the light-emitting area R0.
  • the light-emitting area R0 includes four corners, and first partition structures 11 are provided outside the three corners of the light-emitting area R0.
  • the orthographic projection of the first partition structure 11 on the base substrate BS surrounds at least half of the orthographic projection of the light-emitting region R0 on the base substrate BS.
  • the orthographic projection of the first partition structure 11 on the base substrate BS surrounds at least three-quarters of the orthographic projection of the light-emitting area R0 on the base substrate BS.
  • the orthographic projection of the conductive structure 50 on the base substrate BS overlaps with the orthographic projection of the first partition structure 11 on the base substrate BS.
  • the conductive structure 50 includes the data line DT or the power line PL1.
  • the data line DT extends in the direction Y
  • the power line PL1 extends in the direction Y.
  • the data lines DT or the power lines PL1 are arranged in the direction X.
  • the conductive structure 50 may also be provided below the first partition structure 11 of other display substrates, and is not limited to the drawing showing the conductive structure 50 .
  • the conductive structure 50 may also be other conductors or structures such as capacitor plates.
  • FIG. 25A is a schematic plan view of another display substrate according to an embodiment of the present disclosure.
  • the first partition structure 11 is annular.
  • the first partition structure 11 is arranged in an annular shape to surround the light-emitting area R0.
  • the second electrode E2 is on the first partition structure 11.
  • the protruding portion is continuous to facilitate signal transmission on the second electrode E2 of different sub-pixels.
  • the cross-sectional view of the first partition structure 11 is as shown before.
  • the light-emitting area R0 of each sub-pixel SP is surrounded by a first partition structure 11 .
  • FIG. 25B is a schematic plan view of another display substrate according to an embodiment of the present disclosure.
  • the first partition structure 11 includes at least one partition substructure 01 , and the orthographic projection of the at least one partition substructure 01 on the base substrate BS at least surrounds the light-emitting area R0 One-half of the orthographic projection on the base substrate BS.
  • the light-emitting area R0 of each sub-pixel SP is surrounded by three or four partition substructures 01 .
  • the number of partition substructures 01 can be determined as needed.
  • the display substrate includes a first sub-pixel 201 , a second sub-pixel 202 , a third sub-pixel 203 and a fourth sub-pixel 204 .
  • one of the first sub-pixel 201 and the third sub-pixel 203 is a blue sub-pixel
  • the other one of the first sub-pixel 201 and the third sub-pixel 203 is a red sub-pixel
  • the second sub-pixel 202 and the fourth sub-pixel are 204 may be sub-pixels of the same color, for example, both are green sub-pixels.
  • the emission colors of the first sub-pixel 201, the second sub-pixel 202, the third sub-pixel 203 and the fourth sub-pixel 204 can be determined as needed.
  • a first sub-pixel 201, a second sub-pixel 202, a third sub-pixel 203 and a fourth sub-pixel 204 constitute a repeating unit RP.
  • the second sub-pixel 202 and the fourth sub-pixel 204 are respectively located on both sides of the center connecting line CL of the first sub-pixel 201 and the third sub-pixel 203.
  • 25A and 25B illustrate the center C1 of the first sub-pixel 201 and the center C2 of the third sub-pixel 203.
  • the first sub-pixel 201 and the third sub-pixel 203 are also located on both sides of the center line connecting the second sub-pixel 202 and the fourth sub-pixel 204.
  • only one partition structure is provided between two adjacent sub-pixels, so that the width of the interval between two adjacent sub-pixels can be reduced to increase the pixel density.
  • Spacers 58 are also shown in Figures 25A and 25B. Spacers 58 are configured to support the fine metal mask during fabrication of the light emitting layer.
  • the spacer 58 is within the area surrounded by the first sub-pixel 201, the second sub-pixel 202, the third sub-pixel 203, and the fourth sub-pixel 204.
  • a spacer 58 is provided between the first sub-pixel 201 and the third sub-pixel 203 arranged in the second direction Y.
  • Direction X intersects direction Y.
  • direction X is perpendicular to direction Y.
  • Both the direction X and the direction Y are directions parallel to the main surface of the base substrate.
  • direction Z is perpendicular to direction X, and perpendicular to direction Y.
  • first partition structure 11 In addition to the form of the first partition structure 11 shown in Figures 14 to 16, Figure 23, Figure 24, Figure 25A, and Figure 25B, the first partition structure 11 can also adopt other suitable forms.
  • FIG. 26 is a schematic diagram of a light-emitting element in a display substrate according to an embodiment of the present disclosure.
  • the light-emitting functional layer FL includes a stacked charge generation layer 40 , a first light-emitting layer 41 and a second light-emitting layer 42 .
  • the first light-emitting layer 41 is located on the first
  • the second light-emitting layer 42 is located between the second electrode E2 and the charge generation layer 40, and the charge generation layer 40 is disconnected at the protrusion PR1. Since the charge generation layer 40 is disconnected at the first isolation structure 11 , the propagation path of charges is longer, and the resistance of the charge generation layer in the light-emitting functional layer is larger, which can effectively avoid crosstalk between adjacent sub-pixels.
  • the sub-functional layer between the charge generation layer 40 and the first electrode E1 is also disconnected at the protrusion PR1, and the charge generation layer 40 is also disconnected at the protrusion PR1.
  • the sub-functional layer between layer 40 and second electrode E2 is not disconnected at protrusion PR1.
  • the sub-functional layer between the charge generation layer 40 and the first electrode E1 is also disconnected at the protrusion PR1, and the charge generation layer
  • the sub-functional layers between 40 and the second electrode E2 are also disconnected at the protruding portion PR1. In this case, each sub-functional layer of the light-emitting functional layer FL is disconnected at the protruding portion PR1.
  • the light-emitting functional layer FL further includes a first charge transport layer 51 located between the first electrode E1 and the first light-emitting layer 41 and a first charge transport layer 51 located between the first electrode E1 and the first light-emitting layer 41 . and the second charge transport layer 52 between the charge generation layer 40, the first charge transport layer 51 and the second charge transport layer 52 are disconnected at the protruding portion PR1.
  • the first charge transport layer 51 is a hole transport layer HTL
  • the second charge transport layer 52 is an electron transport layer ETL.
  • ETL electron transport layer
  • Figure 27 is a schematic diagram of a pixel circuit and a light-emitting element in a display substrate.
  • Figure 27 takes the pixel circuit of 7T1C as an example to illustrate. It should be noted that the pixel circuit is not limited to that shown in Figure 27 and can be set as needed.
  • the display substrate includes a sub-pixel SP, and the sub-pixel includes a pixel circuit PXC and a light-emitting element EMC.
  • the light-emitting element EMC includes a first electrode E1, a second electrode E2, and a light-emitting functional layer located between the first electrode E1 and the second electrode E2.
  • the pixel circuit PXC includes a transistor and a storage capacitor Cst.
  • the transistors include transistors T1-T7, and the storage capacitor Cst includes plate Ca1 and plate Cb1.
  • 27 also shows the gate line GT that provides the scan signal SCAN, the data line DT that provides the data signal DATA, the light-emitting control signal line EML that provides the light-emitting control signal EM, the power line PL1 that provides the power supply voltage VDD, the power line PL1 that provides the power supply voltage VSS.
  • the transistor T1 is a driving transistor
  • the transistor T2 is a data writing transistor
  • the transistor T3 is a threshold compensation transistor
  • the transistor T4 is a light emission control transistor
  • the transistor T5 is a light emission control transistor
  • the transistor T6 is a reset control transistor.
  • Transistor T7 is a reset control transistor.
  • the second partition structure 12 is annular to surround the hole region R2.
  • the second electrode E2 is disconnected at the protruding portion PR2 of the second partition structure 12 .
  • the second electrode E2 is continuous at the protrusion PR1.
  • the first partition structure 11 is annular and is continuously arranged around the light-emitting area.
  • the first partition structure 11 has a gap 1101.
  • the size of the first partition portion 11 a in the direction perpendicular to the base substrate BS is smaller than the size of the second partition portion 11 b in the direction perpendicular to the base substrate BS.
  • the first partition portion 11 a has a larger size in a direction perpendicular to the base substrate BS than the second partition portion 11 b Dimensions in a direction perpendicular to the base substrate BS.
  • the size of the first partition portion 11 a in the direction perpendicular to the base substrate BS is smaller than the size of the third partition portion 13 in the direction perpendicular to the base substrate BS.
  • the second partition part 11 b and the fourth partition part 14 are located on the same layer.
  • the second partition part 11b and the fourth partition part 14 are located on different layers and made of different materials.
  • the first partition structure 11 and the second partition structure 12 have the same layer structure.
  • the first partition structure 11 and the second partition structure 12 have different layer structures.
  • the number of film layers included in the first partition portion 11 a is less than or equal to the number of film layers included in the third partition portion 13 .
  • the material of the first partition structure 11 includes a conductive material
  • the material of the second partition structure 12 includes a conductive material.
  • conductive materials include metals and conductive metal oxides.
  • the material of the first partition structure 11 includes an inorganic insulating material
  • the material of the second partition structure 12 includes an inorganic insulating material
  • the first partition part 11 a and the second partition part 11 b are made of different materials
  • the third partition part 13 and the fourth partition part 14 are made of different materials.
  • the materials are different
  • the first partition part 11a and the third partition part 13 are made of the same material
  • the second partition part 11b and the fourth partition part 14 are made of the same material.
  • the materials of the first partition part 11 a and the third partition part 13 include organic materials
  • the materials of the second partition part 11 b and the fourth partition part 14 include inorganic insulating materials.
  • the material of the first partition part 11 a and the third partition part 13 includes an organic insulating material
  • the material of the second partition part 11 b and the fourth partition part 14 includes a conductive material.
  • the material of the first partition part 11a includes an organic insulating material
  • the material of the second partition part 11b includes an organic insulating material
  • the material of the third partition part 13 includes an inorganic insulating material
  • the material of the fourth partition part 14 includes Materials include conductive materials.
  • the first partition part 11a and the second partition part 11b have an integrated structure.
  • the material of the second partition part 11b is different from the material of the first partition part 11a.
  • the inorganic insulating material includes SiOx, SiNy, or SiOxNy.
  • conductive materials include metals or conductive metal oxides.
  • the organic insulating material includes one or a combination of acrylic, polyethylene terephthalate, polyimide, polyamide, polycarbonate, epoxy resin, etc.
  • a plurality of second partition structures 12 are provided.
  • the second partition structure 12 also includes a fifth partition part 15 .
  • the material of the fifth partition part 15 includes a conductive material.
  • the plurality of second partition structures 12 The fifth partition part 15 is an integral structure, and a plurality of fourth partition parts 14 are arranged sequentially around the hole area R2.
  • the conductive part 61 is the fifth partition part 15 .
  • the first partition structure 11 is T-shaped.
  • the second electrode E2 is the cathode of the light-emitting element
  • the first electrode E1 is the anode of the light-emitting element
  • the display substrate forms a common cathode structure.
  • the second electrode E2 is a continuous electrode on the entire surface and is not interrupted by the partition structure, it is beneficial to reduce the resistance of the second electrode E2 and facilitate signal transmission on the second electrode E2.
  • the first electrodes E1 of different sub-pixels are insulated from each other, and the first electrodes E1 of different sub-pixels are provided independently of each other and can be applied with different signals.
  • the second electrodes E2 of different sub-pixels are connected to each other and can be applied with the same signal.
  • FIG. 4 and FIG. 7 take the second partition structure 12 located on both sides of the barrier dam 17 as an example to illustrate the same structure.
  • the structures of the second partition structures 12 located on both sides of the barrier dam 17 may also be different, so that the second electrode E2 is located outside the barrier dam 17 (to the left of the barrier dam 17 in the figure). is blocked, but is not blocked inside the barrier dam 17 (the right side of the barrier dam 17 in the figure), or so that the second electrode E2 is not blocked outside the barrier dam 17 (the left side of the barrier dam 17 in the figure), On the other hand, the inner side of the barrier dam 17 (the right side of the barrier dam 17 in the figure) is blocked.
  • the isolation of the second electrode E2 by the first isolation structure 11 and the second isolation structure 12 can be achieved by controlling process conditions or adding processes. Whether the second electrode E2 is blocked at the first partition structure 11 or the second partition structure 12 can also be realized by adjusting the process.
  • the thickness of the first partition structure 11 in the direction perpendicular to the base substrate BS is smaller than the thickness of the planarization layer PLN in the direction perpendicular to the base substrate BS.
  • the maximum thickness of the first partition structure 11 in the direction perpendicular to the substrate BS is smaller than the planarization layer PLN in the direction perpendicular to the substrate.
  • the maximum thickness in the direction of the base substrate BS is smaller than the planarization layer PLN in the direction perpendicular to the substrate.
  • the maximum thickness of the first partition structure 11 in the direction perpendicular to the substrate BS is smaller than the planarization layer PLN in the direction perpendicular to the substrate.
  • the maximum thickness in the direction of the base substrate BS is smaller than the planarization layer PLN in the direction perpendicular to the substrate.
  • the maximum thickness of the first partition structure 11 in the direction perpendicular to the base substrate BS is equal to the maximum thickness of the pixel defining pattern PDL in the direction perpendicular to the base substrate BS.
  • the side of the first partition 11a is arc-shaped, and the transition is relatively gentle, which is conducive to the placement of the second electrode E2 on the first partition 11a on the side.
  • the material of the second electrode E2 is usually metal or alloy, and metal or alloy has better climbing performance.
  • the side shape of the first partition portion 11a can also be adjusted.
  • organic materials include resin, but are not limited thereto.
  • the organic material includes one or a combination of acrylic or polyethylene terephthalate, polyimide, polyamide, polycarbonate, epoxy resin, etc.
  • the display substrate provided by some embodiments of the present disclosure can effectively realize that the first partition structure and the second partition structure can be etched simultaneously, and has good process compatibility.
  • the first partition structure and the second partition structure can be formed by etching after the backplane process is completed, without risks such as glue holes.
  • components located on the same layer may be formed from the same film layer through the same patterning process.
  • the patterning or patterning process may include only a photolithography process, or may include a photolithography process and an etching step, or may include printing, inkjet, or other processes for forming predetermined patterns.
  • Photolithography process refers to processes including film formation, exposure, development, etc., using photoresist, mask, exposure machine, etc. to form patterns.
  • a corresponding patterning process may be selected according to the structure formed in the embodiments of the present disclosure.
  • the thickness of a component refers to the dimension of the component in a direction perpendicular to the base substrate.
  • the base substrate BS, buffer layer BF, insulating layer GI1, insulating layer GI2, insulating layer ILD, planarization layer PLN, and spacer PS are all made of insulating materials.
  • the material of the base substrate BS includes polyimide, but is not limited thereto.
  • the materials of the buffer layer BF, the insulating layer GI1, the insulating layer GI2, and the insulating layer ILD include inorganic insulating materials.
  • the materials of the planarization layer PLN, the pixel defining pattern PDL, and the spacer PS include organic insulating materials.
  • the inorganic insulating material includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.
  • the organic insulating material includes one or a combination of acrylic, polyethylene terephthalate, polyimide, polyamide, polycarbonate, epoxy resin, etc.
  • the insulating layer GI1 may also be called a gate insulating layer
  • the insulating layer GI2 may also be called a gate insulating layer
  • the insulating layer ILD may also be called an interlayer insulating layer.
  • An embodiment of the present disclosure also provides a display device, including any of the above display substrates.
  • FIG. 28 is a schematic diagram of a display device provided by an embodiment of the present disclosure.
  • the display device 500 includes a display substrate 100 .
  • the display substrate 100 is any of the above display substrates.
  • the display substrate mentioned in the embodiments of the present disclosure may also be called a display panel.
  • the display substrate may be a flexible display substrate, but is not limited thereto.
  • the display substrate disposes a partition structure between adjacent sub-pixels, and causes at least one sub-functional layer in the light-emitting functional layer, for example, a charge generation layer, to be disconnected at the location where the partition structure is located. , thereby avoiding crosstalk between adjacent sub-pixels caused by sub-functional layers with higher conductivity (for example, charge generation layers). Therefore, a display device including the display substrate can also avoid crosstalk between adjacent sub-pixels, and therefore has higher product yield and higher display quality.
  • the display substrate can adopt a Tandem structure to increase the pixel density. Therefore, a display device including the display substrate has the advantages of long life, low power consumption, high brightness, and high resolution.
  • the display device can be a display device such as an organic light-emitting diode display device, as well as any product or component with a display function such as a television, a digital camera, a mobile phone, a watch, a tablet computer, a notebook computer, a navigator, etc. including the display device. Examples include but are not limited to this.

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Abstract

提供一种显示基板和显示装置。显示基板包括：衬底基板；多个子像素，子像素包括发光元件，发光元件包括第一电极、发光功能层、以及第二电极，发光功能层包括多个子功能层；第一隔断结构，位于显示区，并包括层叠设置的第一隔断部和第二隔断部，第一隔断部位于第二隔断部的靠近衬底基板的一侧；以及第二隔断结构，位于边框区，并包括层叠设置的第三隔断部和第四隔断部，第三隔断部位于第四隔断部的靠近衬底基板的一侧；第二隔断部具有第一突出部，第一突出部相对于第一隔断部突出，发光功能层的至少一个子功能层在第一突出部处断开，第四隔断部具有第二突出部，第二突出部相对于第三隔断部突出，发光功能层的至少一个子功能层在第二突出部处断开。

Description

显示基板和显示装置
相关申请的交叉引用
出于所有目的，本申请要求于2021年11月30日递交的中国专利申请第202111444104.8号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种显示基板和显示装置。
背景技术
随着显示技术的不断发展，有机发光二极管(OLED)显示装置因其广色域、高对比度、轻薄设计、自发光、以及宽视角等优点已经成为当前各大厂商的研究热点和技术发展的方向。
目前，有机发光二极管显示装置已经广泛地应用到各种电子产品中，小到智能手环、智能手表、智能手机、平板电脑等电子产品，大到笔记本电脑、台式电脑、电视机等电子产品。因此，市场对于有源矩阵有机发光二极管显示装置的需求也日益旺盛。
发明内容
本公开的实施例提供一种显示基板和显示装置。
本公开的实施例提供一种显示基板，包括：衬底基板，包括孔区、显示区以及位于所述孔区和所述显示区之间的边框区；多个子像素，位于所述显示区，所述子像素包括发光元件，所述发光元件具有发光区，所述发光元件包括第一电极、发光功能层、以及第二电极，所述第二电极位于所述发光功能层的背离所述衬底基板的一侧，所述第一电极位于所述发光功能层的靠近所述衬底基板的一侧，所述发光功能层包括多个子功能层；第一隔断结构，位于所述显示区，并包括层叠设置的第一隔断部和第二隔断部，所述第一隔断部位于所述第二隔断部的靠近所述衬底基板的一侧；以及第二隔断结构，位于所述边框区，并包括层叠设置的第三隔断部和第四隔断部，所述第三隔断部位于所述第四隔断部的靠近所述衬底基板的一侧；所述第二隔断部具有第一突出部，所述第一突出部相对于所述第一隔断部突出，所述发光功能层的至少一个子功能层在所述第一突出部处断开，所述第四隔断部具有第二突出部，所述第二突出部相对于所述第三隔断部突出，所述发光功能层的至少一个子功能层在所述第二突出部处断开；所述第一隔断结构围绕所述发光区；所述第二隔断结构呈环形，以围绕所述孔区。
根据本公开的实施例提供的显示基板，所述第二电极在所述第一突出部处连续，所述第一隔断结构环形设置。
根据本公开的实施例提供的显示基板，所述第一隔断结构呈环形，连续设置。
根据本公开的实施例提供的显示基板，所述第一隔断结构具有缺口，所述第一电极具有主体部和连接部，所述主体部在所述衬底基板上的正投影与所述发光区在所述衬底基板上的正投影交叠，所述连接部位于所述缺口处。
根据本公开的实施例提供的显示基板，显示基板还包括封装层，所述封装层包括第一封装层、第二封装层和第三封装层，所述第一封装层、所述第二封装层和所述第三封装层依次设置，所述第一封装层比所述第三封装层更靠近所述衬底基板，所述第一封装层和所述第三封装层具有叠层接触部，所述第二隔断结构设置为多个，多个第二隔断结构中的一个在所述衬底基板上的正投影与所述第二封装层在所述衬底基板上的正投影交叠，所述多个第二隔断结构中的另一个在所述衬底基板上的正投影与所述叠层接触部在所述衬底基板上的正投影交叠。
根据本公开的实施例提供的显示基板，显示基板还包括阻挡坝，所述阻挡坝位于所述边框区，所述第二隔断结构包括位于所述阻挡坝的两侧的两个第二隔断结构。
根据本公开的实施例提供的显示基板，所述第二隔断部的厚度大于所述第一隔断部的厚度。
根据本公开的实施例提供的显示基板，所述第一隔断部与所述第二隔断部的厚度之比大于或等于0.25，并且小于或等于1。
根据本公开的实施例提供的显示基板，所述第一隔断部在垂直于所述衬底基板的方向上的尺寸小于所述第三隔断部在垂直于所述衬底基板的方向上的尺寸。
根据本公开的实施例提供的显示基板，所述第二隔断部和所述第四隔断部位于同一层。
根据本公开的实施例提供的显示基板，所述第一隔断结构和所述第二隔断结构具有相同的层结构。
根据本公开的实施例提供的显示基板，所述第一隔断部包括的膜层的个数小于或等于所述第三隔断部包括的膜层的个数。
根据本公开的实施例提供的显示基板，所述第一隔断结构的材料包括导电材料，所述第二隔断结构的材料包括导电材料。
根据本公开的实施例提供的显示基板，所述导电材料包括金属和导电的金属氧化物。
根据本公开的实施例提供的显示基板，所述第二隔断部和所述第四隔断 部位于同一层，所述第三隔断部包括与所述第一隔断部位于同一层的部分。
根据本公开的实施例提供的显示基板，所述第一隔断结构的材料包括无机绝缘材料，所述第二隔断结构的材料包括无机绝缘材料。
根据本公开的实施例提供的显示基板，所述第一隔断部和所述第二隔断部的材料不同，所述第三隔断部和所述第四隔断部的材料不同，所述第一隔断部和所述第三隔断部的材料相同，所述第二隔断部和所述第四隔断部的材料相同。
根据本公开的实施例提供的显示基板，所述第一隔断部和所述第三隔断部的材料包括有机材料，所述第二隔断部和所述第四隔断部的材料包括无机绝缘材料。
根据本公开的实施例提供的显示基板，所述第一隔断部和所述第三隔断部的材料包括有机绝缘材料，所述第二隔断部和所述第四隔断部的材料包括导电材料。
根据本公开的实施例提供的显示基板，所述第一隔断部的材料包括有机绝缘材料，所述第二隔断部的材料包括有机绝缘材料，所述第三隔断部的材料包括无机绝缘材料，所述第四隔断部的材料包括导电材料。
根据本公开的实施例提供的显示基板，所述第一隔断部和所述第二隔断部为一体结构。
根据本公开的实施例提供的显示基板，所述第二隔断结构包括两个子隔断结构，所述两个子隔断结构的第二突出部相对设置。
根据本公开的实施例提供的显示基板，所述第二隔断结构设置为多个，所述第二隔断结构还包括第五隔断部，所述第五隔断部的材料包括导电材料，多个第二隔断结构的第五隔断部为一体结构，多个第四隔断部围绕所述孔区依次设置。
根据本公开的实施例提供的显示基板，显示基板还包括导电结构，所述导电结构在所述衬底基板上的正投影与所述第一隔断结构在所述衬底基板上的正投影交叠。
根据本公开的实施例提供的显示基板，所述导电结构包括数据线或电源线。
根据本公开的实施例提供的显示基板，所述第一隔断结构呈T字型。
根据本公开的实施例提供的显示基板，所述隔断结构包括至少一个隔断子结构，所述至少一个隔断子结构在所述衬底基板上的正投影至少环绕所述发光区在所述衬底基板上的正投影的二分之一。
本公开的实施例还提供一种显示装置，包括上述任一显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为发光元件的示意图。
图2为一种显示基板的示意图。
图3为一种显示基板的示意图。
图4为本公开的实施例提供的显示基板的截面示意图。
图5A是图4中的第一隔断结构处的放大图。
图5B是图4中的第二隔断结构处的放大图。
图6A至图6D为图4所示的显示基板的制作方法的流程图。
图7为本公开的实施例提供的显示基板的截面示意图。
图8A是图7中的第一隔断结构处的放大图。
图8B是图7中的第二隔断结构处的放大图。
图9A至图9C为图7所示的显示基板的制作方法的流程图。
图10为本公开的实施例提供的显示基板的剖视示意图。
图11A为本公开的实施例提供的另一显示基板的剖视示意图。
图11B为本公开的实施例提供的另一显示基板的剖视示意图。
图11C为本公开的实施例提供的另一显示基板的剖视示意图。
图12A为本公开的实施例提供的显示基板的制作流程图。
图12B为本公开的实施例提供的显示基板的制作流程图。
图13为本公开的实施例提供的显示基板中的多个第二隔断结构的平面示意图。
图14为图10所示的显示基板中的第一隔断结构和第一电极的平面示意图。
图15为图11A或图11B所示的显示基板中的第一隔断结构和导电结构的平面示意图。
图16为图10所示的显示基板中的第一隔断结构的平面示意图。
图17为本公开的实施例提供的一种显示基板的剖视示意图。
图18A为本公开的实施例提供的另一显示基板的剖视示意图。
图18B为本公开的实施例提供的另一显示基板的剖视示意图。
图18C为本公开的实施例提供的另一显示基板的剖视示意图。
图19A为本公开的实施例提供的显示基板的制作流程图。
图19B为本公开的实施例提供的显示基板的制作流程图。
图20为本公开的实施例提供的一种显示基板的剖视示意图。
图21为图20所示的显示基板的制作流程图。
图22为图20所示的显示基板的边框区内的第二隔断结构的平面图。
图23为本公开的实施例提供的显示基板的显示区内的第一隔断结构的平面图。
图24为本公开的实施例提供的显示基板的显示区内的第一隔断结构的平面图。
图25A为本公开一实施例提供的另一种显示基板的平面示意图。
图25B为本公开一实施例提供的另一种显示基板的平面示意图。
图26为本公开的实施例提供的显示基板中的发光元件的示意图。
图27为一种显示基板中的像素电路和发光元件的示意图。
图28为本公开一实施例提供的一种显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
随着显示技术的不断发展，人们对于显示品质的追求也越来越高。为了进一步降低功耗并实现高亮度，可将OLED显示基板中的发光元件中的一个发光层替换为两个发光层，并在该两个发光层之间增加电荷产生层(CGL)，使用N/P-CGL作为异质结，将两个发光器件结构串联，形成双叠层设计，构成Tandem结构，Tandem结构的显示基板实现了双发光器件串联，在相同发光强度下，极大地降低了发光元件的发光电流，提升了发光元件的寿命，有利于车载等高寿命新技术开发量产。Tandem结构的显示装置具有寿命长、功耗低、亮度高等优点。
图1为发光元件的示意图。图1(a)为通常的发光元件的示意图。图1(b)为一种具有Tandem结构的发光元件的示意图。如图1(b)所示，Tandem结构的不同发光元件之间的电荷产生层(CGL)是相连的。
图1示出了第一电极E1、第二电极E2、空穴传输层HTL、电子传输层ETL、光耦合层CPL、增透层ARL、P型掺杂的电荷产生层P-CGL、N型掺杂的电荷产生层N-CGL、发光层R、发光层G、发光层B。发光层R包括分别含有发光材料r1和发光材料r2的两个子层，发光层G包括分别含有发光材料g1和发光材料g2的两个子层，发光层B包含发光材料b1和发光材料b2。发光材料r1和发光材料r2为发红光的两种不同的材料，发光材料g1和发光材料g2为发绿光的两种不同的材料，发光材料b1和发光材料b2为发蓝光的两种不同的材料。
图2为一种显示基板的示意图。如图2所示，显示基板包括平坦化层PLN1、平坦化层PLN2、像素限定层PDL、电极E1、发光功能层FL、电极E2以及封装层EPS。图1示出了发光元件EM01和发光元件EM02，发光元件EM01和发光元件EM02的电荷产生层(CGL)可为一体结构，采用开口掩膜来制作。
然而，发明人注意到，对于高分辨率的产品而言，由于电荷产生层具有较强的导电性，而相邻的子像素的发光功能层(这里指包括两个发光层和电荷产生层的膜层)是相连的，因此电荷产生层(子功能层)容易导致相邻子像素之间的串扰，影响产品画质，从而严重地影响显示品质。
例如，相邻子像素之间的串扰是指应该不发光的发光元件发光的情况。如图2所示，若想要的情况是发光元件EM01发光，而发光元件EM02不发光，但因电荷产生层的导电性，使得发光元件EM02也发光，从而形成串扰。
图3为一种显示基板的示意图。如图3所示，显示基板包括孔区R2、显示区R1和位于孔区R2和显示区R1之间的边框区R3。如图3所示，孔区R2为圆形。需要说明的是，本公开的实施例以孔区R2的形状为圆形为例进行说明，但孔区R2也可以采用其他适合的形状，不限于圆形。并且，孔区R2的设置位置也不限于图中所示，可根据需要进行设置。例如，部分栅线、部分数据线等导线在孔区R2周围绕线，形成边框区R3。
例如，采用屏内开孔的方案时，孔区R2内的至少部分结构被去除，即，屏内开孔的方案需牺牲部分的显示区以形成孔区。例如，显示基板的孔区R2内的全部结构均被去除。例如，在形成封装层之后，进行挖孔去除显示基板的位于孔区R2的部分。传感器可部分设置在孔区R2内，也可以全部设置在孔区R2内。例如，传感器包括相机。
一方面，为了避免水氧侵袭发光元件，在边框区R3可以设置隔断结构，以隔断发光元件的发光功能层，避免水氧沿着孔区R2周围的发光功能层进入显示区R1。
另一方面，为了减轻或避免因发光功能层中的导电性较强的子功能层导致的串扰问题，可在显示区设置隔断结构。
本公开的实施例提供的显示基板，在显示区R2设置第一隔断结构，以提升显示基板的信赖性，在边框区R3设置第二隔断结构，以减轻或避免串扰。
图4为本公开的实施例提供的显示基板的截面示意图。图5A是图4中的第一隔断结构处的放大图。图5B是图4中的第二隔断结构处的放大图。图6A至图6D为图4所示的显示基板的制作方法的流程图。
如图4所示，显示基板DP1包括：衬底基板BS、多个子像素SP、第一隔断结构11以及第二隔断结构12。如图4所示，衬底基板BS包括孔区R2、显示区R1以及位于孔区R2和显示区R1之间的边框区R3。
如图4所示，多个子像素SP位于衬底基板BS的主表面SF0上，子像素SP包括发光元件EMC，发光元件EMC具有发光区R0。
如图4所示，发光元件EMC包括第一电极E1、发光功能层FL、以及第二电极E2，第二电极E2位于发光功能层FL的背离衬底基板BS的一侧，第一电极E1位于发光功能层FL的靠近衬底基板BS的一侧，发光功能层FL包括多个子功能层。
例如，第一电极E1采用导电材料制作。例如，第一电极E1的材料包括金属和导电的金属氧化物。例如，第一电极E1采用氧化铟锡(ITO)、银(Ag)、氧化铟锡(ITO)层叠设置的结构。第一电极E1的材料和结构可根据需要设置。
例如，第二电极E2采用导电材料制作。例如，第二电极E2的材料包括金属或合金。例如，第二电极E2的材料包括Mg/Ag合金。第二电极E2的材料和结构可根据需要设置。
例如，不同子像素的第二电极E2电连接，以利于提供相同的电压信号。
如图4和图5A所示，第一隔断结构11位于显示区R1，第一隔断结构11位于相邻子像素SP的发光区R0之间，并包括层叠设置的第一隔断部11a和第二隔断部11b，第一隔断部11a位于第二隔断部11b的靠近衬底基板BS的一侧；第二隔断部11b具有突出部PR1，突出部PR1相对于第一隔断部11a突出。例如，突出部PR1相对于第一隔断部11a的至少一部分突出。例如，突出部PR1相对于第一隔断部11a的靠近第二隔断部11b的一侧突出，发光功能层FL的至少一个子功能层在突出部PR1处断开。例如，从第一电极E1指向第二电极E2的方向为方向Z。第一隔断结构11具有突出部PR1利于隔断发光功能层FL的至少一个子功能层。
例如，一个元件在突出部PR1处断开包括在突出部PR1的侧面处断开。
如图4和图5B所示，第二隔断结构12位于边框区R3，并包括层叠设置的第三隔断部13和第四隔断部14，第三隔断部13位于第四隔断部14的靠近衬底基板BS的一侧。
如图4所示，第四隔断部14具有突出部PR2，突出部PR2相对于第三隔 断部13突出，发光功能层FL的至少一个子功能层在突出部PR2处断开。例如，突出部PR2相对于第三隔断部13的靠近第四隔断部14的一侧突出。
如图4所示，显示基板包括缓冲层BF、绝缘层GI1、绝缘层GI2、绝缘层ILD、平坦化层PLN、像素限定图案PDL、隔垫物PS。隔垫物PS被配置为在制作发光层时支撑精细金属掩模。例如，如图4所示，像素限定图案PDL包括多个开口OPN，开口OPN被配置为限定子像素SP的发光区R0，开口OPN被配置为暴露第一电极E1的至少一部分。
图4还示出了薄膜晶体管T0，薄膜晶体管T0包括栅极GE、有源层CV、源极Ea、漏极Eb，第一电极E1与漏极Eb相连。薄膜晶体管的源极Ea和漏极Eb在结构上可相同，在称谓上可互换。
图4还示出了电容C0的第一极板Ca和第二极板Cb。例如，电容C0可为后续提及的存储电容Cst，但不限于此。
图4还示出了封装层EPS。例如，封装层EPS包括第一封装层EPS1、第二封装层EPS2、以及第三封装层EPS3。例如，第一封装层EPS1和第三封装层EPS3为无机层，可采用化学气相沉积(CVD)工艺形成。第二封装层EPS2为有机层，可采用喷墨打印工艺形成。如图4所示，第二封装层EPS2的厚度大于第一封装层EPS1的厚度。如图4所示，第二封装层EPS2的厚度大于第三封装层EPS3的厚度。
如图4所示，在边框区R3，第一封装层EPS1和第三封装层EPS3接触，形成叠层接触部CP。
例如，第二隔断部11b的厚度大于第一隔断部11a的厚度的情况下，更利于封装层EPS的封装。
例如，在隔断结构的两个隔断部的厚度差较小的情况下，更利于封装层EPS的封装，利于提高封装效果。
例如，在第一隔断部11a与第二隔断部11b的厚度之比大于或等于0.25，并且小于或等于1的情况下，更利于封装层EPS的封装。
图4和图5B还示出了阻挡坝17。阻挡坝17包括子坝171和子坝172。例如，子坝171和平坦化层PLN位于同一层，由同一膜层采用同一构图工艺形成。例如，子坝172和像素限定图案PDL位于同一层，由同一膜层采用同一构图工艺形成。
如图4和图5B所示，显示基板包括两个第二隔断结构12：隔断结构121和隔断结构122，隔断结构121和隔断结构122分设在阻挡坝17的两侧。阻挡坝17在垂直于衬底基板BS的方向(方向Z)上的尺寸大于第二隔断结构12在垂直于衬底基板BS的方向上的尺寸。图4和图5B仅示出了两个第二隔断结构12，需要说明的是，还可以设置三个或三个以上的第二隔断结构12。
如图4和图5B所示，隔断结构121在衬底基板BS上的正投影与第二封 装层EPS2在衬底基板BS上的正投影交叠，隔断结构121在衬底基板BS上的正投影和叠层接触部CP在衬底基板BS上的正投影交叠。
图4和图5B以一个第二隔断结构12在衬底基板BS上的正投影与第二封装层EPS2在衬底基板BS上的正投影交叠为例进行说明，但不限于此。例如，在另一些实施例中，多个第二隔断结构12在衬底基板BS上的正投影与第二封装层EPS2在衬底基板BS上的正投影交叠。
图4和图5B以一个第二隔断结构12在衬底基板BS上的正投影和叠层接触部CP在衬底基板BS上的正投影交叠为例进行说明，但不限于此。例如，在另一些实施例中，多个第二隔断结构12在衬底基板BS上的正投影和叠层接触部CP在衬底基板BS上的正投影交叠。
例如，如图4和图5B所示，阻挡坝17的左侧设有至少一个第二隔断结构12，在本公开的一些实施例中，阻挡坝17的左侧设有3-7个第二隔断结构12。例如，如图4和图5B所示，阻挡坝17的右侧设有至少一个第二隔断结构12，在本公开的一些实施例中，阻挡坝17的右侧设有3-7个第二隔断结构12。
如图4和图5B所示，隔断结构122在衬底基板BS上的正投影与第二封装层EPS2在衬底基板BS上的正投影不交叠。
如图4所示，第一导电图案层LY1包括栅极GE和第一极板Ca，第二导电图案层LY2包括第二极板Cb，第三导电图案层LY3包括源极Ea和漏极Eb。例如，第三导电图案层LY3可包括层叠设置的多个子层，例如，第三导电图案层LY3可包括Ti/Al/Ti三个子层的叠层结构。
例如，如图4所示，第一隔断部11a可为金属层，例如，为Mo层。例如，如图4所示，第一隔断部11a的厚度为
Figure PCTCN2022124631-appb-000001
因第一隔断部11a的材料为金属材料，例如，为金属Mo，厚度较小，利于使得第一隔断结构11隔断发光功能层FL，并且不隔断第二电极E2，利于第二电极E2保持连续，利于提高显示基板发光的均一性。
例如，如图4所示，第一隔断部11a的厚度小于第二隔断部11b的厚度。
例如，如图4所示，第三隔断部13包括子层131和子层132。例如，子层131可与薄膜晶体管的源极Ea和漏极Eb位于同一层。例如，子层132可以与第一隔断部11a位于同一层。
例如，如图4所示，第一隔断部11a的材料包括Mo，第三隔断部13的材料包括Mo、Al和Ti。第三隔断部13包括与第一隔断部11a位于同一层的部分。即，第三隔断部13包括与第一隔断部11a位于同一层的子层132。
例如，如图4所示，第二隔断部11b和第四隔断部14位于同一层。第二隔断部11b和第四隔断部14可均与第一电极E1位于同一层。
如图4所示，第二隔断结构12的第三隔断部13的厚度大于第一隔断结 构11的第一隔断部11a的厚度，使得在孔区R2附近的边框区R3，发光功能层FL和第二电极E2均被隔断，从而，将发光材料在显示区域和孔之间进行隔断，防止孔周围的水氧沿着发光材料进入显示区R1，提高发光元件的使用寿命。
如图4所示，根据本公开的实施例提供的显示基板，显示基板还包括像素电路PXC，像素电路PXC被配置为驱动发光元件EMC发光，第一电极E1通过贯穿平坦化层PLN的过孔V0与像素电路PXC相连。
例如，如图4所示，多个子像素SP包括子像素SP1和子像素SP2。子像素SP1和子像素SP2为两个相邻的子像素。显示基板上设置的子像素的个数不限于图中所示，可根据需要而定。
在本公开的实施例中，发光功能层FL包括的子功能层的数量可根据需要来设置。
在本公开的实施例提供的显示基板中，可通过在相邻的子像素之间设置第一隔断结构，并使得发光功能层中的多个子功能层中的至少一个在隔断结构所在的位置断开，增大发光功能层FL中的导电率较高的子功能层的电阻，从而减轻或避免多个子功能层中导电率较高的膜层造成相邻子像素之间的串扰，减轻或防止发光元件在发光时发生串扰。
本公开的实施例提供的显示基板，第一隔断结构11在形成第一电极E1之后形成，不需改变显示基板的背板结构。并且，第一隔断结构11设置在发光元件的第一电极E1之间，使得第一隔断结构11有较大的设置空间，利于设置不同结构的第一隔断结构11。
图4所示的第一隔断结构11的材料和第二隔断结构12的材料均为导电材料。第一隔断结构11可以隔断有机发光材料，可以设置在显示区的相邻子像素之间。
图6A至图6D示出了显示基板DP1的制作方法。显示基板DP1的制作方法包括如下步骤。
如图6A所示，显示基板的制作方法包括：在衬底基板上形成缓冲层BF，然后在缓冲层BF上形成有源层CV，以及在有源层CV上形成绝缘层GI1。在绝缘层GI1上形成栅极GE和第一极板Ca，在栅极GE和第一极板Ca上形成绝缘层GI2，在绝缘层GI2上形成第二极板Cb，在第二极板Cb上形成绝缘层ILD，在绝缘层ILD上形成源极Ea、漏极Eb、以及中间子层1310。
如图6B所示，在源极Ea、以及漏极Eb上形成平坦化层PLN并在边框区形成子坝171，在显示区形成中间层11aa并在边框区形成中间子层1320。
如图6C所示，在显示区形成第一电极E1和第二隔断部11b，并在边框区形成第四隔断部14；在显示区形成像素限定图案PDL和隔垫物PS，并在边框区形成子坝172。
如图6D所示，对中间层11aa、中间子层1310和中间子层1320进行刻蚀，形成第一隔断部11a和第三隔断部13。
图7为本公开的实施例提供的显示基板的截面示意图。图8A是图7中的第一隔断结构处的放大图。图8B是图7中的第二隔断结构处的放大图。图9A至图9C为图7所示的显示基板的制作方法的流程图。
图7所示的显示基板DP2与图4所示的显示基板DP1的区别在于：图7所示的第一隔断结构11和第二隔断结构12均为无机绝缘结构。
如图7所示，第一隔断结构11包括第一隔断部11a和第二隔断部11b。第一隔断部11a和第二隔断部11b均采用无机绝缘材料。
如图7所示，第二隔断结构12包括第三隔断部13和第四隔断部14。第三隔断部13包括子层131和子层132。第三隔断部13(子层131和子层132)和第四隔断部14均采用无机绝缘材料。
例如，如图7所示，第一隔断部11a、第二隔断部11b、第三隔断部13和第四隔断部14采用的无机绝缘材料包括SiOx、SiNy、SiOxNy至少之一。
如图7、图8A、图8B所示，第一隔断结构11呈T字型，第二隔断结构12包括呈T字型的部分。
当然，第一隔断结构11不限于T字型，在其他的实施例中，第一隔断结构11也可以呈工字型，也可以采用其他适合的形状。第二隔断结构12可以呈T字型，也可以呈工字型，当然，也可以采用其他适合的形状。
图9A至图9C示出了显示基板DP2的制作方法。显示基板的制作方法包括如下步骤。
如图9A所示，在衬底基板上形成缓冲层BF，然后在缓冲层BF上形成有源层CV，以及在有源层CV上形成绝缘层GI1。在绝缘层GI1上形成栅极GE和第一极板Ca，在栅极GE和第一极板Ca上形成绝缘层GI2，在绝缘层GI2上形成第二极板Cb，在第二极板Cb上形成绝缘层ILD以及中间子层1310，在绝缘层ILD上形成源极Ea和漏极Eb。
如图9B所示，在源极Ea和漏极Eb上形成平坦化层PLN并在边框区形成子坝171；在显示区形成中间层11aa并在边框区形成中间子层1320；以及在显示区形成第二隔断部11b，并在边框区形成第四隔断部14；在显示区形成第一电极E1；在显示区形成像素限定图案PDL并在边框区形成子坝172；形成隔垫物PS。
如图9C所示，对中间层11aa、中间子层1310和中间子层1320进行刻蚀，形成第一隔断部11a和第三隔断部13。
例如，如图7所示，第一隔断部11a和第二隔断部11b采用不同的无机绝缘材料，以利于形成具有突出部的第一隔断结构11。例如，如图7所示，第三隔断部13和第四隔断部14采用不同的无机绝缘材料，以利于形成具有 突出部的第二隔断结构12。
例如，如图7所示，第一隔断部11a和第三隔断部13的子层132位于同一层，第二隔断部11b和第四隔断部14位于同一层。
例如，如图7所示，采用无机绝缘材料的第一隔断部11a的厚度为
Figure PCTCN2022124631-appb-000002
采用无机绝缘材料的第三隔断部13的子层132的厚度为
Figure PCTCN2022124631-appb-000003
如图7和图9A所示，子层131和绝缘层ILD位于同一层。
如图7和图9C所示，子层132相对于子层131和第四隔断部14内缩设置，以利于隔断发光功能层FL和第二电极E2。
如图7所示，阻挡坝17设置在绝缘层ILD上。
图7所示的显示基板DP2的其他结构可参照图4所示的显示基板DP1的描述，图7所示的显示基板DP2的有益效果也可参照图4所示的显示基板DP1的有益效果，在此不再赘述。例如，对于第一隔断结构11和第一隔断结构12的厚度比较，对于两个第二隔断结构12相对于封装层EPS的设置方式，图7所示的显示基板DP2均可参照图4所示的显示基板DP1的描述。
图10为本公开的实施例提供的显示基板的剖视示意图。图11A为本公开的实施例提供的另一显示基板的剖视示意图。图11B为本公开的实施例提供的另一显示基板的剖视示意图。图11C为本公开的实施例提供的另一显示基板的剖视示意图。图12A为本公开的实施例提供的显示基板的制作流程图。图12B为本公开的实施例提供的显示基板的制作流程图。图13为本公开的实施例提供的显示基板中的多个第二隔断结构的平面示意图。图14为图10所示的显示基板中的第一隔断结构和第一电极的平面示意图。图15为图11A或图11B所示的显示基板中的第一隔断结构和导电结构的平面示意图。图16为图10所示的显示基板中的第一隔断结构的平面示意图。
如图10、图11A、以及图11B所示，显示基板DP3包括第一隔断结构11和第二隔断结构12，第一隔断结构11位于显示区R1，并位于相邻子像素SP之间，第二隔断结构12位于边框区R3。
如图10、图11A、以及图11B所示，第一隔断结构11包括第一隔断部11a和第二隔断部11b，第一隔断部11a与平坦化层PLN位于同一层，采用有机材料制作，第二隔断部11b与第一电极E1位于同一层，采用导电材料制作。
如图10、图11A、以及图11B所示，第二隔断结构12包括第三隔断部13和第四隔断部14，第三隔断部13与平坦化层PLN位于同一层，采用有机材料制作，第四隔断部14与第一电极E1位于同一层，采用导电材料制作。
如图10、图11A、以及图11B所示，第一隔断部11a的厚度大于第二隔断部11b的厚度，第三隔断部13的厚度大于第四隔断部14的厚度。
如图10、图11A、以及图11B所示，发光功能层FL在第一隔断结构11 处被隔断，以避免或减轻发光时的串扰；发光功能层FL在第二隔断结构12处被断开，防止孔周围的水氧沿着发光材料进入显示区R1，提高发光元件的使用寿命。
如图10、图11A、以及图11B所示，第二电极E2在各处连续，没有被隔断，使得第二电极E2具有较小的电阻，利于提高显示基板发光的均一性。
例如，也可以调整构图工艺，使得第二电极E2在第二隔断结构12处被隔断，进一步提高封装效果。该情况下，第二电极E2在第二隔断结构12处被断开，在第一隔断结构11处不被断开，即在第一隔断结构11处连续。
例如，也可以通过调整第一隔断部11a的形状或尺寸，使得第二电极E2在第一隔断结构11处断开，通过调整第三隔断部13的形状或尺寸，使得第二电极E2在第二隔断结构12处断开。在第二电极E2在第一隔断结构11处断开的情况下，第一隔断结构11可以设置缺口，相邻子像素的第二电极E2可以在缺口处彼此相连，以利于施加相同的信号。
当然，也可以采用其他方式来提高封装效果。例如，为了降低第二电极E2(例如，阴极)的断线风险和提高封装层中的无机层的连续性。在隔断结构处，还可以采用二次掩模的方式，增设辅助连接电极以使得不同子像素的第二电极E2相连，或者，也可以使得光耦合层CPL(如图1所示)导电。即，不同子像素的第二电极E2通过导电的光耦合层CPL相连。例如，封装层中的无机层采用化学气相沉积(CVD)方法制作。
例如，如图11A和图11B所示，与图10所示的显示基板DP31相比，显示基板DP32或显示基板DP33还包括导电结构50，导电结构50在衬底基板BS上的正投影与第一隔断结构11在衬底基板BS上的正投影交叠。
如图11B所示，保护层55覆盖导电结构50，避免导电结构50裸露导致信号短接。例如，保护层55可采用无机绝缘材料制作。例如，保护层55的材料可与钝化层的材料相同。
如图10、图11A、以及图11B所示，对于第一隔断结构11，第二隔断部11b具有突出部PR1，突出部PR1相对于第一隔断部11a突出，使得发光功能层FL在突出部PR1处断开。例如，突出部PR1相对于第一隔断部11a的中间缩窄处突出。
如图10、图11A、以及图11B所示，第一隔断部11a在衬底基板BS上的正投影的面积逐渐减小再逐渐增大。
如图10、图11A、以及图11B所示，对于第二隔断结构12，第四隔断部14具有突出部PR2，突出部PR2相对于第三隔断部13突出，使得发光功能层FL在突出部PR2处断开。例如，突出部PR2相对于第一隔断部11a的中间缩窄处突出。
如图10、图11A、以及图11B所示，第三隔断部13在衬底基板BS上的 正投影的面积逐渐减小再逐渐增大。
如图11C所示，在显示基板DP34中，在显示区，第一隔断部11a和平坦化层PLN之间设有连接部61，平坦化层PLN和第一隔断部11a通过连接部61相连。连接部61的厚度小于平坦化层PLN的厚度，连接部61的厚度小于第一隔断部11a的厚度。在一些实施例中，平坦化层PLN的厚度等于第一隔断部11a的厚度。例如，平坦化层PLN、第一隔断部11a、以及连接部61为一体结构。从而，导电结构50的上方可以被较多的平坦化材料覆盖，防止信号短接。
如图12A所示，显示基板的制作方法包括如下步骤。
步骤S11、在绝缘层ILD上形成平坦化薄膜PLF；在平坦化薄膜PLF上形成第一电极E1、第二隔断部11b、第四隔断部14；并形成像素限定图案PDL。
步骤S12、形成光刻胶图形PT1。
步骤S13、以光刻胶图形PT1为掩模，对平坦化薄膜PLF进行构图。
步骤S14、剥离光刻胶图形PT1，形成第一隔断结构11和第二隔断结构12。
在步骤S13中，对平坦化薄膜PLF进行构图包括干刻工艺。
与图12A所示的显示基板的制作方法相比，在图12B所示的显示基板的制作方法中，第一隔断结构11所在的区域用像素定义中间图案PDL0覆盖，干刻时第一隔断结构11所在的区域先刻蚀像素定义中间图案PDL0，再刻蚀平坦化薄膜PLF，可使得刻蚀工艺完成时，导电结构50的上方仍有平坦化层PLN保留，避免导电结构50裸露以避免信号短接。
如图13所示，显示基板包括四个第二隔断结构12。图13示出了第二隔断结构121、第二隔断结构122、第二隔断结构123以及第二隔断结构124。显示基板包括的第二隔断结构12的数量不限于图中所示。
例如，如图15所示，导电结构50包括数据线DT或电源线PL1。数据线DT沿方向Y延伸，电源线PL1沿方向Y延伸。数据线DT或电源线PL1沿方向X排列。
图16示出了第一电极E1和第一隔断结构11。如图14至图16所示，第一隔断结构11呈网状，包括多个开口110，第一电极E1位于开口110中。每个开口110可对应一个子像素。如图14所示，第一隔断结构11围绕发光区R0。在平面图中，第一隔断结构11位于发光区R0外，且与发光区R0具有间隔。
图17为本公开的实施例提供的一种显示基板的剖视示意图。图18A为本公开的实施例提供的另一显示基板的剖视示意图。图18B为本公开的实施例提供的另一显示基板的剖视示意图。图18C为本公开的实施例提供的另一显示基板的剖视示意图。图19A为本公开的实施例提供的显示基板的制作流程 图。图19B为本公开的实施例提供的显示基板的制作流程图。
图17、图18A至图18C示出了显示基板DP4，图17示出了显示基板DP41，图18A示出了显示基板DP42，图18B示出了显示基板DP43，图18C示出了显示基板DP44。
图17所示的显示基板DP41与图10所示的显示基板DP31相比，第一隔断结构11的第二隔断部11b为无机绝缘材料，且第二隔断结构12的第四隔断部14为无机绝缘材料，第二隔断部11b和第四隔断部14均位于钝化层PVX。
图18A所示的显示基板DP42与图11A所示的显示基板DP32相比，第一隔断结构11的第二隔断部11b为无机绝缘材料，且第二隔断结构12的第四隔断部14为无机绝缘材料，第二隔断部11b和第四隔断部14均位于钝化层PVX。
图18B所示的显示基板DP43与图11B所示的显示基板DP33相比，第一隔断结构11的第二隔断部11b为无机绝缘材料，且第二隔断结构12的第四隔断部14为无机绝缘材料，第二隔断部11b和第四隔断部14均位于钝化层PVX。
图18C所示的显示基板DP44与图11C所示的显示基板DP34相比，第一隔断结构11的第二隔断部11b为无机绝缘材料，且第二隔断结构12的第四隔断部14为无机绝缘材料，第二隔断部11b和第四隔断部14均位于钝化层PVX。
在图19A中，在平坦化薄膜PLF上依次形成钝化层PVX、第一电极E1、以及像素限定图案PDL，钝化层PVX包括第二隔断部11b和第四隔断部14。其余步骤可参照图12A的描述。
在图19B中，在平坦化薄膜PLF上依次形成钝化层PVX、第一电极E1、以及像素限定图案PDL，钝化层PVX包括第二隔断部11b和第四隔断部14。其余步骤可参照图12B的描述。
例如，图17、图18A至图18C所示的显示基板DP4中的第二隔断结构12的平面图可参照图13所示，显示基板DP4中的第一隔断结构11的平面图也可以参考图14至图16所示。
例如，在图17、图18A至图18C所示的显示基板DP4中，第一隔断结构11采用绝缘材料制作，第二隔断结构12采用绝缘材料制作，第一隔断部11a和第三隔断部13采用有机绝缘材料，第二隔断部11b和第四隔断部14采用无机绝缘材料。例如，无机绝缘材料包括SiOx、SiNy、或SiOxNy。例如，有机绝缘材料包括树脂，但不限于此。例如，有机绝缘材料包括亚克力、聚对苯二甲酸乙二醇酯、聚酰亚胺、聚酰胺、聚碳酸酯、环氧树脂等中的一种或几种的组合。当然，在其他的实施例中，第二隔断部11b和第四隔断部14也可以采用金属材料或者导电的金属氧化物。
图20为本公开的实施例提供的一种显示基板的剖视示意图。图21为图20所示的显示基板的制作流程图。图22为图20所示的显示基板的边框区内的第二隔断结构的平面图。图23为本公开的实施例提供的显示基板的显示区内的第一隔断结构的平面图。图24为本公开的实施例提供的显示基板的显示区内的第一隔断结构的平面图。图23和图24可为图20所示的显示基板中的第一隔断结构的平面图。
如图20所示，第一隔断结构11和第二隔断结构12不同。第一隔断结构11和第二隔断结构12的材质不同，结构不同。
如图20所示，在第一隔断结构11中，第一隔断部11a和第二隔断部11b均采用有机绝缘材料制作，第一隔断部11a和第二隔断部11b为一体结构。第一隔断部11a和第二隔断部11b与像素限定图案PDL位于同一层。
如图20所示，在第二隔断结构12中，第三隔断部13与绝缘层ILD位于同一层，采用无机绝缘材料制作，第四隔断部14与第一电极E1位于同一层，采用导电材料制作。
例如，如图20所示，发光功能层FL被第一隔断结构11隔断，包括位于第一隔断结构11上的部分和与该部分具有间隔的另一部分。因为发光功能层FL被第一隔断结构11隔断，避免显示基板在发光时产生串扰。
例如，如图20所示，第二电极E2在设置第一隔断结构11的位置被隔断，形成位于第一隔断结构11上的部分和与该部分具有间隔的另一部分。
例如，如图20所示，发光功能层FL被第二隔断结构12隔断，包括位于第二隔断结构12上的部分和与该部分分离的另一部分，以避免水氧沿孔区周围的发光材料进入显示区，利于提高发光元件的寿命。
例如，如图20所示，第二电极E2在设置第二隔断结构12的位置被隔断，形成位于第二隔断结构12上的部分和与该部分分离的另一部分。
如图21所示，显示基板DP5的制作方法包括如下步骤。
步骤101、依次形成导电部61、绝缘薄膜ILL和平坦化层PLN。
步骤102、形成钝化层PVX。
步骤103、形成第一电极E1和第四隔断部14。
步骤104、形成像素限定图案PDL。
步骤105、以像素限定图案PDL和第四隔断部14为掩膜分别对钝化层PVX和绝缘薄膜ILL进行干刻，形成中间钝化层PVX0和中间绝缘层ILL0。
步骤106、对中间钝化层PVX0和中间绝缘层ILL0进行湿法刻蚀，形成第一隔断结构11和第二隔断结构12。
例如，导电部61可以与薄膜晶体管的栅极位于同一层。
例如，如图20和21所示，第二隔断结构12包括两个子隔断结构12S，两个子隔断结构12S的突出部PR2相对设置。
图20所示的显示基板，可有效实现第一隔断结构、第二隔断结构与Tandem工艺的兼容。
图20所示的显示基板DP5中的第一隔断结构11和第二隔断结构12包括同步刻蚀形成的部分，工艺兼容性好。
图22示出了四个第二隔断结构12。第二隔断结构12呈环形围绕孔区R2设置。
如图20和图22所示，第二隔断结构12在衬底基板上的正投影与导电部61在衬底基板上的正投影交叠。进一步例如，第二隔断结构12在衬底基板上的正投影完全落入导电部61在衬底基板上的正投影内。
如图23所示，第一隔断结构11设置在发光元件的发光区R0外侧，第一隔断结构11具有缺口1101，从而，第一隔断结构11为具有缺口1101的环形结构。
例如，因缺口1101的设置，相邻子像素的发光功能层在缺口1101处连续，发光元件的第二电极在缺口1101处连续。
如图23所示，第一电极E1具有主体部E11和连接部E12，主体部E11在衬底基板上的正投影与发光区R0在衬底基板上的正投影交叠，连接部E12被配置为与其他部件相连。例如，连接部E12与薄膜晶体管T0相连。参考图4和图23，连接部E12在衬底基板上的正投影与过孔V0在衬底基板上的正投影交叠。如图23所示，连接部E12位于缺口1101处。
如图23所示，显示基板包括第一子像素201、第二子像素202、第三子像素203以及第四子像素204。例如，第一子像素201和第三子像素203之一为蓝色子像素，第一子像素201和第三子像素203之另一为红色子像素，第二子像素202和第四子像素204可为相同颜色的子像素，例如，均为绿色子像素。第一子像素201、第二子像素202、第三子像素203以及第四子像素204的发光颜色可根据需要而定。
如图23所示，第一子像素201、第二子像素202、第三子像素203以及第四子像素204构成一个重复单元，第二子像素202和第四子像素204位于第一子像素201和第三子像素203的中心连线的两侧，第二子像素202外侧的第一隔断结构11和第四子像素204外侧的第一隔断结构11的开口朝向相同，第一子像素201外侧的第一隔断结构11和第三子像素203外侧的第一隔断结构11开口朝向相同。
如图23所示，第二子像素202外侧的第一隔断结构11和第四子像素204外侧的第一隔断结构11的开口朝向与第一子像素201外侧的第一隔断结构11和第三子像素203外侧的第一隔断结构11开口朝向不同。如图23所示，第二子像素202外侧的第一隔断结构11和第四子像素204外侧的第一隔断结构11的开口朝向与第一子像素201外侧的第一隔断结构11和第三子像素203外 侧的第一隔断结构11开口朝向相反。
如图23所示，第二子像素202外侧的第一隔断结构11和第四子像素204外侧的第一隔断结构11的开口均朝上，第一子像素201外侧的第一隔断结构11和第三子像素203外侧的第一隔断结构11开口均朝下。
例如，如图23所示，第一隔断结构11位于发光区R0的一个角的位置处。例如，发光区R0包括四个角，发光区R0的三个角外均设有第一隔断结构11。例如，第一隔断结构11在衬底基板BS上的正投影至少环绕发光区R0在衬底基板BS上的正投影的二分之一。例如，第一隔断结构11在衬底基板BS上的正投影至少环绕发光区R0在衬底基板BS上的正投影的四分之三。
例如，如图24所示，导电结构50在衬底基板BS上的正投影与第一隔断结构11在衬底基板BS上的正投影交叠。导电结构50包括数据线DT或电源线PL1。数据线DT沿方向Y延伸，电源线PL1沿方向Y延伸。数据线DT或电源线PL1沿方向X排列。
在本公开的实施例中，其他显示基板的第一隔断结构11的下方也可以设置导电结构50，不限于示出导电结构50的附图。导电结构50除了为电源线、数据线等导线外，还可以为其他导线或电容的极板等结构。
图25A为本公开一实施例提供的另一种显示基板的平面示意图。根据本公开的实施例提供的显示基板，如图25A所示，第一隔断结构11呈环形，第一隔断结构11环形设置，以围绕发光区R0，第二电极E2在第一隔断结构11的突出部处连续，以利于不同子像素的第二电极E2上的信号传递。第一隔断结构11的剖视图如之前所示。
如图25A所示，每个子像素SP的发光区R0被一个第一隔断结构11环绕。
图25B为本公开一实施例提供的另一种显示基板的平面示意图。根据本公开的实施例提供的显示基板，如图25B所示，第一隔断结构11包括至少一个隔断子结构01，至少一个隔断子结构01在衬底基板BS上的正投影至少环绕发光区R0在衬底基板BS上的正投影的二分之一。
如图25B所示，每个子像素SP的发光区R0被三个或四个隔断子结构01环绕。隔断子结构01的个数可根据需要而定。
如图25A和图25B所示，显示基板包括第一子像素201、第二子像素202、第三子像素203以及第四子像素204。例如，第一子像素201和第三子像素203之一为蓝色子像素，第一子像素201和第三子像素203之另一为红色子像素，第二子像素202和第四子像素204可为相同颜色的子像素，例如，均为绿色子像素。第一子像素201、第二子像素202、第三子像素203以及第四子像素204的发光颜色可根据需要而定。
例如，如图25A和图25B所示，一个第一子像素201、一个第二子像素 202、一个第三子像素203以及一个第四子像素204构成一个重复单元RP，在一个重复单元RP中，第二子像素202和第四子像素204分设在第一子像素201和第三子像素203的中心连线CL的两侧。图25A和图25B示出了第一子像素201的中心C1和第三子像素203的中心C2。相应的，第一子像素201和第三子像素203也分设在第二子像素202和第四子像素204的中心连线的两侧。
例如，在其他的实施例中，在相邻的两个子像素之间，仅设置有一个隔断结构，从而可减小相邻两个子像素之间的间隔的宽度，以提高像素密度。
图25A和图25B还示出了隔垫物58。隔垫物58被配置为在制作发光层时支撑精细金属掩模。
如所示，隔垫物58在第一子像素201、第二子像素202、第三子像素203、以及第四子像素204围设的区域内。
如图25B所示，在第二方向Y上排列的第一子像素201和第三子像素203之间设置隔垫物58。
一些附图示出了方向X和方向Y。方向X与方向Y相交。例如，方向X垂直于方向Y。方向X与方向Y均为平行于衬底基板的主表面的方向。例如，方向Z垂直于方向X，并垂直于方向Y。
除了图14至图16、图23、图24、图25A、图25B示出的第一隔断结构11的形式外，第一隔断结构11也可以采用其他适合的形式。
图26为本公开的实施例提供的显示基板中的发光元件的示意图。如图26所示，根据本公开的实施例提供的显示基板，发光功能层FL包括层叠设置的电荷产生层40、第一发光层41和第二发光层42，第一发光层41位于第一电极E1和电荷产生层40之间，第二发光层42位于第二电极E2和电荷产生层40之间，电荷产生层40在突出部PR1处断开。因电荷产生层40在第一隔断结构11处断开，使得电荷的传播路径较长，发光功能层中的电荷生成层的电阻较大，能有效避免相邻子像素之间的串扰。
例如，在一些实施例中，除了电荷产生层40在突出部PR1处断开之外，电荷产生层40和第一电极E1之间的子功能层在突出部PR1处也断开，而电荷产生层40和第二电极E2之间的子功能层在突出部PR1处不断开。在另一些实施例中，除了电荷产生层40在突出部PR1处断开之外，电荷产生层40和第一电极E1之间的子功能层在突出部PR1处也断开，而电荷产生层40和第二电极E2之间的子功能层在突出部PR1处也断开，该情况下，发光功能层FL的各个子功能层在突出部PR1处均断开。
如图26所示，根据本公开的实施例提供的显示基板，发光功能层FL还包括位于第一电极E1和第一发光层41之间的第一电荷传输层51以及位于第一发光层41和电荷产生层40之间的第二电荷传输层52，第一电荷传输层51 和第二电荷传输层52在突出部PR1处断开。
如图26所示，第一电荷传输层51为空穴传输层HTL，第二电荷传输层52为电子传输层ETL。其余各个结构可参考图1的描述。
图27为一种显示基板中的像素电路和发光元件的示意图。图27以7T1C的像素电路为例进行说明。需要说明的是，像素电路不限于图27所示，可根据需要设置。如图27所示，显示基板包括子像素SP，子像素包括像素电路PXC和发光元件EMC。发光元件EMC包括第一电极E1、第二电极E2、以及位于第一电极E1和第二电极E2之间的发光功能层。像素电路PXC包括晶体管和存储电容Cst。例如，晶体管包括晶体管T1-T7，存储电容Cst包括极板Ca1和极板Cb1。图27还示出了提供扫描信号SCAN的栅线GT、提供数据信号DATA的数据线DT、提供发光控制信号EM的发光控制信号线EML、提供电源电压VDD的电源线PL1、提供电源电压VSS的电源线PL2、提供复位信号RESET的复位控制信号线RST1、提供扫描信号SCAN的复位控制信号线RST2、提供初始化信号Vinit1的初始化信号线INT1、以及提供初始化信号Vinit2的初始化信号线INT2。
例如，如图27所示，晶体管T1为驱动晶体管，晶体管T2为数据写入晶体管，晶体管T3为阈值补偿晶体管，晶体管T4为发光控制晶体管，晶体管T5为发光控制晶体管，晶体管T6为复位控制晶体管，晶体管T7为复位控制晶体管。
例如，如图13和图22所示，第二隔断结构12呈环形，以围绕孔区R2。
例如，如图4、图5B、图7、和图20所示，第二电极E2在第二隔断结构12的突出部PR2处断开。
例如，如图4、图5A、图10、图11A、图11B、图17、图18A、图18B和图20所示，第二电极E2在突出部PR1处连续。
例如，如图14所示，第一隔断结构11呈环形，围绕发光区连续设置。
例如，如图24所示，第一隔断结构11具有缺口1101。
例如，如图4和图7所示，第一隔断部11a在垂直于衬底基板BS的方向上的尺寸小于第二隔断部11b在垂直于衬底基板BS的方向上的尺寸。
例如，如图10、图11A至图11C、图17、图18A至图18C、以及图20所示，第一隔断部11a在垂直于衬底基板BS的方向上的尺寸大于第二隔断部11b在垂直于衬底基板BS的方向上的尺寸。
例如，如图4和图7所示，第一隔断部11a在垂直于衬底基板BS的方向上的尺寸小于第三隔断部13在垂直于衬底基板BS的方向上的尺寸。
例如，如图4、图7、图10、图11A至图11C、图17、以及图18A至图18C所示，第二隔断部11b与第四隔断部14位于同一层。
例如，如图20所示，第二隔断部11b与第四隔断部14位于不同层，采 用不同的材料制作。
例如，如图10、图11A至图11C、图17、以及图18A至图18C所示，第一隔断结构11和第二隔断结构12具有相同的层结构。
例如，如图4、图7、以及图20所示，第一隔断结构11和第二隔断结构12具有不同的层结构。
例如，如图4和图7所示，第一隔断部11a包括的膜层的个数小于或等于第三隔断部13包括的膜层的个数。
例如，如图4所示，第一隔断结构11的材料包括导电材料，第二隔断结构12的材料包括导电材料。例如，导电材料包括金属和导电的金属氧化物。
例如，如图7所示，第一隔断结构11的材料包括无机绝缘材料，第二隔断结构12的材料包括无机绝缘材料。
例如，如图10、图11A至图11C、图17、以及图18A至图18C所示，第一隔断部11a和第二隔断部11b的材料不同，第三隔断部13和第四隔断部14的材料不同，第一隔断部11a和第三隔断部13的材料相同，第二隔断部11b和第四隔断部14的材料相同。
例如，如图17、以及图18A至图18C所示，第一隔断部11a和第三隔断部13的材料包括有机材料，第二隔断部11b和第四隔断部14的材料包括无机绝缘材料。
例如，如图10、图11A至图11C所示，第一隔断部11a和第三隔断部13的材料包括有机绝缘材料，第二隔断部11b和第四隔断部14的材料包括导电材料。
例如，如图20所示，第一隔断部11a的材料包括有机绝缘材料，第二隔断部11b的材料包括有机绝缘材料，第三隔断部13的材料包括无机绝缘材料，第四隔断部14的材料包括导电材料。
例如，如图20所示，第一隔断部11a和第二隔断部11b为一体结构。
例如，如图4、图7、图10、图11A至图11C、图17、以及图18A至图18C所示，第二隔断部11b的材料与第一隔断部11a的材料不同。
例如，在本公开的实施例中，无机绝缘材料包括SiOx、SiNy、或SiOxNy。例如，导电材料包括金属或导电的金属氧化物。例如，有机绝缘材料包括亚克力、聚对苯二甲酸乙二醇酯、聚酰亚胺、聚酰胺、聚碳酸酯、环氧树脂等中的一种或几种的组合。
例如，如图20所示，第二隔断结构12设置为多个，第二隔断结构12还包括第五隔断部15，第五隔断部15的材料包括导电材料，多个第二隔断结构12的第五隔断部15为一体结构，多个第四隔断部14围绕孔区R2依次设置。导电部61即为第五隔断部15。
例如，如图4、图7、图10、图11A至图11C、图17、图18A至图18C 以及图20所示，第一隔断结构11呈T字型。
例如，第二电极E2为发光元件的阴极，第一电极E1为发光元件的阳极。在一些实施例中，显示基板形成共阴极的结构。在第二电极E2为整面的连续电极，不被隔断结构断开的情况下，利于减小第二电极E2的电阻，利于第二电极E2上的信号传递。
例如，在本公开的实施例中，不同子像素的第一电极E1彼此绝缘，不同子像素的第一电极E1彼此独立设置，可被施加不同的信号。不同子像素的第二电极E2彼此相连，可被施加相同的信号。
在本公开的实施例中，对于位于边框区的第二隔断结构12，图4和图7中以位于阻挡坝17两侧的第二隔断结构12的结构相同为例进行说明。在另一些实施例中，位于阻挡坝17两侧的第二隔断结构12的结构也可以不相同，从而，使得第二电极E2在阻挡坝17的外侧(图中阻挡坝17的左侧)被隔断，而在阻挡坝17的内侧(图中阻挡坝17的右侧)不被隔断，或者，使得第二电极E2在阻挡坝17的外侧(图中阻挡坝17的左侧)不被隔断，而在阻挡坝17的内侧(图中阻挡坝17的右侧)被隔断。
根据实际需要，第一隔断结构11和第二隔断结构12对第二电极E2的隔断，均可以通过控制工艺条件，或者增加工艺来实现。第二电极E2在第一隔断结构11或第二隔断结构12处是否被隔断，也可以通过调整工艺来实现。
例如，如图4和图7所示，第一隔断结构11在垂直于衬底基板BS的方向上的厚度小于平坦化层PLN在垂直于衬底基板BS的方向上的厚度。
例如，如图10、图11A至图11C、图17、图18A至图18C所示，第一隔断结构11在垂直于衬底基板BS的方向上的最大厚度小于平坦化层PLN在垂直于衬底基板BS的方向上的最大厚度。
例如，如图10、图11A至图11C、图17、图18A至图18C所示，第一隔断结构11在垂直于衬底基板BS的方向上的最大厚度小于平坦化层PLN在垂直于衬底基板BS的方向上的最大厚度。
例如，如图20所示，第一隔断结构11在垂直于衬底基板BS的方向上的最大厚度等于像素限定图案PDL在垂直于衬底基板BS的方向上的最大厚度。
例如，如图10、图11A至图11C、图17、图18A至图18C所示，第一隔断部11a的侧面呈弧形，过渡比较平缓，利于第二电极E2设置在第一隔断部11a的侧面上。第二电极E2的材料通常为金属或合金，金属或合金具有较好的爬坡性能。在其他的实施例中，也可以调整第一隔断部11a的侧面形状。
例如，有机材料包括树脂，但不限于此。例如，有机材料包括亚克力或聚对苯二甲酸乙二醇酯、聚酰亚胺、聚酰胺、聚碳酸酯、环氧树脂等中的一种或几种的组合。
本公开的一些实施例提供的显示基板，可有效实现第一隔断结构与第二 隔断结构可同步刻蚀，工艺兼容性好。
本公开的一些实施例提供的显示基板，第一隔断结构与第二隔断结构可在背板工艺全部完成后再经刻蚀形成，无涂胶孔晕等风险。
例如，在本公开的实施例中，位于同一层的部件可由同一膜层经同一构图工艺形成。在本公开的实施例中，构图或构图工艺可只包括光刻工艺，或包括光刻工艺以及刻蚀步骤，或者可以包括打印、喷墨等其他用于形成预定图形的工艺。光刻工艺是指包括成膜、曝光、显影等工艺过程，利用光刻胶、掩模板、曝光机等形成图形。可根据本公开的实施例中所形成的结构选择相应的构图工艺。
例如，在本公开的实施例中，一个部件的厚度是指该部件在垂直于衬底基板的方向上的尺寸。
例如，在本公开的实施例中，衬底基板BS、缓冲层BF、绝缘层GI1、绝缘层GI2、绝缘层ILD、平坦化层PLN、隔垫物PS均采用绝缘材料制作。例如，衬底基板BS的材料包括聚酰亚胺，但不限于此。例如，缓冲层BF、绝缘层GI1、绝缘层GI2、绝缘层ILD的材料包括无机绝缘材料。例如，平坦化层PLN、像素限定图案PDL、隔垫物PS的材料包括有机绝缘材料。例如，无机绝缘材料包括氧化硅、氮化硅、氮氧化硅至少之一。例如，有机绝缘材料包括亚克力、聚对苯二甲酸乙二醇酯、聚酰亚胺、聚酰胺、聚碳酸酯、环氧树脂等中的一种或几种的组合。
例如，绝缘层GI1也可称作栅绝缘层，绝缘层GI2也可称栅绝缘层，绝缘层ILD也可称作层间绝缘层。
在本公开的附图中，若图的左侧示出了(a)，图的右侧示出了(b)，则，(a)表示位于显示区，(b)表示位于边框区。
本公开的实施例还提供一种显示装置，包括上述任一显示基板。
图28为本公开一实施例提供的一种显示装置的示意图。如图28所示，该显示装置500包括显示基板100。显示基板100即为上述任一的显示基板。本公开的实施例中提及的显示基板，也可以称作显示面板。例如，显示基板可为柔性显示基板，但不限于此。
一方面，该显示基板(显示面板)通过在相邻的子像素之间设置隔断结构，并使得发光功能层中的至少一个子功能层，例如，电荷产生层，在隔断结构所在的位置断开，从而避免导电性较高的子功能层(例如，电荷产生层)造成相邻子像素之间的串扰。由此，包括该显示基板的显示装置因此也可避免相邻子像素之间的串扰，因此具有较高的产品良率和较高的显示品质。
另一方面，由于显示基板可在采用Tandem结构，以提高像素密度。因此，包括该显示基板的显示装置具有寿命长、功耗低、亮度高、分辨率高等优点。
例如，该显示装置可以为有机发光二极管显示装置等显示器件以及包括该显示装置的电视、数码相机、手机、手表、平板电脑、笔记本电脑、导航仪等任何具有显示功能的产品或者部件，本公开的实施例包括但不限于此。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (28)

  1. 一种显示基板，包括：
    衬底基板，包括孔区、显示区以及位于所述孔区和所述显示区之间的边框区；
    多个子像素，位于所述显示区，所述子像素包括发光元件，所述发光元件具有发光区，所述发光元件包括第一电极、发光功能层、以及第二电极，所述第二电极位于所述发光功能层的背离所述衬底基板的一侧，所述第一电极位于所述发光功能层的靠近所述衬底基板的一侧，所述发光功能层包括多个子功能层；
    第一隔断结构，位于所述显示区，并包括层叠设置的第一隔断部和第二隔断部，所述第一隔断部位于所述第二隔断部的靠近所述衬底基板的一侧；以及
    第二隔断结构，位于所述边框区，并包括层叠设置的第三隔断部和第四隔断部，所述第三隔断部位于所述第四隔断部的靠近所述衬底基板的一侧；
    其中，所述第二隔断部具有第一突出部，所述第一突出部相对于所述第一隔断部突出，所述发光功能层的至少一个子功能层在所述第一突出部处断开，
    所述第四隔断部具有第二突出部，所述第二突出部相对于所述第三隔断部突出，所述发光功能层的至少一个子功能层在所述第二突出部处断开；
    所述第一隔断结构围绕所述发光区；
    所述第二隔断结构呈环形，以围绕所述孔区。
  2. 根据权利要求1所述的显示基板，其中，所述第二电极在所述第一突出部处连续，所述第一隔断结构环形设置。
  3. 根据权利要求1或2所述的显示基板，其中，所述第一隔断结构呈环形，连续设置。
  4. 根据权利要求1-3任一项所述的显示基板，其中，所述第一隔断结构具有缺口，所述第一电极具有主体部和连接部，所述主体部在所述衬底基板上的正投影与所述发光区在所述衬底基板上的正投影交叠，所述连接部位于所述缺口处。
  5. 根据权利要求1-4任一项所述的显示基板，还包括封装层，其中，所述封装层包括第一封装层、第二封装层和第三封装层，所述第一封装层、所述第二封装层和所述第三封装层依次设置，所述第一封装层比所述第三封装层更靠近所述衬底基板，所述第一封装层和所述第三封装层具有叠层接触部，所述第二隔断结构设置为多个，多个第二隔断结构中的一个在所述衬底基板上的正投影与所述第二封装层在所述衬底基板上的正投影交叠，所述多个第二隔断结构中的另一个在所述衬底基板上的正投影与所述叠层接触部在所述 衬底基板上的正投影交叠。
  6. 根据权利要求1-5任一项所述的显示基板，还包括阻挡坝，其中，所述阻挡坝位于所述边框区，所述第二隔断结构包括位于所述阻挡坝的两侧的多个第二隔断结构。
  7. 根据权利要求1-6任一项所述的显示基板，其中，所述第二隔断部的厚度大于所述第一隔断部的厚度。
  8. 根据权利要求1-7任一项所述的显示基板，其中，所述第一隔断部与所述第二隔断部的厚度之比大于或等于0.25，并且小于或等于1。
  9. 根据权利要求1-8任一项所述的显示基板，其中，所述第一隔断部在垂直于所述衬底基板的方向上的尺寸小于所述第三隔断部在垂直于所述衬底基板的方向上的尺寸。
  10. 根据权利要求1-9任一项所述的显示基板，其中，所述第二隔断部和所述第四隔断部位于同一层。
  11. 根据权利要求1-10任一项所述的显示基板，其中，所述第一隔断结构和所述第二隔断结构具有相同的层结构。
  12. 根据权利要求1-10任一项所述的显示基板，其中，所述第一隔断部包括的膜层的个数小于或等于所述第三隔断部包括的膜层的个数。
  13. 根据权利要求1-12任一项所述的显示基板，其中，所述第一隔断结构的材料包括导电材料，所述第二隔断结构的材料包括导电材料。
  14. 根据权利要求13所述的显示基板，其中，所述导电材料包括金属和导电的金属氧化物。
  15. 根据权利要求14所述的显示基板，其中，所述第二隔断部和所述第四隔断部位于同一层，所述第三隔断部包括与所述第一隔断部位于同一层的部分。
  16. 根据权利要求1-12任一项所述的显示基板，其中，所述第一隔断结构的材料包括无机绝缘材料，所述第二隔断结构的材料包括无机绝缘材料。
  17. 根据权利要求1-12任一项所述的显示基板，其中，所述第一隔断部和所述第二隔断部的材料不同，所述第三隔断部和所述第四隔断部的材料不同，所述第一隔断部和所述第三隔断部的材料相同，所述第二隔断部和所述第四隔断部的材料相同。
  18. 根据权利要求1-12任一项所述的显示基板，其中，所述第一隔断部和所述第三隔断部的材料包括有机材料，所述第二隔断部和所述第四隔断部的材料包括无机绝缘材料。
  19. 根据权利要求1-12任一项所述的显示基板，其中，所述第一隔断部和所述第三隔断部的材料包括有机绝缘材料，所述第二隔断部和所述第四隔断部的材料包括导电材料。
  20. 根据权利要求1-12任一项所述的显示基板，其中，所述第一隔断部的材料包括有机绝缘材料，所述第二隔断部的材料包括有机绝缘材料，所述第三隔断部的材料包括无机绝缘材料，所述第四隔断部的材料包括导电材料。
  21. 根据权利要求20所述的显示基板，其中，所述第一隔断部和所述第二隔断部为一体结构。
  22. 根据权利要求20或21所述的显示基板，其中，所述第二隔断结构包括两个子隔断结构，所述两个子隔断结构的第二突出部相对设置。
  23. 根据权利要求20-22任一项所述的显示基板，其中，所述第二隔断结构设置为多个，所述第二隔断结构还包括第五隔断部，所述第五隔断部的材料包括导电材料，多个第二隔断结构的第五隔断部为一体结构，多个第四隔断部围绕所述孔区依次设置。
  24. 根据权利要求1-23任一项所述的显示基板，还包括导电结构，其中，所述导电结构在所述衬底基板上的正投影与所述第一隔断结构在所述衬底基板上的正投影交叠。
  25. 根据权利要求24所述的显示基板，其中，所述导电结构包括数据线或电源线。
  26. 根据权利要求1-25任一项所述的显示基板，其中，所述第一隔断结构呈T字型。
  27. 根据权利要求1-26任一项所述的显示基板，其中，所述隔断结构包括至少一个隔断子结构，所述至少一个隔断子结构在所述衬底基板上的正投影至少环绕所述发光区在所述衬底基板上的正投影的二分之一。
  28. 一种显示装置，包括权利要求1-27任一项所述的显示基板。
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