WO2023098293A1 - 显示基板及其制作方法和显示装置 - Google Patents

显示基板及其制作方法和显示装置 Download PDF

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Publication number
WO2023098293A1
WO2023098293A1 PCT/CN2022/124368 CN2022124368W WO2023098293A1 WO 2023098293 A1 WO2023098293 A1 WO 2023098293A1 CN 2022124368 W CN2022124368 W CN 2022124368W WO 2023098293 A1 WO2023098293 A1 WO 2023098293A1
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WIPO (PCT)
Prior art keywords
partition
light
layer
electrode
display substrate
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PCT/CN2022/124368
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English (en)
French (fr)
Inventor
秦成杰
张微
王本莲
龙跃
黄炜赟
辛燕霞
贺伟
李雪萍
杨小飞
郭晓亮
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Publication of WO2023098293A1 publication Critical patent/WO2023098293A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass

Definitions

  • Embodiments of the present disclosure relate to a display substrate, a manufacturing method thereof, and a display device.
  • OLED organic light-emitting diode
  • organic light emitting diode display devices have been widely used in various electronic products, ranging from small electronic products such as smart bracelets, smart watches, smart phones, and tablet computers to large electronic products such as notebook computers, desktop computers, and televisions. Therefore, the market demand for active matrix organic light emitting diode display devices is also increasing.
  • Embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device.
  • An embodiment of the present disclosure provides a display substrate, including: a base substrate; a plurality of sub-pixels located on the main surface of the base substrate, the sub-pixels include a light-emitting element, the light-emitting element has a light-emitting area, the The light-emitting element includes a first electrode, a light-emitting functional layer, and a second electrode, the second electrode is located on the side of the light-emitting functional layer away from the base substrate, and the first electrode is located on the side of the light-emitting functional layer
  • the light-emitting functional layer includes a plurality of sub-functional layers; and an isolation structure, located between the light-emitting regions of adjacent sub-pixels, and includes a first isolation part and a second isolation part stacked , the first partition is located on a side of the second partition that is close to the base substrate; the second partition has a protruding portion, and the protruding portion is relatively close to the first partition.
  • the material of the first partition includes an organic material
  • the material of the second partition Comprising organic materials, along the direction from the first electrode to the second electrode, the orthographic projection of the isolation structure on the base substrate gradually decreases and then gradually increases.
  • the second partition is in contact with the first partition.
  • the partition structure is in the shape of a gourd or an hourglass.
  • the partition structure includes a bottom surface, a top surface, and two sides located between the bottom surface and the top surface, the sides are V-shaped, and the two V-shaped Bottom relative setting.
  • the angle between the side of the first partition and the side of the second partition is greater than or equal to 60 degrees and less than or equal to equals 150 degrees.
  • the angle between the top surface of the second partition portion close to the top surface of the partition structure and the top surface is an acute angle, and the acute angle is greater than or equal to 60 degrees and Less than or equal to 80 degrees.
  • the angle between the top surface of the second partition portion close to the top surface of the partition structure and the top surface is an obtuse angle, and the obtuse angle is greater than 110 degrees and less than or It is equal to 160 degrees.
  • the display substrate further includes: a pixel defining pattern including a plurality of openings configured to define the light emitting regions of the sub-pixels, the openings configured to expose the At least a part of the first electrode, the pixel defining pattern includes a part located in the same layer as the first partition part.
  • the pixel defining pattern is at least partially separated from the first partition, and both the pixel defining pattern and the first partition are in contact with the same insulating layer and located on the insulating layer. above.
  • the pixel definition pattern includes a first pixel definition part and a second pixel definition part between two adjacent openings, and the partition structure is located at the first pixel definition part. Between the partition structure and the second pixel defining portion, there is a first depression between the isolation structure and the first pixel defining portion, and there is a second depression between the isolation structure and the second pixel defining portion.
  • the orthographic projection of the protrusion on the base substrate at least partially overlaps the orthographic projection of the first electrode on the base substrate.
  • the pixel-defining pattern is integrated with the isolation structure.
  • the material of the first partition includes a positive photoresist
  • the material of the second partition includes a negative photoresist
  • the luminescent functional layer includes a stacked charge generation layer, a first luminescent layer, and a second luminescent layer, and the first luminescent layer is located between the first electrode and the charge generation layers, the second light emitting layer is located between the second electrode and the charge generation layer, and the charge generation layer is disconnected at the protruding portion.
  • the light emitting functional layer further includes a first charge transport layer located between the first electrode and the first light emitting layer, and a charge transport layer located between the first light emitting layer and the first light emitting layer.
  • a second charge transport layer between the charge generation layer, the first charge transport layer and the second charge transport layer are disconnected at the protrusion.
  • the partition structure includes at least one partition substructure, and the orthographic projection of the at least one partition substructure on the substrate substrate at least surrounds the light emitting region on the substrate One-half of the orthographic projection on the substrate.
  • the partition structure is ring-shaped to surround the light emitting area, and the second electrode is continuous at the protruding portion.
  • the display substrate further includes a pixel circuit configured to drive the light-emitting element to emit light
  • the display substrate further includes a planarization layer
  • the first electrode passes through the The via hole in the planarization layer is connected to the pixel circuit, and the first electrode and the first partition are located on the planarization layer.
  • both the first electrode and the first partition part are in contact with the planarization layer.
  • the pixel circuit includes a capacitor, and the orthographic projection of the capacitor on the base substrate and the orthographic projection of the partition structure on the base substrate at least partially overlap .
  • the display substrate further includes a conductive structure configured to provide a signal to the pixel circuit, and the conductive structure is located between the partition structure and the base substrate , the orthographic projection of the conductive structure on the base substrate overlaps with the orthographic projection of the isolation structure on the base substrate.
  • the conductive structure is located between light emitting regions of adjacent sub-pixels, and the conductive structure is electrically connected to the second electrode.
  • the smallest dimension of the isolation structure in a plane parallel to the main surface is greater than the distance between the first electrodes of adjacent sub-pixels.
  • the maximum dimension of the partition structure in a plane parallel to the main surface is greater than or equal to one-fifth of the distance between the first electrodes of adjacent sub-pixels.
  • An embodiment of the present disclosure also provides a display device, including any one of the above display substrates.
  • An embodiment of the present disclosure also provides a method for manufacturing a display substrate, including: forming a plurality of sub-pixels on the main surface of the base substrate, the sub-pixels include a light-emitting element, the light-emitting element has a light-emitting region, and the light-emitting element It includes a first electrode, a light-emitting functional layer, and a second electrode, the second electrode is located on the side of the light-emitting functional layer away from the base substrate, and the first electrode is located on the side of the light-emitting functional layer close to the One side of the base substrate, the light-emitting functional layer includes a plurality of sub-functional layers; and a partition structure is formed between the light-emitting regions of adjacent sub-pixels, and the formation of the partition structure includes forming a stacked first partition and a second partition.
  • the first partition is located on a side of the second partition close to the base substrate; the second partition has a protrusion, and the protrusion is opposite to the first partition
  • the side close to the second partition protrudes, at least one sub-functional layer of the light-emitting functional layer is disconnected at the protruding part
  • the material of the first partition includes an organic material
  • the second partition The material of the part includes an organic material, and along the direction from the first electrode to the second electrode, the orthographic projection of the partition structure on the base substrate gradually decreases and then gradually increases.
  • forming the first partition and the second partition provided in a stack includes: forming a positive photoresist film; forming a negative photoresist film on the positive photoresist film; positive photoresist film; patterning the negative photoresist film to form the second partition; and using the second partition as a mask to pattern the positive photoresist film to form the Describe the first partition.
  • FIG. 1 is a schematic diagram of a light emitting element.
  • FIG. 2 is a schematic diagram of a display substrate.
  • FIG. 3 is a cross-sectional view of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 4 is an enlarged view of the partition structure in FIG. 3 .
  • FIG. 5 is a cross-sectional view of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 6 is an enlarged view of the partition structure in FIG. 5 .
  • FIG. 7 is a cross-sectional view of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 8 is an enlarged view of the partition structure in FIG. 7 .
  • FIG. 9A is a schematic diagram of an isolation structure of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 9B is a schematic diagram of an isolation structure of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of light emitting elements in a display substrate provided by an embodiment of the present disclosure.
  • FIG. 11 is a schematic plan view of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 12 is a schematic plan view of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of a pixel circuit and a light emitting element in a display substrate.
  • FIG. 14A is a schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 14B is a schematic diagram of a display substrate provided by another embodiment of the present disclosure.
  • FIG. 15 is a schematic diagram of a display device provided by an embodiment of the present disclosure.
  • 16A to 16D are schematic diagrams of a manufacturing method of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 17A is a schematic cross-sectional view of a negative photoresist after exposure and development.
  • 17B is a schematic cross-sectional view of the positive photoresist after exposure and development.
  • 18A to 18C are schematic diagrams of a manufacturing method of a display substrate provided by an embodiment of the present disclosure.
  • one light-emitting layer in the light-emitting element in the OLED display panel can be replaced by two light-emitting layers, and a charge generation layer (CGL) is added between the two light-emitting layers, using N /P-CGL is used as a heterojunction to connect two light-emitting device structures in series to form a double-stack design, forming a Tandem structure.
  • the display substrate of the Tandem structure realizes the series connection of two light-emitting devices, which greatly reduces the light emission under the same luminous intensity.
  • a display device with a Tandem structure has the advantages of long life, low power consumption, and high brightness.
  • FIG. 1 is a schematic diagram of a light emitting element.
  • Fig. 1(a) is a schematic diagram of a general light-emitting element.
  • Fig. 1(b) is a schematic diagram of a light-emitting element with a Tandem structure. As shown in Figure 1(b), the charge generation layer (CGL) between different light-emitting elements of the Tandem structure is connected.
  • CGL charge generation layer
  • Figure 1 shows a first electrode E1, a second electrode E2, a hole transport layer HTL, an electron transport layer ETL, an optical coupling layer CPL, an anti-reflection layer ARL, a P-type doped charge generation layer P-CGL, an N-type Doped charge generation layer N-CGL, light emitting layer R, light emitting layer G, light emitting layer B.
  • the luminescent layer R includes two sublayers respectively containing luminescent material R1 and luminescent material R2
  • the luminescent layer G includes two sublayers respectively containing luminescent material G1 and luminescent material G2
  • the luminescent layer B contains luminescent material B1 and luminescent material B2.
  • the luminescent material R1 and the luminescent material R2 are two different materials that emit red light
  • the luminescent material G1 and the luminescent material G2 are two different materials that emit green light
  • the luminescent material B1 and the luminescent material B2 are two different materials that emit blue light. s material.
  • FIG. 2 is a schematic diagram of a display substrate.
  • the display substrate includes a planarization layer PLN1 , a planarization layer PLN2 , a pixel definition layer PDL, an electrode E1 , a light emitting function layer FL, an electrode E2 and an encapsulation layer EPS.
  • Fig. 1 shows the light emitting element EM01 and the light emitting element EM02, the charge generation layer (CGL) of the light emitting element EM01 and the light emitting element EM02 can be an integral structure, which is fabricated by using an open mask.
  • CGL charge generation layer
  • the inventor has noticed that for high-resolution products, since the charge generation layer has strong conductivity, the light-emitting functional layer of the adjacent sub-pixel (herein refers to the layer comprising two light-emitting layers and the charge generation layer) The film layer) is connected, so the charge generation layer is likely to cause crosstalk between adjacent sub-pixels, affecting the image quality of the product, thereby seriously affecting the display quality.
  • crosstalk between adjacent sub-pixels refers to a situation where a light-emitting element that should not emit light emits light. As shown in FIG. 2, if the desired situation is that the light-emitting element EM01 emits light, but the light-emitting element EM02 does not emit light, but due to the conductivity of the charge generation layer, the light-emitting element EM02 also emits light, thereby forming crosstalk.
  • FIG. 3 is a cross-sectional view of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 4 is an enlarged view of the partition structure in FIG. 3 .
  • FIG. 5 is a cross-sectional view of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 6 is an enlarged view of the partition structure in FIG. 5 .
  • FIG. 7 is a cross-sectional view of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 8 is an enlarged view of the partition structure in FIG. 7 .
  • FIG. 9A is a schematic diagram of an isolation structure of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 9B is a schematic diagram of an isolation structure of a display substrate provided by an embodiment of the present disclosure.
  • an embodiment of the present disclosure provides a display substrate including: a base substrate BS, a plurality of sub-pixels SP, and an isolation structure 10 .
  • a plurality of sub-pixels SP are located on the main surface SF0 of the base substrate BS, the sub-pixels SP include a light emitting element EMC, and the light emitting element EMC has a light emitting region R0.
  • FIG. 7 also shows the light emitting element EMC and the light emitting region R0.
  • the light emitting element EMC includes a first electrode E1, a light emitting functional layer FL, and a second electrode E2, and the second electrode E2 is located on the side of the light emitting functional layer FL away from the base substrate BS , the first electrode E1 is located on the side of the light-emitting functional layer FL close to the base substrate BS, and the light-emitting functional layer FL includes a plurality of sub-functional layers.
  • the first electrode E1 is made of conductive material.
  • the material of the first electrode E1 includes metal and conductive metal oxide.
  • the first electrode E1 adopts a stacked structure of indium tin oxide (ITO), silver (Ag), and indium tin oxide (ITO). The material and structure of the first electrode E1 can be set as required.
  • the second electrode E2 is made of conductive material.
  • the material of the second electrode E2 includes metal or alloy.
  • the material of the second electrode E2 includes Mg/Ag alloy. The material and structure of the second electrode E2 can be set as required.
  • the second electrodes E2 of different sub-pixels are electrically connected to facilitate providing the same voltage signal.
  • the isolation structure 10 is located between the light-emitting regions R0 of adjacent sub-pixels SP, and includes a first isolation part 11 and a second isolation part 12 arranged in layers.
  • the first isolation part 11 Located on the side of the second partition 12 close to the base substrate BS; the second partition 12 has a protruding part PR, and the protruding part PR protrudes from the first partition 11, for example, the protruding part PR relative to the first partition 11
  • the side close to the second partition 12 protrudes; at least one sub-functional layer of the light-emitting functional layer FL is disconnected at the protruding part PR, along the direction from the first electrode E1 to the second electrode E2, the partition structure 10 is on the substrate
  • the orthographic projection on the substrate BS gradually decreases and then gradually increases.
  • the direction from the first electrode E1 to the second electrode E2 is the direction Z.
  • the structure of the partition structure 10 narrowed first and then widened is beneficial to partition at least one
  • the protruding portion PR protrudes relative to the top surface of the first partition portion 11 .
  • one element breaking at the protrusion PR includes breaking at the side of the protrusion PR.
  • the material of the first partition 11 includes an organic material
  • the material of the second partition 12 includes an organic material.
  • organic materials include resins, but are not limited thereto.
  • the organic material includes one or a combination of acrylic or polyethylene terephthalate, polyimide, polyamide, polycarbonate, epoxy resin, and the like.
  • the material of the first partition 11 may include photoresist
  • the material of the second partition 12 may include photoresist.
  • the material of the second partition 12 is different from that of the first partition 11 .
  • the cross-section of the second partition 12 is an inverted trapezoid, but not limited thereto, and the cross-section of the second partition 12 can also adopt other suitable shapes.
  • the plurality of sub-pixels SP includes a sub-pixel SP1 and a sub-pixel SP2 .
  • the sub-pixel SP1 and the sub-pixel SP2 are two adjacent sub-pixels.
  • the number of sub-pixels disposed on the display substrate is not limited to what is shown in the figure, and can be determined according to needs.
  • the number of sub-functional layers included in the light-emitting functional layer FL can be set as required.
  • a partition structure can be provided between adjacent sub-pixels, and at least one of the multiple sub-functional layers in the light-emitting functional layer is disconnected at the position where the partition structure is located, Increase the resistance of the sub-functional layer with higher conductivity in the light-emitting functional layer FL, thereby reducing the crosstalk between adjacent sub-pixels caused by the film layer with higher conductivity in the multiple sub-functional layers.
  • the isolation structure 10 is formed after the formation of the first electrode E1 , without changing the backplane structure of the display substrate, and there is no risk of glue-coated holes or halos.
  • the partition structure 10 is disposed between the first electrodes E1 of the light emitting element, so that the partition structure 10 has a larger installation space, which is beneficial to install partition structures 10 of different structures.
  • the partition structure 10 is hourglass-shaped. As shown in Figure 7, the partition structure 10 is gourd-shaped or inverted gourd-shaped. The size of one end of the base substrate BS and an end away from the base substrate BS is larger than that at the narrowed position of the partition structure 10 .
  • the isolation structure 10 may be disposed between sub-pixels in the display area of the display substrate.
  • the partition structure 10 includes a bottom surface SF1, a top surface SF2, and two side surfaces SF3 between the bottom surface SF1 and the top surface SF2.
  • the SF3 is V-shaped, and the bottoms of the two Vs are opposite to each other.
  • the display substrate further includes: a pixel definition pattern PDL including a plurality of openings OPN configured to limit the light emission of the sub-pixel SP
  • the region R0, the opening OPN is configured to expose at least a portion of the first electrode E1.
  • the pixel defining pattern PDL is located on the same layer as the first partition portion 11 .
  • two elements located in the same layer means that the two elements are patterned by the same film layer.
  • the pixel defining pattern PDL is at least partially separated from the first partition 11 , and both the pixel defining pattern PDL and the first partition 11 are in contact with the same insulating layer. and on top of this insulating layer. 3 to 6 show that both the pixel defining pattern PDL and the first partition 11 are in contact with the planarization layer PLN and are located on the planarization layer PLN.
  • the pixel definition pattern PDL includes a first pixel definition portion PDL1 and a second pixel definition portion PDL2 located between two adjacent openings OPN, and the partition
  • the structure 10 is located between the first pixel defining portion PDL1 and the second pixel defining portion PDL2, there is a first recess RC1 between the partition structure 10 and the first pixel defining portion PDL1, and there is a recess RC1 between the partition structure 10 and the second pixel defining portion PDL2.
  • the first recess RC1 and the second recess RC2 are filled with the encapsulation layer EPS.
  • the encapsulation layer EPS includes a first encapsulation layer EPS1 , a second encapsulation layer EPS2 , and a third encapsulation layer EPS3 .
  • the first encapsulation layer EPS1 and the third encapsulation layer EPS3 are inorganic layers and can be formed by a chemical vapor deposition (CVD) process.
  • the second encapsulation layer EPS2 is an organic layer, which can be formed by an inkjet printing process.
  • the thickness of the second encapsulation layer EPS2 is greater than the thickness of the first encapsulation layer EPS1 .
  • the thickness of the second encapsulation layer EPS2 is greater than the thickness of the third encapsulation layer EPS3 .
  • the encapsulation layer EPS covers the entire display substrate and is well covered at the isolation structure to prevent the light-emitting element from being corroded by water and oxygen.
  • the partition structure 10 provided by the embodiments of the present disclosure can not only effectively partition at least one sub-functional layer in the light-emitting functional layer, but also does not affect the thin-film packaging effect of the packaging layer.
  • the partition structure 10 provided by the embodiments of the present disclosure does not affect the film-forming uniformity of the encapsulation layer EPS, avoids the discontinuous film-formation problem of the encapsulation layer, and prevents the light-emitting element from being ineffective due to water vapor intrusion.
  • the partition structure 10 is located between the first pixel defining portion PDL1 and the second pixel defining portion PDL2, and has intervals from the first pixel defining portion PDL1 and the second pixel defining portion PDL2, the protruding
  • the orthographic projection of the portion PR on the base substrate BS does not overlap with the orthographic projection of the first electrode E1 on the base substrate BS.
  • the angle A2 between the portion of the second partition portion 12 close to the top surface SF2 of the partition structure 10 and the top surface SF2 is an acute angle, for example, the acute angle A2 is greater than or equal to 60 degrees and Less than or equal to 80 degrees.
  • the thickness of the second partition portion 12 is greater than half of the thickness of the first partition portion 11 and less than or equal to the thickness of the first partition portion 11 .
  • the thickness of the second partition portion 12 is smaller than the thickness of the first partition portion 11 .
  • the side of the first partition 11 and the side of the second partition 12 The angle A0 between the sides is greater than or equal to 60 degrees and less than or equal to 150 degrees.
  • the angle A0 between the sides of the first partition 11 and the side of the second partition 12 is greater than 90 degrees and less than or equal to 150 degrees.
  • the angle A0 between the sides of the first partition 11 and the side of the second partition 12 is greater than 90 degrees and less than or equal to 120 degrees.
  • the value of the included angle A0 is related to the encapsulation effect. For example, the gentler the two sides forming the angle A0 are, the better the package effect will be. Of course, other methods can also be used to improve the encapsulation effect.
  • auxiliary connection electrodes can also be added by means of a secondary mask to connect the second electrodes E2 of different sub-pixels, or the optical coupling layer CPL (as shown in FIG. 1 ) can also be made conductive. That is, the second electrodes E2 of different sub-pixels are connected through the conductive light coupling layer CPL.
  • the inorganic layer in the encapsulation layer is fabricated using a chemical vapor deposition (CVD) method.
  • the angle A2 between the part of the second partition part 12 close to the top surface SF2 of the partition structure 10 (the side of the partition structure 10) and the top surface SF2 is an acute angle, for example, for In order to isolate the luminescent functional layer, the included angle A2 is greater than or equal to 45 degrees and less than or equal to 75 degrees.
  • each of the two base angles (angle A2 ) of the inverted trapezoidal second partition portion 12 is greater than or equal to 45 degrees and less than or equal to 75 degrees.
  • the display substrate includes a capacitor C0, the capacitor C0 includes a plate Ca and a plate Cb, and the orthographic projection and partition of the capacitor C0 on the base substrate BS
  • the orthographic projections of the structures 10 on the substrate substrate BS are at least partially overlapping.
  • the orthographic projection of other structures or other wires on the base substrate BS may at least partially overlap the orthographic projection of the isolation structure 10 on the base substrate BS.
  • These structures or wires overlapping with the isolation structure 10 may be located in the third conductive pattern layer LY3.
  • the display substrate further includes a pixel circuit PXC configured to drive the light-emitting element EMC to emit light
  • the display substrate further includes a planarization layer PLN.
  • An electrode E1 is connected to the pixel circuit PXC through a via hole V0 penetrating the planarization layer, and both the first electrode E1 and the first isolation portion 11 are located on the planarization layer PLN.
  • the isolation structure 10 is integrated with the pixel defining pattern PDL.
  • the pixel defining pattern PDL includes a pixel defining sublayer SL1 and a pixel defining sublayer SL2 .
  • the pixel defining sublayer SL1 is integrally structured with the first partition 11
  • the pixel defining sublayer SL2 is integrally structured with the second partition 12 . That is, the partition structure 10 also serves as the pixel defining pattern PDL at the same time.
  • the orthographic projection of the protrusion PR on the base substrate BS at least partially overlaps with the orthographic projection of the first electrode E1 on the base substrate BS .
  • the thickness of the second partition portion 12 is greater than the thickness of the first partition portion 11 .
  • the thickness of the second partition portion 12 is more than twice the thickness of the first partition portion 11 .
  • the thickness of the second partition part 12 is more than three times the thickness of the first partition part 11 .
  • the ratio of the thickness of the second partition 12 to the thickness of the first partition 11 is greater than or equal to 2 and smaller than or equal to 6.
  • the thickness of an element refers to the dimension of the element in a direction perpendicular to the main surface SF0 of the base substrate.
  • the direction Z is shown in the figure.
  • the direction Z is the direction perpendicular to the main surface SF0 of the base substrate.
  • the main surface SF0 of the base substrate is a surface on which various elements are fabricated.
  • the second partition part 12 is in contact with the first partition part 11 .
  • the first partition part 11 and the second partition part 12 have a contact surface CS, in order to facilitate partitioning at least one sub-functional layer of the light-emitting functional layer while making the second electrode E2 in the protruding part PR
  • the angle A1 between the part of the second partition 12 close to the contact surface CS and the contact surface CS is an obtuse angle.
  • the included angle A1 is greater than 90 degrees and less than or equal to 150 degrees.
  • the included angle A1 can also adopt other values.
  • the angle A2 between the portion of the second isolation portion 12 close to the top surface SF2 of the isolation structure 10 and the top surface SF2 is an obtuse angle.
  • the included angle A2 is greater than 110 degrees and less than or equal to 160 degrees.
  • the material of the first partition 11 includes a positive photoresist
  • the material of the second partition 12 includes a negative photoresist.
  • the isolation structure 10 can be formed by utilizing the properties of the positive photoresist and the negative photoresist.
  • the second electrode E2 is in contact with a part of the side surface SF3 of the isolation structure 10 . As shown in FIGS. 3 to 8 , the second electrode E2 is in contact with the side surface SF3 of the partition structure 10 at the constriction of the partition structure 10 .
  • both the first electrode E1 and the first partition portion 11 are in contact with the planarization layer PLN.
  • both the first electrode E1 and the first partition portion 11 are in contact with the planarization layer PLN2 .
  • the smallest dimension of the isolation structure 10 in a plane parallel to the main surface is smaller than the distance between the first electrodes E1 of adjacent sub-pixels SP.
  • the maximum dimension of the isolation structure 10 in a plane parallel to the main surface is greater than or equal to the distance between the first electrodes E1 of adjacent sub-pixels SP. one-fifth of the distance.
  • the smallest dimension of the isolation structure 10 in a plane parallel to the main surface is greater than the distance between the first electrodes E1 of adjacent sub-pixels SP.
  • the display substrate includes a buffer layer BF, a gate insulating layer GI1 , a gate insulating layer GI2 , and an interlayer insulating layer ILD.
  • the thin film transistor T0 includes a gate GE, an active layer ACT, a source Ea, and a drain Eb, and the first electrode E1 is connected to the drain Eb.
  • the source Ea and the drain Eb of the thin film transistor may be identical in structure and interchangeable in terms of names.
  • the thin film transistor T0 may be a light emission control transistor.
  • Figures 3 and 5 also show the first plate Ca and the second plate Cb of the capacitor.
  • the first conductive pattern layer LY1 includes the grid GE and the first plate Ca
  • the second conductive pattern layer LY2 includes the second plate Cb
  • the third conductive pattern layer LY3 includes the source electrode Ea and Drain Eb.
  • the display substrate includes a planarization layer PLN1 and a planarization layer PLN2 .
  • FIG. 9A is a schematic diagram of an isolation structure of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 9B is a schematic diagram of an isolation structure of a display substrate provided by an embodiment of the present disclosure.
  • the luminescent functional layer FL is broken at the protrusion of the partition structure 10 to form a luminescent functional part FL1 and a luminescent functional part FL2 , and the luminescent functional part FL2 is located on the partition structure 10 . That is, each sub-functional layer of the light emitting functional layer FL is disconnected at the protrusion of the partition structure 10 .
  • the second electrode E2 is continuous everywhere. That is, the second electrode E2 is not disconnected by the partition structure 10 .
  • the material of the second electrode E2 is usually metal or alloy, and metal or alloy has better climbing performance.
  • the difference between the structure shown in FIG. 9B and the structure shown in FIG. 9A is that a part of the sub-functional layer of the light-emitting functional layer FL is disconnected at the protruding part of the partition structure 10, while another part of the sub-functional layer is disconnected at the protruding part of the partition structure 10.
  • the functional sub-part FLa and the functional sub-part FLb are formed, the functional sub-part FLa is not disconnected, and the functional sub-part FLb forms the disconnected parts FLb1 and FLb2.
  • FIG. 10 is a schematic diagram of light emitting elements in a display substrate provided by an embodiment of the present disclosure.
  • the luminescent functional layer FL includes a stacked charge generation layer 40 , a first luminescent layer 41 and a second luminescent layer 42 , and the first luminescent layer 41 is located on the first Between the electrode E1 and the charge generation layer 40, the second light emitting layer 42 is located between the second electrode E2 and the charge generation layer 40, and the charge generation layer 40 is disconnected at the protrusion PR. Since the charge generation layer 40 is disconnected at the isolation structure 10 , the propagation path of the charge is longer, and the resistance of the charge generation layer in the light-emitting functional layer is relatively large, which can effectively avoid crosstalk between adjacent sub-pixels.
  • the sub-functional layer between the charge generation layer 40 and the first electrode E1 is also disconnected at the protrusion PR, and the charge generation The subfunctional layer between the layer 40 and the second electrode E2 is not interrupted at the protrusion PR.
  • the sub-functional layer between the charge generation layer 40 and the first electrode E1 is also disconnected at the protrusion PR, and the charge generation layer The subfunctional layer between 40 and the second electrode E2 is also disconnected at the protrusion PR, and in this case, each subfunctional layer of the light emitting functional layer FL is disconnected at the protrusion PR.
  • the luminescent functional layer FL further includes a first charge transport layer 51 located between the first electrode E1 and the first luminescent layer 41 and a first charge transport layer 51 located between the first luminescent layer 41 . Between the second charge transport layer 52 and the charge generation layer 40, the first charge transport layer 51 and the second charge transport layer 52 are disconnected at the protrusion PR.
  • the first charge transport layer 51 is a hole transport layer HTL
  • the second charge transport layer 52 is an electron transport layer ETL.
  • HTL hole transport layer
  • ETL electron transport layer
  • FIG. 11 is a schematic plan view of another display substrate provided by an embodiment of the present disclosure.
  • the isolation structure 10 is ring-shaped to surround the light-emitting region R0, and the second electrode E2 is continuous at the protruding part of the isolation structure 10, so as to facilitate the second electrode of different sub-pixels. Signal transmission on the second electrode E2.
  • the cross-sectional view of the partition structure 10 is as shown above.
  • each sub-pixel SP is surrounded by an isolation structure 10 .
  • FIG. 12 is a schematic plan view of another display substrate provided by an embodiment of the present disclosure. According to the display substrate provided by the embodiment of the present disclosure, as shown in FIG. One-half of the orthographic projection on the base substrate BS.
  • each sub-pixel SP is surrounded by three or four partition sub-structures 01 .
  • the number of partition substructures 01 can be determined as required.
  • the display substrate includes a first sub-pixel 201 , a second sub-pixel 202 , a third sub-pixel 203 and a fourth sub-pixel 204 .
  • one of the first sub-pixel 201 and the third sub-pixel 203 is a blue sub-pixel
  • the other of the first sub-pixel 201 and the third sub-pixel 203 is a red sub-pixel
  • the second sub-pixel 202 and the fourth sub-pixel 204 may be sub-pixels of the same color, eg, all green sub-pixels.
  • the emission colors of the first sub-pixel 201 , the second sub-pixel 202 , the third sub-pixel 203 and the fourth sub-pixel 204 can be determined as required.
  • a first sub-pixel 201, a second sub-pixel 202, a third sub-pixel 203 and a fourth sub-pixel 204 constitute a repeating unit RP
  • the second sub-pixel 202 and the fourth sub-pixel 204 are located on both sides of the connecting line CL connecting the centers of the first sub-pixel 201 and the third sub-pixel 203
  • 11 and 12 illustrate the center C1 of the first sub-pixel 201 and the center C2 of the third sub-pixel 203
  • the first sub-pixel 201 and the third sub-pixel 203 are also arranged on two sides of a line connecting the centers of the second sub-pixel 202 and the fourth sub-pixel 204 .
  • only one partition structure is provided between two adjacent sub-pixels, so that the width of the space between two adjacent sub-pixels can be reduced to increase the pixel density.
  • the spacer 50 is configured to support a fine metal mask when fabricating the light emitting layer.
  • the spacer 50 is in the area surrounded by the first sub-pixel 201 , the second sub-pixel 202 , the third sub-pixel 203 , and the fourth sub-pixel 204 .
  • spacers 50 are disposed between the first sub-pixels 201 and the third sub-pixels 203 arranged in the second direction Y.
  • Direction X intersects direction Y.
  • direction X is perpendicular to direction Y.
  • Both the direction X and the direction Y are directions parallel to the main surface of the base substrate.
  • direction Z is perpendicular to direction X and perpendicular to direction Y.
  • FIG. 13 is a schematic diagram of a pixel circuit and a light emitting element in a display substrate.
  • Figure 13 takes the pixel circuit of 7T1C as an example for illustration. It should be noted that the pixel circuit is not limited to that shown in FIG. 13 , and can be set as required.
  • the display substrate includes sub-pixels SP, and the sub-pixels include pixel circuits PXC and light emitting elements EMC.
  • the light emitting element EMC includes a first electrode E1, a second electrode E2, and a light emitting functional layer located between the first electrode E1 and the second electrode E2.
  • the pixel circuit PXC includes a transistor and a storage capacitor Cst.
  • the transistors include transistors T1-T7, and the storage capacitor Cst includes a plate Ca1 and a plate Cb1.
  • Fig. 13 also shows the gate line GT providing the scan signal SCAN, the data line DT providing the data signal DATA, the light emitting control signal line EML providing the light emitting control signal EM, the power line PL1 providing the power supply voltage VDD, and the power line providing the power supply voltage VSS.
  • Power line PL2 reset control signal line RST1 for supplying reset signal RESET, reset control signal line RST2 for supplying scan signal SCAN, initialization signal line INT1 for supplying initialization signal Vinit1, and initialization signal line INT2 for supplying initialization signal Vinit2.
  • the transistor T1 is a driving transistor
  • the transistor T2 is a data writing transistor
  • the transistor T3 is a threshold compensation transistor
  • the transistor T4 is a light emission control transistor
  • the transistor T5 is a light emission control transistor
  • the transistor T6 is a reset control transistor.
  • Transistor T7 is a reset control transistor.
  • FIG. 14A is a schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 14B is a schematic diagram of a display substrate provided by another embodiment of the present disclosure.
  • the display substrate further includes a conductive structure 30 configured to provide signals to the pixel circuit, and the conductive structure 30 is located between the isolation structure 10 and the substrate.
  • the orthographic projection of the conductive structure 30 on the base substrate BS overlaps with the orthographic projection of the isolation structure 10 on the base substrate BS.
  • the conductive structure 30 may be located in the third conductive pattern layer LY3, and the isolation structure 10 is formed after the conductive structure 30 is formed.
  • the conductive structure 30 may also be located in other layers. For example, for a display substrate with a lower PPI, the conductive structure 30 may also be in the same layer as the first electrode E1 if there are sufficient wiring positions.
  • the orthographic projection of the conductive structure 30 on the base substrate BS coincides with the orthographic projection of the isolation structure 10 on the base substrate BS.
  • the orthographic projection of the conductive structure 30 on the base substrate BS partially overlaps the orthographic projection of the isolation structure 10 on the base substrate BS.
  • the conductive structure 30 is connected to the second electrode E2, which can greatly reduce the resistance of the second electrode E2 (VSS), reduce the voltage drop on the second electrode E2, thereby reducing the power supply voltage VSS and the power supply voltage in the display substrate.
  • the voltage difference between VDD can better reduce the power consumption of the display substrate.
  • the voltage drop on the second electrode E2 (VSS) can be reduced by about 0.5V.
  • the conductive structure 30 is located between the light emitting regions R0 of adjacent sub-pixels SP, and the conductive structure 30 is electrically connected to the second electrode E2.
  • the connection position of the conductive structure 30 and the second electrode E2 may be located in the peripheral area, but is not limited thereto.
  • the peripheral area can be a frame area of the display substrate.
  • the display area may be an area where a display screen of the substrate is displayed.
  • the display area includes a light emitting area R0 and a spacer area Ra between adjacent sub-pixels.
  • the peripheral area is located on at least one side of the display area.
  • the peripheral area surrounds the display area.
  • the second electrode E2 is the cathode of the light emitting element
  • the first electrode E1 is the anode of the light emitting element.
  • the second electrode E2 is a continuous electrode on the entire surface and is not disconnected by the partition structure 10 , it is beneficial to reduce the resistance of the second electrode E2 and facilitate signal transmission on the second electrode E2 .
  • each sub-functional layer of the light-emitting functional layer FL is disconnected by the partition structure 10, so as to reduce crosstalk between adjacent sub-pixels, and the second electrode E2 is a continuous electrode on the entire surface, which is not disconnected by the partition structure 10 , which is beneficial to reduce the resistance of the second electrode E2 and facilitates signal transmission on the second electrode E2.
  • An embodiment of the present disclosure also provides a display device, including any one of the above display substrates.
  • the display substrate in the embodiments of the present disclosure may also be referred to as a display panel.
  • FIG. 15 is a schematic diagram of a display device provided by an embodiment of the present disclosure.
  • the display device 500 includes a display substrate 100 .
  • the display substrate 100 is any one of the above display substrates.
  • the display substrate is provided with an isolation structure between adjacent sub-pixels, and at least one sub-functional layer in the light-emitting functional layer, for example, the charge generation layer, is disconnected at the position where the isolation structure is located, thereby avoiding conduction.
  • a more sensitive sub-functional layer eg, a charge generation layer
  • the display substrate can adopt the Tandem structure to increase the pixel density. Therefore, the display device including the display substrate has the advantages of long life, low power consumption, high brightness, high resolution and the like.
  • the display device can be a display device such as an organic light-emitting diode display device, and any product or component with a display function such as a TV, a digital camera, a mobile phone, a watch, a tablet computer, a notebook computer, a navigator, etc., which include the display device. Examples include but are not limited to.
  • FIG. 16A to 16D are schematic diagrams of a manufacturing method of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 17A is a schematic cross-sectional view of a negative photoresist after exposure and development.
  • 17B is a schematic cross-sectional view of the positive photoresist after exposure and development.
  • 18A to 18C are schematic diagrams of a manufacturing method of a display substrate provided by an embodiment of the present disclosure.
  • an embodiment of the present disclosure further provides a method for manufacturing a display substrate, including the following steps.
  • the sub-pixels SP include a light-emitting element EMC, the light-emitting element EMC has a light-emitting region R0, and the light-emitting element EMC includes a first electrode E1, a light-emitting functional layer FL, and a second The electrode E2, the second electrode E2 is located on the side of the light emitting functional layer FL away from the base substrate BS, the first electrode E1 is located on the side of the light emitting functional layer FL close to the base substrate BS, and the light emitting functional layer FL includes a plurality of sub-functional layers .
  • Forming the isolation structure 10 includes forming a stacked first isolation portion 11 and a second isolation portion 12.
  • the first isolation portion 11 is located in the second isolation portion. 12 on the side close to the base substrate BS;
  • the second partition 12 has a protruding part PR, and the protruding part PR protrudes relative to the side of the first partition 11 close to the second partition 12, and at least one of the light-emitting functional layers FL
  • the sub-functional layer is disconnected at the protruding part PR, the material of the first partition part 11 includes an organic material, the material of the second partition part 12 includes an organic material, along the direction from the first electrode E1 to the second electrode E2, the partition structure
  • the orthographic projection of 10 on the base substrate BS gradually decreases and then gradually increases.
  • the manufacturing method of the display substrate provided by the embodiment of the present disclosure includes the following steps.
  • the second partition 12 may serve as a spacer to support a fine metal mask when forming the light emitting layer.
  • the partition structure 10 can be formed only by changing the pixel definition pattern and the shape of the spacer, without increasing the number of masks, which is beneficial to the display substrate. make.
  • the isolation structure 10 is formed after the first electrode E1 is formed, and does not affect the fabrication of the backplane.
  • the space for making the partition structure 10 is larger, which is beneficial to form a partition structure 10 with a larger size.
  • the structure formed after exposure and development of the negative photoresist is large and small at the bottom.
  • the structure formed by the positive photoresist after exposure and development is small at the top and large at the bottom.
  • the properties of the positive photoresist and the negative photoresist can be utilized to form an isolation structure to isolate at least one sub-functional layer of the light-emitting functional layer.
  • forming the stacked first partition part 11 and the second partition part 12 includes the following steps.
  • step S04 the following steps may also be included.
  • the second electrode E2 may or may not be disconnected at the protruding portion of the isolation structure 10 .
  • FIG. 18B shows a pixel-defining sub-layer pattern 12P including a second partition 12 .
  • FIG. 18C shows a pattern 11P of a pixel-defining sublayer, which includes a first partition 11 .
  • the thickness of the positive photoresist film 11F may be 0.5 ⁇ 1 ⁇ m.
  • the thickness of the first partition part 11 may be 0.5-1 ⁇ m.
  • the thickness of the negative photoresist film 12F may be 1.2-2 ⁇ m.
  • the thickness of the second partition part 12 may be 1.2-2 ⁇ m.
  • step S03 the first exposure is performed, and a mask plate can be used to block and expose the negative photoresist, and an inverted trapezoid pattern can be formed in the exposed area.
  • step S04 the second exposure is performed, and the positive photoresist is exposed again using the pattern of the negative photoresist. According to the exposure depth, the positive photoresist under the negative photoresist is not exposed, and the negative Positive photoresist not masked by positive photoresist will be removed after exposure. Finally, an inverted gourd-like shape is formed, and the resistance of the sub-functional layer such as the charge generation layer (CGL) is increased by this shape, so as to reduce crosstalk between adjacent sub-pixels when emitting light.
  • the sub-functional layer such as the charge generation layer (CGL)
  • the display substrate shown in FIG. 7 can be formed by using the method shown in FIGS. 18A to 18C .
  • the pixel defining pattern PDL and the isolation structure 10 may be integrated. It can be regarded as that the pixel definition pattern PDL is multiplexed into the isolation structure 10 .
  • the isolation structure 10 can be formed only by changing the shape of the pixel-defining pattern, without increasing the number of masks, which facilitates the manufacture of the display substrate.
  • the isolation structure 10 is formed after the formation of the first electrode E1 , without affecting the fabrication of the backplane.
  • the isolation structure 10 is multiplexed into a pixel-defining pattern, which is formed at one time with the opening area of the pixel-defining pattern, without making a new isolation structure, which simplifies the manufacturing process.
  • the isolation structure 10 is made by using a mask plate, and the second isolation portion 12 formed by the negative resist is used as a mask of the positive photoresist, which can avoid the problem of dislocation (overlay) in the exposure process, thereby, It is suitable for the production of display substrates with very high PPI.
  • photoresist refers to a material whose solubility is changed by irradiation or radiation of ultraviolet light, electron beams, ion beams, X-rays, and the like.
  • positive-tone photoresists the exposed parts are removed after development, and the unexposed parts are left behind after development.
  • negative-tone photoresists the exposed parts are left behind after development, and the unexposed parts are removed after development.
  • the exposure and development process is different.
  • the positive photoresist is developed in the exposure interval, while the negative photoresist is the opposite, and its exposure interval is retained.
  • contours formed by diffused light at the boundaries of negative photoresists and positive photoresists are different.
  • the contours formed by diffusion make the image after development be wide at the bottom and narrow at the top, while the negative photoresist is opposite, wide at the top and wide at the bottom narrow image.
  • the positive photoresist is soluble in strong alkali, and the developer is an alkaline solution, while the developer of the negative photoresist is mostly an organic solution (such as xylene solution).
  • the positive photoresist and the negative photoresist are exposed using the same mask, and the exposure principles and the properties of the developing solution are different for the positive photoresist and the negative photoresist.
  • To form an inverted "gourd-shaped" columnar partition structure and use this shape to increase the resistance of the sub-functional layer in the light-emitting functional layer, such as the charge generation layer (CGL), and reduce crosstalk.
  • CGL charge generation layer
  • components located on the same layer may be formed from the same film layer through the same patterning process.
  • the patterning or patterning process may only include a photolithography process, or include a photolithography process and an etching step, or may include printing, inkjet and other processes for forming a predetermined pattern.
  • the photolithography process refers to the process including film formation, exposure, and development, and uses photoresist, mask plate, exposure machine, etc. to form patterns.
  • a corresponding patterning process can be selected according to the structure formed in the embodiments of the present disclosure.
  • the thickness of a component refers to the dimension of the component in a direction perpendicular to the base substrate.
  • the base substrate BS, the buffer layer BF, the gate insulating layer GI1, the gate insulating layer GI2, the interlayer insulating layer ILD, the planarization layer PLN, the planarization layer PLN1, and the planarization layer PLN2 are all Made of insulating material.
  • the material of the base substrate BS includes polyimide, but is not limited thereto.
  • the base substrate BS may be a flexible base substrate to form a flexible display substrate.
  • materials of the buffer layer BF, the gate insulating layer GI1 , the gate insulating layer GI2 , and the interlayer insulating layer ILD include inorganic insulating materials.
  • the materials of the planarization layer PLN, the planarization layer PLN1 and the planarization layer PLN2 include organic insulating materials.
  • the inorganic insulating material includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.
  • the organic insulating material includes one or a combination of acrylic, polyethylene terephthalate, polyimide, polyamide, polycarbonate, epoxy resin, and the like.
  • the gate GE, the first plate Ca, the second plate Cb, the source Ea and the drain Eb are made of metal or alloy.
  • the active layer ACT is a semiconductor layer, and polysilicon or metal oxide semiconductor can be used.

Abstract

提供一种显示基板及其制作方法和显示装置。显示基板包括：多个子像素，位于衬底基板的主表面上，子像素包括发光元件，发光元件具有发光区，发光元件包括第一电极、发光功能层、以及第二电极，发光功能层包括多个子功能层；以及隔断结构，位于相邻子像素的发光区之间，并包括层叠设置的第一隔断部和第二隔断部，第一隔断部位于第二隔断部的靠近衬底基板的一侧，第二隔断部具有突出部，突出部相对于第一隔断部的靠近第二隔断部的一侧突出，发光功能层的至少一个子功能层在突出部处断开，第一隔断部的材料包括有机材料，第二隔断部的材料包括有机材料，沿从第一电极指向第二电极的方向上，隔断结构在衬底基板上的正投影逐渐减小再逐渐增大。

Description

显示基板及其制作方法和显示装置
相关申请的交叉引用
出于所有目的，本申请要求于2021年11月30日递交的中国专利申请第202111448253.1号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种显示基板及其制作方法和显示装置。
背景技术
随着显示技术的不断发展，有机发光二极管(OLED)显示装置因其广色域、高对比度、轻薄设计、自发光、以及宽视角等优点已经成为当前各大厂商的研究热点和技术发展的方向。
目前，有机发光二极管显示装置已经广泛地应用到各种电子产品中，小到智能手环、智能手表、智能手机、平板电脑等电子产品，大到笔记本电脑、台式电脑、电视机等电子产品。因此，市场对于有源矩阵有机发光二极管显示装置的需求也日益旺盛。
发明内容
本公开的实施例提供一种显示基板及其制作方法和显示装置。
本公开的实施例提供一种显示基板，包括：衬底基板；多个子像素，位于所述衬底基板的主表面上，所述子像素包括发光元件，所述发光元件具有发光区，所述发光元件包括第一电极、发光功能层、以及第二电极，所述第二电极位于所述发光功能层的背离所述衬底基板的一侧，所述第一电极位于所述发光功能层的靠近所述衬底基板的一侧，所述发光功能层包括多个子功能层；以及隔断结构，位于相邻子像素的发光区之间，并包括层叠设置的第一隔断部和第二隔断部，所述第一隔断部位于所述第二隔断部的靠近所述衬底基板的一侧；所述第二隔断部具有突出部，所述突出部相对于所述第一隔断部的靠近所述第二隔断部的一侧突出，所述发光功能层的至少一个子功能层在所述突出部处断开，所述第一隔断部的材料包括有机材料，所述第二隔断部的材料包括有机材料，沿从所述第一电极指向所述第二电极的方向上，所述隔断结构在所述衬底基板上的正投影逐渐减小再逐渐增大。
根据本公开的实施例提供的显示基板，所述第二隔断部与所述第一隔断部接触。
根据本公开的实施例提供的显示基板，所述隔断结构呈葫芦型或沙漏型。
根据本公开的实施例提供的显示基板，所述隔断结构包括底面、顶面和位于所述底面和所述顶面之间的两个侧面，所述侧面呈V字型，两个V字的底部相对设置。
根据本公开的实施例提供的显示基板，在所述隔断结构的同一侧，所述第一隔断部的侧面和所述第二隔断部的侧面之间的夹角大于或等于60度且小于或等于150度。
根据本公开的实施例提供的显示基板，所述第二隔断部的靠近所述隔断结构的顶面的部分与所述顶面之间的夹角为锐角，所述锐角大于或等于60度且小于或等于80度。
根据本公开的实施例提供的显示基板，所述第二隔断部的靠近所述隔断结构的顶面的部分与所述顶面之间的夹角为钝角，所述钝角大于110度且小于或等于160度。
根据本公开的实施例提供的显示基板，显示基板还包括：像素限定图案，包括多个开口，所述开口被配置为限定所述子像素的所述发光区，所述开口被配置为暴露所述第一电极的至少一部分，所述像素限定图案包括与所述第一隔断部位于同一层的部分。
根据本公开的实施例提供的显示基板，所述像素限定图案与所述第一隔断部至少部分分离，所述像素限定图案与所述第一隔断部均与同一绝缘层接触并位于该绝缘层之上。
根据本公开的实施例提供的显示基板，所述像素限定图案包括位于两个相邻开口之间的第一像素限定部和第二像素限定部，所述隔断结构位于所述第一像素限定部和所述第二像素限定部之间，所述隔断结构和所述第一像素限定部之间具有第一凹陷，所述隔断结构和所述第二像素限定部之间具有第二凹陷。
根据本公开的实施例提供的显示基板，所述突出部在所述衬底基板上的正投影与所述第一电极在所述衬底基板上的正投影至少部分交叠。
根据本公开的实施例提供的显示基板，所述像素限定图案与所述隔断结构为一体结构。
根据本公开的实施例提供的显示基板，所述第一隔断部的材料包括正性光刻胶，所述第二隔断部的材料包括负性光刻胶。
根据本公开的实施例提供的显示基板，所述发光功能层包括层叠设置的电荷产生层、第一发光层和第二发光层，所述第一发光层位于所述第一电极和所述电荷产生层之间，所述第二发光层位于所述第二电极和所述电荷产生层之间，所述电荷产生层在所述突出部处断开。
根据本公开的实施例提供的显示基板，所述发光功能层还包括位于所述第一电极和所述第一发光层之间的第一电荷传输层以及位于所述第一发光层 和所述电荷产生层之间的第二电荷传输层，所述第一电荷传输层和所述第二电荷传输层在所述突出部处断开。
根据本公开的实施例提供的显示基板，所述隔断结构包括至少一个隔断子结构，所述至少一个隔断子结构在所述衬底基板上的正投影至少环绕所述发光区在所述衬底基板上的正投影的二分之一。
根据本公开的实施例提供的显示基板，所述隔断结构呈环形，以围绕所述发光区，所述第二电极在所述突出部处连续。
根据本公开的实施例提供的显示基板，显示基板还包括像素电路，所述像素电路被配置为驱动所述发光元件发光，所述显示基板还包括平坦化层，所述第一电极通过贯穿所述平坦化层的过孔与所述像素电路相连，所述第一电极和所述第一隔断部均位于所述平坦化层上。
根据本公开的实施例提供的显示基板，所述第一电极和所述第一隔断部均与所述平坦化层接触。
根据本公开的实施例提供的显示基板，所述像素电路包括电容，所述电容在所述衬底基板上的正投影与所述隔断结构在所述衬底基板上的正投影至少部分交叠。
根据本公开的实施例提供的显示基板，显示基板还包括导电结构，所述导电结构被配置为向所述像素电路提供信号，所述导电结构位于所述隔断结构和所述衬底基板之间，所述导电结构在所述衬底基板上的正投影与所述隔断结构在所述衬底基板上的正投影交叠。
根据本公开的实施例提供的显示基板，所述导电结构位于相邻子像素的发光区之间，所述导电结构与所述第二电极电连接。
根据本公开的实施例提供的显示基板，所述隔断结构在平行于所述主表面的平面内的最小尺寸大于相邻子像素的第一电极之间的间距。
根据本公开的实施例提供的显示基板，所述隔断结构在平行于所述主表面的平面内的最大尺寸大于或等于相邻子像素的第一电极之间的间距的五分之一。
本公开的实施例还提供一种显示装置，包括上述任一显示基板。
本公开的实施例还提供一种显示基板的制作方法，包括：在衬底基板的主表面上形成多个子像素，所述子像素包括发光元件，所述发光元件具有发光区，所述发光元件包括第一电极、发光功能层、以及第二电极，所述第二电极位于所述发光功能层的背离所述衬底基板的一侧，所述第一电极位于所述发光功能层的靠近所述衬底基板的一侧，所述发光功能层包括多个子功能层；以及在相邻子像素的发光区之间形成隔断结构，形成所述隔断结构包括形成层叠设置的第一隔断部和第二隔断部，所述第一隔断部位于所述第二隔断部的靠近所述衬底基板的一侧；所述第二隔断部具有突出部，所述突出部 相对于所述第一隔断部的靠近所述第二隔断部的一侧突出，所述发光功能层的至少一个子功能层在所述突出部处断开，所述第一隔断部的材料包括有机材料，所述第二隔断部的材料包括有机材料，沿从所述第一电极指向所述第二电极的方向上，所述隔断结构在所述衬底基板上的正投影逐渐减小再逐渐增大。
根据本公开的实施例提供的制作方法，形成层叠设置的所述第一隔断部和所述第二隔断部包括：形成正性光刻胶薄膜；在所述正性光刻胶薄膜上形成负性光刻胶薄膜；对所述负性光刻胶薄膜进行构图形成所述第二隔断部；以及以所述第二隔断部为掩膜对所述正性光刻胶薄膜进行构图，形成所述第一隔断部。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为发光元件的示意图。
图2为一种显示基板的示意图。
图3为本公开的实施例提供的一种显示基板的剖视图。
图4为图3中的隔断结构处的放大图。
图5为本公开的实施例提供的另一种显示基板的剖视图。
图6为图5中的隔断结构处的放大图。
图7为本公开的实施例提供的另一种显示基板的剖视图。
图8为图7中的隔断结构处的放大图。
图9A为本公开的实施例提供的一种显示基板的隔断结构处的示意图。
图9B为本公开的实施例提供的一种显示基板的隔断结构处的示意图。
图10为本公开的实施例提供的显示基板中的发光元件的示意图。
图11为本公开一实施例提供的另一种显示基板的平面示意图。
图12为本公开一实施例提供的另一种显示基板的平面示意图。
图13为一种显示基板中的像素电路和发光元件的示意图。
图14A为本公开一实施例提供的显示基板的示意图。
图14B为本公开另一实施例提供的显示基板的示意图。
图15为本公开一实施例提供的一种显示装置的示意图。
图16A至图16D为本公开的实施例提供的一种显示基板的制作方法的示意图。
图17A为负性光刻胶经曝光显影后的截面示意图。
图17B为正性光刻胶经曝光显影后的截面示意图。
图18A至图18C为本公开的实施例提供的一种显示基板的制作方法的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
随着显示技术的不断发展，人们对于显示品质的追求也越来越高。为了进一步降低功耗并实现高亮度，可将OLED显示面板中的发光元件中的一个发光层替换为两个发光层，并在该两个发光层之间增加电荷产生层(CGL)，使用N/P-CGL作为异质结，将两个发光器件结构串联，形成双叠层设计，构成Tandem结构，Tandem结构的显示基板实现了双发光器件串联，在相同发光强度下，极大地降低了发光元件的发光电流，提升了发光元件的寿命，有利于车载等高寿命新技术开发量产。Tandem结构的显示装置具有寿命长、功耗低、亮度高等优点。
图1为发光元件的示意图。图1(a)为通常的发光元件的示意图。图1(b)为一种具有Tandem结构的发光元件的示意图。如图1(b)所示，Tandem结构的不同发光元件之间的电荷产生层(CGL)是相连的。
图1示出了第一电极E1、第二电极E2、空穴传输层HTL、电子传输层ETL、光耦合层CPL、增透层ARL、P型掺杂的电荷产生层P-CGL、N型掺杂的电荷产生层N-CGL、发光层R、发光层G、发光层B。发光层R包括分别含有发光材料R1和发光材料R2的两个子层，发光层G包括分别含有发光材料G1和发光材料G2的两个子层，发光层B包含发光材料B1和发光材料B2。发光材料R1和发光材料R2为发红光的两种不同的材料，发光材料G1和发光材料G2为发绿光的两种不同的材料，发光材料B1和发光材料B2为 发蓝光的两种不同的材料。
图2为一种显示基板的示意图。如图2所示，显示基板包括平坦化层PLN1、平坦化层PLN2、像素限定层PDL、电极E1、发光功能层FL、电极E2以及封装层EPS。图1示出了发光元件EM01和发光元件EM02，发光元件EM01和发光元件EM02的电荷产生层(CGL)可为一体结构，采用开口掩膜来制作。
然而，发明人注意到，对于高分辨率的产品而言，由于电荷产生层具有较强的导电性，而相邻的子像素的发光功能层(这里指包括两个发光层和电荷产生层的膜层)是相连的，因此电荷产生层容易导致相邻子像素之间的串扰，影响产品画质，从而严重地影响显示品质。
例如，相邻子像素之间的串扰是指应该不发光的发光元件发光的情况。如图2所示，若想要的情况是发光元件EM01发光，而发光元件EM02不发光，但因电荷产生层的导电性，使得发光元件EM02也发光，从而形成串扰。
图3为本公开的实施例提供的一种显示基板的剖视图。图4为图3中的隔断结构处的放大图。图5为本公开的实施例提供的另一种显示基板的剖视图。图6为图5中的隔断结构处的放大图。图7为本公开的实施例提供的另一种显示基板的剖视图。图8为图7中的隔断结构处的放大图。图9A为本公开的实施例提供的一种显示基板的隔断结构处的示意图。图9B为本公开的实施例提供的一种显示基板的隔断结构处的示意图。
如图3、图5和图7所示，本公开的实施例提供一种显示基板包括：衬底基板BS、多个子像素SP、以及隔断结构10。
如图3和图5所示，多个子像素SP位于衬底基板BS的主表面SF0上，子像素SP包括发光元件EMC，发光元件EMC具有发光区R0。图7也示出了发光元件EMC以及发光区R0。
如图3、图5和图7所示，发光元件EMC包括第一电极E1、发光功能层FL、以及第二电极E2，第二电极E2位于发光功能层FL的背离衬底基板BS的一侧，第一电极E1位于发光功能层FL的靠近衬底基板BS的一侧，发光功能层FL包括多个子功能层。
例如，第一电极E1采用导电材料制作。例如，第一电极E1的材料包括金属和导电的金属氧化物。例如，第一电极E1采用氧化铟锡(ITO)、银(Ag)、氧化铟锡(ITO)层叠设置的结构。第一电极E1的材料和结构可根据需要设置。
例如，第二电极E2采用导电材料制作。例如，第二电极E2的材料包括金属或合金。例如，第二电极E2的材料包括Mg/Ag合金。第二电极E2的材料和结构可根据需要设置。
例如，不同子像素的第二电极E2电连接，以利于提供相同的电压信号。
如图3、图5和图7所示，隔断结构10位于相邻子像素SP的发光区R0之间，并包括层叠设置的第一隔断部11和第二隔断部12，第一隔断部11位于第二隔断部12的靠近衬底基板BS的一侧；第二隔断部12具有突出部PR，突出部PR突出于第一隔断部11，例如，突出部PR相对于第一隔断部11的靠近第二隔断部12的一侧突出；发光功能层FL的至少一个子功能层在突出部PR处断开，沿从第一电极E1指向第二电极E2的方向上，隔断结构10在衬底基板BS上的正投影逐渐减小再逐渐增大。例如，从第一电极E1指向第二电极E2的方向为方向Z。隔断结构10先缩窄再增宽的结构利于隔断发光功能层FL的至少一个子功能层。
例如，如图3、图5和图7所示，突出部PR相对于第一隔断部11的顶面突出。
例如，一个元件在突出部PR处断开包括在突出部PR的侧面处断开。
例如，第一隔断部11的材料包括有机材料，第二隔断部12的材料包括有机材料。例如，有机材料包括树脂，但不限于此。例如，有机材料包括亚克力或聚对苯二甲酸乙二醇酯、聚酰亚胺、聚酰胺、聚碳酸酯、环氧树脂等中的一种或几种的组合。例如，第一隔断部11的材料可包括光刻胶，第二隔断部12的材料可包括光刻胶。
例如，第二隔断部12的材料与第一隔断部11的材料不同。
例如，如图3、图5和图7所示，第二隔断部12的截面呈倒梯形，但不限于此，第二隔断部12的截面也可以采用其他适合的形状。
如图3、图5和图7所示，多个子像素SP包括子像素SP1和子像素SP2。子像素SP1和子像素SP2为两个相邻的子像素。显示基板上设置的子像素的个数不限于图中所示，可根据需要而定。
在本公开的实施例中，发光功能层FL包括的子功能层的数量可根据需要来设置。
在本公开的实施例提供的显示基板中，可通过在相邻的子像素之间设置隔断结构，并使得发光功能层中的多个子功能层中的至少一个在隔断结构所在的位置断开，增大发光功能层FL中的导电率较高的子功能层的电阻，从而减轻多个子功能层中导电率较高的膜层造成相邻子像素之间的串扰。
本公开的实施例提供的显示基板，隔断结构10在形成第一电极E1之后形成，不需改变显示基板的背板结构，无涂胶孔晕等风险。并且，隔断结构10设置在发光元件的第一电极E1之间，使得隔断结构10有较大的设置空间，利于设置不同结构的隔断结构10。
如图3和图5所示，根据本公开的实施例提供的显示基板，隔断结构10呈沙漏型。如图7所示，隔断结构10呈葫芦型或倒葫芦型，在截面图中，隔断结构10的第一隔断部11和第二隔断部12的接触位置处缩窄，隔断结构10 的靠近衬底基板BS的一端和远离衬底基板BS的一端的尺寸大于隔断结构10的缩窄位置处的尺寸。
如图3、图5和图7所示，隔断结构10可以设置在显示基板的显示区的子像素之间。
如图4、图6和图8所示，根据本公开的实施例提供的显示基板，隔断结构10包括底面SF1、顶面SF2和位于底面SF1和顶面SF2之间的两个侧面SF3，侧面SF3呈V字型，两个V字的底部相对设置。
如图3、图5和图7所示，根据本公开的实施例提供的显示基板，显示基板还包括：像素限定图案PDL，包括多个开口OPN，开口OPN被配置为限定子像素SP的发光区R0，开口OPN被配置为暴露第一电极E1的至少一部分。
如图3至图6所示，像素限定图案PDL与第一隔断部11位于同一层。在本公开的实施例中，两个元件位于同一层是指该两个元件由同一膜层构图而成。
如图3至图6所示，根据本公开的实施例提供的显示基板，像素限定图案PDL与第一隔断部11至少部分分离，像素限定图案PDL与第一隔断部11均与同一绝缘层接触并位于该绝缘层之上。图3至图6示出了像素限定图案PDL与第一隔断部11均与平坦化层PLN接触并位于平坦化层PLN之上。
如图3和图5所示，根据本公开的实施例提供的显示基板，像素限定图案PDL包括位于两个相邻开口OPN之间的第一像素限定部PDL1和第二像素限定部PDL2，隔断结构10位于第一像素限定部PDL1和第二像素限定部PDL2之间，隔断结构10和第一像素限定部PDL1之间具有第一凹陷RC1，隔断结构10和第二像素限定部PDL2之间具有第二凹陷RC2。
如图3和图5所示，第一凹陷RC1和第二凹陷RC2被封装层EPS填充。
在本公开的实施例中，如图3至图6所示，封装层EPS包括第一封装层EPS1、第二封装层EPS2、以及第三封装层EPS3。例如，第一封装层EPS1和第三封装层EPS3为无机层，可采用化学气相沉积(CVD)工艺形成。第二封装层EPS2为有机层，可采用喷墨打印工艺形成。如图3至图6所示，第二封装层EPS2的厚度大于第一封装层EPS1的厚度。如图3至图6所示，第二封装层EPS2的厚度大于第三封装层EPS3的厚度。
例如，封装层EPS覆盖整个显示基板，且在隔断结构处覆盖良好，防止发光元件被水氧侵蚀。本公开的实施例提供的隔断结构10，不仅能有效隔断发光功能层中的至少一个子功能层，还不影响封装层的薄膜封装效果。本公开的实施例提供的隔断结构10，不影响封装层EPS的成膜均一性，避免出现封装层的成膜不连续问题，防止发光元件被水汽入侵失效。
如图3和图5所示，因隔断结构10位于第一像素限定部PDL1和第二像 素限定部PDL2之间，且与第一像素限定部PDL1和第二像素限定部PDL2分别具有间隔，突出部PR在衬底基板BS上的正投影与第一电极E1在衬底基板BS上的正投影不交叠。
例如，如图3和图5所示，第二隔断部12的靠近隔断结构10的顶面SF2的部分与顶面SF2之间的夹角A2为锐角，例如，锐角A2大于或等于60度且小于或等于80度。
例如，如图3和图5所示，第二隔断部12的厚度大于第一隔断部11的厚度的二分之一且小于或等于第一隔断部11的厚度。
例如，如图3和图5所示，第二隔断部12的厚度小于第一隔断部11的厚度。
如图3、图5和图7所示，根据本公开的实施例提供的显示基板，在隔断结构10的同一侧，为了提高封装效果，第一隔断部11的侧面和第二隔断部12的侧面之间的夹角A0大于或等于60度且小于或等于150度。例如，为了进一步提高封装效果，第一隔断部11的侧面和第二隔断部12的侧面之间的夹角A0大于90度且小于或等于150度。进一步例如，为了获得更好的封装效果，第一隔断部11的侧面和第二隔断部12的侧面之间的夹角A0大于90度且小于或等于120度。夹角A0的取值与封装效果有关。例如，构成夹角A0的两个边越平缓，越利于提高封装效果。当然，也可以采用其他方式来提高封装效果。
例如，除了调整夹角A0夹角外，降低第二电极E2(例如，阴极)的断线风险和提高封装层中的无机层的连续性。在隔断结构10处，还可以采用二次掩模的方式，增设辅助连接电极以使得不同子像素的第二电极E2相连，或者，也可以使得光耦合层CPL(如图1所示)导电。即，不同子像素的第二电极E2通过导电的光耦合层CPL相连。例如，封装层中的无机层采用化学气相沉积(CVD)方法制作。
例如，如图5和图6所示，第二隔断部12的靠近隔断结构10的顶面SF2的部分(隔断结构10的侧面)与顶面SF2之间的夹角A2为锐角，例如，为了利于隔断发光功能层，夹角A2大于或等于45度且小于或等于75度。例如，呈倒梯形的第二隔断部12的两个底角(夹角A2)中的每一个均大于或等于45度且小于或等于75度。
如图3和图5所示，根据本公开的实施例提供的显示基板，显示基板包括电容C0，电容C0包括极板Ca和极板Cb，电容C0在衬底基板BS上的正投影与隔断结构10在衬底基板BS上的正投影至少部分交叠。当然，在其他实施例或者在其他位置处，也可以是其他的结构或其他导线在衬底基板BS上的正投影与隔断结构10在衬底基板BS上的正投影至少部分交叠。这些与隔断结构10交叠的结构或导线可以位于第三导电图案层LY3。
如图3和图5所示，根据本公开的实施例提供的显示基板，显示基板还包括像素电路PXC，像素电路PXC被配置为驱动发光元件EMC发光，显示基板还包括平坦化层PLN，第一电极E1通过贯穿平坦化层的过孔V0与像素电路PXC相连，第一电极E1和第一隔断部11均位于平坦化层PLN上。
如图7和图8所示，隔断结构10与像素限定图案PDL为一体结构。
如图7和图8所示，像素限定图案PDL包括像素限定子层SL1和像素限定子层SL2。像素限定子层SL1与第一隔断部11为一体结构，像素限定子层SL2与第二隔断部12为一体结构。即，隔断结构10也同时作为像素限定图案PDL。
如图7和图8所示，根据本公开的实施例提供的显示基板，突出部PR在衬底基板BS上的正投影与第一电极E1在衬底基板BS上的正投影至少部分交叠。
如图7和图8所示，第二隔断部12的厚度大于第一隔断部11的厚度。例如，第二隔断部12的厚度为第一隔断部11的厚度的两倍以上。进一步例如，第二隔断部12的厚度为第一隔断部11的厚度的三倍以上。例如，第二隔断部12的厚度与第一隔断部11的厚度之比大于或等于2小于或等于6。
如图3和图5所示，在本公开的实施例中，一个元件的厚度是指该元件在垂直于衬底基板的主表面SF0的方向上的尺寸。图中示出了方向Z。方向Z即为垂直于衬底基板的主表面SF0的方向。如图3和图5所示，衬底基板的主表面SF0为用于制作各个元件的表面。
如图3至图8所示，根据本公开的实施例提供的显示基板，第二隔断部12与第一隔断部11接触。
例如，如图7和图8所示，第一隔断部11和第二隔断部12具有接触面CS，为了利于隔断发光功能层的至少一个子功能层的同时使得第二电极E2在突出部PR处不断开，第二隔断部12的靠近接触面CS的部分与接触面CS之间的夹角A1为钝角。例如，如图7和图8所示，夹角A1大于90度且小于或等于150度。夹角A1也可以采用其他的数值。
例如，如图7和图8所示，为了利于隔断发光功能层，第二隔断部12的靠近隔断结构10的顶面SF2的部分与顶面SF2之间的夹角A2为钝角。例如，为了更好的隔断发光功能层，夹角A2大于110度且小于或等于160度。
例如，如图7和图8所示，根据本公开的实施例提供的显示基板，第一隔断部11的材料包括正性光刻胶，第二隔断部12的材料包括负性光刻胶。从而，可利用正性光刻胶和负性光刻胶的性质来形成隔断结构10。
如图3至图8所示，第二电极E2与隔断结构10的侧面SF3的一部分相接触。如图3至图8所示，第二电极E2与隔断结构10的侧面SF3在隔断结构10的缩窄处接触。
如图3至图6所示，根据本公开的实施例提供的显示基板，第一电极E1和第一隔断部11均与平坦化层PLN接触。
如图7和图8所示，根据本公开的实施例提供的显示基板，第一电极E1和第一隔断部11均与平坦化层PLN2接触。
如图3和图5所示，根据本公开的实施例提供的显示基板，隔断结构10在平行于主表面的平面内的最小尺寸小于相邻子像素SP的第一电极E1之间的间距。
如图3和图5所示，根据本公开的实施例提供的显示基板，隔断结构10在平行于主表面的平面内的最大尺寸大于或等于相邻子像素SP的第一电极E1之间的间距的五分之一。
如图7和图8所示，根据本公开的实施例提供的显示基板，隔断结构10在平行于主表面的平面内的最小尺寸大于相邻子像素SP的第一电极E1之间的间距。
如图3至图6所示，显示基板包括缓冲层BF、栅绝缘层GI1、栅绝缘层GI2、层间绝缘层ILD。
图3和图5还示出了薄膜晶体管T0，薄膜晶体管T0包括栅极GE、有源层ACT、源极Ea、漏极Eb，第一电极E1与漏极Eb相连。薄膜晶体管的源极Ea和漏极Eb在结构上可相同，在称谓上可互换。例如，薄膜晶体管T0可为发光控制晶体管。
图3和图5还示出了电容的第一极板Ca和第二极板Cb。
如图3和图5所示，第一导电图案层LY1包括栅极GE和第一极板Ca，第二导电图案层LY2包括第二极板Cb，第三导电图案层LY3包括源极Ea和漏极Eb。
如图7和图8所示，根据本公开的实施例提供的显示基板，显示基板包括平坦化层PLN1和平坦化层PLN2。
为了清楚起见，在本公开的附图中，没有示出显示基板的所有结构。
图9A为本公开的实施例提供的显示基板的隔断结构处的示意图。图9B为本公开的实施例提供的显示基板的隔断结构处的示意图。
如图9A所示，发光功能层FL在隔断结构10的突出部处断开，形成发光功能部FL1和发光功能部FL2，发光功能部FL2位于隔断结构10上。即，发光功能层FL的每个子功能层均在隔断结构10的突出部处断开。
如图9A所示，第二电极E2在各处连续。即，第二电极E2没有被隔断结构10断开。第二电极E2的材料通常为金属或合金，金属或合金具有较好的爬坡性能。
图9B所示的结构与图9A所示的结构的区别在于：发光功能层FL的一部分子功能层在隔断结构10的突出部处断开，而另一部分子功能层在隔断结 构10的突出部处不断开，形成功能子部FLa和功能子部FLb，功能子部FLa没有断开，而功能子部FLb形成断开的部分FLb1和FLb2。
图10为本公开的实施例提供的显示基板中的发光元件的示意图。如图10所示，根据本公开的实施例提供的显示基板，发光功能层FL包括层叠设置的电荷产生层40、第一发光层41和第二发光层42，第一发光层41位于第一电极E1和电荷产生层40之间，第二发光层42位于第二电极E2和电荷产生层40之间，电荷产生层40在突出部PR处断开。因电荷产生层40在隔断结构10处断开，使得电荷的传播路径较长，发光功能层中的电荷生成层的电阻较大，能有效避免相邻子像素之间的串扰。
例如，在一些实施例中，除了电荷产生层40在突出部PR处断开之外，电荷产生层40和第一电极E1之间的子功能层在突出部PR处也断开，而电荷产生层40和第二电极E2之间的子功能层在突出部PR处不断开。在另一些实施例中，除了电荷产生层40在突出部PR处断开之外，电荷产生层40和第一电极E1之间的子功能层在突出部PR处也断开，而电荷产生层40和第二电极E2之间的子功能层在突出部PR处也断开，该情况下，发光功能层FL的各个子功能层在突出部PR处均断开。
如图10所示，根据本公开的实施例提供的显示基板，发光功能层FL还包括位于第一电极E1和第一发光层41之间的第一电荷传输层51以及位于第一发光层41和电荷产生层40之间的第二电荷传输层52，第一电荷传输层51和第二电荷传输层52在突出部PR处断开。
如图10所示，第一电荷传输层51为空穴传输层HTL，第二电荷传输层52为电子传输层ETL。其余各个结构可参考图1的描述。
图11为本公开一实施例提供的另一种显示基板的平面示意图。根据本公开的实施例提供的显示基板，如图11所示，隔断结构10呈环形，以围绕发光区R0，第二电极E2在隔断结构10的突出部处连续，以利于不同子像素的第二电极E2上的信号传递。隔断结构10的剖视图如之前所示。
如图11所示，每个子像素SP的发光区R0被一个隔断结构10环绕。
图12为本公开一实施例提供的另一种显示基板的平面示意图。根据本公开的实施例提供的显示基板，如图12所示，隔断结构10包括至少一个隔断子结构01，至少一个隔断子结构01在衬底基板BS上的正投影至少环绕发光区R0在衬底基板BS上的正投影的二分之一。
如图12所示，每个子像素SP的发光区R0被三个或四个隔断子结构01环绕。隔断子结构01的个数可根据需要而定。
如图11和图12所示，显示基板包括第一子像素201、第二子像素202、第三子像素203以及第四子像素204。例如，第一子像素201和第三子像素203之一为蓝色子像素，第一子像素201和第三子像素203之另一为红色子像 素，第二子像素202和第四子像素204可为相同颜色的子像素，例如，均为绿色子像素。第一子像素201、第二子像素202、第三子像素203以及第四子像素204的发光颜色可根据需要而定。
例如，如图11和图12所示，一个第一子像素201、一个第二子像素202、一个第三子像素203以及一个第四子像素204构成一个重复单元RP，在一个重复单元RP中，第二子像素202和第四子像素204分设在第一子像素201和第三子像素203的中心连线CL的两侧。图11和图12示出了第一子像素201的中心C1和第三子像素203的中心C2。相应的，第一子像素201和第三子像素203也分设在第二子像素202和第四子像素204的中心连线的两侧。
例如，在其他的实施例中，在相邻的两个子像素之间，仅设置有一个隔断结构，从而可减小相邻两个子像素之间的间隔的宽度，以提高像素密度。
图11和图12还示出了隔垫物50。隔垫物50被配置为在制作发光层时支撑精细金属掩模。
如所示，隔垫物50在第一子像素201、第二子像素202、第三子像素203、以及第四子像素204围设的区域内。
如图12所示，在第二方向Y上排列的第一子像素201和第三子像素203之间设置隔垫物50。
图11和图12示出了方向X和方向Y。方向X与方向Y相交。例如，方向X垂直于方向Y。方向X与方向Y均为平行于衬底基板的主表面的方向。例如，方向Z垂直于方向X，并垂直于方向Y。
图13为一种显示基板中的像素电路和发光元件的示意图。图13以7T1C的像素电路为例进行说明。需要说明的是，像素电路不限于图13所示，可根据需要设置。如图13所示，显示基板包括子像素SP，子像素包括像素电路PXC和发光元件EMC。发光元件EMC包括第一电极E1、第二电极E2、以及位于第一电极E1和第二电极E2之间的发光功能层。像素电路PXC包括晶体管和存储电容Cst。例如，晶体管包括晶体管T1-T7，存储电容Cst包括极板Ca1和极板Cb1。图13还示出了提供扫描信号SCAN的栅线GT、提供数据信号DATA的数据线DT、提供发光控制信号EM的发光控制信号线EML、提供电源电压VDD的电源线PL1、提供电源电压VSS的电源线PL2、提供复位信号RESET的复位控制信号线RST1、提供扫描信号SCAN的复位控制信号线RST2、提供初始化信号Vinit1的初始化信号线INT1、以及提供初始化信号Vinit2的初始化信号线INT2。
例如，如图13所示，晶体管T1为驱动晶体管，晶体管T2为数据写入晶体管，晶体管T3为阈值补偿晶体管，晶体管T4为发光控制晶体管，晶体管T5为发光控制晶体管，晶体管T6为复位控制晶体管，晶体管T7为复位控制晶体管。
图14A为本公开一实施例提供的显示基板的示意图。图14B为本公开另一实施例提供的显示基板的示意图。
如图14A和图14B所示，根据本公开的实施例提供的显示基板，显示基板还包括导电结构30，导电结构30被配置为向像素电路提供信号，导电结构30位于隔断结构10和衬底基板BS之间，导电结构30在衬底基板BS上的正投影与隔断结构10在衬底基板BS上的正投影交叠。例如，导电结构30可位于第三导电图案层LY3，形成导电结构30之后形成隔断结构10。当然，导电结构30也可以位于其他层。例如，对于较低PPI的显示基板，布线位置较充足的情况下，导电结构30也可以与第一电极E1同层。
在一些实施例中，如图14A所示，导电结构30在衬底基板BS上的正投影与隔断结构10在衬底基板BS上的正投影重合。
在一些实施例中，如图14B所示，导电结构30在衬底基板BS上的正投影与隔断结构10在衬底基板BS上的正投影部分交叠。
例如，导电结构30与第二电极E2相连，能够使得该第二电极E2(VSS)的电阻大大降低，使第二电极E2上的压降降低，从而减小显示基板中电源电压VSS与电源电压VDD之间的压差，更好的降低显示基板的功耗。例如，根据IR-Drop仿真结果，第二电极E2(VSS)上的压降可以降低0.5V左右。
例如，根据本公开的实施例提供的显示基板，导电结构30位于相邻子像素SP的发光区R0之间，导电结构30与第二电极E2电连接。导电结构30与第二电极E2的相连位置可位于周边区，但不限于此。例如，周边区可为显示基板的边框区。显示区可为显示基板的显示画面的区域。显示区包括发光区R0和相邻子像素之间的间隔区Ra。例如，周边区位于显示区的至少一侧。例如，周边区围绕显示区。
例如，第二电极E2为发光元件的阴极，第一电极E1为发光元件的阳极。在第二电极E2为整面的连续电极，不被隔断结构10断开的情况下，利于减小第二电极E2的电阻，利于第二电极E2上的信号传递。
在一些实施例中，发光功能层FL的各个子功能层被隔断结构10断开，以利于减轻相邻子像素的串扰，第二电极E2为整面的连续电极，不被隔断结构10断开，利于减小第二电极E2的电阻，利于第二电极E2上的信号传递。
本公开的实施例还提供一种显示装置，包括上述任一显示基板。例如，本公开的实施例中的显示基板也可以称作显示面板。
图15为本公开一实施例提供的一种显示装置的示意图。如图15所示，该显示装置500包括显示基板100。显示基板100即为上述任一的显示基板。
一方面，该显示基板通过在相邻的子像素之间设置隔断结构，并使得发光功能层中的至少一个子功能层，例如，电荷产生层，在隔断结构所在的位置断开，从而避免导电性较高的子功能层(例如，电荷产生层)造成相邻子 像素之间的串扰。由此，包括该显示基板的显示装置因此也可避免相邻子像素之间的串扰，因此具有较高的产品良率和较高的显示品质。
另一方面，由于显示基板可在采用Tandem结构，以提高像素密度。因此，包括该显示基板的显示装置具有寿命长、功耗低、亮度高、分辨率高等优点。
例如，该显示装置可以为有机发光二极管显示装置等显示器件以及包括该显示装置的电视、数码相机、手机、手表、平板电脑、笔记本电脑、导航仪等任何具有显示功能的产品或者部件，本公开的实施例包括但不限于此。
图16A至图16D为本公开的实施例提供的一种显示基板的制作方法的示意图。图17A为负性光刻胶经曝光显影后的截面示意图。图17B为正性光刻胶经曝光显影后的截面示意图。图18A至图18C为本公开的实施例提供的一种显示基板的制作方法的示意图。
参考图3、图5、图7、图16A至图16D以及图18A至图18C，本公开的实施例还提供一种显示基板的制作方法，包括如下步骤。
S11、在衬底基板BS的主表面上形成多个子像素SP，子像素SP包括发光元件EMC，发光元件EMC具有发光区R0，发光元件EMC包括第一电极E1、发光功能层FL、以及第二电极E2，第二电极E2位于发光功能层FL的背离衬底基板BS的一侧，第一电极E1位于发光功能层FL的靠近衬底基板BS的一侧，发光功能层FL包括多个子功能层。
S12、在相邻子像素SP的发光区R0之间形成隔断结构10，形成隔断结构10包括形成层叠设置的第一隔断部11和第二隔断部12，第一隔断部11位于第二隔断部12的靠近衬底基板BS的一侧；第二隔断部12具有突出部PR，突出部PR相对于第一隔断部11的靠近第二隔断部12的一侧突出，发光功能层FL的至少一个子功能层在突出部PR处断开，第一隔断部11的材料包括有机材料，第二隔断部12的材料包括有机材料，沿从第一电极E1指向第二电极E2的方向上，隔断结构10在衬底基板BS上的正投影逐渐减小再逐渐增大。
如图16A至图16D所示，本公开的实施例提供的显示基板的制作方法，包括如下步骤。
S21、如图16A所示，在形成第一电极E1的衬底基板BS上形成像素限定薄膜PDF。
S22、如图16B所示，对像素限定薄膜PDF进行构图，形成像素限定图案以及第一隔断部11。
S23、如图16C所示，在像素限定图案以及第一隔断部11上形成支撑薄膜TF。
S24、如图16D所示，对支撑薄膜TF进行构图，形成第二隔断部12。
例如，第二隔断部12可作为隔垫物以在形成发光层时支撑精细金属掩模。
在第二隔断部12复用为隔垫物的情况下，一方面，仅通过像素限定图案以及隔垫物的形状的变化，即可形成隔断结构10，不增加掩膜数量，利于显示基板的制作。另一方面，隔断结构10在形成第一电极E1之后形成，不影响背板的制作。再一方面，制作隔断结构10的空间较大，利于形成较大尺寸的隔断结构10。
如图17A所示，负性光刻胶在曝光显影后形成的结构上大下小。如图17B所示，正性光刻胶在曝光显影后形成的结构上小下大。可利用正性光刻胶和负性光刻胶的性质，来形成隔断结构，以隔断发光功能层的至少一个子功能层。
如图18A至图18C所示，根据本公开的实施例提供的显示基板的制作方法，形成层叠设置的第一隔断部11和第二隔断部12包括如下步骤。
S01、如图18A所示，形成正性光刻胶薄膜11F。
S02、如图18A所示，在正性光刻胶薄膜11F上形成负性光刻胶薄膜12F。
S03、如图18B所示，对负性光刻胶薄膜12F进行构图形成第二隔断部12。
S04、如图18C所示，以第二隔断部12为掩膜对正性光刻胶薄膜进行构图，形成第一隔断部11，从而形成隔断结构10。
在步骤S04之后，还可包括如下步骤。
S05、形成发光功能层，发光功能层的至少一个功能子层在隔断结构10的突出部处断开。
S06、形成第二电极E2，第二电极E2在隔断结构10的突出部处可断开，也可不断开。
图18B示出了像素限定子层的图形12P，像素限定子层的图形12P包括第二隔断部12。
图18C示出了像素限定子层的图形11P，像素限定子层的图形11P包括第一隔断部11。
例如，正性光刻胶薄膜11F的厚度可为0.5～1μm。例如，第一隔断部11的厚度可为0.5～1μm。
例如，负性光刻胶薄膜12F的厚度可为1.2～2μm。例如，第二隔断部12的厚度可为1.2～2μm。
在步骤S03中，进行第一次曝光，可采用掩膜版遮挡，对负性光刻胶进行曝光，被曝光区域可形成倒梯形的图形。
在步骤S04中，进行第二次曝光，利用负性光刻胶的图形对正性光刻胶再次进行曝光，根据曝光深度，负性光刻胶下的正性光刻胶不被曝光，负性光刻胶未遮挡的正性光刻胶将被曝光后去除。最终形成类似倒葫芦的形状， 以该形状来增大子功能层例如电荷产生层(CGL)的电阻，以减轻发光时相邻子像素之间的串扰。
采用图18A至图18C所示的方法可形成图7所示的显示基板。
如图7和图18C所示，像素限定图案PDL与隔断结构10可以为一体结构。可看成像素限定图案PDL复用为隔断结构10。
对于图18A至图18C所示的制作方法和图7所示的显示基板，具有如下至少之一的效果。
(1)、仅通过像素限定图案的形状的变化，即可形成隔断结构10，不增加掩膜数量，利于显示基板的制作。
(2)、隔断结构10在形成第一电极E1之后形成，不影响背板的制作。
(3)、隔断结构10复用为像素限定图案，与像素限定图案的开口区域一次形成，无需制作新的隔断结构，简化制作工艺。
(4)、隔断结构10采用一个掩膜版制作，利用负性胶形成的第二隔断部12作为正性光刻胶的掩膜，可以避免曝光工艺中的错位(overlay)的问题，从而，适用于很高PPI的显示基板的制作。
在图18A至图18C中，“+”表示正性光刻胶，“-”表示负性光刻胶。光刻胶是指通过紫外光、电子束、离子束、X射线等的照射或辐射，其溶解度发生变化的材料。对于正性光刻胶，被曝光的部分显影后被去除，未被曝光的部分显影后被留下。对于负性光刻胶，被曝光的部分显影后被留下，未被曝光的部分显影后被去除。
负性光刻胶与正性光刻胶主要有以下三点不同。
(1)、曝光显影过程不同，正性光刻胶在曝光区间显影，负性光刻胶则相反，其曝光区间得到保留。
(2)、负性光刻胶和正性光刻胶边界漫射光形成的轮廓不同，漫射形成的轮廓使显影后的图像为下宽上窄的图像，而负性胶相反，为上宽下窄的图像。
(3)、正性光刻胶溶于强碱，显影剂采用碱溶液，而负性光刻胶的显影剂多采用有机溶液(如二甲苯溶液)。
如图18A至图18C所示，正性光刻胶和负性光刻胶采用同一张掩膜版曝光，通过正性光刻胶和负性光刻胶的曝光原理以及显影药液的性质不同来形成倒“葫芦状”的柱状的隔断结构，以该形状来增大发光功能层中的子功能层例如电荷生成层(CGL)的电阻，减轻串扰。
例如，在本公开的实施例中，位于同一层的部件可由同一膜层经同一构图工艺形成。在本公开的实施例中，构图或构图工艺可只包括光刻工艺，或包括光刻工艺以及刻蚀步骤，或者可以包括打印、喷墨等其他用于形成预定图形的工艺。光刻工艺是指包括成膜、曝光、显影等工艺过程，利用光刻胶、 掩模板、曝光机等形成图形。可根据本公开的实施例中所形成的结构选择相应的构图工艺。
例如，在本公开的实施例中，一个部件的厚度是指该部件在垂直于衬底基板的方向上的尺寸。
例如，在本公开的实施例中，衬底基板BS、缓冲层BF、栅绝缘层GI1、栅绝缘层GI2、层间绝缘层ILD、平坦化层PLN、平坦化层PLN1、平坦化层PLN2均采用绝缘材料制作。例如，衬底基板BS的材料包括聚酰亚胺，但不限于此。例如，衬底基板BS可以为柔性衬底基板，以形成柔性显示基板。例如，缓冲层BF、栅绝缘层GI1、栅绝缘层GI2、层间绝缘层ILD的材料包括无机绝缘材料。例如，平坦化层PLN、平坦化层PLN1、平坦化层PLN2的材料包括有机绝缘材料。例如，无机绝缘材料包括氧化硅、氮化硅、氮氧化硅至少之一。例如，有机绝缘材料包括亚克力、聚对苯二甲酸乙二醇酯、聚酰亚胺、聚酰胺、聚碳酸酯、环氧树脂等中的一种或几种的组合。
例如，在本公开的实施例中，栅极GE、第一极板Ca、第二极板Cb、源极Ea和漏极Eb采用金属或合金制作。
例如，在本公开的实施例中，有源层ACT为半导体层，可采用多晶硅或金属氧化物半导体。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (27)

  1. 一种显示基板，包括：
    衬底基板；
    多个子像素，位于所述衬底基板的主表面上，所述子像素包括发光元件，所述发光元件具有发光区，所述发光元件包括第一电极、发光功能层、以及第二电极，所述第二电极位于所述发光功能层的背离所述衬底基板的一侧，所述第一电极位于所述发光功能层的靠近所述衬底基板的一侧，所述发光功能层包括多个子功能层；以及
    隔断结构，位于相邻子像素的发光区之间，并包括层叠设置的第一隔断部和第二隔断部，所述第一隔断部位于所述第二隔断部的靠近所述衬底基板的一侧，
    其中，所述第二隔断部具有突出部，所述突出部相对于所述第一隔断部的靠近所述第二隔断部的一侧突出，所述发光功能层的至少一个子功能层在所述突出部处断开，所述第一隔断部的材料包括有机材料，所述第二隔断部的材料包括有机材料，沿从所述第一电极指向所述第二电极的方向上，所述隔断结构在所述衬底基板上的正投影逐渐减小再逐渐增大。
  2. 根据权利要求1所述的显示基板，其中，所述第二隔断部与所述第一隔断部接触。
  3. 根据权利要求1或2所述的显示基板，其中，所述隔断结构呈葫芦型或沙漏型。
  4. 根据权利要求1-3任一项所述的显示基板，其中，所述隔断结构包括底面、顶面和位于所述底面和所述顶面之间的两个侧面，所述侧面呈V字型，两个V字的底部相对设置。
  5. 根据权利要求1-4任一项所述的显示基板，其中，在所述隔断结构的同一侧，所述第一隔断部的侧面和所述第二隔断部的侧面之间的夹角大于或等于60度且小于或等于150度。
  6. 根据权利要求1-5任一项所述的显示基板，其中，所述第二隔断部的靠近所述隔断结构的顶面的部分与所述顶面之间的夹角为锐角，所述锐角大于或等于60度且小于或等于80度。
  7. 根据权利要求1-6任一项所述的显示基板，其中，所述第二隔断部的靠近所述隔断结构的顶面的部分与所述顶面之间的夹角为钝角，所述钝角大于110度且小于或等于160度。
  8. 根据权利要求1-7任一项所述的显示基板，还包括：
    像素限定图案，包括多个开口，所述开口被配置为限定所述子像素的所述发光区，所述开口被配置为暴露所述第一电极的至少一部分，
    其中，所述像素限定图案包括与所述第一隔断部位于同一层的部分。
  9. 根据权利要求8所述的显示基板，其中，所述像素限定图案与所述第一隔断部至少部分分离，所述像素限定图案与所述第一隔断部均与同一绝缘层接触并位于该绝缘层之上。
  10. 根据权利要求8或9所述的显示基板，其中，所述像素限定图案包括位于两个相邻开口之间的第一像素限定部和第二像素限定部，所述隔断结构位于所述第一像素限定部和所述第二像素限定部之间，所述隔断结构和所述第一像素限定部之间具有第一凹陷，所述隔断结构和所述第二像素限定部之间具有第二凹陷。
  11. 根据权利要求8-10任一项所述的显示基板，其中，所述突出部在所述衬底基板上的正投影与所述第一电极在所述衬底基板上的正投影至少部分交叠。
  12. 根据权利要求8-11任一项所述的显示基板，其中，所述像素限定图案与所述隔断结构为一体结构。
  13. 根据权利要求1-12任一项所述的显示基板，其中，所述第一隔断部的材料包括正性光刻胶，所述第二隔断部的材料包括负性光刻胶。
  14. 根据权利要求1-13任一项所述的显示基板，其中，所述发光功能层包括层叠设置的电荷产生层、第一发光层和第二发光层，所述第一发光层位于所述第一电极和所述电荷产生层之间，所述第二发光层位于所述第二电极和所述电荷产生层之间，所述电荷产生层在所述突出部处断开。
  15. 根据权利要求14所述的显示基板，其中，所述发光功能层还包括位于所述第一电极和所述第一发光层之间的第一电荷传输层以及位于所述第一发光层和所述电荷产生层之间的第二电荷传输层，所述第一电荷传输层和所述第二电荷传输层在所述突出部处断开。
  16. 根据权利要求1-15任一项所述的显示基板，其中，所述隔断结构包括至少一个隔断子结构，所述至少一个隔断子结构在所述衬底基板上的正投影至少环绕所述发光区在所述衬底基板上的正投影的二分之一。
  17. 根据权利要求1-16任一项所述的显示基板，其中，所述隔断结构呈环形，以围绕所述发光区，所述第二电极在所述突出部处连续。
  18. 根据权利要求1-17任一项所述的显示基板，还包括像素电路，其中，所述像素电路被配置为驱动所述发光元件发光，所述显示基板还包括平坦化层，所述第一电极通过贯穿所述平坦化层的过孔与所述像素电路相连，所述第一电极和所述第一隔断部均位于所述平坦化层上。
  19. 根据权利要求18所述的显示基板，其中，所述第一电极和所述第一隔断部均与所述平坦化层接触。
  20. 根据权利要求18或19所述的显示基板，其中，所述像素电路包括电容，所述电容在所述衬底基板上的正投影与所述隔断结构在所述衬底基板 上的正投影至少部分交叠。
  21. 根据权利要求18-20任一项所述的显示基板，还包括导电结构，其中，所述导电结构被配置为向所述像素电路提供信号，所述导电结构位于所述隔断结构和所述衬底基板之间，所述导电结构在所述衬底基板上的正投影与所述隔断结构在所述衬底基板上的正投影交叠。
  22. 根据权利要求21所述的显示基板，其中，所述导电结构位于相邻子像素的发光区之间，所述导电结构与所述第二电极电连接。
  23. 根据权利要求1-22任一项所述的显示基板，其中，所述隔断结构在平行于所述主表面的平面内的最小尺寸大于相邻子像素的第一电极之间的间距。
  24. 根据权利要求1-23任一项所述的显示基板，其中，所述隔断结构在平行于所述主表面的平面内的最大尺寸大于或等于相邻子像素的第一电极之间的间距的五分之一。
  25. 一种显示装置，包括权利要求1-24任一项所述的显示基板。
  26. 一种显示基板的制作方法，包括：
    在衬底基板的主表面上形成多个子像素，所述子像素包括发光元件，所述发光元件具有发光区，所述发光元件包括第一电极、发光功能层、以及第二电极，所述第二电极位于所述发光功能层的背离所述衬底基板的一侧，所述第一电极位于所述发光功能层的靠近所述衬底基板的一侧，所述发光功能层包括多个子功能层；以及
    在相邻子像素的发光区之间形成隔断结构，形成所述隔断结构包括形成层叠设置的第一隔断部和第二隔断部，所述第一隔断部位于所述第二隔断部的靠近所述衬底基板的一侧，
    其中，所述第二隔断部具有突出部，所述突出部相对于所述第一隔断部的靠近所述第二隔断部的一侧突出，所述发光功能层的至少一个子功能层在所述突出部处断开，所述第一隔断部的材料包括有机材料，所述第二隔断部的材料包括有机材料，沿从所述第一电极指向所述第二电极的方向上，所述隔断结构在所述衬底基板上的正投影逐渐减小再逐渐增大。
  27. 根据权利要求26所述的制作方法，其中，形成层叠设置的所述第一隔断部和所述第二隔断部包括：
    形成正性光刻胶薄膜；
    在所述正性光刻胶薄膜上形成负性光刻胶薄膜；
    对所述负性光刻胶薄膜进行构图形成所述第二隔断部；以及
    以所述第二隔断部为掩膜对所述正性光刻胶薄膜进行构图，形成所述第一隔断部。
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