WO2021035442A1 - 显示面板及其制作方法、显示装置 - Google Patents

显示面板及其制作方法、显示装置 Download PDF

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Publication number
WO2021035442A1
WO2021035442A1 PCT/CN2019/102345 CN2019102345W WO2021035442A1 WO 2021035442 A1 WO2021035442 A1 WO 2021035442A1 CN 2019102345 W CN2019102345 W CN 2019102345W WO 2021035442 A1 WO2021035442 A1 WO 2021035442A1
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WIPO (PCT)
Prior art keywords
transparent conductive
substrate
layer
conductive layer
metal layer
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PCT/CN2019/102345
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English (en)
French (fr)
Inventor
李东升
陈小川
杨盛际
黄冠达
王辉
张筱丹
王晏酩
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2019/102345 priority Critical patent/WO2021035442A1/zh
Priority to CN201980001445.2A priority patent/CN112740434B/zh
Priority to US16/958,284 priority patent/US11864420B2/en
Publication of WO2021035442A1 publication Critical patent/WO2021035442A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/85—Arrangements for extracting light from the devices
    • H10K50/856—Arrangements for extracting light from the devices comprising reflective means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80518—Reflective anodes, e.g. ITO combined with thick metallic layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/875—Arrangements for extracting light from the devices
    • H10K59/878—Arrangements for extracting light from the devices comprising reflective means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/10—Transparent electrodes, e.g. using graphene
    • H10K2102/101—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO]
    • H10K2102/102—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO] comprising tin oxides, e.g. fluorine-doped SnO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/10—Transparent electrodes, e.g. using graphene
    • H10K2102/101—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO]
    • H10K2102/103—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO] comprising indium oxides, e.g. ITO

Definitions

  • At least one embodiment of the present disclosure provides a display panel, a manufacturing method thereof, and a display device.
  • the anode structure has a great influence on the brightness of the light emitted by the organic light-emitting layer.
  • An anode with a lower work function is not conducive to the injection of anode holes, and the reflectivity of the anode will also affect the amount of light finally emitted from the light-emitting device, thereby affecting the brightness of the light-emitting device.
  • At least one embodiment of the present disclosure provides a display panel including a substrate, a plurality of pixels, an anode, a light-emitting layer, and a driving circuit; the plurality of pixels are located on one side of the substrate; At least one includes an anode and a light-emitting layer; the anode includes a stack of a first transparent conductive layer and a metal layer, the first transparent conductive layer is located on the side of the metal layer away from the substrate, and the first transparent conductive layer is completely Covering the metal layer, and the orthographic projection of the metal layer on the substrate is within the orthographic projection of the first transparent conductive layer on the substrate; the light-emitting layer is stacked on the anode and is located A side of the first transparent conductive layer away from the metal layer; a driving circuit is located between the substrate and the light-emitting layer, wherein the driving circuit includes a driving transistor and a storage capacitor, and the driving transistor includes A source electrode, a drain electrode and a gate electrode, one of the source electrode
  • the anode further includes a second transparent conductive layer, and the second transparent conductive layer is stacked with the first transparent conductive layer and the metal layer and is located at the Between the metal layer and the driving circuit, the first transparent conductive layer and the second transparent conductive layer completely cover the metal layer, and the orthographic projection of the metal layer on the substrate is located at the The second transparent conductive layer is in an orthographic projection on the substrate.
  • the second transparent conductive layer includes a first surface facing the substrate, opposite to the first surface and located on the first surface away from the substrate.
  • the second surface on one side of the bottom and the side surface intersecting both the first surface and the second surface; the first transparent conductive layer covers the side surface of the second transparent conductive layer and the side surface of the second transparent conductive layer The portion of the second surface that is not covered by the metal layer.
  • the orthographic projection of the first transparent conductive layer on the substrate completely overlaps the projection of the second transparent conductive layer on the substrate.
  • the substrate has a main surface, and the second transparent conductive layer, the first transparent conductive layer, and the metal layer are stacked on the main surface of the substrate
  • the angle between the side surface of the second transparent conductive layer and the main surface of the substrate ranges from 30° to 60°.
  • the substrate has a main surface, the first transparent conductive layer and the metal layer are stacked on the main surface of the substrate, and the first The transparent conductive layer is located on the side of the metal layer away from the substrate; the metal layer includes a first surface facing the substrate, opposite to the first surface, and located far away from the first surface.
  • the second surface on one side of the substrate and the side surface intersecting both the first surface and the second surface; the first transparent conductive layer covers the second surface of the metal layer and the side surface of the metal layer side.
  • the first transparent conductive layer includes a first surface facing the substrate, opposite to the first surface and located on the first surface away from the substrate.
  • the second surface on one side of the bottom and the side surface intersecting the first surface or the second surface; the angle between the side surface of the first transparent conductive layer and the main surface of the substrate is smaller than that of the metal layer The angle between the side surface and the main surface of the substrate.
  • the angle between the side surface of the first transparent conductive layer and the main surface of the substrate ranges from 20° to 50°.
  • the angle between the side surface and the main surface of the substrate ranges from 30° to 60°.
  • the work function of the first transparent conductive layer is greater than the work function of the metal layer.
  • the work function of the material of the first transparent conductive layer is greater than 4.60 eV.
  • the material of the first transparent conductive layer and the material of the second transparent conductive layer both include indium tin oxide (ITO), indium zinc oxide (IZO ) And at least one of aluminum-doped zinc oxide (AZO).
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • AZO aluminum-doped zinc oxide
  • the reflectivity of the metal layer is greater than the reflectivity of the first transparent conductive layer.
  • the reflectivity of the metal layer is greater than or equal to 90%.
  • the material of the metal layer is silver.
  • the thickness of the metal layer is greater than the thickness of the first transparent conductive layer, and the thickness of the metal layer is greater than the thickness of the second transparent conductive layer.
  • a display panel provided in at least one embodiment of the present disclosure includes: a plurality of the anodes distributed at intervals, wherein the light-emitting layer has a continuous overall structure and covers the first transparent electrode layer of the plurality of anodes The second surface of each of the plurality of anodes, the side surface of the first transparent electrode layer of each of the plurality of anodes, and the space between adjacent two of the plurality of anodes; the display panel includes a cathode located on the light-emitting layer The side away from the plurality of anodes.
  • the display panel is a Micro LED display panel or an OLED display panel.
  • the display panel provided in at least one embodiment of the present disclosure further includes a light reflection layer, which is located between the base substrate and the anode and is electrically connected to the anode.
  • the display panel provided by at least one embodiment of the present disclosure further includes a first insulating layer located between the anode and the light reflection layer and including a first via hole, wherein the anode passes through the The first via hole is electrically connected to the light reflection layer.
  • the display panel provided by at least one embodiment of the present disclosure further includes a second insulating layer, and the second insulating layer is located between the light reflective layer and the source electrode and the drain electrode and includes a second via hole, wherein: One of the source electrode and the drain electrode is electrically connected to the light reflection layer through the second via hole.
  • At least one embodiment of the present disclosure further provides a display device, which includes any display panel provided in the embodiments of the present disclosure.
  • At least one embodiment of the present disclosure further provides a manufacturing method of a display panel, the manufacturing method includes: providing a substrate; forming a plurality of pixels on one side of the substrate, wherein at least one of the plurality of pixels includes An anode and a light-emitting layer, the anode includes a first transparent conductive layer and a metal layer that are stacked, the first transparent conductive layer is located on the side of the metal layer away from the substrate, and the first transparent conductive layer completely covers The metal layer, and the orthographic projection of the metal layer on the substrate is located within the orthographic projection of the first transparent conductive layer on the substrate; the light-emitting layer and the anode are stacked and located at the A side of the first transparent conductive layer away from the metal layer; and a drive circuit is formed, wherein the drive circuit is located between the substrate and the anode, and includes a drive transistor and a storage capacitor, and the drive The transistor includes a source, a drain, and a gate, one of the source and the drain is electrical
  • forming the anode includes: forming a first mask on the substrate, wherein the first mask includes a direction perpendicular to the substrate.
  • the first opening and the second opening that are stacked on top of each other and penetrate each other, the orthographic projection of the first opening on the substrate is located within the orthographic projection of the second opening on the substrate, and the first opening Located on a side of the second opening away from the substrate; and using the first mask to form the first transparent conductive layer and the metal layer.
  • the metal layer includes a first surface facing the substrate, a second surface opposite to the first surface, and the first surface and the The side surfaces where the second surfaces all intersect; the first opening has a normal line passing through its center and perpendicular to the substrate; and forming the first transparent conductive layer and the metal layer by using the first mask includes: A metal material source is arranged on the side of the first opening away from the substrate, and the metal material source is used to vaporize to form the metal layer, wherein the metal material from the metal material source passes through the After the first opening and the second opening reach the first position on the substrate furthest from the normal line, the connection between the first position and the metal material source and the substrate Having a first included angle; arranging a first transparent conductive material source on a side of the first opening away from the substrate, using the first transparent conductive material source to vaporize to form the first transparent conductive layer, Wherein, the transparent conductive material from the first transparent conductive material source passes through the first
  • the metal material source is located on the normal line of the first opening, or, in a direction parallel to the substrate, the metal material source and The normal lines are separated by a first distance; in the direction perpendicular to the substrate, the distance between the metal material source and the substrate is the first height; in the direction parallel to the substrate The first transparent conductive material source and the normal line are separated by a second distance; in a direction perpendicular to the substrate, the distance between the first transparent conductive material source and the substrate is The second height; the second distance is greater than the first distance, and the second height is equal to the first height.
  • the manufacturing method provided by at least one embodiment of the present disclosure further includes: forming a second transparent conductive layer on the substrate by using the first mask, wherein the second transparent conductive layer and the first transparent
  • the conductive layer and the metal layer are stacked in a direction perpendicular to the substrate and are located between the metal layer and the driving circuit.
  • the first transparent conductive layer and the second transparent conductive layer completely cover Covering the metal layer, and the orthographic projection of the metal layer on the substrate is within the orthographic projection of the second transparent conductive layer on the substrate; the first mask is used to form the first
  • the two transparent conductive layers include: arranging a second transparent conductive material source on a side of the first opening away from the substrate, and forming the second transparent conductive layer by vapor deposition using the second transparent conductive material source; Wherein, in a direction parallel to the substrate, the second transparent conductive material source is separated from the normal line by a third distance; in a direction perpendicular to the substrate, the second transparent conductive material is The distance between the material source and the substrate is a third height; and the third distance is greater than the first distance and less than the second distance, and the third height is equal to the first height.
  • Fig. 1A is a schematic diagram of a planar structure of three pixels of a display panel provided by an embodiment of the present disclosure
  • Fig. 1B is a schematic cross-sectional view taken along the line A-A' in Fig. 1A;
  • FIG. 1C is a schematic diagram of the principle of a pixel circuit of a display panel provided by an embodiment of the present disclosure
  • FIG. 1D is a circuit diagram of a specific implementation example of a voltage control circuit and a pixel circuit of a display panel provided by some embodiments of the present disclosure
  • 1E is a schematic diagram of a planar structure of three pixels of another display panel provided by an embodiment of the present disclosure
  • Fig. 1F is a schematic cross-sectional view taken along the line D-D' in Fig. 1E;
  • 2A is a schematic diagram of a planar structure of three pixels of another display panel provided by an embodiment of the present disclosure
  • Fig. 2B is a schematic cross-sectional view taken along the line B-B' in Fig. 2A;
  • 2C is a schematic diagram of a planar structure of three pixels of another display panel provided by an embodiment of the present disclosure
  • Fig. 2D is a schematic cross-sectional view taken along the line C-C' in Fig. 2C;
  • FIG. 3 is a schematic diagram of a display device provided by an embodiment of the present disclosure.
  • 4A-4J are schematic diagrams of a method for manufacturing a display panel according to an embodiment of the present disclosure.
  • 5A-5F are schematic diagrams of another method for manufacturing a display panel provided by an embodiment of the present disclosure.
  • the included angle between the side surface of the first transparent conductive layer and the main surface of the substrate in the embodiments of the present disclosure refers to the acute angle between the two, and the angle between the side surface of the metal layer and the main surface of the substrate Angle also refers to the acute angle between the two.
  • the center of the first opening refers to the geometric center of the regular figure.
  • the center of the first opening refers to the center of the circle; when the plane shape of the first opening is a rectangle, the center of the first opening refers to the diagonal of the rectangle. Point of intersection.
  • the center of the first opening refers to a certain position in the central area of the irregular figure. The meaning of the center of the second opening is the same as that of the first opening.
  • the anode is composed of a first chromium metal layer, an aluminum metal layer, a second chromium metal layer, and a molybdenum metal layer (Cr/Al/Cr/Mo) stacked in sequence, and the aluminum metal layer has a higher reflectivity
  • the first chromium metal layer, the second chromium metal layer and the molybdenum metal layer protect the aluminum metal layer, but this also affects the reflectivity of the anode, thereby reducing the light utilization efficiency of the light-emitting device.
  • At least one embodiment of the present disclosure provides a light emitting device, which includes an anode and a light emitting layer.
  • the anode includes a first transparent conductive layer and a metal layer that are stacked; the light-emitting layer and the anode are stacked and located on the side of the first transparent conductive layer away from the metal layer; the work function of the first transparent conductive layer is greater than that of the metal The work function of the layer, and the reflectivity of the metal layer is greater than the reflectivity of the first transparent conductive layer.
  • At least one embodiment of the present disclosure provides a display panel.
  • the display panel includes a substrate, a plurality of pixels, and a driving circuit.
  • a plurality of pixels are located on one side of the substrate, at least one of the plurality of pixels includes a light-emitting device; the light-emitting device includes an anode and a light-emitting layer, and the anode includes a first transparent conductive layer and a metal layer that are stacked.
  • the first transparent conductive layer is located on the side of the metal layer away from the substrate, the first transparent conductive layer completely covers the metal layer, and the orthographic projection of the metal layer on the substrate is located on the first transparent conductive layer.
  • a transparent conductive layer is in the orthographic projection on the substrate; the light-emitting layer is stacked with the anode and is located on the side of the first transparent conductive layer away from the metal layer, wherein the first transparent
  • the work function of the conductive layer is greater than the work function of the metal layer, and the reflectivity of the metal layer is greater than the reflectivity of the first transparent conductive layer
  • a driving circuit is located between the substrate and the anode, wherein, The driving circuit includes a driving transistor and a storage capacitor.
  • the driving transistor includes a source, a drain, and a gate. One of the source and the drain is electrically connected to the anode, and the gate is connected to the anode.
  • the storage capacitor is electrically connected, and the storage capacitor is configured to store a data signal.
  • the anode refers to the electrode connected to the positive electrode of the light-emitting device with the applied driving voltage, and the holes in the anode will move to the light-emitting layer of the light-emitting device under the driving of the applied driving voltage.
  • the cathode refers to the electrode connected to the negative electrode of the light-emitting device and the applied driving voltage. The electrons in the cathode move to the light-emitting layer of the light-emitting device under the driving voltage of the applied driving voltage, and then recombine with the holes from the anode in the light-emitting layer , So that the light-emitting layer emits light.
  • FIG. 1A is a schematic plan view of three pixels of a display panel provided by an embodiment of the present disclosure
  • FIG. 1B is a schematic cross-sectional view taken along the line A-A' in FIG. 1A.
  • the display panel 10 includes an array substrate 110, and the array substrate 110 includes a substrate 1 and a light emitting device located on the substrate 1.
  • the light-emitting device includes an anode 2, a light-emitting layer 4 and a cathode 8.
  • the anode 2 includes a first transparent conductive layer 21 and a metal layer 23 that are stacked, and the first transparent conductive layer 21 is located on the side of the metal layer 23 away from the substrate 1.
  • the light emitting layer 4 is stacked on the anode 2 and is located on the side of the first transparent conductive layer 21 away from the metal layer 23.
  • the light-emitting layer 4 is in direct contact with the first transparent conductive layer 21, and the first transparent conductive layer 21 is in direct contact with the metal layer 23, that is, there is no other layer or structure between the light-emitting layer 4 and the first transparent conductive layer 21, There is no other layer or structure between the first transparent conductive layer 21 and the metal layer 23.
  • the cathode 8 is located on the side of the light-emitting layer 4 away from the anode 2.
  • the display panel 10 further includes a substrate 1 having a main surface 101, and an anode 2, a light emitting layer 4 and a cathode 8 are disposed on the main surface 101 of the substrate 1.
  • the light-emitting layer 4 and the anode 2 are stacked in a direction perpendicular to the main surface 101 of the substrate 1, the first transparent conductive layer 21 and the metal layer 23 are stacked in a direction perpendicular to the main surface 101 of the substrate 1, and the first transparent conductive layer
  • the layer 21 is located on the side of the metal layer 23 away from the substrate 1.
  • the work function of the first transparent conductive layer 21 is greater than the work function of the metal layer 23, and the reflectivity of the metal layer 23 is greater than the reflectivity of the first transparent conductive layer 21.
  • the light emitted by the light-emitting layer 4 is reflected by the anode 2 and then emitted through the cathode to realize display.
  • the work function of the transparent conductive layer 21 is larger than that of the metal layer 23, which is beneficial to improve the hole injection ability of the light-emitting layer, so that the intensity of the light emitted by the light-emitting layer is high; on the other hand, the metal layer 23 has a higher reflectivity. Conducive to improving the efficiency of light utilization. Therefore, the light emission brightness of the display panel 10 is large.
  • the driving circuit includes a voltage control circuit and a pixel circuit.
  • FIG. 1C is a schematic diagram of the principle of a pixel circuit of a display panel provided by an embodiment of the present disclosure.
  • the display panel includes an array substrate 110.
  • the array substrate 110 includes a substrate 1 and a pixel circuit 100 located on the substrate 1.
  • the pixel circuit 100 is located between the substrate 1 and the anode 2, and the pixel circuit 100 includes a driver.
  • the transistor T1 and the storage capacitor Cst; the driving transistor T1 includes a gate G, a first electrode and a second electrode, one of the first electrode and the second electrode is electrically connected to the anode 2, and the gate G is electrically connected to the storage capacitor Cst ,
  • the storage capacitor Cst is configured to store data signals.
  • the drain electrode D of the first electrode and the source electrode S of the second electrode are taken as an example.
  • the first electrode and the second electrode can be interchanged.
  • the array substrate 110 includes a silicon substrate 113.
  • the silicon substrate 113 includes a substrate 1, which is sequentially stacked, and a pixel circuit 430, a light reflection layer 440, and a pixel circuit 430 disposed on the main surface 101 of the substrate 1.
  • the first insulating layer 450 For example, the anode 2, the light emitting layer 4 and the cathode 8 are arranged on the first insulating layer 450, that is, the anode 2, the light emitting layer 4 and the cathode 8 are arranged on the side of the first insulating layer 450 away from the main surface 101 of the substrate 1.
  • the light reflection layer 440 is located between the substrate 1 and the anode 2, is configured to reflect light from the light emitting layer 4, and is electrically connected to the anode 2.
  • the first insulating layer 450 is light-transmissive so that light emitted by the light-emitting layer 4 penetrates therethrough and reaches the light reflection layer 440 to be reflected by the light reflection layer 440.
  • the first insulating layer 450 is located between the anode 2 and the light reflective layer 440 and includes the first via hole 452.
  • the first via hole 452 is filled with a metal member 451, and the light reflection layer 440 is electrically connected to the anode 2 through the first via hole 452 and the metal member 451.
  • the light reflection layer 440 is electrically connected to the metal layer 23 of the anode 2 through the first via 452. That is, the metal member 451 is in contact with the light reflection layer 440 and the metal layer 23 of the anode 2 to electrically connect the two.
  • the light reflective layer 440 is electrically connected to the source S of the driving transistor T1 so that the source S of the driving transistor T1 and the anode 2 are electrically connected.
  • the electrical signal provided by the pixel circuit 430 in the silicon substrate is transmitted to the anode 2 through the light reflective layer 440, thereby improving the light utilization efficiency .
  • the display panel 10 further includes a second insulating layer 460.
  • the second insulating layer 460 is located between the light reflective layer 440 and the source S and the drain D and includes a second via 462; one of the source S and the drain D
  • the second via 462 is electrically connected to the light reflective layer 440, so that one of the source electrode S and the drain electrode D is electrically connected to the anode 2.
  • the light reflection layer 440 may not be provided, and the anode 2 is directly electrically connected to the source S of the driving transistor T1 through the first via 452. In this way, it is not only beneficial to realize the control of the light-emitting device by the pixel circuit 430, but also makes the structure of the display device more compact, which is beneficial to the miniaturization of various devices of the display panel.
  • the metal member 451 is made of a metal material, such as tungsten metal, and the first via filled with tungsten metal is also called a tungsten first via (W-via).
  • W-via tungsten first via
  • the thickness of the first insulating layer 450 is relatively large, the formation of the tungsten first via hole in the first insulating layer 450 can ensure the stability of the conductive path, and since the process of making the tungsten first via is mature, The obtained first insulating layer 450 has good surface flatness, which is beneficial to reduce the contact resistance between the first insulating layer 450 and the anode 2.
  • the tungsten first via is not only suitable for realizing the electrical connection between the first insulating layer 450 and the anode 2, but also for the electrical connection between the light reflection layer 440 and the pixel circuit 430, and other wiring layers. The electrical connection between.
  • the silicon substrate 113 includes a pixel circuit 430, the pixel circuit 430 and the light reflection layer 440 are electrically connected to each other, and the pixel circuit 430 is used to drive the light emitting device to emit light.
  • the pixel circuit 430 includes at least a driving transistor T1 and a switching transistor (not shown in the figure), and the driving transistor T1 and the light reflection layer 440 are electrically connected to each other.
  • the electrical signal for driving the light-emitting device can be transmitted to the anode 2 through the light reflection layer 440, thereby controlling the light-emitting device to emit light.
  • the driving transistor T1 includes a gate electrode G, a source electrode S, and a drain electrode D.
  • the source electrode S of the driving transistor T1 is electrically connected to the light reflection layer 440.
  • the driving transistor T1 When the driving transistor T1 is in the on state, the electrical signal provided by the power line may be transmitted to the anode 2 through the source electrode S and the light reflection layer 440 of the driving transistor T1. Since a voltage difference is formed between the anode 2 and the cathode 8, an electric field is formed between the two, and the organic light-emitting layer 116 emits light under the action of the electric field. It can be understood that, in the driving transistor T1, the positions of the source electrode S and the drain electrode D are interchangeable. Therefore, one of the source electrode S and the drain electrode D and the light reflection layer 440 may be electrically connected to each other.
  • the display panel 10 includes a plurality of sub-pixels (or pixel units).
  • FIG. 7 exemplarily shows three sub-pixels.
  • the three sub-pixels are respectively a red sub-pixel SP1, a green sub-pixel SP2, and a blue sub-pixel SP3.
  • Each sub-pixel corresponds to a sub-pixel area of the array substrate 110. That is, each sub-pixel is provided with an independent light-emitting device and a driving transistor T1.
  • the first insulating layer 450 in the three sub-pixels is integrally formed to facilitate fabrication.
  • the display panel 10 further includes a bonding pad 453, and the bonding pad 453 is used for bonding with a flexible printed circuit board (FPC bonding) or bonding with wiring (wire bonding).
  • the first insulating layer 450 further includes an opening 454 exposing the pad 453, and the arrangement of the opening 454 facilitates the electrical connection and signal communication between the pad 453 and an external circuit.
  • the color of the sub-pixels in the display device is only illustrative, and may also include other colors such as yellow and white.
  • the array substrate 110 includes a plurality of light-emitting elements L located in a display area 130 (area AA) and a pixel circuit 100 coupled to each light-emitting element L in a one-to-one correspondence.
  • the pixel circuit 100 includes a driving transistor.
  • the driving circuit may further include a plurality of voltage control circuits 20 located in a non-display area of the array substrate (a region other than the display area 130 in the array substrate). For example, at least two pixel circuits 100 in a row share one voltage control circuit 20, and the first pole of the driving transistor in a row of pixel circuits 100 is coupled to the common voltage control circuit 20, and the second pole of each driving transistor is connected to the corresponding light emitting circuit.
  • the element L is coupled.
  • the voltage control circuit 20 is configured to output an initialization signal Vinit to the first pole of the driving transistor in response to the reset control signal RE, and control the corresponding light-emitting element L to reset; and in response to the light-emission control signal EM, output the first power signal VDD To the first pole of the driving transistor to drive the light-emitting element L to emit light.
  • the structure of each pixel circuit in the display area 130 can be simplified, and the occupied area of the pixel circuit in the display area 130 can be reduced, so that the display area 130 can be equipped with more pixel circuits and light-emitting elements to achieve high PPI.
  • Organic light emitting display panel is configured to output an initialization signal Vinit to the first pole of the driving transistor in response to the reset control signal RE, and control the corresponding light-emitting element L to reset; and in response to the light-emission control signal EM, output the first power signal VDD To the first pole of the driving transistor to drive the light-emitting element L to emit
  • the voltage control circuit 20 outputs the initialization signal Vinit to the first pole of the driving transistor under the control of the reset control signal RE to control the reset of the corresponding light-emitting element, thereby avoiding the voltage pair applied to the light-emitting element when the previous frame emits light. The effect of the next frame of light, thereby improving the afterimage phenomenon.
  • the array substrate may further include a plurality of pixel units PX located in the display area 130, each pixel unit PX includes a plurality of sub-pixels; each sub-pixel includes a light-emitting element L and a pixel circuit 100 respectively.
  • the pixel unit PX may include three sub-pixels of different colors. The three sub-pixels may be red sub-pixels, green sub-pixels, and blue sub-pixels, respectively.
  • the pixel unit PX may also include 4, 5 or more sub-pixels, which need to be designed and determined according to the actual application environment, which is not limited here.
  • the pixel circuits 100 in at least two adjacent sub-pixels in the same row can share one voltage control circuit 20.
  • all the pixel circuits 100 in the same row may share one voltage control circuit 20.
  • the pixel circuits 100 in two, three or more adjacent sub-pixels in the same row may share one voltage control circuit 20, which is not limited here. In this way, the area occupied by the pixel circuit in the display area 130 can be reduced by sharing the voltage control circuit 20.
  • FIG. 1D is a circuit diagram of a specific implementation example of a voltage control circuit and a pixel circuit of a display panel provided by some embodiments of the present disclosure.
  • the driving transistor T1 in the pixel circuit 100 may be an N-type transistor.
  • the first terminal S may be used as its source and the second terminal D as its drain.
  • the second terminal D can be used as the source and the first terminal S can be used as the drain.
  • the light emitting element L may include an OLED.
  • the anode of the OLED is electrically connected to the second terminal D of the driving transistor T1
  • the cathode of the OLED is electrically connected to the second power terminal VSS.
  • the voltage of the second power terminal VSS is generally a negative voltage or the ground voltage VGND (generally 0V), and the voltage of the initialization signal Vinit can also be set to the ground voltage VGND, which is not limited here.
  • the OLED can be set to Micro OLED or Mini OLED, which is further conducive to the realization of a high PPI organic light emitting display panel.
  • the voltage control circuit 20 may include a first switching transistor M1 and a second switching transistor M2.
  • the gate of the first switch transistor M1 is used to receive the reset control signal RE, the first pole of the first switch transistor M1 is used to receive the initialization signal Vinit, the second pole of the first switch transistor M1 and the second pole of the second switch transistor M2 ⁇ Coupled.
  • the gate of the second switch transistor M2 is used to receive the light emission control signal EM, the first pole of the second switch transistor M2 is used to receive the first power signal VDD, and the second pole of the second switch transistor M2 is connected to the first switch transistor M1.
  • the second pole is coupled.
  • the types of the first switching transistor M1 and the second switching transistor M2 may be different.
  • the first switch transistor M1 is an N-type transistor
  • the second switch transistor M2 is a P-type transistor
  • the first switch transistor M1 is a P-type transistor
  • the second switch transistor M2 is an N-type transistor.
  • the type of the first switching transistor M1 and the second switching transistor M2 can also be the same.
  • the types of the first switching transistor M1 and the second switching transistor M2 need to be designed according to the actual application environment, which is not limited here.
  • the pixel circuit 100 may further include a third switching transistor M3 and a storage capacitor Cst.
  • the gate of the third switch transistor M3 is used to receive the first gate scan signal S1
  • the first pole of the third switch transistor M3 is used to receive the data signal DA
  • the second pole of the third switch transistor M3 is connected to the driving transistor T1.
  • the gate G is coupled.
  • the first terminal of the storage capacitor Cst is coupled to the gate G of the driving transistor T1, and the second terminal of the storage capacitor Cst is coupled to the ground terminal GND.
  • the pixel circuit 100 may further include a fourth switch transistor M4.
  • the gate of the fourth switch transistor M4 is used to receive the second gate scan signal S2, the first pole of the fourth switch transistor M4 is used to receive the data signal DA, and the second pole of the fourth switch transistor M4 is connected to the driving transistor T1.
  • the gate G is coupled.
  • the type of the fourth switching transistor M4 and the third switching transistor M3 are different.
  • the third switch transistor M3 is an N-type transistor
  • the fourth switch transistor M4 is a P-type transistor
  • the fourth switch transistor M4 is an N-type transistor.
  • the pixel circuit 100 may further include a fifth switch transistor M5.
  • the gate of the fifth switch transistor M5 is used to receive the reset control signal VT, the first pole of the fifth switch transistor M5 is coupled to the source S of the driving transistor T1, and the second pole of the fifth switch transistor M5 is connected to the second switch transistor.
  • the second pole of M2 is coupled.
  • the P-type fourth switch transistor M4 when the voltage of the data signal DA is a voltage corresponding to a high gray scale, for example, the P-type fourth switch transistor M4 is turned on to transmit the data signal DA to the gate G of the driving transistor T1, which can avoid data
  • the voltage of the signal DA is affected by, for example, the threshold voltage of the N-type third switching transistor M3.
  • the N-type third switch transistor M3 When the voltage of the data signal DA is a voltage corresponding to a low gray scale, for example, the N-type third switch transistor M3 is turned on to transmit the data signal DA to the gate G of the driving transistor T1, which can prevent the voltage of the data signal DA from being affected.
  • the influence of the threshold voltage of the P-type fourth switching transistor M4. This can increase the voltage range input to the gate G of the driving transistor T1.
  • the work function of the material of the first transparent conductive layer 21 is greater than 4.60 eV, which can increase the work function of the anode 2 and thereby increase the hole injection rate of the light emitting layer 4.
  • the material of the first transparent conductive layer 21 includes at least one of indium tin oxide (ITO), indium zinc oxide (IZO), and aluminum-doped zinc oxide (AZO).
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • AZO aluminum-doped zinc oxide
  • the work functions of these transparent conductive materials are larger than those of some metals.
  • the work function of ITO is about 4.8 eV
  • the work function of IZO is 4.9 eV-5.2 eV
  • the work function of AZO is about 5.2 eV.
  • the work function of silver is about 4.6eV
  • the work function of aluminum is about 4.28eV
  • chromium is about 4.3eV-4.5eV.
  • the reflectivity of the metal layer 23 is greater than or equal to 90%.
  • the material of the metal layer 23 is silver (Ag).
  • the material of the metal layer 23 may also include other metals, such as aluminum (Al).
  • Al aluminum
  • the surface of Al is more likely to be oxidized to form a passivation film, which affects the bonding strength between the metal layer and ITO. Therefore, the bonding strength between Ag and ITO is higher than when Al is used. It should be noted that the material of the metal layer 23 is not limited to the types listed above.
  • the metal layer 23 includes a first surface 231 facing the substrate 1, a second surface 232 opposite to the first surface 231 and located on the side of the first surface 231 away from the substrate 1, and a second surface 232 connected to the first surface 231 and the second surface 231.
  • the first surface 231 of the metal layer 23 is in direct contact with the first transparent conductive layer 21.
  • the first transparent conductive layer 21 covers the first surface 231 and the side surface 233 of the metal layer 23 to prevent the metal layer 23 from contacting the light emitting layer 4, so that only the first transparent conductive layer 21 with a higher work function is in contact with the light emitting layer 4.
  • the metal layer 23 is not in contact with the light-emitting layer 4 to increase the hole injection rate of the light-emitting layer 4.
  • the first transparent conductive layer 21 covers the entire first surface 231 and the entire side surface 233 of the metal layer 23 so that the entire first surface 231 and the entire side surface 233 are not in contact with the light emitting layer 4. That is, as shown in FIGS. 1A and 1B, the orthographic projection of the metal layer 23 on the substrate 1 is within the orthographic projection of the first transparent conductive layer 21 on the substrate 1.
  • the thickness of the metal layer 23 (the thickness in the direction in which the first transparent conductive layer 21 and the metal layer 23 are stacked, that is, the thickness in the direction perpendicular to the main surface of the substrate 1) is greater than that of the first transparent conductive layer 21.
  • Thickness (the thickness in the direction in which the first transparent conductive layer 21 and the metal layer 23 are stacked, that is, the thickness in the direction perpendicular to the main surface of the substrate 1).
  • the thickness of the first transparent conductive layer 21 is less than or equal to 80 angstroms
  • the thickness of the metal layer 23 is greater than or equal to 100 angstroms and less than or equal to 300 angstroms.
  • the thickness of the first transparent conductive layer 21 is too large, the light transmittance of the anode 2 will decrease. If the thickness of the metal layer 23 is too thin, the reflectivity of the anode 2 will decrease, which is not conducive to improving the light utilization efficiency of the light emitting device.
  • the first transparent conductive layer 21 includes a first surface 211 facing the substrate 1, a second surface 212 opposite to the first surface 211 and located on a side of the first surface 211 away from the substrate 1, and a second surface 212 opposite to the first surface 211.
  • the angle ⁇ between the side surface 213 of the first transparent conductive layer 21 and the main surface 101 of the substrate 1 is smaller than that between the side surface 233 of the metal layer 23 and the substrate 1
  • the included angle ⁇ between the main surfaces 101 that is, the slope of the side surface of the metal layer).
  • the display panel 10 includes a plurality of the anodes 2 spaced apart.
  • the light-emitting layer 4 is a continuous overall structure (that is, without discontinuity) and covers the second surface 212 of the first transparent electrode layer 21 of each of the plurality of anodes 2 and the first transparent electrode of each of the plurality of anodes The side surface 213 of the layer 21 and the space between adjacent anodes 2.
  • the cathode 8 is located on the side of the light-emitting layer 4 away from the plurality of anodes 2 and covers the light-emitting layer 4. In this case, the light-emitting layer 4 emits white light.
  • the cathode 8 may have a continuous overall structure as shown in FIG. 1B.
  • the cathode may also include a plurality of parts spaced apart from each other.
  • the slope of the side surface 213 of the first transparent conductive layer 21 is smaller than the slope of the side surface 233 of the metal layer 23, which can avoid the disconnection problem caused by the disconnection of the light emitting layer 4.
  • the slope of the side surface of the first transparent conductive layer may also be equal to or greater than the slope of the side surface of the metal layer.
  • the display panel 10 includes a plurality of pixels and a plurality of anodes 2, each pixel includes a plurality of sub-pixels emitting light of different colors, and each of the plurality of sub-pixels One anode 2 is provided among them.
  • the light-emitting layer 4 includes a plurality of parts, and one of the parts of the light-emitting layer 4 is provided in each of the plurality of sub-pixels.
  • each of the plurality of pixels includes three sub-pixels of red, green and blue, and a plurality of parts of the light-emitting layer 4 are respectively located in the three sub-pixels of red, green, and blue, and emit red, green, and blue light, respectively.
  • Each of the multiple portions of the light-emitting layer 4 covers the second surface 212 of the first transparent electrode layer 21 of the anode 2 and the side surface 213 of the first transparent electrode layer 21 of the anode 2 in the sub-pixel where it is located.
  • the display panel 10 further includes a pixel defining layer 9.
  • the pixel defining layer 9 includes an opening and a main body portion.
  • the opening exposes the light-emitting layer 4, and the main body portion is located between two adjacent sub-pixels to prevent adjacent ones. Crosstalk of light of different colors emitted by sub-pixels.
  • the cathode 8 is located on the side of the light-emitting layer 4 away from the plurality of anodes 2 and covers the light-emitting layer 4 and the pixel defining layer 9.
  • the light-emitting layer 4 is an electroluminescent layer, such as an organic electroluminescent layer or an inorganic electroluminescent layer, for example, including an organic light-emitting diode.
  • the substrate 1 may be a base substrate, such as a quartz substrate, a glass substrate, a flexible substrate, etc., or an insulating layer such as a flat layer. It is not limited to the types listed above, and can be designed as required.
  • FIG. 2A is a schematic plan view of three pixels of another display panel provided by an embodiment of the present disclosure
  • FIG. 2B is a schematic cross-sectional view taken along the line B-B' in FIG. 2A.
  • the difference between the display panel 10 shown in FIG. 2B and the light emitting device shown in FIG. 1B is that the anode 2 further includes a second transparent conductive layer 22.
  • the second transparent conductive layer 22 and the first transparent conductive layer 21 and the metal layer 23 are stacked in a direction perpendicular to the substrate 1 and are located on the side of the metal layer 23 away from the first transparent conductive layer 21.
  • the second transparent conductive layer 22 is located between the metal layer 23 and the driving circuit, the first transparent conductive layer 21 and the second transparent conductive layer 22 completely cover the metal layer 23, and the orthographic projection of the metal layer 23 on the substrate 1 Located in the orthographic projection of the second transparent conductive layer 22 on the substrate 1.
  • the metal layer 23 is in direct contact with the second transparent conductive layer 22, that is, there is no other layer or structure between the metal layer 23 and the second transparent conductive layer 22.
  • the work function of the second transparent conductive layer 22 is greater than the work function of the metal layer 23, and the reflectivity of the metal layer 23 is greater than the reflectivity of the second transparent conductive layer 22.
  • Providing the second transparent conductive layer 22 can further improve the hole injection capability of the light emitting layer 4.
  • the second transparent conductive layer 22 is located on the side of the metal layer 23 close to the substrate 1, for example, is in contact with the first insulating layer 450 Due to the difference between the material of the second transparent conductive layer 22 and the material of the metal layer 23, the bonding strength of the second transparent conductive layer 22 and the first insulating layer 450 is higher than the bonding strength of the metal layer 23 and the first insulating layer 450, thereby The bonding strength between the anode 2 and the first insulating layer 450 can be improved, and the structural stability of the display panel 10 can be improved.
  • the light reflection layer 440 is electrically connected to the second transparent conductive layer 22 of the anode 2 through the first via 452. That is, the metal member 451 is respectively in contact with the light reflective layer 440 and the second transparent conductive layer 22 of the anode 2 to electrically connect the two.
  • the second transparent conductive layer 22 includes a first surface 221 facing the substrate 1, and a second surface 221 opposite to the first surface 221 and located on the side of the first surface 221 away from the substrate 1.
  • the first transparent conductive layer 21 also covers the side surface 223 of the second transparent conductive layer 22 and the portion of the second surface 222 of the second transparent conductive layer 22 that is not covered by the metal layer 23, which is beneficial to reduce the size of the first transparent conductive layer 21.
  • the slope of the side surface 213 is also beneficial to more tightly wrap the metal layer 23 to avoid its influence on the hole injection rate of the light-emitting layer 4. That is, as shown in FIGS.
  • the orthographic projection of the metal layer 23 on the substrate 1 is within the orthographic projection of the first transparent conductive layer 21 on the substrate 1, and the second transparent conductive layer 22 is on the substrate 1.
  • the orthographic projection on 1 is within the orthographic projection of the first transparent conductive layer 21 on the substrate 1.
  • the orthographic projection of the second transparent conductive layer 22 on the substrate 1 completely coincides with the orthographic projection of the first transparent conductive layer 21 on the substrate 1.
  • the thickness of the metal layer 23 (the thickness in the stacking direction of the metal layer 23 and the second transparent conductive layer 22, that is, the thickness in the direction perpendicular to the substrate) is greater than the thickness of the second transparent conductive layer 22 (in the metal layer 23).
  • the thickness of the second transparent conductive layer 22 is less than or equal to 80 angstroms, and the excessive thickness of the second transparent conductive layer 22 may cause the light transmittance to decrease.
  • the material of the second transparent conductive layer 22 includes at least one of indium tin oxide (ITO), indium zinc oxide (IZO), and aluminum-doped zinc oxide (AZO).
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • AZO aluminum-doped zinc oxide
  • the material of the second transparent conductive layer 22 may be the same as the material of the first transparent conductive layer 21.
  • the first transparent conductive layer 21 includes a first surface 211 facing the substrate 1, opposite to the first surface 211 and located on a side of the first surface 211 away from the substrate 1.
  • the main surface 101 of the substrate 1 is away from the first part 214 of the substrate 1 and the second part 215 close to the substrate 1 in the direction.
  • the angle ⁇ between the first portion 214 of the side surface 213 of the first transparent conductive layer 21 and the main surface 101 of the substrate 1 (that is, the slope of the first portion 213) is smaller than that between the side surface 233 of the metal layer 23 and the main surface 101 of the substrate 1.
  • the included angle ⁇ (that is, the slope of the side surface of the metal layer), the included angle ⁇ between the second part 214 of the side surface 213 of the first transparent conductive layer 21 and the main surface 101 of the substrate 1 (that is, the slope of the first part 213) It is smaller than the angle ⁇ between the side surface 233 of the metal layer 23 and the main surface 101 of the substrate 1 (that is, the slope of the side surface of the metal layer) to avoid the disconnection problem caused by the disconnection of the light emitting layer 4 described above.
  • the first insulating layer 450 is substantially parallel to the main surface 101 of the substrate 1, the angle between a certain structure and the main surface 101 of the base substrate 1 can be substantially equal to the structure and the first insulating layer 450.
  • the included angle of the surface away from the substrate 1 is the same for the above-mentioned included angle ⁇ , included angle ⁇ , and included angle ⁇ .
  • FIG. 2B Other features and effects of the light-emitting device shown in FIG. 2B that are not mentioned are the same as those in FIG. 1B, and the pixel circuit structure is also the same as that in FIGS. 1B-1D. Please refer to the previous description, and will not be repeated here.
  • FIG. 2C is a schematic plan view of three pixels of another display panel provided by an embodiment of the present disclosure
  • FIG. 2D is a schematic cross-sectional view taken along the line C-C' in FIG. 2C.
  • the light-emitting device shown in FIG. 2D has the following differences from the light-emitting device in FIG. 2B.
  • the orthographic projection of the first transparent conductive layer 21 on the substrate 1 and the orthographic projection of the second transparent conductive layer 22 on the substrate 1 basically overlap.
  • the first transparent conductive layer 21 in addition to covering the metal layer 23 and the second transparent conductive layer 22, the first transparent conductive layer 21 also covers a part of the main surface 101 of the substrate 1, that is, the second transparent conductive layer 22 is on the substrate 1.
  • the orthographic projection on is located within the orthographic projection of the first transparent conductive layer 21 on the substrate 1 and overlaps with a part of the orthographic projection of the first transparent conductive layer 21 on the substrate 1. Therefore, the first surface 211 of the first transparent conductive layer 21 facing the substrate 1 includes a portion that is in contact with the first insulating layer 450, which is beneficial to more tightly wrap the metal layer 23 to avoid holes in the light-emitting layer 4. The impact of injection rate.
  • the display panel is a Micro LED display panel, such as a Micro OLED display panel.
  • Micro LED display panels have high requirements for luminous intensity.
  • the light-emitting device provided by the embodiments of the present disclosure can increase the hole injection rate of the light-emitting layer, the light emitted by the light-emitting layer has high intensity, and the anode has high reflectivity. , Therefore, the display panel has a higher display brightness.
  • the display panel can also be other types of display panels, such as OLED display panels.
  • FIG. 3 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure. As shown in FIG. 3, the display device 11 provided by the embodiment of the present disclosure includes any display panel 10 provided by the embodiment of the present disclosure.
  • the display device is, for example, a Micro LED display device, an OLED display device, and the like.
  • the display device can be, for example, any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • At least one embodiment of the present disclosure further provides a manufacturing method of a display panel, the manufacturing method includes: providing a substrate; forming a plurality of pixels on one side of the substrate, wherein at least one of the plurality of pixels includes A light-emitting device, the light-emitting device includes an anode and a light-emitting layer; the anode includes a first transparent conductive layer and a metal layer that are stacked, and the first transparent conductive layer is located on the side of the metal layer away from the substrate; the light-emitting layer and The anodes are stacked and located on the side of the first transparent conductive layer away from the metal layer, wherein the work function of the first transparent conductive layer is greater than the work function of the metal layer, and the metal The reflectivity of the layer is greater than the reflectivity of the first transparent conductive layer; and a pixel circuit is formed, wherein the pixel circuit is located between the substrate and the anode, and includes a driving transistor and a storage capacitor, and the driving The transistor includes
  • forming the first transparent conductive layer and the metal layer includes forming a first mask on the substrate and using the first mask to form the first transparent conductive layer and the metal layer.
  • FIGS. 4A to 4I are schematic diagrams of a method for manufacturing a light emitting device according to an embodiment of the present disclosure.
  • the substrate 1 may be, for example, a base substrate, such as a quartz substrate, a glass substrate, a flexible substrate, etc., or an insulating layer such as a flat layer. It is not limited to the types listed above, and can be designed as required.
  • Forming the first mask includes the steps shown in FIGS. 4B to 4C.
  • a base layer 5 is formed on the substrate 1; a photoresist layer 6 is formed on the base layer 5.
  • the base layer 5 is an anti-reflection layer, for example, the material of the base layer 5 is an organic polymer or copolymer. In some embodiments, the material of the base layer 5 is easily highly cross-linked. In some embodiments, the material of the base layer 5 includes a monomer having a hydroxyl group. In some embodiments, the material of the base layer 5 includes monomer units that can undergo hydration when exposed to water with a certain pH value. Unsaturated hydrocarbons are generally easy to hydrate. In some embodiments, the base layer 5 includes monomer units having an alkene, alkyne, or aromatic group.
  • the base layer 5 includes ester, acrylate, or isocyanate monomers. In some embodiments, the base layer 5 is an acrylate polymer or copolymer. In some embodiments, the base layer 5 includes aromatic monomers. In some embodiments, the base layer 5 is a styrene polymer or copolymer. On the one hand, the base layer 5 is easily soluble in the developer to obtain the first opening 50; on the other hand, the anti-reflection effect of the base layer 5 is beneficial to improve the accuracy of the pattern of the first mask.
  • the thickness of the base layer 5 in the direction perpendicular to the substrate 1 can be adjusted as required, for example, according to the thickness of the film layer formed in the first opening 50 in the direction perpendicular to the substrate 1 To determine the thickness of the base layer 5.
  • the thickness of the base layer 5 is greater than or equal to the sum of the thickness of the first transparent conductive layer 21 and the thickness of the metal layer 23 to ensure that the steps of forming the first transparent conductive layer 21 and the metal layer 23 proceed smoothly.
  • the base layer 5 and the photoresist layer 6 shown in FIG. 4B are exposed and developed using a second mask (not shown).
  • the material of the base layer 5 is higher than that of the photoresist layer 6. It is more soluble in the developer to form the first opening 50 in the base layer 5 and the second opening 60 in the photoresist layer 6.
  • the first opening 50 and the second opening 60 are stacked in a direction perpendicular to the substrate 1 and pass through each other, and the orthographic projection of the first opening 50 on the substrate 1 is located within the orthographic projection of the second opening 60 on the substrate 1.
  • the second opening 60 includes a first part and a second part, and the orthographic projection of the first part on the substrate 1 coincides with the orthographic projection of the first opening 50 on the substrate 1, and the second part is on the substrate 1.
  • the orthographic projection and the orthographic projection of the first opening 50 on the substrate 1 do not coincide.
  • the first opening 50 is located on a side of the second opening 60 away from the substrate 1.
  • the first opening 50 has a normal line 1 passing through its center and perpendicular to the substrate 1.
  • Using the first mask to form a metal layer includes: arranging a metal material source 7 on the side of the first opening 50 away from the substrate 1, and using the metal material source 7 to vapor-deposit to form the metal layer, wherein the metal material source is located in the first opening On the normal line l where the center position of 50 is located, in the direction perpendicular to the substrate 1, the distance between the metal material source 7 and the substrate 1 is the first height h 1 .
  • the metal material from the metal material source 7 sequentially passes through the second opening 60 and the first opening 50 and reaches the first position on the substrate 1 that is the farthest from the normal line 1.
  • the substrate 1 is rotated around the normal line 1 or an axis parallel to the normal line 1, thereby forming the metal layer 23 shown in FIG. 4F.
  • the above normal line 1 further passes through the center of the second opening 60.
  • the first opening 50 and the second opening 60 are concentric, for example, the planar shape of the first opening 50 and the planar shape of the second opening 60 Are concentric circles, concentric rectangles, etc.
  • using the first mask to form the metal layer includes: arranging the metal material source 7 on the side of the first opening 50 away from the substrate 1, and using the metal material source 7 to form the metal layer by vapor deposition , Wherein, in the direction parallel to the substrate 1, the metal material source 7 is separated from the normal line 1 by a first distance d 1 , the normal line 1 is perpendicular to the substrate 1, and in the direction perpendicular to the substrate 1, the metal The distance between the material source 7 and the substrate 1 is the first height h 1 .
  • the metal material from the metal material source 7 sequentially passes through the second opening 60 and the first opening 50 and reaches the first position on the substrate 1 that is the farthest from the normal line 1.
  • the substrate 1 is rotated around the normal line 1 or an axis parallel to the normal line 1, thereby forming the metal layer 23 shown in FIG. 4F.
  • using the first mask to form the first transparent conductive layer includes: arranging the first transparent conductive material source 81 on the side of the first opening 50 away from the substrate 1, using the first transparent conductive material The source 81 is vapor-deposited to form the first transparent conductive layer. In the process of evaporating the first transparent conductive material source 81, the transparent conductive material from the first transparent conductive material source 81 sequentially passes through the second opening 60 and the first opening 50 and reaches the normal line of the distance on the substrate 1.
  • the second farthest position where the connection line between the second position and the first transparent conductive material source 81 and the substrate 1 has a second included angle ⁇ 2 , and the second included angle ⁇ 2 is smaller than the first included angle ⁇ 1 .
  • the metal layer 23 includes a first surface 231 facing the substrate 1 in a direction perpendicular to the substrate 1, a second surface 232 opposite to the first surface 231 and located on the side of the first surface 231 away from the substrate 1, and The side surface 233 intersecting both the first surface 231 and the second surface 232.
  • the substrate 1 is rotated about the normal line 1 or an axis parallel to the normal line 1, thereby forming the first transparent conductive layer 21 shown in FIG.
  • the transparent conductive layer 21 covers the second surface 232 and the side surface 233 of the metal layer 23 to prevent the metal layer 23 from contacting the light-emitting layer subsequently formed thereon, so that the work function of the first transparent conductive layer is higher than that of the metal layer. 21 is in contact with the light-emitting layer subsequently formed above it, which is beneficial to increase the hole injection rate of the light-emitting layer and increase the luminous intensity. In this way, the first transparent conductive layer 21 and the metal layer 23 stacked in the direction perpendicular to the substrate 1 of the anode are formed.
  • the first transparent conductive material source 81 is separated from the normal line 1 by a second distance d 2 , and the second distance d 2 is greater than the first distance d 1 ; the first transparent conductive material
  • the distance between the source 81 and the substrate 1 is a second height h 2 , and the second height h 2 is equal to the first height h 1 .
  • the above-mentioned first transparent conductive layer 21 is formed, and the first transparent conductive layer 21 covers the second surface 232 and the side surface 233 of the metal layer 23 to achieve the above technical effect.
  • the embodiment of the present disclosure does not limit the distance between the first transparent conductive material source 81 and the normal line 1, the distance between the first transparent conductive material source 81 and the substrate 1, and the distance between the metal material source 7 and the substrate 1.
  • the design is based on the size of the first opening 50, the size of the second opening 60, and the parameters of the vapor deposition equipment used.
  • the manufacturing method of the light emitting device further includes: after forming the metal layer 23 and the first transparent conductive layer 21, removing the photoresist layer 6 and removing the base layer 5.
  • the photoresist layer 6 is peeled off, and the base layer 5 is dissolved by a developer to remove it.
  • the above method uses the same mask to form the first transparent conductive layer 21 and the metal layer 23 by the vapor deposition method. Compared with the wet etching method, higher manufacturing precision can be achieved, so that the arrays used in the display panel are manufactured. When distributed light-emitting devices, high resolution can be achieved. In addition, the method of removing the photoresist layer 6 and the base layer 5 is simple.
  • the manufacturing method of the light-emitting device further includes: forming the light-emitting layer 4.
  • the light-emitting layer 4 is an electroluminescent layer, such as an organic electroluminescent layer or an inorganic electroluminescent layer, such as an organic diode light-emitting layer.
  • the light-emitting layer 4 is located on the side of the first transparent conductive layer 21 away from the metal layer 23.
  • the work function of the first transparent conductive layer 21 is greater than the work function of the metal layer 23, and the reflectivity of the metal layer 23 is greater than the reflectivity of the first transparent conductive layer 21.
  • the light emitted by the light-emitting layer 4 is reflected by the anode 2 and then emitted through the cathode to realize display.
  • the work function of the transparent conductive layer 21 is larger than that of the metal layer 23, which is beneficial to improve the hole injection ability of the light-emitting layer, so that the intensity of the light emitted by the light-emitting layer is high; on the other hand, the metal layer 23 has a higher reflectivity. Conducive to improving the efficiency of light utilization. Therefore, the light emission brightness of the display panel 10 is large.
  • the display panel 10 includes a plurality of the anodes distributed at intervals.
  • the light-emitting layer 4 has a continuous overall structure (that is, without discontinuity) and covers the second surface 212 of the first transparent electrode layer 21 of each of the plurality of anodes and the side surface 213 of the first transparent electrode layer 21 of each of the plurality of anodes. And the spacing between adjacent anodes 2.
  • the above-mentioned gradient of the side surface 213 of the first transparent conductive layer 21 is smaller than the above-mentioned gradient of the side surface 233 of the metal layer 23, which can avoid the disconnection problem caused by the disconnection of the light-emitting layer 4.
  • the material and work function of the first transparent conductive layer 21 the material and work function of the second transparent conductive layer 22, and the material of the metal layer 23, please refer to the description in the previous embodiment of the light emitting device.
  • a cathode 8 is formed on the side of the light-emitting layer 4 away from the anode 2.
  • the cathode 8 may have a continuous overall structure as shown in FIG. 1B.
  • the cathode may also include a plurality of parts spaced apart from each other.
  • the material of the cathode 8 is a transparent conductive material, for example, the material includes at least one of indium tin oxide (ITO), indium zinc oxide (IZO), and aluminum-doped zinc oxide (AZO).
  • the cathode 8 can be formed by an evaporation method.
  • the same first transparent conductive material source can be used as the evaporation source to form the first transparent conductive layer and the cathode.
  • another manufacturing method provided in an embodiment of the present disclosure further includes: forming a second transparent conductive layer on the substrate, wherein the second transparent conductive layer is stacked with the first transparent conductive layer and the metal layer, and is located on the metal layer. The side of the layer away from the first transparent conductive layer.
  • the second transparent conductive layer can be formed using the first mask. That is, the second transparent conductive layer, the metal layer, and the first transparent conductive layer are formed through the first mask.
  • the method provided in this embodiment is simple to operate, can simplify the process, and improve production efficiency.
  • the steps shown in FIGS. 5A to 5D are executed.
  • the thickness of the base layer 5 is greater than or equal to the sum of the thickness of the first transparent conductive layer 21, the thickness of the metal layer 23, and the thickness of the second transparent conductive layer 22 to ensure The above steps of forming the first transparent conductive layer 21, the metal layer 23, and the second transparent conductive layer 22 proceed smoothly.
  • the thickness of the base layer 5 is greater than the thickness of the base layer 5 in the embodiment shown in FIGS. 4A to 4C.
  • the second transparent conductive material source 82 is disposed on the side of the first opening 50 away from the substrate 1, and the second transparent conductive material source 82 is used to form the second transparent layer by evaporation.
  • the transparent conductive material from the first transparent conductive material source 8 sequentially passes through the second opening 60 and the first opening 50 and reaches the normal line of the distance on the substrate 1.
  • the farthest third position, the third included angle ⁇ 3 is between the line connecting the third position and the first transparent conductive material source 8 and the substrate 1.
  • the second transparent conductive layer 22 includes a first surface 221 facing the substrate 1, a second surface 222 opposite to the first surface 221 and located on the side of the first surface 221 away from the substrate 1, and a second surface 222 opposite to the first surface 221 The side surface 223 that intersects the second surface 222.
  • the second transparent conductive material source 82 is separated from the normal line 1 by a third distance d 3 , and the distance between the second transparent conductive material source 82 and the substrate 1 is the first Three height h 3 . In this way, the second transparent conductive layer 22 is formed.
  • the metal material source 7 is disposed on the side of the first opening 50 away from the substrate 1, and the metal material source 7 is used to form the metal layer by evaporation.
  • the metal material source 7 is located on the normal line 1 perpendicular to the substrate 1 where the center of the first opening 50 is located.
  • the metal material from the metal material source 7 sequentially passes through the second opening 60 and the first opening 50 and reaches the first position on the substrate 1 that is the farthest from the normal line 1.
  • the third included angle ⁇ 3 is smaller than the first included angle ⁇ 1 .
  • the substrate 1 is rotated around the normal line 1 or an axis parallel to the normal line 1, thereby forming the metal layer 23 shown in FIG. 5D, and the metal layer 23 covers the second transparent conductive layer 22 A part of the second surface 222, that is, the metal layer 23 does not completely cover the second surface 222 of the second transparent conductive layer 22.
  • using the first mask to form the metal layer includes: arranging the metal material source 7 on the side of the first opening 50 away from the substrate 1, and using the metal material source 7 to form the metal layer by evaporation.
  • the metal material source 7 in the direction parallel to the substrate 1, the metal material source 7 is separated from the normal line 1 by a first distance d 1 , the normal line 1 is perpendicular to the substrate 1, and in the direction perpendicular to the substrate 1, the metal The distance between the material source 7 and the substrate 1 is the first height h 1 .
  • the third distance d 3 is greater than the first distance d 1 , and the third height h 3 is equal to the first height h 1 , thereby forming the metal layer 23 shown in FIG. 5D, and the metal layer 23 covers the second surface 222 of the second transparent conductive layer 22 A part of the metal layer 23 does not completely cover the second surface 222 of the second transparent conductive layer 22.
  • the first transparent conductive material source 81 is disposed on the side of the first opening 50 away from the substrate 1, and the first transparent conductive material source 81 is used for vapor deposition to form the first transparent conductive layer.
  • the transparent conductive material from the first transparent conductive material source 81 sequentially passes through the second opening 60 and the first opening 50 and reaches the normal line of the distance on the substrate 1.
  • the farthest first position, where the connection line between the first position and the first transparent conductive material source 81 and the substrate 1 has a second included angle ⁇ 2 .
  • the second included angle ⁇ 2 is smaller than the first included angle ⁇ 1.
  • the substrate 1 rotates around the normal line l or an axis parallel to the normal line l, thereby forming the one shown in FIG. 5E
  • the first transparent conductive layer 21 is shown, and the first transparent conductive layer 21 covers the metal layer 23.
  • the second included angle ⁇ 2 is less than or equal to the third included angle ⁇ 3 , so that the first transparent conductive layer 21 also covers the side surface 223 of the second transparent conductive layer 22 and the second surface 222 of the second transparent conductive layer 22
  • the part not covered by the metal layer 23 is beneficial to reduce the slope of the side surface 213 of the first transparent conductive layer 21 and to more tightly wrap the metal layer 23 to avoid its influence on the hole injection rate of the light-emitting layer 4.
  • the second included angle ⁇ 2 is smaller than the third included angle ⁇ 3 , the structure shown in FIG. 5E is formed, and the orthographic projection of the first transparent conductive layer 21 on the substrate 1 and the second transparent conductive layer 22 on the substrate
  • the orthographic projections on 1 basically overlap.
  • the structure shown in FIG. 5F is formed, and the first surface 211 of the first transparent conductive layer 21 facing the substrate 1 except for covering the metal layer 23 and the second In addition to the transparent conductive layer, it also covers a part of the main surface 101 of the substrate 1.
  • the first transparent conductive material source 81 is separated from the normal line 1 by a second distance d 2 , and the second distance d 2 is greater than the first distance d 1 ; the first transparent conductive material
  • the distance between the source 81 and the substrate 1 is a second height h 2 , and the second height h 2 is equal to the first height h 1 and the third height h 3 .
  • the third distance is less than or equal to the second distance d 2 , so as to realize that the first transparent conductive layer 21 also covers the side surface 223 of the second transparent conductive layer 22/the second surface 222 of the second transparent conductive layer 22.
  • the part covered by the metal layer 23 to achieve the above technical effect.
  • the structure shown in FIG. 5E is obtained.
  • the first transparent conductive layer 21, the second transparent conductive layer 22, and the metal layer 23 are stacked in a direction perpendicular to the substrate 1, and the second transparent conductive layer 2 is located on the side of the metal layer 23 away from the first transparent conductive layer 21 .
  • the manufacturing method of the display panel further includes: sequentially forming the light-emitting layer 4 and the cathode 8 using the same process as in FIGS. 4I-4J, please refer to the previous description.
  • the first transparent conductive material source 81 is used as the second transparent conductive material source 82, that is, the same transparent conductive material source is used as the evaporation source to form the first transparent conductive layer and the second transparent conductive layer to simplify the process.
  • the first transparent conductive material source 81 may be used to form the first transparent conductive layer, the second transparent conductive layer and the cathode to further simplify the process.
  • the manufacturing method instead of using the same mask to form the first transparent conductive layer, the metal layer, and the second transparent conductive layer, two masks are used to form the first transparent conductive layer, respectively.
  • the third mask is used to form the above-mentioned metal layer through a patterning process, and the pattern of the third mask corresponds to the pattern of the metal layer; then the fourth mask is used to form the above-mentioned first transparent conductive layer through a patterning process, and the fourth mask is The pattern corresponds to the pattern of the first transparent conductive layer.
  • the second transparent conductive layer is formed through a patterning process using a third mask, and the pattern of the third mask corresponds to the pattern of the second transparent conductive layer; then, the metal layer is formed through a patterning process using a fourth mask.
  • the pattern of the four mask corresponds to the pattern of the metal layer; the third mask is then used to form the above-mentioned first transparent conductive layer through a patterning process, and the pattern of the third mask corresponds to the pattern of the second transparent conductive layer, wherein the fourth mask
  • the mold and the third mask may be the same mask.
  • the array substrate includes a silicon substrate, and the silicon substrate includes the aforementioned substrate 1.
  • the foregoing embodiment of the method for manufacturing a display panel is described by taking the formation of a light-emitting device on the substrate 1 as an example.
  • the display panel is shown in FIG. 1B, and the light-emitting device is formed on the first insulating layer 450.
  • the specific forming method is the same as in the above-mentioned implementation.
  • the process of forming other structures of the array substrate such as forming the driving transistor T1 and other transistors of the pixel circuit, forming the via 452, etc., can be performed by those skilled in the art according to conventional techniques in the art.

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Abstract

一种显示面板(10)及其制作方法、显示装置(11)。显示面板(10)包括：衬底(1)、多个像素和驱动电路。多个像素位于衬底(1)一侧，多个像素中的至少一个包括发光器件；发光器件包括阳极(2)和发光层(4)，阳极(2)包括堆叠设置的第一透明导电层(21)和金属层(23)，第一透明导电层(21)位于金属层(23)的远离衬底(1)的一侧；发光层(4)与阳极(2)堆叠设置，且位于第一透明导电层(21)的远离金属层(23)的一侧，其中，第一透明导电层(21)的功函数大于金属层(23)的功函数，且金属层(23)的反射率大于第一透明导电层(21)的反射率；驱动电路位于衬底（1）和阳极（2）之间，其中，驱动电路包括驱动晶体管（T1）和存储电容(Cst)，驱动晶体管(T1)包括源极(S)、漏极(D)和栅极(G)，源极(S)和漏极(D)之一与阳极(2)电连接，栅极(G)与存储电容(Cst)电连接，存储电容(Cst)配置为存储数据信号。显示面板(10)能够提高发光层(4)的空穴注入能力，使得发光层(4)发出的光的强度高，并提高光的利用效率。

Description

显示面板及其制作方法、显示装置 技术领域
本公开至少一实施例提供一种显示面板及其制作方法、显示装置。
背景技术
在OLED显示和Micro OLED显示领域，有时候对有机发光器件的发光亮度有较高的要求。阳极结构对有机发光层所发出的光的亮度有较大影响。功函数较低的阳极不利于阳极空穴的注入，阳极的反射率也会影响最终从发光器件所出射的光量，从而影响发光器件呈现的亮度。
发明内容
本公开至少一实施例提供一种显示面板，该显示面板包括衬底、多个像素、阳极、发光层和驱动电路；多个像素位于所述衬底的一侧；所述多个像素中的至少一个包括阳极和发光层；阳极包括堆叠设置的第一透明导电层和金属层，所述第一透明导电层位于金属层的远离所述衬底的一侧，所述第一透明导电层完全覆盖所述金属层，且所述金属层在所述衬底上的正投影位于所述第一透明导电层在所述衬底上的正投影内；发光层与所述阳极堆叠设置，且位于所述第一透明导电层的远离所述金属层的一侧；驱动电路位于所述衬底和所述发光层之间，其中，所述驱动电路包括驱动晶体管和存储电容，所述驱动晶体管包括源极、漏极和栅极，所述源极和所述漏极之一与所述阳极电连接，所述栅极与所述存储电容电连接，所述存储电容配置为存储数据信号。
例如，在本公开至少一实施例提供的显示面板中，所述阳极还包括第二透明导电层，第二透明导电层与所述第一透明导电层和所述金属层堆叠设置，且位于所述金属层和所述驱动电路之间，所述第一透明导电层和所述第二透明导电层完全包覆所述金属层，且所述金属层在所述衬底上的正投影位于所述第二透明导电层在所述衬底上的正投影内。
例如，在本公开至少一实施例提供的显示面板中，所述第二透明导电层包括面向所述衬底的第一表面、与该第一表面相对且位于该第一表面的远离所述衬底的一侧的第二表面以及与该第一表面和该第二表面均相交的侧面；所述第一透明导电层覆盖所述第二透明导电层的侧面和所述第二透明导电层的第二表面的未被所述金属层覆盖的部分。
例如，在本公开至少一实施例提供的显示面板中，所述第一透明导电层在所述衬底上的正投影与所述第二透明导电层在所述衬底上的投影完全重叠。
例如，在本公开至少一实施例提供的显示面板中，所述衬底具有主表面，所述第二透明导电层、第一透明导电层和所述金属层堆叠于所述衬底的主表面上，所述第二透明导电层的侧面与所述衬底的主表面之间的夹角范围是30°～60°。
例如，在本公开至少一实施例提供的显示面板中，所述衬底具有主表面，所述第一透明导电层与所述金属层堆叠于所述衬底的主表面上，所述第一透明导电层位于所述金属层的远离所述衬底的一侧；所述金属层包括面向所述衬底的第一表面、与所述第一表面相对且位于所述第一表面的远离所述衬底的一侧的第二表面以及与所述第一表面和所述第二表面均相交的侧面；所述第一透明导电层覆盖所述金属层的第二表面和所述金属层的侧面。
例如，在本公开至少一实施例提供的显示面板中，所述第一透明导电层包括面向所述衬底的第一表面、与该第一表面相对且位于该第一表面的远离所述衬底的一侧的第二表面以及与该第一表面或该第二表面相交的侧面；所述第一透明导电层的侧面与所述衬底的主表面之间的夹角小于所述金属层的侧面的与所述衬底的主表面之间的夹角。
例如，在本公开至少一实施例提供的显示面板中，所述第一透明导电层的侧面与所述衬底的主表面之间的夹角范围是20°～50°，所述金属层的侧面的与所述衬底的主表面之间的夹角范围是30°～60°。
例如，在本公开至少一实施例提供的显示面板中，所述第一透明导电层的功函数大于所述金属层的功函数。
例如，在本公开至少一实施例提供的显示面板中，所述第一透明导电层 的材料的功函数大于4.60eV。
例如，在本公开至少一实施例提供的显示面板中，所述第一透明导电层的材料和所述第二透明导电层的材料均包括铟锡氧化物(ITO)、铟锌氧化物(IZO)和掺铝的氧化锌(AZO)中的至少之一。
例如，在本公开至少一实施例提供的显示面板中，所述金属层的反射率大于所述第一透明导电层的反射率。
例如，在本公开至少一实施例提供的显示面板中，所述金属层的反射率大于等于90％。
例如，在本公开至少一实施例提供的显示面板中，所述金属层的材料为银。
例如，在本公开至少一实施例提供的显示面板中，所述金属层的厚度大于所述第一透明导电层的厚度，且所述金属层的厚度大于所述第二透明导电层的厚度。
例如，在本公开至少一实施例提供的显示面板包括：间隔分布的多个所述阳极，其中，所述发光层为连续的整体结构且覆盖多个所述阳极的所述第一透明电极层的第二表面、多个所述阳极的每个的所述第一透明电极层的侧面以及所述多个阳极中相邻两个之间的间隔；该显示面板包括阴极，位于所述发光层的远离所述多个阳极的一侧。
例如，在本公开至少一实施例提供的显示面板中，所述显示面板为Micro LED显示面板或OLED显示面板。
例如，在本公开至少一实施例提供的显示面板还包括光反射层，光反射层位于所述衬底基板和所述阳极之间，与所述阳极电连接。
例如，本公开至少一实施例提供的显示面板还包括第一绝缘层，第一绝缘层位于所述阳极与所述光反射层之间且包括第一过孔，其中，所述阳极通过所述第一过孔与所述光反射层电连接。
例如，本公开至少一实施例提供的显示面板还包括第二绝缘层，第二绝缘层位于所述光反射层与所述源极、所述漏极之间且包括第二过孔，其中，所述源极和所述漏极之一通过所述第二过孔与所述光反射层电连接。
本公开至少一实施例还提供一种显示装置，该显示装置包括本公开实施 例提供的任意一种显示面板。
本公开至少一实施例还提供一种显示面板的制作方法，该制作方法包括：提供衬底；在所述衬底的一侧形成多个像素，其中，所述多个像素中的至少一个包括阳极和发光层，所述阳极包括堆叠设置的第一透明导电层和金属层，所述第一透明导电层位于金属层的远离所述衬底的一侧，所述第一透明导电层完全覆盖所述金属层，且所述金属层在所述衬底上的正投影位于所述第一透明导电层在所述衬底上的正投影内；发光层与所述阳极堆叠设置，且位于所述第一透明导电层的远离所述金属层的一侧；以及形成驱动电路，其中，所述驱动电路位于所述衬底和所述阳极之间，且包括驱动晶体管和存储电容，所述驱动晶体管包括源极、漏极和栅极，所述源极和所述漏极之一与所述阳极电连接，所述栅极与所述存储电容电连接，所述存储电容配置为存储数据信号。
例如，本公开至少一实施例提供的制作方法中，形成所述阳极包括：在所述衬底上形成第一掩模，其中，所述第一掩模包括在垂直于所述衬底的方向上堆叠且彼此贯通的第一开口和第二开口，所述第一开口在所述衬底上的正投影位于所述第二开口在所述衬底上的正投影内，所述第一开口位于所述第二开口的远离所述衬底的一侧；以及利用所述第一掩模形成所述第一透明导电层和所述金属层。
例如，本公开至少一实施例提供的制作方法中，所述金属层包括面向所述衬底的第一表面、与所述第一表面相对的第二表面和与所述第一表面和所述第二表面均相交的侧面；所述第一开口具有经过其中心且垂直于所述衬底的法线；利用所述第一掩模形成所述第一透明导电层和所述金属层包括：将金属材料源设置于所述第一开口的远离所述衬底的一侧，采用所述金属材料源蒸镀形成所述金属层，其中，来自所述金属材料源的金属材料穿过所述第一开口和所述第二开口后到达所述衬底上的距离所述法线最远的第一位置，所述第一位置与所述金属材料源的连线与所述衬底之间具有第一夹角；将第一透明导电材料源设置于所述第一开口的远离所述衬底的一侧，采用所述第一透明导电材料源蒸镀形成所述第一透明导电层，其中，来自所述第一透明导电材料源的透明导电材料穿过所述第一开口和所述第二开口后到达所述衬 底上的距离所述法线最远的第二位置，所述第二位置与所述第一透明导电材料源的连线与所述衬底之间具有第二夹角；所述第二夹角小于所述第一夹角，且所述衬底围绕所述法线或与所述法线平行的轴线转动，以使所述第一透明导电层覆盖所述金属层的第二表面和所述金属层的侧面。
例如，本公开至少一实施例提供的制作方法中，所述金属材料源位于所述第一开口的所述法线上，或者，在平行于所述衬底的方向上所述金属材料源与所述法线之间间隔开第一距离；在垂直于所述衬底的方向上，所述金属材料源到衬底之间的距离为第一高度；在平行于所述衬底的方向上所述第一透明导电材料源与所述法线之间间隔开第二距离；在垂直于所述衬底的方向上，所述第一透明导电材料源到所述衬底之间的距离为第二高度；所述第二距离大于所述第一距离，所述第二高度等于所述第一高度。
例如，本公开至少一实施例提供的制作方法还包括：利用所述第一掩模在所述衬底上形成第二透明导电层，其中，所述第二透明导电层与所述第一透明导电层和所述金属层在垂直于所述衬底的方向上堆叠，且位于所述金属层和所述驱动电路之间，所述第一透明导电层和所述第二透明导电层完全包覆所述金属层，且所述金属层在所述衬底上的正投影位于所述第二透明导电层在所述衬底上的正投影内；利用所述第一掩模形成所述第二透明导电层包括：将第二透明导电材料源设置于所述第一开口的远离所述衬底的一侧，采用所述第二透明导电材料源蒸镀形成所述第二透明导电层，其中，在平行于所述衬底的方向上所述第二透明导电材料源与所述法线之间间隔开第三距离；在垂直于所述衬底的方向上，所述第二透明导电材料源与所述衬底之间的距离为第三高度；以及所述第三距离大于所述第一距离且小于所述第二距离，所述第三高度等于所述第一高度。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为本公开一实施例提供的一种显示面板的三个像素的平面结构示 意图；
图1B为沿图1A中的A-A’线的一种截面示意图；
图1C为本公开一实施例提供的一种显示面板的像素电路原理示意图；
图1D为本公开一些实施例提供的一种显示面板的电压控制电路和像素电路的具体实现示例的电路图；
图1E为本公开一实施例提供的另一种显示面板的三个像素的平面结构示意图；
图1F为沿图1E中的D-D’线的截面示意图；
图2A为本公开一实施例提供的另一种显示面板的三个像素的平面结构示意图；
图2B为沿图2A中的B-B’线的截面示意图；
图2C为本公开一实施例提供的又一种显示面板的三个像素的平面结构示意图；
图2D为沿图2C中的C-C’线的截面示意图；
图3为本公开一实施例提供的一种显示装置的示意图；
图4A-图4J为本公开一实施例提供的一种显示面板制作方法示意图；
图5A-图5F为本公开一实施例提供的另一种显示面板制作方法示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。以下所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现在该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同， 而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
需要说明的是，本公开实施例中的第一透明导电层的侧面的与衬底的主表面的夹角是指两者所夹的锐角，金属层的侧面的与衬底的主表面的夹角也是指这两者所夹的锐角。
需要说明的是，本公开实施例中，当第一开口的平面形状为规则图形时，第一开口的中心是指该规则图形的几何中心。例如当第一开口的平面形状为圆形，第一开口的中心是指该圆形的圆心；当第一开口的平面形状为矩形时，第一开口的中心是指该矩形的对角线的交点。当第一开口的平面形状为不规则图形时，第一开口的中心是指该不规则图形的中央区域中的某一位置。第二开口的中心的含义与第一开口的相同。
在一种发光器件中，阳极由依次层叠的第一铬金属层、铝金属层、第二铬金属层和钼金属层(Cr/Al/Cr/Mo)构成，铝金属层的反射率较高，第一铬金属层、第二铬金属层和钼金属层保护铝金属层，但是这也影响了的阳极的反射率，从而降低了发光器件的光利用效率。
本公开至少一实施例提供一种发光器件，该发光器件包括：阳极和发光层。阳极包括堆叠设置的第一透明导电层和金属层；发光层与阳极堆叠设置，且位于第一透明导电层的远离金属层的一侧；所述第一透明导电层的功函数大于所述金属层的功函数，且所述金属层的反射率大于所述第一透明导电层的反射率。
本公开至少一实施例提供一种显示面板，该显示面板包括：衬底、多个像素和驱动电路。多个像素位于所述衬底一侧，所述多个像素中的至少一个包括发光器件；发光器件包括阳极和发光层，所述阳极包括堆叠设置的第一透明导电层和金属层，所述第一透明导电层位于金属层的远离所述衬底的一侧，所述第一透明导电层完全覆盖所述金属层，且所述金属层在所述衬底上的正投影位于所述第一透明导电层在所述衬底上的正投影内；发光层与所述阳极堆叠设置，且位于所述第一透明导电层的远离所述金属层的一侧，其中， 所述第一透明导电层的功函数大于所述金属层的功函数，且所述金属层的反射率大于所述第一透明导电层的反射率；驱动电路位于所述衬底和所述阳极之间，其中，所述驱动电路包括驱动晶体管和存储电容，所述驱动晶体管包括源极、漏极和栅极，所述源极和所述漏极之一与所述阳极电连接，所述栅极与所述存储电容电连接，所述存储电容配置为存储数据信号。
需要说明的是，在本公开的实施例中，阳极是指与发光器件的与外加驱动电压的正极相连的电极，阳极中的空穴会在外加驱动电压的驱动下向发光器件的发光层移动。阴极是指与发光器件的与外加驱动电压的负极相连的电极，阴极中的电子会在外加驱动电压的驱动下向发光器件的发光层移动，然后在发光层与来自阳极的空穴进行再结合，从而使发光层发光。
示例性地，图1A为本公开一实施例提供的一种显示面板的三个像素的平面结构示意图，图1B为沿图1A中的A-A’线的截面示意图。如图1A和图1B所示，显示面板10包括阵列基板110，阵列基板110包括衬底1、位于衬底1上的发光器件。发光器件包括阳极2、发光层4和阴极8。阳极2包括堆叠设置的第一透明导电层21和金属层23，第一透明导电层21位于金属层23的远离衬底1的一侧。发光层4与阳极2堆叠设置，且位于第一透明导电层21的远离金属层23的一侧。例如，发光层4与第一透明导电层21直接接触，第一透明导电层21与金属层23直接接触，即发光层4与第一透明导电层21之间不存在任何其他的层或结构，第一透明导电层21与金属层23之间不存在任何其他的层或结构。阴极8位于发光层4的远离阳极2的一侧。例如，显示面板10还包括衬底1，衬底1具有主表面101，阳极2、发光层4和阴极8设置于衬底1的主表面101上。发光层4与阳极2在垂直于衬底1的主表面101的方向上堆叠，第一透明导电层21和金属层23在垂直于衬底1的主表面101的方向上堆叠，第一透明导电层21位于金属层23的远离衬底1的一侧。第一透明导电层21的功函数大于金属层23的功函数，且金属层23的反射率大于第一透明导电层21的反射率。在该发光器件中，发光层4发出的光经阳极2反射后经由阴极射出以实现显示。一方面，透明导电层21功函数比金属层23的大，利于提高发光层的空穴注入能力，使得发光层发出的光的强度高；另一方面，金属层23具有较高的反射率，利于提高光的利用效率。 从而，显示面板10的发光亮度大。
例如，驱动电路包括电压控制电路和像素电路。图1C为本公开一实施例提供的一种显示面板的像素电路原理示意图。参考图1B和图1C，显示面板包括阵列基板110，阵列基板110包括衬底1和位于衬底1上的像素电路100；像素电路100位于衬底1和阳极2之间，像素电路100包括驱动晶体管T1和存储电容Cst；驱动晶体管T1驱动晶体管T1包括栅极G、第一极和第二极，第一极和第二极之一与阳极2电连接，栅极G与存储电容Cst电连接，存储电容Cst配置为存储数据信号。例如图2B中以第一极为漏极D，第二极为源极S为例，第一极和第二极可以互换，在其他实施例中，也可以是第一极为漏极D，第二极为源极S。
如图1B所示，例如，阵列基板110包括硅基板113，例如硅基板113包括依次层叠设置的衬底1、和设置于衬底1的主表面101上的像素电路430、光反射层440和第一绝缘层450。例如，阳极2、发光层4和阴极8设置于第一绝缘层450上，即阳极2、发光层4和阴极8设置于第一绝缘层450的远离衬底1的主表面101的一侧。光反射层440位于衬底1和阳极2之间，配置为反射来自发光4层的光，且与阳极2电连接。例如，第一绝缘层450为透光的以使由发光层4发出的光从中穿透并且到达光反射层440以被光反射层440反射。
例如，第一绝缘层450位于阳极2与光反射层440之间且包括第一过孔452。第一过孔452中填充有金属构件451，光反射层440通过第一过孔452和金属构件451与阳极2电连接。例如，光反射层440通过第一过孔452与阳极2的金属层23电连接。即，金属构件451与光反射层440和阳极2的金属层23接触以将这两者电连接。光反射层440与驱动晶体管T1的源极S电连接从而使得驱动晶体管T1的源极S与阳极2电连接。这样，通过在第一绝缘层450中形成光反射层440和阳极2之间的导电通道，将硅基板中像素电路430提供的电信号通过光反射层440传输到阳极2，提高光的利用效率。
例如，显示面板10还包括第二绝缘层460，第二绝缘层460位于光反射层440与源极S、漏极D之间且包括第二过孔462；源极S和漏极D之一通过第二过孔462与光反射层440电连接，从而实现源极S和漏极D之一与阳 极2电连接。
当然，在其他实施例中，也可以不设置光反射层440，阳极2通过第一过孔452直接与驱动晶体管T1的源极S电连接。通过这种方式，不仅有利于实现像素电路430对发光器件的控制，而且使该显示装置的结构更紧凑，有利于显示面板的各个器件的微型化。
例如，金属构件451由金属材料制成，例如钨金属，由钨金属填充的第一过孔也称为钨第一过孔(W-via)。例如，在第一绝缘层450厚度较大的情况下，在第一绝缘层450中形成钨第一过孔可以保证导电通路的稳定性，而且，由于制作钨第一过孔的工艺成熟，所得到的第一绝缘层450的表面平坦度好，有利于降低第一绝缘层450与阳极2之间的接触电阻。可以理解的是，钨第一过孔不仅适于实现第一绝缘层450与阳极2之间的电连接，还适于光反射层440与像素电路430之间的电连接，以及其他布线层之间的电连接。
例如，硅基板113包括像素电路430，像素电路430与光反射层440彼此电连接，像素电路430用于驱动发光器件发光。像素电路430至少包括驱动晶体管T1和开关晶体管(图中未示出)，驱动晶体管T1与光反射层440之间彼此电连接。由此，驱动发光器件的电信号可通过光反射层440传输到阳极2，从而控制发光器件发光。例如，驱动晶体管T1包括栅电极G、源电极S和漏电极D。例如，驱动晶体管T1的源电极S电连接于光反射层440。在驱动晶体管T1处于开启状态时，由电源线提供的电信号可经过驱动晶体管T1的源电极S和光反射层440传输到阳极2。由于阳极2与阴极8之间形成电压差，在二者之间形成电场，有机发光层116在该电场作用下发光。可以理解的是，驱动晶体管T1中，源电极S和漏电极D的位置可互换，因此，源电极S和漏电极D之一与光反射层440彼此电连接即可。
由于上述硅基板113的制作工艺精度高，有利于形成高硅基板113的显示面板，适合用于制作Micro-OLED或Mini-OLED显示面板。
例如，显示面板10包括多个子像素(或像素单元)，图7中示例性地示出了三个子像素，例如该三个子像素分别为红色子像素SP1、绿色子像素SP2和蓝色子像素SP3。每个子像素对应阵列基板110的一个子像素区。也即是，每个子像素中设置有独立的发光器件和驱动晶体管T1。
例如，三个子像素中的第一绝缘层450为一体形成以方便制作。例如，显示面板10还包括焊盘453，焊盘453用于与柔性印刷电路板绑定(FPC bonding)或者与布线绑定(Wire bonding)。如图1B所示，第一绝缘层450还包括暴露焊盘453的开口454，开口454的设置有利于焊盘453与外界电路之间的电连接和信号连通。该显示装置中子像素的颜色仅为示意性的，还可以包括诸如黄色、白色等其他颜色。
如图1C所示，阵列基板110包括位于显示区域130(AA区)中的多个发光元件L以及与各发光元件L一一对应耦接的像素电路100，像素电路100包括驱动晶体管。并且，驱动电路还可以包括位于阵列基板的非显示区(阵列基板中除显示区域130之外的区域)中的多个电压控制电路20。例如，一行中至少两个像素电路100共用一个电压控制电路20，且一行像素电路100中驱动晶体管的第一极与共用的电压控制电路20耦接，各驱动晶体管的第二极与对应的发光元件L耦接。电压控制电路20被配置为响应于复位控制信号RE，将初始化信号Vinit输出至驱动晶体管的第一极，控制对应的发光元件L复位；以及响应于发光控制信号EM，将第一电源信号VDD输出至驱动晶体管的第一极，以驱动发光元件L发光。通过共用电压控制电路20，可以简化显示区域130中各像素电路的结构，降低显示区域130中像素电路的占用面积，从而可以使显示区域130设置更多的像素电路和发光元件，实现高PPI的有机发光显示面板。并且，电压控制电路20在复位控制信号RE的控制下将初始化信号Vinit输出至驱动晶体管的第一极，控制对应的发光元件复位，从而可以避免上一帧发光时加载于发光元件上的电压对下一帧发光的影响，进而改善残影现象。
例如，该阵列基板还可以包括位于显示区域130的多个像素单元PX，每个像素单元PX包括多个子像素；各子像素分别包括一个发光元件L与一个像素电路100。进一步地，像素单元PX可以包括3个不同颜色的子像素。这3个子像素可以分别为红色子像素、绿色子像素以及蓝色子像素。当然，像素单元PX也可以包括4个、5个或更多的子像素，这需要根据实际应用环境来设计确定，在此不作限定。
例如，可以使同一行中相邻的至少两个子像素中的像素电路100共用一 个电压控制电路20。例如，在一些示例中，如图1C所示，可以使同一行中的所有像素电路100共用一个电压控制电路20。或者，在其他示例中，也可以使同一行中相邻的两个、三个或更多子像素中的像素电路100共用一个电压控制电路20，在此不作限定。这样，通过共用电压控制电路20可以降低显示区域130中像素电路的占用面积。
图1D为本公开一些实施例提供的一种显示面板的电压控制电路和像素电路的具体实现示例的电路图。例如，像素电路100中的驱动晶体管T1可以为N型晶体管，在电流由其第一端S流向第二端D时，可以将第一端S作为其源极，第二端D作为其漏极。在电流由其第二端D流向第一端S时，可以将第二端D作为其源极，第一端S作为其漏极。并且，发光元件L可以包括OLED。这样，OLED的正极与驱动晶体管T1的第二端D电连接，OLED的负极与第二电源端VSS电连接。第二电源端VSS的电压一般为负电压或接地电压VGND(一般为0V)，初始化信号Vinit的电压也可以设置为接地电压VGND，在此不作限定。例如，可以将OLED设置为Micro OLED或Mini OLED，这样进一步有利于实现高PPI的有机发光显示面板。
例如，以一行中包括的两个像素电路100为例，电压控制电路20可以包括第一开关晶体管M1和第二开关晶体管M2。第一开关晶体管M1的栅极用于接收复位控制信号RE，第一开关晶体管M1的第一极用于接收初始化信号Vinit，第一开关晶体管M1的第二极与第二开关晶体管M2的第二极耦接。第二开关晶体管M2的栅极用于接收发光控制信号EM，第二开关晶体管M2的第一极用于接收第一电源信号VDD，第二开关晶体管M2的第二极与第一开关晶体管M1的第二极耦接。
例如，可以使第一开关晶体管M1与第二开关晶体管M2的类型不同。例如，第一开关晶体管M1为N型晶体管，第二开关晶体管M2为P型晶体管。或者，第一开关晶体管M1为P型晶体管，第二开关晶体管M2为N型晶体管。当然，也可以使第一开关晶体管M1与第二开关晶体管M2的类型相同。在实际应用中，需要根据实际应用环境来设计第一开关晶体管M1与第二开关晶体管M2的类型，在此不作限定。
例如，像素电路100还可以包括第三开关晶体管M3和存储电容Cst。例 如，第三开关晶体管M3的栅极用于接收第一栅极扫描信号S1，第三开关晶体管M3的第一极用于接收数据信号DA，第三开关晶体管M3的第二极与驱动晶体管T1的栅极G耦接。存储电容Cst的第一端与驱动晶体管T1的栅极G耦接，存储电容Cst的第二端与接地端GND耦接。
例如，像素电路100还可以包括第四开关晶体管M4。例如，第四开关晶体管M4的栅极用于接收第二栅极扫描信号S2，第四开关晶体管M4的第一极用于接收数据信号DA，第四开关晶体管M4的第二极与驱动晶体管T1的栅极G耦接。并且，第四开关晶体管M4与第三开关晶体管M3的类型不同。例如，第三开关晶体管M3为N型晶体管，第四开关晶体管M4为P型晶体管；或者，第三开关晶体管M3为P型晶体管，第四开关晶体管M4为N型晶体管。
例如，像素电路100还可以包括第五开关晶体管M5。第五开关晶体管M5的栅极用于接收复位控制信号VT，第五开关晶体管M5的第一极与驱动晶体管T1的源极S耦接，第五开关晶体管M5的第二极与第二开关晶体管M2的第二极耦接。
需要说明的是，在数据信号DA的电压为高灰阶对应的电压时，通过例如P型的第四开关晶体管M4导通以将数据信号DA传输给驱动晶体管T1的栅极G，可以避免数据信号DA的电压受例如N型的第三开关晶体管M3的阈值电压的影响。在数据信号DA的电压为低灰阶对应的电压时，通过例如N型的第三开关晶体管M3导通以将数据信号DA传输给驱动晶体管T1的栅极G，可以避免数据信号DA的电压受例如P型的第四开关晶体管M4的阈值电压的影响。这样可以提高输入到驱动晶体管T1的栅极G上的电压范围。
例如，第一透明导电层21的材料的功函数大于4.60eV，这能够提高阳极2的功函数，从而提高发光层4的空穴注入率。
例如，第一透明导电层21的材料包括铟锡氧化物(ITO)、铟锌氧化物(IZO)和掺铝的氧化锌(AZO)中的至少之一。这几种透明导电材料的功函数较大，大于一些金属的功函数。例如，ITO的功函数约为4.8eV，IZO的功函数为4.9eV-5.2eV，AZO的功函数约为5.2eV。例如银的功函数约为 4.6eV，铝的功函数约为4.28eV，铬的功函数约为4.3eV-4.5eV。
例如，金属层23的反射率大于等于90％。例如，金属层23的材料为银(Ag)。当然，在其他实施例中，金属层23的材料也可以包括其他金属，例如铝(Al)。Al的表面更容易被氧化而形成钝化膜而影响金属层与ITO的结合强度，因此与采用Al相比，Ag与ITO的结合强度更高。需要说明的是，金属层23的材料不限于以上列举种类。
金属层23包括面向衬底1的第一表面231、与该第一表面231相对且位于该第一表面231的远离衬底1的一侧的第二表面232和与第一表面231和第二表面232均相交的侧面233。例如，金属层23的第一表面231与第一透明导电层21直接接触。第一透明导电层21覆盖金属层23的第一表面231和侧面233，以防止金属层23与发光层4接触，从而，只有功函数较高的第一透明导电层21与发光层4接触而金属层23不与发光层4接触，以提高发光层4的空穴注入率。例如，第一透明导电层21覆盖金属层23的整个第一表面231和整个侧面233以使整个第一表面231和整个侧面233不与发光层4接触。即，如图1A和图1B所示，金属层23在衬底1上的正投影位于第一透明导电层21在衬底1上的正投影内。
例如，金属层23的厚度(在第一透明导电层21和金属层23堆叠设置的方向上的厚度，即在垂直于衬底1的主表面方向上的厚度)大于第一透明导电层21的厚度(在第一透明导电层21和金属层23堆叠设置的方向上的厚度，即在垂直于衬底1的主表面方向上的厚度)。例如，第一透明导电层21的厚度小于等于80埃，金属层23的厚度大于等于100埃且小于等于300埃。第一透明导电层21的厚度过大会导致阳极2的透光率降低，金属层23的厚度过薄会导致阳极2的反射率降低，不利于提高发光器件的光利用率。
例如，第一透明导电层21包括面向衬底1的第一表面211、与该第一表面211相对且位于该第一表面211的远离衬底1的一侧的第二表面212和与该第一表面211和第二表面212均相交的侧面213。例如，第一透明导电层21的侧面213与衬底1的主表面101之间的夹角α(即第一透明导电层的侧面的坡度)小于金属层23的侧面233的与衬底1的主表面101之间的夹角β(即金属层的侧面的坡度)。如图1B所示，例如，显示面板10包括间隔分 布的多个所述阳极2。发光层4为连续的整体结构(即无间断)且覆盖多个所述阳极2的每个的第一透明电极层21的第二表面212和多个所述阳极的每个的第一透明电极层21的侧面213以及相邻阳极2之间的间隔。阴极8位于发光层4的远离多个阳极2的一侧，且覆盖发光层4。这种情况下，发光层4发白光。例如，阴极8可以是如图1B所示的连续的整体结构，在其他实施例中，阴极也可以包括彼此间隔分布的多个部分。在这种情况下，第一透明导电层21的侧面213的坡度小于金属层23的侧面233的坡度，可以避免发光层4断开而导致的断路问题。当然，在其他实施例中，上述第一透明导电层的侧面的坡度也可以等于或者大于上述金属层的侧面的坡度。
例如，在另一个实施例中，如图1E和1F所示，显示面板10包括多个像素和多个阳极2，每个像素包括多个发不同颜色的光的子像素，多个子像素的每个中设置一个阳极2。发光层4包括多个部分，多个子像素的每个中设置发光层4的多个部分中的一个。例如，多个像素的每个包括红绿蓝三个子像素，发光层4的多个部分分别位于红、绿、蓝三个子像素中，且分别发红光、绿光和蓝光。发光层4的多个部分的每个覆盖其所在的子像素中的阳极2的第一透明电极层21的第二表面212以及覆盖该阳极2的第一透明电极层21的侧面213。这种情况下，例如显示面板10还包括像素界定层9，像素界定层9包括开口和主体部，开口暴露发光层4，主体部位于多个子像素中相邻的两个之间以防止相邻子像素所发出的不同颜色的光的串扰。阴极8位于发光层4的远离多个阳极2的一侧，覆盖发光层4和像素界定层9。
例如，在本公开的实施例中，发光层4为电致发光层，例如为有机电致发光层或无机电致发光层，例如包括有机发光二极管。
例如，在本公开的实施例中，衬底1可以是衬底基板，例如石英基板、玻璃基板、柔性基板等，也可以是平坦层等绝缘层。不限于以上列举种类，可根据需要设计。
图2A为本公开一实施例提供的另一种显示面板的三个像素的平面结构示意图，图2B为沿图2A中的B-B’线的截面示意图。图2B所示的显示面板10与图1B所示的发光器件的区别在于，阳极2还包括第二透明导电层22。第二透明导电层22与第一透明导电层21和金属层23在垂直于衬底1的方向 上堆叠设置，且位于金属层23的远离第一透明导电层21的一侧。例如，第二透明导电层22位于金属层23和驱动电路之间，第一透明导电层21和第二透明导电层22完全包覆金属层23，且金属层23在衬底1上的正投影位于第二透明导电层22在衬底1上的正投影内。例如，金属层23与第二透明导电层22直接接触，即金属层23与第二透明导电层22之间不存在任何其他的层或结构。第二透明导电层22的功函数大于金属层23的功函数，且金属层23的反射率大于第二透明导电层22的反射率。设置第二透明导电层22可以进一步提高发光层4的空穴注入能力，此外，例如，第二透明导电层22位于金属层23的靠近衬底1的一侧，例如与第一绝缘层450接触，由于第二透明导电层22的材料与金属层23的材料的差异，第二透明导电层22与第一绝缘层450的结合强度高于金属层23与第一绝缘层450的结合强度，从而能够提高阳极2与第一绝缘层450的结合强度，提高显示面板10的结构稳定性。
例如，在图2B所示的实施例中，光反射层440通过第一过孔452与阳极2的第二透明导电层22电连接。即，金属构件451分别与光反射层440和阳极2的第二透明导电层22接触以将这两者电连接。
例如，如图2B所示，第二透明导电层22包括面向衬底1的第一表面221、与该第一表面221相对且位于该第一表面221的远离衬底1的一侧的第二表面222和与该第二表面222相交的侧面223。第一透明导电层21还覆盖第二透明导电层22的侧面223和第二透明导电层22的第二表面222的未被金属层23覆盖的部分，这有利于减小第一透明导电层21的侧面213的坡度，还有利于更加严密地包裹金属层23，以避免其对发光层4的空穴注入率的影响。即，如图2A和图2B所示，金属层23在衬底1上的正投影位于第一透明导电层21在衬底1上的正投影内，并且，第二透明导电层22在衬底1上的正投影位于第一透明导电层21在衬底1上的正投影内。例如，第二透明导电层22在衬底1上的正投影与第一透明导电层21在衬底1上的正投影完全重合。
例如，金属层23的厚度(在金属层23与第二透明导电层22堆叠方向上的厚度，即在垂直于衬底方向上的厚度)大于第二透明导电层22的厚度(在金属层23与第二透明导电层22堆叠方向上的厚度，即在垂直于衬底方向上的厚度)。例如，第二透明导电层22的厚度小于等于80埃，第二透明导电 层22过厚度过大会导致透光率降低。
例如，第二透明导电层22的材料包括铟锡氧化物(ITO)、铟锌氧化物(IZO)和掺铝的氧化锌(AZO)中的至少之一。例如，第二透明导电层22的材料可以与第一透明导电层21的材料相同。
例如，在图2B所示的实施例中，第一透明导电层21包括面向衬底1的第一表面211、与该第一表面211相对且位于该第一表面211的远离衬底1的一侧的第二表面212和与该第一表面211和第二表面212均相交的侧面213。由于第二透明导电层22和金属层23具有高度差，且第二透明导电层22的第一表面221包括未被金属层23覆盖的部分，第一透明导电层21的侧面213包括在垂直于衬底1的主表面101的方向上远离衬底1的第一部分214和靠近衬底1的第二部分215。第一透明导电层21的侧面213的第一部分214与衬底1的主表面101之间的夹角α(即第一部分213的坡度)小于金属层23的侧面233与衬底1的主表面101的夹角β(即金属层的侧面的坡度)，第一透明导电层21的侧面213的第二部分214与衬底1的主表面101之间的夹角θ(即第一部分213的坡度)小于金属层23的侧面233与衬底1的主表面101之间的夹角β(即金属层的侧面的坡度)，以避免上述发光层4断开而导致的断路问题。需要说明的是，当第一绝缘层450与衬底1的主表面101基本平行，某结构与衬底基板1的主表面101之间的夹角基本可等同于该结构与第一绝缘层450的远离衬底1的表面的夹角，对于上述夹角α、夹角β和夹角θ均是如此。
图2B所示的发光器件的未提及的其他特征及效果均与图1B中的相同，像素电路结构也与图1B-1D中的相同，请参考之前的描述，在此不再重复。
图2C为本公开一实施例提供的又一种显示面板的三个像素的平面结构示意图，图2D为沿图2C中的C-C’线的截面示意图。图2D所示的发光器件与图2B中的发光器件具有以下区别。在图2B中，第一透明导电层21在衬底1上的正投影与第二透明导电层22在衬底1上的正投影基本重叠。在图2C中，第一透明导电层21除了覆盖金属层23和第二透明导电层22之外，还覆盖衬底1的主表面101的一部分，即，第二透明导电层22在衬底1上的正投影位于第一透明导电层21在衬底1上的正投影内且与第一透明导电层 21在衬底1上的正投影的一部分重叠。从而，第一透明导电层21的面向衬底1的第一表面211包括与第一绝缘层450接触的部分，这有利于更加严密地包裹金属层23，以避免其对发光层4的空穴注入率的影响。
例如，显示面板为Micro LED显示面板，例如Micro OLED显示面板。Micro LED显示面板对发光强度的要求较高，采用本公开实施例提供的发光器件，能够提高发光层的空穴注入率，发光层发出的光的强度高，同时，阳极具有较高的反射率，因此，显示面板具有较高的显示亮度。并且，当然，显示面板也可以为其他种类的显示面板，例如OLED显示面板等。
本公开至少一实施例还提供一种显示装置，该显示装置包括本公开实施例提供的任意一种显示面板。图3为本公开一实施例提供的一种显示装置的结构示意图。如图3所示，本公开实施例提供的显示装置11包括本公开实施例提供的任意一种显示面板10。
该显示装置例如为Micro LED显示装置、OLED显示装置等。该显示装置例如可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开至少一实施例还提供一种显示面板的制作方法，该制作方法包括：提供衬底；在所述衬底的一侧形成多个像素，其中，所述多个像素中的至少一个包括发光器件，发光器件包括阳极和发光层；所述阳极包括堆叠设置的第一透明导电层和金属层，所述第一透明导电层位于金属层的远离所述衬底的一侧；发光层与所述阳极堆叠设置，且位于所述第一透明导电层的远离所述金属层的一侧，其中，所述第一透明导电层的功函数大于所述金属层的功函数，且所述金属层的反射率大于所述第一透明导电层的反射率；以及形成像素电路，其中，所述像素电路位于所述衬底和所述阳极之间，且包括驱动晶体管和存储电容，所述驱动晶体管包括源极、漏极和栅极，所述源极和所述漏极之一与所述阳极电连接，所述栅极与所述存储电容电连接，所述存储电容配置为存储数据信号。
例如，形成第一透明导电层和金属层包括：在衬底上形成第一掩模以及利用第一掩模形成第一透明导电层和金属层。
示例性地，图4A-图4I为本公开一实施例提供的一种发光器件制作方法 示意图。
如图4A所示，提供衬底1。衬底1例如可以是衬底基板，例如石英基板、玻璃基板、柔性基板等，也可以是平坦层等绝缘层。不限于以上列举种类，可根据需要设计。
形成第一掩模包括图4B-图4C所示的步骤。
如图4B所示，在衬底1上形成基底层5；在基底层5上形成光刻胶层6。例如，基底层5为抗反射层，例如，基底层5的材料是有机聚合物或共聚物。在一些实施例中，基底层5的材料易于高度交联。在一些实施例中，基底层5的材料包括具有羟基基团的单体。在一些实施例中，基底层5的材料包括当暴露于一定pH值的水中时，能够进行水合作用的单体单元。不饱和碳氢化合物通常易于水合。在一些实施例中，基底层5包括具有烯烃、炔烃或芳族基团的单体单元。在一些实施例中，基底层5包括酯、丙烯酸酯、或异氰酸酯单体。在一些实施例中，基底层5是丙烯酸酯聚合物或共聚物。在一些实施例中，基底层5包括芳族单体。在一些实施例中，基底层5是苯乙烯聚合物或共聚物。一方面，利用了基底层5易溶于显影液的性质，从而得到第一开口50；另一方面，基底层5的抗反射作用利于提高上述第一掩模的图案的精度。
需要说明的是，基底层5的在垂直于衬底1方向上的厚度可以根据需要进行调节，例如可以根据后续在第一开口50中形成的膜层的在垂直于衬底1方向上的厚度来确定基底层5的厚度。例如，基底层5的厚度大于等于第一透明导电层21的厚度和金属层23的厚度之和，以保证上述形成第一透明导电层21和金属层23的步骤顺利进行。
如图4C所示，利用第二掩模(图未示出)对图4B所示的基底层5和光刻胶层6进行曝光、显影，基底层5的材料比光刻胶层6的材料更易溶于显影液以在基底层5中而形成第一开口50，在光刻胶层6中形成第二开口60。第一开口50与第二开口60在垂直于衬底1的方向上堆叠且彼此贯通，第一开口50在衬底1上的正投影位于第二开口60在衬底1上的正投影内，并且，第二开口60包括第一部分和第二部分，该第一部分在衬底1上的正投影与第一开口50在衬底1上的正投影重合，该第二部分在衬底1上的正投影与第一 开口50在衬底1上的正投影不重合。第一开口50位于第二开口60的远离衬底1的一侧。
然后，如图4D所示，第一开口50具有经过其中心且垂直于衬底1的法线l。利用第一掩模形成金属层包括：将金属材料源7设置于第一开口50的远离衬底1的一侧，采用金属材料源7蒸镀形成金属层，其中，金属材料源位于第一开口50的中心位置所在的法线l上，在垂直于衬底1的方向上，金属材料源7与衬底1之间的距离为第一高度h 1。在对金属材料源7进行蒸镀的过程中，来自金属材料源7的金属材料依次穿过第二开口60和第一开口50后到达衬底1上的距离法线l最远的第一位置，该第一位置与金属材料源7的连线与衬底1之间具有第一夹角θ 1。在蒸镀金属材料源7的过程中，衬底1是绕法线l或与法线l平行的轴线旋转的，从而形成图4F所示的金属层23。例如，上述法线l还进一步通过第二开口60的中心，这种情况下，第一开口50和第二开口60是同心的，例如第一开口50的平面形状与第二开口60的平面形状是同心圆、同心矩形等。
或者，如图4E所示，利用第一掩模形成金属层包括：将金属材料源7设置于第一开口50的远离衬底1的一侧，采用金属材料源7蒸镀形成所述金属层，其中，在平行于衬底1的方向上金属材料源7与法线l之间间隔开第一距离d 1，法线l垂直于衬底1，在垂直于衬底1的方向上，金属材料源7到衬底1之间的距离为第一高度h 1。在对金属材料源7进行蒸镀的过程中，来自金属材料源7的金属材料依次穿过第二开口60和第一开口50后到达衬底1上的距离法线l最远的第一位置，该第一位置与金属材料源7的连线与衬底1之间具有第一夹角θ 1。在蒸镀金属材料源7的过程中，衬底1是绕法线l或与法线l平行的轴线旋转的，从而形成图4F所示的金属层23。
然后，如图4F所示，利用第一掩模形成第一透明导电层包括：将第一透明导电材料源81设置于第一开口50的远离衬底1的一侧，采用第一透明导电材料源81蒸镀形成所述第一透明导电层。在对第一透明导电材料源81进行蒸镀的过程中，来自第一透明导电材料源81的透明导电材料依次穿过第二开口60和第一开口50后到达衬底1上的距离法线l最远的第二位置，该第二位置与第一透明导电材料源81的连线与衬底1之间具有第二夹角θ 2， 第二夹角θ 2小于第一夹角θ 1。金属层23包括在垂直于衬底1的方向上面向衬底1的第一表面231、与第一表面231相对且位于该第一表面231的远离衬底1的一侧的第二表面232和与第一表面231和第二表面232均相交的侧面233。在蒸镀第一透明导电材料源8的过程中，衬底1是绕法线l或与法线l平行的轴线旋转的，从而形成图4G所示的第一透明导电层21，使得第一透明导电层21覆盖金属层23的第二表面232和侧面233，以防止金属层23与后续形成在其上方的发光层接触，而使功函数比金属层的功函数高的第一透明导电层21与后续形成在其上方的发光层接触，有利于提高发光层的空穴注入率，提高发光强度。如此，形成阳极的在垂直于衬底1方向上堆叠的第一透明导电层21和金属层23。例如，在平行于衬底1的方向上，第一透明导电材料源81与法线l之间间隔开第二距离d 2，第二距离d 2大于第一距离d 1；第一透明导电材料源81到衬底1之间的距离为第二高度h 2，第二高度h 2等于第一高度h 1。从而，实现形成上述第一透明导电层21，第一透明导电层21覆盖金属层23的第二表面232和侧面233，以达到上技术效果。
需要说明的是，本公开实施例对第一透明导电材料源81与法线l之间的距离、第一透明导电材料源81与基底1的距离和金属材料源7与基底1的距离不作限定，只要能够按上述方法形成目标结构即可，本领域技术人员可以根据实际需要进行设计。例如根据第一开口50的尺寸、第二开口60的尺寸和所用蒸镀设备的参数等进行设计。
接着，如图4H所示，发光器件的制作方法还包括：在形成金属层23和第一透明导电层21之后，去除光刻胶层6并去除基底层5。例如，将光刻胶层6剥离，利用显影液溶解基底层5而将其去除。
上述方法采用同一道掩模利用蒸镀法形成第一透明导电层21和金属层23，相比较于采用湿刻法，可以达到更高的制作精度，从而，在制作用于显示面板的呈阵列分布的发光器件时，能够实现高分辨率。并且，去除光刻胶层6和基底层5的方法简单。
如图4I所示，发光器件的制作方法还包括：形成发光层4。例如，发光层4为电致发光层，例如为有机电致发光层或无机电致发光层，例如为有机二极管发光层。在垂直于衬底1的方向上，发光层4位于第一透明导电层21 的远离金属层23的一侧。第一透明导电层21的功函数大于金属层23的功函数，且金属层23的反射率大于第一透明导电层21的反射率。在该发光器件中，发光层4发出的光经阳极2反射后经由阴极射出以实现显示。一方面，透明导电层21功函数比金属层23的大，利于提高发光层的空穴注入能力，使得发光层发出的光的强度高；另一方面，金属层23具有较高的反射率，利于提高光的利用效率。从而，显示面板10的发光亮度大。
例如，显示面板10包括间隔分布的多个所述阳极。发光层4为连续的整体结构(即无间断)且覆盖多个阳极的每个的第一透明电极层21的第二表面212和多个阳极的每个的第一透明电极层21的侧面213以及相邻阳极2之间的间隔。在这种情况下，例如，第一透明导电层21的侧面213的上述坡度小于金属层23的侧面233的上述坡度，可以避免发光层4断开而导致的断路问题。
第一透明导电层21的材料和功函数、第二透明导电层22的材料和功函数、金属层23的材料请参考之前关于发光器件的实施例中的描述。
如图4J所示，在发光层4的远离阳极2的一侧形成阴极8。例如，阴极8可以是如图1B所示的连续的整体结构，在其他实施中，阴极也可以包括彼此间隔分布的多个部分。例如，阴极8的材料为透明导电材料，例如料包括铟锡氧化物(ITO)、铟锌氧化物(IZO)和掺铝的氧化锌(AZO)中的至少之一。例如，可以采用蒸镀法形成阴极8。例如，可以采用同一第一透明导电材料源作为蒸镀源形成第一透明导电层和阴极。
例如，在本公开一实施例提供的另一种制作方法还包括：在衬底上形成第二透明导电层，其中，第二透明导电层与第一透明导电层和金属层堆叠，且位于金属层的远离第一透明导电层的一侧。
例如，可以利用第一掩模形成第二透明导电层。即，通过第一掩模这一道掩模形成第二透明导电层、金属层和第一透明导电层。和采用多道掩模分别形成第二透明导电层、金属层和第一透明导电层的工艺相比，本实施例提供的这种方法操作简单，能够简化工艺，提高生产效率。
在执行完图4A-图4C所示的步骤之后，执行图5A-图5D所示的步骤。在图5A-图5D所示的实施例中，例如，基底层5的厚度大于等于第一透明 导电层21的厚度、金属层23的厚度和第二透明导电层22的厚度之和，以保证上述形成第一透明导电层21、金属层23和第二透明导电层22的步骤顺利进行。基底层5的厚度大于图4A-图4C所示的实施例中的基底层5的厚度。
如图5A所示，将第二透明导电材料源82设置于第一开口50的远离衬底1的一侧，采用第二透明导电材料源82通过蒸镀形成所述第二透明层。在对第一透明导电材料源8进行蒸镀的过程中，来自第一透明导电材料源8的透明导电材料依次穿过第二开口60和第一开口50后到达衬底1上的距离法线l最远的第三位置，该第三位置与第一透明导电材料源8的连线与衬底1之间具有所述第三夹角θ 3。在蒸镀第一透明导电材料源8的过程中，衬底1绕与法线l平行的轴线旋转，从而形成图5B所示的第二透明导电层22。第二透明导电层22包括面向衬底1的第一表面221、与该第一表面221相对且位于第一表面221的远离衬底1的一侧的第二表面222和与该第一表面221和该第二表面222均相交的侧面223。例如，在平行于衬底1的方向上，第二透明导电材料源82与法线l之间间隔开第三距离d 3，第二透明导电材料源82与衬底1之间的距离为第三高度h 3。从而实现形成上述第二透明导电层22。
接着，如图5B所示，将金属材料源7设置于第一开口50的远离衬底1的一侧，利用金属材料源7通过蒸镀形成所述金属层。例如，金属材料源7位于第一开口50的中心位置所在的垂直于衬底1的法线l上。在对金属材料源7进行蒸镀的过程中，来自金属材料源7的金属材料依次穿过第二开口60和第一开口50后到达衬底1上的距离法线l最远的第一位置，该第一位置与金属材料源7的连线与衬底1之间具有第一夹角θ 1。第三夹角θ 3小于第一夹角θ 1。在蒸镀金属材料源7的过程中，衬底1绕法线l或与法线l平行的轴线旋转，从而形成图5D所示的金属层23，金属层23覆盖第二透明导电层22的第二表面222的一部分，即金属层23不完全覆盖第二透明导电层22的第二表面222。
或者，如图5C所示，利用第一掩模形成金属层包括：将金属材料源7设置于第一开口50的远离衬底1的一侧，采用金属材料源7蒸镀形成所述金属层，其中，在平行于衬底1的方向上金属材料源7与法线l之间间隔开第 一距离d 1，法线l垂直于衬底1，在垂直于衬底1的方向上，金属材料源7与衬底1之间的距离为第一高度h 1。第三距离d 3大于第一距离d 1，第三高度h 3等于第一高度h 1，从而形成图5D所示的金属层23，金属层23覆盖第二透明导电层22的第二表面222的一部分，即金属层23不完全覆盖第二透明导电层22的第二表面222。
然后，如图5D所示，将第一透明导电材料源81设置于第一开口50的远离衬底1的一侧，采用第一透明导电材料源81蒸镀形成所述第一透明导电层。在对第一透明导电材料源81进行蒸镀的过程中，来自第一透明导电材料源81的透明导电材料依次穿过第二开口60和第一开口50后到达衬底1上的距离法线l最远的第一位置，该第一位置与第一透明导电材料源81的连线与衬底1之间具有第二夹角θ 2。第二夹角θ 2小于第一夹角θ 1，在蒸镀第一透明导电材料源81的过程中，衬底1绕法线l或与法线l平行的轴线旋转，从而形成图5E所示的第一透明导电层21，第一透明导电层21覆盖金属层23。例如，第二夹角θ 2小于或等于第三夹角θ 3，从而，第一透明导电层21还覆盖第二透明导电层22的侧面223和第二透明导电层22的第二表面222的未被金属层23覆盖的部分，这有利于减小第一透明导电层21的侧面213的坡度，以及更加严密地包裹金属层23，避免其对发光层4的空穴注入率的影响。例如，当第二夹角θ 2小于第三夹角θ 3时，形成图5E所示的结构，第一透明导电层21在衬底1上的正投影与第二透明导电层22在衬底1上的正投影基本重叠。例如，当第二夹角θ 2小于第三夹角θ 3时，形成图5F所示的结构，第一透明导电层21的面向衬底1的第一表面211除了覆盖金属层23和第二透明导电层之外，还覆盖衬底1的主表面101的一部分。例如，在平行于衬底1的方向上，第一透明导电材料源81与法线l之间间隔开第二距离d 2，第二距离d 2大于第一距离d 1；第一透明导电材料源81到衬底1之间的距离为第二高度h 2，第二高度h 2等于第一高度h 1和第三高度h 3。此时，例如，第三距离小于等于第二距离d 2，从而实现第一透明导电层21还覆盖第二透明导电层22的侧面223/第二透明导电层22的第二表面222的未被金属层23覆盖的部分，以达到上述技术效果。
去除基底层5和光刻胶层6之后得到图5E所示的结构。第一透明导电 层21、第二透明导电层22和金属层23在垂直于衬底1的方向上堆叠，且第二透明导电层2位于金属层23的远离第一透明导电层21的一侧。
形成5E所示的结构之后，该显示面板的制作方法还包括：采用与图4I-4J相同的工艺依次形成发光层4和阴极8，请参考之前的描述。例如，采用第一透明导电材料源81作为第二透明导电材料源82，即采用同一透明导电材料源作为蒸镀源形成第一透明导电层和第二透明导电层，以简化工艺。例如，可以采用第一透明导电材料源81形成第一透明导电层、第二透明导电层和阴极，以进一步简化工艺。
其他没有提及的结构特征及技术效果，均与关于发光器件的实施例中的描述相同，请参考之前的描述，在此不再重复。
在本公开另一实施例提供的制作方法中，也可以不采用同一道掩模形成第一透明导电层、金属层和第二透明导电层，而是利用两道掩模分别形成第一透明导电层、金属层，或者，利用三道掩模分别形成第一透明导电层、金属层和第二透明导电层。例如，利用第三掩模通过构图工艺形成上述金属层，第三掩模的图案与金属层的图案对应；然后利用第四掩模通过构图工艺形成上述第一透明导电层，第四掩模的图案与第一透明导电层的图案对应。或者，利用第三掩模通过构图工艺形成上述第二透明导电层，第三掩模的图案与第二透明导电层的图案对应；然后，利用第四掩模通过构图工艺形成上述金属层，第四掩模的图案与金属层的图案对应；再利用第三掩模通过构图工艺形成上述第一透明导电层，第三掩模的图案与第二透明导电层的图案对应，其中，第四掩模与第三掩模可以是同一道掩模。
例如，阵列基板包括硅基板，硅基板包括上述衬底1。上述关于显示面板的制作方法实施例以在衬底1上形成发光器件为例进行说明，例如显示面板如图1B所示，发光器件形成在第一绝缘层450上，具体形成方法与上述实施中的相同，只是以第一绝缘层450替换了发光器件制备的衬底1。形成阵列基板的其他结构的工艺，例如形成像素电路的驱动晶体管T1和其他晶体管、形成过孔452等工艺，本领域技术人员可以根据本领域常规技术进行。
在显示面板的制作方法实施例中没有提及的特征及其技术效果，均与关于图1B-1D、图2B-2C所示的显示面板中的相同，请参考之前的描述，在此 不再赘述。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围根据权利要求书所界定的范围确定。

Claims (26)

  1. 一种显示面板，包括：
    衬底；
    多个像素，位于所述衬底的一侧，其中，所述多个像素中的至少一个包括：
    阳极，包括堆叠设置的第一透明导电层和金属层，所述第一透明导电层位于金属层的远离所述衬底的一侧，所述第一透明导电层完全覆盖所述金属层，且所述金属层在所述衬底上的正投影位于所述第一透明导电层在所述衬底上的正投影内；以及
    发光层，与所述阳极堆叠设置，且位于所述第一透明导电层的远离所述金属层的一侧；
    驱动电路，位于所述衬底和所述发光层之间，其中，所述驱动电路包括驱动晶体管和存储电容，所述驱动晶体管包括源极、漏极和栅极，所述源极和所述漏极之一与所述阳极电连接，所述栅极与所述存储电容电连接，所述存储电容配置为存储数据信号。
  2. 根据权利要求1所述的显示面板，其中，所述阳极还包括：
    第二透明导电层，与所述第一透明导电层和所述金属层堆叠设置，且位于所述金属层和所述驱动电路之间，所述第一透明导电层和所述第二透明导电层完全包覆所述金属层，且所述金属层在所述衬底上的正投影位于所述第二透明导电层在所述衬底上的正投影内。
  3. 根据权利要求2所述的显示面板，其中，所述第二透明导电层包括面向所述衬底的第一表面、与该第一表面相对且位于该第一表面的远离所述衬底的一侧的第二表面以及与该第一表面和该第二表面均相交的侧面；
    所述第一透明导电层覆盖所述第二透明导电层的侧面和所述第二透明导电层的第二表面的未被所述金属层覆盖的部分。
  4. 根据权利要求3所述的显示面板，其中，所述第一透明导电层在所述衬底上的正投影与所述第二透明导电层在所述衬底上的投影完全重叠。
  5. 根据权利要求3或4所述的显示面板，其中，所述衬底具有主表面， 所述第二透明导电层、第一透明导电层和所述金属层堆叠于所述衬底的主表面上，所述第二透明导电层的侧面与所述衬底的主表面之间的夹角范围是30°～60°。
  6. 根据权利要求1-4任一所述的显示面板，其中，所述衬底具有主表面，所述第一透明导电层与所述金属层堆叠于所述衬底的主表面上，所述第一透明导电层位于所述金属层的远离所述衬底的一侧；所述金属层包括面向所述衬底的第一表面、与所述第一表面相对且位于所述第一表面的远离所述衬底的一侧的第二表面以及与所述第一表面和所述第二表面均相交的侧面；
    所述第一透明导电层覆盖所述金属层的第二表面和所述金属层的侧面。
  7. 根据权利要求6所述的显示面板，其中，
    所述第一透明导电层包括面向所述衬底的第一表面、与该第一表面相对且位于该第一表面的远离所述衬底的一侧的第二表面以及与该第一表面或该第二表面相交的侧面；
    所述第一透明导电层的侧面与所述衬底的主表面之间的夹角小于所述金属层的侧面的与所述衬底的主表面之间的夹角。
  8. 根据权利要求7所述的显示面板，其中，所述第一透明导电层的侧面与所述衬底的主表面之间的夹角范围是20°～50°，所述金属层的侧面的与所述衬底的主表面之间的夹角范围是30°～60°。
  9. 根据权利要求1-8任一所述的显示面板，其中，所述第一透明导电层的功函数大于所述金属层的功函数。
  10. 根据权利要求9所述的显示面板，其中，所述第一透明导电层的材料的功函数大于4.60eV。
  11. 根据权利要求2-10任一所述的显示面板，其中，所述第一透明导电层的材料和所述第二透明导电层的材料均包括铟锡氧化物(ITO)、铟锌氧化物(IZO)和掺铝的氧化锌(AZO)中的至少之一。
  12. 根据权利要求1-11任一所述的显示面板，其中，所述金属层的反射率大于所述第一透明导电层的反射率。
  13. 根据权利要求1-12任一所述的显示面板，其中，所述金属层的反射率大于等于90％。
  14. 根据权利要求1-13任一所述的显示面板，其中，所述金属层的材料为银。
  15. 根据权利要求2-14任一所述的显示面板，其中，所述金属层的厚度大于所述第一透明导电层的厚度，且所述金属层的厚度大于所述第二透明导电层的厚度。
  16. 根据权利要求7或8所述的显示面板，包括：间隔分布的多个所述阳极，其中，
    所述发光层为连续的整体结构且覆盖多个所述阳极的所述第一透明电极层的第二表面、多个所述阳极的每个的所述第一透明电极层的侧面；以及
    阴极，位于所述发光层的远离所述多个阳极的一侧。
  17. 根据权利要求1-16任一所述的显示面板，其中，所述显示面板为Micro LED显示面板或OLED显示面板。
  18. 根据权利要求1-17任一所述的显示面板，还包括：
    光反射层，位于所述衬底基板和所述阳极之间，与所述阳极电连接。
  19. 根据权利要求18所述的显示面板，还包括：
    第一绝缘层，位于所述阳极与所述光反射层之间且包括第一过孔，其中，所述阳极通过所述第一过孔与所述光反射层电连接。
  20. 根据权利要求19所述的显示面板，还包括：
    第二绝缘层，位于所述光反射层与所述源极、所述漏极之间且包括第二过孔，其中，所述源极和所述漏极之一通过所述第二过孔与所述光反射层电连接。
  21. 一种显示装置，包括权利要求1-20任一所述的显示面板。
  22. 一种显示面板的制作方法，包括：
    提供衬底；
    在所述衬底的一侧形成多个像素，其中，所述多个像素中的至少一个包括：
    阳极，其中，所述阳极包括堆叠设置的第一透明导电层和金属层，所述第一透明导电层位于金属层的远离所述衬底的一侧，所述第一透明导电层完全覆盖所述金属层，且所述金属层在所述衬底上的正投影位于所述第一 透明导电层在所述衬底上的正投影内；以及
    发光层，与所述阳极堆叠设置，且位于所述第一透明导电层的远离所述金属层的一侧；以及
    形成驱动电路，其中，所述驱动电路位于所述衬底和所述阳极之间，且包括驱动晶体管和存储电容，所述驱动晶体管包括源极、漏极和栅极，所述源极和所述漏极之一与所述阳极电连接，所述栅极与所述存储电容电连接，所述存储电容配置为存储数据信号。
  23. 根据权利要求22所述的制作方法，其中，形成所述阳极包括：
    在所述衬底上形成第一掩模，其中，所述第一掩模包括在垂直于所述衬底的方向上堆叠且彼此贯通的第一开口和第二开口，所述第一开口在所述衬底上的正投影位于所述第二开口在所述衬底上的正投影内，所述第一开口位于所述第二开口的远离所述衬底的一侧；以及
    利用所述第一掩模形成所述第一透明导电层和所述金属层。
  24. 根据权利要求23所述的制作方法，其中，
    所述金属层包括面向所述衬底的第一表面、与所述第一表面相对的第二表面和与所述第一表面和所述第二表面均相交的侧面；所述第一开口具有经过其中心且垂直于所述衬底的法线；
    利用所述第一掩模形成所述第一透明导电层和所述金属层包括：
    将金属材料源设置于所述第一开口的远离所述衬底的一侧，采用所述金属材料源蒸镀形成所述金属层，其中，来自所述金属材料源的金属材料穿过所述第一开口和所述第二开口后到达所述衬底上的距离所述法线最远的第一位置，所述第一位置与所述金属材料源的连线与所述衬底之间具有第一夹角；
    将第一透明导电材料源设置于所述第一开口的远离所述衬底的一侧，采用所述第一透明导电材料源蒸镀形成所述第一透明导电层，其中，来自所述第一透明导电材料源的透明导电材料穿过所述第一开口和所述第二开口后到达所述衬底上的距离所述法线最远的第二位置，所述第二位置与所述第一透明导电材料源的连线与所述衬底之间具有第二夹角；
    所述第二夹角小于所述第一夹角，且所述衬底围绕所述法线或与所述法线平行的轴线转动，以使所述第一透明导电层覆盖所述金属层的第二表面和 所述金属层的侧面。
  25. 根据权利要求24所述的制作方法，其中，
    所述金属材料源位于所述第一开口的所述法线上，或者，在平行于所述衬底的方向上所述金属材料源与所述法线之间间隔开第一距离；在垂直于所述衬底的方向上，所述金属材料源到衬底之间的距离为第一高度；
    在平行于所述衬底的方向上所述第一透明导电材料源与所述法线之间间隔开第二距离；在垂直于所述衬底的方向上，所述第一透明导电材料源到所述衬底之间的距离为第二高度；
    所述第二距离大于所述第一距离，所述第二高度等于所述第一高度。
  26. 根据权利要求25所述的制作方法，还包括：
    利用所述第一掩模在所述衬底上形成第二透明导电层，其中，所述第二透明导电层与所述第一透明导电层和所述金属层在垂直于所述衬底的方向上堆叠，且位于所述金属层和所述驱动电路之间，所述第一透明导电层和所述第二透明导电层完全包覆所述金属层，且所述金属层在所述衬底上的正投影位于所述第二透明导电层在所述衬底上的正投影内；
    利用所述第一掩模形成所述第二透明导电层包括：
    将第二透明导电材料源设置于所述第一开口的远离所述衬底的一侧，采用所述第二透明导电材料源蒸镀形成所述第二透明导电层，其中，在平行于所述衬底的方向上所述第二透明导电材料源与所述法线之间间隔开第三距离；在垂直于所述衬底的方向上，所述第二透明导电材料源与所述衬底之间的距离为第三高度；以及
    所述第三距离大于所述第一距离且小于所述第二距离，所述第三高度等于所述第一高度。
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