WO2023093314A8 - 板级架构、封装模组、电子设备及板级架构的制作方法 - Google Patents

板级架构、封装模组、电子设备及板级架构的制作方法 Download PDF

Info

Publication number
WO2023093314A8
WO2023093314A8 PCT/CN2022/124093 CN2022124093W WO2023093314A8 WO 2023093314 A8 WO2023093314 A8 WO 2023093314A8 CN 2022124093 W CN2022124093 W CN 2022124093W WO 2023093314 A8 WO2023093314 A8 WO 2023093314A8
Authority
WO
WIPO (PCT)
Prior art keywords
board
level architecture
electronic device
manufacturing
encapsulation module
Prior art date
Application number
PCT/CN2022/124093
Other languages
English (en)
French (fr)
Other versions
WO2023093314A1 (zh
Inventor
于超伟
高峰
刘丰
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Publication of WO2023093314A1 publication Critical patent/WO2023093314A1/zh
Publication of WO2023093314A8 publication Critical patent/WO2023093314A8/zh

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

本申请实施例提供一种板级架构, 封装模组, 电子设备及板级架构的制作方法, 该板级架构通过在转接板的下表面与第一电路板的上表面之间设置第一粘接层和至少一个第一导电介质, 其中, 第一粘接层用于粘接转接板和第一电路板, 至少一个第一导电介质用于电连接转接板和第一电路板, 这样, 能够提高第一电路板与转接板之间的连接可靠性, 从而能够提高板级架构的整体可靠性.
PCT/CN2022/124093 2021-11-24 2022-10-09 板级架构, 封装模组, 电子设备及板级架构的制作方法 WO2023093314A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202111403070.8 2021-11-24
CN202111403070.8A CN114364124A (zh) 2021-11-24 2021-11-24 板级架构、封装模组、电子设备及板级架构的制作方法

Publications (2)

Publication Number Publication Date
WO2023093314A1 WO2023093314A1 (zh) 2023-06-01
WO2023093314A8 true WO2023093314A8 (zh) 2023-07-27

Family

ID=81095293

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/124093 WO2023093314A1 (zh) 2021-11-24 2022-10-09 板级架构, 封装模组, 电子设备及板级架构的制作方法

Country Status (2)

Country Link
CN (1) CN114364124A (zh)
WO (1) WO2023093314A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114364124A (zh) * 2021-11-24 2022-04-15 华为技术有限公司 板级架构、封装模组、电子设备及板级架构的制作方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5719440A (en) * 1995-12-19 1998-02-17 Micron Technology, Inc. Flip chip adaptor package for bare die
CN106686886B (zh) * 2017-01-18 2019-11-29 维沃移动通信有限公司 一种印制电路板及移动终端
CN107680917B (zh) * 2017-08-11 2020-03-20 华为技术有限公司 一种板级架构及其制备方法、移动终端
CN110299329A (zh) * 2018-03-21 2019-10-01 华为技术有限公司 一种封装结构及其制作方法、电子设备
CN111968942B (zh) * 2020-08-24 2023-08-04 浙江集迈科微电子有限公司 一种转接板侧壁互联射频模组的互联工艺
CN111933590B (zh) * 2020-09-11 2021-01-01 甬矽电子(宁波)股份有限公司 封装结构和封装结构制作方法
CN112736031A (zh) * 2020-12-23 2021-04-30 海光信息技术股份有限公司 转接板及其制作方法，半导体器件及其制作方法
CN115020369A (zh) * 2021-03-03 2022-09-06 华为技术有限公司 电路板组件及其制造方法和电子设备
CN114364124A (zh) * 2021-11-24 2022-04-15 华为技术有限公司 板级架构、封装模组、电子设备及板级架构的制作方法

Also Published As

Publication number Publication date
WO2023093314A1 (zh) 2023-06-01
CN114364124A (zh) 2022-04-15

Similar Documents

Publication Publication Date Title
US7902652B2 (en) Semiconductor package and semiconductor system in package using the same
US6331221B1 (en) Process for providing electrical connection between a semiconductor die and a semiconductor die receiving member
KR100966684B1 (ko) 반도체 장치와 그것을 이용한 반도체 모듈
JP3499202B2 (ja) 半導体装置の製造方法
US7344916B2 (en) Package for a semiconductor device
KR101015266B1 (ko) 고밀도 3차원 반도체 다이 패키지
KR20050002220A (ko) 적층형 볼 그리드 어레이 패키지 및 그 제조방법
US9142472B2 (en) Integrated circuit and method of making
WO2007026392A1 (ja) 半導体装置およびその製造方法
CN103493610A (zh) 刚性柔性基板及其制造方法
JP2009141169A (ja) 半導体装置
KR20100056247A (ko) 접착층을 구비하는 반도체 패키지
JP2001119147A (ja) 電子部品内蔵多層基板及びその製造方法
WO2023093314A8 (zh) 板级架构、封装模组、电子设备及板级架构的制作方法
US6476475B1 (en) Stacked SRAM die package
CN100472780C (zh) 电子零部件及其制造方法
US20110110058A1 (en) Board on chip package substrate and manufacturing method thereof
US10269774B2 (en) Semiconductor device
US8461696B2 (en) Substrate for semiconductor package, semiconductor package including the same, and stack package using the semiconductor package
KR100592785B1 (ko) 칩 스케일 패키지를 적층한 적층 패키지
US20240170301A1 (en) Packaging structure, packaging substrate, and manufacturing method of the packaging structure
KR19980043249A (ko) 홈이 형성된 인쇄 회로 기판을 갖는 칩 스케일 패키지
KR20050027384A (ko) 재배선 패드를 갖는 칩 사이즈 패키지 및 그 적층체
KR20070019359A (ko) 밀봉 수지 주입용 개구부를 구비하는 양면 실장형 기판 및그를 이용하는 멀티 칩 패키지의 제조방법
KR20020028473A (ko) 적층 패키지

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22897399

Country of ref document: EP

Kind code of ref document: A1