WO2023070525A1 - 阵列基板及液晶显示面板 - Google Patents

阵列基板及液晶显示面板 Download PDF

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Publication number
WO2023070525A1
WO2023070525A1 PCT/CN2021/127433 CN2021127433W WO2023070525A1 WO 2023070525 A1 WO2023070525 A1 WO 2023070525A1 CN 2021127433 W CN2021127433 W CN 2021127433W WO 2023070525 A1 WO2023070525 A1 WO 2023070525A1
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WIPO (PCT)
Prior art keywords
shielding
electrodes
electrode
substrate
electric field
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2021/127433
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English (en)
French (fr)
Inventor
肖军城
李吉
刘菁
何孝金
俞云
龙芬
赵迎春
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US17/611,628 priority Critical patent/US20240036414A1/en
Publication of WO2023070525A1 publication Critical patent/WO2023070525A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136218—Shield electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

Definitions

  • the present application relates to the field of display technology, in particular to an array substrate and a liquid crystal display panel.
  • the liquid crystal display panel includes an array substrate, a color filter substrate, and a liquid crystal layer arranged between the array substrate and the color filter substrate.
  • the array substrate includes gate lines, data lines, pixel electrodes and thin film transistors, the gate lines and data lines perpendicular to each other define a pixel area, the thin film transistors and pixel electrodes are formed in the pixel area, and the gate lines are used to provide turn-on signals to the thin film transistors,
  • the data lines are used to provide data signals to the pixel electrodes, and realize grayscale display by controlling the deflection degree of the liquid crystal layer.
  • the charge on the data line will generate an electric field, which will interfere with the pixel electrode, causing adverse effects such as light leakage and crosstalk.
  • the present application provides an array substrate and a liquid crystal display panel, which can shield the electric field generated by the charge on the data line, and prevent interference to pixel electrodes, resulting in adverse effects such as light leakage and crosstalk.
  • an array substrate which includes:
  • a data wiring layer is arranged on the substrate, the data wiring layer includes a plurality of data lines, and the plurality of data lines are arranged at intervals along the first direction;
  • An electric field shielding layer is arranged on the substrate, the electric field shielding layer includes a plurality of shielding electrodes, the orthographic projection of the shielding electrodes on the substrate is the same as that of the data line on the substrate The orthographic projections are at least partially coincident.
  • the shielding electrode is arranged opposite to the data line.
  • the electric field shielding layer further includes a plurality of scanning lines, and the plurality of scanning lines are arranged at intervals along the second direction;
  • the shielding electrode includes a plurality of shielding sub-electrodes arranged at intervals along the second direction, and one shielding sub-electrode is arranged between two adjacent scanning lines.
  • the electric field shielding layer further includes a plurality of first connection electrodes, and the plurality of first connection electrodes are arranged at intervals along the second direction; Each of the first connection electrodes is arranged between two adjacent scanning lines, and the plurality of shielding sub-electrodes between two adjacent scanning lines are all connected to the first connection electrodes.
  • the data wiring layer further includes at least one second connection electrode, and the second connection electrode is arranged in a staggered manner from the data line;
  • the second connection electrode includes a plurality of connection sub-electrodes, A plurality of the connection sub-electrodes are arranged at intervals along the second direction, and the orthographic projection of the connection sub-electrodes on the electric field shielding layer is located between two adjacent shielding sub-electrodes, and two adjacent The shielding sub-electrodes are connected through the connecting sub-electrodes.
  • the voltage of the signal on the shielding electrode is lower than the minimum value of the voltage of the signal on the data line, or the voltage of the signal on the shielding electrode is greater than the signal on the data line the maximum value of the voltage.
  • the voltage of the signal of the shielding electrode is between -20 volts and 0 volts, or the voltage of the signal of the shielding electrode is between 14 volts and 30 volts.
  • the substrate, the electric field shielding layer and the data wiring layer are stacked in sequence.
  • the substrate, the data wiring layer and the electric field shielding layer are stacked in sequence.
  • the present application also provides a liquid crystal display panel, which includes:
  • the alignment substrate is disposed opposite to the array substrate;
  • liquid crystal layer is arranged between the array substrate and the alignment substrate;
  • the array substrate includes:
  • a data wiring layer is arranged on the substrate, the data wiring layer includes a plurality of data lines, and the plurality of data lines are arranged at intervals along the first direction;
  • An electric field shielding layer is arranged on the substrate, the electric field shielding layer includes a plurality of shielding electrodes, the orthographic projection of the shielding electrodes on the substrate is the same as that of the data line on the substrate The orthographic projections are at least partially coincident.
  • the shielding electrode is arranged opposite to the data line.
  • the electric field shielding layer further includes a plurality of scanning lines, and the plurality of scanning lines are arranged at intervals along the second direction;
  • the shielding electrode includes a plurality of shielding sub-electrodes arranged at intervals along the second direction, and one shielding sub-electrode is arranged between two adjacent scanning lines.
  • the electric field shielding layer further includes a plurality of first connection electrodes arranged at intervals along the second direction; two adjacent scanning lines Each of the first connection electrodes is disposed therebetween, and the plurality of shielding sub-electrodes between two adjacent scanning lines are all connected to the first connection electrodes.
  • the data wiring layer further includes at least one second connection electrode, and the second connection electrode is arranged in a staggered manner from the data line;
  • the second connection electrode includes a plurality of connection sub-electrodes A plurality of the connection sub-electrodes are arranged at intervals along the second direction, and the orthographic projection of the connection sub-electrodes on the electric field shielding layer is located between two adjacent shielding sub-electrodes, and two adjacent The shielding sub-electrodes are connected through the connecting sub-electrodes.
  • the voltage of the signal on the shielding electrode is lower than the minimum value of the voltage of the signal on the data line, or the voltage of the signal on the shielding electrode is greater than the minimum value of the voltage of the signal on the data line The maximum value of the voltage of the signal.
  • the voltage of the signal of the shielding electrode is between -20 volts and 0 volts, or the voltage of the signal of the shielding electrode is between 14 volts and 30 volts.
  • liquid crystal display panel provided in the present application, 17.
  • the substrate, the electric field shielding layer and the data wiring layer are stacked in sequence.
  • the substrate, the data wiring layer and the electric field shielding layer are stacked in sequence.
  • the array substrate and liquid crystal display panel provided by this application can shield the electric field generated by the charge on the data line by setting the shielding electrode directly opposite to the data line, so as to prevent interference to the pixel electrode, causing adverse effects such as light leakage and crosstalk; in addition , since the shielding electrode and the data line are arranged facing each other, the aperture ratio of the pixel can be increased.
  • FIG. 1 is a schematic structural diagram of an array substrate provided in an embodiment of the present application.
  • Fig. 2 is a schematic cross-sectional view of the array substrate shown in Fig. 1 along the direction A-A';
  • Fig. 3 is a schematic cross-sectional view of the array substrate shown in Fig. 1 along the B-B' direction;
  • FIG. 4 is a schematic voltage diagram of signals connected to data lines and shielding electrodes in the array substrate provided by the embodiment of the present application;
  • FIG. 5 is another voltage schematic diagram of signals connected to the data lines and the shielding electrodes in the array substrate provided by the embodiment of the present application;
  • FIG. 6 is another schematic structural view of the array substrate provided by the embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a liquid crystal display panel provided by an embodiment of the present application.
  • the embodiment of the present application provides an array substrate, which can shield the electric field generated by the charge on the data line, and avoid interference to the pixel electrode, causing adverse effects such as light leakage and crosstalk.
  • Figure 1 is a schematic structural view of the array substrate provided by the embodiment of the present application
  • Figure 2 is a schematic cross-sectional view of the array substrate shown in Figure 1 along the A-A' direction
  • Figure 3 is The schematic cross-sectional view of the array substrate along the BB' direction shown in FIG. 1
  • the array substrate 10 provided by the embodiment of the present application includes a substrate 101 , a data wiring layer 102 and an electric field shielding layer 103 .
  • the data wiring layer 102 is disposed on the substrate 101 .
  • the electric field shielding layer 103 is disposed on the substrate 101 .
  • the data wiring layer 102 and the electric field shielding layer 103 are located in different layers.
  • the data wiring layer 102 includes a plurality of data lines 1021 .
  • a plurality of data lines 1021 are arranged at intervals along the first direction.
  • the electric field shielding layer 103 includes a plurality of shielding electrodes 1031 .
  • the orthographic projection of the shielding electrode 1031 on the substrate 101 is at least partially coincident with the orthographic projection of the data line 1021 on the substrate 101 .
  • the plurality of shielding electrodes 1031 corresponds to the plurality of data lines 1021 one by one, and the orthographic projection of each shielding electrode 1031 on the substrate 101 is at least at least equal to the orthographic projection of the corresponding data line 1021 on the substrate 101 partially overlapped. It can be understood that the shielding electrode 1031 is arranged opposite to the data line 1021 .
  • the plurality of shielding electrodes 1031 and the plurality of data lines 1021 are arranged opposite to each other; that is, the orthographic projections of the shielding electrodes 1031 on the substrate 101 and the orthographic projections of the data lines 1021 on the substrate 101 at least partially overlap.
  • the array substrate 10 needs to be provided with a data wiring layer 102 to form a plurality of data lines 1021.
  • the shielding electrode 1031 and the data lines 1021 by arranging the shielding electrode 1031 and the data lines 1021 to face each other, the electric field generated by the charges on the data lines 1021 can be shielded. , to prevent interference to the pixel electrodes, resulting in adverse effects such as light leakage and crosstalk; in addition, since the shielding electrodes 1031 and the data lines 1021 are arranged facing each other, the aperture ratio of the pixels can be increased.
  • the substrate 101 , the electric field shielding layer 103 and the data wiring layer 102 are stacked in sequence; that is, the electric field shielding layer 103 is disposed below the data wiring layer 102 .
  • the substrate 101 , the data wiring layer 102 and the electric field shielding layer 103 are stacked in sequence; that is, the electric field shielding layer 103 is disposed above the data wiring layer 102 . That is, the present application can set the relative positions of the electric field shielding layer 103 and the data wiring layer 102 according to the actual process.
  • the width of the shielding electrode 1031 is greater than the width of the data line 1021; that is, the present application can ensure that the shielding electrode 1031 is not easily broken by setting the width of the shielding electrode 1031 to be greater than the width of the data line 1021.
  • the width of the shielding electrode 1031 is smaller than the width of the data line 1021 ; that is, the present application can further increase the pixel aperture ratio by setting the width of the shielding electrode 1031 smaller than the width of the data line 1021 .
  • the width of the shielding electrode 1031 is equal to the width of the data line 1021; that is, the present application can set the width of the shielding electrode 1031 to be equal to the width of the data line 1021, thereby ensuring that the shielding electrode 1031 is not easily broken. At the same time, the pixel aperture ratio is further improved.
  • the pixels on the array substrate 10 may adopt a 4-domain pixel design. In another implementation manner, the pixels on the array substrate 10 may adopt an 8-domain pixel design.
  • the signal connected to the shielding electrode 1031 on the array substrate 10 may be a direct current signal. In another implementation manner, the signal connected to the shielding electrode 1031 on the array substrate 10 may be an AC signal.
  • the material of the shielding electrode 1031 on the array substrate 10 may be metal; for example, the material of the shielding electrode 1031 on the array substrate 10 may be copper or aluminum. In another implementation manner, the material of the shielding electrode 1031 on the array substrate 10 may be indium tin oxide.
  • FIG. 1, FIG. 2, and FIG. 3 Please continue to refer to FIG. 1, FIG. 2, and FIG. 3.
  • FIG. 1, FIG. 2, and FIG. width The following will take the array substrate 10 shown in FIG. 1 , FIG. 2 and FIG. 3 as an example for description.
  • the electric field shielding layer 103 further includes a plurality of scanning lines 1032 .
  • a plurality of scan lines 1032 are arranged at intervals along the second direction.
  • a plurality of scanning lines 1032 and a plurality of shielding electrodes 1031 are formed in the same layer.
  • a scanning wiring layer needs to be arranged on the array substrate 10 to form a plurality of scanning lines 1032; the embodiment of the present application adopts Forming a plurality of scanning lines 1032 and a plurality of shielding electrodes 1031 in the same layer can reduce the overall thickness of the array substrate 10 and simplify the manufacturing process.
  • the electric field shielding layer 103 in the embodiment of the present application can form a plurality of shielding electrodes 1031 while forming a plurality of scanning lines 1032; that is, the electric field shielding layer 103 in the embodiment of the present application is a scanning wiring layer, It can form a plurality of scanning lines 1032, and can also form a plurality of shielding electrodes 1031.
  • the shielding electrode 1031 includes a plurality of shielding sub-electrodes 10311 .
  • a plurality of shielding sub-electrodes 10311 are arranged at intervals along the second direction. It should be noted that since the electric field shielding layer 103 includes a plurality of scanning lines 1032 and a plurality of shielding electrodes 1031, in order to insulate the scanning lines 1032 and the shielding electrodes 1031, the shielding electrodes 1031 need to be split into a plurality of shielding sub-electrodes 10311 .
  • the shielding electrode 1031 includes a plurality of shielding sub-electrodes 10311, the plurality of shielding sub-electrodes 10311 are arranged at intervals along the second direction, and a shielding electrode 1031 is arranged between two adjacent scanning lines 1032.
  • the electrode 1031 corresponds to a shielding sub-electrode 10311 .
  • each shielding electrode 1031 includes a plurality of shielding sub-electrodes 10311, and the plurality of shielding sub-electrodes 10311 corresponding to one shielding electrode 1031 are arranged at intervals along the second direction, and adjacent to two scanning lines A plurality of shielding sub-electrodes 10311 corresponding to the plurality of shielding electrodes 1031 are disposed between 1032 .
  • the electric field shielding layer 103 further includes a plurality of first connecting electrodes 1033 .
  • a plurality of first connection electrodes 1033 are arranged at intervals along the second direction.
  • a first connection electrode 1033 is disposed between two adjacent scan lines 1032 , and a plurality of shielding sub-electrodes 10311 between two adjacent scan lines 1032 are connected to corresponding first connection electrodes 1033 .
  • each first connection electrode 1033 is provided with a signal connection terminal, and the signal connection terminal is used for receiving electrical signals.
  • the plurality of shielding sub-electrodes 103111 between two adjacent scan lines 1032 are connected to electrical signals through corresponding first connecting electrodes 1033 .
  • the array substrate 10 provided in the embodiment of the present application can shield the electric field generated by the charge on the data line 1021 by arranging the shielding electrode 1031 to face the data line 1021, so as to prevent interference to the pixel electrode, causing adverse effects such as light leakage and crosstalk. ; Since the shielding electrode 1031 is directly opposite to the data line 1021, the aperture ratio of the pixel can be increased.
  • the voltage of the signal on the shielding electrode 1031 is smaller than the minimum voltage of the signal on the data line 1021 , or the voltage of the signal on the shielding electrode 1031 is greater than the maximum voltage of the signal on the data line 1021 .
  • the voltage of the signal connected to the data line 1021 is between A volts and B volts.
  • the voltage of the signal connected to the shielding electrode 1031 is less than A volts, or, the voltage of the signal connected to the shielding electrode 1031 is greater than B volts, and A is smaller than B. That is, the voltage of the signal connected to the shielding electrode 1031 is not within the variable range of the voltage of the signal connected to the data line 1021 .
  • a polysilicon layer is generally disposed under the data wiring layer 102 .
  • the voltage of the signal connected to the shielding electrode 1031 out of the variable range of the voltage connected to the data line 1021, it is possible to prevent the polysilicon layer between the data wiring layer 102 and the electric field shielding layer 103 from randomly
  • the positive and negative polarity switching of the signal on the data line 1021 causes an electrical change, which causes the voltage fluctuation of the signal on the shielding electrode 1031 to cause horizontal crosstalk.
  • FIG. 4 is a schematic voltage diagram of signals connected to the data line and the shielding electrode in the array substrate provided by the embodiment of the present application.
  • FIG. 5 is another schematic voltage diagram of signals connected to the data line and the shielding electrode in the array substrate provided by the embodiment of the present application. 1, 4, and 5, the voltage D1 of the signal connected to the data line 1021 is between 0 volts and 14 volts, and the voltage D2 of the signal connected to the shielding electrode 1031 can be between -20 Alternatively, the voltage D2 of the signal connected to the shielding electrode 1031 may be between 14 volts and 30 volts.
  • FIG. 6 is another schematic structural diagram of the array substrate provided by the embodiment of the present application.
  • the difference between the array substrate 20 shown in FIG. 6 and the array substrate 10 shown in FIG. 1 is that in the array substrate 20 shown in FIG. 5 , the data wiring layer 102 further includes at least one second connection electrode 1022 .
  • the second connection electrode 1022 and the data lines 1021 are arranged in a staggered manner.
  • the second connection electrode 1022 includes a plurality of connection sub-electrodes 10221, the plurality of connection sub-electrodes 10221 are arranged at intervals along the second direction, and the orthographic projections of the connection sub-electrodes 10221 on the electric field shielding layer 103 are located in two adjacent shielding sub-electrodes 10311 Between them, two adjacent shielding sub-electrodes 10311 are connected through corresponding connection sub-electrodes 10221 .
  • the second connection electrodes 1022 are formed on the data wiring layer 102, and the plurality of shielding sub-electrodes 10331 arranged at intervals along the second direction are connected through the second connection electrodes 1022, so that the array substrate 10 All the shielding electrodes 1031 on are electrically connected. Therefore, in the embodiment of the present application, only one connection terminal needs to be provided on the array substrate 10 , and electrical signals are connected through one connection terminal.
  • the width of the second connection electrode 1022 can be set to be the difference between the width of the shielding electrode 1031 and the width of the data line 1021, so that The orthographic projection of the shielding electrode 1031 on the substrate can be overlapped with the orthographic projection of the data line 1021 on the substrate and the orthographic projection of the second connection electrode 1022 on the substrate 101 , thereby increasing the pixel aperture ratio.
  • the array substrate provided by this application can shield the electric field generated by the charge on the data line by arranging the shielding electrode directly opposite to the data line, so as to prevent interference to the pixel electrode, causing adverse effects such as light leakage and crosstalk; due to the shielding electrode and the data line
  • the lines are arranged facing each other, so that the pixel aperture ratio can be increased.
  • FIG. 7 is a schematic structural diagram of a liquid crystal display panel provided by an embodiment of the present application.
  • the liquid crystal display panel 1000 provided by the embodiment of the present application includes an array substrate 10 , an alignment substrate 200 and a liquid crystal layer 100 .
  • the alignment substrate 200 is disposed opposite to the array substrate 10 .
  • the liquid crystal layer 100 is disposed between the array substrate 10 and the alignment substrate 200 .
  • the alignment substrate 200 may be a color filter substrate. That is, in the liquid crystal display panel 1000 , the color resist layer is not disposed on the array substrate 10 , but is disposed on the alignment substrate 200 . In another embodiment, the color-resist layer is not provided on the alignment substrate 200 , but the color-resist layer is provided on the array substrate 10 .
  • the array substrate 10 may specifically refer to the array substrate described in the above embodiments, which will not be repeated here.
  • the liquid crystal display panel provided by this application can shield the electric field generated by the charge on the data line by arranging the shielding electrode directly opposite to the data line, so as to prevent interference to the pixel electrode and cause adverse effects such as light leakage and crosstalk;
  • the data lines are arranged facing each other, so that the pixel aperture ratio can be improved.

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  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
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Abstract

一种阵列基板（10）以及液晶显示面板（1000），阵列基板（10）包括：基板（101）、数据布线层（102）和电场屏蔽层（103）；其中，数据布线层（102）设置在基板（101）上，数据布线层（102）包括多条数据线（1021），多条数据线（1021）沿着第一方向间隔设置；电场屏蔽层（103）设置在基板（101）上，电场屏蔽层（103）与数据布线层（102）位于不同层，电场屏蔽层（103）包括多个屏蔽电极（1031），多个屏蔽电极（1031）与多条数据线（1021）一一正对设置。

Description

阵列基板及液晶显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种阵列基板及液晶显示面板。
 背景技术
液晶显示面板包括阵列基板、彩膜基板以及设置在阵列基板和彩膜基板之间的液晶层。阵列基板包括栅线、数据线、像素电极和薄膜晶体管，相互垂直的栅线和数据线定义了像素区域，薄膜晶体管和像素电极形成在像素区域内，栅线用于向薄膜晶体管提供开启信号，数据线用于向像素电极提供数据信号，通过控制液晶层的偏转程度实现灰度显示。
然而，数据线上的电荷会产生电场，从而对像素电极产生干扰，造成漏光和串扰等不良影响。
 技术问题
本申请提供一种阵列基板及液晶显示面板，可以屏蔽数据线上的电荷产生的电场，防止对像素电极产生干扰，造成漏光和串扰等不良影响。
 技术解决方案
第一方面，本申请提供一种阵列基板，其包括：
基板；
数据布线层，所述数据布线层设置在所述基板上，所述数据布线层包括多条数据线，多条所述数据线沿着第一方向间隔设置；以及
电场屏蔽层，所述电场屏蔽层设置在所述基板上，所述电场屏蔽层包括多个屏蔽电极，所述屏蔽电极在所述基板上的正投影与所述数据线在所述基板上的正投影至少部分重合。
在本申请提供的阵列基板中，所述屏蔽电极与所述数据线正对设置。
在本申请提供的阵列基板中，所述电场屏蔽层还包括多条扫描线，多条所述扫描线沿着第二方向间隔设置；
所述屏蔽电极包括多个沿着所述第二方向间隔设置的屏蔽子电极，且相邻两条所述扫描线之间均设置有一所述屏蔽子电极。
在本申请提供的阵列基板中，所述电场屏蔽层还包括多个第一连接电极，多个所述第一连接电极沿着所述第二方向间隔设置；相邻两条所述扫描线之间均设置有一所述第一连接电极，且相邻两条所述扫描线之间的多个所述屏蔽子电极均与所述第一连接电极连接。
在本申请提供的阵列基板中，所述数据布线层还包括至少一第二连接电极，所述第二连接电极与所述数据线错开设置；所述第二连接电极包括多个连接子电极，多个所述连接子电极沿着所述第二方向间隔设置，且所述连接子电极在所述电场屏蔽层上的正投影位于相邻两个所述屏蔽子电极之间，相邻两个所述屏蔽子电极通过所述连接子电极连接。
在本申请提供的阵列基板中，所述屏蔽电极上的信号的电压小于所述数据线上的信号的电压的最小值，或者所述屏蔽电极上的信号的电压大于所述数据线上的信号的电压的最大值。
在本申请提供的阵列基板中，所述屏蔽电极的信号的电压介于-20伏至0伏之间，或者，所述屏蔽电极的信号的电压介于14伏至30伏之间。
在本申请提供的阵列基板中，所述基板、所述电场屏蔽层以及所述数据布线层依次层叠设置。
在本申请提供的阵列基板中，所述基板、所述数据布线层以及所述电场屏蔽层依次层叠设置。
第二方面，本申请还提供一种液晶显示面板，其包括：
以上所述的阵列基板；
对位基板，所述对位基板与所述阵列基板相对设置；以及
液晶层，所述液晶层设置在所述阵列基板与所述对位基板之间；
所述阵列基板包括：
基板；
数据布线层，所述数据布线层设置在所述基板上，所述数据布线层包括多条数据线，多条所述数据线沿着第一方向间隔设置；以及
电场屏蔽层，所述电场屏蔽层设置在所述基板上，所述电场屏蔽层包括多个屏蔽电极，所述屏蔽电极在所述基板上的正投影与所述数据线在所述基板上的正投影至少部分重合。
在本申请提供的液晶显示面板中，所述屏蔽电极与所述数据线正对设置。
在本申请提供的液晶显示面板中，所述电场屏蔽层还包括多条扫描线，多条所述扫描线沿着第二方向间隔设置；
所述屏蔽电极包括多个沿着所述第二方向间隔设置的屏蔽子电极，且相邻两条所述扫描线之间均设置有一所述屏蔽子电极。
在本申请提供的液晶显示面板中，所述电场屏蔽层还包括多个第一连接电极，多个所述第一连接电极沿着所述第二方向间隔设置；相邻两条所述扫描线之间均设置有一所述第一连接电极，且相邻两条所述扫描线之间的多个所述屏蔽子电极均与所述第一连接电极连接。
在本申请提供的液晶显示面板中，所述数据布线层还包括至少一第二连接电极，所述第二连接电极与所述数据线错开设置；所述第二连接电极包括多个连接子电极，多个所述连接子电极沿着所述第二方向间隔设置，且所述连接子电极在所述电场屏蔽层上的正投影位于相邻两个所述屏蔽子电极之间，相邻两个所述屏蔽子电极通过所述连接子电极连接。
在本申请提供的液晶显示面板中，所述屏蔽电极上的信号的电压小于所述数据线上的信号的电压的最小值，或者所述屏蔽电极上的信号的电压大于所述数据线上的信号的电压的最大值。
在本申请提供的液晶显示面板中，所述屏蔽电极的信号的电压介于-20伏至0伏之间，或者，所述屏蔽电极的信号的电压介于14伏至30伏之间。
在本申请提供的液晶显示面板中17、根据权利要求10所述的液晶显示面板，其中，所述基板、所述电场屏蔽层以及所述数据布线层依次层叠设置。
在本申请提供的液晶显示面板中，所述基板、所述数据布线层以及所述电场屏蔽层依次层叠设置。
 有益效果
本申请提供的阵列基板以及液晶显示面板，通过将屏蔽电极与数据线正对设置，从而可以屏蔽数据线上的电荷产生的电场，防止对像素电极产生干扰，造成漏光和串扰等不良影响；另外，由于屏蔽电极与数据线正对设置，从而可以提高像素开口率。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的阵列基板的结构示意图；
图2为图1所示的阵列基板沿着A-A’方向的截面示意图；
图3为图1所示的阵列基板沿着B-B’方向的截面示意图；
图4为本申请实施例提供的阵列基板中数据线以及屏蔽电极接入的信号的电压示意图；
图5为本申请实施例提供的阵列基板中数据线以及屏蔽电极接入的信号的另一电压示意图；
图6为本申请实施例提供的阵列基板的另一结构示意图；
图7为本申请实施例提供的液晶显示面板的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本申请，并不用于限制本申请。本申请的权利要求书以及说明书中的术语“第一”、“第二”等是用于区别不同对象，而不是用于描述特定顺序。
本申请实施例提供一种阵列基板，可以屏蔽数据线上的电荷产生的电场，避免对像素电极产生干扰，造成漏光和串扰等不良影响。下文进行详细说明，需要说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。
请参阅图1、图2、图3，图1为本申请实施例提供的阵列基板的结构示意图；图2为图1所示的阵列基板沿着A-A’方向的截面示意图；图3为图1所示的阵列基板沿着B-B’方向的截面示意图。结合图1、图2、图3所示，本申请实施例提供的阵列基板10包括基板101、数据布线层102及电场屏蔽层103。数据布线层102设置在基板101上。电场屏蔽层103设置在基板101上。数据布线层102和电场屏蔽层103位于不同层。数据布线层102包括多条数据线1021。多条数据线1021沿着第一方向间隔设置。电场屏蔽层103包括多个屏蔽电极1031。屏蔽电极1031在基板101上的正投影与数据线1021在基板101上的正投影至少部分重合。
在一种实施方式中，多个屏蔽电极1031与多条数据线1021一一对应，且每个屏蔽电极1031在基板101上的正投影与相对应的数据线1021在基板101上的正投影至少部分重合。可以理解的，屏蔽电极1031与数据线1021正对设置。
需要说明的是，多个屏蔽电极1031与多条数据线1021一一正对设置；也即，屏蔽电极1031在基板101上的正投影与数据线1021在基板101上的正投影至少部分重合。可以理解的，阵列基板10需要设置数据布线层102用于形成多条数据线1021，本申请实施例通过将屏蔽电极1031与数据线1021正对设置，可以屏蔽数据线1021上的电荷产生的电场，防止对像素电极产生干扰，造成漏光和串扰等不良影响；另外，由于屏蔽电极1031与数据线1021正对设置，从而可以提高像素开口率。
在一种实施方式中，基板101、电场屏蔽层103以及数据布线层102依次层叠设置；也即，电场屏蔽层103设置在数据布线层102下方。在另一种实施方式中，基板101、数据布线层102以及电场屏蔽层103依次层叠设置；也即，电场屏蔽层103设置在数据布线层102上方。也即，本申请可以根据实际工艺设置电场屏蔽层103与数据布线层102的相对位置。
在一种实施方式中，屏蔽电极1031的宽度大于数据线1021的宽度；也即，本申请可以通过设置屏蔽电极1031的宽度大于数据线1021的宽度，从而可以保证屏蔽电极1031不容易断线。在另一种实施方式中，屏蔽电极1031的宽度小于数据线1021的宽度；也即，本申请可以通过设置屏蔽电极1031的宽度小于数据线1021的宽度，从而可以进一步提高像素开口率。在再一种实施方式中，屏蔽电极1031的宽度等于数据线1021的宽度；也即，本申请可以通过设置屏蔽电极1031的宽度等于数据线1021的宽度，从而可以在保证屏蔽电极1031不容易断线的同时，进一步提高像素开口率。
在一种实施方式中，阵列基板10上的像素可以采用4畴像素设计。在另一种实施方式中，阵列基板10上的像素可以采用8畴像素设计。
在一种实施方式中，阵列基板10上的屏蔽电极1031接入的信号可以为直流信号。在另一种实施方式中，阵列基板10上的屏蔽电极1031接入的信号可以为交流信号。
在一种实施方式中，阵列基板10上的屏蔽电极1031的材料可以为金属；比如，阵列基板10上的屏蔽电极1031的材料可以为铜或者铝。在另一种实施方式中，阵列基板10上的屏蔽电极1031的材料可以为氧化铟锡。
请继续参阅图1、图2、图3、在图1、图2、图3中，基板101、电场屏蔽层103以及数据布线层102依次层叠设置，且屏蔽电极1031的宽度大于数据线1021的宽度。下面将以图1、图2、图3所示的阵列基板10为例进行说明。
在本申请实施例中，电场屏蔽层103还包括多条扫描线1032。多条扫描线1032沿着第二方向间隔设置。多条扫描线1032以及多个屏蔽电极1031同层形成。需要说明的是，在阵列基板10上除了需设置数据布线层102来形成多条数据线1021外，在阵列基板10上还需设置扫描布线层来形成多条扫描线1032；本申请实施例通过将多条扫描线1032以及多个屏蔽电极1031同层形成，从而可以降低阵列基板10的整体厚度，且还能简化制作工艺。
可以理解的，本申请实施例中的电场屏蔽层103在形成多条扫描线1032的同时可以形成多个屏蔽电极1031；也即，本申请实施例中的电场屏蔽层103即为扫描布线层，其既可以形成多条扫描线1032，也可以形成多个屏蔽电,1031。
具体的，屏蔽电极1031包括多个屏蔽子电极10311。多个屏蔽子电极10311沿着第二方向间隔设置。需要说明的是，由于电场屏蔽层103包括多条扫描线1032以及多个屏蔽电极1031，为了使得扫描线1032与屏蔽电极1031之间绝缘，需将屏蔽电极1031拆分为多个屏蔽子电极10311。
其中，对于一个屏蔽电极1031而言，屏蔽电极1031包括多个屏蔽子电极10311，多个屏蔽子电极10311沿着第二方向间隔设置，且相邻两条扫描线1032之间均设置有一个屏蔽电极1031对应的一个屏蔽子电极10311。对于多个屏蔽电极1031而言，每个屏蔽电极1031均包括多个屏蔽子电极10311，一个屏蔽电极1031对应的多个屏蔽子电极10311沿着第二方向间隔设置，且相邻两条扫描线1032之间均设置有多个屏蔽电极1031对应的多个屏蔽子电极10311。
在本申请实施例中，电场屏蔽层103还包括多个第一连接电极1033。多个第一连接电极1033沿着第二方向间隔设置。相邻两条扫描线1032之间均设置有一第一连接电极1033，且相邻两条扫描线1032之间的多个屏蔽子电极10311均与相应第一连接电极1033连接。
其中，每一第一连接电极1033均设置信号连接端子，信号连接端子用于接入电信号。在本申请实施例中，相邻两条扫描线1032之间的多个屏蔽子电极103111均是各自通过相应的第一连接电极1033接入电信号。
本申请实施例提供的阵列基板10，通过将屏蔽电极1031与数据线1021正对设置，从而可以屏蔽数据线1021上的电荷产生的电场，防止对像素电极产生干扰，造成漏光和串扰等不良影响；由于屏蔽电极1031与数据线1021正对设置，从而可以提高像素开口率。
在本申请实施例中，屏蔽电极1031上的信号的电压小于数据线1021上的信号的电压的最小值，或者屏蔽电极1031上的信号的电压大于数据线1021上的信号的电压的最大值。比如：接入数据线1021上的信号的电压介于A伏至B伏之间。其中，接入屏蔽电极1031上的信号的电压小于A伏，或者，接入屏蔽电极1031上的信号的电压大于B伏，A小于B。也即，接入屏蔽电极1031上的信号的电压不在接入数据线1021上的信号的电压的可变范围内。
需要说明的是，阵列基板10通过4道掩膜工艺形成时，数据布线层102下方一般设置有多晶硅层。本申请实施例通过将接入屏蔽电极1031上的信号的电压设置成不在接入数据线1021上的电压的可变范围内，可以避免数据布线层102与电场屏蔽层103之间的多晶硅层随数据线1021上的信号的正负极性切换发生电性变化，导致屏蔽电极1031上的信号的电压波动，发生水平串扰。
比如，请参阅图4，图4为本申请实施例提供的阵列基板中数据线以及屏蔽电极接入的信号的电压示意图。图5为本申请实施例提供的阵列基板中数据线以及屏蔽电极接入的信号的另一电压示意图。结合图1、图4所示、图5所示，接入数据线1021上的信号的电压D1介于0伏至14伏之间，接入屏蔽电极1031的信号的电压D2可以介于-20伏至0伏之间，或者，接入屏蔽电极1031的信号的电压D2可以介于14伏至30伏之间。
请参阅图6，图6为本申请实施例提供的阵列基板的另一结构示意图。其中，图6所示的阵列基板20与图1所示的阵列基板10的区别在于：在图5所示的阵列基板20中，数据布线层102还包括至少一第二连接电极1022。
其中，第二连接电极1022与数据线1021错开设置。第二连接电极1022包括多个连接子电极10221，多个连接子电极10221沿着第二方向间隔设置，且连接子电极10221在电场屏蔽层103上的正投影位于相邻两个屏蔽子电极10311之间，相邻两个屏蔽子电极10311通过相应连接子电极10221连接。
需要说明的是，本申请实施例通过在数据布线层102上形成第二连接电极1022，通过第二连接电极1022连通沿着第二方向间隔设置的多个屏蔽子电极10331，从而使得阵列基板10上的所有屏蔽电极1031电性连通。因此，本申请实施例仅需在阵列基板10上设置一个连接端子即可，通过一个连接端子接入电信号。
进一步的，在本申请实施例中，由于屏蔽电极1031的宽度大于数据线1021的宽度，故可以将第二连接电极1022的宽度设置成屏蔽电极1031的宽度与数据线1021的宽度之差，从而可以使得屏蔽电极1031在基板上的正投影与数据线1021在基板上的正投影以及第二连接电极1022在基板101上的正投影重合，进而提高像素开口率。
本申请提供的阵列基板，通过将屏蔽电极与数据线正对设置，从而可以屏蔽数据线上的电荷产生的电场，防止对像素电极产生干扰，造成漏光和串扰等不良影响；由于屏蔽电极与数据线正对设置，从而可以提高像素开口率。
请参阅图7，图7为本申请实施例提供的液晶显示面板的结构示意图。如图7所示，本身申请实施例提供的液晶显示面板1000包括阵列基板10、对位基板200以及液晶层100。其中，对位基板200与阵列基板10相对设置。液晶层设100置在阵列基板10与对位基板200之间。
在一种实施方式中，对位基板200可以为彩膜基板。也即，液晶显示面板1000没有将色阻层设置在阵列基板10上，而是设置在对位基板200上。在另一种实施方式中，对位基板200上并未设置色阻层，色阻层是设置在阵列基板10上。
在本申请实施例中，阵列基板10具体可参照以上实施例所描述的阵列基板，在此不做赘述。
本申请提供的液晶显示面板，通过将屏蔽电极与数据线正对设置，从而可以屏蔽数据线上的电荷产生的电场，防止对像素电极产生干扰，造成漏光和串扰等不良影响；由于屏蔽电极与数据线正对设置，从而可以提高像素开口率。
以上对本申请实施例所提供的限流电路进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (18)

  1. 一种阵列基板，其包括：
    基板；
    数据布线层，所述数据布线层设置在所述基板上，所述数据布线层包括多条数据线，多条所述数据线沿着第一方向间隔设置；以及
    电场屏蔽层，所述电场屏蔽层设置在所述基板上，所述电场屏蔽层包括多个屏蔽电极，所述屏蔽电极在所述基板上的正投影与所述数据线在所述基板上的正投影至少部分重合。
  2. 根据权利要求1所述的阵列基板，其中，所述屏蔽电极与所述数据线正对设置。
  3. 根据权利要求1所述的阵列基板，其中，所述电场屏蔽层还包括多条扫描线，多条所述扫描线沿着第二方向间隔设置；
    所述屏蔽电极包括多个沿着所述第二方向间隔设置的屏蔽子电极，且相邻两条所述扫描线之间均设置有一所述屏蔽子电极。
  4. 根据权利要求3所述的阵列基板，其中，所述电场屏蔽层还包括多个第一连接电极，多个所述第一连接电极沿着所述第二方向间隔设置；相邻两条所述扫描线之间均设置有一所述第一连接电极，且相邻两条所述扫描线之间的多个所述屏蔽子电极均与所述第一连接电极连接。
  5. 根据权利要求4所述的阵列基板，其中，所述数据布线层还包括至少一第二连接电极，所述第二连接电极与所述数据线错开设置；所述第二连接电极包括多个连接子电极，多个所述连接子电极沿着所述第二方向间隔设置，且所述连接子电极在所述电场屏蔽层上的正投影位于相邻两个所述屏蔽子电极之间，相邻两个所述屏蔽子电极通过所述连接子电极连接。
  6. 根据权利要求1所述的阵列基板，其中，所述屏蔽电极上的信号的电压小于所述数据线上的信号的电压的最小值，或者所述屏蔽电极上的信号的电压大于所述数据线上的信号的电压的最大值。
  7. 根据权利要求6所述的阵列基板，其中，所述屏蔽电极的信号的电压介于-20伏至0伏之间，或者，所述屏蔽电极的信号的电压介于14伏至30伏之间。
  8. 根据权利要求1所述的阵列基板，其中，所述基板、所述电场屏蔽层以及所述数据布线层依次层叠设置。
  9. 根据权利要求1所述的阵列基板，其中，所述基板、所述数据布线层以及所述电场屏蔽层依次层叠设置。
  10. 一种液晶显示面板，其包括：
    阵列基板；
    对位基板，所述对位基板与所述阵列基板相对设置；以及
    液晶层，所述液晶层设置在所述阵列基板与所述对位基板之间；
    所述阵列基板包括：
    基板；
    数据布线层，所述数据布线层设置在所述基板上，所述数据布线层包括多条数据线，多条所述数据线沿着第一方向间隔设置；以及
    电场屏蔽层，所述电场屏蔽层设置在所述基板上，所述电场屏蔽层包括多个屏蔽电极，所述屏蔽电极在所述基板上的正投影与所述数据线在所述基板上的正投影至少部分重合。
  11. 根据权利要求10所述的液晶显示面板，其中，所述屏蔽电极与所述数据线正对设置。
  12. 根据权利要求10所述的液晶显示面板，其中，所述电场屏蔽层还包括多条扫描线，多条所述扫描线沿着第二方向间隔设置；
    所述屏蔽电极包括多个沿着所述第二方向间隔设置的屏蔽子电极，且相邻两条所述扫描线之间均设置有一所述屏蔽子电极。
  13. 根据权利要求12所述的液晶显示面板，其中，所述电场屏蔽层还包括多个第一连接电极，多个所述第一连接电极沿着所述第二方向间隔设置；相邻两条所述扫描线之间均设置有一所述第一连接电极，且相邻两条所述扫描线之间的多个所述屏蔽子电极均与所述第一连接电极连接。
  14. 根据权利要求13所述的液晶显示面板，其中，所述数据布线层还包括至少一第二连接电极，所述第二连接电极与所述数据线错开设置；所述第二连接电极包括多个连接子电极，多个所述连接子电极沿着所述第二方向间隔设置，且所述连接子电极在所述电场屏蔽层上的正投影位于相邻两个所述屏蔽子电极之间，相邻两个所述屏蔽子电极通过所述连接子电极连接。
  15. 根据权利要求10所述的液晶显示面板，其中，所述屏蔽电极上的信号的电压小于所述数据线上的信号的电压的最小值，或者所述屏蔽电极上的信号的电压大于所述数据线上的信号的电压的最大值。
  16. 根据权利要求15所述的液晶显示面板，其中，所述屏蔽电极的信号的电压介于-20伏至0伏之间，或者，所述屏蔽电极的信号的电压介于14伏至30伏之间。
  17. 根据权利要求10所述的液晶显示面板，其中，所述基板、所述电场屏蔽层以及所述数据布线层依次层叠设置。
  18. 根据权利要求10所述的液晶显示面板，其中，所述基板、所述数据布线层以及所述电场屏蔽层依次层叠设置。
PCT/CN2021/127433 2021-10-25 2021-10-29 阵列基板及液晶显示面板 Ceased WO2023070525A1 (zh)

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