WO2023062781A1 - 半導体装置、電力変換装置および半導体装置の製造方法 - Google Patents

半導体装置、電力変換装置および半導体装置の製造方法 Download PDF

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WO2023062781A1
WO2023062781A1 PCT/JP2021/038065 JP2021038065W WO2023062781A1 WO 2023062781 A1 WO2023062781 A1 WO 2023062781A1 JP 2021038065 W JP2021038065 W JP 2021038065W WO 2023062781 A1 WO2023062781 A1 WO 2023062781A1
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Prior art keywords
surface electrode
electrode
layer
short
semiconductor device
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English (en)
French (fr)
Japanese (ja)
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敦文 井上
哲 根岸
剛史 川上
朋宏 玉城
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to CN202180103149.0A priority Critical patent/CN118160099A/zh
Priority to JP2023553847A priority patent/JP7642087B2/ja
Priority to DE112021008362.7T priority patent/DE112021008362T5/de
Priority to PCT/JP2021/038065 priority patent/WO2023062781A1/ja
Priority to US18/685,521 priority patent/US20240355874A1/en
Publication of WO2023062781A1 publication Critical patent/WO2023062781A1/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/412—Deposition of metallic or metal-silicide materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6536—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to radiation, e.g. visible light
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/68—Organic materials, e.g. photoresists
    • H10P14/683—Organic materials, e.g. photoresists carbon-based polymeric organic materials, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/10—Arrangements for heating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/63—Vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials

Definitions

  • the present disclosure relates to a semiconductor device, a method for manufacturing the semiconductor device, and a power converter using the same.
  • IGBTs insulated gate bipolar transistors
  • MOSFETs insulated gate field effect transistors
  • the short-circuit withstand time which is the time during which the semiconductor device does not break down even if it is turned on in a short-circuited state, may be reduced.
  • semiconductor devices may be used in high-temperature environments, or control current and heat generation may be large, and there is a demand for improved heat dissipation properties of semiconductor substrates.
  • Patent Document 1 discloses that a metal layer containing nickel is not formed on a surface electrode of a semiconductor element.
  • a technique is disclosed in which heat is dissipated from the surface of a semiconductor element through a metal layer, which is formed by an electrolytic plating method.
  • a gate electrode, an emitter electrode, a gate wiring provided in a wiring region between the gate electrode and the emitter electrode, and an insulating film covering the gate wiring are formed.
  • a semiconductor element has electrodes insulated from each other, a conductive layer separated from these electrodes in a region between these electrodes, and an insulating layer covering the conductive layer, an uneven structure is formed. be done.
  • the surface of the insulating layer covering the conductive layer, particularly the concave portion between the electrode and the conductive layer is subjected to a plating treatment such as a plating solution or a plating solution cleaning agent. Substances contained in the liquid remain to form a conductive film, which sometimes causes a short circuit between the electrodes insulated from each other.
  • the present disclosure has been made to solve the above-described problems, and prevents short circuits between electrodes when metal plating layers are formed on the electrodes insulated from each other on the surface of a semiconductor device.
  • An object is to provide a semiconductor device.
  • a semiconductor device of the present disclosure includes a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, and a first surface electrode formed on the first main surface. , a second surface electrode formed apart from the first surface electrode in plan view and electrically insulated from the first surface electrode, and a first main surface between the first surface electrode and the second surface electrode a conductive layer having electrical conductivity formed apart from the first surface electrode and the second surface electrode in plan view; a conductive layer; and a first main electrode between the first surface electrode and the second surface electrode; an insulating layer having insulating properties and formed to cover the surface and the ends of the first surface electrode and the second surface electrode on the side closer to the conductive layer; and insulation between the first surface electrode and the conductive layer.
  • It is formed over the layer and over the insulating layer between the second surface electrode and the conductive layer, has a thickness equal to or greater than the height from the lower end to the upper end of the conductive layer, and is made of a material different from that of the insulating layer. It comprises an insulating short-circuit prevention layer, metal plating layers respectively formed on the first surface electrode and the second surface electrode, and a back surface electrode formed on the second main surface.
  • a planar electrode layer is formed on the first main surface of the semiconductor substrate and patterned so that the first surface electrode and the first surface electrode are separated from each other in plan view.
  • the first surface electrode, the second surface electrode and the short-circuit prevention layer are immersed in a plating solution using a plating method.
  • a semiconductor device in which a short circuit prevention layer is formed between electrodes insulated from each other on the surface of a semiconductor element to prevent short circuits between these electrodes.
  • FIG. 1 is a schematic plan view showing a schematic configuration of a semiconductor device according to a first embodiment
  • FIG. 1 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device according to Embodiment 1
  • FIG. 1 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device according to Embodiment 1
  • FIG. 1 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device according to Embodiment 1
  • FIG. 10 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device according to a second embodiment; 9 is a graph showing the short-circuit withstand capability of the semiconductor device according to the second embodiment; 1 is a schematic plan view showing a schematic configuration of a semiconductor device according to Embodiments 1 and 2; FIG. FIG. 10 is a schematic diagram showing a schematic configuration of a power conversion system to which a power conversion device according to Embodiment 3 is applied;
  • an IGBT will be described as an example, but it has electrodes insulated from each other on the surface of the semiconductor element, a conductive layer provided separately in a region between these electrodes in plan view, and an insulating layer covering the conductive layer. It can be changed appropriately as long as it is one, and it may be a MOSFET or an IGBT and a MOSFET.
  • FIG. 1 and 2 are a schematic plan view and a schematic cross-sectional view, respectively, showing a semiconductor device according to this embodiment.
  • the semiconductor device is provided with an active region 10, which is a region through which a main current of the semiconductor device flows, and a termination region 11, which is a region outside the active region.
  • a gate wiring 5a covered with an insulating layer 6 is formed in the gate wiring region 4 between the emitter electrode 2a and the gate electrode 3a.
  • a short-circuit prevention layer 7 is provided between them.
  • a metal plating layer 8 is formed on the emitter electrode 2a and the gate electrode 3a, and a collector electrode 9a is formed on the rear surface of the semiconductor substrate 1.
  • the insulating layer 6 and the metal plating layer 8 are omitted for the sake of simple explanation.
  • the semiconductor substrate 1 has a first main surface 1a on the front side and a second main surface 1b on the back side.
  • Semiconductor layers such as a drift layer, an emitter layer, a collector layer, a field stop layer, and an electrolytic relaxation layer are formed on the first main surface 1a side or the second main surface 1b side of the semiconductor substrate 1 .
  • a substrate made of silicon, for example, may be used as the semiconductor substrate 1 .
  • the emitter electrode 2a and the gate electrode 3a which are the first surface electrode 2 and the second surface electrode 3, are formed on the first main surface 1a of the active region 10 of the semiconductor substrate 1 so as to be separated from each other and electrically insulated. be done.
  • Aluminum for example, may be used for the emitter electrode 2a and the gate electrode 3a, and an alloy material such as an alloy of aluminum and silicon may be used.
  • the gate wiring region 4 is a region in which the gate wiring 5a and the insulating layer 6 are provided on the first main surface 1a of the semiconductor substrate 1, and a convex portion 4a and a concave portion 4b are formed.
  • the region between the emitter electrode 2a and the gate electrode 3a is the gate wiring region 4.
  • the width of the gate wiring region 4 that is, the horizontal distance between the outer peripheral ends of the emitter electrode 2a and the gate electrode 3a is, for example, about 100 ⁇ m. In some cases, the width of the gate wiring region 4 is set to 100 ⁇ m or less in order to expand the region through which the main current of the semiconductor device flows.
  • the gate wiring 5a is also provided in the termination region 11. As shown in FIG.
  • the gate wiring 5a is formed on the first main surface 1a between the emitter electrode 2a and the gate electrode 3a so as to be separated from the emitter electrode 2a and the gate electrode 3a in plan view. is the conductive layer 5 .
  • a conductive material such as aluminum may be used for the gate wiring 5a, or an alloy material such as an alloy of aluminum and silicon may be used.
  • the insulating layer 6 is close to the gate wiring 5a, the first main surface 1a between the emitter electrode 2a and the gate electrode 3a, and the gate wiring 5a of each of the emitter electrode 2a and the gate electrode 3a. side edges.
  • the end portion includes the end faces of the emitter electrode 2a and the gate electrode 3a, and is defined as a region from the outer periphery to 100 ⁇ m inside the outer periphery on the upper surface of the emitter electrode 2a and the gate electrode 3a. It can be increased or decreased depending on the element design.
  • the gate wiring 5a on which the insulating layer 6 is laminated has the convex portion 4a, and the concave portion 4b is formed between the emitter electrode 2a and the gate wiring 5a and between the gate electrode 3a and the gate wiring 5a. is formed.
  • the insulating layer 6 may be made of an insulating material, such as silicon nitride.
  • the short-circuit prevention layer 7 covers the insulating layer 6 between the emitter electrode 2a and the gate wiring 5a and the insulating layer 6 between the gate electrode 3a and the gate wiring 5a. It is formed. Further, the short-circuit prevention layer 7 fills the concave portion 4b so as to planarize the convex portion 4a and the concave portion 4b.
  • the thickness of the short-circuit preventing layer 7 indicates the height from the lower end to the upper end of the short-circuit preventing layer 7, and is equal to or greater than the thickness of the gate wiring 5a, in other words, equal to or greater than the height from the lower end to the upper end of the gate wiring 5a. By doing so, the height of the upper end of the short-circuit prevention layer 7 is equal to or higher than the height of the upper end of the projection 4a.
  • the short-circuit prevention layer 7 has insulating properties and is made of a material different from that of the insulating layer 6 .
  • materials such as polyimide, polybenzoxazole, polytetrafluoroethylene, and siloxane can be used for the short circuit prevention layer 7.
  • FIG. The short circuit prevention layer 7 has chemical resistance to the plating solution, moisture resistance, heat resistance, adhesiveness, and the convex portions 4a and the concave portions as described later, compared with insulating materials such as silicon nitride and silicon oxide used for the insulating layer 6.
  • polyimide and polybenzoxazole are suitable in terms of chemical resistance, moisture resistance, heat resistance, fluidity and the like.
  • the liquid containing a conductive substance is difficult to detach and evaporate, and the bottom of the concave portion 4b is likely to generate surface tension. In particular, it adheres and remains in the vicinity of the bottom surface and side wall surfaces of the recess 4b, that is, at the corners. In some cases, the residual material spreads over the bottom surface and side wall surfaces of recess 4b to form a conductive film between emitter electrode 2a and gate electrode 3a.
  • the short-circuit prevention layer 7 is formed to fill the concave portion 4b and the metal plating layer 8 is formed, it is possible to prevent the conductive substance from adhering and remaining on the bottom of the concave portion 4b, and the emitter electrode 2a and the gate electrode 3a. It is possible to suppress the formation of a conductive film between. Further, it is possible to prevent the short circuit between the emitter electrode 2a and the gate electrode 3a.
  • the metal plating layer 8 is formed on the emitter electrode 2a and the gate electrode 3a, respectively, and promotes heat dissipation from the emitter electrode 2a and the gate electrode 3a.
  • the heat capacity on the surface side of the semiconductor device can be increased compared to the case where the metal plating layer 8 is not formed.
  • the heat generated in the semiconductor device is radiated from the metal plating layer 8 to an external space or an external material, or is conducted to the metal plating layer 8, thereby improving the short-circuit resistance of the semiconductor device.
  • nickel may be used for the metal plating layer 8 and an alloy such as nickel and phosphorus, nickel and boron, or a laminate of nickel and gold or copper and gold may be used.
  • an alloy of nickel and phosphorus can reduce the manufacturing cost and improve the heat dissipation and short-circuit resistance of the semiconductor device.
  • the collector electrode 9a is the back electrode 9, and is formed on the second main surface 1b of the semiconductor substrate 1, as shown in FIG.
  • the collector electrode 9a for example, aluminum, titanium, or the like may be used, or a laminate of aluminum, nickel, gold, or the like may be used.
  • a planar electrode layer made of aluminum is formed on the first main surface 1a of the semiconductor substrate 1 on which the semiconductor layer is formed by using, for example, a sputtering method, and an etching method is used. and patterning.
  • Emitter electrode 2a, gate electrode 3a and gate wiring 5a are collectively formed so as to be separated from each other.
  • the emitter electrode 2a, the gate electrode 3a, and the gate wiring 5a are collectively formed, the emitter electrode 2a, the gate electrode 3a, and the gate wiring 5a have the same thickness, and the depth of the recess 4b is constant regardless of the position.
  • the short-circuit prevention layer 7 can be easily embedded in 4b.
  • the manufacturing process can be facilitated and the manufacturing cost can be reduced.
  • the same thickness or constant depth does not only mean that the thickness is completely the same or the depth is constant, but it also means that the thickness or depth is within about 10% of the maximum value. include.
  • a PVD Physical Vapor
  • a sputtering method or a vapor deposition method is applied on the first main surface 1a of the semiconductor substrate 1 between the emitter electrode 2a and the gate electrode 3a and on the gate wiring 5a.
  • a silicon nitride layer is formed as the insulating layer 6 by using a deposition method or a CVD (Chemical Vapor Deposition) method.
  • photolithography and etching are used to expose the upper surfaces of the emitter electrode 2a and the gate electrode 3a except for the end portions.
  • a convex portion 4a and a concave portion 4b are formed in the gate wiring region 4 between the emitter electrode 2a and the gate electrode 3a.
  • liquid photosensitive polyimide is applied, for example, using a dispenser or a spin coater so as to cover the insulating layer 6 in the recess 4b and have a thickness equal to or greater than the thickness of the gate wiring 5a.
  • the photosensitive polyimide is irradiated with light to cure the photosensitive polyimide, and the short-circuit prevention layer 7 is formed.
  • the short-circuit prevention layer 7 may be formed by patterning the photosensitive polyimide.
  • the short-circuit prevention layer 7 may also be formed on the insulating layer 6 of the convex portion 4a.
  • the short-circuit prevention layer 7 may be formed only on the insulating layer 6 in the recess 4b using photolithography.
  • a laminate of nickel and gold, that is, a metal plating layer 8 is formed on the emitter electrode 2a and the gate electrode 3a using, for example, electroless plating.
  • the emitter electrode 2a, the gate electrode 3a, and the short-circuit prevention layer 7, which are immersed in chemicals such as a plating solution, that is, a degreasing solution, an etching solution, a conditioning solution, a substitution solution, a plating solution, and a cleaning solution are collectively referred to as an immersion portion. Also, an example of plating treatment will be described.
  • the immersion part is immersed in a degreasing liquid, a part of the natural oxide film formed on the surface of the immersion part is dissolved, and the organic matter adhering to the surface of the immersion part is removed.
  • the surface of the immersion portion is washed with pure water, and the immersion portion is immersed in an etchant to dissolve and remove the surface oxide film. Since residue generated by etching adheres to the surface of the immersed portion, the immersed portion is washed with pure water or the like and immersed in a conditioning liquid to remove the residue and form an oxide film with less contamination on the immersed portion.
  • the short-circuit prevention layer 7 when the short-circuit prevention layer 7 is not formed, residues may remain in the concave portions 4b or the convex portions 4a, and a conductive film may be formed. If there is, the residue adhering to the surface of the short-circuit prevention layer 7 can be easily removed by washing.
  • the surface of the immersed portion is washed with pure water or the like and immersed in a zinc substitution solution, thereby dissolving the oxide film formed on the immersed portion and removing aluminum from the surfaces of the emitter electrode 2a and the gate electrode 3a. is dissolved and ionized, and zinc is deposited. Further, the surface of the immersion portion is washed with pure water or the like and immersed in a nickel plating solution, whereby zinc is substituted with nickel to form a nickel plating layer.
  • zinc may remain in the concave portions 4b or the convex portions 4a and be replaced with nickel, thereby forming a conductive film.
  • the residue adhering to the surface of the short-circuit prevention layer 7 can be easily removed by washing.
  • the surfaces of the short-circuit prevention layer 7 and the nickel plating layer are washed with pure water or the like, and gold plating is applied to form a gold plating layer that prevents oxidation of nickel on the surface of the nickel plating layer. .
  • the above is the description of the metal plating layer forming process.
  • an aluminum layer that is, a collector electrode 9a is formed planarly on the second main surface 1b of the semiconductor substrate 1 by using, for example, a sputtering method. As described above, the semiconductor device according to this embodiment is manufactured.
  • the short-circuit prevention layer 7 covers the insulating layer 6 between the emitter electrode 2a and the gate wiring 5a and the insulating layer 6 between the gate electrode 3a and the gate wiring 5a, and the gate wiring
  • the concave portion 4b is filled so as to flatten the convex portion 4a and the concave portion 4b of the region 4. Then, as shown in FIG.
  • the metal plating layer 8 is formed, substances contained in the plating solution, such as the plating solution and the plating solution cleaning agent, remain on the surface of the insulating layer 6 covering the gate wiring 5a, particularly in the recesses 4b; It is possible to suppress the formation of a conductive film between the emitter electrode 2a and the gate electrode 3a.
  • a semiconductor device in which a metal plating layer 8 is formed on each of the emitter electrode 2a and the gate electrode 3a which are insulated from each other on the surface of the semiconductor element to prevent the emitter electrode 2a and the gate electrode 3a from being short-circuited. can.
  • FIG. 3 is a schematic cross-sectional view showing another form of the present embodiment.
  • the short-circuit prevention layer 7 may be formed on the insulating layer 6 covering the gate wiring 5a, in other words, on the convex portion 4a.
  • the thickness of the short-circuit prevention layer 7 indicates the height from the lower end of the short-circuit prevention layer 7 formed in the concave portion 4b to the upper end of the short-circuit prevention layer 7 formed in the convex portion 4a.
  • the surface of the short-circuit prevention layer 7 is hydrophobic, when the metal plating layer 8 is formed, the surface of the short-circuit prevention layer 7 contains a plating solution such as a plating solution and a plating solution cleaning agent. Remaining substances can be further suppressed. Further, it is possible to prevent short-circuiting between the emitter electrode 2a and the gate electrode 3a due to the formation of a conductive film between the emitter electrode 2a and the gate electrode 3a.
  • thermosetting polyimide as a liquid material is used, for example, using a dispenser or a spin coater. is applied and the thermosetting polyimide is heated and cured to form the short-circuit prevention layer 7 .
  • the short-circuit prevention layer 7 is formed inside the gate wiring region 4, but in the present embodiment, the short-circuit prevention layer 7 extends outside the gate wiring region 4.
  • An example having a region formed and in contact with the emitter electrode 2a and the gate electrode 3a will be described. Other configurations are the same as those of the first embodiment.
  • the short-circuit prevention layer 7 is formed over the insulating layer 6 covering the ends of the emitter electrode 2a and the gate electrode 3a, and has a region in contact with the emitter electrode 2a and the gate electrode 3a. .
  • the short-circuit prevention layer 7 is also formed on the emitter electrode 2a and the gate electrode 3a outside the gate wiring region 4, the short-circuit prevention is better than when the short-circuit prevention layer 7 is formed only inside the gate wiring region 4.
  • the range for forming the layer 7 can be expanded, and the short-circuit prevention layer 7 can be easily formed.
  • FIG. 5 shows an example in which both ends of the short-circuit prevention layer 7 have regions in contact with the emitter electrode 2a and the gate electrode 3a. may be formed. That is, both ends of the short-circuit prevention layer 7 may be formed so as not to have regions contacting the emitter electrode 2a and the gate electrode 3a.
  • the area of the region where the short-circuit prevention layer 7 contacts the emitter electrode 2a and the gate electrode 3a is preferably small. If the contact area is small, the contact area between the emitter electrode 2a and the gate electrode 3a of the metal plating layer 8 can be increased, and heat dissipation from the emitter electrode 2a and the gate electrode 3a through the metal plating layer 8 is promoted.
  • test samples were used in which a DBA (Direct Bonded Aluminum) substrate and a semiconductor element were connected by soldering and wire bonding.
  • DBA Direct Bonded Aluminum
  • a short-circuit prevention layer 7 is also formed on the ends of the emitter electrode 2a and the gate electrode 3a outside the gate wiring region 4, and the thickness of the emitter electrode 2a and the gate electrode 3a is increased. Those having different metal plating layers 8 formed thereon were used.
  • the semiconductor substrate 1 of the semiconductor element is a silicon substrate, and the thickness of the silicon substrate is 90 ⁇ m. The height of the portion 4a was 5 ⁇ m.
  • the electrical resistance between the emitter electrode 2a and the gate electrode 3a was measured.
  • the electrical resistance of all the test samples exceeded the upper measurement limit of 30 M ⁇ of the measuring device used for measurement, and it was confirmed that the emitter electrode 2a and the gate electrode 3a were not short-circuited.
  • test conditions were as follows: voltage applied to gate electrode 3a was 20 V, voltage applied to the capacitor used as a short-circuit current source was 800 V, and test sample temperature was 150°C.
  • the time for short-circuiting between the emitter electrode 2a and the gate electrode 3a was increased by 0.2 ⁇ s from 4.0 ⁇ s, and the maximum value of the short-circuiting time during which no breakdown occurred was taken as the short-circuit tolerance.
  • FIG. 6 is a graph showing relative values of short-circuit withstand capability of the semiconductor device according to the present embodiment.
  • the dotted line in FIG. 6 is an auxiliary line showing the behavior of the relative value of the short-circuit resistance with respect to each thickness.
  • the thickness of the metal plating layer 8 is 0 ⁇ m, that is, the short-circuit resistance when the metal plating layer 8 is not formed is 1
  • the formation of the metal plating layer 8 has a positive correlation with the heat dissipation. It was confirmed that the relative value of the short-circuit withstand capability was a value exceeding 1.
  • a metal plating layer 8 is formed on each of the electrodes 3a to prevent a short circuit between the emitter electrode 2a and the gate electrode 3a. Further, by increasing the thickness of the metal plating layer 8, it is possible to prevent a short circuit between the emitter electrode 2a and the gate electrode 3a and improve the short circuit resistance of the semiconductor device.
  • the first surface electrode 2, the second surface electrode 3, the conductive layer 5, and the back surface electrode 9 are the emitter electrode 2a, the gate electrode 3a, the gate wiring 5a, and the collector electrode 9a, respectively.
  • An example in which an insulated gate bipolar transistor is formed in the semiconductor device has been shown, but an insulated gate field effect transistor may be formed in the semiconductor device with a source electrode, a gate electrode 3a, a gate wiring 5a, and a drain electrode, respectively. .
  • the horizontal distance between the insulating layer 6 covering the emitter electrode 2a and the insulating layer 6 covering the gate wiring 5a that is, the width of the recess 4b is 1 ⁇ m to 30 ⁇ m.
  • the height from the lower end of the gate wiring 5a to the upper end of the insulating layer 6 covering the gate wiring 5a that is, when the height of the convex portion 4a is 0.5 ⁇ m or more and 10 ⁇ m or less, the convex portion A conductive film is likely to be formed on 4a or recess 4b.
  • the concave portion 4b is narrow and deep, the liquid containing the conductive substance easily adheres and remains, and spreads from the concave portion 4b to the convex portion 4a to form a conductive film.
  • the thickness of the emitter electrode 2a and the gate electrode 3a is preferably 1 ⁇ m or more and less than 10 ⁇ m.
  • the thickness of the emitter electrode 2a and the gate electrode 3a is 1 ⁇ m or more and less than 10 ⁇ m, the time required for electrode formation can be reduced, and the heat dissipation and short-circuit resistance of the semiconductor device can be improved.
  • the thickness of the metal plating layer 8 may be 1 ⁇ m or more and 50 ⁇ m or less, preferably 5 ⁇ m or more and 40 ⁇ m or less.
  • the thickness of the metal plating layer 8 is 5 ⁇ m or more and 40 ⁇ m or less, the time required for forming the plating layer can be reduced, and the heat dissipation and short-circuit resistance of the semiconductor device can be improved. If the thickness of the metal plating layer 8 exceeds 50 ⁇ m, the stress generated in the semiconductor element increases, which may cause the semiconductor element to warp.
  • a substrate made of a compound semiconductor such as silicon carbide, gallium nitride, gallium arsenide, or gallium oxide may be used.
  • the semiconductor device When using a substrate made of a compound semiconductor, the semiconductor device may be operated at a higher temperature than when using a substrate made of silicon. Therefore, the short-circuit prevention layer 7 and the metal plating layer 8 are formed, and the effect of heat dissipation from the metal plating layer 8 can be increased without short-circuiting the semiconductor device.
  • the thickness of the semiconductor substrate 1 may be 1 ⁇ m or more and 150 ⁇ m or less, preferably 50 ⁇ m or more and 100 ⁇ m or less, from the viewpoint of conduction loss, turn-off loss, heat dissipation, etc. of the semiconductor device.
  • the thickness of the semiconductor substrate 1 is 50 ⁇ m or more and 100 ⁇ m or less, the handling of the semiconductor substrate 1 in the manufacturing process is facilitated, and problems such as cracks and breaks in the semiconductor substrate 1 can be suppressed, and conduction loss and turn-off loss can be suppressed. can.
  • the thickness of the semiconductor substrate 1 is reduced to 100 ⁇ m or less, the heat capacity of the semiconductor substrate 1 becomes small, and the short-circuit resistance of the semiconductor device may decrease. In this case, it is more preferable to form the short-circuit preventing layer 7 to prevent short-circuiting and to form the metal plating layer 8 to improve the heat dissipation of the semiconductor device.
  • the thickness of the short-circuit prevention layer 7 is the same as the thickness of the gate wiring 5a or the difference thereof is 5 ⁇ m or less, the pressure applied to the semiconductor element can be dispersed when the semiconductor element is pressed from above in the mounting process, for example. be able to. In addition, it is possible to prevent cracking of the semiconductor element due to excessive pressure, failure of crimping the semiconductor element due to insufficient pressure, and the like.
  • a metal plating layer may be formed on the surface of the collector electrode 9a opposite to the surface in contact with the semiconductor substrate 1 .
  • a second metal plating layer may be formed on the collector electrode 9a at the same time as the metal plating layer 8 is formed on the emitter electrode 2a and the gate electrode 3a of the surface electrodes. Forming the second metal plating layer on the collector electrode 9a can promote heat dissipation from the back side of the semiconductor device.
  • the gate electrode 3a and the gate wiring 5a are formed in a conductive wiring layer formed below the gate electrode 3a and the gate wiring 5a in the active region 10 or the termination region 11. They are connected through a polysilicon layer.
  • the gate wiring 5a is arranged between the emitter electrodes 2a and the gate electrodes 3a, as shown in the schematic plan view of FIG. may be formed on the gate wiring region 4 between the .
  • Embodiment 3 This embodiment applies the semiconductor device according to the first or second embodiment described above to a power conversion device 200 .
  • Application of the semiconductor device according to Embodiment 1 or 2 is not limited to a specific power converter, but the case where the semiconductor device according to Embodiment 1 or 2 is applied to a three-phase inverter will be described below to explain.
  • FIG. 8 is a schematic diagram showing a schematic configuration of a power conversion system to which the power conversion device 200 according to the present embodiment is applied.
  • the power conversion system has a power supply 100 , a power converter 200 and a load 300 .
  • the power supply 100 is a DC power supply and supplies DC power to the power converter 200 .
  • the power supply 100 may be configured with various devices, for example, it may be configured with a DC system, a solar battery, a storage battery, or may be configured with a rectifier circuit or an AC/DC converter connected to an AC system. Also, the power supply 100 may be configured with a DC/DC converter that converts the DC power output from the DC system into a predetermined power.
  • the power converter 200 is a three-phase inverter connected between the power supply 100 and the load 300 , converts the DC power supplied from the power supply 100 into AC power, and supplies the AC power to the load 300 .
  • the power conversion device 200 includes a main conversion circuit 201 that converts input DC power into AC power and outputs it, and a driving circuit that outputs a drive signal for driving each switching element of the main conversion circuit 201. It has a circuit 202 and a control circuit 203 that outputs a control signal for controlling the driving circuit 202 to the driving circuit 202 .
  • the load 300 is a three-phase electric motor driven by AC power supplied from the power converter 200 .
  • the load 300 is not limited to a specific application, and is an electric motor mounted on various electric devices, such as a hybrid vehicle, an electric vehicle, a railroad vehicle, an elevator, or an electric motor for an air conditioner.
  • the main converter circuit 201 has a switching element and a freewheeling diode (not shown). By switching the switching element, the DC power supplied from the power supply 100 is converted into AC power and supplied to the load 300. .
  • the main conversion circuit 201 is a two-level three-phase full bridge circuit, and includes six switching elements and each switching element. , and six freewheeling diodes anti-parallel to .
  • the semiconductor device according to Embodiment 1 or 2 is applied to each switching element of main conversion circuit 201 .
  • the six switching elements are connected in series every two switching elements to form upper and lower arms, and the upper and lower arms form U-phase, V-phase, and W-phase of the full bridge circuit.
  • Output terminals of the upper and lower arms, that is, three output terminals of the main conversion circuit 201 are connected to the load 300 .
  • the drive circuit 202 generates a drive signal for driving the switching element of the main converter circuit 201 and supplies it to the control electrode of the switching element of the main converter circuit 201 .
  • a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrode of each switching element.
  • the driving signal is a voltage signal greater than the threshold voltage of the switching element, in other words an ON signal, and when maintaining the switching element in the OFF state, the driving signal is greater than the threshold voltage of the switching element.
  • a small voltage signal in other words an off signal.
  • the control circuit 203 controls the switching elements of the main conversion circuit 201 so that the desired power is supplied to the load 300 .
  • the ON time which is the time during which each switching element of the main conversion circuit 201 should be in the ON state
  • the main conversion circuit 201 can be controlled by pulse width modulation control that modulates the ON time of the switching element according to the voltage to be output.
  • a control signal is output to the drive circuit 202 as a control command so that an ON signal is output to the switching element that should be in the ON state and an OFF signal is output to the switching element that should be in the OFF state at each time point.
  • the drive circuit 202 outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element according to this control signal.
  • the semiconductor device according to the first or second embodiment is applied as the switching element of the main conversion circuit 201, the short circuit of the switching element is prevented, and the power with increased short circuit resistance A conversion device 200 can be implemented.
  • the present invention is not limited to this, and can be applied to various power converters.
  • the power converter may be multi-level, such as tri-level.
  • the first or second embodiment may be applied to a single-phase inverter.
  • the first or second embodiment can be applied to a DC/DC converter or an AC/DC converter.
  • the power conversion device to which Embodiment 1 or 2 is applied is not limited to one for the case where the load is an electric motor. It can also be used as a power supply device for a contactor power supply system, and can also be used as a power conditioner for a photovoltaic power generation system, an electric storage system, and the like.
  • 1 semiconductor substrate 1a first main surface, 1b second main surface, 2 first surface electrode, 2a emitter electrode, 3 second surface electrode, 3a gate electrode, 4 gate wiring region, 4a convex portion, 4b concave portion, 5 conductivity layer, 5a gate wiring, 6 insulating layer, 7 short circuit prevention layer, 8 metal plating layer, 9 back electrode, 9a collector electrode, 10 active region, 11 termination region, 100 power source, 200 power conversion device, 201 main conversion circuit, 202 drive circuit, 203 control circuit, 300 load.

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  • Engineering & Computer Science (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
PCT/JP2021/038065 2021-10-14 2021-10-14 半導体装置、電力変換装置および半導体装置の製造方法 Ceased WO2023062781A1 (ja)

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JP2023553847A JP7642087B2 (ja) 2021-10-14 2021-10-14 半導体装置、電力変換装置および半導体装置の製造方法
DE112021008362.7T DE112021008362T5 (de) 2021-10-14 2021-10-14 Halbleitervorrichtung, Stromrichter und Herstellungsverfahren für eine Halbleitervorrichtung
PCT/JP2021/038065 WO2023062781A1 (ja) 2021-10-14 2021-10-14 半導体装置、電力変換装置および半導体装置の製造方法
US18/685,521 US20240355874A1 (en) 2021-10-14 2021-10-14 Semiconductor apparatus, power converter and manufacturing method for semiconductor apparatus

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Citations (6)

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JP2007142138A (ja) * 2005-11-18 2007-06-07 Mitsubishi Electric Corp 半導体装置
JP2010161240A (ja) * 2009-01-08 2010-07-22 Toyota Motor Corp 半導体装置
JP2015231033A (ja) * 2014-06-06 2015-12-21 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
JP2020074382A (ja) * 2018-01-09 2020-05-14 ローム株式会社 半導体装置
JP2020150200A (ja) * 2019-03-15 2020-09-17 株式会社東芝 半導体装置
WO2021070252A1 (ja) * 2019-10-08 2021-04-15 三菱電機株式会社 半導体装置

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Publication number Priority date Publication date Assignee Title
JP5494559B2 (ja) 2011-04-21 2014-05-14 富士電機株式会社 半導体装置およびその製造方法
WO2020202600A1 (ja) 2019-03-29 2020-10-08 株式会社 東芝 半導体装置、半導体装置の製造方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007142138A (ja) * 2005-11-18 2007-06-07 Mitsubishi Electric Corp 半導体装置
JP2010161240A (ja) * 2009-01-08 2010-07-22 Toyota Motor Corp 半導体装置
JP2015231033A (ja) * 2014-06-06 2015-12-21 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
JP2020074382A (ja) * 2018-01-09 2020-05-14 ローム株式会社 半導体装置
JP2020150200A (ja) * 2019-03-15 2020-09-17 株式会社東芝 半導体装置
WO2021070252A1 (ja) * 2019-10-08 2021-04-15 三菱電機株式会社 半導体装置

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