WO2023044870A1 - 环栅晶体管、其制备方法、cmos晶体管及电子设备 - Google Patents

环栅晶体管、其制备方法、cmos晶体管及电子设备 Download PDF

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WO2023044870A1
WO2023044870A1 PCT/CN2021/120782 CN2021120782W WO2023044870A1 WO 2023044870 A1 WO2023044870 A1 WO 2023044870A1 CN 2021120782 W CN2021120782 W CN 2021120782W WO 2023044870 A1 WO2023044870 A1 WO 2023044870A1
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gate
drain
layer
source
sacrificial
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PCT/CN2021/120782
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English (en)
French (fr)
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刘明山
侯朝昭
董耀旗
许俊豪
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华为技术有限公司
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Priority to CN202180100879.5A priority Critical patent/CN117693820A/zh
Priority to PCT/CN2021/120782 priority patent/WO2023044870A1/zh
Publication of WO2023044870A1 publication Critical patent/WO2023044870A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present application relates to the technical field of semiconductors, in particular to a gate-all-around transistor, a preparation method thereof, a CMOS transistor and electronic equipment.
  • CMOS complementary metal oxide semiconductor
  • the field-effect transistor (Fin Field-Effect Transistor, Fin FET) era has continued to the 5nm process node.
  • Fin FET Fin Field-Effect Transistor
  • the microelectronics academic and industrial circles are planning the research and development of next-generation devices based on new materials and new architectures.
  • Gate-all-around (Gate-all-around, GAA) transistors have better current drive capability and better gate control performance than Fin FETs, so they have more advantages in terms of transistor size reduction, layout area and power consumption.
  • GAA Gate-all-around
  • the source and drain will only start epitaxial along the exposed surface of the channel layer during the initial growth, but will not be epitaxial at the SiN internal isolation part, and then along the channel layer
  • the epitaxially grown interfaces will fuse together to cover the surface of the SiN internal isolation, but defects or stacking faults will be formed at the growth-fused interfaces.
  • the strain of the source and drain formed in this way will be relaxed, and no effective compressive strain will be formed on the channel, thereby reducing the mobility of holes.
  • the present application provides a gate-all-round transistor, its preparation method, CMOS transistor and electronic equipment, which are used to increase the compressive strain of the source and drain of the P-type gate-all-round transistor to the channel.
  • a gate-all-around transistor may include a substrate, a fin structure, a source, a drain, an internal isolation portion, and a gate structure on the substrate.
  • the fin-shaped structure includes a plurality of channel layers stacked at intervals along a direction perpendicular to the substrate; the source and the drain are respectively located on both sides of the fin-shaped structure; each of the trenches
  • the side of the track layer facing the substrate is provided with two internal isolation parts, and any of the two internal isolation parts is connected to the side of the source close to the fin structure and to the drain. Oxidation is performed on one side close to the fin structure; the gate structure is located between the source and the drain and covers the fin structure.
  • an internal isolation part is formed by oxidizing the side of the source close to the spacer wall and the side of the drain close to the spacer wall, so that in the previous step, the source and The drain epitaxial growth starts along the exposed surface of the sacrificial layer and the channel layer, so the initial growth surface of the source and drain is a continuous surface, compared with the initial growth surface of the source and drain in the related art, which is multiple discontinuities On the surface, the source and drain with better crystal quality can be grown, so the fusion interface, defects, and dislocations in the epitaxial growth of the source and drain are significantly reduced.
  • the strain of the source and drain is just It will not relax and form sufficient compressive strain on the channel.
  • the source and drain of epitaxial growth will not affect the performance of the transistor. Therefore, a transistor structure compatible with N-type gate-around transistors and P-type gate-around transistors is provided.
  • the gate structure may include two sidewalls arranged opposite to each other, a gate dielectric layer wrapping each of the channel layers, and a gap between the two sidewalls.
  • the gate layer one of the two sidewalls is arranged close to the source, and the other sidewall is arranged close to the drain.
  • the material of the source electrode and the drain electrode is the same, and the material of the source electrode and the drain electrode can be set according to the structure of the device.
  • the material of the source and the drain may be a P-type doped semiconductor, for example, the P-type doped semiconductor is a P-type doped silicon germanium semiconductor.
  • the doped P-type ions may be trivalent ions, such as boron, aluminum, gallium and so on.
  • the material of the source electrode and the drain electrode is P-type doped silicon germanium semiconductor
  • the material of the internal isolation part may include silicon germanium oxide
  • the material of the source and the drain may be an N-type doped semiconductor, for example, the N-type doped semiconductor is an N-type doped silicon semiconductor.
  • the doped N-type ions may be pentavalent ions, such as nitrogen, phosphorus, arsenic and other ions.
  • the material of the internal isolation part may include silicon oxide.
  • the thickness of the internal isolation part along the channel direction can be controlled between 1nm and 5nm, for example, the internal isolation part along the channel
  • the thickness of the direction may be 1 nm, 2 nm, 3 nm, 4 nm or 5 nm.
  • the direction of the channel is parallel to the direction in which the source points to the drain.
  • a method for manufacturing a gate-all-round transistor may include the following steps: firstly forming a fin on a substrate, a sacrificial gate and two sidewalls across the fin;
  • the fins include sacrificial layers and channel layers stacked and alternately arranged repeatedly, and the two sidewalls are respectively located on both sides of the sacrificial gate; and then epitaxially grown on the exposed fins outside the sidewalls source and drain; then removing the sacrificial gate and the sacrificial layer to form a plurality of suspended channel layers; then the side of the source close to the spacer and the drain A side close to the spacer is oxidized to form a plurality of internal isolation parts; finally a gate dielectric layer and a gate layer are formed between the two sidewalls.
  • the initial growth surface of the source and drain is a continuous surface, compared with the source in the related art
  • the initial growth surfaces of the electrode and the drain are multiple discontinuous surfaces, which can grow the source and the drain with better crystal quality, so the fusion interface in the source and the drain is significantly reduced, so that the source and drain of the epitaxial growth The strain will not relax, thereby forming an effective compressive strain on the channel.
  • the source and drain are heavily doped compared to the channel layer, the heavily doped source and drain are easier to oxidize than the channel layer, and the oxidation rate of the source and drain is faster than that of the channel layer.
  • the internal isolation part can be formed only at the floating region of the source near the sidewall and the floating region of the drain near the sidewall, and the channel layer is basically not oxidized. Therefore, the source, the drain, and the gate layer formed in the floating region are physically isolated by the internal isolation part, thereby reducing parasitic capacitance.
  • the present application does not limit the thickness of the sacrificial layer and the channel layer, and the thicknesses of the sacrificial layer and the channel layer can be set according to the actual requirements of the gate-around transistor.
  • the substrate may be a semiconductor material, for example, the material of the substrate may be silicon, germanium, silicon germanium, gallium nitride, aluminum nitride, gallium arsenide, silicon carbide, zinc oxide, gallium oxide and phosphide One of indium, and not limited to the examples listed here.
  • the sacrificial layer can be formed from a material having a similar lattice constant to that of the channel layer, and in the same etching process, the sacrificial layer and the channel layer have a higher etching selectivity ratio. In subsequent selective etching, the sacrificial layer can be etched away, while the channel layer remains, so as to form a suspended channel layer.
  • the channel layer may be formed using Si semiconductor material
  • the sacrificial layer may be formed using SiGe semiconductor material.
  • the bottommost layer of the fin is a sacrificial layer
  • the topmost layer is a channel layer.
  • the sacrificial layer and the channel layer can be epitaxially grown on the substrate in sequence, and the epitaxial growth can be repeated several times, thereby forming a multi-layer sacrificial layer and a multi-layer channel layer stacked in sequence.
  • the sacrificial layer and the channel layer are then patterned by a patterning process to form fins.
  • the doping concentration of the source and the drain is greater than the doping concentration of the channel layer;
  • Oxidizing the side very close to the sidewall to form a plurality of internal isolation parts may include: oxidizing the side of the source close to the sidewall and the side of the drain close to the sidewall, so that the The oxidation rate of the source near the side wall and the oxidation rate of the drain near the side wall are greater than the oxidation rate of the channel layer; on the side of the source near the side wall And a plurality of internal isolation parts are respectively formed on the side of the drain close to the sidewall.
  • the sacrificial gate across the fin and two sidewalls can be formed through the following steps: forming a sacrificial gate material layer covering the fin; Form a mask protective layer on the layer; pattern the mask protective layer and the sacrificial gate material layer to form a sacrificial gate across the fin; form side gates on both sides of the sacrificial gate respectively wall.
  • the sacrificial gate material layer may be formed using any suitable material, including one of polysilicon, germanium, silicon nitride, silicon oxide or a combination thereof.
  • the mask protection layer is used to protect the sacrificial gate material layer from being exposed in subsequent process steps.
  • the mask protection layer can be formed using a hard mask material, such as silicon nitride.
  • the sidewalls may be formed of low dielectric constant materials, such as including but not limited to silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide and combinations thereof.
  • low dielectric constant materials such as including but not limited to silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide and combinations thereof.
  • CVD chemical Vapor Deposition
  • ALD atomic layer deposition
  • a third aspect provides a CMOS transistor, which includes two gate-around transistors as described in the first aspect or various implementation manners of the first aspect, wherein the two gate-around transistors can be N-type respectively transistors and P-type transistors.
  • an electronic device in a fourth aspect, includes a circuit board, and the gate-all-round transistor as described in the first aspect or various implementation manners of the first aspect is arranged on the circuit board, and/or is set The CMOS transistor described in various implementation manners of the third aspect on the circuit board.
  • FIG. 1 is a schematic diagram of a three-dimensional structure of a gate-all-around transistor provided by the related art
  • Fig. 2 is a schematic cross-sectional structure diagram of the gate-all-around transistor shown in Fig. 1 along the direction AA';
  • 3a to 3i are structural schematic diagrams of the preparation process of the gate-all-around transistor provided by the related art
  • FIG. 4 is a schematic diagram of source and drain growth in a gate-all-around transistor provided by the related art
  • FIG. 5 is a schematic structural diagram of a gate-all-around transistor provided in an embodiment of the present application.
  • FIG. 6 is a flowchart of a method for manufacturing a gate-all-around transistor provided in an embodiment of the present application
  • FIG. 7a to 7h are three-dimensional structural schematic diagrams of the preparation process of the gate-all-around transistor in the embodiment of the present application.
  • 8a to 8i are schematic cross-sectional structure diagrams of the fabrication process of the gate-all-around transistor in the embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a CMOS transistor provided in an embodiment of the present application.
  • FIG. 10 is a flowchart of a method for manufacturing a CMOS transistor provided in an embodiment of the present application.
  • 11a to 11h are three-dimensional structural schematic diagrams of the manufacturing process of the CMOS transistor in the embodiment of the present application.
  • 061 sacrificial gate material layer 062 mask protection layer;
  • the gate-all-around transistor can achieve ideal control over the channel because the gate structure can be arranged around the channel. Therefore, the gate-all-around transistor provided by the embodiment of the present application can be widely used in various scenarios as components of electronic equipment, such as The electronic device may be a logic device, a processor, etc. It should be noted that the gate-all-around transistor proposed in the embodiment of the present application is intended to include but not be limited to be applied in these and any other suitable types of electronic devices.
  • Figure 1 is a schematic diagram of a three-dimensional structure of a gate-all-around transistor in the related art
  • Figure 2 is a cross-section of the gate-all-round transistor shown in Figure 1 along the direction AA' Schematic.
  • Its preparation process may include: (1) as shown in Figure 3a, alternate epitaxial growth of SiGe layer 11 and Si layer 12; (2) as shown in Figure 3b, patterning SiGe layer 11 and Si layer 12 to form fins 1 (3) As shown in Figure 3c, form a sacrificial gate (dummy gate) 2 and sidewalls 3 located on both sides of the sacrificial gate 2; (4) As shown in Figure 3d, remove the fins 1 on the outside of the sidewall 3 (5) as shown in Figure 3e, remove the SiGe layer 11 below the sidewall 3; (6) as shown in Figure 3f, deposit a SiN inner spacer (inner spacer) 4 at the gap below the sidewall 3; (7 ) as shown in FIG.
  • 3g epitaxially grow source 51 and drain 52; (8) as shown in FIG. 3h, remove sacrificial gate 2 to expose SiGe layer 11 and Si layer 12 below sacrificial gate 2; ) As shown in Figure 3i, remove the remaining SiGe layer 11 in the fin 1, leaving the suspended Si layer 12 as a channel material; (10) As shown in Figure 1 and Figure 2, form a gate dielectric layer 6 and a gate polar layer7.
  • the epitaxial growth of the source and drain is critical.
  • a source-drain strain source such as SiGe
  • the source electrode 51 and the drain electrode 52 are first epitaxially grown along the exposed surface of the Si layer 12, and then these growth surfaces will be fused together, and will also cover the SiN internal isolation. At this time, defects or stacking faults will be formed at the interface where the growth merges, until the growth of the entire source 51 and drain 52 is completed. In this way, the strain on the source 51 and the drain 52 will be relaxed, and no effective compressive strain will be formed on the channel, thus not helpful to the improvement of hole mobility.
  • the embodiment of the present application provides a gate-all-around transistor and a manufacturing method thereof, which can maintain sufficient compressive strain on the channel from the epitaxially grown source and drain.
  • references to "one embodiment” or “some embodiments” or the like in this specification means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application.
  • appearances of the phrases “in one embodiment,” “in some embodiments,” “in other embodiments,” “in other embodiments,” etc. in various places in this specification are not necessarily All refer to the same embodiment, but mean “one or more but not all embodiments” unless specifically stated otherwise.
  • the terms “including”, “comprising”, “having” and variations thereof mean “including but not limited to”, unless specifically stated otherwise.
  • FIG. 5 is a schematic structural diagram of a gate-all-around transistor provided by an embodiment of the present application.
  • the gate-all-around transistor 100 may include a substrate 01 , a fin structure 02 on the substrate 01 , a source 031 , a drain 032 , a plurality of internal isolation parts 04 and a gate structure 05 .
  • the fin structure 02 includes a plurality of channel layers 021 stacked at intervals along a direction perpendicular to the substrate 01; the source 031 and the drain 032 are respectively located on both sides of the fin structure 02 ; Each channel layer 021 facing the substrate 01 side is provided with two internal isolation parts 04, and any of the two internal isolation parts 04 is obtained by making the source 031 close to the One side of the fin structure 02 and the side of the drain 032 close to the fin structure 02 are formed by oxidation; the gate structure 05 is located between the source 031 and the drain 032 and covers the Fin structure 02.
  • the gate structure 05 may include two sidewalls 051 opposite to each other, a gate dielectric layer 052 wrapping each of the channel layers 021, and filling the two sidewalls.
  • the gate layer 053 in the gap between the walls 051 one of the two sidewalls 051 is arranged close to the source 031 , and the other sidewall 051 is arranged close to the drain 032 .
  • FIG. 6 shows a schematic flowchart of a method for manufacturing a gate-all-around transistor provided in an embodiment of the present application.
  • the method may include the following steps:
  • Step S101 forming a fin on the substrate, a sacrificial gate and two side walls across the fin; the fin includes sacrificial layers and channel layers stacked and alternately arranged repeatedly, and the two side walls The walls are respectively located on both sides of the sacrificial grid;
  • the fin 02 ′ includes sacrificial layers 022 and channel layers stacked and alternately arranged repeatedly. 021.
  • a sacrificial gate 06 and two sidewalls 051 across the fin 02' are then formed, and the two sidewalls 051 are respectively located on both sides of the sacrificial gate 06. .
  • the fins 02' exposed outside the sidewalls 051 are finally removed, and the fins 02' located under the sacrificial gate 06 and the sidewalls 051 are retained.
  • Figure 8a is a schematic cross-sectional view of the structure shown in Figure 7a along the direction AA'
  • Figure 8b is a schematic cross-sectional view of the structure shown in Figure 7b along the direction AA'
  • Figure 8c is a schematic cross-sectional view of the structure shown in Figure 7c along the direction AA'.
  • the gate-all-around transistor includes three layers of sacrificial layers 022 and three layers of channel layers 021 as an example for illustration. It can be understood that in the gate-all-around transistor, the number of layers of the sacrificial layer 022 and the channel layer 021 can be determined according to the actual requirements of the device, which is not limited here. For example, the numbers of the sacrificial layer 022 and the channel layer 021 can be set according to the conductivity of the gate-around transistor.
  • the present application does not limit the thicknesses of the sacrificial layer 022 and the channel layer 021 , and the thicknesses of the sacrificial layer 022 and the channel layer 021 can be set according to requirements of an actual gate-around transistor.
  • the substrate 01 may be a semiconductor material.
  • the material of the substrate 01 may be silicon, germanium, silicon germanium, gallium nitride, aluminum nitride, gallium arsenide, silicon carbide, zinc oxide, gallium oxide and One of indium phosphide, and not limited to the examples listed here.
  • the sacrificial layer 022 can be formed from a material having a similar lattice constant to that of the channel layer 021, and in the same etching process, the sacrificial layer 022 and the channel layer 021 have a higher etching selectivity ratio, In this way, during subsequent selective etching, the sacrificial layer 022 can be etched away, while the channel layer 021 remains, so as to form the suspended channel layer 021 .
  • the channel layer 021 may be formed using Si semiconductor material
  • the sacrificial layer 022 may be formed using SiGe semiconductor material.
  • the bottommost layer of the fin 02' is the sacrificial layer 022, and the topmost layer is the channel layer 021.
  • the sacrificial layer 022 and the channel layer 021 can be epitaxially grown on the substrate 01 in sequence, and the epitaxial growth can be repeated several times, thereby forming a multi-layer sacrificial layer 022 and a multi-layer channel layer 021 stacked in sequence.
  • the sacrificial layer 022 and the channel layer 021 are patterned by a patterning process to form fins 02'.
  • the extension method of the sacrificial gate 06 can be set to be perpendicular to the extension direction of the fin 02'.
  • the sacrificial gate 06 may be formed in the following manner: firstly, a sacrificial gate material layer covering the fin 02' is formed; then a mask protection layer is formed on the sacrificial gate material layer and then patterning the mask protection layer and the sacrificial gate material layer to form a sacrificial gate 06 across the fin 02' as shown in Figure 7b and Figure 8b, that is, the sacrificial gate
  • the pole 06 includes a patterned sacrificial gate material layer 061 and a mask protection layer 062 ; then spacers 051 are respectively formed on both sides of the sacrificial gate 06 .
  • the sacrificial gate material layer 061 may be formed using any suitable material, including one of polysilicon, germanium, silicon nitride, silicon oxide or a combination thereof.
  • the protective mask layer 062 is used to protect the sacrificial gate material layer 061 from being exposed in subsequent process steps.
  • the mask protection layer 061 can be formed using a hard mask material, such as silicon nitride.
  • the spacer wall 051 can be formed using a material with a low dielectric constant, such as including but not limited to silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide and combinations thereof.
  • a material with a low dielectric constant such as including but not limited to silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide and combinations thereof.
  • conventional CVD method or ALD method can be used to deposit the sidewall 051 , which is not limited here.
  • Step S102 epitaxially grow the source 031 and the drain 032 on the exposed fin 02' outside the spacer 051.
  • 8d is a schematic cross-sectional view of the structure shown in FIG. 7d along the direction AA'.
  • the material of the source 031 and the drain 032 is the same, and the material of the source 031 and the drain 032 can be set according to the structure of the device.
  • the material of the source 031 and the drain 032 may be a P-type doped semiconductor, for example, the P-type doped semiconductor is a P-type doped silicon germanium semiconductor.
  • the doped P-type ions may be trivalent ions, such as boron, aluminum, gallium and other ions.
  • the material of the source 031 and the drain 032 may be an N-type doped semiconductor, for example, the N-type doped semiconductor is an N-type doped silicon semiconductor.
  • the doped N-type ions may be pentavalent ions, such as nitrogen, phosphorus, arsenic and other ions.
  • the initial growth surfaces of the source 031 and the drain 032 are a continuous surface.
  • the source 031 and the drain 032 with better crystal quality can be grown, so the fusion interface in the source 031 and the drain 032 is significantly
  • the strain of the epitaxially grown source 031 and drain 032 will not be relaxed, thereby forming an effective compressive strain on the channel.
  • the epitaxially grown source 031 and drain 032 will not affect the performance of the transistor. Therefore, a transistor structure compatible with N-type gate-around transistors and P-type gate-around transistors is provided.
  • Step S103 removing the sacrificial gate and the sacrificial layer to form a plurality of suspended channel layers.
  • the sacrificial gate 06 may be removed first, so as to expose the fin 02' located below the sacrificial gate 06.
  • the sacrificial layer 022 in the fin 02' is removed to form a plurality of suspended channel layers 021.
  • Fig. 8e is a schematic cross-sectional view of the structure shown in Fig. 7e along the direction AA'
  • Fig. 8f is a schematic cross-sectional view of the structure shown in Fig. 7f along the direction AA'.
  • the sacrificial gate 06 may be removed by dry etching, wet etching or a combination thereof, which is not limited herein.
  • the sacrificial layer 022 in the fin 02' may be removed by dry etching or wet etching, which is not limited herein.
  • the sacrificial layer 022 in the fin 02' can be selectively etched away by using an etching method significantly higher than the etching rate of the channel layer 021, so that the remaining channel layer 021 is suspended, here
  • the suspended channel layer 021 may be called a nanowire channel.
  • Step S104 oxidizing the side of the source 031 close to the sidewall 051 and the side of the drain 032 close to the sidewall 051 to form a plurality of internal isolation parts 04 .
  • the doping concentration of the source and the drain is generally greater than the doping concentration of the channel layer.
  • the oxidation rate of the source near the side wall and the drain near the side wall is greater than the oxidation rate of the channel layer, so that a plurality of internal quarantine department.
  • the source 031 and the drain 032 are heavily doped compared to the channel layer 021, and the heavily doped source 031 and the drain 032 are easier to oxidize than the channel layer 021.
  • the oxidation rate is faster than that of the channel layer 021, oxidizing the side of the source 031 close to the sidewall 051 and the side of the drain 032 close to the sidewall 051 can make the source 031 and the drain Part of the oxidized volume of 032 expands toward the suspended area, so that internal isolation can be formed only at the suspended area on the side of the source 031 close to the sidewall 051 and the suspended area of the drain 032 on the side close to the sidewall 051 part 04, and the channel layer 021 is substantially not oxidized.
  • the material of the internal isolation part 04 may include silicon germanium oxide.
  • the material of the internal isolation part 04 may include silicon oxide.
  • the doping concentration of the channel layer 021 is low or not doped, while the doping concentration of the source electrode 031 and the drain electrode 032 is relatively high.
  • the source 031 and the drain 032 are P-type doped SiGe semiconductors, since SiGe is easier to oxidize than Si, and heavily doped SiGe is also easier to oxidize than undoped or lightly doped Si, thus using the source
  • the oxidation rate of the electrode 031 and the drain 032 is faster than that of the Si channel layer 021, so that the internal isolation part 04 of SiGeOx can be formed.
  • the source 031 and the drain 032 are N-type doped Si semiconductors, since heavily doped Si is easier to oxidize than undoped Si, the oxidation rate of the source 031 and the drain 032 is higher than that of the Si channel
  • the layer 021 is fast, so that the internal isolation part 04 of SiO x can be formed.
  • Exemplary, low-temperature steam oxidation (steam oxidation) method can be used to oxidize the source and drain, wherein, low temperature can effectively avoid the diffusion of impurity atoms and germanium atoms in the source and drain, so that SiGe can be realized Under this condition, the silicon channel layer only generates a thin layer of native oxide (native oxide), so as to achieve the purpose of selective oxidation.
  • steam oxidation steam oxidation
  • the internal isolation part 04 is a material with a low dielectric constant, which can physically isolate the source electrode 031 , the drain electrode 032 and the gate layer subsequently formed in the floating region, thereby reducing parasitic capacitance.
  • the thickness of the internal isolation part 04 along the channel direction can be controlled between 1nm and 5nm, for example, 1nm , 2nm, 3nm, 4nm or 5nm.
  • the channel direction is parallel to the direction in which the source 031 points to the drain 032 .
  • Step S105 forming a gate dielectric layer and a gate layer between the two spacers.
  • a gate dielectric layer 052 wrapping each of the channel layers 021 can be formed first; as shown in FIG. 7h and FIG. 8i, and then A gate layer 053 is formed between the spacers 051.
  • Figure 8h is a schematic cross-sectional view of the structure shown in Figure 7g along the direction AA'
  • Figure 8i is a schematic cross-sectional view of the structure shown in Figure 7h along the direction AA'.
  • an all-enveloping gate dielectric layer 052 may be formed on the surface of each of the channel layers 021 by using atomic layer deposition or low pressure chemical vapor deposition.
  • the gate dielectric layer 052 can be formed using a material with a high dielectric constant, such as Si, titanium (Ti), zirconium (Zr), hafnium (Hf) oxide or oxynitride, for example, the The gate dielectric layer 052 may be a dielectric layer formed by any one of SiO 2 , HfON, HfO 2 , ZrO, TiO 2 or a stack thereof.
  • the gate layer 053 may be formed on the surface of the gate dielectric layer 052 by atomic layer deposition until the gate layer 053 completely fills the gap between the two spacers 051 .
  • the gate layer 053 may be formed of titanium, titanium nitride, aluminum, tungsten, tantalum nitride or a stack of the above materials.
  • the fabrication of the gate-all-around transistor is completed.
  • the source by oxidizing the side of the source 031 close to the sidewall 051 and the side of the drain 032 close to the sidewall 051 to form an internal isolation part 04, the source can be 031 and the drain 032 start along the exposed surfaces of the sacrificial layer 022 and the channel layer 021 during the epitaxial growth, so the initial growth surfaces of the source 031 and the drain 032 are a continuous surface.
  • the source 031 and the drain 032 Compared with the initial growth planes of the source 031 and the drain 032 in the related art, which are multiple discontinuous planes, the source 031 and the drain 032 with better crystal quality can be grown, so the fusion interface in the source 031 and the drain 032 is significantly
  • the strain of the epitaxially grown source 031 and drain 032 will not be relaxed, thereby forming an effective compressive strain on the channel.
  • the epitaxially grown source 031 and drain 032 will not affect the performance of the transistor.
  • the preparation method is compatible with the existing CMOS transistor technology, it is especially suitable for the preparation of N-type MOS transistors and P-type MOS transistors below the 5nm node.
  • the embodiment of the present application also provides a CMOS transistor, as shown in FIG. Type transistor 100_n and P type transistor 100_P. Since the problem-solving principle of the CMOS transistor is similar to that of the aforementioned gate-all-around transistor, the implementation of the CMOS transistor can refer to the implementation of the aforementioned gate-all-around transistor, and repeated descriptions will not be repeated here.
  • two gate-around transistors may share a gate structure.
  • the preparation method includes the following steps:
  • Step S201 as shown in FIG. 11a, two fins 02' arranged along the first direction X are formed on the substrate 01, and each fin 02' includes sacrificial layers 022 and channel layers stacked and alternately arranged 021.
  • the first direction X is perpendicular to the direction AA'.
  • Step S202 as shown in FIG. 11 b , forming a sacrificial gate 06 and two sidewalls 051 across the two fins 02 ′, and the two sidewalls 051 are respectively located on two sides of the sacrificial gate 06 . side, the sacrificial gate 06 and the spacer 051 both extend along the first direction X.
  • Step S203 remove the exposed parts of the two fins 02' outside the sidewall 051, and keep the two fins 02' located between the sacrificial gate 06 and the sidewall The part below 051.
  • Step S204 epitaxially grow the source 031 and the drain 032 on the two exposed fins 02' outside the spacer 051.
  • the material of the source 031 and the drain 032 on both sides of one fin 02' is P-type doped semiconductor, and the material of the source 031 and drain 032 on both sides of the other fin 02' is N-type doped semiconductor .
  • Step S205 as shown in FIG. 11e , removing the sacrificial gate 06 to expose two fins 02' under the sacrificial gate 06.
  • Step S206 as shown in Figure 11f, removing the sacrificial layer 022 in each of the fins 02' to form a plurality of suspended channel layers 021.
  • Step S207 oxidize the side of the source 031 close to the sidewall 051 and the side of the drain 032 close to the sidewall 051 to form an internal isolation part 04 .
  • Step S208 as shown in FIG. 11 g , forming a gate dielectric layer 052 surrounding each of the channel layers 021 .
  • Step S209 as shown in FIG. 11 h , forming a gate layer 053 between the two sidewalls 051 .
  • steps S201-S209 may refer to steps S101-S105, which will not be repeated here.
  • an embodiment of the present application further provides an electronic device, including a circuit board, a gate-around transistor disposed on the circuit board, and/or a CMOS transistor disposed on the circuit board. Since the problem-solving principle of the electronic device is similar to that of the aforementioned gate-all-around transistor, the implementation of the electronic device can refer to the aforementioned implementation of the gate-all-around transistor, and repeated descriptions will not be repeated.

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Abstract

一种环栅晶体管、其制备方法、CMOS晶体管及电子设备，其中，环栅晶体管（100）包括衬底（01）以及位于衬底（01）上的鳍形结构（02）、源极（031）、漏极（032）、内部隔离部（04）和栅极结构（05）。由于内部隔离部（04）是通过对源极（031）靠近侧墙（051）一侧以及对漏极（032）靠近侧墙（051）一侧进行氧化形成，可以使源极（031）和漏极（032）在外延生长时是沿着牺牲层（022）和沟道层（021）的暴露面开始，因此源极（031）和漏极（032）的初始生长面是一连续面，相比源极（031）和漏极（032）的初始生长面为多个间断面，可以生长出晶体质量较好的源极（031）和漏极（032），对于P型环栅晶体管，源极（031）和漏极（032）的应变就不会驰豫掉，进而对沟道形成足够的压应变。对于N型环栅晶体管，外延生长的源极（031）和漏极（032）也不会影响晶体管的性能。

Description

环栅晶体管、其制备方法、CMOS晶体管及电子设备 技术领域
本申请涉及半导体技术领域，尤其涉及到一种环栅晶体管、其制备方法、CMOS晶体管及电子设备。
背景技术
随着摩尔定律的持续推进，芯片中晶体管的尺寸持续微缩，集成度不断提高，工作电压不断减小，以此来满足芯片高性能，低功耗的需求。从第一个晶体管的发明到目前的主流5nm技术节点，经历了半个多世纪，在每一个技术节点，创新的工艺技术被提出来进一步推动晶体管的发展。传统的晶体管特征尺寸的持续微缩已经达到了物理极限，导致芯片功耗，性能和成本的矛盾，因此互补金属氧化物半导体(Complementary metal oxide semiconductor，CMOS)器件从二维平面结构进入到了3D鳍式场效应晶体管(Fin Field-Effect Transistor，Fin FET)时代，并且已经延续到了5nm工艺节点。为了进一步延伸摩尔定律，微电子学术界和工业界纷纷布局基于新材料和新架构的下一代器件的研发。环栅(Gate-all-around，GAA)晶体管比Fin FET具有更好的电流驱动能力，更优异的栅控性能，从而在晶体管尺寸微缩，版图面积以及功耗方面，更有优势，成为5nm以下节点的候选结构。但是现有的P型环栅晶体管中，源极和漏极在初始生长时只会沿着沟道层的暴露面开始外延，而在SiN内部隔离部处不会外延，之后沿着沟道层外延生长的界面会融合在一起，从而覆盖住SiN内部隔离部的表面，但是在生长融合的界面处会形成缺陷(defects)或者堆叠层错(stacking faults)。这样形成的源极和漏极的应变就会驰豫掉，对沟道形成不了有效的压应变，从而降低空穴的迁移率。
发明内容
本申请提供了一种环栅晶体管、其制备方法、CMOS晶体管及电子设备，用于提高P型环栅晶体管中源极和漏极对沟道的压应变。
第一方面，提供了一种环栅晶体管，该环栅晶体管可以包括衬底以及位于所述衬底上的鳍形结构、源极、漏极、内部隔离部和栅极结构。其中，所述鳍形结构包括沿垂直于所述衬底方向间隔堆叠的多个沟道层；所述源极和所述漏极分别位于所述鳍形结构的两侧；每一所述沟道层面向所述衬底一侧均设置有两个所述内部隔离部，且任意所述两个内部隔离部是通过对所述源极靠近所述鳍形结构一侧以及对所述漏极靠近所述鳍形结构一侧进行氧化形成；所述栅极结构位于所述源极和所述漏极之间且覆盖所述鳍形结构。
本申请提供的环栅晶体管，通过对所述源极靠近所述侧墙一侧以及对所述漏极靠近所述侧墙一侧进行氧化形成内部隔离部，从而在之前步骤中，源极和漏极外延生长沿着牺牲层和沟道层的暴露面开始，因此源极和漏极的初始生长面是一连续面，相比相关技术中源极和漏极的初始生长面为多个间断面，可以生长出晶体质量较好的源极和漏极，因此源极和漏极外延生长中融合界面、缺陷、位错显著减少，对于P型环栅晶体管，源极和漏极的应变就不会驰豫掉，进而对沟道形成足够的压应变。对于N型环栅晶体管，外延生长的源极和漏极也不会影响晶体管的性能。从而提供一种兼容N型环栅晶体管和P型环栅晶体管 的晶体管结构。
示例性的，在本申请中，所述栅极结构可以包括相对设置的两个侧墙、包裹各所述沟道层的栅介电层、以及填充所述两个侧墙之间的间隙的栅极层，所述两个侧墙中一个所述侧墙靠近所述源极设置，另一个所述侧墙靠近所述漏极设置。
在具体实施时，所述源极和漏极的材料相同，所述源极和所述漏极的材料可以根据器件的结构设定。
当环栅晶体管为P型晶体管时，源极和漏极的材料可以为P型掺杂半导体，例如所述P型掺杂半导体为P型掺杂的锗硅半导体。其中，掺杂的P型离子可以为三价离子，例如硼、铝、镓等离子。
在具体实施时，当源极和漏极的材料为P型掺杂的锗硅半导体，内部隔离部的材料可以包括氧化锗硅。
当环栅晶体管为N型晶体管时，源极和漏极的材料可以为N型掺杂半导体，例如所述N型掺杂半导体为N型掺杂的硅半导体。其中，掺杂的N型离子可以为五价离子，例如氮、磷、砷等离子。
在具体实施时，当源极和漏极的材料为N型掺杂的硅半导体，内部隔离部的材料可以包括氧化硅。
为了对源极与栅极层，以及漏极与栅极层进行有效的隔离，示例性的，内部隔离部沿沟道方向的厚度可以控制在1nm～5nm之间，例如内部隔离部沿沟道方向的厚度可以为1nm、2nm、3nm、4nm或5nm。其中，在本申请中，沟道方向与源极指向漏极的方向平行。
第二方面，提供了一种环栅晶体管的制备方法，该制备方法可以包括以下步骤：首先在衬底上形成鳍片以及横跨所述鳍片的牺牲栅极和两个侧墙；所述鳍片包括层叠且交替重复设置的牺牲层和沟道层，所述两个侧墙分别位于所述牺牲栅极的两侧；然后在所述侧墙外侧且裸露的所述鳍片处外延生长源极和漏极；接着去除所述牺牲栅极和所述牺牲层，形成多个悬空的所述沟道层；接着再对所述源极靠近所述侧墙一侧以及对所述漏极靠近所述侧墙一侧进行氧化形成多个内部隔离部；最后在所述两个侧墙之间形成栅介电层和栅极层。
在该申请中，由于源极和漏极在外延生长时是沿着牺牲层和沟道层的暴露面开始，因此源极和漏极的初始生长面是一连续面，相比相关技术中源极和漏极的初始生长面为多个间断面，可以生长出晶体质量较好的源极和漏极，因此源极和漏极中融合界面显著减少，从而外延生长的源极和漏极的应变就不会驰豫掉，进而对沟道形成有效的压应变。并且，由于源极和漏极相比沟道层为重掺杂，重掺杂的源极和漏极比沟道层更容易氧化，利用源极和漏极的氧化率比沟道层的快，从而可以仅在源极靠近所述侧墙一侧的悬空区域以及所述漏极靠近所述侧墙一侧的悬空区域处形成内部隔离部，而沟道层基本不被氧化。从而利用内部隔离部物理隔离源极、漏极和形成在悬空区域中的栅极层，从而减小寄生电容。
本申请对牺牲层和沟道层的厚度不作限定，可以根据实际环栅晶体管要求设定牺牲层和沟道层的厚度。
在本申请中，衬底可以是半导体材料，例如，衬底的材质可以为硅、锗、硅锗、氮化镓、氮化铝、砷化镓、碳化硅、氧化锌及氧化镓及磷化铟中的一种，且并不限于此处所列举的示例。
在本申请中，牺牲层可以选与沟道层具有相近的晶格常数的材料形成，并且在同一刻蚀工艺中，牺牲层与沟道层具有较高的刻蚀选择比，这样，在进行后续的选择性刻蚀时可 以将牺牲层刻蚀掉，而保留沟道层，从而形成悬空的沟道层。示例性的，沟道层可以采用Si半导体材料形成，牺牲层可以采用SiGe半导体材料形成。
在具体实施时，在鳍片中最底层为牺牲层，最顶层为沟道层。在制备时，可以在衬底依次外延生长牺牲层和沟道层，重复外延生长多次，从而形成依次层叠设置的多层牺牲层和多层沟道层。然后采用构图工艺对牺牲层和沟道层进行图形化，从而形成鳍片。
在一种可行的实现方式中，所述源极、所述漏极的掺杂浓度大于所述沟道层的掺杂浓度；对所述源极靠近所述侧墙一侧以及对所述漏极靠近所述侧墙一侧进行氧化形成多个内部隔离部，可以包括：对所述源极靠近所述侧墙一侧以及对所述漏极靠近所述侧墙一侧进行氧化，使所述源极靠近所述侧墙一侧的氧化速率以及所述漏极靠近所述侧墙一侧的氧化速率大于所述沟道层的氧化速率；在所述源极靠近所述侧墙一侧以及对所述漏极靠近所述侧墙一侧分别形成多个内部隔离部。
在一种可行的实现方式中，可以通过如下步骤形成横跨所述鳍片的牺牲栅极和两个侧墙：形成覆盖所述鳍片的牺牲栅极材料层；在所述牺牲栅极材料层上形成掩膜保护层；对所述掩膜保护层和所述牺牲栅极材料层进行构图，形成横跨所述鳍片的牺牲栅极；在所述牺牲栅极的两侧分别形成侧墙。
其中，牺牲栅极材料层可以采用任何适当的材料形成，包括多晶硅、锗、氮化硅、氧化硅或其组合中的一个。在该实施例中，掩膜保护层用于保护牺牲栅极材料层以防其在后续工艺步骤中被暴露。示例性的，掩膜保护层可以采用硬掩膜材料形成，例如氮化硅。
示例性的，侧墙可以采用低介电常数的材料形成，例如包括但不限于氮化硅、氧化硅、氮氧化硅，碳氧化硅及其组合。在具体实施时，可以采用常规的化学气相沉积(Chemical Vapor Deposition，CVD)或者原子层沉积(Atomic Layer Deposition，ALD)法来沉积侧墙，在此不作限定。
第三方面，提供了一种CMOS晶体管，该CMOS晶体管包括两个如第一方面或第一方面的各种实施方式所述的环栅晶体管，其中两个所述环栅晶体管可以分别为N型晶体管和P型晶体管。
第四方面，提供了一种电子设备，该电子设备包括电路板，设置在所述电路板上的如第一方面或第一方面的各种实施方式所述的环栅晶体管，和/或设置在所述电路板上的如第三方面的各种实施方式所述的CMOS晶体管。
上述第三方面和第四方面可以达到的技术效果可以参照上述第一方面中任一可能设计可以达到的技术效果说明，这里不再重复赘述。
附图说明
图1为相关技术提供的环栅晶体管的立体结构示意图；
图2为图1所示的环栅晶体管沿AA’方向的剖面结构示意图；
图3a～图3i为相关技术提供的环栅晶体管的制备过程的结构示意图；
图4为相关技术提供的环栅晶体管中源极和漏极生长的示意图；
图5为本申请实施例提供的一种环栅晶体管的结构示意图；
图6为本申请一种实施例提供的环栅晶体管的制备方法的流程图；
图7a～图7h为本申请实施例中环栅晶体管的制备过程的立体结构示意图；
图8a～图8i为本申请实施例中环栅晶体管的制备过程的剖面结构示意图；
图9为本申请实施例提供的一种CMOS晶体管的结构示意图；
图10为本申请一种实施例提供的CMOS晶体管的制备方法的流程图；
图11a～图11h为本申请实施例中CMOS晶体管的制备过程的立体结构示意图。
附图标记说明：
100     环栅晶体管；                01     衬底；
02      鳍形结构；                  02’    鳍片；
021     沟道层；                    022    牺牲层；
031     源极；                      032     漏极；
04      内部隔离部；                05     栅极结构；
051     侧墙；                      052    栅介电层；
053     栅极层；                    06     牺牲栅极；
061     牺牲栅极材料层；             062   掩膜保护层；
100_n   N型晶体管；                 100_P P型晶体管。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本申请更全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。在图中相同的附图标记表示相同或类似的结构，因而将省略对它们的重复描述。本申请中所描述的表达位置与方向的词，均是以附图为例进行的说明，但根据需要也可以做出改变，所做改变均包含在本申请保护范围内。本申请的附图仅用于示意相对位置关系不代表真实比例。
需要说明的是，在以下描述中阐述了具体细节以便于充分理解本申请。但是本申请能够以多种不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本申请内涵的情况下做类似推广。因此本申请不受下面公开的具体实施方式的限制。说明书后续描述为实施本申请的较佳实施方式，所述描述乃以说明本申请的一般原则为目的，并非用以限定本申请的范围。本申请的保护范围当视所附权利要求所界定者为准。
为了方便理解本申请实施例提供的一种环栅晶体管，下面首先介绍一下其应用场景。
环栅晶体管由于栅极结构可以围绕沟道设置而能实现对沟道的理想控制，因此，本申请实施例提供的环栅晶体管可以作为电子设备的元器件被广泛应用在各种场景中，例如该电子设备可以为逻辑器件、处理器等，应注意的是，本申请实施例提出的环栅晶体管旨在包括但不限于应用在这些和任意其它适合类型的电子设备中。
目前，常见的环栅晶体管的结构如图1和图2所示，其中，图1为相关技术中环栅晶体管的立体结构示意图；图2为图1所示的环栅晶体管沿AA’方向的剖面结构示意图。其制备工艺流程可以包括：(1)如图3a所示，交替外延生长SiGe层11和Si层12；(2)如图3b所示，对SiGe层11和Si层12进行构图形成鳍片1；(3)如图3c所示，形成牺牲栅极(dummy gate)2和位于牺牲栅极2两侧的侧墙3；(4)如图3d所示，去除侧墙3外侧的鳍片1；(5)如图3e所示，去除侧墙3下方的SiGe层11；(6)如图3f所示，在侧墙3下方的空隙处沉积SiN内部隔离部(inner spacer)4；(7)如图3g所示，外延生长源极51和漏极52；(8)如图3h所示，去除牺牲栅极2，以露出牺牲栅极2下方的SiGe层11 和Si层12；(9)如图3i所示，去除鳍片1中剩余的SiGe层11，留下悬空的Si层12作为沟道材料；(10)如图1和图2所示，形成栅介电层6和栅极层7。
在该环栅晶体管中，源极和漏极的外延生长很关键，在P型器件中希望引入源漏应变源，比如SiGe，从而引起对沟道的压应变，这样有利于沟道中空穴迁移率的提高以及电学性能的改善。然而在实际制备工艺中，如图4所示，源极51和漏极52在生长时首先沿着Si层12的暴露面开始外延，之后这些生长面会融合在一起，也会覆盖住SiN内部隔离部4的表面，此时在生长融合的界面处会形成缺陷(defects)或者堆叠层错(stacking faults)，直至完成整个源极51和漏极52的生长。这样源极51和漏极52的应变就会驰豫掉，对沟道形成不了有效的压应变，从而对空穴迁移率的提高没有帮助。
为此，本申请实施例提供了一种环栅晶体管及其制备方法，可以使外延生长的源极和漏极对沟道保持足够的压应变。下面将结合附图对本申请作进一步地详细描述。
以下实施例中所使用的术语只是为了描述特定实施例的目的，而并非旨在作为对本申请的限制。如在本申请的说明书和所附权利要求书中所使用的那样，单数表达形式“一个”、“一种”、“所述”、“上述”、“该”和“这一”旨在也包括例如“一个或多个”这种表达形式，除非其上下文中明确地有相反指示。
在本说明书中描述的参考“一个实施例”或“一些实施例”等意味着在本申请的一个或多个实施例中包括结合该实施例描述的特定特征、结构或特点。由此，在本说明书中的不同之处出现的语句“在一个实施例中”、“在一些实施例中”、“在其他一些实施例中”、“在另外一些实施例中”等不是必然都参考相同的实施例，而是意味着“一个或多个但不是所有的实施例”，除非是以其他方式另外特别强调。术语“包括”、“包含”、“具有”及它们的变形都意味着“包括但不限于”，除非是以其他方式另外特别强调。
参见图5，图5为本申请实施例提供的一种环栅晶体管的结构示意图。该环栅晶体管100可以包括衬底01以及位于所述衬底01上的鳍形结构02、源极031、漏极032、多个内部隔离部04和栅极结构05。其中，所述鳍形结构02包括沿垂直于所述衬底01方向间隔堆叠的多个沟道层021；所述源极031和所述漏极032分别位于所述鳍形结构02的两侧；每一所述沟道层021面向所述衬底01一侧均设置有两个所述内部隔离部04，且任意所述两个内部隔离部04是通过对所述源极031靠近所述鳍形结构02一侧以及对所述漏极032靠近所述鳍形结构02一侧进行氧化形成；所述栅极结构05位于所述源极031和所述漏极032之间且覆盖所述鳍形结构02。
在具体实施时，如图5所示，所述栅极结构05可以包括相对设置的两个侧墙051、包裹各所述沟道层021的栅介电层052、以及填充所述两个侧墙051之间的间隙的栅极层053，所述两个侧墙051中一个所述侧墙051靠近所述源极031设置，另一个所述侧墙051靠近所述漏极032设置。
参见图6，图6示出了本申请实施例提供的环栅晶体管的制备方法的流程示意图，该制备方法可以包括以下步骤：
步骤S101、在衬底上形成鳍片以及横跨所述鳍片的牺牲栅极和两个侧墙；所述鳍片包括层叠且交替重复设置的牺牲层和沟道层，所述两个侧墙分别位于所述牺牲栅极的两侧；
在一种可行的实现方式中，如图7a和图8a所示，先在衬底01上形成鳍片02’，所述鳍片02’包括层叠且交替重复设置的牺牲层022和沟道层021。如图7b和图8b所示，然后形成横跨所述鳍片02’的牺牲栅极06和两个侧墙051，且所述两个侧墙051分别位于所述 牺牲栅极06的两侧。如图7c和图8c所示，最后去除裸露于所述侧墙051外侧的鳍片02’，保留位于所述牺牲栅极06和所述侧墙051下方的所述鳍片02’。其中，图8a为图7a所示结构沿AA’方向的剖面示意图，图8b为图7b所示结构沿AA’方向的剖面示意图，图8c为图7c所示结构沿AA’方向的剖面示意图。其中，图7a中以环栅晶体管中包括三层牺牲层022和三层沟道层021为例进行示意。可以理解，环栅晶体管中，牺牲层022和沟道层021的层数可以根据器件的实际需求来确定，在此不作限定。例如，可以根据环栅晶体管的导电性能来设定牺牲层022和沟道层021的层数。
本申请对牺牲层022和沟道层021的厚度不作限定，可以根据实际环栅晶体管要求设定牺牲层022和沟道层021的厚度。
在本申请中，衬底01可以是半导体材料，例如，衬底01的材质可以为硅、锗、硅锗、氮化镓、氮化铝、砷化镓、碳化硅、氧化锌及氧化镓及磷化铟中的一种，且并不限于此处所列举的示例。
在本申请中，牺牲层022可以选与沟道层021具有相近的晶格常数的材料形成，并且在同一刻蚀工艺中，牺牲层022与沟道层021具有较高的刻蚀选择比，这样，在进行后续的选择性刻蚀时可以将牺牲层022刻蚀掉，而保留沟道层021，从而形成悬空的沟道层021。示例性的，沟道层021可以采用Si半导体材料形成，牺牲层022可以采用SiGe半导体材料形成。
在具体实施时，在鳍片02’中最底层为牺牲层022，最顶层为沟道层021。在制备时，可以在衬底01依次外延生长牺牲层022和沟道层021，重复外延生长多次，从而形成依次层叠设置的多层牺牲层022和多层沟道层021。然后采用构图工艺对牺牲层022和沟道层021进行图形化，从而形成鳍片02’。
在具体实施时，牺牲栅极06的延伸方法可以设置为与鳍片02’的延伸方向垂直。
在一种可行的实现方式中，可以通过如下方式形成牺牲栅极06：首先形成覆盖所述鳍片02’的牺牲栅极材料层；然后在所述牺牲栅极材料层上形成掩膜保护层；之后对所述掩膜保护层和所述牺牲栅极材料层进行构图形，形成如图7b和图8b所示的横跨所述鳍片02’的牺牲栅极06，即所述牺牲栅极06包括图形化的牺牲栅极材料层061和掩膜保护层062；然后在所述牺牲栅极06的两侧分别形成侧墙051。
其中，牺牲栅极材料层061可以采用任何适当的材料形成，包括多晶硅、锗、氮化硅、氧化硅或其组合中的一个。在该实施例中，掩膜保护层062用于保护牺牲栅极材料层061以防其在后续工艺步骤中被暴露。示例性的，掩膜保护层061可以采用硬掩膜材料形成，例如氮化硅。
示例性的，侧墙051可以采用低介电常数的材料形成，例如包括但不限于氮化硅、氧化硅、氮氧化硅，碳氧化硅及其组合。在具体实施时，可以采用常规的CVD法或者ALD法等来沉积侧墙051，在此不作限定。
步骤S102、如图7d和图8d所示，在所述侧墙051外侧且裸露的所述鳍片02’处外延生长源极031和漏极032。其中图8d为图7d所示结构沿AA’方向的剖面示意图。
在具体实施时，所述源极031和漏极032的材料相同，所述源极031和所述漏极032的材料可以根据器件的结构设定。
当环栅晶体管为P型晶体管时，源极031和漏极032的材料可以为P型掺杂半导体，例如所述P型掺杂半导体为P型掺杂的锗硅半导体。其中，掺杂的P型离子可以为三价离 子，例如硼、铝、镓等离子。
当环栅晶体管为N型晶体管时，源极031和漏极032的材料可以为N型掺杂半导体，例如所述N型掺杂半导体为N型掺杂的硅半导体。其中，掺杂的N型离子可以为五价离子，例如氮、磷、砷等离子。
在该步骤中，由于源极031和漏极032在外延生长时是沿着牺牲层022和沟道层021的暴露面开始，因此源极031和漏极032的初始生长面是一连续面。相比相关技术中源极031和漏极032的初始生长面为多个间断面，可以生长出晶体质量较好的源极031和漏极032，因此源极031和漏极032中融合界面显著减少，对于P型环栅晶体管，外延生长的源极031和漏极032的应变就不会驰豫掉，进而对沟道形成有效的压应变。对于N型环栅晶体管，外延生长的源极031和漏极032也不会影响晶体管的性能。从而提供一种兼容N型环栅晶体管和P型环栅晶体管的晶体管结构。
步骤S103、去除所述牺牲栅极和所述牺牲层，形成多个悬空的所述沟道层。
示例性的，如图7e和图8e所示，可以先去除所述牺牲栅极06，以裸露出位于所述牺牲栅极06下方的鳍片02’。如图7f和图8f所示，然后去除所述鳍片02’中的牺牲层022，形成多个悬空的所述沟道层021。其中，图8e为图7e所示结构沿AA’方向的剖面示意图，图8f为图7f所示结构沿AA’方向的剖面示意图。
在具体实施时，可以采用干法刻蚀法、湿法刻蚀法或者二者组合去除所述牺牲栅极06，在此不作限定。
在具体实施时，可以采用干法刻蚀法或湿法刻蚀法去除所述鳍片02’中的牺牲层022，在此不作限定。
示例性的，可以采用明显高于沟道层021的刻蚀速率的刻蚀方法选择性的刻蚀掉鳍片02’中的牺牲层022，使保留下来的沟道层021呈悬空设置，这里可以将悬空的沟道层021称为纳米线沟道。
步骤S104、如图8g所示，对所述源极031靠近所述侧墙051一侧以及对所述漏极032靠近所述侧墙051一侧进行氧化形成多个内部隔离部04。
在具体实施时，所述源极、所述漏极的掺杂浓度一般都大于所述沟道层的掺杂浓度。对所述源极靠近所述侧墙一侧以及对所述漏极靠近所述侧墙一侧进行氧化时，使所述源极靠近所述侧墙一侧的氧化速率以及所述漏极靠近所述侧墙一侧的氧化速率大于所述沟道层的氧化速率，从而在所述源极靠近所述侧墙一侧以及对所述漏极靠近所述侧墙一侧分别形成多个内部隔离部。
这是由于源极031和漏极032相比沟道层021为重掺杂，重掺杂的源极031和漏极032比沟道层021更容易氧化，利用源极031和漏极032的氧化率比沟道层021的快，对所述源极031靠近所述侧墙051一侧以及对所述漏极032靠近所述侧墙051一侧进行氧化，可以使源极031和漏极032被氧化的部分体积向悬空区域膨胀，从而可以仅在源极031靠近所述侧墙051一侧的悬空区域以及所述漏极032靠近所述侧墙051一侧的悬空区域处形成内部隔离部04，而沟道层021基本不被氧化。
在具体实施时，当源极031和漏极032的材料为P型掺杂的锗硅半导体，内部隔离部04的材料可以包括氧化锗硅。当源极031和漏极032的材料为N型掺杂的硅半导体，内部隔离部04的材料可以包括氧化硅。
示例性的，以沟道层021为Si半导体材料为例，沟道层021的掺杂浓度较低或者不掺 杂，而源极031和漏极032的掺杂浓度较高。
当源极031和漏极032为P型掺杂的SiGe半导体时，由于SiGe比Si更容易氧化，且重掺杂的SiGe也比不掺杂或轻掺杂的Si更容易氧化，从而利用源极031和漏极032的氧化速率比Si沟道层021的快，从而可以形成SiGeO x的内部隔离部04。当源极031和漏极032为N型掺杂的Si半导体时，由于重掺杂的Si比不掺杂的Si更容易氧化，从而利用源极031和漏极032的氧化速率比Si沟道层021的快，从而可以形成SiO x的内部隔离部04。
示例性的，可以采用低温蒸汽氧化(steam oxidation)方法对源极和漏极进行氧化，其中，低温可以有效避免对于源极和漏极中的杂质原子和锗原子的扩散，从而可以对SiGe实现速率较快的氧化速率，而在该条件下硅沟道层仅仅生成一层很薄的本征氧化物(native oxide)，从而实现选择性氧化的目的。
本申请中，内部隔离部04作为低介电常数的材料，可以物理隔离源极031、漏极032和后续形成在悬空区域中的栅极层，从而减小寄生电容。
为了对源极031与栅极层053，以及漏极032与栅极层053进行有效的隔离，示例性的，内部隔离部04沿沟道方向的厚度可以控制在1nm～5nm之间，例如1nm、2nm、3nm、4nm或5nm。其中，在本申请中，沟道方向与源极031指向漏极032的方向平行。
步骤S105、在所述两个侧墙之间形成栅介电层和栅极层。
在一种可行的实现方式中，如图7g和图8h所示，可以先形成包裹各所述沟道层021的栅介电层052；如图7h和图8i所示，然后在所述两个侧墙051之间形成栅极层053。其中图8h为图7g所示结构沿AA’方向的剖面示意图，图8i为图7h所示结构沿AA’方向的剖面示意图。
在具体实施时，可以采用原子层沉积法或低压化学气相沉积法等在各所述沟道层021的表面形成全包围式的栅介电层052。示例性的，所述栅介电层052可以采用高介电常数的材料形成，诸如Si、钛(Ti)、锆(Zr)、铪(Hf)的氧化物或氮氧化物，例如，所述栅介电层052可以为SiO 2、HfON、HfO 2、ZrO、TiO 2中的任意一种形成的介质层或它们的叠层。
在具体实施时，可以采用原子层沉积法于所述栅介电层052表面形成栅极层053，直至所述栅极层053完全填充所述两个侧墙051之间的空隙。示例性的，所述栅极层053可以为钛、氮化钛、铝、钨、氮化钽或上述材料组成的叠层等形成。
至此，完成环栅晶体管的制备。本申请提供的环栅晶体管，通过对所述源极031靠近所述侧墙051一侧以及对所述漏极032靠近所述侧墙051一侧进行氧化形成内部隔离部04，可以使源极031和漏极032在外延生长时是沿着牺牲层022和沟道层021的暴露面开始，因此源极031和漏极032的初始生长面是一连续面。相比相关技术中源极031和漏极032的初始生长面为多个间断面，可以生长出晶体质量较好的源极031和漏极032，因此源极031和漏极032中融合界面显著减少，对于P型环栅晶体管，外延生长的源极031和漏极032的应变就不会驰豫掉，进而对沟道形成有效的压应变。对于N型环栅晶体管，外延生长的源极031和漏极032也不会影响晶体管的性能。
另外，由于该制备方法与现有CMOS晶体管工艺兼容，尤为适用于5nm节点以下的N型MOS晶体管和P型MOS晶体管的制备。
相应地，本申请实施例还提供了一种CMOS晶体管，如图9所示，该CMOS晶体管包括两个所述环栅晶体管100_n和100_P，且两个所述环栅晶体管100_n和100_P分别 为N型晶体管100_n和P型晶体管100_P。由于该CMOS晶体管解决问题的原理与前述一种环栅晶体管相似，因此该CMOS晶体管的实施可以参见前述环栅晶体管的实施，重复之处不再赘述。
示例性的，在本申请中，两个所述环栅晶体管可以共用栅极结构。
为方便理解本申请实施例提供的CMOS晶体管，下面结合附图详细说明其制备方法。如图10所示，在本申请实施例中，该制备方法包括以下步骤：
步骤S201、如图11a所示，在衬底01上形成沿第一方向X排列的两个鳍片02’，各所述鳍片02’包括层叠且交替重复设置的牺牲层022和沟道层021。其中，图11a中，第一方向X与AA’方向垂直。
步骤S202、如图11b所示，形成横跨所述两个鳍片02’的牺牲栅极06和两个侧墙051，且所述两个侧墙051分别位于所述牺牲栅极06的两侧，所述牺牲栅极06和所述侧墙051均沿所述第一方向X延伸。
步骤S203、如图11c所示，去除所述两个鳍片02’裸露于所述侧墙051外侧的部分，保留所述两个鳍片02’位于所述牺牲栅极06和所述侧墙051下方的部分。
步骤S204、如图11d所示，在所述侧墙051外侧且裸露的所述两个鳍片02’处外延生长源极031和漏极032。
其中，一个鳍片02’两侧的源极031和漏极032的材料为P型掺杂半导体，另一个鳍片02’两侧的源极031和漏极032的材料为N型掺杂半导体。
步骤S205、如图11e所示，去除所述牺牲栅极06，以裸露出位于所述牺牲栅极06下方的两个鳍片02’。
步骤S206、如图11f所示，去除各所述鳍片02’中的牺牲层022，形成多个悬空的所述沟道层021。
步骤S207、如图8g所示，对所述源极031靠近所述侧墙051一侧以及对所述漏极032靠近所述侧墙051一侧进行氧化形成内部隔离部04。
步骤S208、如图11g所示，形成包裹各所述沟道层021的栅介电层052。
步骤S209、如图11h所示，在所述两个侧墙051之间形成栅极层053。
至此，完成CMOS晶体管的制备。在具体实施时，步骤S201～S209的实施可以参见步骤S101～S105，在此不作赘述。
相应地，本申请实施例还提供了一种电子设备，包括电路板，设置在所述电路板上的环栅晶体管，和/或设置在所述电路板上的CMOS晶体管。由于该电子设备解决问题的原理与前述一种环栅晶体管相似，因此该电子设备的实施可以参见前述环栅晶体管的实施，重复之处不再赘述。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (14)

  1. 一种环栅晶体管，其特征在于，包括：
    衬底；
    位于所述衬底上的鳍形结构，所述鳍形结构包括沿垂直于所述衬底方向间隔堆叠的多个沟道层；
    分别位于所述鳍形结构两侧的源极和漏极；
    位于所述多个沟道层的每一所述沟道层面向所述衬底一侧的两个内部隔离部，且任意所述两个内部隔离部均是通过对所述源极靠近所述鳍形结构一侧以及对所述漏极靠近所述鳍形结构一侧进行氧化形成；
    位于所述源极和所述漏极之间且覆盖所述鳍形结构的栅极结构。
  2. 如权利要求1所述的环栅晶体管，其特征在于，所述源极和所述漏极的材料为P型掺杂半导体。
  3. 如权利要求2所述的环栅晶体管，其特征在于，所述P型掺杂半导体为P型掺杂的锗硅半导体。
  4. 如权利要求3所述的环栅晶体管，其特征在于，所述内部隔离部的材料包括氧化锗硅。
  5. 如权利要求1所述的环栅晶体管，其特征在于，所述源极和所述漏极的材料为N型掺杂半导体。
  6. 如权利要求5所述的环栅晶体管，其特征在于，所述N型掺杂半导体为N型掺杂的硅半导体。
  7. 如权利要求6所述的环栅晶体管，其特征在于，所述内部隔离部的材料包括氧化硅。
  8. 如权利要求1-7任一项所述的环栅晶体管，其特征在于，所述内部隔离部沿沟道方向的厚度为1nm～5nm。
  9. 如权利要求1-8任一项所述的环栅晶体管，其特征在于，所述栅极结构包括：相对设置的两个侧墙、包裹各所述沟道层的栅介电层、以及填充于所述两个侧墙之间的间隙的栅极层。
  10. 一种CMOS晶体管，其特征在于，包括两个如权利要求1-9任一项所述的环栅晶体管，其中两个所述环栅晶体管分别为N型晶体管和P型晶体管。
  11. 一种电子设备，其特征在于，包括电路板，设置在所述电路板上的如权利要求1-9 任一项所述的环栅晶体管，和/或设置在所述电路板上的如权利要求10所述的CMOS晶体管。
  12. 一种环栅晶体管的制备方法，其特征在于，包括：
    在衬底上形成鳍片以及横跨所述鳍片的牺牲栅极和两个侧墙；所述鳍片包括层叠且交替重复设置的牺牲层和沟道层，所述两个侧墙分别位于所述牺牲栅极的两侧；
    在所述侧墙外侧且裸露的所述鳍片处外延生长源极和漏极；
    去除所述牺牲栅极和所述牺牲层，形成多个悬空的所述沟道层；
    对所述源极靠近所述侧墙一侧以及对所述漏极靠近所述侧墙一侧进行氧化形成多个内部隔离部；
    在所述两个侧墙之间形成栅介电层和栅极层。
  13. 如权利要求12所述的制备方法，其特征在于，所述源极、所述漏极的掺杂浓度大于所述沟道层的掺杂浓度；
    所述对所述源极靠近所述侧墙一侧以及对所述漏极靠近所述侧墙一侧进行氧化形成多个内部隔离部，包括：
    对所述源极靠近所述侧墙一侧以及对所述漏极靠近所述侧墙一侧进行氧化，使所述源极靠近所述侧墙一侧的氧化速率以及所述漏极靠近所述侧墙一侧的氧化速率大于所述沟道层的氧化速率；
    在所述源极靠近所述侧墙一侧以及对所述漏极靠近所述侧墙一侧分别形成多个内部隔离部。
  14. 如权利要求12或13所述的制备方法，其特征在于，所述形成横跨所述鳍片的牺牲栅极和两个侧墙，包括：
    形成覆盖所述鳍片的牺牲栅极材料层；
    在所述牺牲栅极材料层上形成掩膜保护层；
    对所述掩膜保护层和所述牺牲栅极材料层进行构图，形成横跨所述鳍片的牺牲栅极；
    在所述牺牲栅极的两侧分别形成侧墙。
PCT/CN2021/120782 2021-09-26 2021-09-26 环栅晶体管、其制备方法、cmos晶体管及电子设备 WO2023044870A1 (zh)

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