TWI731468B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI731468B
TWI731468B TW108140802A TW108140802A TWI731468B TW I731468 B TWI731468 B TW I731468B TW 108140802 A TW108140802 A TW 108140802A TW 108140802 A TW108140802 A TW 108140802A TW I731468 B TWI731468 B TW I731468B
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material stack
epitaxial material
epitaxial
gate
nanowires
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TW108140802A
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TW202029288A (zh
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廖翊博
楊凱傑
蔡慶威
程冠倫
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台灣積體電路製造股份有限公司
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Abstract

本揭露實施例提供一種半導體裝置之製造方法，包括：在基板中形成第一凹槽及第二凹槽；在第一凹槽中生長第一磊晶材料堆疊，第一磊晶材料堆疊包括第一半導體材料及第二半導體材料所組成的第一交替層，第一磊晶材料堆疊的第一交替層是未摻雜的；在第二凹槽中生長第二磊晶材料堆疊，第二磊晶材料堆疊包括第一半導體材料及第二半導體材料所組成的第二交替層，第二磊晶材料堆疊之第一子集是未摻雜的，而第二磊晶材料堆疊之第二子集則是經摻雜的；圖案化第一磊晶材料堆疊及第二磊晶材料堆疊，以分別形成複數第一奈米線及複數第二奈米線；以及形成環繞第一奈米線的第一閘極結構以及環繞第二奈米線的第二閘極結構。

Description

半導體裝置及其製造方法
本揭露係有關於一種半導體裝置，特別係有關於一種閘極全環(gate-all-around,GAA)電晶體的半導體裝置。
半導體裝置被用於各項電子應用，例如個人電腦、手機、數位相機、以及其他電子設備。電子裝置的製造通常是藉由在半導體基板上相繼地沉積絕緣或介電層、導電層、以及半導體層的材料，並以微影技術圖案化各種材料層以在其上形成電路組件及元件來完成。
藉由持續地降低最小特徵尺寸(minimum feature size)，半導體工業不停地增進各種電子組件(例如：電晶體、二極體、電阻器、電容器等)的整合密度(integration density)，這允許更多的組件被整合於給定的區域中。然而，隨著最小特徵尺寸的減少，額外需要處理的問題也隨之出現。
本揭露實施例提供一種半導體裝置之製造方法，包括：在基板中形成第一凹槽及第二凹槽；在第一凹槽中生長第一磊晶材料堆疊，第一磊晶材 料堆疊包括第一半導體材料及第二半導體材料所組成的交替層，第一磊晶材料堆疊的交替層是未摻雜的；在第二凹槽中生長第二磊晶材料堆疊，第二磊晶材料堆疊包括第一半導體材料及第二半導體材料所組成的交替層，第二磊晶材料堆疊之第一子集是未摻雜的，而第二磊晶材料堆疊之第二子集則是經摻雜的；圖案化第一磊晶材料堆疊及第二磊晶材料堆疊，以分別形成複數第一奈米線及複數第二奈米線；以及形成環繞第一奈米線的第一閘極結構以及環繞第二奈米線的第二閘極結構。
本揭露實施例提供一種半導體裝置之製造方法，包括：在基板中生長第一磊晶材料堆疊，第一磊晶材料堆疊具有第一平均雜質濃度；在基板中生長第二磊晶材料堆疊，第二磊晶材料堆疊具有第二平均雜質濃度；在基板中生長第三磊晶材料堆疊，第三磊晶材料堆疊具有第三平均雜質濃度，第一平均雜質濃度、第二平均雜質濃度及第三平均雜質濃度並不相同；平坦化基板，使得第一磊晶材料堆疊之頂部表面、第二磊晶材料堆疊之頂部表面、以及第三磊晶材料堆疊之頂部表面呈水平；圖案化第一磊晶材料堆疊、第二磊晶材料堆疊、以及第三磊晶材料堆疊，以分別形成複數第一奈米線、複數第二奈米線、以及複數第三奈米線；以及形成圍繞第一奈米線的第一閘極結構、圍繞第二奈米線的第二閘極結構、以及圍繞第三奈米線的第三閘極結構。
本揭露實施例提供一種半導體裝置，包括：第一電晶體，包括複數第一奈米線及環繞第一奈米線的第一閘極結構，第一奈米線具有第一平均雜質濃度，第一閘極結構包括第一組功函數調諧層；第二電晶體，包括複數第二奈米線及環繞第二奈米線的第二閘極結構，第二奈米線具有第二平均雜質濃度，第二平均雜質濃度不同於第一平均雜質濃度，第二閘極結構包括第一組功 函數調諧層；第三電晶體，包括複數第三奈米線及環繞第三奈米線的第三閘極結構，第三奈米線具有第一平均雜質濃度，第三閘極結構包括第二組功函數調諧層；以及第四電晶體，包括複數第四奈米線及環繞第四奈米線的第四閘極結構，第四奈米線具有第二平均雜質濃度，第四閘極結構包括第二組功函數調諧層，第二組功函數調諧層不同於第一組功函數調諧層。
50:基板
50A:區域
50B:區域
50C:區域
52:凹槽
54:遮罩層
56:磊晶材料堆疊
58A:第一半導體層
58B:第二半導體層
60:第一磊晶生長製程
62:凹槽
64:遮罩層
66:磊晶材料堆疊
66A:第一子集
66B:第二子集
70A:第一半導體層
70B:第二半導體層
72:第二磊晶生長製程
74:凹槽
78:磊晶材料堆疊
78A:第一子集
78B:第二子集
90:鰭片
92:GAA結構
94:遮罩
94A:第一遮罩層
94B:第二遮罩層
96:STI區域
96A:填充材料
96B:襯墊
100:虛擬介電質
102:虛擬閘極
104:遮罩
106:閘極間隔層
108:閘極間隔物
110:源極/汲極凹槽
112:磊晶源極/汲極區域
114:第一層間介電質
116:接觸蝕刻停止層
118:凹槽
A/B-A/B:截面
120:閘極介電層
122:閘極電極
124A:第一組功函數調諧層
124B:第二組功函數調諧層
126:第二層間介電質
128:閘極接點
130:源極/汲極接點
本揭露之態樣自後續實施方式及附圖可更佳理解。須強調的是，依據產業之標準作法，各種特徵並未按比例繪製。事實上，各種特徵之尺寸可能任意增加或減少以清楚論述。
第1圖至第20圖係根據一些實施例所示，製造閘極全環場效電晶體之中間階段的各種圖式。
第21A圖至第21B圖係根據一些實施例所示，製造閘極全環場效電晶體之中間階段的各種圖式。
第22圖係根據一些實施例所示，製造閘極全環場效電晶體之中間階段的各種圖式。
第23A圖至第23B圖係根據一些實施例所示，製造閘極全環場效電晶體之中間階段的各種圖式。
第24圖係根據一些實施例所示，製造閘極全環場效電晶體之中間階段的各種圖式。
第25A圖至第25C圖係根據一些實施例所示，製造閘極全環場效電晶體之中間階段的各種圖式。
以下之揭露提供許多不同實施例或範例，用以實施本揭露之不同特徵。本揭露之各部件及排列方式，其特定範例敘述於下以簡化說明。理所當然的，這些範例並非用以限制本揭露。舉例來說，若敘述中有著第一特徵成形於第二特徵之上或上方，其可能包含第一特徵與第二特徵以直接接觸成形之實施例，亦可能包含有附加特徵形成於第一特徵與第二特徵之間，而使第一特徵與第二特徵間並非直接接觸之實施例。此外，本揭露可在多種範例中重複參考數字及/或字母。該重複之目的係為簡化及清晰易懂，且本身並不規定所討論之多種實施例及/或配置間之關係。
進一步來說，本揭露可能會使用空間相對術語，例如「在...下方」、「下方」、「低於」、「在...上方」、「高於」及類似詞彙，以便於敘述圖式中一個元件或特徵與其他元件或特徵間之關係。除了圖式所描繪之方位外，空間相對術語亦欲涵蓋使用中或操作中之裝置其不同方位。設備可能會被轉向不同方位(旋轉90度或其他方位)，而此處所使用之空間相對術語則可相應地進行解讀。
根據一些實施例，在基板中形成複數磊晶材料堆疊(epitaxial material stack)。在生長期間，複數磊晶材料堆疊被摻雜，且具有不同的平均雜質濃度(impurity concentration)。磊晶材料堆疊接著被圖案化，以形成用於閘極全環(gate-all-around,GAA)場效電晶體(field-effect transistor,FET)的奈米線。每個GAA FET的奈米線的平均雜質濃度決定GAA FET的臨界電壓(threshold voltage)。因此，具有複數臨界電壓的裝置可被形成於同一個基板上。
第1圖至第12圖係根據一些實施例所示，製造閘極全環場效電晶 體(GAA FET)之中間階段的截面圖。具有不同臨界電壓的GAA FET被形成於相同裝置的不同區域中。FET的臨界電壓係指創建FET之源極端與汲極端之間的導電路徑所需的最小閘極-源極電壓。
在第1圖中，基板50被提供。基板50可為半導體基板，例如體半導體(bulk semiconductor)、絕緣層上半導體(semiconductor-on-insulator,SOI)基板等，且可為經摻雜的(doped，例如：以p型或n型摻雜物摻雜)或未摻雜的(undoped)。基板50可為晶圓，例如矽晶圓。一般而言，SOI基板是形成於絕緣層上的半導體材料層。絕緣層，舉例來說，可為埋入式氧化物(buried oxide,BOX)層、矽氧化物層等。絕緣層被提供於基板上，基板通常為矽基板或玻璃基板。亦可使用其他基板，例如多層基板或梯度(gradient)基板。在一些實施例中，基板50之半導體材料包括矽；鍺；化合物半導體，包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦；合金半導體，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、及/或GaInAsP；或其組合。
基板50具有區域50A、區域50B及區域50C。區域50A、區域50B及區域50C可被用於形成諸如NMOS電晶體之n型裝置，例如n型GAA FET，或是可被用於形成諸如PMOS電晶體之p型裝置，例如p型GAA FET。區域50A、區域50B及區域50C彼此間可被物理性地隔離，且任何數量之裝置特徵(例如：其他主動裝置、摻雜區域、隔離結構等)可被設置於區域50A、區域50B與區域50C之間。如將於下文進一步討論的，磊晶材料堆疊將被形成於區域50A、區域50B及區域50C中。磊晶材料堆疊將被圖案化以在區域50A、區域50B及區域50C中形成GAA FET。儘管每個區域繪有一個磊晶材料堆疊，但應理解的是，區域50A、區域50B及區域50C可包括複數磊晶材料堆疊。
形成在區域50A、區域50B及區域50C中的GAA FET具有不同的臨界電壓。特別地，具有第一臨界電壓V1的GAA FET被形成於區域50A中，具有較大之第二臨界電壓V2的GAA FET被形成於區域50B中，而具有又更大的第三臨界電壓V3的GAA FET被形成於區域50C中。此外，可以在區域50A、區域50B及區域50C中形成n型GAA FET或p型GAA FET。在它們的閘極電極中使用不同的功函數(work function)材料來形成n型GAA FET及p型GAA FET。如此一來，具有六種可能之臨界電壓的GAA FET(例如：三種為n型GAA FET，另外三種為p型GAA FET)被形成於基板50上。
此外，適當的井(well，未圖示)可被形成於基板50中。在一些實施例中，p型井被形成於形成有n型GAA FET的區域中(例如：NMOS區域)，而n型井被形成於形成有p型GAA FET的區域中(例如：PMOS區域)。不同的佈植(implant)操作可被用於形成n型井及p型井。
在具有不同之井類型的實施例中，可使用光阻(photoresist)或其他遮罩(未圖示)來達成NMOS區域及PMOS區域之不同的佈植操作。舉例來說，光阻可被形成於基板50上，並被圖案化以曝露基板50的PMOS區域。可使用自旋塗佈(spin-on)技術以形成光阻，並可使用可接受之微影(photolithography)技術以圖案化光阻。一旦將光阻圖案化，就在PMOS區域中執行n型雜質佈植，且光阻可充作遮罩以大體上防止n型雜質被佈植到NMOS區域中。n型雜質可為佈植到該區域中的磷、砷、銻(antimony)等，其濃度等於或小於1018cm-3，例如在約1017cm-3與約1018cm-3之間。在佈植後，光阻可被移除，例如藉由可接受之灰化(ashing)製程移除。
在PMOS區域的佈植後，光阻被形成於基板50上，並被圖案化以 曝露基板50的NMOS區域。可使用自旋塗佈技術以形成光阻，並可使用可接受之微影技術以圖案化光阻。一旦將光阻圖案化，就在NMOS區域中執行p型雜質佈植，且光阻可充作遮罩以大體上防止p型雜質被佈植到PMOS區域中。p型雜質可為佈植到該區域中的硼、BF2、銦等，其濃度等於或小於1018cm-3，例如在約1017cm-3與約1018cm-3之間。在佈植後，光阻可被移除，例如藉由可接受之灰化製程來移除。
在基板50之NMOS及PMOS區域的佈植之後，可執行退火(anneal)以活化(activate)所佈植的p型及/或n型雜質。在一些實施例中，基板50被磊晶生長並在生長期間被原位(in situ)摻雜，如此一來便能夠取消佈植操作，然而原位摻雜及佈植摻雜可一同使用。
在第2圖中，凹槽(recess)52被形成於基板50的區域50A中。可藉由可接受之微影及蝕刻技術形成凹槽52。舉例來說，可在基板50上形成遮罩層54。遮罩層54可由諸如氮化矽、氧化矽、碳氮化矽(silicon carbonitride)、碳氧化矽(silicon oxycarbonitride)、碳氧化矽(silicon oxycarbide)等非金屬材料所形成，且可藉由諸如化學氣相沉積(CVD)等之沉積製程來形成。遮罩層54亦可由諸如氮化鈦、鈦、氮化鉭，鉭等之金屬材料形成，並可藉由物理氣相沉積(physical vapor deposition,PVD)、射頻PVD(Radio Frequency PVD,RFPVD)、原子層沉積(Atomic Layer Deposition,ALD)等來形成。在形成後，遮罩層54可被圖案化以具有與區域50A中之凹槽52對應的開口。圖案化可藉由下列操作完成：在遮罩層54上形成光阻(未圖示)、曝光(expose)並顯影(develop)光阻以具有凹槽52的圖案、以及將光阻圖案轉移到遮罩層54。接著，圖案化之遮罩層54可被用作蝕刻遮罩，以蝕刻基底50之區域50A中的凹槽52。蝕刻可為任何可接受之蝕刻製程，例如反應式離 子蝕刻(reactive ion etch,RIE)、中子束蝕刻(neutral beam etch,NBE)等、或其組合。蝕刻可為非等向性的(anisotropic)。
在第3圖中，磊晶材料堆疊56被形成於凹槽52中。磊晶材料堆疊56包括交替的第一半導體層58A及第二半導體層58B。第一半導體層58A由第一半導體材料所形成，而第二半導體層58B由不同的第二半導體材料所形成。第一半導體材料為適於形成p型FET之通道區域的材料，例如矽鍺(SixGe1-x，其中x可處於0到1的範圍內)。第二半導體材料為適於形成n型FET之通道區域的材料，例如矽。磊晶材料堆疊56可包括任何數量的薄層。在形成於基板50上之GAA FET有六個可能的臨界電壓的實施例中，可形成總共八個的薄層(例如：每種半導體材料各四層)。
磊晶材料堆疊56將被圖案化以在區域50A中形成GAA FET的通道區域。特別地，磊晶材料堆疊56將被圖案化以形成水平奈米線，所獲得之GAA FET的通道區域包括複數水平奈米線。由磊晶材料堆疊56(例如：在基板50之區域50A中)所形成的GAA FET具有第一臨界電壓V1。第一臨界電壓V1為低。在一些實施例中，對於p型裝置，第一臨界電壓V1處於約-0.13V至約-0.07V的範圍中，而對於n型裝置，第一臨界電壓V1處於約0.13V至約0.07V的範圍中。
可藉由第一磊晶生長製程60來形成磊晶材料堆疊56，第一磊晶生長製程60可在生長腔體中執行。在第一磊晶生長製程60期間，生長腔體被循環性地曝露於第一組前驅物(precursor)以選擇性地在凹槽52中生長第一半導體層58A，並接著曝露於第二組前驅物以選擇性地在凹槽52中生長第二半導體層58B。第一組前驅物包括用於第一半導體材料(例如：矽鍺)的前驅物，而第二組前驅物包括用於第二半導體材料(例如：矽)的前驅物。磊晶材料堆疊56為未摻雜 的。如此一來，用於第一磊晶生長製程60的前驅物並未包含用於雜質的前驅物。在一些實施例中，第一組前驅物包括矽前驅物(例如：矽烷(silane))以及鍺前驅物(例如：鍺烷(germane))，而第二組前驅物包括矽前驅物，但刪除了鍺前驅物。第一磊晶生長製程60可因此包括連續地使矽前驅物流向生長腔體，並接著循環地：(1)當生長第一半導體層58A時使鍺前驅物流向生長腔體；(2)當生長第二半導體層58B時使鍺前驅物不會流向生長腔體。循環曝露可被重複，直到形成所欲獲得的薄層數量。
在第4圖中，執行平坦化製程以使基板50之頂部表面與磊晶材料堆疊56之頂部表面呈水平(level)。平坦化製程亦移除遮罩層54以及磊晶材料堆疊56自凹槽52延伸出來的部分。平坦化製程可為化學機械研磨(chemical mechanical polish,CMP)、回蝕刻(etch back)製程、其組合等。在平坦化製程後，基板50與磊晶材料堆疊56之頂部表面是呈水平的。
在第5圖中，凹槽62被形成於基板50之區域50B中。可用與形成凹槽52之方法相似的方法來形成凹槽62，例如在可接受之蝕刻製程期間使用圖案化之遮罩層64作為蝕刻遮罩。或者，可藉由不同方法形成凹槽62。
在第6圖及第7圖中，磊晶材料堆疊66被形成於凹槽62中。磊晶材料堆疊66包括交替之半導體層。薄層之第一子集66A為未摻雜之半導體層。薄層之第二子集66B為經摻雜之半導體層。磊晶材料堆疊66具有與磊晶材料堆疊56相同數量之薄層。
磊晶材料堆疊66亦將被圖案化以在區域50B中形成GAA FET的通道區域。形成自磊晶材料堆疊66的GAA FET(例如：在基板50之區域50B中)具有第二臨界電壓V2。GAA FET之臨界電壓受GAA FET之通道區域中的雜質濃度所 影響，其中較高的雜質濃度會導致較高的臨界電壓。FET之通道區域中的雜質濃度是指形成FET之通道區域的奈米線的平均雜質濃度。因為磊晶材料堆疊66包括經摻雜的薄層，因此第二臨界電壓V2大於第一臨界電壓V1。在一些實施例中，對於p型裝置，第二臨界電壓V2處於約-0.23V至約-0.17V的範圍中，而對於n型裝置，第二臨界電壓V2處於約0.23V至約0.17V的範圍中。
薄層的第一子集66A(見第6圖)包括第一半導體層58A與第二半導體層58B的交替層。藉由執行第一磊晶生長製程60的一些循環以形成薄層的第一子集66A。在希望GAA FET有六個可能的臨界電壓的實施例中，磊晶材料堆疊66的第一子集66A包括堆疊之總層數的一半。
薄層的第二子集66B(見第7圖)包括交替之第一半導體層70A與第二半導體層70B。第一半導體層70A由與第一半導體層58A相同之基礎半導體材料(例如：矽鍺)所形成，並額外以V族元素(例如：磷、砷等)摻雜。第二半導體層70B由與第二半導體層58B相同之基礎半導體材料(例如：矽)所形成，並額外以III族元素(例如：硼)摻雜。薄層的第二子集66B可藉由第二磊晶生長製程72來形成，第二磊晶生長製程72可在與第一磊晶生長製程60相同的生長腔體中執行。在第二磊晶生長製程72期間，生長腔體被曝露於與第一磊晶生長製程60相同之前驅物組合中，並額外地曝露於合適之雜質前驅物中。舉例來說，在第二磊晶生長製程72期間，第一組前驅物可進一步包括V族雜質的前驅物，而第二組前驅物可進一步包括III族雜質的前驅物。第二磊晶生長製程72可因此包括連續地使矽前驅物流向生長腔體，並接著循環地：(1)當生長第一半導體層70A時使鍺以及V族前驅物流向生長腔體；(2)當生長第二半導體層70B時使鍺前驅物不會流向生長腔體，並使III族前驅物流向生長腔體。循環曝露可被重複，直到形成所 欲獲得的薄層數量。接續上述範例，磊晶材料堆疊66的第二子集66B可包括堆疊之總層數的一半。
第一半導體層70A及第二半導體層70B可被摻雜至任何的雜質濃度。如上所述，更大的雜質濃度會增加區域50B中所獲得之GAA FET的臨界電壓。第一半導體層70A與第二半導體層70B可被摻雜至相同濃度，或是可被摻雜為不同濃度。在一些實施例中，第一半導體層70A被以砷進行摻雜，並摻雜至約1017cm-3至約1019cm-3的濃度(例如：約1019cm-3)，而第二半導體層70B被以硼進行摻雜，並摻雜至1017cm-3至約1019cm-3的濃度(例如：約1019cm-3)。
在第8圖中，執行平坦化製程以使基板50之頂部表面與磊晶材料堆疊66之頂部表面呈水平。平坦化製程亦移除遮罩層64以及磊晶材料堆疊66延伸出凹槽62的部分。平坦化製程可為化學機械研磨(CMP)、回蝕刻製程、其組合等。在平坦化製程後，基板50之頂部表面與磊晶材料堆疊56、磊晶材料堆疊66之頂部表面是呈水平的。
在第9圖中，凹槽74被形成於基板50之區域50C中。可用與形成凹槽52之方法相似的方法來形成凹槽74，例如在可接受之蝕刻製程期間使用圖案化之遮罩層76作為蝕刻遮罩。或者，可藉由不同方法形成凹槽74。
在第10圖及第11圖中，磊晶材料堆疊78被形成於凹槽74中。磊晶材料堆疊74包括交替之半導體層。薄層之第一子集78A為未摻雜之半導體層。薄層之第二子集78B為經摻雜之半導體層。磊晶材料堆疊78具有與磊晶材料堆疊56及磊晶材料堆疊66相同數量之薄層。
磊晶材料堆疊78亦將被圖案化以在區域50C中形成GAA FET的通道區域。形成自磊晶材料堆疊78的GAA FET(例如：在基板50之區域50C中)具有 第三臨界電壓V3。如上所述，GAA FET之臨界電壓受GAA FET之通道區域中的雜質濃度所影響，且通道區域中的雜質濃度是指形成通道區域之奈米線的平均雜質濃度。在所示的實施例中，磊晶材料堆疊66與磊晶材料堆疊78之類似的薄層具有相同的雜質濃度，且磊晶材料堆疊78中經摻雜之半導體層的數量，大於磊晶材料堆疊66中經摻雜之半導體層的數量。在其他實施例中(未圖示)，磊晶材料堆疊66與磊晶材料堆疊78之薄層具有不同的雜質濃度，且磊晶材料堆疊78中經摻雜之半導體層的數量，與磊晶材料堆疊66中經摻雜之半導體層的數量相同。磊晶材料堆疊78中的平均雜質濃度因此大於磊晶材料堆疊66。因為磊晶材料堆疊78包括比磊晶材料堆疊66更多的經摻雜之薄層，因此第三臨界電壓V3大於第二臨界電壓V2以及第一臨界電壓V1。在一些實施例中，對於p型裝置，第三臨界電壓V3處於約-0.33V至約-0.27V的範圍中，而對於n型裝置，第三臨界電壓V3處於約0.33V至約0.27V的範圍中。
薄層的第一子集78A(見第10圖)包括第一半導體層58A與第二半導體層58B的交替層。藉由執行第一磊晶生長製程60的一些循環以形成薄層的第一子集78A。在希望GAA FET有六個可能的臨界電壓的實施例中，磊晶材料堆疊78的第一子集78A包括堆疊之總層數的四分之一。
薄層的第二子集78B(見第11圖)包括第一半導體層70A與第二半導體層70B之交替層。藉由執行第二磊晶生長製程72的一些循環以形成薄層的第二子集78B。在希望GAA FET有六個可能的臨界電壓的實施例中，磊晶材料堆疊78的第二子集78B包括堆疊之總層數的四分之三。
在第12圖中，執行平坦化製程以使基板50之頂部表面與磊晶材料堆疊78之頂部表面呈水平。平坦化製程亦移除遮罩層76以及磊晶材料堆疊78延 伸出凹槽74的部分。平坦化製程可為化學機械研磨(CMP)、回蝕刻製程、其組合等。在平坦化製程後，基板50之頂部表面與磊晶材料堆疊56、磊晶材料堆疊66、以及磊晶材料堆疊78之頂部表面是呈水平的。
第13圖至第20圖及第22圖係根據一些實施例所示，製造GAA FET之進一步之中間階段的透視圖。第21A圖及第21B圖係沿著第20圖中之參考截面A/B-A/B的截面圖。第23A圖及第23B圖係沿著第22圖中之參考截面A/B-A/B的截面圖。基板50之區域50A/50B/50C僅有其中一個被繪示。應理解的是，相似之製程可被執行於基板50之所有的區域50A/50B/50C中。此外，儘管僅繪示單一閘極結構及一對源極/汲極區域，但應當理解，實際上可形成複數閘極結構及許多源極/汲極區域。
在第13圖中，鰭片90及GAA結構92被形成於基板50中。鰭片90為半導體條(strip)，而GAA結構92設置於鰭片90上。在一些實施例中，可藉由分別在基板50以及磊晶材料堆疊56、磊晶材料堆疊66和磊晶材料堆疊78中蝕刻溝槽以形成鰭片90及GAA結構92。
可藉由合適之方法圖案化GAA結構92。舉例來說，可使用一或多種微影製程來圖案化結構，包括雙重圖案化(double-patterning)或多重圖案化(multi-patterning)製程。一般而言，雙重圖案化或多重圖案化製程結合微影及自我對準(self-aligned)製程，這允許創建之圖案所具有之間距，舉例來說，小於另外使用單一、直接之微影製程所能獲得的間距。舉例來說，在一個實施例中，犧牲層被形成於基板上，並使用微影製程將之圖案化。使用自我對準製程沿著圖案化之犧牲層形成間隔物。犧牲層接著被移除，而間隔物被留下，間隔物可隨後被用於圖案化GAA結構92。
在一些實施例中，剩餘的間隔物被用於圖案化遮罩94，遮罩94接著被用於圖案化GAA結構92以及鰭片90。遮罩94可為單層遮罩，或可為多層遮罩，例如包括第一遮罩層94A及第二遮罩層94B的多層遮罩。第一遮罩層94A及第二遮罩層94B皆可形成自介電材料，例如氧化矽、氮化矽、其組合等，且可根據可接受之技術進行沉積或熱生長(thermally grown)。第一遮罩層94A及第二遮罩層94B為具有高蝕刻選擇性(etch selectivity)的不同材料。舉例來說，第一遮罩層94A可為氧化矽，而第二遮罩層94B可為氮化矽。可藉由任何可接受之蝕刻製程以圖案化遮罩94。遮罩94可接著被用作蝕刻遮罩以蝕刻基板50以及磊晶材料堆疊56、磊晶材料堆疊66、及磊晶材料堆疊78。蝕刻可為任何可接受之蝕刻製程，例如反應式離子蝕刻(RIE)、中子束蝕刻(NBE)等、或其組合。蝕刻可為非等向性的。
在第14圖中，淺溝槽隔離(Shallow Trench Isolation,STI)區域96被形成於基板50上以及相鄰之鰭片90之間。作為形成STI區域96之範例，絕緣材料可被形成於基板50上。絕緣材料可為諸如氧化矽之氧化物、氮化物等、或其組合，且絕緣材料可藉由高密度電漿化學氣相沉積(high density plasma chemicalvapor deposition,HDP-CVD)、流動式化學氣相沉積(flowable CVD,FCVD)(例如：在遠程電漿系統中進行基於CVD之材料沉積，並進行後固化以使其轉變為另一種材料，例如氧化物)等、或其組合來形成。可藉由任何可使用之可接受製程形成其他絕緣材料。在所繪實施例中，絕緣材料為藉由FCVD所形成之氧化矽。一旦絕緣材料被形成，便可執行退火(anneal)製程。在一個實施例中，絕緣材料被形成，使得多餘之絕緣材料覆蓋鰭片90及GAA結構92。在一些實施例中，首先沿著基板50及鰭片90的表面形成襯墊(liner)96B，並在襯墊96B上形成諸如上面所 討論之填充材料96A。在一些實施例中，襯墊96B被省略。接著，對絕緣材料施加移除製程，以移除鰭片90及GAA結構92上之多餘的絕緣材料。在一些實施例中，可利用諸如化學機械研磨(CMP)、回蝕刻製程、其組合等之平坦化製程。平坦化製程曝露GAA結構92，使得在完成平坦化製程後，GAA結構92及絕緣材料的頂表面是呈水平的。接下來，絕緣材料被掘入(recess)以形成STI區域96。絕緣材料被掘入使得GAA結構92自相鄰之STI區域96之間突出。此外，STI區域96之頂部表面可具有如圖所示之平坦表面、凸表面、凹表面(例如：凹陷(dishing))、或其組合。可藉由適當之蝕刻將STI區域96之頂部表面形成為平坦的，凸起的、及/或凹面的。可使用可接受之蝕刻製程掘入STI區域96，例如對絕緣材料之材料具有選擇性的蝕刻製程(例如：對絕緣材料之材料的蝕刻速率高於對鰭片90及GAA結構92之材料的蝕刻速率)。舉例來說，以合適之蝕刻製程進行化學氧化移除(chemical oxide removal)，例如可使用運用稀氫氟酸(dilute hydrofluoric,dHF)之酸的蝕刻製程。
在第15圖中，虛擬介電質(dummy dielectrics)100被形成於GAA結構92上，而虛擬閘極102被形成於虛擬介電質100上。作為形成虛擬介電質100及虛擬閘極102的範例，虛擬介電層可被形成於GAA結構92及STI區域96上。虛擬介電層，舉例來說，可為氧化矽、氮化矽、其組合等，且根據合適之技術進行沉積或熱生長。虛擬閘極層可接著被形成於虛擬介電層上。虛擬閘極層可被形成於虛擬介電層上並接著被平坦化，例如以CMP平坦化。虛擬閘極層可為導電材料並選自一個組合，該組合包括非晶矽(amorphous silicon)、多晶矽(polysilicon)、多晶矽鍺(poly-SiGe)、金屬氮化物、金屬矽化物、金屬氧化物、以及金屬。可藉由物理氣相沉積(PVD)、化學氣相沉積(CVD)、濺鍍(sputter)沉積、 或本技術領域中已知並使用之用於沉積導電材料的其他技術，來沉積虛擬閘極層。虛擬閘極層可由其他材料製造，這些材料對隔離區的蝕刻具有高蝕刻選擇性。遮罩104接著被形成於虛擬閘極層上。遮罩104可由氮化矽、氮氧化矽、其組合等所形成，並可使用可接受之微影及蝕刻技術來圖案化。遮罩104的圖案接著藉由可接受之蝕刻技術而被轉移到虛擬閘極層上，以形成虛擬閘極102，並接著藉由可接受之蝕刻技術而被轉移到虛擬介電層上，以形成虛擬介電質100。虛擬閘極102覆蓋GAA結構92之各別的通道區域。遮罩104之圖案可將每個虛擬閘極102與相鄰之虛擬閘極物理性地隔離。虛擬閘極102所具有之長度方向亦可基本垂直於鰭片90之長度方向。
在第16圖中，藉由在GAA結構92、STI區域96、以及虛擬閘極102上順應性地(conformally)沉積絕緣材料，以形成閘極間隔層106。絕緣材料可為氮化矽、碳氮化矽、其組合等。在一些實施例中，閘極間隔層106包括複數子層。舉例來說，可藉由熱氧化或沉積來形成第一子層(有時亦稱為閘極密封間隔層)，並可藉由在第一子層上順應性地沉積來形成第二子層(有時亦稱為主閘極間隔層)。
形成閘極間隔層106後，可執行用於輕度摻雜之源極/汲極(lightly doped source/drain,LDD)區域(未圖示)的佈植。適當類型(例如：p型或n型)之雜質可被佈植，以進入曝露之GAA結構92及/或鰭片90之中。n型雜質可為先前所述之任何n型雜質，而p型雜質可為先前所述之任何p型雜質。輕度摻雜之源極/汲極區域可具有濃度自約1015cm-3至約1016cm-3的雜質。可使用退火以活化所佈植的雜質。
在第17圖中，藉由非等向性地蝕刻閘極間隔層106來形成閘極間 隔物108。非等向性蝕刻可移除閘極間隔層106之水平的部分(例如：STI區域及虛擬閘極102上的部分)，並留下閘極間隔層106之垂直的部分(例如：沿著虛擬閘極102及GAA結構92之側壁的部分)以形成閘極間隔物108。
此外，源極/汲極凹槽110被形成於GAA結構92中。源極/汲極凹槽110可延伸穿過GAA結構92並延伸至鰭片90之中。可藉由可接受之蝕刻技術並使用虛擬閘極102作為蝕刻遮罩來形成源極/汲極凹槽110。
在第18圖中，磊晶源極/汲極區域112被形成於源極/汲極凹槽110中，以對GAA結構92之各別通道區域施加應力，進而增進性能。磊晶源極/汲極區域112被形成於GAA結構92中，使得每個虛擬閘極102被設置於各別之相鄰的一對磊晶源極/汲極區域112之間。在一些實施例中，磊晶源極/汲極區域112可延伸至鰭片90之中，且亦可貫穿穿過鰭片90。在一些實施例中，閘極間隔物108被用於將磊晶源極/汲極區域112與虛擬閘極102以適當的橫向距離彼此分隔，使得磊晶源極/汲極區域112與隨後形成之所得GAA FET的閘極不會短路。
在源極/汲極凹槽110中磊晶生長磊晶源極/汲極區域112。磊晶源極/汲極區域112可包括任何可接受之材料，例如適用於n型或p型GAA FET的材料。舉例來說，當形成n型GAA FET時，磊晶源極/汲極區域112可包括在通道區域中施加拉伸應變(tensile strain)的材料，例如矽、SiC、SiCP、SiP等。同樣地，當形成p型GAA FET時，磊晶源極/汲極區域112可包括在通道區域中施加壓縮應變(compressive strain)的材料，例如SiGe、SiGeB、Ge、GeSn等。磊晶源極/汲極區域112可具有自各別鰭片90之表面抬升的表面，且可具有端面(facet)。
磊晶源極/汲極區域112及/或鰭片90可被以摻雜物摻雜以形成源極/汲極區域，與先前所述之形成輕度摻雜之源極/汲極區域的製程相似，並在隨 後執行退火。源極/汲極區域所具有之雜質濃度可處於約1019cm-3與約1021cm-3之間。用於源極/汲極區域之n型及/或p型雜質可為先前所述之任何雜質。在一些實施例中，磊晶源極/汲極區域112可在生長期間原位摻雜。
作為用於形成磊晶源極/汲極區域112之磊晶製程的結果，磊晶源極/汲極區域112之上部表面具有端面，端面橫向地向外擴張並超出鰭片90的側壁。在所示的實施例中，這些端面使得相同GAA FET之相鄰的磊晶源極/汲極區域112合併，如圖所示。在其他實施例中(未圖示)，在完成磊晶製程後，相鄰之磊晶源極/汲極區域112仍舊保持分離。
在第19圖中，第一層間介電質(inter-layer dielectric,ILD)114被沉積於所示之中間結構上。第一層間介電質114可由介電材料形成，並可藉由合適之方法沉積，例如CVD、電漿增強形化學氣相沉積(plasma-enhanced CVD,PECVD)、或是FCVD。介電材料可包括磷矽酸鹽玻璃(Phospho-Silicate Glass,PSG)、硼矽酸鹽玻璃(Boro-Silicate Glass,BSG)、摻硼之磷矽酸鹽玻璃(Boron-Doped Phospho-Silicate Glass,BPSG)、未摻雜之矽酸鹽玻璃(undoped Silicate Glass,USG)等。可藉由使用任何可接受之製程形成其他絕緣材料。在一些實施例中，接觸蝕刻停止層(contact etch stop layer,CESL)116被設置於第一層間介電質114與磊晶源極/汲極區域112之間、第一層間介電質114與閘極間隔物108之間、以及第一層間介電質114與STI區域96之間。接觸蝕刻停止層116可包括介電材料，例如氮化矽、氧化矽、氮氧化矽等，具有與所覆蓋的第一層間介電質114之材料不同的蝕刻速率。
此外，可執行諸如CMP之平坦化製程，以使第一層間介電質114及接觸蝕刻停止層116之頂部表面與虛擬閘極102及閘極間隔物108之頂部表面 呈水平。平坦化製程亦可移除虛擬閘極102上的遮罩104，以及移除閘極間隔物108沿著遮罩104之側壁的部分。在平坦化製程後，虛擬閘極102、閘極間隔物108、以及第一層間介電質114之頂部表面是呈水平的。因此，虛擬閘極102之頂部表面經由第一層間介電質114而曝露。
在第20圖中，虛擬閘極102在蝕刻操作中被移除，進而形成凹槽118。虛擬介電質100在凹槽118中的部分亦可被移除。在一些實施例中，在晶粒(die)的第一區域中(例如：核心邏輯區域)，虛擬介電質100自凹槽118中被移除，而在晶粒的第二區域中(例如：輸入/輸出區域)，虛擬介電質100則是留在凹槽118中。在一些實施例中，藉由非等向性乾式蝕刻移除虛擬閘極102。舉例來說，蝕刻製程可包括使用反應氣體(reaction gas)的乾式蝕刻製程，以在不蝕刻第一層間介電質114或閘極間隔物108的情況下，選擇性地蝕刻虛擬閘極102。每個凹槽118曝露各別之GAA結構92的通道區域。在移除期間，當虛擬閘極102被蝕刻時，虛擬介電質100可被用作蝕刻停止層。在移除虛擬閘極102後，可接著選擇是否要移除虛擬介電質100。
在移除虛擬閘極102及虛擬介電質100後，移除GAA堆疊92(亦稱為GAA結構92)之適當的部分。當形成p型FET時(見第21A圖)，第二半導體層58B自GAA堆疊92中被移除，留下第一半導體層58A以作為p型FET的通道區域。當形成n型FET時(見第21B圖)，第一半導體層58A自GAA堆疊92中被移除，留下第二半導體層58B以作為n型FET的通道區域。可藉由適當之蝕刻進行移除，例如以非等向性濕式蝕刻對欲移除的材料(例如：當移除第一半導體層58A時為矽鍺，而當移除第二半導體材料層58B時則為矽)進行選擇性的蝕刻。可在與形成凹槽118之製程不同或相同的製程中蝕刻GAA堆疊92。
在第22圖中，閘極介電層120及閘極電極122被形成，以取代閘極。閘極介電層120被順應性地沉積於凹槽118中，例如在鰭片90之頂部表面與側壁上，以及閘極間隔物108之側壁上。閘極介電層120亦可被形成在第一層間介電質114上。應注意的是，閘極介電層120環繞GAA堆疊92之剩餘的水平奈米線。當形成p型FET時(見第23A圖)，閘極介電層120環繞剩餘之第一半導體層58A及第一半導體層70A(例如：p型GAA FET之奈米線)。當形成n型FET時(見第23B圖)，閘極介電層120環繞剩餘之第二半導體層58B及第二半導體層70B(例如：n型GAA FET之奈米線)。根據一些實施例，閘極介電層120包括氧化矽、氮化矽、或其複數層。在一些實施例中，閘極介電層120包括高k值介電材料，且在這些實施例中，閘極介電層120可具有大於約7.0的k值，並可包括鉿(Hf)、鋁(Al)、鋯(Zr)、鑭(La)、鎂(Mg)、鋇(Ba)、鈦(Ti)、鉛(Pb)及其組合的金屬氧化物或矽酸鹽。閘極介電層120之形成方法可包括分子束沉積(Molecular-Beam Deposition,MBD)、ALD、PECVD等。在虛擬介電質100的一些部分保留在凹槽118中的實施例中，閘極介電層120包括虛擬介電質100的材料(例如：SiO2)。
閘極電極122被沉積在閘極介電層120上且圍繞閘極介電層120，並填充凹槽118剩餘的部分。閘極電極122可包括含金屬材料，例如TiN、TiO、TaN、TaC、Co、Ru、Al、W、其組合、或其複數層。舉例來說，儘管僅顯示了單層的閘極電極122，但閘極電極122可包括任何數量之襯墊層、任何數量之功函數調諧層(work function tuning layer，討論於下)、以及填充材料。在填充閘極電極122後，可執行諸如CMP的平坦化製程，以移除閘極介電層120及閘極電極122之材料的多餘部分，這些多餘部分位在第一層間介電質114之頂部表面上。閘極電極122及閘極介電層120之材料的剩餘部分因此形成所得GAA FET的替換閘 極。每個閘極電極122及對應之閘極介電層120可被統稱為「閘極堆疊」。每個閘極堆疊延伸圍繞由圖案化GAA結構92所形成的奈米線。
在一些實施例中，對於n型與p型裝置，功函數調諧層並不相同。當形成p型FET時(見第23A圖)，第一組功函數調諧層124A被形成，圍繞每個閘極介電層120。當形成n型FET時(見第23B圖)，第二組功函數調諧層124B被形成，圍繞每個閘極介電層120。第一組功函數調諧層124A包括不同於第二組功函數調諧層124B的功函數金屬。舉例來說，第一組功函數調諧層124A可包括TiN、TaN、Mo，而第二組功函數調諧層124B可包括WN、Ta、Ti。所選擇之功函數調諧層的材料會調整所得GAA FET的臨界電壓。因為GAA結構92具有三個初始臨界電壓(V1、V2及V3)，且有兩組功函數調諧層材料(n型及p型)可供選擇，因此所得GAA FET可具有六個可能之臨界電壓中的一個。
在第24圖中，第二層間介電質126被沉積於第一層間介電質114上。在一些實施例中，第二層間介電質126是藉由流動式CVD方法形成的流動薄膜(flowable film)。在一些實施例中，第二層間介電質126由介電材料所形成，例如PSG、BSG、BPSG、USG等，且可藉由任何合適之方法沉積，例如CVD及PECVD。在一些實施例中，在形成第二層間介電質126之前，先在閘極堆疊上形成閘極遮罩(未圖示)。
此外，根據一些實施例，形成穿過第二層間介電質126及第一層間介電質114的閘極接點128及源極/汲極接點130。形成穿過第一層間介電質114及第二層間介電質126且用於源極/汲極接點130的開口，並形成穿過第二層間介電質126(且可選擇是否穿過閘極遮罩)且用於閘極接點128的開口。可使用可接受之微影及蝕刻技術以形成開口。在開口中形成襯墊(例如：擴散阻擋層(diffusion barrier layer)、黏著層(adhesion layer)等)以及導電材料。襯墊可包括鈦、氮化鈦、鉭、氮化鉭等。導電材料可為銅、銅合金、銀、金、鎢、鈷、鋁、鎳等。可執行諸如CMP的平坦化製程以自第二層間介電質126之頂部表面移除多餘的材料。剩餘的襯墊及導電材料在開口中形成源極/汲極接點130及閘極接點128。可執行退火製程以在磊晶源極/汲極區域112與源極/汲極接點130之間的界面處形成矽化物。源極/汲極接點130實體地且電性地耦接至磊晶源極/汲極區域112，而閘極接點128實體地且電性地耦接至閘極電極122。源極/汲極接點130與閘極接點128可藉由不同的製程來形成，或者可藉由相同的製程來形成。儘管所示的一些源極/汲極接點130及閘極接點128被形成於相同截面中，但應理解的是，每個源極/汲極接點130及閘極接點128可被形成在不同截面中，這可避免接點的短路。
第25A圖、第25B圖及第25C圖係根據一些實施例，顯示製造GAA FET之中間階段的截面圖。如上所述，通道區域中的雜質濃度係指平均雜質濃度。在第25A圖所示的實施例中，一些磊晶材料堆疊(例如磊晶材料堆疊66)所具有之薄層數量為其他堆疊的一半，但薄層厚度為其他堆疊的兩倍，因此，第25A圖之磊晶材料堆疊66具有與第12圖之磊晶材料堆疊66相同的平均雜質濃度。因此，區域50B之GAA結構可藉由較少的磊晶操作形成，這可降低製造成本。第25B圖及第25C圖顯示所得GAA FET在區域50B中的截面圖。p型(見第25B圖)及n型(見第25C圖)裝置在它們的通道區域中皆具有較大的奈米線，這可容納較高的通道電流。
實施例可達成許多優點。以經摻雜及未摻雜區域形成複數磊晶材料堆疊，可允許具有不同臨界電壓之GAA FET形成於相同基板上。對n型及p型裝置使用不同功函數材料，亦可增加可能之不同的臨界電壓的數量。
在一個實施例中，一種半導體裝置之製造方法包括：在基板中形成第一凹槽及第二凹槽；在第一凹槽中生長第一磊晶材料堆疊，第一磊晶材料堆疊包括第一半導體材料及第二半導體材料所組成的交替層，第一磊晶材料堆疊的交替層是未摻雜的；在第二凹槽中生長第二磊晶材料堆疊，第二磊晶材料堆疊包括第一半導體材料及第二半導體材料所組成的交替層，第二磊晶材料堆疊之第一子集是未摻雜的，而第二磊晶材料堆疊之第二子集則是經摻雜的；圖案化第一磊晶材料堆疊及第二磊晶材料堆疊，以分別形成複數第一奈米線及複數第二奈米線；以及形成環繞第一奈米線的第一閘極結構以及環繞第二奈米線的第二閘極結構。
在半導體裝置之製造方法的一些實施例中，第一半導體材料為矽鍺，而第二半導體材料為矽，其中第二磊晶材料堆疊之第二子集中的複數矽鍺層被以五族元素摻雜，而第二磊晶材料堆疊之第二子集中的複數矽層被以三族元素摻雜。在半導體裝置之製造方法的一些實施例中，第一閘極結構的形成包括環繞第一奈米線沉積第一金屬，而第二閘極結構的形成包括環繞第二奈米線沉積第二金屬，其中上述第二金屬不同於上述第一金屬。在一些實施例中，半導體裝置之製造方法更包括：在基板中形成第三凹槽；在第三凹槽中生長第三磊晶材料堆疊，第三材料堆疊包括第一半導體材料及第二半導體材料所組成的第三交替層，第三磊晶材料堆疊之第一子集是未摻雜的，而第三磊晶材料堆疊之第二子集則是經摻雜的，其中第三磊晶材料堆疊之第二子集所包含的薄層多於第二磊晶材料堆疊之第二子集；圖案化第三磊晶材料堆疊以形成複數第三奈米線；以及形成環繞第三奈米線的第三閘極結構。在半導體裝置之製造方法的一些實施例中，第一磊晶材料堆疊的生長包括：以第一磊晶生長製程生長第一 磊晶材料堆疊。在半導體裝置之製造方法的一些實施例中，第二磊晶材料堆疊的生長包括：以第一磊晶生長製程生長第二磊晶材料堆疊的第一子集；以及以第二磊晶生長製程生長第二磊晶材料堆疊的第二子集，第二磊晶生長製程不同於第一磊晶生長製程。在半導體裝置之製造方法的一些實施例中，第三磊晶材料堆疊的生長包括：以第一磊晶生長製程生長第三磊晶材料堆疊的第一子集；以及以第二磊晶生長製程生長第三磊晶材料堆疊的第二子集。在半導體裝置之製造方法的一些實施例中，第一磊晶材料堆疊的圖案化包括：在第一磊晶材料堆疊中蝕刻複數溝槽以形成第一閘極全環(GAA)結構，第一閘極全環結構包括第一半導體材料及第二半導體材料所組成的交替層；在第一閘極全環結構上形成複數第一閘極間隔物；以及執行蝕刻操作以蝕刻第一閘極全環結構在第一閘極間隔物之間的部分，蝕刻操作選擇性地移除第一半導體材料的薄層，留下形成第一奈米線之第二半導體材料的薄層。在一些實施例中，半導體裝置之製造方法更包括：平坦化基板使得第二磊晶材料堆疊之頂部表面、第一磊晶材料堆疊之頂部表面、以及基板之頂部表面呈水平。
在一個實施例中，一種半導體裝置之製造方法包括：在基板中生長第一磊晶材料堆疊，第一磊晶材料堆疊具有第一平均雜質濃度；在基板中生長第二磊晶材料堆疊，第二磊晶材料堆疊具有第二平均雜質濃度；在基板中生長第三磊晶材料堆疊，第三磊晶材料堆疊具有第三平均雜質濃度，第一平均雜質濃度、第二平均雜質濃度及第三平均雜質濃度並不相同；平坦化基板，使得第一磊晶材料堆疊之頂部表面、第二磊晶材料堆疊之頂部表面、以及第三磊晶材料堆疊之頂部表面呈水平；圖案化第一磊晶材料堆疊、第二磊晶材料堆疊、以及第三磊晶材料堆疊，以分別形成複數第一奈米線、複數第二奈米線、以及 複數第三奈米線；以及形成圍繞第一奈米線的第一閘極結構、圍繞第二奈米線的第二閘極結構、以及圍繞第三奈米線的第三閘極結構。
在半導體裝置之製造方法的一些實施例中，第一磊晶材料堆疊、第二磊晶材料堆疊、以及第三磊晶材料堆疊具有相同數量的薄層。在半導體裝置之製造方法的一些實施例中，第一磊晶材料堆疊以及第三磊晶材料堆疊具有第一數量的薄層，而第二磊晶材料堆疊具有第二數量的薄層，其中第二數量不同於第一數量。
在一個實施例中，一種半導體裝置包括：第一電晶體，包括複數第一奈米線及環繞第一奈米線的第一閘極結構，第一奈米線具有第一平均雜質濃度，第一閘極結構包括第一組功函數調諧層；第二電晶體，包括複數第二奈米線及環繞第二奈米線的第二閘極結構，第二奈米線具有第二平均雜質濃度，第二平均雜質濃度不同於第一平均雜質濃度，第二閘極結構包括第一組功函數調諧層；第三電晶體，包括複數第三奈米線及環繞第三奈米線的第三閘極結構，第三奈米線具有第一平均雜質濃度，第三閘極結構包括第二組功函數調諧層；以及第四電晶體，包括複數第四奈米線及環繞第四奈米線的第四閘極結構，第四奈米線具有第二平均雜質濃度，第四閘極結構包括第二組功函數調諧層，第二組功函數調諧層不同於第一組功函數調諧層。
在半導體裝置的一些實施例中，第一電晶體、第二電晶體、第三電晶體、以及第四電晶體中的每一個，皆具有相同數量的奈米線。在半導體裝置的一些實施例中，第一電晶體及第三電晶體具有第一數量的奈米線，而第二電晶體及第四電晶體具有第二數量的奈米線，其中第二數量不同於第一數量。在半導體裝置的一些實施例中，第一電晶體及第二電晶體為p型閘極全環(GAA) 場效電晶體(FET)，而第三電晶體及第四電晶體為n型閘極全環場效電晶體。在半導體裝置的一些實施例中，第一奈米線包括未摻雜之矽鍺，第二奈米線之第一子集包括未摻雜之矽鍺，而第二奈米線之第二子集包括以五族雜質摻雜之矽鍺。在半導體裝置的一些實施例中，第一組功函數調諧層包括氮化鈦、氮化鉭或鉬。在半導體裝置的一些實施例中，第三奈米線包括未摻雜的矽，第四奈米線之第一子集包括未摻雜的矽，而第四奈米線之第二子集包括以三族雜質摻雜的矽。在半導體裝置的一些實施例中，第二組功函數調諧層包括氮化鎢、鉭或鈦。
前述內文概述多項實施例或範例之特徵，如此可使於本技術領域中具有通常知識者更佳地瞭解本揭露之態樣。本技術領域中具有通常知識者應當理解他們可輕易地以本揭露為基礎設計或修改其他製程及結構，以完成相同之目的及/或達到與本文介紹之實施例或範例相同之優點。本技術領域中具有通常知識者亦需理解，這些等效結構並未脫離本揭露之精神及範圍，且在不脫離本揭露之精神及範圍之情況下，可對本揭露進行各種改變、置換以及變更。
50:基板
50A:區域
50B:區域
50C:區域
56:磊晶材料堆疊
58A:第一半導體層
58B:第二半導體層
66:磊晶材料堆疊
70A:第一半導體層
70B:第二半導體層
78:磊晶材料堆疊

Claims (11)

  1. 一種半導體裝置之製造方法，包括：在一基板中形成一第一凹槽及一第二凹槽；在上述第一凹槽中生長一第一磊晶材料堆疊，上述第一磊晶材料堆疊包括一第一半導體材料及一第二半導體材料所組成的交替層，上述第一磊晶材料堆疊的交替層是未摻雜的；在上述第二凹槽中生長一第二磊晶材料堆疊，上述第二磊晶材料堆疊包括上述第一半導體材料及上述第二半導體材料所組成的交替層，上述第二磊晶材料堆疊之一第一子集是未摻雜的，而上述第二磊晶材料堆疊之一第二子集則是經摻雜的；圖案化上述第一磊晶材料堆疊及上述第二磊晶材料堆疊，以分別形成複數第一奈米線及複數第二奈米線；以及形成環繞上述第一奈米線的一第一閘極結構以及環繞上述第二奈米線的一第二閘極結構。
  2. 如請求項1之半導體裝置之製造方法，其中上述第一閘極結構的形成包括環繞上述第一奈米線沉積一第一金屬，而上述第二閘極結構的形成包括環繞上述第二奈米線沉積一第二金屬，其中上述第二金屬不同於上述第一金屬。
  3. 如請求項1之半導體裝置之製造方法，更包括：在上述基板中形成一第三凹槽；在上述第三凹槽中生長一第三磊晶材料堆疊，上述第三材料堆疊包括上述第一半導體材料及上述第二半導體材料所組成的交替層，上述第三磊晶材料堆疊 之一第一子集是未摻雜的，而上述第三磊晶材料堆疊之一第二子集則是經摻雜的，其中上述第三磊晶材料堆疊之上述第二子集所包含的薄層多於上述第二磊晶材料堆疊之上述第二子集；圖案化上述第三磊晶材料堆疊以形成複數第三奈米線；以及形成環繞上述第三奈米線的一第三閘極結構。
  4. 如請求項3之半導體裝置之製造方法，其中：上述第一磊晶材料堆疊的生長包括：以一第一磊晶生長製程生長上述第一磊晶材料堆疊；上述第二磊晶材料堆疊的生長包括：以上述第一磊晶生長製程生長上述第二磊晶材料堆疊的上述第一子集；以及以一第二磊晶生長製程生長上述第二磊晶材料堆疊的上述第二子集，上述第二磊晶生長製程不同於上述第一磊晶生長製程；上述第三磊晶材料堆疊的生長包括：以上述第一磊晶生長製程生長上述第三磊晶材料堆疊的上述第一子集；以及以上述第二磊晶生長製程生長上述第三磊晶材料堆疊的上述第二子集。
  5. 如請求項1之半導體裝置之製造方法，其中上述第一磊晶材料堆疊的圖案化包括：在上述第一磊晶材料堆疊中蝕刻複數溝槽以形成一第一閘極全環(GAA)結構，上述第一閘極全環結構包括上述第一半導體材料及上述第二半導體材料所組成的交替層；在上述第一閘極全環結構上形成複數第一閘極間隔物；以及執行一蝕刻操作以蝕刻上述第一閘極全環結構在上述第一閘極間隔物之間 的部分，上述蝕刻操作選擇性地移除上述第一半導體材料的薄層，留下形成上述第一奈米線之上述第二半導體材料的薄層。
  6. 一種半導體裝置之製造方法，包括：在一基板中生長一第一磊晶材料堆疊，上述第一磊晶材料堆疊具有一第一平均雜質濃度；在上述基板中生長一第二磊晶材料堆疊，上述第二磊晶材料堆疊具有一第二平均雜質濃度；在上述基板中生長一第三磊晶材料堆疊，上述第三磊晶材料堆疊具有一第三平均雜質濃度，上述第一平均雜質濃度、上述第二平均雜質濃度及上述第三平均雜質濃度並不相同；平坦化上述基板，使得上述第一磊晶材料堆疊之頂部表面、上述第二磊晶材料堆疊之頂部表面、以及上述第三磊晶材料堆疊之頂部表面呈水平；圖案化上述第一磊晶材料堆疊、上述第二磊晶材料堆疊、以及上述第三磊晶材料堆疊，以分別形成複數第一奈米線、複數第二奈米線、以及複數第三奈米線；以及形成圍繞上述第一奈米線的一第一閘極結構、圍繞上述第二奈米線的一第二閘極結構、以及圍繞上述第三奈米線的一第三閘極結構。
  7. 一種半導體裝置，包括：一第一電晶體，包括複數第一奈米線及環繞上述第一奈米線的一第一閘極結構，上述第一奈米線具有一第一平均雜質濃度，上述第一閘極結構包括一第一組功函數調諧層；一第二電晶體，包括複數第二奈米線及環繞上述第二奈米線的一第二閘極結 構，上述第二奈米線具有一第二平均雜質濃度，上述第二平均雜質濃度不同於上述第一平均雜質濃度，上述第二閘極結構包括上述第一組功函數調諧層；一第三電晶體，包括複數第三奈米線及環繞上述第三奈米線的一第三閘極結構，上述第三奈米線具有上述第一平均雜質濃度，上述第三閘極結構包括一第二組功函數調諧層；以及一第四電晶體，包括複數第四奈米線及環繞上述第四奈米線的一第四閘極結構，上述第四奈米線具有上述第二平均雜質濃度，上述第四閘極結構包括上述第二組功函數調諧層，上述第二組功函數調諧層不同於上述第一組功函數調諧層，上述第四奈米線之一第一子集包括未摻雜的矽，上述第四奈米線之一第二子集包括摻雜的矽。
  8. 如請求項7之半導體裝置，其中上述第一電晶體、上述第二電晶體、上述第三電晶體、以及上述第四電晶體中的每一個，皆具有相同數量的奈米線。
  9. 如請求項7之半導體裝置，其中上述第一電晶體及上述第三電晶體具有一第一數量的奈米線，而上述第二電晶體及上述第四電晶體具有一第二數量的奈米線，上述第二數量不同於上述第一數量。
  10. 如請求項7之半導體裝置，其中上述第一電晶體及上述第二電晶體為p型閘極全環(GAA)場效電晶體(FET)，而上述第三電晶體及上述第四電晶體為n型閘極全環場效電晶體。
  11. 如請求項10之半導體裝置，其中上述第一奈米線包括未摻雜之矽鍺，上述第二奈米線之一第一子集包括未摻雜之矽鍺，上述第二奈米線之一第二子集包括以五族雜質摻雜之矽鍺，上述第三奈米線包括未摻雜的矽，上 述第四奈米線的該第二子集以三族雜質摻雜。
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