WO2023040128A1 - 阵列基板、显示面板以及阵列基板的制备方法 - Google Patents

阵列基板、显示面板以及阵列基板的制备方法 Download PDF

Info

Publication number
WO2023040128A1
WO2023040128A1 PCT/CN2021/143538 CN2021143538W WO2023040128A1 WO 2023040128 A1 WO2023040128 A1 WO 2023040128A1 CN 2021143538 W CN2021143538 W CN 2021143538W WO 2023040128 A1 WO2023040128 A1 WO 2023040128A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
groove
thin film
film transistor
shielding layer
Prior art date
Application number
PCT/CN2021/143538
Other languages
English (en)
French (fr)
Inventor
金璐
袁海江
Original Assignee
惠科股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 惠科股份有限公司 filed Critical 惠科股份有限公司
Publication of WO2023040128A1 publication Critical patent/WO2023040128A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present application relates to the field of display technology, and in particular to an array substrate, a display panel and a method for preparing the array substrate.
  • liquid crystal display panels Liquid Crystal Display, LCD
  • organic light emitting diode display panels Organic Light Emitting Diode, OLED
  • TFT Thin Film Transistor
  • the active layer is a very important film layer, which determines the performance of thin film transistors to a large extent, and many active layers have the problem of leakage current when exposed to light, which will lead to the failure of thin film transistors.
  • an array substrate In view of the purpose of this application is to provide an array substrate, a display panel and a method for preparing the array substrate, aiming at improving the performance instability of the active layer of the thin film transistor of the existing array substrate due to light exposure.
  • the present application discloses an array substrate, including a base substrate and a thin film transistor layer, the thin film transistor layer is arranged on the base substrate; the thin film transistor layer includes an active layer; the array substrate also includes a shielding layer , the shielding layer is disposed between the base substrate and the thin film transistor layer, the shielding layer is provided with a groove, and the active layer at least partially protrudes into the groove.
  • the present application also discloses a display panel, including an array substrate and a printed circuit board, the printed circuit board is bonded to the array substrate, and the array substrate adopts any one of the array substrates disclosed in the present application.
  • the present application also discloses a method for preparing an array substrate, which is configured to prepare any one of the array substrates disclosed in the present application, and the preparation method includes the steps of:
  • the thin film transistor layer is formed on the shielding layer, and the active layer of the formed thin film transistor layer at least partially protrudes into the groove.
  • the present application makes the shielding layer form a groove, and the active layer is at least partly deep into the groove. Designed so that the upper surfaces on both sides of the shielding layer are higher than at least a part of the lower surface of the active layer, forming a semi-surrounding structure for the active layer, so that the shielding layer can shield the active layer from below and from the side, That is to say, it can not only block the light under the shielding layer, but also well block the light incident from the side from reaching the active layer.
  • An excellent shading effect can be achieved through a shielding layer, avoiding the active layer of the thin film transistor.
  • the problem of leakage current caused by light exposure improves the working stability of the thin film transistor and improves the display effect.
  • FIG. 1 is a schematic diagram of a first embodiment of an array substrate of the present application
  • FIG. 2 is a schematic diagram of a second embodiment of the array substrate of the present application.
  • FIG. 3 is a schematic diagram of a third embodiment of the array substrate of the present application.
  • FIG. 4 is a schematic diagram of a display panel according to an embodiment of the present application.
  • FIG. 5 is a schematic diagram of the first embodiment of the method for preparing an array substrate of the present application.
  • FIG. 6 is a schematic diagram of a second embodiment of the method for preparing an array substrate of the present application.
  • FIG. 7 is a schematic diagram of a third embodiment of the method for preparing an array substrate of the present application.
  • Fig. 8 is a schematic structural diagram of the first stage of film layer change during the preparation process of the array substrate of the embodiment of the present application;
  • Fig. 9 is a schematic structural diagram of the second stage of film layer change during the preparation process of the array substrate of the embodiment of the present application.
  • Fig. 10 is a schematic structural diagram of the third stage of film layer change during the preparation process of the array substrate of the embodiment of the present application.
  • Fig. 11 is a schematic structural diagram of the fourth stage of film layer change during the preparation process of the array substrate of the embodiment of the present application.
  • Fig. 12 is a schematic structural diagram of the fifth stage of film layer change during the preparation process of the array substrate of the embodiment of the present application.
  • Fig. 13 is a schematic structural diagram of the sixth stage of film layer change during the preparation process of the array substrate of the embodiment of the present application;
  • Fig. 14 is a schematic structural diagram of the seventh stage of film layer change during the preparation process of the array substrate of the embodiment of the present application;
  • Fig. 15 is a schematic structural diagram of the eighth stage of film layer change during the preparation process of the array substrate of the embodiment of the present application.
  • Fig. 16 is a schematic structural diagram of the ninth stage of film layer change during the preparation process of the array substrate of the embodiment of the present application;
  • Fig. 17 is a schematic structural diagram of the tenth stage of film layer change during the preparation process of the array substrate of the embodiment of the present application;
  • Fig. 18 is a schematic structural diagram of the eleventh stage of film layer change during the preparation process of the array substrate of the embodiment of the present application;
  • Fig. 19 is a structural schematic diagram of the twelfth stage of film layer change during the preparation process of the array substrate of the embodiment of the present application;
  • Fig. 20 is a schematic structural diagram of the thirteenth stage of film layer change during the preparation process of the array substrate of the embodiment of the present application;
  • FIG. 21 is a schematic structural view of the final stage of film layer change during the preparation of the array substrate according to the embodiment of the present application.
  • the present application discloses an array substrate, including a base substrate and a thin film transistor layer, the thin film transistor layer is arranged on the base substrate; the thin film transistor layer includes an active layer; the array substrate also includes a shielding layer , the shielding layer is disposed between the base substrate and the thin film transistor layer, the shielding layer is provided with a groove, and the active layer at least partially protrudes into the groove.
  • the orthographic projection of the shielding layer on the base substrate completely covers the orthographic projection of the active layer on the substrate, and the height of at least a part of the upper surface of the shielding layer is higher than that of the active layer The height of the lower surface of a part.
  • this application uses the design that the shielding layer forms a groove, and the active layer is at least partly deep into the groove, so that in the The upper surfaces on both sides of the shielding layer are higher than at least a part of the lower surface of the active layer, forming a semi-surrounding structure for the active layer.
  • the shielding layer can shield the active layer from below and from the side, that is, not only It can block the light below the layer, and can well block the light incident from the side from reaching the active layer.
  • An excellent light-shielding effect can be achieved through a layer of blocking layer, which can prevent the active layer of the thin film transistor from being exposed to light and cause leakage.
  • the current problem can be improved to improve the working stability of the thin film transistor and improve the display effect.
  • the groove may be formed by the shielding layer itself, for example, the thickness of a certain position of the shielding layer is thinner than that of other positions, thereby forming the groove.
  • the groove can also be formed in other ways, such as depositing a film layer under the shielding layer, the film layer is first formed with a groove structure or a through-groove structure, and then the shielding layer is deposited to form a grooved groove. Occlusion layer.
  • the shielding layer of the present application can be designed as a liquid crystal display panel (LCD), or as an organic light-emitting diode display panel (OLED); it can be configured as a top-gate structure, or as a bottom-gate structure.
  • LCD liquid crystal display panel
  • OLED organic light-emitting diode display panel
  • Fig. 1 is a schematic diagram of the first embodiment of the array substrate of the present application.
  • the array substrate 10 disclosed in this embodiment includes a base substrate 110 and a thin film transistor layer 200, and the thin film transistor layer 200 is arranged on the On the base substrate 110;
  • the thin film transistor layer 200 includes an active layer;
  • the shielding layer includes a first shielding layer 11,
  • the thin film transistor layer 200 includes a driving thin film transistor 201, and the first shielding layer 11 corresponds to the
  • the driving thin film transistor 201 is set;
  • the groove includes a first groove 111, the first groove 111 is formed by the first shielding layer 11, the first groove 111 includes a groove bottom wall and two grooves
  • the side walls of the groove, the two side walls of the groove are arranged on both sides of the bottom wall of the groove, and the two ends of the bottom wall of the groove are respectively connected to the lower ends of the two side walls of the groove;
  • the active layer includes a first active layer 15, the first active layer 15 is located in the driving thin film transistor 201, and the first active layer 15 at least partially extends into the first groove 111 , and the height of the upper end of the side wall of the groove is greater than the height of the lower surface of the portion of the first active layer 15 corresponding to the bottom wall of the groove.
  • the height of the upper end of the side wall of the groove can also be greater than the height of the upper surface of the part of the first active layer 15 corresponding to the bottom of the first groove 111, even when the first active layer 15
  • the height of the upper end of the side wall of the groove may be higher than the height of the entire upper surface of the first active layer 15 .
  • the shielding layer can use other film layers to complete the preparation of the grooves, specifically, the array substrate 10
  • a first buffer layer 13 may also be included, and the first buffer layer 13 is arranged between the base substrate 110 and the shielding layer, specifically, between the base substrate 110 and the first shielding layer 11 , the first buffer layer 13 is provided with a first buffer groove 131, the thickness of the first shielding layer 11 is smaller than the depth of the first buffer groove 131, and the first shielding layer 11 at least covers the first A bottom wall and side walls of a buffer groove 131 form the groove.
  • the existence of the first buffer layer 13 and the first buffer groove 131 can facilitate the deposition of the shielding layer to form a groove that half surrounds the active layer.
  • the first buffer groove 131 can be a groove structure in which the first buffer layer 13 is concave but does not penetrate the first buffer layer 13, or a through groove structure penetrating the first buffer layer 13; if it is a groove structure, then The depth of the first buffer groove 131 is relatively shallow, which can reduce the risk of disconnection of the shielding layer and the film layer on it; if it is a through groove structure, the depth of the first buffer groove 131 is deeper, and the depth of the formed groove is also deeper, which can The active layer is better shielded from light from the side, and the problem of leakage current caused by oblique and refracted light entering the active layer from the side is improved.
  • the active layer can be directly formed on the shielding layer.
  • the shielding layer is made of a metal material (such as molybdenum (Mo), titanium (Ti), silver (Ag), aluminum (Al), molybdenum copper (MoCu) alloy, molybdenum ( (Mo) and aluminum (Al) when made of metal materials such as laminated structures), as an improvement of the first embodiment, the array substrate 10 further includes a second buffer layer 14, and the second buffer layer 14 Provided between the shielding layer and the thin film transistor layer 200, specifically, between the first shielding layer 11 and the thin film transistor layer 200; the second buffer layer 14 is formed corresponding to the groove The second buffer groove 141, specifically, the second buffer groove 141 is formed corresponding to the first groove 111;
  • the active layer covers the bottom wall and sidewall of the second buffer groove 141 to form an active layer groove, the width of the active layer is smaller than the width of the shielding layer, and the active layer, The total thickness of the second buffer layer 14 and the shielding layer is smaller than the depth of the first buffer groove 131 .
  • the shielding layer is made of metal, the second buffer layer 14 can prevent metal ions from diffusing into the active layer and affect the stability of the active layer.
  • the first active layer 15 covers the bottom wall and the side wall of the second buffer groove 141 to form an active layer groove 151, and the first active layer 15
  • the width is smaller than the width of the first shielding layer 11, and the total thickness of the first active layer 15, the second buffer layer 14 and the first shielding layer 11 is smaller than the depth of the first buffer groove 131 .
  • the groove wall of the first buffer tank 131 has a stepped shape.
  • the shielding layer when the depth of the first buffer tank 131 is relatively deep, the shielding layer and The risk of disconnection of the film layer on it; in addition, while the shielding layer forms a groove corresponding to the first buffer groove 131, the shielding layer itself can also be prepared by a semi-permeable membrane so that the film thickness ratio at the corresponding groove position is The thickness of the films on both sides is thin to obtain deeper grooves to better form a semi-enclosed shielding structure for the active layer.
  • the thin film transistor layer 200 of the present application includes at least a driving thin film transistor 201, and the active layer of the driving thin film transistor 201 can be made of amorphous silicon, polysilicon, or indium zinc oxide and other materials.
  • the following is an example of a top-gate structure thin film transistor made of indium zinc oxide material, specifically:
  • FIG. 2 is a schematic diagram of the second embodiment of the array substrate of the present application. As shown in FIG. 2, combined with FIG.
  • the driving thin film transistor 201 includes the first active layer 15, the first active layer 15 includes an indium gallium zinc oxide layer, and the driving thin film transistor 201 further includes: the gate insulating layer 17 is disposed on the indium gallium zinc oxide layer.
  • the interlayer dielectric layer 19 includes a first via hole 20, a second via hole 21 and a third via hole 22, a source electrode 24 and a drain electrode 25, which are arranged on the interlayer dielectric layer 19, and the drain electrode 25 passes through the first via hole 20 connected to the indium gallium zinc oxide layer; the source electrode 24 is connected to the indium gallium zinc oxide layer through the second via hole 21, and connected to the first shielding layer 11 through the third via hole 22; and the passivation layer 26 is set On the interlayer dielectric layer 19, an anode via hole 29 is arranged on the passivation layer 26; a flat layer 27 is arranged on the passivation layer 26, and an anode 28 is arranged on the flat layer 27, and the anode 28 is connected to the source 24.
  • the oxide active layer formed by indium gallium zinc oxide has excellent flexibility, and can also be set in the field of flexible display.
  • the output terminal of the thin film transistor is the source
  • the input terminal is the drain, which is different from the general situation where the source is used as the input terminal and the drain is used as the output terminal. The difference is common knowledge known to those skilled in the art, so it will not be repeated here.
  • the shielding layer includes a titanium metal layer, a titanium nitride layer or a laminated titanium metal layer and titanium nitride layer, that is, the shielding layer is made of titanium metal material or titanium nitride material.
  • the shielding layer can not only shield light, but also because the shielding layer is made of a metal material and is connected to the source, so the shielding layer plays the role of an auxiliary gate, that is, a double gate structure is formed, and the top gate/active layer Accumulate carriers at the same time as the bottom gate/active layer to form a top gate channel and a bottom gate channel, which can increase carrier mobility, have a larger gate capacitance, and control the surface potential of the channel more effectively.
  • the generation of the short channel effect can be suppressed, which is beneficial to the preparation of small-scale devices and the realization of high resolution.
  • the active layer especially when indium gallium zinc oxide is used as the active layer, its carriers (electrons) are mainly generated through oxygen vacancies, and the intervention of hydrogen will produce a series of chemical reactions, eventually occupying oxygen vacancies and releasing them.
  • the source of hydrogen is mainly used in the backplane preparation process, such as silane (SiH4) materials containing hydrogen, resulting in a trace amount of hydrogen remaining in the film layer; hydrogen in organic materials; back-end packaging processes may use materials with high hydrogen content such as silicon nitride/silicon oxynitride, due to hydrogen Molecule/atom/ion structures are small in size, so they can usually diffuse and migrate in each film layer.
  • silane (SiH4) materials containing hydrogen resulting in a trace amount of hydrogen remaining in the film layer
  • hydrogen in organic materials back-end packaging processes may use materials with high hydrogen content such as silicon nitride/silicon oxynitride, due to hydrogen Molecule/atom/ion structures are small in size, so they can usually diffuse and migrate in each film layer.
  • the crystal structure of titanium is a close-packed hexagonal system, which determines that the titanium film has the characteristics of high density and can block hydrogen penetration to a large extent; Very good adsorption, even if a small amount of hydrogen can enter the interior of titanium, it will be trapped in the lattice gap to form a Ti-H structure, so it is difficult for hydrogen to pass through the Ti film and affect the TFT device.
  • the shielding layer made of titanium metal material or titanium nitride material can block the lateral penetration of hydrogen into the active layer, and the thin film of the active layer is formed by using Indium Gallium Zinc Oxide (Indium Gallium Zinc Oxide, Indium Gallium Zinc Oxide) Transistors have extremely small leakage current, and using InGaZnO as the active layer can effectively reduce the leakage current of thin film transistors, thereby improving the display quality of the display panel.
  • Indium Gallium Zinc Oxide Indium Gallium Zinc Oxide, Indium Gallium Zinc Oxide
  • both the first buffer layer 13 and the second buffer layer 14 may include a SiOx layer, an AlO layer, or a stacked SiOx layer and an AlOx layer, or be made of silicon oxynitride (SiOxNy). Since both SiOx and AlOx do not contain hydrogen, the hydrogen content in the film can be further reduced.
  • the active layer includes an indium zinc oxide layer, and at the same time, the shielding layer is made of titanium metal material or titanium nitride material, and the second buffer layer is made of silicon oxide (SiOx) material or aluminum oxide (AlO) material, since the material of the shielding layer does not contain hydrogen, a better effect of reducing hydrogen can be achieved.
  • the thin film transistor layer 200 includes a source 24, and the shielding layer may further include a groove extension 123, and the groove extension 123 is connected to the side wall of the groove (for example may be connected to the side wall of the first groove 111);
  • the array substrate 10 further includes a capacitive electrode layer 23 disposed above the second buffer layer 14, the capacitive electrode layer 23 is formed in the same manufacturing process as the first active layer 15, and the groove extension 123, Both the capacitor electrode layer 23 and the source electrode 24 are at least partially overlapped to form a storage capacitor.
  • the source can be the source of the driving thin film transistor 201, and can also be the switch source of the switching thin film transistor.
  • the three-layer structure of the shielding layer, the capacitor electrode layer and the source forms a laminated capacitor electrode layer 23, not only The photomask process is reduced, the production efficiency is improved, and a capacitor with a larger capacity can be formed with a smaller area. While increasing the capacitance, the aperture ratio of the product is increased, which is more conducive to achieving high resolution.
  • Fig. 3 is a schematic diagram of the third embodiment of the array substrate of the present application. As shown in Fig. 3, this embodiment is an improvement based on the first and second embodiments. In order to better realize the switching performance, on the array substrate 10, except In addition to the driving thin film transistor 201, other thin film transistors may also be provided, and the number of other thin film transistors is variable. The following is an example where the number is one. That is, the thin film transistor layer 200 also includes a switching thin film transistor 202, The shielding layer includes a second shielding layer 12, and the second shielding layer 12 is set corresponding to the switching thin film transistor 201; the groove includes a second groove 121, and the second groove 121 is formed by the second groove. The shielding layer 12 is formed, the second groove 121 includes two second groove side walls, the two second groove side walls are arranged at intervals, and a hollow is formed between the two second groove side walls Hollow part 122;
  • the active layer includes a second active layer 16, the second active layer 16 is located in the switching thin film transistor 202, and the second active layer 16 at least partially extends into the second groove 121 , and the height of the upper end of the side wall of the second groove 121 is greater than the height of the lower surface of the portion of the second active layer 16 corresponding to the hollow portion 122 .
  • the switching thin film transistor 202 can also be provided with a first buffer layer, or the first buffer layer and the second buffer layer at the same time, the specific structure refers to the first embodiment, and will not be repeated.
  • Two different thin film transistors can meet different driving requirements according to different configurations.
  • the driving thin film transistor 201 and the switching thin film transistor 202 can be divided to achieve the required charging effect.
  • the driving thin film transistor 201 and the switching thin film transistor 202 can be formed through a common manufacturing process, as follows:
  • the switching thin film transistor 202 and the driving thin film transistor 201 are formed through a common manufacturing process
  • the common manufacturing process here refers to that at least a part of the film layers of the switching thin film transistor 202 and a part of the film layers of the driving thin film transistor 201 pass through
  • the switch thin film transistor 202 includes a second active layer 16, a switch insulating layer 30, a switch gate 31, a switch source 32 and a switch drain 33
  • the second active layer 16 includes a switch InGaZnO layer
  • the switch indium gallium zinc oxide layer is arranged on the second buffer layer 14
  • the switch indium gallium zinc oxide layer and the indium gallium zinc oxide layer are formed by the same process
  • the switch insulating layer 30 is arranged on the switch indium gallium zinc oxide layer layer
  • the switch insulating layer 30 is set on the same layer as the gate insulating layer 17
  • the switch gate 31 is formed on the switch insulating layer 30, and the switch gate 31 and the gate 18 are
  • the hole 34 is connected to the switch indium gallium zinc oxide layer; the switch drain 33 is connected to the switch indium gallium zinc oxide layer through the fifth via hole 35; the first buffer layer 13 also includes a first switch buffer groove 132, and the switch thin film transistor 202 Set corresponding to the first switch buffer groove 132; between the first buffer layer 121 and the second buffer layer 122, a second shielding layer 12 is arranged corresponding to the first switch buffer groove 132, and the second shielding layer 12 and the first shielding layer 11 is formed by a common manufacturing process; a second switch buffer groove 142 is disposed on the second buffer layer 13 , and the second switch buffer groove 142 is disposed corresponding to the first switch buffer groove 132 .
  • the switch gate 31 of the switch TFT 202 is connected to the scan line (SL), the switch drain 33 is connected to the data line (DL), and the switch source 32 is connected to the gate 18 of the drive TFT 201 .
  • the drain 25 of the driving thin film transistor 201 is connected to the reference voltage terminal, so that the switching thin film transistor 202 can adjust the anode voltage by controlling the voltage at the gate of the driving thin film transistor 201 .
  • FIG. 4 is a schematic diagram of a display panel according to an embodiment of the present application. As shown in FIG. 4 , the present application also discloses a display panel, including an array substrate 10 and a printed circuit board 300 , and the printed circuit board 300 is bound and connected to As for the array substrate 10, the array substrate 10 adopts any one of the array substrates 10 disclosed in this application.
  • the display panel 100 when the display panel 100 is a liquid crystal display panel, the display panel 100 further includes a color filter substrate disposed opposite to the array substrate 10 and a liquid crystal layer disposed between the array substrate 10 and the color filter substrate.
  • the display panel 100 when the display panel 100 is an organic light emitting diode display panel, the display panel further includes a light-emitting device layer disposed on the array substrate 10, the light-emitting device layer is deposited and formed by inkjet printing or evaporation process, and the light-emitting device layer includes an anode, an A hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron injection layer, etc., and the light emitting layer includes a red light emitting layer, a green light emitting layer and a blue light emitting layer.
  • FIG. 5 is a schematic diagram of the first embodiment of the method for preparing an array substrate of the present application. As shown in FIG. Array substrate, the preparation method comprises the steps of:
  • S1 setting a base substrate, depositing and etching on the base substrate to form the shielding layer, and the shielding layer forms the groove;
  • S2 Fabricate a thin film transistor layer on the shielding layer, and at least part of the active layer of the formed thin film transistor layer protrudes into the groove.
  • the groove can be realized by adjusting the film thickness of the shielding layer itself, or by means of other film layers.
  • FIG. 6 is a schematic diagram of a second embodiment of the method for preparing an array substrate of the present application.
  • a base substrate is provided, and the shielding layer is formed by depositing and etching on the base substrate,
  • the step S1 of forming the groove on the shielding layer includes:
  • S12 Depositing the shielding layer on the first buffer layer, the shielding layer covering the bottom wall and the sidewall of the first buffer tank to form the groove;
  • the step S2 of forming a thin film transistor layer on the shielding layer, wherein the active layer of the thin film transistor layer at least partially extends into the groove includes:
  • S21 Depositing a second buffer layer on the shielding layer, the second buffer layer covers the shielding layer, and forms a second buffer groove corresponding to the groove;
  • S22 Fabricate the thin film transistor layer on the second buffer layer corresponding to the top of the blocking layer, and the active layer of the formed thin film transistor layer covers the bottom wall of the second buffer groove and sidewalls to form an active layer groove, and the total thickness of the formed active layer, the second buffer layer and the shielding layer is smaller than the depth of the first buffer groove.
  • this step S21 may not be required, for example, when the shielding layer is made of non-metallic materials such as black matrix; It can be realized at the same time through the film thickness of the shielding layer and other film layers, that is, the shielding layer forms a groove corresponding to the position of the first buffer groove, and corresponding to the groove position, the thickness of the shielding layer is thinner than that of other positions, so as to obtain a deeper groove.
  • Fig. 7 is a schematic diagram of the third embodiment of the preparation method of the array substrate of the present application. As shown in Fig. 7, the present application also discloses a preparation method of the array substrate, and the array substrate is divided into a driving thin film transistor area and a switching thin film transistor area , including the following steps:
  • S111 Deposit a shielding layer material on the first buffer layer having the first buffer tank and the second buffer tank, etch the shielding layer material to form a first shielding layer corresponding to the first buffer tank, and the formed shielding layer covers the first
  • the bottom wall and the side wall of the buffer groove form the first groove, protrude from the first buffer groove, and extend to the upper surface of the first buffer layer to form a groove extension; at the same time, form a second shield corresponding to the second buffer groove layer, the formed second shielding layer covers at least the sidewall of the second groove, and is hollowed out corresponding to the groove bottom of the second buffer groove to form the second groove;
  • S112 Depositing a second buffer layer material on the first shielding layer and the second shielding layer, etching the second buffer layer material to form a second buffer layer covering the first buffer layer, the first groove, and the second groove, and The total thickness of the formed second buffer layer and the first shielding layer is less than the depth of the first buffer groove, that is, the height of the upper ends of the side walls of the first groove and the second groove is greater than the corresponding first groove and the second groove of the second buffer layer. the height of the upper surface at the location of the second recess;
  • S113 deposit an indium gallium zinc oxide material on the second buffer layer, etch to obtain an indium gallium zinc oxide layer corresponding to the first groove, and a switch indium gallium zinc oxide layer corresponding to the second groove;
  • S114 Deposit insulating layer material and gate layer material on the indium gallium zinc oxide layer and the switch indium gallium zinc oxide layer, etch to form the gate insulating layer and gate corresponding to the indium gallium zinc oxide layer, and the corresponding switch indium gallium oxide layer A switch insulating layer and a switch gate set by a zinc layer;
  • S115 deposit an interlayer dielectric layer material on the gate insulating layer and the switch insulating layer, and etch to form an interlayer dielectric layer.
  • the formed interlayer dielectric layer has a first via hole and a second via hole corresponding to both ends of the indium gallium zinc oxide layer.
  • S116 Depositing a metal material on the interlayer dielectric layer, etching to form a drain connected to the indium gallium zinc oxide layer through the first via hole, connected to the indium gallium zinc oxide layer through the second via hole, and connected to the indium gallium zinc oxide layer through the third via hole
  • the source electrode of the extension part is used to obtain the driving thin film transistor corresponding to the thin film transistor region; at the same time, the drain electrode of the switch connected to the switch InGaZn layer is formed through the fourth via hole, and the switch drain electrode is connected to the switch InGaZn layer through the fifth via hole
  • the switching source of the zinc layer is used to obtain the switching thin film transistor corresponding to the switching thin film transistor region;
  • S117 Deposit a passivation layer material on the source, drain, switch source and switch drain, etch to form a passivation layer with an anode via hole, and the formed anode via hole corresponds to the source; and on the passivation layer An anode connected to the source through the anode via is formed.
  • the main difference between this embodiment and the embodiment shown in FIG. 10 is that not only the thin film transistor and the switching thin film transistor are formed through a common process, but also the storage capacitor is also formed through a common process.
  • the buffer groove mentioned above can be a groove structure without hollowing out, or a through groove structure hollowed out, which is determined according to requirements.
  • Fig. 8-Fig. 21 shows the whole process of preparing the improved driving thin film transistor and switching thin film transistor of the present application on the array substrate by showing the schematic diagram of film layer changes in the preparation process, specifically :
  • Figure 8 is a schematic structural diagram of the first stage of film layer change during the preparation of the array substrate of the embodiment of the present application. 36 film structure diagram.
  • Fig. 9 is a schematic structural diagram of the second stage of film layer change during the preparation process of the array substrate of the embodiment of the present application. As shown in Fig. 9, it shows the film layer structure of the first buffer layer 13 obtained by etching the first buffer layer material picture.
  • FIG. 10 is a schematic structural diagram of the third stage of film layer change during the preparation process of the array substrate of the embodiment of the present application. As shown in FIG. 10 , it shows the film layer structure after peeling off the photoresist 36 above the first buffer layer 13 picture.
  • Fig. 11 is a schematic structural diagram of the fourth stage of film layer change during the preparation of the array substrate of the embodiment of the present application. As shown in Fig. 11, it shows the deposition of the shielding layer material and the film of photoresist 36 on the first buffer layer layer structure diagram.
  • Fig. 12 is a schematic structural diagram of the fifth stage of film layer change during the preparation process of the array substrate of the embodiment of the present application. As shown in Fig. 12, it shows that the shielding layer material is etched to form the first shielding layer 11 and the second shielding layer 12 Subsequent film layer structure diagram.
  • Figure 13 is a schematic structural diagram of the sixth stage of film layer change during the preparation of the array substrate of the embodiment of the present application.
  • the film layer structure diagram of is corresponding to the film layer structure after step S111 is executed.
  • Fig. 14 is a schematic structural diagram of the seventh stage of film layer change during the preparation of the array substrate of the embodiment of the present application. As shown in Fig. 14, it shows that the second buffer layer is deposited on the first shielding layer 11 and the second shielding layer 12 The material, the active layer material, and the film layer structure after forming the photoresist 36 above the active layer material correspond to the film layer structure after step S112 is performed.
  • Fig. 15 is a schematic structural diagram of the eighth stage of film layer change in the preparation process of the array substrate of the embodiment of the present application. As shown in Fig. 15, it shows that the first active layer 15, the second active layer 15, The film structure diagram after the source layer 16 and the capacitive electrode layer 23.
  • Fig. 16 is a schematic structural diagram of the ninth stage of film layer change during the preparation process of the array substrate of the embodiment of the present application. As shown in Fig. 16, it shows that the first active layer 15, the second active layer 16 and the capacitive electrode layer are peeled off
  • the layer structure diagram after the photoresist above 23 corresponds to the layer structure after step S113 is performed.
  • FIG. 17 is a schematic structural diagram of the tenth stage of film layer change during the preparation of the array substrate of the embodiment of the present application. As shown in FIG. 17 , it shows that the gate insulating layer 17 and the gate 18 are formed on the first active layer 15 , and a film layer structure diagram after forming the switch insulating layer 30 and the switch gate 31 on the second active layer 16, corresponding to the film layer structure after performing step S114.
  • Fig. 18 is a schematic structural diagram of the eleventh stage of film layer change during the preparation process of the array substrate according to the embodiment of the present application. As shown in Fig. The film layer structure diagram after the interlayer dielectric layer 19 of the hole 22 , the fourth via hole 34 and the fifth via hole 35 corresponds to the film layer structure after step S115 is performed.
  • Fig. 19 is a schematic structural diagram of the twelfth stage of film layer change during the preparation process of the array substrate of the embodiment of the present application. As shown in Fig. 19, it shows the first via hole 20, the second via hole 21, and the fourth via hole 34 and the fifth via hole 35 to form the source electrode 24 and the drain electrode 25, and form the film layer structure diagram after the switching source electrode 32 and the switching drain electrode 33, corresponding to the film layer structure after performing step S116.
  • Fig. 20 is a schematic structural diagram of the thirteenth stage of film layer change during the preparation of the array substrate of the embodiment of the present application. As shown in Fig. 20, it shows that a passivation layer 26 and a flat layer 27 are formed above the source and drain electrodes, And a film layer structure diagram after the anode via hole 29 is formed on the flat layer 27 .
  • Fig. 21 is a schematic structural diagram of the final stage of film layer change during the preparation process of the array substrate of the embodiment of the present application. As shown in Fig. 21, it shows the film layer structure diagram after the anode 28 is formed corresponding to the position of the anode via hole, corresponding to the execution of step S117 Subsequent film structure, the driving thin film transistor and the switching thin film transistor have been prepared so far.
  • the pixel definition layer and other film layers can also be formed on the anode, but this is not the main invention of this application, so it will not be described in detail.
  • the first shielding layer 11 and the second shielding layer 12 are formed in the same layer, and a photoresist 36 with a predetermined pattern is formed by a common photomask process, and then formed by a common etching process.
  • the first active layer 15, the capacitive electrode layer 23 and the second active layer 16 are also in the same layer, and so on, the film layers such as the gate, source and drain layers, and the gate insulating layer can also share the same manufacturing process. Forming.
  • inventive concept of the present application can form a lot of embodiments, but the space of the application documents is limited, and it is impossible to list them one by one.
  • the technical features can be combined arbitrarily to form a new embodiment, and the original technical effect will be enhanced after each embodiment or technical feature is combined.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本申请公开了一种阵列基板、显示面板以及阵列基板的制备方法，所述阵列基板（10）包括：包括衬底基板（110）和薄膜晶体管层（200），所述薄膜晶体管层（200）设于所述衬底基板（110）上；所述薄膜晶体管层（200）包括有源层；还包括遮挡层，所述遮挡层设于所述衬底基板（110）和所述薄膜晶体管层（200）之间，所述遮挡层设有凹槽，所述有源层至少部分伸入至所述凹槽内。本申请通过以上方式，改善有源层受到光照而造成的漏电流问题。

Description

阵列基板、显示面板以及阵列基板的制备方法
本申请要求于2021年09月15日提交中国专利局，申请号为CN202111077851.2，申请名称为“阵列基板、显示面板以及阵列基板的制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板、显示面板以及阵列基板的制备方法。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术；
目前，液晶显示面板(Liquid Crystal Display，LCD)和有机发光二极管显示面板(Organic Light Emitting Diode，OLED)中均具有阵列基板，阵列基板上设置有薄膜晶体管(Thin Film Transistor，TFT)。
在薄膜晶体管中，有源层是非常重要的膜层，在很大程度上决定了薄膜晶体管的性能，而很多的有源层，都存在受到光照时产生漏电流的问题，将导致薄膜晶体管的性能不稳定；现有技术中为了解决这个技术问题，在有源层的下方设置了遮挡层，但是遮挡层的效果有限，薄膜晶体管的性能依然不稳定。
发明内容
鉴于本申请的目的是提供一种阵列基板、显示面板以及阵列基板的制备方法，旨在改善现有阵列基板的薄膜晶体管的有源层受到光照导致性能不稳定的现象。
本申请公开了一种阵列基板，包括衬底基板和薄膜晶体管层，所述薄膜晶体管层设于所述衬底基板上；所述薄膜晶体管层包括有源层；所述阵列基板还包括遮挡层，所述遮挡层设于所述衬底基板和所述薄膜晶体管层之间，所述遮挡层设有凹槽，所述有源层至少部分伸入至所述凹槽内。
本申请还公开了一种显示面板，包括阵列基板和印刷电路板，所述印刷电路板绑定连接于所述阵列基板，所述阵列基板采用本申请公开的任意一种所述的阵列基板。
本申请还公开了一种阵列基板的制备方法，设置为制备本申请公开的任意一种所述的阵列基板，所述制备方法包括步骤：
设置一衬底基板，在所述衬底基板上沉积并蚀刻形成所述遮挡层，所述遮挡层形成所述凹槽；
在所述遮挡层上制作所述薄膜晶体管层，形成的所述薄膜晶体管层的有源层至少部分伸入所述凹槽内。
相对于现有技术的显示面板中，有源层受到光照产生漏电流而导致薄膜晶体管稳定性差的方案来说，本申请通过让遮挡层形成凹槽，且有源层至少部分深入凹槽内的设计，使得在遮挡层的两侧的上表面高于有源层至少一部分的下表面，对有源层形成半包围结构，这样的 话，遮挡层就可以从下方以及侧面对有源层进行遮挡，即不仅仅可以遮住遮挡层下方的光线，而且可以很好地阻挡从侧面入射的光线照射到有源层，通过一层遮挡层即达到了极好的遮光效果，避免薄膜晶体管的有源层受到光照而产生漏电流的问题，提高薄膜晶体管的工作稳定性，提高显示效果。
附图说明
图1是本申请阵列基板的第一实施例的示意图；
图2是本申请阵列基板的第二实施例的示意图；
图3是本申请阵列基板的第三实施例的示意图；
图4是本申请实施例一种显示面板的示意图；
图5是本申请阵列基板的制备方法的第一实施例的示意图；
图6是本申请阵列基板的制备方法的第二实施例的示意图；
图7是本申请阵列基板的制备方法的第三实施例的示意图；
图8是本申请实施例阵列基板的制备过程中膜层变化第一阶段的结构示意图；
图9是本申请实施例阵列基板的制备过程中膜层变化第二阶段的结构示意图；
图10是本申请实施例阵列基板的制备过程中膜层变化第三阶段的结构示意图；
图11是本申请实施例阵列基板的制备过程中膜层变化第四阶段的结构示意图；
图12是本申请实施例阵列基板的制备过程中膜层变化第五阶段的结构示意图；
图13是本申请实施例阵列基板的制备过程中膜层变化第六阶段的结构示意图；
图14是本申请实施例阵列基板的制备过程中膜层变化第七阶段的结构示意图；
图15是本申请实施例阵列基板的制备过程中膜层变化第八阶段的结构示意图；
图16是本申请实施例阵列基板的制备过程中膜层变化第九阶段的结构示意图；
图17是本申请实施例阵列基板的制备过程中膜层变化第十阶段的结构示意图；
图18是本申请实施例阵列基板的制备过程中膜层变化第十一阶段的结构示意图；
图19是本申请实施例阵列基板的制备过程中膜层变化第十二阶段的结构示意图；
图20是本申请实施例阵列基板的制备过程中膜层变化第十三阶段的结构示意图；
图21是本申请实施例阵列基板的制备过程中膜层变化最终阶段的结构示意图。
具体实施方式
下面参考附图和可选的实施例对本申请作详细说明。
本申请公开了一种阵列基板，包括衬底基板和薄膜晶体管层，所述薄膜晶体管层设于所述衬底基板上；所述薄膜晶体管层包括有源层；所述阵列基板还包括遮挡层，所述遮挡层设于所述衬底基板和所述薄膜晶体管层之间，所述遮挡层设有凹槽，所述有源层至少部分伸入至所述凹槽内。其中，所述遮挡层在所述衬底基板的正投影完全覆盖所述有源层在衬底基板 的正投影，且所述遮挡层至少一部分的上表面的高度，高于所述有源层一部分的下表面的高度。
相对于显示面板中，有源层受到光照产生漏电流而导致薄膜晶体管稳定性差的方案来说，本申请通过让遮挡层形成凹槽，且有源层至少部分深入凹槽内的设计，使得在遮挡层的两侧的上表面高于有源层至少一部分的下表面，对有源层形成半包围结构，这样的话，遮挡层就可以从下方，以及侧面对有源层进行遮挡，即不仅仅可以遮挡层下方的光线，而且可以很好地阻挡从侧面入射的光线照射到有源层，通过一层遮挡层即达到了极好的遮光效果，避免薄膜晶体管的有源层受到光照而产生漏电流的问题，提高薄膜晶体管的工作稳定性，提高显示效果。
其中，该凹槽可以是遮挡层自身形成，例如遮挡层的某一位置厚度较其他位置薄，从而形成凹槽。当然，也可以通过其他方式形成该凹槽，例如在遮挡层下方先沉积一膜层，该膜层先形成以凹槽结构或者通槽结构，然后再沉积遮挡层，即可形成具有凹槽的遮挡层。
另外，本申请的遮挡层的设计，可以设置为液晶显示面板(LCD)，也可以设置为有机发光二极管显示面板(OLED)；可以设置为顶栅结构，也可以应设置为底栅结构。如下，以OLED以及顶栅结构为例，结合附图对本申请进行更具体地说明：
图1是本申请阵列基板的第一实施例的示意图，如图1所示，本实施例公开的阵列基板10包括衬底基板110和薄膜晶体管层200，所述薄膜晶体管层200设于所述衬底基板110上；所述薄膜晶体管层200包括有源层；所述遮挡层包括第一遮挡层11，所述薄膜晶体管层200包括驱动薄膜晶体管201，所述第一遮挡层11对应所述驱动薄膜晶体管201设置；所述凹槽包括第一凹槽111，所述第一凹槽111由所述第一遮挡层11形成，所述第一凹槽111包括凹槽底壁和两个凹槽侧壁，两个所述凹槽侧壁设于所述凹槽底壁的两侧，且所述凹槽底壁的两端分别和两个所述凹槽侧壁的下端连接；
所述有源层包括第一有源层15，所述第一有源层15位于所述驱动薄膜晶体管201内，所述第一有源层15至少部分伸入所述第一凹槽111内，且所述凹槽侧壁的上端的高度，大于所述第一有源层15对应所述凹槽底壁设置的部分的下表面的高度。
当然，所述凹槽侧壁上端的高度也可以大于所述第一有源层15对应所述第一凹槽111底部设置的部分的上表面的高度，甚至，当第一有源层15的宽度小于凹槽的宽度，并完全伸入凹槽内时，所述凹槽侧壁上端的高度可以高于整个第一有源层15的上表面的高度。
可选的，作为第一实施例的一种改进，如图1所示，为了更好更容易地形成凹槽，该遮挡层可以借助其他膜层完成凹槽的制备，具体的，阵列基板10还可以包括第一缓冲层13，所述第一缓冲层13设于所述衬底基板110和所述遮挡层之间，具体的，在衬底基板110和所述第一遮挡层11之间，所述第一缓冲层13设有第一缓冲槽131，所述第一遮挡层11的厚 度小于所述第一缓冲槽131的深度，且所述第一遮挡层11至少铺满所述第一缓冲槽131的底壁和侧壁以形成所述凹槽。第一缓冲层13以及第一缓冲槽131的存在，可以方便遮挡层沉积形成半包围有源层的凹槽。其中，第一缓冲槽131可以是第一缓冲层13下凹但不贯穿第一缓冲层13的凹槽结构，也可以是贯穿第一缓冲层13的通槽结构；若为凹槽结构，则第一缓冲槽131深度较浅，可以减少遮挡层以及其上的膜层断线的风险；若为通槽结构的话，第一缓冲槽131的深度更深，形成的凹槽的深度也更深，可以更好地从侧面对有源层进行遮光，改善斜射和折射的光线从侧面进入有源层而导致漏电流的问题。
当遮挡层采用黑矩阵等非金属材料制成，此时，有源层可以直接形成在遮挡层上。
当然为了减少不好的元素侵入有源层，例如遮挡层采用金属材料(例如采用钼(Mo)、钛(Ti)、银(Ag)、铝(Al)、钼铜(MoCu)合金、钼(Mo)和铝(Al)的叠层结构等金属材料制成时)制成时，作为第一实施例的一种改进，阵列基板10还包括第二缓冲层14，所述第二缓冲层14设于所述遮挡层和所述薄膜晶体管层200之间，具体的，在所述第一遮挡层11和所述薄膜晶体管层200之间；所述第二缓冲层14对应所述凹槽形成第二缓冲槽141，具体的，对应第一凹槽111形成第二缓冲槽141；
所述有源层铺满所述第二缓冲槽141的底壁和侧壁以形成有源层凹槽，所述有源层的宽度小于所述遮挡层的宽度，且所述有源层、所述第二缓冲层14和所述遮挡层的总厚度小于所述第一缓冲槽131的深度。当所述遮挡层采用金属材质制成时，所述第二缓冲层14可以阻挡金属离子扩散到有源层影响有源层的稳定性。
具体到第一遮挡层11位置，所述第一有源层15铺满所述第二缓冲槽141的底壁和侧壁以形成有源层凹槽151，所述第一有源层15的宽度小于所述第一遮挡层11的宽度，且所述第一有源层15、所述第二缓冲层14和所述第一遮挡层11的总厚度小于所述第一缓冲槽131的深度。
另外，作为本实施例的进一步改进，还可以考虑将第一缓冲槽131的槽壁为台阶形状，这样的话，可以在第一缓冲槽131的深度较深的情况下，也可以减少遮挡层以及其上的膜层发生断线的风险；另外，在遮挡层对应第一缓冲槽131形成凹槽的同时，该遮挡层本身也可以通过半透膜制备而使得对应凹槽位置处的膜厚比两侧的膜厚薄，以得到更深的凹槽以更好地对有源层形成半包围遮挡结构。
本申请的薄膜晶体管层200至少包括有驱动薄膜晶体管201，该驱动薄膜晶体管201的有源层可以采用非晶硅，多晶硅，也可以采用氧化铟锌等材料制成。如下以采用氧化铟锌材料制成的顶栅结构薄膜晶体管为例进行介绍，具体的：
图2是本申请阵列基板的第二实施例的示意图，如图2所示，结合图1可知，本实施例跟第一实施例的主要区别在于：薄膜晶体管层200包括驱动薄膜晶体管201，所述驱动薄膜 晶体管201包括所述第一有源层15，所述第一有源层15包括氧化铟镓锌层，所述驱动薄膜晶体管201还包括：栅极绝缘层17设置于氧化铟镓锌层上，栅极18设置于栅极绝缘层17上，层间介质层19设置在栅极18上，覆盖第二缓冲层122、氧化铟镓锌层、栅极绝缘层17以及栅极18，层间介质层19包括第一过孔20和第二过孔21以及第三过孔22，源极24和漏极25，设置于层间介质层19上，漏极25通过第一过孔20与氧化铟镓锌层相连接；源极24通过第二过孔21与氧化铟镓锌层相连接，并通过第三过孔22与第一遮挡层11相连接；以及钝化层26，设置在层间介质层19上，钝化层26上设置有阳极过孔29；平坦层27，设置在钝化层26上，平坦层27上设置有阳极28，阳极28通过阳极过孔29连接于源极24。氧化铟镓锌形成的氧化物有源层具有优越的柔韧性，也可以设置为柔性显示的领域。本实施例中，氧化铟镓锌作为有源层时，薄膜晶体管的输出端是源极，而输入端则是漏极，与一般情况下，源极作为输入端，漏极作为输出端的情况有所区别，这是本领域技术人员公知的常识，因而，不再赘述。
其中，所述遮挡层包括钛金属层、氮化钛层或叠层设置的钛金属层和氮化钛层，即所述遮挡层采用钛金属材料或氮化钛材料制成。此时，遮挡层不仅可以遮光，而且由于遮挡层采用金属材料制成，且与源极相连通，如此该遮挡层起到了辅助栅极的作用，即形成双栅结构，顶栅/有源层和底栅/有源层同时积累载流子，形成顶栅沟道和底栅沟道，可以增加载流子迁移率，可以具有更大的栅电容，能更有效地控制沟道表面势，可以抑制短沟道效应的产生，有利于制备小尺寸器件和实现高分辨率。
另外，有源层，特别是氧化铟镓锌作为有源层时，它的载流子(电子)主要通过氧空位产生，而氢元素的介入会产生一系列化学反应，最终占据氧空位并释放出更多的电子，从而导致氧化铟镓锌的载流子浓度变高，阈值电压产生负偏，使薄膜晶体管更容易开启；而氢的来源，主要是背板制备工艺中，使用到如硅烷(SiH4)这类含有氢的材料，导致膜层中有微量氢残留；有机材料中的氢；后端封装工艺可能使用氮化硅/氮氧化硅这类含氢量高的材料，由于氢的分子/原子/离子结构体积均很小，所以通常可以在各膜层中扩散、迁移。
因而，以钛为例，一方面，钛的晶体结构为密排六方晶系，这决定了钛膜层具有高致密性的特点，能够很大程度地阻隔氢渗透；另一方面钛对于氢有很好的吸附作用，即便有微量的氢可以进入钛内部，也会被捕获在晶格间隙位置，形成Ti-H的结构，因此氢很难透过Ti膜层而影响TFT器件。因而，采用钛金属材料或氮化钛材料制成的遮挡层，可以阻挡氢横向渗透进入有源层，利用铟镓锌氧化物(Indium Gallium Zinc Oxide，氧化铟镓锌)形成有源层的薄膜晶体管具有极小的漏电流，将氧化铟镓锌作为有源层可以有效降低薄膜晶体管的漏电流，进而提升显示面板的显示画质。
其中，第一缓冲层13和第二缓冲层14均可以包括SiOx层、AlO层或者叠层设置的SiOx 层和AlOx层，或者是采用硅氮氧化物(SiOxNy)制成。由于SiOx和AlOx均不含氢元素，因而，可以进一步减少膜层中的氢含量。当然，所述有源层包括氧化铟锌层，同时，所述遮挡层采用钛金属材料或氮化钛材料制成，所述第二缓冲层采用氧化硅(SiOx)材料或氧化铝(AlO)材料制成，由于遮挡层的材料也不含氢，可以达到更好的减少氢元素的效果。
另外，如图2所示，所述薄膜晶体管层200包括源极24，所述遮挡层还可以包括凹槽延伸部123，所述凹槽延伸部123与所述凹槽的侧壁连接(例如可以是和第一凹槽111的侧壁连接)；
所述阵列基板10还包括设于所述第二缓冲层14上方的电容电极层23，所述电容电极层23与所述第一有源层15共用制程形成，所述凹槽延伸部123、所述电容电极层23和所述源极24均至少部分重叠，以形成存储电容。其中，所述源极可以是驱动薄膜晶体管201的源极，也可以是开关薄膜晶体管的开关源极，该遮挡层、电容电极层以及源极三层结构形成叠层的电容电极层23，不仅减少了光罩制程，提高了生产效率，而且，可以利用更小的面积形成更大容量的电容，增大电容的同时，增加产品的开口率，更有利于实现高分辨率。
图3是本申请阵列基板的第三实施例的示意图，如图3所示，本实施例是基于第一和第二实施例的改进，为了更好地实现开关性能，阵列基板10上，除了驱动薄膜晶体管201之外，还可以设置有其他的薄膜晶体管，其他的薄膜晶体管的数量不定，如下以数量为1个为例进行介绍，即：所述薄膜晶体管层200还包括开关薄膜晶体管202，所述遮挡层包括第二遮挡层12，所述第二遮挡层12对应所述开关薄膜晶体管201设置；所述凹槽包括第二凹槽121，所述第二凹槽121由所述第二遮挡层12形成，所述第二凹槽121包括两个第二凹槽侧壁，两个所述第二凹槽侧壁间隔设置，且两个所述第二凹槽侧壁之间镂空形成镂空部122；
所述有源层包括第二有源层16，所述第二有源层16位于所述开关薄膜晶体管202内，所述第二有源层16至少部分伸入所述第二凹槽121内，且所述第二凹槽121的侧壁上端的高度，大于所述第二有源层16对应所述镂空部122设置的部分的下表面的高度。同理于第一实施例，该开关薄膜晶体管202也可以设置第一缓冲层，或第一缓冲层和同时设置第二缓冲层，具体结构参考第一实施例，不再赘述。
两种不同的薄膜晶体管，可以根据不同的搭配满足不同的驱动需求，例如，以OLED为例，驱动薄膜晶体管201和开关薄膜晶体管202可以进行分工，以达到需求的充电效果。
为了节省制程，提高生产效果，该驱动薄膜晶体管201和开关薄膜晶体管202，可以通过共用制程形成，具体如下：
如图3所示，所述开关薄膜晶体管202和所述驱动薄膜晶体管201通过共用制程形成，这里的共用制程指的是开关薄膜晶体管202的至少一部分膜层与驱动薄膜晶体管201的一部分膜层通过共用制程形成，开关薄膜晶体管202包括第二有源层16、开关绝缘层30、开关 栅极31、开关源极32和开关漏极33，所述第二有源层16包括开关氧化铟镓锌层，所述开关氧化铟镓锌层设置于第二缓冲层14上，所述开关氧化铟镓锌层与氧化铟镓锌层共用制程形成，所述开关绝缘层30设置于开关氧化铟镓锌层上，所述开关绝缘层30与栅极绝缘层17同层设置；所述开关栅极31形成在开关绝缘层30上，所述开关栅极31与栅极18通过共用制程形成；所述开关源极32和开关漏极33相对设置在层间介质层19上，所述层间介质层19还包括第四过孔34和第五过孔35，所述开关源极32通过第四过孔34与开关氧化铟镓锌层相连接；开关漏极33通过第五过孔35与开关氧化铟镓锌层相连接；第一缓冲层13还包括第一开关缓冲槽132，开关薄膜晶体管202对应第一开关缓冲槽132设置；在第一缓冲层121和第二缓冲层122之间，对应第一开关缓冲槽132处设置有第二遮挡层12，第二遮挡层12与第一遮挡层11通过共用制程形成；在第二缓冲层13上设置有第二开关缓冲槽142，所述第二开关缓冲槽142对应第一开关缓冲槽132设置。
其中，开关薄膜晶体管202的开关栅极31与扫描线(SL)相连，开关漏极33与数据线(DL)相连，开关源极32与驱动薄膜晶体管201的栅极18相连。驱动薄膜晶体管201的漏极25与参考电压端相连，这样的话，开关薄膜晶体管202就可以通过控制驱动薄膜晶体管201的栅极处的电压，调节阳极电压。
图4是本申请实施例一种显示面板的示意图，如图4所示，本申请还公开了一种显示面板，包括阵列基板10和印刷电路板300，所述印刷电路板300绑定连接于所述阵列基板10，所述阵列基板10采用本申请公开的任意一种所述的阵列基板10。
其中，当显示面板100为液晶显示面板，显示面板100还包括与阵列基板10相对设置的彩膜基板以及设置于阵列基板10和彩膜基板之间的液晶层。当显示面板100为有机发光二极管显示面板，显示面板还包括设置于阵列基板10上的发光器件层，发光器件层通过喷墨打印或蒸镀工艺沉积形成，发光器件层包括依次层叠设置的阳极、空穴注入层、空穴传输层、发光层、电子传输层以及电子注入层等，发光层包括红色发光层、绿色发光层以及蓝色发光层。
图5是本申请阵列基板的制备方法的第一实施例的示意图，如图5所示，本申请还公开了一种阵列基板的制备方法，设置为制备本申请公开的任意一种所述的阵列基板，所述制备方法包括步骤：
S1:设置一衬底基板，在所述衬底基板上沉积并蚀刻形成所述遮挡层，所述遮挡层形成所述凹槽；
S2:在所述遮挡层上制作薄膜晶体管层，形成的所述薄膜晶体管层的有源层至少部分伸入所述凹槽内。其中，该凹槽可以是遮挡层自己本身通过调节膜厚等方式来实现，可以是借助其他膜层来实现。
图6是本申请阵列基板的制备方法的第二实施例的示意图，如图6所示，例如，所述设置一衬底基板，在所述衬底基板上沉积并蚀刻形成所述遮挡层，所述遮挡层形成所述凹槽的步骤S1包括：
S11:在所述衬底基板上沉积第一缓冲层，在所述第一缓冲层上蚀刻出第一缓冲槽；
S12:在所述第一缓冲层上沉积所述遮挡层，所述遮挡层铺满所述第一缓冲槽的底壁和侧壁以形成所述凹槽；
所述在所述遮挡层上制作薄膜晶体管层，所述薄膜晶体管层的有源层至少部分伸入所述凹槽内的步骤S2包括：
S21:在所述遮挡层上沉积第二缓冲层，所述第二缓冲层覆盖所述遮挡层，并对应所述凹槽内形成第二缓冲槽；
S22:在所述第二缓冲层上，且对应所述遮挡层的上方制作所述薄膜晶体管层，形成的所述薄膜晶体管层的所述有源层铺满所述第二缓冲槽的底壁和侧壁以形成有源层凹槽，且形成的所述有源层、所述第二缓冲层和所述遮挡层的总厚度小于所述第一缓冲槽的深度。
其中，在不需要第二缓冲层时，也可以不要该步骤S21，例如，遮挡层是采用黑矩阵等非金属材料制成时；另外，除了第一缓冲层辅助形成凹槽的方式以外，也可以通过遮挡层膜厚和其他膜层辅助同时实现，即遮挡层对应第一缓冲槽的位置形成凹槽，且对应凹槽位置，遮挡层的厚度比其他位置的厚度薄，从而得到深度更深的凹槽。
图7是本申请阵列基板的制备方法的第三实施例的示意图，如图7所示，本申请还公开了一种阵列基板的制备方法，阵列基板划分为驱动薄膜晶体管区域和开关薄膜晶体管区域，包括以下步骤：
S111:在具有第一缓冲槽和第二缓冲槽的第一缓冲层上沉积遮挡层材料，蚀刻遮挡层材料，形成对应第一缓冲槽设置的第一遮挡层，形成的遮挡层铺满第一缓冲槽的底壁和侧壁以形成第一凹槽，并突出于第一缓冲槽，延伸至第一缓冲层的上表面形成凹槽延伸部；同时，形成对应第二缓冲槽的第二遮挡层，形成的第二遮挡层至少覆盖第二凹槽的侧壁，且对应第二缓冲槽的槽底镂空以形成第二凹槽；
S112：在第一遮挡层和第二遮挡层上沉积第二缓冲层材料，蚀刻第二缓冲层材料，形成覆盖第一缓冲层、第一凹槽、第二凹槽的第二缓冲层，且形成的第二缓冲层和第一遮挡层的总厚度小于第一缓冲槽的深度，即第一凹槽和第二凹槽的侧壁上端的高度，大于第二缓冲层对应第一凹槽和第二凹槽位置处的上表面的高度；
S113：在第二缓冲层上沉积氧化铟镓锌材料，蚀刻得到对应第一凹槽设置的氧化铟镓锌层，以及对应第二凹槽设置的开关氧化铟镓锌层；
S114：在氧化铟镓锌层和开关氧化铟镓锌层上沉积绝缘层材料和栅极层材料，蚀刻形成 对应氧化铟镓锌层设置的栅极绝缘层和栅极，以及对应开关氧化铟镓锌层设置的开关绝缘层和开关栅极；
S115：在栅极绝缘层和开关绝缘层上沉积层间介质层材料，蚀刻形成层间介质层，形成的层间介质层，对应氧化铟镓锌层的两端形成有第一过孔和第二过孔，对应延伸部设置有第三过孔，对应开关氧化铟镓锌层的两端设置有第四过孔和第五过孔；
S116：在层间介质层上沉积金属材料，蚀刻形成通过第一过孔连接于氧化铟镓锌层的漏极，以及通过第二过孔连接于氧化铟镓锌，并通过第三过孔连接于延伸部的源极，以得到对应薄膜晶体管区域的驱动薄膜晶体管；同时形成通过第四过孔连接于开关氧化铟镓锌层的开关漏极，以及通过第五过孔连接于开关氧化铟镓锌层的开关源极以得到对应开关薄膜晶体管区域的开关薄膜晶体管；
S117：在源极、漏极、开关源极和开关漏极上沉积钝化层材料，蚀刻形成具有阳极过孔的钝化层，形成的阳极过孔对应源极设置；并在钝化层上形成通过阳极过孔连接于源极的阳极。本实施例，与图10所示实施例的主要区别在于，不仅薄膜晶体管和开关薄膜晶体管是通过共用制程形成，且该存储电容也是通过共用制程形成的。其中，上述的缓冲槽，可以是不镂空的凹槽结构，也可以是镂空的通槽结构，根据需求决定。
对应于阵列基板的制备方法的第三实施例，图8-图21通过展示制备过程的膜层变化示意图来展示在阵列基板制备本申请改进的驱动薄膜晶体管和开关薄膜晶体管的整个过程，具体的：
图8是本申请实施例阵列基板的制备过程中膜层变化第一阶段的结构示意图，如图8所示，展示的是在衬底基板110上沉积第一缓冲层材料，和形成光刻胶36的膜层结构图。
图9是本申请实施例阵列基板的制备过程中膜层变化第二阶段的结构示意图，如图9所示，展示的是对第一缓冲层材料进行蚀刻得到第一缓冲层13的膜层结构图。
图10是本申请实施例阵列基板的制备过程中膜层变化第三阶段的结构示意图，如图10所示，展示的是剥离位于第一缓冲层13上方的光刻胶36之后的膜层结构图。
图11是本申请实施例阵列基板的制备过程中膜层变化第四阶段的结构示意图，如图11所示，展示的是在第一缓冲层上方沉积遮挡层材料，以及光刻胶36的膜层结构图。
图12是本申请实施例阵列基板的制备过程中膜层变化第五阶段的结构示意图，如图12所示，展示的是对遮挡层材料进行蚀刻形成第一遮挡层11和第二遮挡层12之后的膜层结构图。
图13是本申请实施例阵列基板的制备过程中膜层变化第六阶段的结构示意图，如图13所示，展示的是剥离第一遮挡层11和第二遮挡层12上方的光刻胶之后的膜层结构图，对应执行步骤S111之后的膜层结构。
图14是本申请实施例阵列基板的制备过程中膜层变化第七阶段的结构示意图，如图14所示，展示的是在第一遮挡层11和第二遮挡层12上方沉积第二缓冲层材料、有源层材料和形成位于有源层材料上方的光刻胶36之后的膜层结构图，对应执行步骤S112之后的膜层结构。
图15是本申请实施例阵列基板的制备过程中膜层变化第八阶段的结构示意图，如图15所示，展示的是对有源层材料进行蚀刻得到第一有源层15、第二有源层16和电容电极层23之后的膜层结构图。
图16是本申请实施例阵列基板的制备过程中膜层变化第九阶段的结构示意图，如图16所示，展示的是剥离第一有源层15、第二有源层16和电容电极层23上方的光刻胶之后的膜层结构图，对应执行步骤S113之后的膜层结构。
图17是本申请实施例阵列基板的制备过程中膜层变化第十阶段的结构示意图，如图17所示，展示的是在第一有源层15上方形成栅极绝缘层17和栅极18，并在第二有源层16上方形成开关绝缘层30和开关栅极31之后的膜层结构图，对应执行步骤S114之后的膜层结构。
图18是本申请实施例阵列基板的制备过程中膜层变化第十一阶段的结构示意图，如图18所示，展示的是形成具有第一过孔20、第二过孔21、第三过孔22、第四过孔34和第五过孔35的层间介质层19之后的膜层结构图，对应执行步骤S115之后的膜层结构。
图19是本申请实施例阵列基板的制备过程中膜层变化第十二阶段的结构示意图，如图19所示，展示的是对应第一过孔20、第二过孔21、第四过孔34和第五过孔35位置形成源极24和漏极25，并形成开关源极32和开关漏极33之后的膜层结构图，对应执行步骤S116之后的膜层结构。
图20是本申请实施例阵列基板的制备过程中膜层变化第十三阶段的结构示意图，如图20所示，展示的是在源极和漏极上方形成钝化层26和平坦层27，且在平坦层27上形成阳极过孔29之后的膜层结构图。
图21是本申请实施例阵列基板的制备过程中膜层变化最终阶段的结构示意图，如图21所示，展示的是对应阳极过孔位置形成阳极28之后的膜层结构图，对应执行步骤S117之后的膜层结构，至此驱动薄膜晶体管和开关薄膜晶体管完成制备，当然，在阳极之上还可以形成像素定义层等膜层，但不是本申请的主要发明点所在，因而，不予赘述。当然，图8-图21中所示的驱动薄膜晶体管和开关薄膜晶体管的结构仅是一种示例，而不是限制，该驱动薄膜晶体管和开关薄膜晶体管采用其他的驱动结构也是可以的。其中，第一遮挡层11和第二遮挡层12是同层形成的，通过共用光罩制程，形成预设图案的光刻胶36，然后再共用蚀刻制程形成。同理，该第一有源层15、电容电极层23和第二有源层16也是同层的，以此 类推，栅极、源漏极层、栅极绝缘层等膜层也是可以共用制程形成的。
需要说明的是，本方案中涉及到的各步骤的限定，在不影响具体方案实施的前提下，并不认定为对步骤先后顺序作出限定，写在前面的步骤可以是在先执行的，也可以是在后执行的，甚至也可以是同时执行的，只要能实施本方案，都应当视为属于本申请的保护范围。
需要说明的是，本申请的发明构思可以形成非常多的实施例，但是申请文件的篇幅有限，无法一一列出，因而，在不相冲突的前提下，以上描述的各实施例之间或各技术特征之间可以任意组合形成新的实施例，各实施例或技术特征组合之后，将会增强原有的技术效果。
以上内容是结合具体的可选实施方式对本申请所作的进一步详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以作出若干简单推演或替换，都应当视为本申请的保护范围。

Claims (18)

  1. 一种阵列基板，包括衬底基板和薄膜晶体管层，所述薄膜晶体管层设于所述衬底基板上；所述薄膜晶体管层包括有源层；所述阵列基板还包括遮挡层，所述遮挡层设于所述衬底基板和所述薄膜晶体管层之间，所述遮挡层设有凹槽，所述有源层至少部分伸入至所述凹槽内。
  2. 根据权利要求1所述的阵列基板，其中，所述薄膜晶体管层包括驱动薄膜晶体管，所述遮挡层包括第一遮挡层，所述第一遮挡层对应所述驱动薄膜晶体管设置；所述凹槽包括第一凹槽，所述第一凹槽由所述第一遮挡层形成，所述第一凹槽包括凹槽底壁和两个凹槽侧壁，两个所述凹槽侧壁设于所述凹槽底壁的两侧，且所述凹槽底壁的两端分别和两个所述凹槽侧壁的下端连接；
    所述有源层包括第一有源层，所述第一有源层位于所述驱动薄膜晶体管内，所述第一有源层至少部分伸入所述第一凹槽内。
  3. 根据权利要求2所述的阵列基板，其中，所述薄膜晶体管层还包括开关薄膜晶体管，所述遮挡层还包括第二遮挡层，所述第二遮挡层对应所述开关薄膜晶体管设置；所述凹槽包括第二凹槽，所述第二凹槽由所述第二遮挡层形成，所述第二凹槽包括两个第二凹槽侧壁，两个所述第二凹槽侧壁间隔设置，且两个所述第二凹槽侧壁之间镂空形成镂空部；
    所述有源层包括第二有源层，所述第二有源层位于所述驱动薄膜晶体管内，所述第二有源层至少部分伸入所述第二凹槽内。
  4. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括第一缓冲层，所述第一缓冲层设于所述衬底基板和所述遮挡层之间，所述第一缓冲层设有第一缓冲槽，所述遮挡层的厚度小于所述第一缓冲槽的深度，且所述遮挡层至少铺满所述第一缓冲槽的底壁和侧壁以形成所述凹槽。
  5. 根据权利要求2所述的阵列基板，其中，所述阵列基板还包括第一缓冲层，所述第一缓冲层设于所述衬底基板和所述遮挡层之间，所述第一缓冲层设有第一缓冲槽，所述遮挡层的厚度小于所述第一缓冲槽的深度，且所述遮挡层至少铺满所述第一缓冲槽的底壁和侧壁以形成所述凹槽。
  6. 根据权利要求3所述的阵列基板，其中，所述阵列基板还包括第一缓冲层，所述第一缓冲层设于所述衬底基板和所述遮挡层之间，所述第一缓冲层设有第一缓冲槽，所述遮挡层的厚度小于所述第一缓冲槽的深度，且所述遮挡层至少铺满所述第一缓冲槽的底壁和侧壁以形成所述凹槽。
  7. 根据权利要求4所述的阵列基板，其中，所述阵列基板还包括第二缓冲层，所述第二缓冲层设于所述遮挡层和所述薄膜晶体管层之间；所述第二缓冲层对应所述凹槽形成第二 缓冲槽；
    所述有源层铺满所述第二缓冲槽的底壁和侧壁以形成有源层凹槽。
  8. 根据权利要求7所述的阵列基板，其中，所述有源层包括氧化铟锌层，所述遮挡层采用钛金属材料或氮化钛材料制成，所述第二缓冲层采用氧化硅材料或氧化铝材料制成。
  9. 根据权利要求7所述的阵列基板，其中，所述薄膜晶体管层包括源极，所述遮挡层还包括凹槽延伸部，所述凹槽延伸部与所述凹槽的侧壁连接；
    所述阵列基板还包括设于所述第二缓冲层上方的电容电极层，所述凹槽延伸部、所述电容电极层和所述源极均至少部分重叠，以形成存储电容。
  10. 根据权利要求2所述的阵列基板，其中，所述驱动薄膜晶体管还包括：栅极绝缘层设置于氧化铟镓锌层上，栅极设置于栅极绝缘层上，层间介质层设置在栅极上，覆盖第二缓冲层、氧化铟镓锌层、栅极绝缘层以及栅极，层间介质层包括第一过孔和第二过孔以及第三过孔，源极和漏极，设置于层间介质层上，漏极通过第一过孔与氧化铟镓锌层相连接；源极通过第二过孔与氧化铟镓锌层相连接，并通过第三过孔与第一遮挡层相连接。
  11. 根据权利要求1所述的阵列基板，其中，所述遮挡层包括钛金属层、氮化钛层或叠层设置的钛金属层和氮化钛层。
  12. 一种显示面板，包括阵列基板和印刷电路板，所述印刷电路板绑定连接于所述阵列基板，所述阵列基板包括衬底基板和薄膜晶体管层，所述薄膜晶体管层设于所述衬底基板上；所述薄膜晶体管层包括有源层；其特征在于：还包括遮挡层，所述遮挡层设于所述衬底基板和所述薄膜晶体管层之间，所述遮挡层设有凹槽，所述有源层至少部分伸入至所述凹槽内。
  13. 根据权利要求12所述的显示面板，其中，所述薄膜晶体管层包括驱动薄膜晶体管，所述遮挡层包括第一遮挡层，所述第一遮挡层对应所述驱动薄膜晶体管设置；所述凹槽包括第一凹槽，所述第一凹槽由所述第一遮挡层形成，所述第一凹槽包括凹槽底壁和两个凹槽侧壁，两个所述凹槽侧壁设于所述凹槽底壁的两侧，且所述凹槽底壁的两端分别和两个所述凹槽侧壁的下端连接；
    所述有源层包括第一有源层，所述第一有源层位于所述驱动薄膜晶体管内，所述第一有源层至少部分伸入所述第一凹槽内。
  14. 根据权利要求12所述的显示面板，其中，所述薄膜晶体管层还包括开关薄膜晶体管，所述遮挡层还包括第二遮挡层，所述第二遮挡层对应所述开关薄膜晶体管设置；所述凹槽包括第二凹槽，所述第二凹槽由所述第二遮挡层形成，所述第二凹槽包括两个第二凹槽侧壁，两个所述第二凹槽侧壁间隔设置，且两个所述第二凹槽侧壁之间镂空形成镂空部；
    所述有源层包括第二有源层，所述第二有源层位于所述驱动薄膜晶体管内，所述第二有源层至少部分伸入所述第二凹槽内。
  15. 根据权利要求12所述的显示面板，其中，所述薄膜晶体管层还包括开关薄膜晶体管，所述遮挡层还包括第二遮挡层，所述第二遮挡层对应所述开关薄膜晶体管设置；所述凹槽包括第二凹槽，所述第二凹槽由所述第二遮挡层形成，所述第二凹槽包括两个第二凹槽侧壁，两个所述第二凹槽侧壁间隔设置，且两个所述第二凹槽侧壁之间镂空形成镂空部；
    所述有源层包括第二有源层，所述第二有源层位于所述驱动薄膜晶体管内，所述第二有源层至少部分伸入所述第二凹槽内。
  16. 根据权利要求12所述的显示面板，其中，所述显示面板还包括设置在所述阵列基板上的发光器件层，所述发光器件层通过喷墨打印或蒸镀工艺沉积形成，所述发光器件层包括依次层叠设置的阳极、空穴注入层、空穴传输层、发光层、电子传输层以及电子注入层，所述发光层包括红色发光层、绿色发光层以及蓝色发光层。
  17. 一种阵列基板的制备方法，设置为制备阵列基板，所述阵列基板包括衬底基板和薄膜晶体管层，所述薄膜晶体管层设于所述衬底基板上；所述薄膜晶体管层包括有源层；其特征在于：还包括遮挡层，所述遮挡层设于所述衬底基板和所述薄膜晶体管层之间，所述遮挡层设有凹槽，所述有源层至少部分伸入至所述凹槽内，所述制备方法包括步骤：
    设置一衬底基板，在所述衬底基板上沉积并蚀刻形成所述遮挡层，所述遮挡层形成所述凹槽；以及
    在所述遮挡层上制作所述薄膜晶体管层，形成的所述薄膜晶体管层的有源层至少部分伸入所述凹槽内。
  18. 根据权利要求17所述的阵列基板的制备方法，其中，所述设置一衬底基板，在所述衬底基板上沉积并蚀刻形成所述遮挡层，所述遮挡层形成所述凹槽的步骤包括：
    在所述衬底基板上沉积第一缓冲层，在所述第一缓冲层上蚀刻出第一缓冲槽；以及
    在所述第一缓冲层上沉积所述遮挡层，所述遮挡层铺满所述第一缓冲槽的底壁和侧壁以形成所述凹槽；
    所述在所述遮挡层上制作所述薄膜晶体管层，所述薄膜晶体管层的有源层至少部分伸入所述凹槽内的步骤包括：
    在所述遮挡层上沉积第二缓冲层，所述第二缓冲层覆盖所述遮挡层，并对应所述凹槽内形成第二缓冲槽；以及
    在所述第二缓冲层上，且对应所述遮挡层的上方制作所述薄膜晶体管层，形成的所述薄膜晶体管层的所述有源层铺满所述第二缓冲槽的底壁和侧壁以形成有源层凹槽，且形成的所述有源层、所述第二缓冲层和所述遮挡层的总厚度小于所述第一缓冲槽的深度。
PCT/CN2021/143538 2021-09-15 2021-12-31 阵列基板、显示面板以及阵列基板的制备方法 WO2023040128A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202111077851.2A CN113540131B (zh) 2021-09-15 2021-09-15 阵列基板、显示面板以及阵列基板的制备方法
CN202111077851.2 2021-09-15

Publications (1)

Publication Number Publication Date
WO2023040128A1 true WO2023040128A1 (zh) 2023-03-23

Family

ID=78093269

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/143538 WO2023040128A1 (zh) 2021-09-15 2021-12-31 阵列基板、显示面板以及阵列基板的制备方法

Country Status (2)

Country Link
CN (1) CN113540131B (zh)
WO (1) WO2023040128A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113540131B (zh) * 2021-09-15 2022-01-18 惠科股份有限公司 阵列基板、显示面板以及阵列基板的制备方法
CN115763499A (zh) * 2022-12-23 2023-03-07 武汉华星光电技术有限公司 阵列基板及其制备方法、显示装置

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020071073A1 (en) * 2000-12-07 2002-06-13 Nec Corporation Active matrix type liquid crystal display device
JP2004271903A (ja) * 2003-03-07 2004-09-30 Sharp Corp 薄膜トランジスタ基板およびその製造方法並びに液晶表示装置
CN101017298A (zh) * 2006-02-07 2007-08-15 精工爱普生株式会社 液晶装置及投影仪
CN110265412A (zh) * 2019-06-27 2019-09-20 京东方科技集团股份有限公司 阵列基板、显示面板和阵列基板的制造方法
CN111223876A (zh) * 2019-11-06 2020-06-02 深圳市华星光电半导体显示技术有限公司 显示面板及显示面板的制备方法
CN113066818A (zh) * 2019-12-13 2021-07-02 华为技术有限公司 一种显示屏和电子设备
CN113284945A (zh) * 2021-04-13 2021-08-20 武汉华星光电半导体显示技术有限公司 薄膜晶体管及制备方法、显示基板
CN113540131A (zh) * 2021-09-15 2021-10-22 惠科股份有限公司 阵列基板、显示面板以及阵列基板的制备方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3230669B2 (ja) * 1998-11-26 2001-11-19 日本電気株式会社 液晶表示装置用薄膜トランジスタ基板およびその製造方法
CN108573956B (zh) * 2018-04-17 2020-04-17 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN110911424B (zh) * 2019-12-11 2022-08-09 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示面板

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020071073A1 (en) * 2000-12-07 2002-06-13 Nec Corporation Active matrix type liquid crystal display device
JP2004271903A (ja) * 2003-03-07 2004-09-30 Sharp Corp 薄膜トランジスタ基板およびその製造方法並びに液晶表示装置
CN101017298A (zh) * 2006-02-07 2007-08-15 精工爱普生株式会社 液晶装置及投影仪
CN110265412A (zh) * 2019-06-27 2019-09-20 京东方科技集团股份有限公司 阵列基板、显示面板和阵列基板的制造方法
CN111223876A (zh) * 2019-11-06 2020-06-02 深圳市华星光电半导体显示技术有限公司 显示面板及显示面板的制备方法
CN113066818A (zh) * 2019-12-13 2021-07-02 华为技术有限公司 一种显示屏和电子设备
CN113284945A (zh) * 2021-04-13 2021-08-20 武汉华星光电半导体显示技术有限公司 薄膜晶体管及制备方法、显示基板
CN113540131A (zh) * 2021-09-15 2021-10-22 惠科股份有限公司 阵列基板、显示面板以及阵列基板的制备方法

Also Published As

Publication number Publication date
CN113540131B (zh) 2022-01-18
CN113540131A (zh) 2021-10-22

Similar Documents

Publication Publication Date Title
WO2023040128A1 (zh) 阵列基板、显示面板以及阵列基板的制备方法
US20200105789A1 (en) Array substrate, method of manufacturing the same, and display panel
US9947699B2 (en) Manufacturing method of dual gate oxide semiconductor TFT substrate and substrate thereof
JP2024129053A (ja) 半導体装置
EP3703111A1 (en) Tft substrate, manufacturing method thereof and oled panel manufacturing method
US8946701B2 (en) Thin film transistor, array substrate and display device
US10707236B2 (en) Array substrate, manufacturing method therefor and display device
US9368525B2 (en) Display device and electronic apparatus
US20210217784A1 (en) Array substrate, method for manufacturing array substrate, and display panel
WO2016165186A1 (zh) 双栅极氧化物半导体tft基板的制作方法及其结构
WO2020238384A1 (zh) 阵列基板的制作方法、阵列基板、显示面板及显示装置
US10497563B2 (en) Thin film transistor and method for manufacturing the same, array substrate and method for manufacturing the same, display panel and display device
KR102044667B1 (ko) 산화물 박막 트랜지스터를 구비한 평판표시장치 및 그의 제조방법
WO2018006441A1 (zh) 薄膜晶体管、阵列基板及其制备方法
WO2020244313A1 (zh) 阵列基板及其制备方法、显示面板、显示装置
WO2016165185A1 (zh) 双栅极氧化物半导体tft基板的制作方法及其结构
WO2016165187A1 (zh) 双栅极氧化物半导体tft基板的制作方法及其结构
TW201513369A (zh) 薄膜電晶體及其製造方法
US11222904B2 (en) Thin film transistor and manufacturing method thereof, array substrate and manufacturing method thereof, and display device
WO2020215603A1 (zh) Oled显示面板及其制备方法
CN102024842A (zh) 显示器及其制造方法
WO2020215602A1 (zh) Oled显示面板的制备方法及oled显示面板
CN107195634A (zh) 一种tft阵列基板及其制作方法
WO2023082349A1 (zh) 阵列基板及其制备方法、显示面板
WO2021159566A1 (zh) 显示面板及其制作方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21957390

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE