WO2023028790A1 - 存储器及其操作方法、存储器系统 - Google Patents

存储器及其操作方法、存储器系统 Download PDF

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Publication number
WO2023028790A1
WO2023028790A1 PCT/CN2021/115475 CN2021115475W WO2023028790A1 WO 2023028790 A1 WO2023028790 A1 WO 2023028790A1 CN 2021115475 W CN2021115475 W CN 2021115475W WO 2023028790 A1 WO2023028790 A1 WO 2023028790A1
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Prior art keywords
programming
storage
plane
planes
memory
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PCT/CN2021/115475
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English (en)
French (fr)
Inventor
郭晓江
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长江存储科技有限责任公司
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Priority to PCT/CN2021/115475 priority Critical patent/WO2023028790A1/zh
Priority to JP2023537895A priority patent/JP2023554144A/ja
Priority to CN202180003644.4A priority patent/CN113994315A/zh
Priority to EP21955369.0A priority patent/EP4202938A1/en
Priority to KR1020237021007A priority patent/KR20230108332A/ko
Priority to US18/090,409 priority patent/US20230148416A1/en
Publication of WO2023028790A1 publication Critical patent/WO2023028790A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/102—External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device

Definitions

  • the embodiments of the present application relate to the field of semiconductors, and in particular, to a memory, an operation method thereof, and a memory system.
  • the memory can be divided into a single storage plane (Plane) type and a multi storage plane type.
  • a memory of the single-plane type includes one plane; a memory of the multi-plane type includes multiple planes.
  • a multi-plane programming mode can be used to simultaneously program two or more storage planes of the memory, so as to improve programming efficiency.
  • Using the multi-side programming mode can certainly improve the programming efficiency, but there will inevitably be the problem of adjacent plane interference. A programming failure occurred on the surface. Therefore, there is an urgent need to provide a programming method that can reduce the adverse effects of adjacent surface interference on the premise of ensuring a certain programming efficiency.
  • embodiments of the present application provide a memory, an operation method thereof, and a memory system.
  • An embodiment of the present application provides a method for operating a memory, including:
  • a single-side programming mode is used to continue to perform programming operations on each of the at least two storage planes in sequence.
  • the single-side programming mode is adopted, and the programming operation is continued on each of the at least two storage planes in sequence, including:
  • the first programming voltage is lower than the second programming voltage;
  • the second programming voltage is a programming voltage applied to the first selected word line of the corresponding storage plane when it is determined that there is a storage plane with a programming abnormality;
  • the first selected word line is the selected word line of the corresponding storage plane when it is determined that there is a programming abnormality in the storage plane.
  • the method also includes:
  • the first programming voltage is applied on the first selected word line of the corresponding storage plane; the first turn-on voltage is applied on the unselected word line in the corresponding storage plane; the first turn-on voltage is smaller than the second Turn-on voltage; the second turn-on voltage is the turn-on voltage applied to the unselected word line of the corresponding storage plane when it is determined that there is a storage plane with abnormal programming.
  • the determination of the storage plane with programming exception among the at least two storage planes includes:
  • the method also includes:
  • program verification voltages are respectively applied to the currently programmed memory cells in different memory planes.
  • the method also includes:
  • program verification voltages are respectively applied to memory cells corresponding to different word lines in the same storage plane.
  • a single-side programming mode is adopted to continue to perform programming operations on each of the at least two storage planes in sequence, including :
  • the method also includes:
  • the single-side programming mode is used to continue to program each of the at least two storage planes sequentially, including:
  • the programming operation is continued on the second storage plane of the at least two storage planes.
  • the method also includes:
  • the multi-side programming mode is used to continue programming operations on the at least two storage planes.
  • An embodiment of the present application provides a memory, including: multiple storage planes and peripheral circuits coupled to the storage planes; wherein,
  • the peripheral circuit is configured to simultaneously perform programming operations on at least two storage planes among the plurality of storage planes in a multi-plane programming mode; programming mode, continuing to perform programming operations on each of the at least two storage planes in sequence.
  • the peripheral circuit includes: a control circuit and a row driver; the row driver is coupled to the at least two storage planes and is controlled by the control circuit;
  • the row driver is configured to apply a word line driving voltage to at least two storage planes simultaneously performing programming operations in a multi-plane programming mode
  • the row driver is configured to apply a word line driving voltage to a selected storage plane in a single-plane programming mode.
  • the row driver is configured to, after switching from the multi-side programming mode to the single-side programming mode, for each storage plane, apply the first programming voltage on the first selected word line of the corresponding storage plane;
  • the first programming voltage is lower than the second programming voltage;
  • the second programming voltage is a programming voltage applied to the first selected word line of the corresponding storage plane when it is determined that there is a storage plane with a programming abnormality;
  • the first selected word line is the selected word line of the corresponding storage plane when it is determined that there is a programming abnormality in the storage plane.
  • the row driver is configured such that, when the first programming voltage is applied to the first selected word line of the corresponding storage plane; the first turn-on voltage is applied to the unselected word lines of the corresponding storage plane ; The first conduction voltage is less than the second conduction voltage; the second conduction voltage is the conduction voltage applied to the unselected word line of the corresponding storage plane when it is determined that there is a storage plane with abnormal programming.
  • the peripheral circuit is configured as:
  • the peripheral circuit further includes: a plurality of program verification voltage generators; each of the plurality of program verification voltage generators is respectively coupled to one of the at least two storage planes, and is controlled by the Controlled by the control circuit;
  • the plurality of program verification voltage generators are configured to respectively apply program verification voltages to currently programmed memory cells in different storage planes.
  • each of the plurality of program verification voltage generators is respectively coupled to a word line of one of the at least two storage planes;
  • the plurality of program verification voltage generators are configured to respectively apply program verification voltages to memory cells corresponding to different word lines in the same storage plane.
  • the peripheral circuit is configured to, when it is determined that there is a programming abnormal storage plane among the at least two storage planes, directly adopt the single-side programming mode, and continue to program each of the at least two storage planes. Perform programming operations in sequence;
  • the peripheral circuit is configured to suspend the programming operation when it is determined that there is a programming abnormal storage plane among the at least two storage planes; after receiving the second instruction, adopt a single-side programming mode and continue programming the at least two storage planes Each memory plane in the memory is programmed in turn.
  • the peripheral circuit further includes: a register configured to save the first flag when it is determined that there is a programming abnormal storage plane among the multiple storage planes;
  • the peripheral circuit is configured to: when receiving the first instruction, use other storage planes in the memory to store data stored in the storage plane allocated to the programming exception; the first instruction is used to instruct the corresponding The data stored in the storage plane is dumped.
  • the memory includes a three-dimensional NAND memory.
  • the embodiment of the present application also provides a memory system, including:
  • a storage controller coupled to the storage.
  • the method also includes:
  • the peripheral circuit is configured to receive a second instruction; in response to the second instruction, use a multi-plane programming mode to simultaneously perform programming operations on at least two storage planes among the plurality of storage planes; determine that the at least two When there is a storage plane with abnormal programming in the storage plane, suspend the programming operation and save the first mark;
  • the memory controller is configured to issue a third instruction based on the first flag
  • the peripheral circuit is configured to receive a third instruction; in response to the third instruction, adopt a single-side programming mode and continue to perform programming operations on each of the at least two storage planes in sequence.
  • the multi-sided programming mode when receiving a programming operation instruction, the multi-sided programming mode is used by default to perform the programming operation, so as to ensure a certain programming efficiency; when it is determined that there is a programming exception, switch to the single-sided programming mode to continue Programming, in this way, can limit the programming abnormality to the abnormal storage plane itself, and reduce the impact of the programming abnormality on other normal storage planes, that is, reduce the adverse effect caused by the adjacent plane interference.
  • FIG. 1 is a schematic diagram of a first implementation flow of a memory operation method provided by an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a memory provided by an embodiment of the present application.
  • FIG. 3 is a second schematic diagram of an implementation flow of a storage operation method provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a memory system provided by an embodiment of the present application.
  • the memory in the embodiment of the present application includes but is not limited to a three-dimensional NAND memory.
  • a three-dimensional NAND memory is used as an example for description.
  • embodiments of the present application concept are not limited to this configuration, but are also applicable to two-dimensional NAND memory.
  • the present application is applicable to other non-volatile memory devices, for example, Electrically Erasable Programmable Read-Only Memory (EEPROM, Electrically Erasable Programmable Read-Only Memory), NOR Type Flash Memory, Phase Change Random Access Memory (PRAM, Chase Random Access Memory), Magnetic Random Access Memory (MRAM, Magnetoresistive Random Access Memory), Resistive Random Access Memory (RRAM, Resistive Random Access Memory), Ferroelectric Random Access Memory (FRAM, Ferroelectric Random Access Memory) Access Memory), etc.
  • EEPROM Electrically Erasable Programmable Read-Only Memory
  • NOR Type Flash Memory Phase Change Random Access Memory
  • MRAM Magnetoresistive Random Access Memory
  • Resistive Random Access Memory Resistive Random Access Memory
  • FRAM Ferroelectric Random Access Memory
  • the three-dimensional NAND memory may include a memory cell array and peripheral circuits; wherein, the memory cell array has a plurality of storage planes (Plane), each storage plane includes a plurality of storage blocks (Block), and each storage A block includes a plurality of memory pages (Page), and a memory page is the smallest unit of reading and writing (ie, programming), while a memory block is the smallest unit of erasing.
  • the memory cell array has a plurality of storage planes (Plane), each storage plane includes a plurality of storage blocks (Block), and each storage A block includes a plurality of memory pages (Page), and a memory page is the smallest unit of reading and writing (ie, programming), while a memory block is the smallest unit of erasing.
  • the peripheral circuits may include any suitable digital, analog and/or mixed-signal circuits configured to facilitate various operations of the memory such as read operations, write operations, and erase operations.
  • the peripheral circuit may include control logic (such as a control circuit or a controller), a data buffer, a decoder (a decoder may also be called a decoder), a driver, and a read/write circuit and the like.
  • control logic such as a control circuit or a controller
  • a data buffer such as a control circuit or a controller
  • a decoder a decoder may also be called a decoder
  • the decoder can apply the corresponding voltage from the driver to the corresponding bit line and word line based on the decoded address to realize the data reading.
  • the three-dimensional NAND memory in the memory system has many kinds of defects, some defects can be detected when leaving the factory, and some defects are exposed with the change of the use environment after leaving the factory.
  • there may be structural weak points in some memory cell arrays of 3D NAND memory and these structural weak points may take a long time or a large number of programming operations and erasing operations before developing and becoming defects.
  • the memory cell array of the three-dimensional NAND memory needs to withstand high pressure stress during programming and erasing cycles, and weak structures in some memory cell arrays of the three-dimensional NAND memory will develop into defects after cycling.
  • a defect occurs in a three-dimensional NAND-type memory
  • data loss may occur. If the defect is a short circuit of a word line (WL, Word Line), the data in the memory cells corresponding to the entire WL may be destroyed. Since each WL may correspond to multiple character string storage units, based on this, a large amount of data may be lost, which may cause failures to the memory system.
  • This type of failure is generally defined as a reliability failure of a three-dimensional NAND type memory, which may further cause a failure of the memory system in the field.
  • the memory system can use Redundant Arrays of Independent Disks (RAID, Redundant Arrays of Independent Disks) to recover lost data.
  • RAID Redundant Arrays of Independent Disks
  • a general storage system adopts a plane-level RAID, and a plane-level RAID can only recover a failure of one storage plane. If programming fails on multiple planes, the memory system will not be able to recover the data. For such failures, the memory system can implement RAID at the die (Die) level, but the configuration cost of the memory system will increase.
  • the internal voltage bias power supply is usually shared between different planes during programming operations in order to save circuit area and power consumption. If one plane is defective, none of the other planes sharing the internal voltage bias supply may reach the target level, so programming failures often occur on multiple planes even if only one plane is physically defective, which is the aforementioned Neighbor Plane Disturb (NPD, Neighbor Plane Disturb). Hence, adjacent surface interference will bring adverse effects such as the aforementioned data loss. Based on this, if a physical defect only exists in one storage plane, it is hoped that the fault only occurs in the defective storage plane.
  • NPD Neighbor Plane Disturb
  • FIG. 1 is a schematic diagram of the implementation process of a method for operating a memory device provided in the embodiment of the present application.
  • the method includes:
  • Step 101 Simultaneously perform programming operations on at least two storage planes among the multiple storage planes of the memory by using a multi-plane programming mode
  • Step 102 When it is determined that there is a programming abnormal storage plane among the at least two storage planes, adopt a single-side programming mode, and continue to perform a programming operation on each of the at least two storage planes in sequence.
  • the memory includes a plurality of storage planes, and according to the configuration of the memory, the multiple storage planes can be programmed simultaneously; the multiple storage planes can also be divided into several groups, and the multiple storage planes in each group can be programmed simultaneously. programming.
  • the multi-plane programming mode can be understood as multiple storage planes included in the memory are programmed simultaneously under the control of a controller, and multiple storage planes that are programmed simultaneously can share the same row driver.
  • the multiple storage planes that are programmed simultaneously can be programmed simultaneously in the same row (word line), or can be programmed simultaneously in different rows (word lines).
  • the operation commands of the single-side programming mode and the multi-side programming mode may be different.
  • multi-side programming is a more commonly used programming mode selection.
  • the programming exception can be understood as a programming failure on a storage plane that is being programmed at the same time due to a storage plane defect or other factors.
  • the word line driving voltage is simultaneously applied to the word lines in the corresponding storage plane (the word line driving voltage includes The programming voltage applied to the selected word line and the turn-on voltage applied to the unselected word line); in the program verification process, the program verification voltage is applied to the word lines in the corresponding storage plane at the same time.
  • the programming verification of one storage plane fails, the multiple storage planes that are programmed at the same time are reflected as the programming verification failure.
  • the embodiment of the present application does not limit the specific manner of judging a storage plane with a programming exception among multiple storage planes that are programmed simultaneously.
  • the determining a storage plane with programming exception among the at least two storage planes includes:
  • the preset times can be understood as the maximum program verification times corresponding to a certain data (programming state).
  • a relationship table between the data state and the maximum number of programming verification times can be established first based on empirical values.
  • the maximum number of programming verification times corresponding to the data state can be found by using the data state, that is, the preset number of programming verification times.
  • the maximum number of program verification times is related to the type of data written and the memory cell used for writing data (single-level cell type or multi-level cell type).
  • the type of the memory cell is a three-level cell (TLC) as an example.
  • the three-level cell has 8 data states in total, of which 1 data state (the 0th state) is used as the erase state, and 7 data states ( The first state to the seventh state) are used as the programming state, which adopts the ISPP programming method.
  • 1 data state the 0th state
  • 7 data states The first state to the seventh state
  • the programming state which adopts the ISPP programming method.
  • the preset number of program verification times is related to the number of bits in the data state. Generally, the higher the number of bits in the data state, the greater the preset number of program verification times corresponding to the data state.
  • TLC triple-level cell
  • the programming verification of the corresponding data state is performed. Specifically, all memory cells are programmed first. The first state, and then verify whether all memory cells can reach the first state within the preset number of programming verifications, such as 6 times, if yes, continue to edit the second state of the memory cells whose written data exceeds the first state , and then verify the second state. If the verification is passed, program and verify the corresponding states for the memory cells whose written data is in a higher state in turn, until the verification of the highest state corresponding to the written data is completed. During this period, if there is a verification failure in a certain data state, that is, exceeding the preset number of corresponding programming verifications but still not reaching the corresponding data state, it means that the currently programmed storage plane is a storage plane with abnormal programming.
  • the plane is the storage plane for programming exceptions. It can be understood that the memory has a certain error correction capability.
  • the error correction circuit ECC can be used to correct a certain number of erroneous memory cells. Therefore, for a limited number of program verification errors (within the error correction capability), the current programming will not be determined.
  • the storage planes of the current program it is the storage plane with abnormal programming, but it will not be determined that the storage plane of the current programming is the storage plane with abnormal programming until the number of error verification exceeds the range of error correction capability.
  • a flag can be set to indicate the failure of multi-side programming, and the flag indicating the failure of multi-side programming can be stored in the status register of the memory.
  • the control logic can directly switch to the single-side programming mode for programming.
  • the memory checks the flag of the state register for indicating the failure of multi-side programming the multi-side programming state can be suspended. At this time, the memory system or the host checks the status register when the memory suspends the multi-side programming state and finds that the multi-side programming state Programming is abnormal. At this time, the memory system or the host sends an instruction to instruct the memory to switch to the single-sided programming mode for programming.
  • the single-side programming mode is used to continue to sequentially perform programming on each storage plane of the at least two storage planes.
  • programming operations including:
  • the memory when there is an abnormality in the multi-sided programming mode, the memory can automatically switch from the multi-sided programming mode to the single-sided programming mode, and the memory can also wait for an instruction issued by the host or the memory controller in the memory system to use the single-sided memory. After the instruction of multi-sided programming mode, switch from multi-sided programming mode to single-sided programming mode.
  • the memory system (Memory System) or the host detects the programming failure through the status register.
  • the memory system or the host can take further measures, such as issuing an instruction to dump the data stored in the storage plane where the programming exception exists.
  • the method also includes:
  • the first flag indicates a storage plane with a programming exception among the plurality of storage planes; the first instruction is used to instruct to dump data stored in the storage plane corresponding to the first flag.
  • storage plane A has structural defects, such as leakage
  • storage plane B has no structural defects, if the same voltage source is used to supply storage planes A and B simultaneously
  • the same verification voltage is originally applied to the word lines of storage plane A and B.
  • the verification voltage actually applied to the word line of storage plane A by the voltage source shared across the planes is different from that applied to the word line of storage plane B.
  • the verification voltages on the word lines of the two may be different (the actual applied voltage on the word lines of storage surface A with leakage is lower), and even deviate from the target applied voltage.
  • the target value of the writing threshold voltage Vt is related to the programming voltage.
  • the applied programming voltages of the two storage planes are different, the target voltages of the writing thresholds of the two storage planes are different.
  • the There may be deviations in the written data, and even the written data on the storage surface B also has deviations. That is, even if a memory plane free of structural defects shows a passing multi-plane programming state, the write threshold voltage Vt distribution of the memory cell may be turned off due to incorrect verify conditions caused by cross-plane shared verify voltage deviations. In this case, this potential problem can be mitigated by independent power supply.
  • the method also includes:
  • program verification voltages are respectively applied to the currently programmed memory cells in different memory planes.
  • the method also includes:
  • program verification voltages are respectively applied to memory cells corresponding to different word lines in the same storage plane.
  • different voltage sources are used to power selected WLs in different storage planes during programming voltage verification; on the basis of independently supplying programming verification voltage sources for different storage planes, different voltage sources can be further used
  • the source supplies power to WLs of different rows in the same plane.
  • the independent power supply here refers to the physical isolation of each voltage source.
  • step 102 in an embodiment, it may not be determined which plane has a problem in the multiple storage planes that are programmed simultaneously, but only whether there is at least one of the multiple storage planes that are programmed simultaneously There is a problem with a storage plane.
  • the single-side programming mode is adopted to continue to program each of the multiple storage planes that are programmed simultaneously.
  • the single-side programming mode can be understood as only one storage plane included in the memory is programmed at a time.
  • the row driver only applies the word line driving voltage to a selected storage plane.
  • the programming operation is continued on the second storage plane of the at least two storage planes.
  • the first storage plane and the second storage plane are any one of the aforementioned multiple storage planes programmed simultaneously.
  • each storage plane may be programmed sequentially in random order; Each memory plane is programmed sequentially.
  • the previous programming state is continued.
  • the multi-plane programming mode is used to perform programming operations on the storage plane A, storage plane B, and storage plane C of the memory at the same time; if there is a storage plane with abnormal programming in the multi-plane programming, it is assumed that it is due to the structural nature of the storage plane A. Defects lead to programming exceptions, and storage plane B and storage plane C have no structural defects; when switching to single-side programming mode, continue programming on storage plane A, storage plane B, and storage plane C, assuming that storage plane A is first programmed.
  • the single-side programming mode is used to continue to perform programming operations on each of the at least two storage planes in sequence, including:
  • the first programming voltage is lower than the second programming voltage;
  • the second programming voltage is a programming voltage applied to the first selected word line of the corresponding storage plane when it is determined that there is a storage plane with a programming abnormality;
  • the first selected word line is the selected word line of the corresponding storage plane when it is determined that there is a programming abnormality in the storage plane.
  • the initial programming voltage Vpgm applied to the selected word line can be set to a lower level. That is to say, the programming voltage applied to the selected word line (ie, the first word line) is appropriately lowered when the multi-side programming fails.
  • the down-regulation amount can be determined according to empirical values. It should be noted that when the voltage down-regulation operation is performed, the over-programming can be alleviated to a certain extent.
  • the method also includes:
  • the first programming voltage is applied on the first selected word line of the corresponding storage plane; the first turn-on voltage is applied on the unselected word line in the corresponding storage plane; the first turn-on voltage is smaller than the second Turn-on voltage; the second turn-on voltage is the turn-on voltage applied to the unselected word line of the corresponding storage plane when it is determined that there is a storage plane with abnormal programming.
  • the initial turn-on voltage Vpass applied to the unselected word lines can also be set to a lower level.
  • the Vpgm/Vpass of the word line of the corresponding storage plane can be determined according to the program verification voltage of the corresponding storage plane during multi-plane programming.
  • the method also includes:
  • the multi-side programming mode is used to continue programming operations on the at least two storage planes.
  • the multi-faceted programming mode is always used for programming.
  • the solution proposed by the embodiment of the present application handles the failure of multi-sided programming by suspending the multi-sided programming mode, and then performs programming in the single-sided programming mode.
  • the scheme proposed in the embodiment of the present application can deal with the interference fault of the adjacent surface of the three-dimensional NAND memory and improve the reliability of the three-dimensional NAND memory.
  • the solution proposed by the embodiment of the present application can make the program verification of all storage planes more accurate even when there is a defect on one plane and the voltage bias of the defective storage plane becomes inaccurate due to electric leakage.
  • the solutions proposed in the embodiments of the present application can be used to detect possible defects in a memory cell array.
  • the solution proposed by the embodiment of the present application can reposition the internal deviation when switching to the single-side programming mode, so as to avoid over-programming.
  • An embodiment of the present application also provides a memory, including: multiple storage planes and peripheral circuits coupled to the storage planes; wherein,
  • the peripheral circuit for example, can be realized by a controller, a logic circuit, etc., which can be correspondingly configured with corresponding firmware, for example, by executing the firmware: using a multi-plane programming mode to program at least two of the multiple storage planes The programming operation is performed on the storage planes at the same time; when it is determined that there is a programming abnormal storage plane among the at least two storage planes, a single-side programming mode is adopted to continue to perform programming operations on each of the at least two storage planes in sequence.
  • FIG. 2 is a block diagram of a memory 1 provided by an embodiment of the present application.
  • the memory 1 has a double storage plane structure, and may include peripheral circuits; wherein, the peripheral circuits may include: a control circuit 10, a voltage generating circuit 11, a row driver 12, and a column driver 131, 132; the storage planes include storage planes 141, 142 .
  • the peripheral circuits may include: a control circuit 10, a voltage generating circuit 11, a row driver 12, and a column driver 131, 132; the storage planes include storage planes 141, 142 .
  • a dual plane structure is used in this embodiment, it should be understood that other numbers of planes may also be employed within the scope of the present application.
  • the storage planes 141 and 142 can be programmed at the same time.
  • control circuit 10 can be coupled to the voltage generating circuit 11 , the row driver 12 and the column drivers 131 , 132 .
  • the voltage generating circuit 11 may be coupled to a row driver 12 .
  • the row driver 12 may be coupled to the storage plane 142 via a string selection line SSL2, word lines WL2(1) to WL2(N), and a ground selection line GSL2.
  • Column driver 132 may be coupled to storage plane 142 via bit lines BL2(1) to BL2(M).
  • Each of the storage planes 141, 142 may contain multiple storage blocks, each storage block may contain multiple storage pages, and each storage page may contain multiple storage cells.
  • the storage cells in storage plane 141 can be addressed by word lines WL1(1) to WL1(N) and bit lines BL1(1) to BL1(M), and the storage cells in storage plane 142 can be addressed by word lines WL2(1 ) to WL2(N) and bit lines BL2(1) to BL2(M) for addressing.
  • the control circuit 10 can communicate with a host or a memory controller (Memory Controller) to receive data to be stored in the memory slices 141, 142 and to send data acquired from the memory slices 141, 142.
  • the control circuit 10 may receive commands, addresses or data from a host or a memory controller and generate column address signals Scadr1, Scadr2, row address signals Sradr, and voltage control signals Svc.
  • the voltage generation circuit 11 may generate voltages for read, program, erase, and verify operations. The voltage generated by the voltage generating circuit 11 may exceed the power supply voltage supplied to the memory 1 .
  • Row driver 12 is operable in response to row address signal Sradr from control circuit 10 to select a word line for read, program, erase, and verify operations.
  • the column drivers 131, 132 may operate in response to column address signals Scadr1, Scadr2 from the control circuit 10 to generate bit line signals to select bit lines for read, program, erase and verify operations.
  • the voltage generation circuit 11 can generate a suitable verification voltage
  • the row driver 12 can apply the suitable verification voltage to the selected word line, apply the power supply voltage to the string selection lines SSL1, SSL2, and apply the power supply voltage to the ground selection lines GSL1, GSL2, and the column drivers 131, 132 can apply the ground voltage to the unselected bit lines, and apply the power supply voltage to the selected bit lines of the memory slices 141, 142 respectively so that the selected bit lines Read data from the selected memory cell online. If the data read is incorrect, the control circuit 10 may verify the selected memory cell as fail, and if the data read is correct, the control circuit 10 may verify the selected memory cell as pass.
  • the memory cells may be of single level cell (SLC) type, two level cell (MLC) type, triple level cell (TLC) type, quad level cell (QLC) type, five level cell (PLC) type or higher.
  • the Q possible data states may include erased state S(0) and program states S(1) through S(Q-1), where program state S(1) is the lowest program state and program state S(Q- 1) In the highest program state.
  • the TLC can be programmed to one of 8 possible data states, where program state S(1) is the lowest program state and program state S(7) is the highest program state.
  • a memory cell may be initially set to an erased state S(0), and later, a series of program-verify operations may be performed on the memory cell to program it to a corresponding target program state.
  • a series of program verify operations may start from the lowest program state S(1) and proceed to higher program states until the threshold voltages of selected memory cells reach the corresponding verify voltage levels of the corresponding target program states.
  • the verification voltages can be respectively selected as the minimum threshold voltages of the threshold voltage distribution curves of the program states S(1) to S(Q ⁇ 1).
  • Each program verify operation may include a program operation and a subsequent verify operation.
  • some of the memory cells may be selected and programmed into the program state in a row-by-row fashion from the first row to the Nth row, or from the Nth row to the first row.
  • the peripheral circuit includes: a control circuit and a row driver; the row driver is coupled to the at least two storage planes and is controlled by the control circuit;
  • the row driver is configured to apply a word line driving voltage to at least two storage planes simultaneously performing programming operations in a multi-plane programming mode
  • the row driver here can be understood with reference to the row driver in FIG.
  • a word line drive voltage is applied to one of the memory planes.
  • the word line driving voltage includes a programming voltage applied to a selected word line and a turn-on voltage applied to an unselected word line or becomes a programming pass voltage.
  • the row driver is configured to apply a first programming voltage on the first selected word line of the corresponding storage plane for each storage plane after switching from the multi-side programming mode to the single-side programming mode;
  • the first programming voltage is lower than the second programming voltage;
  • the second programming voltage is a programming voltage applied to the first selected word line of the corresponding storage plane when it is determined that there is a storage plane with a programming abnormality;
  • the first selected word line is the selected word line of the corresponding storage plane when it is determined that there is a programming abnormality in the storage plane.
  • the row driver is configured such that when a first programming voltage is applied to a first selected word line of the corresponding storage plane; a first conductive voltage is applied to an unselected word line of the corresponding storage plane.
  • the conduction voltage; the first conduction voltage is less than the second conduction voltage; the second conduction voltage is the conduction applied to the unselected word line of the corresponding storage plane when it is determined that there is a storage plane with abnormal programming pass voltage.
  • control circuit 10 controls the voltage generating circuit to output a lower initial programming voltage/initial turn-on voltage (Vpgm/Vpass), and controls the row driver to apply Vpgm only to the selected word line of a selected storage plane, and Vpass is applied to unselected word lines.
  • Vpgm/Vpass initial programming voltage/initial turn-on voltage
  • the peripheral circuit is configured as:
  • the peripheral circuit further includes: a plurality of program verification voltage generators; each of the plurality of program verification voltage generators is respectively coupled to one of the at least two storage planes, and controlled by the control circuit;
  • the plurality of program verification voltage generators are configured to respectively apply program verification voltages to currently programmed memory cells in different storage planes.
  • each of the plurality of program verification voltage generators is respectively coupled to a word line of one of the at least two storage planes
  • the plurality of program verification voltage generators are configured to respectively apply program verification voltages to memory cells corresponding to different word lines in the same storage plane.
  • the plurality of program verification voltage generators belong to sub-circuits of the voltage generating circuit in FIG. 2 . It should be noted that when the multiple program verification voltage generators are applied to the word lines of different storage planes through the row driver, they can still maintain physical isolation.
  • the peripheral circuit further includes: a register configured to save the first flag when it is determined that there is a programming abnormal storage plane among the multiple storage planes;
  • the peripheral circuit is further configured to: when receiving the first instruction, use other storage planes in the memory to store data stored in the storage plane allocated to the programming exception; The data stored in the corresponding storage plane is dumped.
  • the register may be a status register.
  • control circuit can decide whether to switch the programming mode by itself, and after the single-sided programming mode ends, the memory system or the host detects the programming failure through the status register. In this case, the memory system or the host can Taking further measures, such as issuing an instruction to dump the data stored in the storage plane where programming exceptions exist.
  • the memory when the memory sees the flag of the status register indicating the failure of multi-sided programming, it can also suspend the multi-sided programming state. At this time, the memory system or the host checks the status register when the memory suspends the multi-sided programming state and finds that multi-sided programming Abnormal, at this time, the memory system or the host sends an instruction to instruct the memory to switch to the single-sided programming mode for programming.
  • the memory includes three-dimensional NAND type memory.
  • FIG. 3 is a schematic diagram of an implementation flow of the method for operating a memory according to the embodiment of the present application. As shown in Figure 3, the method includes the following steps:
  • Step 301 start;
  • the memory is ready for initialization and other preparations.
  • control circuit When the control circuit receives an instruction from the host or the memory controller to perform multi-faceted programming operations, go to step 302 .
  • Step 302 programming using multi-faceted programming mode
  • the peripheral circuit uses a multi-plane programming mode to program multiple storage planes in the memory at the same time.
  • step 302 After step 302, go to step 303.
  • Step 303 judging whether there is a programming exception on the storage plane
  • control circuit judges whether there is programming abnormality on the storage surface according to whether the number of times of the programming voltage exceeds a preset number of times.
  • the program verification times for different PV levels can be tracked. Check if the number of programming verifications exceeds the preset number of times. If the number of verification times of a certain PV level exceeds the preset number, it indicates that there is a programming exception on the storage plane. At this time, a structural defect growing on a certain storage surface may be one of the causes of abnormal programming.
  • step 304 When the judgment result indicates that there is an abnormal surface, go to step 304; when the judgment result shows that there is no abnormal surface, go to step 305.
  • Step 304 Set a flag to notify the multi-faceted programming mode to be suspended
  • a flag is set to indicate the multi-side programming failure, and the flag indicating the multi-side programming failure can be stored in the status register of the memory.
  • the memory suspends the multi-side programming operation, it further transitions to the single-side programming operation.
  • the host or memory system can detect the flag in the status register and perform corresponding follow-up processing. After step 304, go to step 306.
  • peripheral circuit continues to use the multi-plane programming mode to program multiple storage planes in the memory at the same time.
  • Step 306 modify Vpgm/Vpass to a lower voltage
  • control circuit controls the voltage generation circuit to set Vpgm/Vpass to a lower level, and at the same time apply it to the word line of the storage plane by using the row driver.
  • Step 307 programming in single-sided mode
  • the peripheral circuit sequentially programs each of the multiple storage planes in a single-side programming mode.
  • a program pass/program fail is generated at a single-side level when a program operation is performed in a single-side mode.
  • step 306 is actually executed when each storage plane in step 307 starts programming.
  • Step 308 end.
  • the embodiment of the present application also provides a memory system 1000, as shown in Figure 4, the memory system 1000 includes:
  • a storage controller 2 which is coupled to the storage 1.
  • the peripheral circuit is configured to receive a second instruction; in response to the second instruction, use a multi-plane programming mode to simultaneously perform programming operations on at least two storage planes among the plurality of storage planes ; When it is determined that there is a programming abnormal storage plane among the at least two storage planes, suspend the programming operation and save the first flag;
  • the memory controller is configured to issue a third instruction based on the first flag
  • the peripheral circuit is configured to receive a third instruction; in response to the third instruction, adopt a single-side programming mode and continue to perform programming operations on each of the at least two storage planes in sequence.
  • the second instruction is used to instruct the memory 1 to perform a programming operation in a multi-side programming mode
  • the third instruction is used to instruct the memory 1 to perform a programming operation in a single-side programming mode.
  • the memory controller 2 can be used to control the memory 1 to execute erasing, reading or writing operations, and to decode, analyze or perform operations on instructions issued or received in the memory.
  • the memory controller 2 can be coupled with the memory 1 through a memory I/F (InterFace).
  • the first flag may be stored in a state register corresponding to each memory 1 .
  • the memory controller 2 accesses the state register corresponding to the memory 1, and the memory controller 2 sends a third instruction to the memory whose programming is suspended according to the first flag, and the memory 1 that suspends programming receives the third instruction After the command, use the single-sided programming mode for programming.

Abstract

本申请实施例提供了一种存储器及其操作方法、存储器系统，其中，存储器的操作包括：采用多面编程模式对存储器的多个存储面中的至少两个存储面同时进行编程操作；确定所述至少两个存储面中存在编程异常的存储面时，采用单面编程模式，继续对所述至少两个存储面中的每个存储面依次进行编程操作。

Description

存储器及其操作方法、存储器系统 技术领域
本申请实施例涉及半导体领域，特别涉及一种存储器及其操作方法、存储器系统。
背景技术
根据存储器的存储单元阵列的结构配置，可以将存储器分为单存储面(Plane)类型和多存储面类型。单存储面类型的存储器包括一个存储面；多存储面类型的存储器包括多个存储面。对于多存储面类型的存储器，可以采用多面编程模式同时对存储器的两个或更多个存储面进行编程，以提高编程效率。
采用多面编程模式固然能提高编程效率，但不可避免的会存在邻面干扰的问题，例如，采用多面编程模式的情况下，如果一个存储面发生编程失败，经常会在同时编程的其它多个存储面上发生编程失败。因此，亟待提供一种编程方法，在保证一定的编程效率的前提下，减小邻面干扰带来的不利影响。
发明内容
为解决现有存在的技术问题的一个或多个，本申请实施例提出一种存储器及其操作方法、存储器系统。
本申请实施例提供了一种存储器的操作方法，包括：
采用多面编程模式对存储器的多个存储面中的至少两个存储面同时进行编程操作；
确定所述至少两个存储面中存在编程异常的存储面时，采用单面编程 模式，继续对所述至少两个存储面中的每个存储面依次进行编程操作。
上述方案中，所述采用单面编程模式，继续对所述至少两个存储面中的每个存储面依次进行编程操作，包括：
在采用单面编程模式时，针对每一存储面，在相应存储面的第一选中字线上施加第一编程电压；
其中，所述第一编程电压小于第二编程电压；所述第二编程电压为确定存在编程异常的存储面时，施加在所述相应存储面的所述第一选中字线上的编程电压；所述第一选中字线为确定存在编程异常的存储面时，相应存储面的选中字线。
上述方案中，所述方法还包括：
在所述相应存储面的第一选中字线上施加第一编程电压时；在所述相应存储面中未选中的字线上施加第一导通电压；所述第一导通电压小于第二导通电压；所述第二导通电压为确定存在编程异常的存储面时，施加在所述相应存储面的未选中字线上的导通电压。
上述方案中，所述确定所述至少两个存储面中存在编程异常的存储面，包括：
检测所述至少两个存储面中当前编程的存储单元的编程验证次数；
当所述编程验证次数超出当前待写入数据对应的预设次数时，确定所述至少两个存储面中存在编程异常的存储面。
上述方案中，所述方法还包括：
利用不同的电压源，分别给不同存储面中的当前编程的存储单元施加编程验证电压。
上述方案中，所述方法还包括：
利用不同的电压源，分别给同一存储面中的不同字线对应的存储单元施加编程验证电压。
上述方案中，所述确定所述至少两个存储面中存在编程异常的存储面时，采用单面编程模式，继续对所述至少两个存储面中的每个存储面依次进行编程操作，包括：
确定所述至少两个存储面中存在编程异常的存储面时，直接采用单面编程模式，继续对所述至少两个存储面中的每个存储面依次进行编程操作；或者，
确定所述至少两个存储面中存在编程异常的存储面时，暂停编程操作；在接收到第二指令后采用单面编程模式，继续对所述至少两个存储面中的每个存储面依次进行编程操作。上述方案中，所述方法还包括：
确定所述至少两个存储面中存在编程异常的存储面时，保存第一标记；
接收到第一指令时，利用所述存储器中的其它存储面存储分配给存在编程异常的存储面中存储数据；所述第一指令用于指示将第一标记中对应的存储面中存储数据进行转存。
上述方案中，所述采用单面编程模式继续对所述至少两个存储面中的每个存储面依次进行编程操作，包括：
对所述至少两个存储面中的第一存储面继续进行编程操作；
确定所述第一存储面编程失败或者编程完成时，对所述至少两个存储面中的第二存储面继续进行编程操作。
上述方案中，所述方法还包括：
确定所述至少两个存储面中不存在编程异常的存储面时，采用所述多面编程模式，继续对所述至少两个存储面进行编程操作。
本申请实施例提供了一种存储器，包括：多个存储面及与所述存储面耦接的外围电路；其中，
所述外围电路配置为，采用多面编程模式对所述多个存储面中的至少两个存储面同时进行编程操作；确定所述至少两个存储面中存在编程异常 的存储面时，采用单面编程模式，继续对所述至少两个存储面中的每个存储面依次进行编程操作。
上述方案中，所述外围电路包括：控制电路和行驱动器；所述行驱动器与所述至少两个存储面均耦接，并被所述控制电路所控制；
所述行驱动器配置为，在多面编程模式下，对同时进行编程操作的至少两个存储面均施加字线驱动电压；
所述行驱动器配置为，在单面编程模式下，对选择的一个存储面施加字线驱动电压。
上述方案中，所述行驱动器配置为，在由多面编程模式切换为单面编程模式后，针对每一存储面，在相应存储面的第一选中字线上施加第一编程电压；
其中，所述第一编程电压小于第二编程电压；所述第二编程电压为确定存在编程异常的存储面时，施加在所述相应存储面的所述第一选中字线上的编程电压；所述第一选中字线为确定存在编程异常的存储面时，相应存储面的选中字线。
上述方案中，所述行驱动器配置为，在所述相应存储面的第一选中字线上施加第一编程电压时；在所述相应存储面中未选中的字线上施加第一导通电压；所述第一导通电压小于第二导通电压；所述第二导通电压为确定存在编程异常的存储面时，施加在所述相应存储面的未选中字线上的导通电压。
上述方案中，所述外围电路配置为：
检测所述至少两个存储面中当前编程的存储单元的编程验证次数；
当所述编程验证次数超出当前待写入数据对应的预设次数时，确定所述至少两个存储面中存在编程异常的存储面。
上述方案中，所述外围电路还包括：多个编程验证电压生成器；多个 编程验证电压生成器中的每个分别与所述至少两个存储面中的一个存储面耦接，并被所述控制电路所控制；
所述多个编程验证电压生成器配置为：分别给不同存储面中的当前编程的存储单元施加编程验证电压。
上述方案中，所述多个编程验证电压生成器中的每个分别与所述至少两个存储面中的一个存储面的一条字线耦接；
所述多个编程验证电压生成器配置为：分别给同一存储面中的不同字线对应的存储单元施加编程验证电压。
上述方案中，所述外围电路配置为，确定所述至少两个存储面中存在编程异常的存储面时，直接采用单面编程模式，继续对所述至少两个存储面中的每个存储面依次进行编程操作；
或者，
所述外围电路配置为，确定所述至少两个存储面中存在编程异常的存储面时，暂停编程操作；在接收到第二指令后采用单面编程模式，继续对所述至少两个存储面中的每个存储面依次进行编程操作。
上述方案中，所述外围电路还包括：寄存器，配置为确定所述多个存储面中存在编程异常的存储面时，保存第一标记；
所述外围电路配置为：接收到第一指令时，利用所述存储器中的其它存储面存储分配给存在编程异常的存储面中存储数据；所述第一指令用于指示将第一标记中对应的存储面中存储数据进行转存。
上述方案中，所述存储器包括三维NAND型存储器。
本申请实施例还提供了一种存储器系统，包括：
一个或多个如上述实施例中所述的存储器；以及
存储控制器，其与所述存储器耦接。
上述方案中，所述方法还包括：
所述外围电路配置为，接收到第二指令；响应于所述第二指令，采用多面编程模式对所述多个存储面中的至少两个存储面同时进行编程操作；确定所述至少两个存储面中存在编程异常的存储面时，暂停编程操作并保存第一标记；
所述存储器控制器配置为，根据所述第一标记，发出第三指令；
所述外围电路配置为，接收到第三指令；响应于所述第三指令，采用单面编程模式，继续对所述至少两个存储面中的每个存储面依次进行编程操作。
本申请实施例中，在采用多面编程模式对多个存储面同时编程出现问题时，并没有一直停留在该编程模式中，而是采用单面编程模式继续对该多个存储面中的每个存储面依次进行编程操作。也就是说，本申请实施例在接收到编程操作的指令时，默认采用多面编程模式进行编程操作，从而能够保证一定的编程效率；当在确定存在编程异常时，切换到单面编程模式继续进行编程，如此，能够将编程异常限制在本身存在异常的存储面内，减轻编程异常对其它正常存储面的影响，即减小邻面干扰带来的不利影响。
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一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制。
图1为本申请实施例提供的一种存储器的操作方法的实现流程示意图一；
图2为本申请实施例提供的一种存储器的结构示意图；
图3为本申请实施例提供的一种存储器的操作方法的实现流程示意图二；
图4为本申请实施例提供的一种存储器系统的结构示意图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
本申请实施例中的存储器包括但不限于三维NAND型存储器，为了便于理解，以三维NAND型存储器为例进行说明。但是应当理解，本申请构思的实施例不限于此配置，而是还可应用于二维NAND存储器。另外，在不脱离本申请的范围的情况下，本申请可适用于其它非易失性存储器件，例如，电可擦除可编程只读存储器(EEPROM，Electrically Erasable Programmable Read-Only Memory)、NOR型闪存存储器、相变随机(PRAM，Chase Random Access Memory)、磁性随机存储器(MRAM，Magnetoresistive Random Access Memory)、阻变随机存储器(RRAM，Resistive Random Access Memory)、铁电随机存储器(FRAM，Ferroelectric Random Access Memory)等。
实际应用中，所述三维NAND型存储器可以包括存储单元阵列和外围电路；其中，所述存储单元阵列多个存储面(Plane)，每个存储面包括多个存储块(Block)，每个存储块包括多个存储页(Page)，存储页是读取和写(即编程)的最小单位，而存储块是擦除的最小单位。
所述外围电路可以包括配置为便于存储器实现读取操作、写操作、擦除操作等各种操作的任何合适的数字、模拟和/或混合信号电路。例如，外围电路可以包括控制逻辑(例如控制电路或控制器)、数据缓冲器、解码器(解码器也可以称为译码器)、驱动器及读写电路等。当控制逻辑收到读写操作命令及地址数据时，在控制逻辑的作用下，解码器可以基于解码的地 址将从驱动器施加的相应电压到相应的位线、字线上，以实现数据的读写，并通过数据缓冲器与外部进行数据交互。
存储器系统中的三维NAND型存储器存在多种缺陷，有些缺陷可以在出厂时检测到，有些缺陷是在出厂后随着使用环境的变化而暴露出来的。实际应用中，三维NAND型存储器的某些存储单元阵列中可能存在结构性薄弱点，这些结构性薄弱点可能需要较长的时间或较多次编程操作、擦除操作后才能发展并成为缺陷。例如，三维NAND型存储器的存储单元阵列在编程和擦除循环过程中需要经受高压应力，三维NAND型存储器的某些存储单元阵列中薄弱结构会在循环后发展为缺陷。
三维NAND型存储器出现缺陷时，可能出现数据丢失的现象。如果缺陷为字线(WL，Word Line)短路，则整个WL对应的存储单元中的数据均可能被破坏。由于每个WL可以对应多个字符串的存储单元，基于此，可能出现大量数据丢失的现象，从而给存储器系统带来故障。这种类型的故障一般被定义为三维NAND型存储器的可靠性故障，该故障在现场可能会进一步导致存储器系统的故障。
在编程状态失败(PSF，Programming Status Failed)的情况下，存储器系统可以使用独立冗余磁盘阵列(RAID，Redundant Arrays of Independent Disks)来恢复丢失的数据。一般存储器系统采用面级别的RAID，面级别的RAID只能恢复一个存储面的故障。如果多个面出现编程失败，存储器系统将无法恢复数据。对于此类故障，存储器系统可以在管芯(Die)级别进行RAID，但存储器系统的配置成本将会增加。
在三维NAND型存储器中，内部电压偏置电源通常在编程操作期间在不同面之间共享，这是为了节省电路面积和功耗。如果一个存储面有缺陷，则共享内部电压偏置电源的其它存储面可能均无法达到目标电平，因此即使只有一个面有物理缺陷，也经常会在多个面上发生编程失败，这就是前 述的邻面干扰(NPD，Neighbor Plane Disturb)。显然，邻面干扰会带来如前述的数据丢失等不利影响。基于此，如果物理缺陷仅存在于一个存储面中，则希望故障仅发生在该缺陷存储面中。
本申请实施例提出一种存储器(memory device)的操作方法，图1为本申请实施例提供的一种存储器的操作方法的实现流程示意图，所述方法包括：
步骤101：采用多面编程模式对存储器的多个存储面中的至少两个存储面同时进行编程操作；
步骤102：确定所述至少两个存储面中存在编程异常的存储面时，采用单面编程模式，继续对所述至少两个存储面中的每个存储面依次进行编程操作。
这里，所述存储器包括多个存储面，根据存储器的配置情况，多个存储面可以同时进行编程；多个存储面也可以分为几个小组，每个组内的多个存储面可以同时进行编程。
在步骤101中，所述多面编程模式可以理解为存储器中包含的多个存储面在一个控制器的控制作用下同时进行编程，同时进行编程的多个存储面可以共用同一个行驱动器。实际应用中，同时进行编程的多个存储面，根据行驱动器的配置情况，可以是相同行(字线)同时进行编程；也可以是不同行(字线)同时进行编程。
实际应用中，单面编程模式与多面编程模式的操作命令可以不同。为了提高存储器的编程速度，多面编程是更常用的编程模式选择。
在步骤102中，所述编程异常可以理解为由于存储面缺陷或其它因素导致同时进行编程的某个存储面出现编程失败。
实际应用中，对于同时进行编程的多个存储面，针对每个存储面，在编程的过程中，是同时对相应的存储面中的字线均施加字线驱动电压(这 里字线驱动电压包括施加在选中字线上的编程电压和施加在未选中字线上的导通电压)；在编程验证的过程中，是同时对相应的存储面中的字线均施加编程验证电压。当一个存储面的编程验证未通过，同时进行编程的多个存储面均体现为编程验证未通过。
实际应用中，本申请实施例不限制判断同时进行编程的多个存储面中存在编程异常的存储面的具体方式。
在一些实施例中，所述确定所述至少两个存储面中存在编程异常的存储面，包括：
检测所述至少两个存储面中当前编程的存储单元的编程验证次数；
当所述编程验证次数超出当前待写入数据对应的预设次数时，确定所述至少两个存储面中存在编程异常的存储面。
这里，所述预设次数可以理解为某数据(编程态)对应的最大编程验证次数。
实际应用中，可以根据经验值，先建立数据态与最大编程验证次数的关系表。在该表中，利用数据态可以查到该数据态对应的最大编程验证次数即编程验证预设次数。实际应用中，最大编程验证次数与写入数据及用于写入数据的存储单元的类型(单级单元类型或多级单元类型)相关。
示例性地，以存储单元的类型为三级单元(TLC)为例进行说明，三级单元共有8个数据态，其中1个数据态(第0态)作为擦除态，7个数据态(第1态至第7态)作为编程态，其采用ISPP编程方式。可以根据实际经验值得到编程到达第1态，大概需要施加几次编程脉冲，即进行几次编程验证，如编程到达第1态，需要在6次编程验证之内完成；编程到达第2态，需要在9次编程验证之内完成；一般编到越高的数据态，需要越多的编程验证次数。也就是说，编程验证预设次数与数据态的位数相关，一般数据态的位数越高，对对应该数据态的编程验证预设次数越大。
实际应用中，在进行编程操作时，对于同时进行编程的多个存储面中的任一个存储面，在一些实施例中，可以对一个存储页中所有的存储单元在编完一个数据态时，就进行相应数据态的编程验证；在另一些实施例中，在一个存储页编程完成后，对该存储页中的每个存储单元的编程状态从低态到高态依次进行编程验证。
仍以存储单元的类型为三级单元(TLC)为例进行说明。在对存储页中的每个存储单元进行编程验证时，对个存储页中所有的存储单元在编完一个数据态时，就进行相应数据态的编程验证，具体地，先对所有存储单元编第1态，然后对所有的存储单元均验证是否能够在编程验证预设次数如，6次内到达第1态，如果可以，则继续对写入数据超过第1态的存储单元编第2态，之后进行第2态的验证，如果验证通过，依次对写入数据为更高态的存储单元进行编程及相应态的验证，直到写入数据对应的最高态验证完成。期间，如果在某个数据态出现验证失败，即超出相应编程验证预设次数但仍未到达相应的数据态，则表示当前编程的存储面中为编程异常的存储面。
需要说明的是，在一实施例中，在进行编程验证时，并不是当一个存储页中任意一个存储单元的编程验证次数超出了，但还没到达指定的数据态时就确定当前编程的存储面中为编程异常的存储面。可以理解的是，存储器具备一定的纠错能力，如可以利用误差校正电路ECC纠正一定数量错误存储单元，因此，对于有限数量内(纠错能力范围内)的编程验证错误，不会确定当前编程的存储面中为编程异常的存储面，而是等到错误验证个数超出纠错能力范围才会确定当前编程的存储面中为编程异常的存储面。
实际应用中，可以设置标志以指示多面编程失败，指示多面编程失败的标志可以存放在存储器的状态寄存器里。在一实施例中，当存储器查看到状态寄存器的用于指示多面编程失败的标志时，控制逻辑可以直接切换 到单面编程模式进行编程。在另一些实施例中，当存储器查看到状态寄存器的用于指示多面编程失败的标志时，可以暂停多面编程状态，此时存储器系统或主机在存储器暂停多面编程状态时查看状态寄存器并发现，多面编程异常，此时由存储器系统或主机发出指令，指示存储器切换到单面编程模式进行编程。
基于此，在一些实施例，所述确定所述至少两个存储面中存在编程异常的存储面时，采用单面编程模式，继续对所述至少两个存储面中的每个存储面依次进行编程操作，包括：
确定所述至少两个存储面中存在编程异常的存储面时，直接采用单面编程模式，继续对所述至少两个存储面中的每个存储面依次进行编程操作；
或者，
确定所述至少两个存储面中存在编程异常的存储面时，暂停编程操作；在接收到第二指令后采用单面编程模式，继续对所述至少两个存储面中的每个存储面依次进行编程操作。
也就是说，实际应用中，在多面编程模式存在异常时，存储器可以自动进行由多面编程模式到单面编程模式的切换，存储器也可以等待主机或存储器系统中存储器控制器发出的指示存储器使用单面编程模式的指令后，再由多面编程模式切换到单面编程模式。
实际应用中，在单面编程模式结束后，存储器系统(Memory System)或主机通过状态寄存器检测到该编程失败情况。在这种情况下，存储器系统或主机可以采取进一步措施，如发出指令指示将存在编程异常的存储面中存储数据进行转存。
基于此，在一些实施例中，所述方法还包括：
确定所述多个存储面中存在编程异常的存储面时，保存第一标记；
接收到第一指令时，利用所述存储器中的其它存储面存储分配给存在 编程异常的存储面中存储数据；所述第一指令用于指示将第一标记中对应的存储面中存储数据进行转存。
这里，所述第一标记表征所述多个存储面中存在编程异常的存储面；所述第一指令用于指示将第一标记中对应的存储面中存储数据进行转存。实际应用中，当同时进行编程的多个存储面中，存储面A存在结构性缺陷，如存在漏电，而存储面B无结构性缺陷时，若利用同一个电压源给存储面A、B同时进行供电时，本来预备在存储面A、B的字线上施加相同的验证电压，然而，该跨面共享的电压源实际施加在存储面A的字线上的验证电压与施加在存储面B的字线上的验证电压可能不同(存在漏电的存储面A的字线上的实际施加电压更低)，甚至均与目标施加电压产生偏移。可以理解的是，写入阈值电压Vt的目标值与编程电压相关，当两个存储面的被施加的编程电压不同时，两个存储面写入阈值的目标电压不同，这时存储面A的写入数据可能存在偏差，甚至连存储面B的写入数据也存在偏差。也就是说，即使无结构性缺陷的存储面显示通过多面编程状态，存储单元的写入阈值电压Vt分布也可能由于跨面共享验证电压偏差导致的不正确验证条件而关闭。此时，可以通过独立供电缓解该潜在的问题。
在一些实施例中，所述方法还包括：
利用不同的电压源，分别给不同存储面中的当前编程的存储单元施加编程验证电压。
其中，在一些实施例中，所述方法还包括：
利用不同的电压源，分别给同一存储面中的不同字线对应的存储单元施加编程验证电压。
实际应用中，在编程电压验证期间，利用不同的电压源为不同存储面中选定的WL进行供电；在将不同存储面的编程验证电压源独立供应的基础上，还可以进一步利用不同的电压源为同一存储面中不同的行的WL进 行供电。需要说明的是，这里的独立供电指的是各电压源存在物理隔离。
可以理解的是，这样可以使得不同存储面上的编程验证电压独立，从而确保无结构性缺陷的存储面的编程验证结果是准确的。
需要说明的是，在步骤102中，在一实施例中，可以不判断出同时进行编程的多个存储面具体是哪个面存在问题，而只判断同时进行编程的多个存储面中是否存在至少某一个存储面存在问题。
本申请实施例中，在确定存在编程异常的存储面时，采用单面编程模式，继续对同时进行编程的多个存储面中的每个面依次进行编程。这里，所述单面编程模式可以理解为一次仅对存储器中包含的一个存储面进行编程。在单面编程模式下，行驱动器仅对选择的一个存储面施加字线驱动电压。
在一些实施例中，所述采用单面编程模式继续对所述至少两个存储面中的每个存储面依次进行编程操作，包括：
对所述至少两个存储面中的第一存储面继续进行编程操作；
确定所述第一存储面编程失败或者编程完成时，对所述至少两个存储面中的第二存储面继续进行编程操作。
这里，所述第一存储面和第二存储面均为前述同时进行编程的多个存储面中的任一中存储面。
实际应用中，在切换为单面编程模式后，对于所述至少两个存储面中的每个存储面可以按照随机先后的次序分别对每个存储面依次进行编程；也可以按照指定的顺序分别对每个存储面依次进行编程。对于每一个存储面在进行编程时，均继续之前的编程状态。
示例性地，采用多面编程模式对存储器的存储面A、存储面B、存储面C同时进行编程操作；检测到多面编程中存在编程异常的存储面，此时假设是由于存储面A的结构性缺陷导致该编程异常，存储面B、存储面C无 结构性缺陷；在切换到单面编程模式时，对存储面A或存储面B、存储面C继续进行编程，假设先对存储面A进行编程，从存储面A的页缓存器(PB，Page Buffer)中获取用于继续编程的数据，如存储单元的类型为三级存储单元(TLC)，多面验证失败时正在编第一字线中的某些存储单元的第2态，则继续对第一字线中的某些存储单元的第2态进行编程，由于存储面A存在缺陷，存储面A最终还是会以面级别的编程失败告终，在存储面A显示编程失败时(此时可以确定存在缺陷的存储面为存储面A)，开始对存储面B进行编程，从存储面B的PB中获取用于继续编程的数据，存储面B编程完成时，再开始对存储面C进行编程，从存储面C的PB中获取用于继续编程的数据，直到存储面C编程完成。
需要说明的是，对于存在缺陷的存储面A，若存储面A的PB中会一直保存该次编程所有待写入数据，则可以将A中写入失败的数据转到其他的不存在缺陷的存储面中；若存储面A的PB仅动态保存该次编程的待写入数据，则可以利用前述的RAID进行数据恢复，并将A中恢复的和未写入的数据转到其他的不存在缺陷的存储面中。
实际应用中，利用多面编程模式同时进行编程的多个存储面利用同一行驱动器进行字线驱动电压的提供，然而当同时进行编程的多个存储面中存在有缺陷的存储面，如存在有漏电的面时，电源产生的电压比实际施加在存储面字线上的电压高，在切换为单面编程后，漏电流的分布发生变化，过高的电源产生的电压可以会导致过编程的问题。
基于此，在一些实施例中，所述采用单面编程模式，继续对所述至少两个存储面中的每个存储面依次进行编程操作，包括：
在采用单面编程模式时，针对每一存储面，在相应存储面的第一选中字线上施加第一编程电压；
其中，所述第一编程电压小于第二编程电压；所述第二编程电压为确 定存在编程异常的存储面时，施加在所述相应存储面的所述第一选中字线上的编程电压；所述第一选中字线为确定存在编程异常的存储面时，相应存储面的选中字线。
实际应用中，对于每一存储面在进行继续编程时，可以将施加在选中字线上的起始编程电压Vpgm设置为较低的级别。也就是说，将多面编程失败时施加在选中字线(即第一字线)上的编程电压进行适当的下调。实际应用中，该下调的量可以根据经验值进行确定。需要说明的是，当进行了电压下调操作时，就能在一定程度上缓解过编程。
其中，在一些实施例中，所述方法还包括：
在所述相应存储面的第一选中字线上施加第一编程电压时；在所述相应存储面中未选中的字线上施加第一导通电压；所述第一导通电压小于第二导通电压；所述第二导通电压为确定存在编程异常的存储面时，施加在所述相应存储面的未选中字线上的导通电压。
实际应用中，对于每一存储面在进行继续编程时，还可以将施加在未选中字线上的起始导通电压Vpass设置为较低的级别。
在一些实施例中，可以根据多面编程时相应存储面的编程验证电压的确定所述相应存储面字线的Vpgm/Vpass。
在一些实施例中，所述方法还包括：
确定所述至少两个存储面中不存在编程异常的存储面时，采用所述多面编程模式，继续对所述至少两个存储面进行编程操作。
也就是说，在多面编程不存在异常时，一直采用多面编程模式进行编程。
本申请实施例所提出的方案，通过暂停多面编程模式来处理多面编程的失败，然后在单面编程模式下进行编程。本申请实施例所提出的方案可以处理三维NAND型存储器相邻面干扰故障并提高三维NAND型存储器的 可靠性。本申请实施例所提出的种方案，即使在一个面存在缺陷并且由于漏电导致缺陷存储面电压偏置变得不准确时，也可以使所有存储面的编程验证更加准确。本申请实施例所提出的方案可以用来检测存储单元阵列中可能存在的缺陷情况。本申请实施例所提出的方案，可以在切换为单面编程模式时重新定位内部偏差，以避免过度编程。
本申请实施例还提供一种存储器，包括：多个存储面及与所述存储面耦接的外围电路；其中，
所述外围电路，例如可以通过控制器、逻辑电路等实现，其例如可以对应地配置有相应的固件，通过例如执行固件来实现：采用多面编程模式对所述多个存储面中的至少两个存储面同时进行编程操作；确定所述至少两个存储面中存在编程异常的存储面时，采用单面编程模式，继续对所述至少两个存储面中的每个存储面依次进行编程操作。
图2是本申请的实施例提供的一种存储器1的组成框图。存储器1具有双存储面结构，并且可以包括外围电路；其中，所述外围电路可以包括：控制电路10、电压生成电路11、行驱动12、列驱动器131、132；存储面包括存储面141、142。尽管在该实施例中使用了双存储面结构，但是应当理解，在本申请的范围内也可以采用其它数量的存储面。在采用多面编程模式时，可以同时对存储面141、142进行编程。
实际应用中，控制电路10可以耦接到电压生成电路11、行驱动器12和列驱动器131、132。电压生成电路11可以耦接到行驱动器12。行驱动器12可以经由串选择线SSL1、字线WL1(1)到WL1(N)以及接地选择线GSL1耦接到存储面141，N是正整数，例如，N＝128。行驱动器12可以经由串选择线SSL2、字线WL2(1)至WL2(N)以及接地选择线GSL2耦接到存储面142。列驱动器131可以经由位线BL1(1)到BL1(M)耦接到存储面141，M是正整数，例如，M＝131072。列驱动器132可以经由 位线BL2(1)至BL2(M)耦接到存储面142。存储面141、142中的每一个可以包含多个存储块，每个存储块可以包含多个存储页，每个存储页可以包含多个存储单元。存储面141中的存储单元可以通过字线WL1(1)到WL1(N)以及位线BL1(1)至BL1(M)进行寻址，存储面142中的存储单元可以通过字线WL2(1)至WL2(N)以及位线BL2(1)到BL2(M)进行寻址。
控制电路10可以与主机、或存储器控制器(Memory Controlller)进行通信以接收数据以便存储在存储片141、142中并发送从存储片141、142获取的数据。控制电路10可以从主机或存储器控制器接收命令、地址或数据并且生成列地址信号Scadr1、Scadr2、行地址信号Sradr以及电压控制信号Svc。响应于来自控制电路10的电压控制信号Svc，电压生成电路11可以生成用于读取、编程、擦除和验证操作的电压。电压生成电路11生成的电压可能超过提供给存储器1的电源电压。行驱动器12可以响应于来自控制电路10的行地址信号Sradr而操作，以便选择用于读取、编程、擦除和验证操作的字线。列驱动器131、132可以响应于来自控制电路10的列地址信号Scadr1、Scadr2而操作，以便生成位线信号以选择用于读取、编程、擦除和验证操作的位线。
在编程操作中，电压生成电路11可以使用电源电压(例如，3.3V)来生成编程电压(例如，20V)和编程通过电压(例如，10V)，行驱动器12可以向所选择的字线施加具有编程电压的幅度的编程脉冲，向未选定的字线施加编程通过电压，向串选择线SSL1、SSL2施加电源电压，以及向接地选择线GSL1、GSL2施加接地电压，并且列驱动器131、132可以向所选择的位线施加接地电压(例如，0V)，以及向未选定的位线施加电源电压。在验证操作中，电压生成电路11可以生成合适的验证电压，行驱动器12可以将合适的验证电压施加到所选择的字线，将电源电压施加到串选择线 SSL1、SSL2，并且将电源电压施加到接地选择线GSL1、GSL2，并且列驱动器131、132可以将接地电压施加到未选择的位线，并且将电源电压分别施加到存储片141、142的被选择的位线以便在所选择的位线上从所选择的存储单元中读取数据。如果数据读取是不正确的，则控制电路10可以将所选择的存储单元验证为失败，而如果数据读取是正确的，则控制电路10可以将所选择的存储单元验证为通过。
存储单元可以是单级单元(SLC)类型、二级单元(MLC)类型、三级单元(TLC)类型、四级单元(QLC)类型、五级单元(PLC)类型或更高级别类型。每个存储单元可以保持Q个可能的数据状态之一，其中，Q是等于或大于2的正整数，例如，对于SLC，Q＝2，对于MLC，Q＝4，对于TLC，Q＝8，对于QLC，Q＝16，并且对于PLC，Q＝32。Q个可能的数据状态可以包括擦除状态S(0)和程序状态S(1)至S(Q-1)，其中，程序状态S(1)是最低程序状态，而程序状态S(Q-1)处于最高程序状态。在一个示例中，TLC可以被编程为8种可能的数据状态之一，其中，程序状态S(1)是最低程序状态，而程序状态S(7)是最高程序状态。
存储单元可以起初设置为擦除状态S(0)，并且稍后，可以对存储单元执行一系列编程验证操作，以便将其编程为相应的目标程序状态。一系列编程验证操作可以从最低程序状态S(1)开始，然后进行到较高的程序状态，直到所选择的存储单元的阈值电压达到相应的目标程序状态的相应验证电压电平为止。在一些实施例中，可以将验证电压分别选择作为程序状态S(1)至S(Q-1)的阈值电压分布曲线的最小阈值电压。每个编程验证操作可以包括编程操作和后续的验证操作。在编程操作中，可以选择存储单元中的一些并且按照从第一行到第N行、或者从第N行到第一行的逐行方式编程到程序状态中。
其中，在一些实施例中，所述外围电路包括：控制电路和行驱动器； 所述行驱动器与所述至少两个存储面均耦接，并被所述控制电路所控制；
所述行驱动器配置为，在多面编程模式下，对同时进行编程操作的至少两个存储面均施加字线驱动电压；
所述行驱动器配置为，在单面编程模式下，对选择的一个存储面施加字线驱动电压。
这里的行驱动器可以参考图2中的行驱动器进行理解，不同的是，在本实施例中，所述行驱动器虽然与多个存储面耦接，但在单面模式下，行驱动器仅对选择的一个存储面施加字线驱动电压。这里字线驱动电压包括施加在选中字线上的编程电压和施加在未选中字线上的导通电压或者成为编程通过电压。
在一些实施例中，所述行驱动器配置为，在由多面编程模式切换为单面编程模式后，针对每一存储面，在相应存储面的第一选中字线上施加第一编程电压；
其中，所述第一编程电压小于第二编程电压；所述第二编程电压为确定存在编程异常的存储面时，施加在所述相应存储面的所述第一选中字线上的编程电压；所述第一选中字线为确定存在编程异常的存储面时，相应存储面的选中字线。
在一些实施例中，所述行驱动器配置为，在所述相应存储面的第一选中字线上施加第一编程电压时；在所述相应存储面中未选中的字线上施加第一导通电压；所述第一导通电压小于第二导通电压；所述第二导通电压为确定存在编程异常的存储面时，施加在所述相应一存储面的未选中字线上的导通电压。
实际应用中，控制电路10控制电压生成电路输出较低电平的初始编程电压/初始导通电压(Vpgm/Vpass)，并控制行驱动器仅对选择的一个存储面的选中字线施加Vpgm，并对未选中字线施加Vpass。
在一些实施例中，所述外围电路配置为：
检测所述至少两个存储面中当前编程的存储单元的编程验证次数；
当所述编程验证次数超出当前待写入数据对应的预设次数时，确定所述至少两个存储面中存在编程异常的存储面。
在一些实施例中，所述外围电路还包括：多个编程验证电压生成器；多个编程验证电压生成器中的每个分别与所述至少两个存储面中的一个存储面耦接，并被所述控制电路所控制；
所述多个编程验证电压生成器配置为：分别给不同存储面中的当前编程的存储单元施加编程验证电压。
在一些实施例中，所述多个编程验证电压生成器中的每个分别与所述至少两个存储面中的一个存储面的一条字线耦接；
所述多个编程验证电压生成器配置为：分别给同一存储面中的不同字线对应的存储单元施加编程验证电压。
这里，所述多个编程验证电压生成器属于图2中电压生成电路的子电路。需要说明的是，多个编程验证电压生成器在通过行驱动器施加到不同存储面的字线上时，仍然可以保持物理隔离。
在一些实施例中，所述外围电路还包括：寄存器，配置为确定所述多个存储面中存在编程异常的存储面时，保存第一标记；
所述外围电路还配置为：接收到第一指令时，利用所述存储器中的其它存储面存储分配给存在编程异常的存储面中存储数据；所述第一指令用于指示将第一标记中对应的存储面中存储数据进行转存。
这里，所述寄存器可以是状态寄存器。
实际应用中，控制电路可以自行决定是否进行编程模式的切换，并在单面编程模式结束以后，存储器系统或主机通过状态寄存器检测到该编程失败情况，在这种情况下，存储器系统或主机可以采取进一步措施，如发 出指令指示将存在编程异常的存储面中存储数据进行转存。
需要说明的是，当存储器查看到状态寄存器的用于指示多面编程失败的标志时，也可以暂停多面编程状态，此时存储器系统或主机在存储器暂停多面编程状态时查看状态寄存器并发现，多面编程异常，此时由存储器系统或主机发出指令，指示存储器切换到单面编程模式进行编程。
在一些实施例中，所述存储器包括三维NAND型存储器。
下面结合应用实施例对本申请再作进一步详细的描述。
本申请应用实施例提供一种存储器的操作方法，图3为本申请实施例存储器的操作方法实现流程示意图。如图3所示，所述方法包括以下步骤：
步骤301：开始；
在开始阶段，存储器做好初始化等准备工作。
当控制电路接收到主机或存储器控制器发出的进行多面编程操作的指令时，转入步骤302。
步骤302：采用多面编程模式进行编程；
这里，外围电路采用多面编程模式对存储器中的多个存储面同时进行编程。
在该步骤中，编程电压在面之间共享。如果任一存储面中的存储单元阵列存在缺陷，则编程电压可能无法达到其目标。编程进展很慢，甚至会导致其他面出现PSF。
在步骤302之后，转入步骤303。
步骤303：判断是否有存储面存在编程异常；
这里，控制电路根据编程电压的次数是否超过预设次数判断是否有存储面存在编程异常。
在该步骤中，可以跟踪不同PV级别的编程验证次数。检查编程验证次数是否超出预设次数。如果某个PV级别的验证次数超过预设次数，则 表明有存储面存在编程异常问题。此时，某一存储面生长的结构缺陷可能是导致编程异常原因之一。
当判断结果表明存在异常面时，转到步骤304；当判断结果表明不存在异常面时，转到步骤305。
步骤304：设置标志，通知暂停使用多面编程模式；
在该步骤中，设置标志以指示多面编程失败，指示多面编程失败的标志可以存放在存储器的状态寄存器里。存储器暂停多面编程操作后，进一步转换到单面编程操作。等到整个编程结束后主机或存储器系统可以检测状态寄存器里的标志，并进行相应的后续处理。在步骤304之后，转入步骤306。
步骤305：继续采用多面编程模式进行编程；
这里，外围电路继续采用多面编程模式对存储器中的多个存储面同时进行编程。
步骤306：将Vpgm/Vpass修正为更低的电压；
这里，控制电路控制电压生成电路将Vpgm/Vpass设置为较低的级别，同时利用行驱动器施加到存储面的字线上。
步骤307：采用单面模式进行编程；
这里，外围电路采用单面编程模式对多个存储面中的每个存储面依次进行编程。
在该步骤中，在采用单面模式进行编程操作时，在单面级别生成编程通过/编程失败。
需要说明的是：实际应用中，步骤306与步骤307之间没有严格的先后顺序，步骤306实际是在步骤307的每个存储面开始编程时执行的。
步骤308：结束。
本申请实施例还提供了一种存储器系统1000，如图4所示，所述存储 器系统1000包括：
一个或多个如上述实施例中所述的存储器1；以及
存储控制器2，其与所述存储器1耦接。
其中，在一些实施例，所述外围电路配置为，接收到第二指令；响应于所述第二指令，采用多面编程模式对所述多个存储面中的至少两个存储面同时进行编程操作；确定所述至少两个存储面中存在编程异常的存储面时，暂停编程操作并保存第一标记；
所述存储器控制器配置为，根据所述第一标记，发出第三指令；
所述外围电路配置为，接收到第三指令；响应于所述第三指令，采用单面编程模式，继续对所述至少两个存储面中的每个存储面依次进行编程操作。
这里，所述第二指令用于指示存储器1采用多面编程模式进行编程操作；所述第三指令用于指示存储器1采用单面编程模式进行编程操作。
实际应用中，所述存储控制器2可以用于控制所述存储器1执行擦除、读取或者写操作，并对所述存储器中发出或接收的指令进行译码、解析或运算。所述存储器控制器2可以通过存储器I/F(InterFace)与所述存储器1耦接。
实际应用中，所述第一标记可以存储在各存储器1对应的状态寄存器中。当存在存储器1暂停编程操作时，存储器控制器2访问该存储器1对应的状态寄存器，存储器控制器2根据第一标记向暂停编程的存储器发出第三指令，暂停编程的存储器1在接收到第三指令后，采用单面编程模式进行编程。
需要说明的是：“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
另外，本申请实施例所记载的技术方案之间，在不冲突的情况下，可 以任意组合。
以上所述，仅为本申请的较佳实施例而已，并非用于限定本申请的保护范围。

Claims (22)

  1. 一种存储器的操作方法，包括：
    采用多面编程模式对存储器的多个存储面中的至少两个存储面同时进行编程操作；
    确定所述至少两个存储面中存在编程异常的存储面时，采用单面编程模式，继续对所述至少两个存储面中的每个存储面依次进行编程操作。
  2. 根据权利要求1所述的方法，其中，所述采用单面编程模式，继续对所述至少两个存储面中的每个存储面依次进行编程操作，包括：
    在采用单面编程模式时，针对每一存储面，在相应存储面的第一选中字线上施加第一编程电压；
    其中，所述第一编程电压小于第二编程电压；所述第二编程电压为确定存在编程异常的存储面时，施加在所述相应存储面的所述第一选中字线上的编程电压；所述第一选中字线为确定存在编程异常的存储面时，相应存储面的选中字线。
  3. 根据权利要求2所述的方法，其中，所述方法还包括：
    在所述相应存储面的第一选中字线上施加第一编程电压时；在所述相应存储面中未选中的字线上施加第一导通电压；所述第一导通电压小于第二导通电压；所述第二导通电压为确定存在编程异常的存储面时，施加在所述相应存储面的未选中字线上的导通电压。
  4. 根据权利要求1所述的方法，其中，所述确定所述至少两个存储面中存在编程异常的存储面，包括：
    检测所述至少两个存储面中当前编程的存储单元的编程验证次数；
    当所述编程验证次数超出当前待写入数据对应的预设次数时，确定所述至少两个存储面中存在编程异常的存储面。
  5. 根据权利要求4所述的方法，其中，所述方法还包括：
    利用不同的电压源，分别给不同存储面中的当前编程的存储单元施加编程验证电压。
  6. 根据权利要求5所述的方法，其中，所述方法还包括：
    利用不同的电压源，分别给同一存储面中的不同字线对应的存储单元施加编程验证电压。
  7. 根据权利要求1所述的方法，其中，所述确定所述至少两个存储面中存在编程异常的存储面时，采用单面编程模式，继续对所述至少两个存储面中的每个存储面依次进行编程操作，包括：
    确定所述至少两个存储面中存在编程异常的存储面时，直接采用单面编程模式，继续对所述至少两个存储面中的每个存储面依次进行编程操作；或者，
    确定所述至少两个存储面中存在编程异常的存储面时，暂停编程操作；在接收到第二指令后采用单面编程模式，继续对所述至少两个存储面中的每个存储面依次进行编程操作。
  8. 根据权利要求1所述的方法，其中，所述方法还包括：
    确定所述至少两个存储面中存在编程异常的存储面时，保存第一标记；
    接收到第一指令时，利用所述存储器中的其它存储面存储分配给存在编程异常的存储面中存储数据；所述第一指令用于指示将第一标记中对应的存储面中存储数据进行转存。
  9. 根据权利要求1所述的方法，其中，所述采用单面编程模式继续对所述至少两个存储面中的每个存储面依次进行编程操作，包括：
    对所述至少两个存储面中的第一存储面继续进行编程操作；
    确定所述第一存储面编程失败或者编程完成时，对所述至少两个存储面中的第二存储面继续进行编程操作。
  10. 根据权利要求1所述的方法，其中，所述方法还包括：
    确定所述至少两个存储面中不存在编程异常的存储面时，采用所述多面编程模式，继续对所述至少两个存储面进行编程操作。
  11. 一种存储器，包括：多个存储面及与所述存储面耦接的外围电路；其中，
    所述外围电路配置为，采用多面编程模式对所述多个存储面中的至少两个存储面同时进行编程操作；确定所述至少两个存储面中存在编程异常的存储面时，采用单面编程模式，继续对所述至少两个存储面中的每个存储面依次进行编程操作。
  12. 根据权利要求11所述的存储器，其中，所述外围电路包括：控制电路和行驱动器；所述行驱动器与所述至少两个存储面均耦接，并被所述控制电路所控制；
    所述行驱动器配置为，在多面编程模式下，对同时进行编程操作的至少两个存储面均施加字线驱动电压；
    所述行驱动器配置为，在单面编程模式下，对选择的一个存储面施加字线驱动电压。
  13. 根据权利要求12所述的存储器，其中，所述行驱动器配置为，在由多面编程模式切换为单面编程模式后，针对每一存储面，在相应存储面的第一选中字线上施加第一编程电压；
    其中，所述第一编程电压小于第二编程电压；所述第二编程电压为确定存在编程异常的存储面时，施加在所述相应存储面的所述第一选中字线上的编程电压；所述第一选中字线为确定存在编程异常的存储面时，相应存储面的选中字线。
  14. 根据权利要求13所述的存储器，其中，所述行驱动器配置为，在所述相应存储面的第一选中字线上施加第一编程电压时；在所述相应存储面中未选中的字线上施加第一导通电压；所述第一导通电压小于第二导通 电压；所述第二导通电压为确定存在编程异常的存储面时，施加在所述相应存储面的未选中字线上的导通电压。
  15. 根据权利要求11所述的存储器，其中，所述外围电路配置为：
    检测所述至少两个存储面中当前编程的存储单元的编程验证次数；
    当所述编程验证次数超出当前待写入数据对应的预设次数时，确定所述至少两个存储面中存在编程异常的存储面。
  16. 根据权利要求15所述的存储器，其中，所述外围电路还包括：多个编程验证电压生成器；多个编程验证电压生成器中的每个分别与所述至少两个存储面中的一个存储面耦接，并被所述控制电路所控制；
    所述多个编程验证电压生成器配置为：分别给不同存储面中的当前编程的存储单元施加编程验证电压。
  17. 根据权利要求16所述的存储器，其中，所述多个编程验证电压生成器中的每个分别与所述至少两个存储面中的一个存储面的一条字线耦接；
    所述多个编程验证电压生成器配置为：分别给同一存储面中的不同字线对应的存储单元施加编程验证电压。
  18. 根据权利要求11所述的存储器，其中，
    所述外围电路配置为，确定所述至少两个存储面中存在编程异常的存储面时，直接采用单面编程模式，继续对所述至少两个存储面中的每个存储面依次进行编程操作；
    或者，
    所述外围电路配置为，确定所述至少两个存储面中存在编程异常的存储面时，暂停编程操作；在接收到第二指令后采用单面编程模式，继续对所述至少两个存储面中的每个存储面依次进行编程操作。
  19. 根据权利要求11所述的存储器，其中，所述外围电路还包括：寄 存器，配置为确定所述多个存储面中存在编程异常的存储面时，保存第一标记；
    所述外围电路配置为：接收到第一指令时，利用所述存储器中的其它存储面存储分配给存在编程异常的存储面中存储数据；所述第一指令用于指示将第一标记中对应的存储面中存储数据进行转存。
  20. 根据权利要求11所述的存储器，其中，所述存储器包括三维NAND型存储器。
  21. 一种存储器系统，包括：
    一个或多个如权利要求11至20中任一项所述的存储器；以及
    存储控制器，其与所述存储器耦接。
  22. 根据权利要求21所述的存储器系统，其中，
    所述外围电路配置为，接收到第二指令；响应于所述第二指令，采用多面编程模式对所述多个存储面中的至少两个存储面同时进行编程操作；确定所述至少两个存储面中存在编程异常的存储面时，暂停编程操作并保存第一标记；
    所述存储器控制器配置为，根据所述第一标记，发出第三指令；
    所述外围电路配置为，接收到第三指令；响应于所述第三指令，采用单面编程模式，继续对所述至少两个存储面中的每个存储面依次进行编程操作。
PCT/CN2021/115475 2021-08-30 2021-08-30 存储器及其操作方法、存储器系统 WO2023028790A1 (zh)

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