WO2023015647A1 - 半导体结构及其形成方法和存储器 - Google Patents

半导体结构及其形成方法和存储器 Download PDF

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Publication number
WO2023015647A1
WO2023015647A1 PCT/CN2021/117214 CN2021117214W WO2023015647A1 WO 2023015647 A1 WO2023015647 A1 WO 2023015647A1 CN 2021117214 W CN2021117214 W CN 2021117214W WO 2023015647 A1 WO2023015647 A1 WO 2023015647A1
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layer
bit line
forming
substrate
top surface
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French (fr)
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宛伟
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Definitions

  • the present application relates to the technical field of semiconductor device manufacturing, in particular to a semiconductor structure, its forming method and memory.
  • Dynamic Random Access Memory (English: Dynamic Random Access Memory, referred to as: DRAM) is a semiconductor memory widely used in mobile phones, computers, automobiles and other electronic products. With the development of science and technology, the feature size of integrated circuit devices is continuously shrinking, and the critical size of DRAM is also getting smaller and smaller, and the difficulty is also increasing. The future DRAM process technology will be around 10-15nm, which is very demanding on the electrical properties of the product. strict. In the capacitive connection contact window etching process, it is often encountered that the dielectric layer (SiN) at the bottom of the contact window is not etched sufficiently, so that the polysilicon (poly) deposited later cannot fully contact the active area, which will increase the resistance of the contact.
  • SiN dielectric layer
  • the purpose of the present application is to provide a semiconductor structure, its forming method and memory.
  • the first aspect of the present application provides a method for forming a semiconductor structure, including: providing a substrate, the substrate has a plurality of word line structures and active regions, and the substrate has a bit line connection column, the The bit line connection column is located above the word line structure interval area; a bit line structure is formed, and the bit line structure is connected to the active region through the bit line connection column; a first a sacrificial layer, so that the top surface of the first sacrificial layer is flush with the top surface of the bit line structure, and the first sacrificial layer includes a carbon layer; a first groove is formed on the first sacrificial layer, so The first trench is perpendicular to the bit line structure, the first trench exposes the substrate; a first dielectric layer is formed, the first dielectric layer fills the first trench and covers the first sacrificial layer planarize the first dielectric layer, and expose the top surface of the first sacrificial layer; remove the first sacrificial layer, and expose the substrate between
  • the second aspect of the present application provides a semiconductor structure prepared by using the above-mentioned method for forming a semiconductor structure.
  • the semiconductor structure includes: a substrate with a plurality of word line structures and an active region inside, and a bit line connection column on the substrate, the The bit line connection column is located above the word line structure interval area; the bit line structure, the bit line structure is connected to the active region through the bit line connection column; the capacitance contact window, the capacitance contact window is located On the substrate, it includes a first dielectric layer and a capacitive contact metal layer, the capacitive contact metal layer is located in the third groove formed between the first dielectric layers, the bottom of the capacitive contact metal layer is in contact with the The active area is fully connected.
  • a third aspect of the present application provides a memory, including the above-mentioned semiconductor structure.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure in the related art
  • FIG. 2 is a schematic structural diagram of a semiconductor structure according to a first embodiment of the present application.
  • Fig. 3 is A-A1 sectional view of Fig. 2;
  • FIG. 4-7 are schematic cross-sectional views of the main process in the process of manufacturing the bit line structure in the embodiment of the present application, and Fig. 4-7 is a cross-sectional view of B-B1 in Fig. 2;
  • Figure 8- Figure 20 is a schematic cross-sectional view of the main process in the process of manufacturing the semiconductor structure in the embodiment of the present application, and Figure 8- Figure 20 is a cross-sectional view of C-C1 in Figure 2;
  • Figure 21 is a top view of Figure 20;
  • FIG. 22 is a flowchart of a method for forming a semiconductor structure according to the second embodiment of the present application.
  • the capacitor contacts the metal layer.
  • first, second and the like used in this application may be used to describe various elements herein, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element.
  • a first resistance could be termed a second resistance, and, similarly, a second resistance could be termed a first resistance, without departing from the scope of the present application.
  • Both the first resistance and the second resistance are resistances, but they are not the same resistance.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure in the related art. Referring to FIG. 1 , the bottom of the polysilicon layer 11 cannot fully contact the active region, and the contact area is small, which increases the contact resistance.
  • FIG. 22 is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present application.
  • the first aspect of the present application provides a method for forming a semiconductor structure, which may include the following steps:
  • the substrate has a plurality of word line structures and active regions, the substrate has a bit line connection column, and the bit line connection column is located above the spaced area of the word line structure.
  • bit line structure is connected to the active region through a bit line connecting column.
  • the material of the first dielectric layer includes silicon carbonitride or silicon nitride. In some embodiments, at least one of chemical vapor deposition, physical vapor deposition and atomic layer deposition can be used to form the first dielectric layer.
  • the capacitive contact metal layer fills the third trench and covers the top surface of the first dielectric layer, and the bottom of the capacitive contact metal layer is completely connected to the active region.
  • the method for forming the semiconductor structure provided by the embodiment of the present application is simple and easy to operate.
  • the first sacrificial layer is deposited on the surface of the active region.
  • the first sacrificial layer adopts a carbon layer, compared with a silicon oxide layer or nitrogen
  • the silicon oxide layer because the carbon layer is easier to remove, is less likely to form residue than the silicon oxide layer or silicon nitride layer, so that the capacitance contact metal layer obtained in the subsequent process is fully in contact with the active area, which can increase the contact with the active area.
  • the contact area of the active region reduces the resistance value of the capacitive contact window and improves the electrical performance.
  • step S30 forming the first sacrificial layer on the substrate includes: step S31 forming the first sacrificial layer on the substrate after forming the bit line structure, and planarizing the first sacrificial layer, so that the first sacrificial layer The top surface of the bit line structure is flush with the top surface of the bit line structure.
  • forming the first sacrificial layer on the substrate in step S30 further includes step S32: stacking and forming a second sacrificial layer and a second mask layer sequentially from bottom to top on the top surface of the planarized first sacrificial layer and a second photoresist layer; forming a second trench on the second mask layer and the second photoresist layer, the second trench is perpendicular to the bit line structure, and the second trench exposes the second sacrificial layer.
  • a second photoresist layer can be formed on the second mask layer, and a second groove can be formed on the second mask layer by using a photolithographic imaging process of grid holes.
  • the second sacrificial layer may include a silicon nitride layer, and the second mask layer may include a silicon oxynitride layer.
  • step S33 is included after step S32: forming a third sacrificial layer on the top surface of the second photoresist layer and the inner wall of the second trench, the third sacrificial layer covering the second photoresist layer , the second mask layer and the second groove; remove the third sacrificial layer on the top surface of the second photoresist layer and the bottom of the second groove to form a spacer layer; remove the second photoresist layer and the second mask layer.
  • the third sacrificial layer may include a silicon oxide layer.
  • step S34 is included after step S33: using the sidewall layer as a mask to sequentially etch the second sacrificial layer and the first sacrificial layer downward to form the first trench; remove the sidewall layer; remove the second A sacrificial layer, forming a first trench on the first sacrificial layer.
  • step S80 is included: forming a capacitive contact window, removing the capacitive contact metal layer on top of the first dielectric layer, and exposing the top surface of the first dielectric layer.
  • an oxygen dry etching process is used to remove the first sacrificial layer.
  • the capacitor contact metal layer includes a polysilicon layer.
  • bit line structure in step S20 includes:
  • Step S21 forming a first isolation dielectric layer on the substrate, and planarizing the first isolation dielectric layer, so that the top surface of the first isolation dielectric layer is flush with the top surface of the bit line connection pillar.
  • Step S22 stack and form a conductive layer, a second isolation dielectric layer, a first mask layer and a first photoresist layer sequentially from bottom to top on the top surface of the first isolation dielectric layer and the top surface of the bit line connection pillar, so that the second Develop a photoresist layer and etch down the first mask layer, the second isolation dielectric layer, the conductive layer and the first isolation dielectric layer sequentially, remove the first photoresist layer and the first mask layer, and form a bit line structure .
  • FIG. 2 to 21 are structural schematic diagrams corresponding to each step in the method for forming a capacitor structure provided in the embodiment of the present application. The steps of the embodiment of the present application will be described in detail below with reference to FIG. 2 to FIG. 21 .
  • the substrate 100 may include but not limited to a single crystal silicon substrate, a polycrystalline silicon substrate, a gallium nitride substrate or a sapphire substrate.
  • the substrate 100 is preferably a single crystal silicon substrate or a polycrystalline silicon substrate. More preferably, the substrate 100 may be a silicon substrate or a lightly doped silicon substrate, such as an N-type polysilicon substrate or a P-type polysilicon substrate.
  • a trench isolation structure 110 extending into the substrate 100 is formed on the substrate 100 , and the trench isolation structure 110 can be specifically formed by opening deep isolation grooves in the substrate 100 The groove is formed by filling the isolation material.
  • the trench isolation structure 110 includes one or more of isolation materials such as silicon nitride, silicon oxide, and silicon oxynitride.
  • the trench isolation structure 110 includes silicon oxide. Multiple independent regions are divided on the substrate 100 by the trench isolation structure 110 to form the active region 120 .
  • a plurality of communication trenches are arranged side by side along the X-axis direction at intervals, each communication trench extends laterally along the Y-axis direction, and the same communication trench laterally penetrates the substrate 100 and the trench along the Y-axis direction.
  • the X-axis direction is different from the Y-axis direction, that is, the angle between the X-axis direction and the Y-axis direction is greater than 0° and less than 180°.
  • the X-axis is perpendicular to the Y-axis.
  • the word line structure 130 can be formed in the communication trench, so as to simultaneously control on-off of multiple active regions 120 through the same word line structure 130 .
  • a silicon dioxide layer is firstly filled on the basis of the active region 120 , and then trenches are etched on the surface of the silicon dioxide layer to form the buried word line structure 130 .
  • An insulating layer is formed on the surface of the word line structure, and the insulating layer may be silicon nitride (not shown in the figure). It should be noted here that the buried word line structure 130 is buried inside the substrate 100 and should not be seen in the top view. In FIG. 2 , the shape of the buried word line structure 130 in the substrate 100 Therefore, the embedded word line structure 130 is marked.
  • a bit line connection pillar 140 is formed on the active region 120 , and the bit line connection pillar 140 is higher than the substrate 100 . Form the bit line structure on the substrate 100. With reference to FIGS. The top surfaces of the bit line connection pillars 140 are flush, and then on the plane of the top surface of the first isolation dielectric layer 101 and the top surface of the bit line connection pillars, the conductive layer 102, the second isolation dielectric layer 103 and The first mask layer.
  • the first mask layer can be a single layer or multiple layers, which can be selected according to process requirements.
  • the first mask layer has a stacked first mask layer A104 and a first mask layer B105, and a photoresist is coated on the first mask layer B105 to form a first photoresist layer 106, and then use a laser to irradiate the first photoresist layer 106 through the photomask to cause a chemical reaction in the photoresist in the exposed area; glue, the latter is called negative photoresist), and transfer the pattern S1 on the photomask to the first photoresist layer 106.
  • the first photoresist layer 106, the first mask layer B105, the first mask layer A104, the second isolation dielectric layer 103 and the conductive layer 102 are used as etching barrier layers in sequence, and the next layer is etched, and the photolithographically defined
  • the patterns S1 are transferred sequentially until the conductive layer 102 and the first isolation dielectric layer 101 are etched, and the top surface of the substrate 100 is exposed, and the first photoresist layer 106, the first mask layer B105 and the first mask layer are removed.
  • film layer A104 thereby forming a bit line structure 150 .
  • the bit line structure 150 includes a first isolation dielectric layer 101 , a conductive layer 102 and a second isolation dielectric layer 103 , and the conductive layer 102 is connected to the active area through the bit line connecting pillar 140 .
  • the materials of the first isolation dielectric layer 101 , the second isolation dielectric layer 103 and the first mask layer B105 include silicon nitride or silicon carbonitride.
  • the material of the conductive layer 102 includes conductive materials such as tungsten or titanium.
  • the material of the first mask layer A104 includes silicon oxide.
  • the bit line structure extends along the X-axis direction. In an optional embodiment, the bit line structure 150 is perpendicular to the word line structure 130 in this embodiment.
  • the specific steps of forming the first trench 210 on the first sacrificial layer 201 in this embodiment include:
  • a sacrificial material is deposited on the substrate 100 by a deposition process to form a first sacrificial layer 201 , which can cover the top surface of the bit line structure.
  • carbon materials can be used to make the first sacrificial layer 201, wherein the deposition process can include chemical vapor deposition (CVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD) and plasma enhanced ALD (PEALD).
  • the first sacrificial layer is planarized so that the top surface of the first sacrificial layer is flush with the top surface of the bit line structure.
  • the first sacrificial layer 201 on the top surface of the bit line structure 150 is removed by a planarization process such as a chemical mechanical polishing process to expose the top surface of the bit line structure 150 .
  • a plasma-enhanced chemical vapor deposition process is used to form the carbon layer.
  • carbon-based gases such as CH 4 are transported into the reaction chamber, and the carbon-based gases such as CH 4 undergo alternating cycles under conditions of low temperature, low pressure, and vacuum.
  • the electric field by setting the appropriate radio frequency voltage, makes the carbon-based gas such as CH 4 undergo a plasma reaction and decomposes into a carbon layer.
  • the reaction is as follows:
  • carbon-containing free radical groups such as CH 3 , CH 2 , CH , C , etc. with lighter molecular weights are deposited on the substrate 100 to form a carbon layer, and the carbon layer covers the bit line structure top surface.
  • the low pressure in this embodiment refers to a pressure between 2 mTorr and 100 mTorr.
  • Low temperature refers to a temperature between 20°C and 40°C.
  • CH 4 is used as a reaction gas to form a carbon layer as an example for illustration, and other hydrocarbon gases, such as C 2 H 6 , C 2 H 2 , etc., can also be selected to form a carbon layer according to actual needs.
  • the second sacrificial layer 301 and the second mask layer 302 are sequentially stacked on the top surface of the planarized first sacrificial layer 201 from bottom to top.
  • the material of the second sacrificial layer 301 may include silicon nitride, and the material of the second mask layer 302 may include silicon oxynitride.
  • the second photoresist layer 303 can be coated on the top surface of the second mask layer 302, and then a laser is used to irradiate the second photoresist layer 303 through the mask to cause a chemical reaction of the photoresist in the exposed area;
  • the photoresist in the exposed area or the unexposed area is dissolved and removed (the former is called a positive photoresist, and the latter is called a negative photoresist), and the pattern S2 on the photomask is transferred to the second photoresist layer 303 .
  • the second photoresist layer 303, the second mask layer 302 and the second sacrificial layer 301 are sequentially used as etching barrier layers, the next layer is etched, and the pattern S2 defined by photolithography is sequentially transferred down, and expose the top surface of the second sacrificial layer 301, thereby forming a second trench 310 on the etched second photoresist layer 303 and second mask layer 302, the second trench 310 is perpendicular to In the bit line structure 150 , the second trench 310 exposes the second sacrificial layer 301 .
  • a third sacrificial layer 401 is formed on the top surface of the second photoresist layer 303 and the inner wall of the second trench 310 , and the third sacrificial layer 401 covers the second photoresist layer 303 , the second mask layer 302 and the second groove 310; remove the third sacrificial layer 401 on the top surface of the second photoresist layer 303 and the bottom of the second groove 310 to form a spacer layer 402; remove the second photoresist layer 303 and the second mask layer 302.
  • the material of the third sacrificial layer 401 may include silicon oxide.
  • etch the third sacrificial layer 401 that is, use an etching process to remove the top surface of the second photoresist layer 303 and the bottom of the second trench 310
  • the third sacrificial layer 401 and the remaining third sacrificial layer 401 form a sidewall layer 402 , and the sidewall layer 402 is located on the sidewall of the second trench 310 .
  • the second photoresist layer 303 and the second mask layer 302 are etched away by using a wet etching process or a dry etching process with the sidewall layer 402 and the second sacrificial layer 301 as an etching barrier layer. .
  • the second sacrificial layer 301 and the first sacrificial layer 201 are sequentially etched downward using the sidewall layer 402 as a mask, and the first sacrificial layer 301 and the first sacrificial layer 201 are formed on the second sacrificial layer 301
  • the second sacrificial layer 301 and the second isolation dielectric layer 103 as an etching barrier layer in sequence, the second sacrificial layer is etched using a wet etching process or a dry etching process.
  • layer 301 and the first sacrificial layer 201 and a first trench 210 is formed on the second sacrificial layer 301 and the first sacrificial layer 201 ; the bottom of the first trench 210 exposes the substrate 100 .
  • Removing the sidewall layer 402 and the second sacrificial layer 301 may adopt a wet etching process or a dry etching process.
  • a first dielectric layer 501 is deposited on the substrate 100, the first dielectric layer 501 fills the first trench 210 and covers the top surface of the first sacrificial layer 201; the first dielectric layer 501 is planarized, and The top surface of the first sacrificial layer 201 is exposed.
  • the material of the first dielectric layer 501 includes silicon carbonitride or silicon nitride.
  • the first dielectric layer 501 may be formed by at least one of chemical vapor deposition, physical vapor deposition and atomic layer deposition.
  • the first sacrificial layer 201 is used as the polishing cut-off layer, and the first dielectric layer 501 on the top surface of the first sacrificial layer 201 is removed by a planarization process such as a chemical mechanical polishing process to expose the top surface of the first sacrificial layer 201 .
  • an oxygen dry etching process may be used to form a third trench 510 exposing the substrate 100 between adjacent first dielectric layers 501 .
  • a third trench 510 is formed at the position of the first sacrificial layer 201 in FIG. 16 , refer to FIG. 17 .
  • a capacitive contact metal layer 601 is formed.
  • the capacitive contact metal layer 601 fills the third trench 510 and covers the top surface of the first dielectric layer 501 .
  • the bottom of the capacitive contact metal layer 601 is completely connected to the active region.
  • FIG. 21 is a top view of FIG. 20; what needs to be explained here is that the buried word line structure 130 is buried inside the substrate 100, and should not be seen in the top view.
  • the buried word line structure 130 is in the shape and position of the substrate 100 , so the buried word line structure 130 is marked.
  • a capacitive contact window is formed, and the capacitive contact metal layer 601 on top of the first dielectric layer 501 is removed to expose the top surface of the first dielectric layer 501 .
  • the capacitive contact metal layer 601 located on the top surface of the first dielectric layer 501 is removed by using a planarization process such as a chemical mechanical polishing process, exposing the top surface of the first dielectric layer 501, and forming Capacitive contact window. It can be understood that the capacitive contact metal layer 601 on the top surface of the first dielectric layer 501 may also be removed by an etch-back process, so that the top surface of the capacitive contact metal layer 601 is flush with the top surface of the first dielectric layer 501 .
  • the first sacrificial layer is deposited on the surface of the active region after forming the bit line structure.
  • the first sacrificial layer is a carbon layer, especially the carbon layer at the bottom of the third trench 510 is easier to remove , the contact area between the deposited capacitive contact metal layer 601 and the active region is larger, the electrical performance is better, and the resistance value is lower.
  • the second aspect of the present application provides a semiconductor structure prepared by using the above-mentioned method for forming a semiconductor structure.
  • the semiconductor structure includes: a substrate 100, a plurality of word line structures 130 and an active region 120 are provided in the substrate 100, and a bit line connection column 140 is provided on the substrate 100, and the bit line connection column 140 is located at the word line
  • the metal layer 601, the capacitor contact metal layer is located in the third trench 510 formed between the first dielectric layers, and the bottom of the capacitor contact metal layer is completely connected to the active region.
  • the top surface of the capacitive contact window and the top surface of the bit line structure 150 may be flush or have a certain height difference.
  • the bit line structure 150 is isolated from the capacitor contact metal layer 601 by the first dielectric layer 501 .
  • the contact area between the bottom of the capacitor contact metal layer and the active region is at least 90% of the cross-sectional area of the top of the capacitor contact metal layer.
  • the bit line structure includes a first isolation dielectric layer, a conductive layer and a second isolation dielectric layer stacked sequentially from bottom to top, and the two ends of the bit line connection column are respectively connected to the conductive layer and the active region.
  • the conductive layer includes a tungsten layer.
  • the capacitor contact metal layer includes a polysilicon layer.
  • the material of the first dielectric layer includes silicon nitride or silicon carbonitride.
  • a third aspect of the present application provides a memory, including the above-mentioned semiconductor structure.

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Abstract

本申请公开了一种半导体结构及其形成方法和存储器，该半导体结构的形成方法包括：提供衬底，衬底内具有多条字线结构和有源区，衬底上具有位线连接柱，位线连接柱位于字线结构间隔区域的上方；位线结构通过位线连接柱与有源区连接；在衬底上形成第一牺牲层，第一牺牲层包括碳层；在第一牺牲层上形成第一沟槽，第一沟槽垂直于位线结构，第一沟槽暴露衬底；形成第一介质层，第一介质层填充第一沟槽及覆盖第一牺牲层的顶面；平坦化第一介质层，暴露第一牺牲层的顶面；去除第一牺牲层，在相邻第一介质层之间形成暴露衬底的第三沟槽；形成电容接触金属层，电容接触金属层填充第三沟槽及覆盖第一介质层的顶面，电容接触金属层的底部与有源区完全连接。

Description

半导体结构及其形成方法和存储器
交叉引用
本申请基于申请号为202110918663.1、申请日为2021年08月11日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及半导体器件制造的技术领域，特别涉及一种半导体结构及其形成方法和存储器。
背景技术
动态随机存储器(英文：Dynamic Random Access Memory，简称:DRAM)是一种广泛应用于手机、电脑、汽车等电子产品中的半导体存储器。随着科技的发展，集成电路器件特征尺寸的不断缩小，DRAM的关键尺寸也越来越小，难度也越来越大，未来DRAM制程技术将在10-15nm左右，这对产品电性要求非常严格。在电容连接接触窗蚀刻制程中常遇见接触窗底部的介质层(SiN)刻蚀不充分，这样后面沉积的多晶硅(poly)不能和有源区充分接触，这样会增大接触的阻值。
发明内容
本申请的目的是提供一种半导体结构及其形成方法和存储器。
本申请的第一方面提供了一种半导体结构的形成方法，包括：提供衬底，所述衬底内具有多条字线结构和有源区，所述衬底上具有位线连接柱，所述位线连接柱位于所述字线结构间隔区域的上方；形成位线结构，所述位线结构通过所述位线连接柱与所述有源区连接；在所述衬底上形成第一牺牲层，使得所述第一牺牲层的顶面和所述位线 结构的顶面平齐，所述第一牺牲层包括碳层；在所述第一牺牲层上形成第一沟槽，所述第一沟槽垂直于所述位线结构，所述第一沟槽暴露所述衬底；形成第一介质层，所述第一介质层填充第一沟槽及覆盖所述第一牺牲层的顶面；平坦化所述第一介质层，且暴露所述第一牺牲层的顶面；去除所述第一牺牲层，在相邻所述第一介质层之间形成暴露所述衬底的第三沟槽；形成电容接触金属层，所述电容接触金属层填充所述第三沟槽及覆盖所述第一介质层的顶面，所述电容接触金属层的底部与所述有源区完全连接。
本申请的第二方面提供了一种半导体结构，采用上述的半导体结构的形成方法制备得到。
在本申请的一种示例性实施例中，所述的半导体结构包括：衬底，所述衬底内具有多条字线结构和有源区，所述衬底上具有位线连接柱，所述位线连接柱位于所述字线结构间隔区域的上方；位线结构，所述位线结构通过所述位线连接柱与所述有源区连接；电容接触窗，所述电容接触窗位于衬底上，其包括第一介质层和电容接触金属层，所述电容接触金属层位于所述第一介质层之间构成的第三沟槽内，所述电容接触金属层的底部与所述有源区完全连接。
本申请的第三方面提供了一种存储器，包括上述的半导体结构。
附图说明
图1是相关技术中半导体结构的结构示意图；
图2是根据本申请第一实施方式的半导体结构的结构示意图；
图3是图2的A-A1剖视图；
图4-图7是本申请实施例中在制作位线结构的过程中主要的工艺截面示意图，且图4-图7是图2的B-B1剖视图；
图8-图20是本申请实施例中在制作半导体结构的过程中主要的工艺截面示意图，且图8-图20是图2的C-C1剖视图；
图21是图20的俯视图；
图22是根据本申请第二实施方式的半导体结构的形成方法流程图。
附图标记：
100-衬底；110-沟槽隔离结构；120-有源区；130-字线结构；140-位线连接柱；150-位线结构；
101-第一隔离介质层；102-导电层；103-第二隔离介质层；104-第一掩膜层A；105-第一掩膜层B；106-第一光刻胶层；
201-第一牺牲层；210-第一沟槽；
301-第二牺牲层；302-第二掩膜层；303-第二光刻胶层；310-第二沟槽；
401-第三牺牲层；402-侧墙层；
501-第一介质层；510-第三沟槽；
601-电容接触金属层。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚明了，下面结合具体实施方式并参照附图，对本申请进一步详细说明。应该理解，这些描述只是示例性的，而并非要限制本申请的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本申请的概念。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
可以理解，本申请所使用的术语“第一”、“第二”等可在本文中用于描述各种元件，但这些元件不受这些术语限制。这些术语仅用于将第一个元件与另一个元件区分。举例来说，在不脱离本申请的范围 的情况下，可以将第一电阻称为第二电阻，且类似地，可将第二电阻称为第一电阻。第一电阻和第二电阻两者都是电阻，但其不是同一电阻。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应当理解的是，术语“包括/包含”或“具有”等指定所陈述的特征、整体、步骤、操作、组件、部分或它们的组合的存在，但是不排除存在或添加一个或更多个其他特征、整体、步骤、操作、组件、部分或它们的组合的可能性。同时，在本说明书中使用的术语“和/或”包括相关所列项目的任何及所有组合。
图1是相关技术中半导体结构的结构示意图，参考图1，多晶硅层11的底部不能和有源区充分接触，接触面积小，这样增大了接触的阻值。
图22为本申请一实施方式的半导体结构的形成方法的流程图。参考图22，在本申请一些实施例中，本申请的第一方面提供了一种半导体结构的形成方法，可以包括以下步骤：
S10、提供衬底，衬底内具有多条字线结构和有源区，衬底上具有位线连接柱，位线连接柱位于字线结构间隔区域的上方。
S20、形成位线结构，位线结构通过位线连接柱与有源区连接。
S30、在衬底上形成第一牺牲层，使得第一牺牲层的顶面和位线结构的顶面平齐，第一牺牲层包括碳层。
S40、在第一牺牲层上形成第一沟槽，第一沟槽垂直于位线结构，第一沟槽暴露衬底。
S50、形成第一介质层，第一介质层填充第一沟槽及覆盖第一牺牲层的顶面；平坦化第一介质层，且暴露第一牺牲层的顶面。第一介质层的材料包括碳氮化硅或氮化硅，在一些实施例中，可采用化学气相沉积、物理气相沉积以及原子层沉积中的至少一种方式来形成第一 介质层。
S60、去除第一牺牲层，在相邻第一介质层之间形成暴露衬底的第三沟槽。
S70、形成电容接触金属层，电容接触金属层填充第三沟槽及覆盖第一介质层的顶面，电容接触金属层的底部与有源区完全连接。
本申请实施例提供的半导体结构的形成方法简单、易操作，通过形成位线结构后在有源区表面沉积第一牺牲层，第一牺牲层采用碳层，相比于用氧化硅层或氮化硅层，由于碳层更易去除,比用氧化硅层或氮化硅层更不容易形成残留物，这样在后面的制程中得到的电容接触金属层和有源区充分接触，可增大与有源区的接触面积，减小电容接触窗的阻值，提高电性能。
可选的实施例中，步骤S30在衬底上形成第一牺牲层包括：步骤S31在形成位线结构之后在衬底上形成第一牺牲层，平坦化第一牺牲层，使得第一牺牲层的顶面和位线结构的顶面平齐。
可选的实施例中，步骤S30在衬底上形成第一牺牲层还包括步骤S32：在平坦化的第一牺牲层的顶面由下至上依次堆叠形成第二牺牲层、第二掩膜层和第二光刻胶层；在第二掩膜层和第二光刻胶层上形成第二沟槽，第二沟槽垂直于位线结构，第二沟槽暴露第二牺牲层。在第二掩膜层上可形成第二光刻胶层，可利用网格孔的光刻成像的工艺在第二掩膜层上形成第二沟槽。第二牺牲层可包括氮化硅层，第二掩膜层可包括氮氧化硅层。
可选的实施例中，步骤S32之后包括步骤S33：在第二光刻胶层的顶面上和第二沟槽的内壁上形成第三牺牲层，第三牺牲层覆盖第二光刻胶层、第二掩膜层和第二沟槽；去除第二光刻胶层顶面及第二沟槽底部的第三牺牲层，形成侧墙层；去除第二光刻胶层和第二掩膜层。第三牺牲层可包括氧化硅层。
可选的实施例中，步骤S33之后包括步骤S34：以侧墙层为掩膜依次向下刻蚀第二牺牲层和第一牺牲层，形成第一沟槽；去除侧墙层；去除第二牺牲层，在第一牺牲层上形成第一沟槽。
可选的实施例中，步骤S70形成电容接触金属层之后包括步骤S80：形成电容接触窗，去除第一介质层顶部的电容接触金属层，暴露第一介质层的顶面。
可选的实施例中，采用氧气干法刻蚀工艺去除第一牺牲层。
可选的实施例中，电容接触金属层包括多晶硅层。
可选的实施例中，步骤S20形成位线结构包括：
步骤S21：在衬底上形成第一隔离介质层，平坦化第一隔离介质层，使得第一隔离介质层的顶面和位线连接柱的顶面平齐。
步骤S22：在第一隔离介质层的顶面和位线连接柱的顶面由下至上依次堆叠形成导电层、第二隔离介质层、第一掩膜层和第一光刻胶层，以第一光刻胶层显影依次向下刻蚀第一掩膜层、第二隔离介质层、导电层和第一隔离介质层，去除第一光刻胶层和第一掩膜层，形成位线结构。
图2～图21为本申请实施例提供的电容结构的形成方法中各步骤对应的结构示意图。下面将结合图2～图21对本申请实施例的步骤进行详细的阐述。
参考图2和图3，提供衬底100，作为示例，衬底100可以包括但不仅限于单晶硅衬底、多晶硅衬底、氮化镓衬底或蓝宝石衬底。优选地，本实施例中，衬底100优选为单晶硅衬底或多晶硅衬底。更为优选地，衬底100可以是硅衬底或轻掺杂的硅衬底，譬如N型多晶硅衬底或P型多晶硅衬底。
在一实施例中，参考图3，衬底100上形成有延伸至衬底100内的沟槽隔离结构110，沟槽隔离结构110具体可通过在衬底100内开设隔离深槽并在隔离深槽内填充隔离材料所形成。具体的，沟槽隔离结构110包括氮化硅、氧化硅、氮氧化硅等隔离材料中的一种或几种，在本实施例中，沟槽隔离结构110包括氧化硅。通过沟槽隔离结构110在衬底100上划分出多个独立的区域以形成有源区120。
在一实施例中，参考图2，多个连通沟槽沿X轴方向并列间隔分 布，各连通沟槽沿Y轴方向横向延伸，同一连通沟槽沿Y轴方向横向穿透衬底100和沟槽隔离结构110，X轴方向不同于Y轴方向，即X轴方向与Y轴方向之间的夹角大于0°小于180°，可选的实施例中，X轴垂直于Y轴。具体的可在连通沟槽内形成字线结构130，从而通过同一字线结构130同时控制多个有源区120的通断。在形成埋入式字线结构130时，首先在有源区120的基础上填上二氧化硅层，之后在该二氧化硅层表面蚀刻出沟槽，以形成埋入式字线结构130。在字线结构的表面形成有一层绝缘层，该绝缘层可以是氮化硅(图中未示出)。这里需要说明的是，埋入式字线结构130是埋入在衬底100内部的，俯视图中应该看不到，图2中为了便于理解埋入式字线结构130在衬底100中的形状位置，所以标注出了埋入式字线结构130。
在一实施例中，在有源区120上形成位线连接柱140，位线连接柱140高于衬底100。在衬底100上形成位线结构，参考图3-图6，形成位线结构包括在衬底100上先沉积第一隔离介质层101，回刻后使得第一隔离介质层101的顶面和位线连接柱140的顶面平齐，然后在第一隔离介质层101的顶面和位线连接柱的顶面的平面上由下至上依次堆叠形成导电层102、第二隔离介质层103和第一掩膜层，第一掩膜层可为单层，也可为多层，可根据工艺要求进行不同的选择。在本实施例中，第一掩膜层具有叠设的第一掩膜层A104和第一掩膜层B105，在第一掩膜层B105上涂覆光刻胶，形成第一光刻胶层106，然后利用激光器通过光罩照射第一光刻胶层106引起曝光区域的光刻胶发生化学反应；再通过显影技术溶解去除曝光区域或未曝光区域的光刻胶(前者称正性光刻胶，后者称负性光刻胶)，将光罩上的图形S1转移到第一光刻胶层106。依次以第一光刻胶层106、第一掩膜层B105、第一掩膜层A104、第二隔离介质层103和导电层102为蚀刻阻挡层，蚀刻下一层，将光刻定义出的图形S1依次转移下去，直 至将导电层102和第一隔离介质层101蚀刻，并将衬底100的顶面暴露，并去除第一光刻胶层106、第一掩膜层B105和第一掩膜层A104；由此形成位线结构150。位线结构150包括第一隔离介质层101、导电层102和第二隔离介质层103，导电层102通过位线连接柱140与有源区连接。其中，第一隔离介质层101、第二隔离介质层103和第一掩膜层B105的材料包括氮化硅或者碳氮化硅。导电层102的材料包括钨或钛等导电材料。第一掩膜层A104的材料包括氧化硅。位线结构沿X轴方向延伸，可选的实施例中，本实施例中位线结构150垂直于字线结构130。
具体的，本实施例中在第一牺牲层201上形成第一沟槽210的具体步骤包括：
首先，参考图7，利用沉积工艺在衬底100上沉积牺牲材料以形成第一牺牲层201，其可覆盖位线结构的顶面。具体的，可采用碳材料制作第一牺牲层201，其中沉积工艺可以包括化学气相沉积(CVD)、低压CVD(LPCVD)、等离子体增强CVD(PECVD)、原子层沉积(ALD)以及等离子体增强ALD(PEALD)。平坦化第一牺牲层，使得第一牺牲层的顶面和位线结构的顶面平齐。作为示例，以位线结构150为研磨截止层，采用化学机械研磨工艺等平坦化工艺去除位于位线结构150顶面的第一牺牲层201，暴露位线结构150的顶面。
本实施例采用等离子体增强化学气相沉积工艺形成碳层。作为示例，将如图6所示的衬底100置于反应腔室之后，传输CH 4等碳基气体至反应腔室内，CH 4等碳基气体在低温、低压、真空的条件下经过交变电场，通过设置合适的射频电压，使得CH 4等碳基气体发生等离子体反应分解成碳层，反应如下所示：
CH 4→CH 3·+H
CH 4→CH 2·+2H
CH 4→CH·+3H
CH 4→C·+4H
在低温、低压条件下，分子质量较轻的CH 3·、CH 2·、CH·、C·等含碳自由基基团沉积在衬底100上,形成碳层，且碳层覆盖位线结构的顶面。
本实施例中的低压是指压力在2毫托到100毫托之间。低温是指温度在20℃到40℃之间。
本实施例是以CH 4作为反应气体生成碳层为例进行说明，也可以根据实际需要选择其他的烃类气体来形成碳层，例如C 2H 6、C 2H 2等。
其次，参考图8，在平坦化的第一牺牲层201的顶面由下至上依次堆叠形成第二牺牲层301和第二掩膜层302。第二牺牲层301的材料可包括氮化硅，第二掩膜层302的材料可包括氮氧化硅。可在第二掩膜层302的顶面涂覆第二光刻胶层303，然后利用激光器通过光罩照射第二光刻胶层303引起曝光区域的光刻胶发生化学反应；再通过显影技术溶解去除曝光区域或未曝光区域的光刻胶(前者称正性光刻胶，后者称负性光刻胶)，将光罩上的图形S2转移到第二光刻胶层303。参考图9-图10，依次以第二光刻胶层303、第二掩膜层302和第二牺牲层301为蚀刻阻挡层，刻蚀下一层，将光刻定义出的图形S2依次转移下去，并将第二牺牲层301的顶面暴露，由此在刻蚀后的第二光刻胶层303和第二掩膜层302上形成第二沟槽310，第二沟槽310垂直于位线结构150，第二沟槽暴310露第二牺牲层301。
再次，参考图11-图12，在第二光刻胶层303的顶面上和第二沟槽310的内壁上形成第三牺牲层401，第三牺牲层401覆盖第二光刻胶层303、第二掩膜层302和第二沟槽310；去除第二光刻胶层303顶面及第二沟槽310底部的第三牺牲层401，形成侧墙层402；去除第二光刻胶层303和第二掩膜层302。第三牺牲层401的材料可包括氧化硅。以第二光刻胶层303和第二牺牲层301为蚀刻阻挡层，刻蚀第三牺牲层401，即利用刻蚀工艺去除第二光刻胶层303顶面及第二 沟槽310底部的第三牺牲层401，剩余的第三牺牲层401形成侧墙层402，侧墙层402位于第二沟槽310的侧壁。参考图13，然后以侧墙层402和第二牺牲层301为蚀刻阻挡层，采用湿法刻蚀工艺或干法刻蚀工艺刻蚀掉第二光刻胶层303和第二掩膜层302。
最后，参考图14-图15，以侧墙层402为掩膜依次向下刻蚀第二牺牲层301和第一牺牲层201，在第二牺牲层301和第一牺牲层201上形成第一沟槽210；去除侧墙层402；去除第二牺牲层301，在第一牺牲层上形成第一沟槽210。以侧墙层402为掩膜，依次以侧墙层402、第二牺牲层301和第二隔离介质层103为蚀刻阻挡层，采用湿法刻蚀工艺或干法刻蚀工艺刻蚀第二牺牲层301和第一牺牲层201，在第二牺牲层301和第一牺牲层201上形成第一沟槽210；第一沟槽210的底部露出衬底100。去除侧墙层402和第二牺牲层301可采用湿法刻蚀工艺或干法刻蚀工艺。
参考图16-图17，在衬底100上沉积第一介质层501，第一介质层501填充第一沟槽210及覆盖第一牺牲层201的顶面；平坦化第一介质层501，且暴露第一牺牲层201的顶面。第一介质层501的材料包括碳氮化硅或氮化硅，在一些实施例中，可采用化学气相沉积、物理气相沉积以及原子层沉积中的至少一种方式来形成第一介质层501。作为示例，以第一牺牲层201为研磨截止层，采用化学机械研磨工艺等平坦化工艺去除位于第一牺牲层201顶面的第一介质层501，暴露第一牺牲层201的顶面。
参考图18，去除第一牺牲层201，可采用氧气干法刻蚀工艺,在相邻第一介质层501之间形成暴露衬底100的第三沟槽510。在图16中第一牺牲层201的位置形成第三沟槽510，参考图17。
参考图19，形成电容接触金属层601，电容接触金属层601填充第三沟槽510及覆盖第一介质层501的顶面，电容接触金属层601的底部与有源区完全连接。
图21是图20的俯视图；这里需要说明的是，埋入式字线结构130是埋入在衬底100内部的，俯视图中应该看不到，图21中为了便于理解埋入式字线结构130在衬底100中的形状位置，所以标注出了埋入式字线结构130。参考图20-图21，形成电容接触窗，去除第一介质层501顶部的电容接触金属层601，暴露第一介质层501的顶面。作为示例，以第一介质层501为研磨截止层，采用化学机械研磨工艺等平坦化工艺去除位于第一介质层501顶面的电容接触金属层601，暴露第一介质层501的顶面,形成电容接触窗。可以理解的是，也可以采用回刻工艺去除位于第一介质层501顶面的电容接触金属层601，以使电容接触金属层601的顶面与第一介质层501的顶面平齐。
本申请实施例提供的半导体结构的形成方法，通过形成位线结构后在有源区表面沉积第一牺牲层，第一牺牲层采用碳层，尤其是第三沟槽510底部的碳层更易去除，沉积的电容接触金属层601与有源区的接触面积更大，电性能更好，阻值更低。
本申请的第二方面提供了一种半导体结构，采用上述的半导体结构的形成方法制备得到。
可选的实施例中，半导体结构包括：衬底100，衬底100内具有多条字线结构130和有源区120，衬底100上具有位线连接柱140，位线连接柱140位于字线结构130间隔区域的上方；位线结构150，位线结构通过位线连接柱与有源区连接；电容接触窗，电容接触窗位于衬底100上，其包括第一介质层501和电容接触金属层601，电容接触金属层位于第一介质层之间构成的第三沟槽510内，电容接触金属层的底部与有源区完全连接。电容接触窗的顶面与位线结构150的顶面可平齐，也可具有一定的高度差。位线结构150与电容接触金属层601之间由第一介质层501隔离。
可选的实施例中，电容接触金属层的底部与有源区连接的接触面 积至少为电容接触金属层顶部的截面积的90％。
可选的实施例中，位线结构包括由下至上依次层叠设置的第一隔离介质层、导电层和第二隔离介质层，位线连接柱的两端分别与导电层和有源区连接。
可选的实施例中，导电层包括钨层。
可选的实施例中，电容接触金属层包括多晶硅层。
可选的实施例中，第一介质层的材料包括氮化硅或者碳氮化硅。
本申请的第三方面提供了一种存储器，包括上述的半导体结构。
应当理解的是，本申请的上述具体实施方式仅仅用于示例性说明或解释本申请的原理，而不构成对本申请的限制。因此，在不偏离本申请的精神和范围的情况下所做的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。此外，本申请所附权利要求旨在涵盖落入所附权利要求范围和边界、或者这种范围和边界的等同形式内的全部变化和修改例。

Claims (17)

  1. 一种半导体结构的形成方法，包括：
    提供衬底，所述衬底内具有多条字线结构和有源区，所述衬底上具有位线连接柱，所述位线连接柱位于所述字线结构间隔区域的上方；
    形成位线结构，所述位线结构通过所述位线连接柱与所述有源区连接；
    在所述衬底上形成第一牺牲层，使得所述第一牺牲层的顶面和所述位线结构的顶面平齐，所述第一牺牲层包括碳层；
    在所述第一牺牲层上形成第一沟槽，所述第一沟槽垂直于所述位线结构，所述第一沟槽暴露所述衬底；
    形成第一介质层，所述第一介质层填充第一沟槽及覆盖所述第一牺牲层的顶面；
    平坦化所述第一介质层，且暴露所述第一牺牲层的顶面；
    去除所述第一牺牲层，在相邻所述第一介质层之间形成暴露所述衬底的第三沟槽；
    形成电容接触金属层，所述电容接触金属层填充所述第三沟槽及覆盖所述第一介质层的顶面，所述电容接触金属层的底部与所述有源区完全连接。
  2. 根据权利要求1所述的半导体结构的形成方法，其中，在所述衬底上形成第一牺牲层包括：
    在形成位线结构之后在所述衬底上形成第一牺牲层，平坦化所述第一牺牲层，使得所述第一牺牲层的顶面和所述位线结构的顶面平齐。
  3. 根据权利要求2所述的半导体结构的形成方法，其中，在所述衬底上形成第一牺牲层还包括：
    在平坦化的所述第一牺牲层的顶面由下至上依次堆叠形成第二牺牲层、第二掩膜层和第二光刻胶层；
    在所述第二掩膜层和第二光刻胶层上形成第二沟槽，所述第二沟槽暴露所述第二牺牲层，所述第二沟槽垂直于所述位线结构。
  4. 根据权利要求3所述的半导体结构的形成方法，其中，在所述第二光刻胶层的顶面上和所述第二沟槽的内壁上形成第三牺牲层，所述第三牺牲层覆盖所述第二光刻胶层、第二掩膜层和所述第二沟槽；
    去除所述第二光刻胶层顶面及所述第二沟槽底部的所述第三牺牲层，形成侧墙层；
    去除所述第二光刻胶层和第二掩膜层。
  5. 根据权利要求4所述的半导体结构的形成方法，其中，以所述侧墙层为掩膜依次向下刻蚀所述第二牺牲层和所述第一牺牲层，形成所述第一沟槽；
    去除所述侧墙层；
    去除所述第二牺牲层，在所述第一牺牲层上形成所述第一沟槽。
  6. 根据权利要求4所述的半导体结构的形成方法，其中，形成电容接触金属层之后包括：
    形成电容接触窗，去除所述第一介质层顶部的所述电容接触金属层，暴露所述第一介质层的顶面。
  7. 根据权利要求4所述的半导体结构的形成方法，其中，采用氧气干法刻蚀工艺去除所述第一牺牲层。
  8. 根据权利要求4所述的半导体结构的形成方法，其中，所述电容接触金属层包括多晶硅层。
  9. 根据权利要求1所述的半导体结构的形成方法，其中，形成位线结构包括：
    在所述衬底上形成第一隔离介质层，使得第一隔离介质层的顶面和位线连接柱的顶面平齐；
    在第一隔离介质层的顶面和位线连接柱的顶面由下至上依次堆叠形成导电层、第二隔离介质层、第一掩膜层和第一光刻胶层，以第一光刻胶层的图案显影依次向下刻蚀第一掩膜层、第二隔离介质层、 导电层和第一隔离介质层，去除第一光刻胶层和第一掩膜层，形成位线结构。
  10. 一种半导体结构，采用如权利要求1-9任一项所述的半导体结构的形成方法制备得到。
  11. 根据权利要求10所述的半导体结构，其中，包括：
    衬底，所述衬底内具有多条字线结构和有源区，所述衬底上具有位线连接柱，所述位线连接柱位于所述字线结构间隔区域的上方；
    位线结构，所述位线结构通过所述位线连接柱与所述有源区连接；
    电容接触窗，所述电容接触窗位于所述衬底上，所述电容接触窗包括第一介质层和电容接触金属层，所述电容接触金属层位于所述第一介质层之间构成的第三沟槽内，所述电容接触金属层的底部与所述有源区完全连接。
  12. 根据权利要求11所述的半导体结构，其中，所述电容接触金属层的底部与所述有源区连接的接触面积至少为所述电容接触金属层顶部的截面积的90％。
  13. 根据权利要求11所述的半导体结构，其中，所述位线结构包括由下至上依次层叠设置的第一隔离介质层、导电层和第二隔离介质层，所述位线连接柱的两端分别与所述导电层和所述有源区连接。
  14. 根据权利要求13所述的半导体结构，其中，所述导电层包括钨层。
  15. 根据权利要求11所述的半导体结构，其中，所述电容接触金属层包括多晶硅层。
  16. 根据权利要求1所述的半导体结构，其中，所述第一介质层的材料包括氮化硅或者碳氮化硅。
  17. 一种存储器，包括如权利要求10-16任一项所述的半导体结构。
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