WO2023005235A1 - 阵列基板、显示模组及显示装置 - Google Patents

阵列基板、显示模组及显示装置 Download PDF

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Publication number
WO2023005235A1
WO2023005235A1 PCT/CN2022/082185 CN2022082185W WO2023005235A1 WO 2023005235 A1 WO2023005235 A1 WO 2023005235A1 CN 2022082185 W CN2022082185 W CN 2022082185W WO 2023005235 A1 WO2023005235 A1 WO 2023005235A1
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WIPO (PCT)
Prior art keywords
line
connection
area
array substrate
connection line
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PCT/CN2022/082185
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English (en)
French (fr)
Inventor
米磊
刘雨生
李洪瑞
Original Assignee
合肥维信诺科技有限公司
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Publication of WO2023005235A1 publication Critical patent/WO2023005235A1/zh
Priority to US18/342,061 priority Critical patent/US20230352391A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present application belongs to the field of display technology, and in particular relates to an array substrate, a display module and a display device.
  • the display device has a display area and a non-display area. There is a fan-shaped wiring area in the non-display area, and a large number of wirings are arranged in the fan-shaped wiring area. These wirings occupy a large space, resulting in a large width of the fan-shaped wiring area. A narrower bezel of the display device is realized.
  • Embodiments of the present application provide an array substrate, a display module, and a display device, which can realize a narrower frame of the display device.
  • an embodiment of the present application provides an array substrate.
  • the array substrate has a display area and a non-display area.
  • the non-display area includes a functional area.
  • the functional area and the display area are spaced apart in a first direction.
  • the array substrate includes: a first data line extending along the first direction in the central area, and a plurality of first data lines are distributed along the second direction at intervals;
  • the data lines extend along the first direction in the edge area, and a plurality of second data lines are distributed along the second direction at intervals;
  • the first connecting lines extend along the first direction between the central area and the functional area, and the first connecting lines
  • the wire is electrically connected to the first data line in one-to-one correspondence;
  • the second connection line is electrically connected to the second data line in a one-to-one correspondence, and the second connection line includes a first connection line segment and a second connection line segment distributed successively.
  • connection ports are electrically connected to the driving integrated circuit chip.
  • an embodiment of the present application provides a display module, including the array substrate of the first aspect.
  • the embodiment of the present application provides a display device, including the display module of the second aspect.
  • the present application provides an array substrate, a display module and a display device.
  • the array substrate includes a first data line located in a central area and a second data line located in an edge area.
  • the first data line is connected to the functional area through the first connection line.
  • the second data line is connected to the functional area through the second connection line.
  • the second connection line includes a first connection line segment and a second connection line segment.
  • the first connecting line segment is a bending line extending in the display area, and the second connecting line segment extends along the first direction between the central area and the functional area.
  • Both the first connection line and the second connection line segment between the central area and the functional area extend along the first direction, and do not form a fan-shaped routing area, nor are they limited by the shape of the fan-shaped routing area.
  • the line change connection unit can make the second data line pass through the second connection line and the line change connection unit, and electrically connect the connection ports arranged in the corresponding order according to the arrangement order of the second data lines, without affecting the central area and the functional area
  • the distance between the central area and the functional area can be further compressed, and a narrower frame of the display device can be realized.
  • FIG. 1 is a schematic top view of an example of a display device
  • FIG. 2 is a schematic structural diagram of an embodiment of an array substrate provided by the present application.
  • Fig. 3 is a partial enlarged view of area Q1 in Fig. 2;
  • FIG. 4 is a schematic structural diagram of another embodiment of the array substrate provided by the present application.
  • Fig. 5 is a partially enlarged view of area Q2 in Fig. 4;
  • Fig. 6 is a schematic diagram of an example of the connection between the line change connection unit and the second connection line provided by the embodiment of the present application;
  • Fig. 7 is a schematic diagram of another example of the connection between the line change connection unit and the second connection line provided by the embodiment of the present application;
  • FIG. 8 is a schematic diagram of an example of a first connecting line segment provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of another embodiment of the array substrate provided by the present application.
  • Fig. 10 is a partially enlarged view of area Q3 in Fig. 9;
  • FIG. 11 is a schematic structural diagram of yet another embodiment of the array substrate provided by the present application.
  • Fig. 12 is a partially enlarged view of area Q4 in Fig. 11;
  • FIG. 13 is a schematic structural diagram of yet another embodiment of the array substrate provided by the present application.
  • Fig. 14 is a partially enlarged view of area Q5 in Fig. 13;
  • Fig. 15 is a schematic diagram of a side section of an example of a display module provided by an embodiment of the present application.
  • FIG. 16 is a schematic diagram of a side section of another example of a display module provided by an embodiment of the present application.
  • FIG. 17 is a schematic diagram of a side section of another example of a display module provided by an embodiment of the present application.
  • the display device has a display area AA and a non-display area NA.
  • a fan-shaped wiring area 11 is provided, that is, the wiring in the non-display area NA can form a trapezoidal area.
  • a large number of wires are arranged in the fan-shaped routing area 11.
  • the width d1 of the fan-shaped routing area 11 is limited by the shape of the fan-shaped routing area 11 and cannot be continuously reduced, that is, the fan-shaped routing area
  • the width d1 of 11 is relatively large, resulting in a large width of the non-display area, which makes the frame of the display device, especially the width d2 of the bottom frame, unable to be further compressed, making it difficult to achieve a narrower frame of the display device.
  • the present application provides an array substrate, a display module, and a display device.
  • the width of the non-display area can be further shortened, thereby further compressing the frame of the display device to realize a display device with a narrower frame.
  • the array substrate has a display area 21 and a non-display area 22 .
  • the non-display area 22 includes a functional area 23 .
  • the functional area 23 is spaced apart from the display area 21 in the first direction.
  • the display area includes a central area 211 and an edge area 212 located on at least one side of the central area 211 along the second direction.
  • the functional area 23 may include parts and areas that realize certain functions or functions, which is not limited here.
  • the display module including the array substrate adopts a COP package, that is, a Chip On Pi package, or a COF package, that is, a Chip On Film package, and the functional area 23 may include a bending area, that is, a bending area.
  • the display module including the array substrate adopts the COG packaging method, that is, the Chip On Glass packaging method, and the functional area 23 may include an IC chip.
  • the first direction and the second direction in the above embodiments are different, and may form a certain angle.
  • the first direction and the second direction are perpendicular to each other.
  • the first direction may be the column direction of the pixel units in the display area
  • the second direction may be the row direction of the pixel units in the display area.
  • the edge area 212 can be located on one side of the central area 211 along the second direction, or can be located on both sides of the central area 211 along the second direction. That is, the central area 211 may be provided with one edge area 212 or two edge areas 212 correspondingly, which is not limited here.
  • the edge area 212 is an area where the central area 211 protrudes relative to the functional area 23 along the second direction. That is, the projection of the central area 211 along the first direction coincides with the projection of the functional area 23 along the first direction. The projection of the edge area 212 along the first direction does not coincide with the projection of the functional area 23 along the first direction.
  • the array substrate may include a first data line 24 , a second data line 25 , a first connection line 26 , a second connection line 27 and a line-switching connection unit 32 .
  • the first data line 24 extends along the first direction in the central region 211 . And a plurality of first data lines 24 are distributed at intervals along the second direction.
  • the number of the first data lines 24 in FIG. 2 and FIG. 3 is only for illustration, and in actual situations, the number of the first data lines 24 in the central area 211 will be more.
  • the resolution of the display device including the array substrate is 2340*1080, and the number of the first data lines 24 may be 1440.
  • the second data line 25 extends along the first direction in the edge area 212 . And a plurality of second data lines 25 are distributed at intervals along the second direction.
  • the numbers of the second data lines 25 in FIG. 2 and FIG. 3 are only for illustration, and in actual situations, the number of the second data lines 25 in the edge area 212 will be more.
  • the resolution of the display device including the array substrate is 2340*1080, and the number of the second data lines 25 may be 720.
  • the first data line 24 and the second data line 25 can provide data signals for the pixel units in the display area 21 .
  • the first connection line 26 extends along a first direction between the central area 211 and the functional area 23 .
  • the first connection line 26 is electrically connected to the first data line 24 in a one-to-one correspondence.
  • the first data line 24 is connected to the functional area 23 through the first connection line 26 .
  • the first data line 24 and the first connection line 26 can be integrally formed.
  • the second connection line 27 is located in the display area AA and between the display area AA and the functional area 23 .
  • the second connection line 27 is electrically connected to the second data line 25 in a one-to-one correspondence.
  • the second data line 25 is connected to the functional area 23 through the second connection line 27 .
  • the second connection line 27 may include a first connection line segment 271 and a second connection line segment 272 distributed continuously, and the first connection line segment 271 is electrically connected to the second connection line segment 272 . That is, a first connecting line segment 271 and a second connecting line segment 272 form a second connecting line 27 . Specifically, one end of the first connecting line segment 271 is electrically connected to the second data line 25, the other end of the first connecting line segment 271 is electrically connected to one end of the second connecting line segment 272, and the other end of the second connecting line segment 272 is electrically connected to the functional Area 23.
  • the first connecting line segment 271 is a bending line extending in the display area 21 , and the first connecting line segment 271 can be bent once or multiple times in the display area 21 , which is not limited herein.
  • the first connecting line segment 271 may pass through the edge area 212 and the central area 211 .
  • the first connecting line segment 271 shown in FIG. 2 and FIG. 3 is bent once in the display area.
  • the first connecting line segment 271 can be bent multiple times in the display area.
  • the second connecting line segment 272 extends along the first direction between the central area 211 and the functional area 23 .
  • the first data line 24 can be electrically connected to the connection port through the first connection line 26 , or can be electrically connected to the connection port through the first connection line 26 and other structures.
  • the connection port is electrically connected with the driver integrated circuit chip, that is, the driver IC chip.
  • the second data line 25 may be electrically connected to the driver integrated circuit chip through the second connection line 27, or electrically connected to the driver integrated circuit chip through the second connection line 27 and other structures.
  • the arrangement order of the first connection line 26 and the second connection line 27 is different from the arrangement order of the first data line 24 and the second data line 25 in the display area 21, and the driving integrated circuit
  • the arrangement order of the output pins of the chip is generally consistent with the arrangement order of the first data line 24 and the second data line 25 in the display area 21, and the arrangement order of the connection ports is consistent with the arrangement order of the output pins of the driver integrated circuit chip.
  • the line change connection unit 32 in the array substrate is configured to be electrically connected to the second connection line 27 and the connection port, for allowing the second data line 25 to pass through the second connection line 27 and the line change connection unit 32, according to the second data line
  • the arrangement sequence of 25 is electrically connected with the connection ports arranged in corresponding order.
  • the cable change connection unit can be disposed between the display area 21 and the connection port.
  • Both the first connection line 26 and the second connection line segment 272 between the central area 211 and the functional area 23 extend along the first direction, and do not form a fan-shaped routing area, and will not be limited by the shape of the fan-shaped routing area.
  • the distance d3 between 211 and the functional area 23 can be further compressed, and correspondingly, the width d4 of the lower frame of the display device including the array substrate can be further shortened.
  • d3 in Figure 3 is shorter than d1 in Figure 1
  • d4 in Figure 3 is shorter than d2 in Figure 1.
  • the array substrate includes a first data line 24 located in a central area 211 and a second data line 25 located in an edge area 212 .
  • the first data line 24 is connected to the functional area 23 through the first connection line 26 .
  • the second data line 25 is connected to the functional area 23 through the second connection line 27 .
  • the second connection line 27 includes a first connection line segment 271 and a second connection line segment 272 .
  • the first connecting line segment 271 is a bending line extending in the display area 21
  • the second connecting line segment 272 extends along the first direction between the central area 211 and the functional area 23 .
  • Both the first connection line 26 and the second connection line segment 272 between the central area 211 and the functional area 23 extend along the first direction, and do not form a fan-shaped routing area, and are not limited by the shape of the fan-shaped routing area.
  • the line change connection unit 32 can make the second data line 25 pass through the second connection line 27 and the line change connection unit 32, and be electrically connected to the connection ports arranged in the corresponding order according to the arrangement order of the second data line 25, without affecting The distance between the central area 211 and the functional area 23 can be further compressed to achieve a narrower frame of the display device.
  • the distance between the display area and the functional area in the display device is about 1.0 mm, and the width of the lower frame of the display device is about 2.5 mm to 3 mm, while the display device including the array substrate in the embodiment of the present application displays
  • the distance between the area and the functional area can be shortened by about 0.5 mm or less, and the width of the lower frame of the display device can be shortened to 2 mm or even less than 2 mm.
  • the correct electrical connection between the second data line 25 and the connection port can be realized by changing the line connection unit 32, that is, the order of the second connection line 27 can be sorted into the correct order, which can correspond to the normal order of the connection port, without changing the original
  • the arrangement order of some connection ports does not require the development and replacement of a new driver integrated circuit chip, which avoids the increase of the cost of the array substrate, display module and display device, and can perform conventional wiring operations.
  • the wire change connection unit 32 may include a wire change connection wire 321 .
  • the wire-changing connecting wires 321 are electrically connected to the second connecting wires 27 in one-to-one correspondence, and are electrically connected to the connecting ports of the connected second connecting wires 27 in a corresponding sequence.
  • the second data line 25 is directly connected to the line change connection unit 32 through the second connection line 27 as an example for illustration.
  • the black squares represent connection ports, specifically including connection ports A1 to A360 , and the connection ports A1 to A360 correspond to the second data lines D1 to D360 respectively.
  • the second connecting line 27 bends and extends in the display area, the second connecting line segment 272 is located between two adjacent first connecting lines 26, and the second connecting line segment corresponds to the second data from left to right in Fig. 6 Lines 25 are D360 to D1 respectively.
  • the label of the second data line corresponding to the second connection line segment is indicated, and above the first connection line 26, the number of the first data line corresponding to the first connection line is indicated. Numbers, the first data lines are D361 to D1080, but only part of the second connecting line segment 272 and the first connecting line 26 are shown in FIG. 6 .
  • the second connecting line 27 corresponding to the second data line 25 is electrically connected to the connection port through a plurality of switching connecting lines 321 .
  • the second connection line segments corresponding to the second data lines D360 to D1 are connected to the connection ports A1 to A360 through a plurality of changeover connection lines 321, and the second connection line segments corresponding to the second data lines D1 are connected through the changeover connection lines 321
  • the second connection line segment corresponding to the second data line D2 is connected to the connection port A2 through the line-changing connection line 321
  • the second connection line segment corresponding to the second data line D3 is connected to the connection port A2 through the line-changing connection line 321.
  • Port A3, and so on, the second connecting line segment corresponding to the second data line D360 is connected to the connecting port A360 through the wire-changing connecting line 321 .
  • the line change connection line 321 includes a first line change connection line segment 3211 extending along the second direction and a second line change connection line segment 3212 extending along the first direction.
  • the two ends of the first wire changing connecting line segment 3211 are respectively electrically connected to the second connecting wire 27 and the second wire changing connecting line segment 3212, and the second wire changing connecting line segment 3212 is electrically connected to the connection port.
  • Capacitance will be generated between the wire-changing connecting wire 321 and other structures in the array substrate, and the resistance of the wire-changing connecting wire 321 itself will also have certain influence on signal transmission.
  • the capacitances generated by each changing connecting line 321 and other structures in the array substrate tend to be consistent, and The respective resistances of the wire-changing connecting lines 321 are also tended to be consistent, which can reduce the difference between the lengths of the wire-changing connecting wires 321 . As shown in FIG.
  • the first line-changing connecting line segment 3211 may extend in the direction from the edge area 212 to the central area 211, and exceed the second connecting line 27 closest to the center of the central area 211, so that each line-changing connecting line
  • the absolute value of the difference between the lengths of 321 is smaller than the acceptable influence length threshold, and the wiring is more uniform.
  • the array substrate may further include a compensation line. As shown in FIG. 7 , the compensation line 33 is electrically connected to the first connection line 26 .
  • the compensation line 33 is located between the connection port and the driving integrated circuit chip, and extends along the first direction.
  • the difference between the capacitance of the second data line 25 and the second connection line 27 and the capacitance of the first data line 24, the first connection line 26 and the compensation line 33 is small, and the capacitance of the second data line 25 and the second connection line 27
  • the difference between the resistance and the resistance of the first data line 24, the first connection line 26 and the compensation line 33 is also small, thereby reducing or avoiding the difference in signal transmission caused by the capacitance and resistance of different wirings being too large, so that each The capacitances generated by each of the traces and other structures in the array substrate tend to be consistent, and the resistance of each trace is also tended to be consistent, thereby improving the signal transmission effect and further improving the display effect.
  • the first connecting line segment in order to shorten the length of the second connecting line 27 , may be a bending line bent once in the display area.
  • the first connecting line segment 271 includes a first connecting sub-line segment 2711 extending along the second direction and a second connecting sub-line segment 2712 extending along the first direction.
  • the first connection sub-segment 2711 is electrically connected to the second connection sub-segment 2712 . Reducing the number of times of bending of the first connection line segment 271 can shorten the length of the second connection line 27, thereby reducing the resistance value, capacitance, etc.
  • a portion of at least one first connecting line segment 271 extending along the first direction is located between two adjacent first data lines 24 . That is, a portion of at least one first connecting line segment 24 extending along the first direction may be provided between two adjacent first data lines 24 . Due to the large number of second data lines 25 located in the edge area 212, if only one first connecting line segment 271 extending along the first direction is set between two adjacent first data lines 25, passing through the central area 211 The difference between the length of the first connecting line segment 271 between two adjacent first data lines 24 in the center of will be larger, that is, the lengths of the multiple first connecting line segments 271 differ greatly, and the uniformity is poor.
  • the parts extending along the first direction of more than two first connecting line segments 271 can be located in adjacent Between two first data lines 24 , that is, between two adjacent first data lines 24 , more than two first connecting line segments 271 may be provided with portions extending along the first direction. As shown in FIG. 9 and FIG. 10 , the parts of the two first connection line segments 271 extending along the first direction are located between two adjacent first data lines 24 . That is, the portions of the two first connecting line segments 271 extending along the first direction are disposed between two adjacent first data lines 24 .
  • the distance between the portion of the first connecting line segment 271 extending along the first direction and the adjacent first data line 24 is smaller than the distance between two adjacent data lines.
  • the distance between the first connecting line segment and the boundary of the pixel unit formed by the data line is equal to or smaller than the size of the pixel unit, that is, pixel pitch.
  • each first connecting line segment 271 may include a first connecting sub-line segment 2711 extending along the second direction and a second connecting sub-line segment extending along the first direction 2712 , at least one second connection sub-line segment 2712 is located between two adjacent first data lines 24 , that is, at least one second connection sub-line segment 2712 is disposed between two adjacent first data lines 24 .
  • the two second connecting sub-line segments 2712 are located between two adjacent first data lines 24, that is, two adjacent first data lines 24 are provided with two second Connect sub-segments 2712.
  • the functional area 23 includes a bending area 231 ie a bending area.
  • the first connecting line 26 and the second connecting line 27 extend into the bending area 231 along the first direction.
  • the part of the first connecting line 26 in the bending area 231 and the part of the second connecting line 27 in the bending area 231 both extend along the first direction.
  • the first connection line 26 and the second connection line 27 extend into the bending area 231 and extend along the first direction in the bending area 231 .
  • the functional area 23 includes a bending area 231 ie a bending area.
  • the array substrate may further include a third connection line 28 .
  • the size of the bending area 231 can be specifically set according to the requirements of the array substrate, and the length of the functional area 23 along the second direction can be set to be longer than the length of the bending area 231 along the second direction.
  • the bending area 231 is located in the functional area 23 , and there is a certain distance between the bending area 231 and the side of the functional area 23 close to the central area 211 .
  • the third connection line 28 is located between the bending area 231 and the side of the functional area 23 close to the central area 211 . Two ends of the third connection line 28 are respectively electrically connected to the second connection line segment 272 and the first connection line 26 in a one-to-one correspondence.
  • the area where the plurality of third connection lines 28 are located on the array substrate forms a fan-shaped wiring area 29 .
  • the third connecting wire 28 electrically connected to the second connecting wire segment 272 can be integrally formed, and the third connecting wire 28 electrically connected to the first connecting wire 26 can be integrally formed.
  • Setting the length of the functional area 23 along the second direction to be longer than the length of the bent area 231 along the second direction can minimize the number of second data lines 25, thereby reducing the number of second connection lines 27, so that the first data
  • the voltage and current of the data signal transmitted by the line 24 and the second data line 25 are more uniform, reducing the load difference caused by the first connection line 26 and the second connection line 27 when the lengths are different, and ensuring that the display including the array substrate The display effect of the device.
  • the length of the upper bottom edge of the fan-shaped wiring area 29 formed by the third connecting wire 28, that is, the bottom edge adjacent to the side of the functional area 23 close to the central area 211, is shorter,
  • the shorter upper base length makes the width of the fan-shaped wiring area 29 shorter than the width of the fan-shaped wiring area 11 in FIG.
  • the width of the fan-shaped wiring area 11 is smaller, and the array substrate of the embodiment of the present application can still further shorten the width of the non-display area NA, thereby further reducing the frame width of the display device, especially reducing the width of the lower frame.
  • the array substrate may further include a fourth connection line 30 .
  • the fourth connection line 30 may be located in the bending area 231 and extend along the first direction.
  • the fourth connecting wire 30 can be electrically connected to the third connecting wire 28 in one-to-one correspondence.
  • the second data line 25 can be connected to the connection port according to the arrangement sequence of the second data line 25 through the second connection line 27, other structures and the line-changing connection unit 32, so as to realize the correspondence with the driver integrated circuit chip.
  • the output pins are electrically connected.
  • Other structures can be determined according to the specific structure of the array substrate, and are not limited here.
  • the second data line 25 can pass through the second connection line 27, the third connection line 28 and the line-changing connection unit 32, and connect with the second data line 25 according to the arrangement sequence of the second data line 25.
  • the connection port is electrically connected.
  • the second data line 25 can be connected through the second connection line 27, the third connection line 28, the fourth connection line 30 and the replacement line.
  • the units 32 are electrically connected to the connection ports according to the arrangement sequence of the second data lines 25 .
  • the second connection line 27 and the second data line 25 may be disposed on the same layer, that is, the second connection line 27 and the second data line 25 may be located on the same metal layer.
  • the array substrate may include a first metal layer M1 , a second metal layer M2 , a third metal layer M3 and a fourth metal layer M4 .
  • the first metal layer M1 , the second metal layer M2 , the third metal layer M3 and the fourth metal layer M4 are often used as signal line metal layers.
  • first data line 24 and the second data line 25 may be located in the third metal layer M3 and/or the fourth metal layer M4, and correspondingly, the second connection line 27 may also be located in the third metal layer M3 and/or Or the fourth metal layer M4.
  • the second connecting line 27 and the second data line 25 are not arranged in the same layer.
  • the second connection line 27 is located on the target metal layer, and the target metal layer may be located between the substrate and the active layer.
  • a metal layer ie, a target metal layer, can be added to the array substrate to realize the second connection line.
  • a metal layer including the first data line 24 and the second data line 25 may be located between the active layer and the anode metal layer.
  • the second connection line 27 and the second data line 25 are not arranged in the same layer, so that the wiring of the second connection line in the display area is more free and flexible. In the case that the second connection line 27 and the second data line 25 are not arranged in the same layer, the second connection line 27 and the second data line 25 can be electrically connected through a through hole.
  • the application also provides a display module.
  • the display module may include the array substrate in the above embodiments.
  • the display module in the embodiment of the present application may be a display module adopting a COP packaging method, a COF packaging method or a COG packaging method, which is not limited herein.
  • the display module is packaged in COG.
  • the display module has a display area 41 and a non-display area 42 .
  • the non-display area 42 includes a functional area 43 .
  • the driver integrated circuit chip 31 is located in the functional area 43 .
  • the distance L1 between the display area 41 and the functional area 43 in FIG. 15 is substantially the same as the distance d3 shown in FIGS. 2 , 4 and 9 .
  • the distance d3 between the display area 21 and the functional area 23 of the array substrate can be further shortened, and correspondingly, the distance L1 between the display area 41 and the functional area 43 of the display module can be further shortened, so that the display module can be further compressed.
  • the frame width can realize a narrower frame of the display module.
  • the display module adopts COF packaging.
  • the display module has a display area 41 and a non-display area 42 .
  • the non-display area 42 includes a functional area 43 .
  • the functional area 43 may specifically include the bending area in the above-mentioned embodiments.
  • the driving integrated circuit chip 31 is located on the cable bent to the back of the array substrate.
  • the distance L1 between the display area 41 and the functional area 43 in FIG. 16 is substantially the same as the distance d3 shown in FIGS. 2 , 4 , 9 and 11 .
  • the distance d3 between the display area 21 and the functional area 23 of the array substrate can be further shortened, and correspondingly, the distance L1 between the display area 41 and the functional area 43 of the display module can be further shortened, so that the display module can be further compressed.
  • the frame width can realize a narrower frame of the display module.
  • the display module adopts a COP package.
  • the display module has a display area 41 and a non-display area 42 .
  • the non-display area 42 includes a functional area 43 .
  • the functional area 43 may specifically include the bending area in the above-mentioned embodiments.
  • the array substrate is a flexible array substrate that can be bent to the back, and the driving integrated circuit chip 31 is located on the flexible array substrate bent to the back.
  • the distance L1 between the display area 41 and the functional area 43 in FIG. 17 is substantially the same as the distance d3 shown in FIGS. 2 , 4 , 9 and 11 .
  • the distance d3 between the display area 21 and the functional area 23 of the array substrate can be further shortened, and correspondingly, the distance L1 between the display area 41 and the functional area 43 of the display module can be further shortened, so that the display module can be further compressed.
  • the frame width can realize a narrower frame of the display module.
  • the present application also provides a display device.
  • the display device includes the display module in the above embodiments.
  • the display device may specifically be a mobile phone, a computer, a tablet computer, a TV, an electronic paper, and other devices with a display function, which are not limited herein.

Abstract

一种阵列基板、显示模组及显示装置，属于显示技术领域。阵列基板包括第一数据线（24），在中心区域（211）沿第一方向延伸；第二数据线（25）在边缘区域（212）沿第一方向延伸；第一连接线（26），在中心区域（211）与功能区域（23）之间沿第一方向延伸，第一连接线（26）与第一数据线（24）一一对应电连接；第二连接线（27），与第二数据线（25）一一对应电连接，包括相继分布的第一连接线段（271）和第二连接线段（272），第一连接线段（271）为在显示区（21）延伸的弯折线，第二连接线段（272）在中心区域（211）与功能区域（23）之间沿第一方向延伸；换线连接单元（32）与第二连接线（27）和连接端口电连接，使第二数据线（25）通过第二连接线（27）和换线连接单元（32）按照第二数据线（25）的排列顺序与连接端口电连接。

Description

阵列基板、显示模组及显示装置
相关申请的交叉引用
本申请要求享有于2021年7月26日提交的名称为“阵列基板、显示模组及显示装置”的中国专利申请202110846778.4的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本申请属于显示技术领域，尤其涉及一种阵列基板、显示模组及显示装置。
背景技术
随着显示技术的发展，用户对显示装置的屏占比要求越来越高，窄边框设计已经成为了显示装置的一大发展趋势。
显示装置具有显示区和非显示区。非显示区中设置有扇形走线区，扇形走线区中设置有大量走线，这些走线占据的空间较大，导致扇形走线区的宽度较大，无法进一步压缩显示装置的边框，难以实现显示装置的更窄边框。
发明内容
本申请实施例提供一种阵列基板、显示模组及显示装置，能够实现显示装置的更窄边框。
第一方面，本申请实施例提供一种阵列基板，阵列基板具有显示区和非显示区，非显示区包括功能区域，功能区域与显示区在第一方向间隔分布，显示区包括中心区域和位于中心区域沿第二方向上的至少一侧的边缘区域，阵列基板包括：第一数据线，在中心区域，沿第一方向延伸，且多条第一数据线沿第二方向间隔分布；第二数据线，在边缘区域，沿第一方 向延伸，且多条第二数据线沿第二方向间隔分布；第一连接线，在中心区域与功能区域之间，沿第一方向延伸，第一连接线与第一数据线一一对应电连接；第二连接线，与第二数据线一一对应电连接，第二连接线包括相继分布的第一连接线段和第二连接线段，第一连接线段为在显示区延伸的弯折线，第二连接线段在中心区域与功能区域之间沿第一方向延伸；换线连接单元，被配置为与第二连接线和连接端口电连接，用于使第二数据线通过第二连接线和换线连接单元，按照第二数据线的排列顺序与对应顺序排列的连接端口电连接，连接端口与驱动集成电路芯片电连接。
第二方面，本申请实施例提供一种显示模组，包括第一方面的阵列基板。
第三方面，本申请实施例提供一种显示装置，包括第二方面的显示模组。
本申请提供一种阵列基板、显示模组及显示装置，阵列基板包括位于中心区域的第一数据线和位于边缘区域的第二数据线。第一数据线通过第一连接线连接至功能区域。第二数据线通过第二连接线连接至功能区域。第二连接线包括第一连接线段和第二连接线段。第一连接线段为在显示区延伸的弯折线，第二连接线段在中心区域与功能区域之间沿第一方向延伸。中心区域与功能区域之间的第一连接线和第二连接线段均沿第一方向延伸，并没有形成扇形走线区，也不会受到扇形走线区形状的限制。而且，换线连接单元可使第二数据线通过第二连接线和换线连接单元，按照第二数据线的排列顺序与对应顺序排列的连接端口电连接，并不会影响中心区域与功能区域之间的距离，中心区域与功能区域之间的距离可进一步压缩，能够实现显示装置的更窄边框。
附图说明
图1为显示装置的一示例的俯视示意图；
图2为本申请提供的阵列基板的一实施例的结构示意图；
图3为图2中区域Q1的局部放大图；
图4为本申请提供的阵列基板的另一实施例的结构示意图；
图5为图4中区域Q2的局部放大图；
图6为本申请实施例提供的换线连接单元与第二连接线连接的一示例的示意图；
图7为本申请实施例提供的换线连接单元与第二连接线连接的另一示例的示意图；
图8为本申请实施例提供的第一连接线段的一示例的示意图；
图9为本申请提供的阵列基板的又一实施例的结构示意图；
图10为图9中区域Q3的局部放大图；
图11为本申请提供的阵列基板的再一实施例的结构示意图；
图12为图11中区域Q4的局部放大图；
图13为本申请提供的阵列基板的又另一实施例的结构示意图；
图14为图13中区域Q5的局部放大图；
图15为本申请实施例提供的显示模组的一示例的侧截面的示意图；
图16为本申请实施例提供的显示模组的另一示例的侧截面的示意图；
图17为本申请实施例提供的显示模组的又一示例的侧截面的示意图。
具体实施方式
下面将详细描述本申请的各个方面的特征和示例性实施例，为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及具体实施例，对本申请进行进一步详细描述。
随着显示技术的发展，用户对显示装置的屏占比要求越要越高，显示装置窄边框设计已经成为了一大发展趋势。如图1所示，显示装置具有显示区AA和非显示区NA。在非显示区NA中设置有扇形走线区11，即非显示区NA中的走线可形成一个梯形区域。扇形走线区11中设置有大量走线，在走线数量非常大的情况下，扇形走线区11的宽度d1受到扇形走线区11形状的限制，不能继续减小，即扇形走线区11的宽度d1较大，导致非显示区的宽度较大，进而使得显示装置的边框尤其是下边框的宽度d2 无法进一步压缩，难以实现显示装置更窄的边框。
本申请提供一种阵列基板、显示模组及显示装置，通过调整数据线的走线，使得非显示区的宽度能够进一步缩短，从而进一步压缩显示装置的边框，以实现边框更窄的显示装置。
如图2和图3所示，该阵列基板具有显示区21和非显示区22。非显示区22包括功能区域23。功能区域23与显示区21在第一方向间隔分布。显示区包括中心区域211和位于中心区域211沿第二方向上的至少一侧的边缘区域212。
功能区域23可包括实现某种或某些功能的部件和区域，在此并不限定。例如，包括阵列基板的显示模组采用COP封装方式即Chip On Pi封装方式或COF封装方式即Chip On Film封装方式，功能区域23可包括弯折区域即bending区域。又例如，包括阵列基板的显示模组采用COG封装方式即Chip On Glass封装方式，功能区域23可包括IC芯片。
上述实施例中的第一方向和第二方向不同，可呈一定角度。在一些示例中，第一方向与第二方向相互垂直。在一些示例中，第一方向可为显示区中像素单元的列方向，第二方向可为显示区中像素单元的行方向。
边缘区域212可位于中心区域211沿第二方向上的一侧，也可位于中心区域211沿第二方向上的两侧。即中心区域211可对应设置有一个边缘区域212或两个边缘区域212，在此并不限定。在一些示例中，边缘区域212为中心区域211沿第二方向相对于功能区域23凸出的区域。即中心区域211沿第一方向的投影与功能区域23沿第一方向的投影重合。边缘区域212沿第一方向的投影与功能区域23沿第一方向的投影不重合。
阵列基板可包括第一数据线24、第二数据线25、第一连接线26、第二连接线27和换线连接单元32。
第一数据线24在中心区域211，沿第一方向延伸。且多条第一数据线24沿第二方向间隔分布。图2和图3中的第一数据线24的数量只是示意，在实际情况中，中心区域211中的第一数据线24的数量会更多。例如，包括阵列基板的显示装置的分辨率为2340*1080，第一数据线24的数量可为1440条。
第二数据线25在边缘区域212，沿第一方向延伸。且多条第二数据线25沿第二方向间隔分布。图2和图3中的第二数据线25的数量只是示意，在实际情况中，边缘区域212中的第二数据线25的数量会更多。例如，包括阵列基板的显示装置的分辨率为2340*1080，第二数据线25的数量可为720条。
第一数据线24与第二数据线25可为显示区21中的像素单元提供数据信号。
第一连接线26在中心区域211与功能区域23之间，沿第一方向延伸。第一连接线26与第一数据线24一一对应电连接。第一数据线24通过第一连接线26连接至功能区域23。第一数据线24与第一连接线26可一体成型。
第二连接线27位于显示区AA以及显示区AA与功能区域23之间。第二连接线27与第二数据线25一一对应电连接。第二数据线25通过第二连接线27连接至功能区域23。
第二连接线27可包括连续分布的第一连接线段271和第二连接线段272，第一连接线段271与第二连接线段272电连接。即一条第一连接线段271和一条第二连接线段272形成一条第二连接线27。具体地，第一连接线段271的一端与第二数据线25电连接，第一连接线段271的另一端与第二连接线段272的一端电连接，第二连接线段272的另一端电连接至功能区域23。
第一连接线段271为在显示区21延伸的弯折线，第一连接线段271在显示区21中可一次弯折或多次弯折，在此并不限定。第一连接线段271可经过边缘区域212和中心区域211。图2和图3所示的第一连接线段271在显示区中一次弯折。
如图4和图5所示，第一连接线段271在显示区中可多次弯折。
第二连接线段272在中心区域211与功能区域23之间沿第一方向延伸。
第一数据线24可通过第一连接线26与连接端口电连接，或通过第一连接线26和其他结构与连接端口电连接。连接端口与驱动集成电路芯片 即驱动IC芯片电连接。第二数据线25可通过第二连接线27与驱动集成电路芯片电连接，或通过第二连接线27和其他结构与驱动集成电路芯片电连接。由于第二连接线27弯折延伸，因此第一连接线26、第二连接线27的排列顺序与显示区21中第一数据线24、第二数据线25的排列顺序不同，而驱动集成电路芯片的输出引脚的排列顺序一般与显示区21中第一数据线24、第二数据线25的排列顺序一致，连接端口的排列顺序与驱动集成电路芯片的输出引脚的排列顺序一致，为了使数据信号能够通过第一连接线26和第二连接线27传输至正确的第一数据线24和第二数据线25，需要对阵列基板进行改进。阵列基板中的换线连接单元32被配置为与第二连接线27和连接端口电连接，用于使第二数据线25通过第二连接线27和换线连接单元32，按照第二数据线25的排列顺序与对应顺序排列的连接端口电连接。换线连接单元可设置于显示区21与连接端口之间。
中心区域211与功能区域23之间的第一连接线26和第二连接线段272均沿第一方向延伸，并没有形成扇形走线区，也不会受到扇形走线区形状的限制，中心区域211与功能区域23之间的距离d3可进一步压缩，对应地，包括阵列基板的显示装置的下边框的宽度d4可进一步缩短。图3中的d3要短于图1中的d1，图3中的d4要短于图1中的d2。
在本申请实施例中，阵列基板包括位于中心区域211的第一数据线24和位于边缘区域212的第二数据线25。第一数据线24通过第一连接线26连接至功能区域23。第二数据线25通过第二连接线27连接至功能区域23。第二连接线27包括第一连接线段271和第二连接线段272。第一连接线段271为在显示区21延伸的弯折线，第二连接线段272在中心区域211与功能区域23之间沿第一方向延伸。中心区域211与功能区域23之间的第一连接线26和第二连接线段272均沿第一方向延伸，并没有形成扇形走线区，也不会受到扇形走线区形状的限制。而且，换线连接单元32可使第二数据线25通过第二连接线27和换线连接单元32，按照第二数据线25的排列顺序与对应顺序排列的连接端口电连接，并不会影响中心区域211与功能区域23之间的距离，中心区域211与功能区域23之间的距离可进一步压缩，能够实现显示装置更窄的边框。
例如，现阶段显示装置中显示区与功能区域之间的距离为1.0毫米左右，显示装置的下边框宽度在2.5毫米至3毫米左右，而包括本申请实施例中的阵列基板的显示装置中显示区与功能区域之间的距离可再缩短0.5毫米左右或更小，显示装置的下边框的宽度可缩短至2毫米甚至2毫米以下。
而且，通过换线连接单元32能够实现第二数据线25与连接端口正确的电连接，即将第二连接线27的顺序梳理为正确的顺序，能够与连接端口的正常顺序对应，不需要更改原有的连接端口的排列顺序，也不需要研发更换新的驱动集成电路芯片，避免了阵列基板、显示模组和显示装置成本的增加，可进行常规的布线操作。
在一些示例中，换线连接单元32可包括换线连接线321。如图2、图3、图4和图5所示，换线连接线321与第二连接线27一一对应电连接，且与连接的第二连接线27对应顺序的连接端口电连接。
为了便于说明，下面以第二数据线25通过第二连接线27直接与换线连接单元32连接为例进行说明。如图6所示，黑色方块表示连接端口，具体包括连接端口A1至A360，连接端口A1至A360分别与第二数据线D1至D360一一对应。但由于第二连接线27在显示区中弯折延伸，第二连接线段272位于相邻两条第一连接线26之间，图6中第二连接线段由左向右分别对应的第二数据线25分别为D360至D1。为了便于说明，在第二连接线段272上方注明了该第二连接线段对应的第二数据线的标号，在第一连接线26上方注明了该第一连接线对应的第一数据线的标号，第一数据线为D361至D1080，但图6中只示出了部分第二连接线段272和第一连接线26。通过多条换线连接线321使与第二数据线25对应的第二连接线27与连接端口电连接。与第二数据线D360至D1对应的第二连接线段通过多条换线连接线321连接至连接端口A1至A360，且与第二数据线D1对应的第二连接线段通过换线连接线321连接至连接端口A1，与第二数据线D2对应的第二连接线段通过换线连接线321连接至连接端口A2，与第二数据线D3对应的第二连接线段通过换线连接线321连接至连接端口A3，以此类推，与第二数据线D360对应的第二连接线段通过换线连接 线321连接至连接端口A360。
如图6所示，换线连接线321包括沿第二方向延伸的第一换线连接线段3211和沿第一方向延伸的第二换线连接线段3212。第一换线连接线段3211的两端分别与第二连接线27以及第二换线连接线段3212电连接，第二换线连接线段3212与连接端口电连接。
由于换线连接线321与阵列基板中的其他结构会产生电容，且换线连接线321自身的电阻也会对信号传输带来一定影响。为了减小或避免不同换线连接线321的电容相差过大、电阻相差过大引起的信号传输差异，使得各换线连接线321各自与阵列基板中的其他结构产生的电容趋于一致，以及使各换线连接线321各自的电阻也趋于一致，可降低各换线连接线321的长度之间的差异。如图7所示，第一换线连接线段3211可在由边缘区域212指向中心区域211的方向上延伸，并超出距离中心区域211的中心最近的第二连接线27，使得各换线连接线321的长度之间的差值的绝对值小于可接收影响长度阈值，且布线更为均匀。
由于第二数据线25连接的第二连接线27具有弯折部分，导致第二数据线25和第二连接线27的长度之和要大于第一数据线24和第一连接线26的长度之和，为了减小第二数据线25和第二连接线27的电容与第一数据线24和第一连接线26的电容之间的差异，以及，减小第二数据线25和第二连接线27的电阻与第一数据线24和第一连接线26的电阻自己拿的差异，阵列基板还可包括补偿线。如图7所示，补偿线33与第一连接线26电连接。补偿线33位于连接端口与驱动集成电路芯片之间，沿第一方向延伸。第二数据线25和第二连接线27的电容与第一数据线24、第一连接线26和补偿线33的电容之间的差异较小，第二数据线25和第二连接线27的电阻与第一数据线24、第一连接线26和补偿线33的电阻之间的差异也较小，从而减小或避免不同走线的电容、电阻相差过大引起的信号传输差异，使得各走线各自与阵列基板中的其他结构产生的电容趋于一致，以及使各走线的电阻也趋于一致，提高信号传输效果，进而提升显示效果。
在一些示例中，为了缩短第二连接线27的长度，第一连接线段在显示区中可为一次弯折的弯折线。具体地，如图8所示，第一连接线段271 包括沿第二方向延伸的第一连接子线段2711和沿第一方向延伸的第二连接子线段2712。第一连接子线段2711与第二连接子线段2712电连接。减少第一连接线段271的弯折次数，能够缩短第二连接线27的长度，从而降低第二数据线25与第二连接线27的阻值、容值等，避免电连接的第二数据线25和第二连接线27的阻值、容值等与电连接的第一数据线24和第一连接线26的阻值、容值等产生较大差异，保证包括阵列基板的显示装置的显示效果。
在一些示例中，至少一条第一连接线段271沿第一方向延伸的部分位于相邻的两条第一数据线24之间。即在相邻的两条第一数据线24之间可设置有至少一条第一连接线段24沿第一方向延伸的部分。由于位于边缘区域212中的第二数据线25的数量较多，若在相邻两条第一数据线25之间只设置一条第一连接线段271沿第一方向延伸的部分，经过中心区域211的中心的相邻两条第一数据线24之间的第一连接线段271的长度与经过邻近边缘区域212的相邻两条第一数据线24之间的第一连接线段271的长度的差异会较大，即多条第一连接线段271的长度相差较大，均一性较差。为了减小多条第一连接线段271的长度之间的差异，保证包括阵列基板的显示装置的显示效果，可使两条以上的第一连接线段271沿第一方向延伸的部分位于相邻的两条第一数据线24之间，即在相邻的两条第一数据线24之间可设置有两条以上第一连接线段271沿第一方向延伸的部分。如图9和图10所示，两条第一连接线段271沿第一方向延伸的部分位于相邻的两条第一数据线24之间。即相邻的两条第一数据线24之间设置有两条第一连接线段271沿第一方向延伸的部分。第一连接线段271沿第一方向延伸的部分与相邻的第一数据线24之间的距离，小于相邻的两条数据线之间的距离。第一连接线段与数据线形成的像素单元的边界的距离等于或小于像素单元的尺寸即pixel pitch。
具体地，当第一连接线段271为弯折一次的弯折线，每一第一连接线段271可包括沿第二方向延伸的第一连接子线段2711和沿第一方向延伸的第二连接子线段2712，至少一条第二连接子线段2712位于相邻的两条第一数据线24之间，即相邻的两条第一数据线24之间设置有至少一条第 二连接子线段2712。如图9和图10所示，两条第二连接子线段2712位于相邻的两条第一数据线24之间，即相邻的两条第一数据线24之间设置有两条第二连接子线段2712。
在一些示例中，功能区域23包括弯折区域231即bending区域。在弯折区域231沿第二方向的长度等于功能区域23沿第二方向的长度的情况下，第一连接线26和第二连接线27沿第一方向延伸入弯折区域231。具体地，第一连接线26在弯折区域231内的部分和第二连接线27在弯折区域231内的部分均沿第一方向延伸。如图11和图12所示，第一连接线26和第二连接线27伸入弯折区域231，并在弯折区域231中沿第一方向延伸。
在另一些示例中，如图13和14所示，功能区域23包括弯折区域231即bending区域。在弯折区域231沿第二方向的长度小于功能区域23沿第二方向的长度相同的情况下，阵列基板还可包括第三连接线28。弯折区域231的大小可根据阵列基板的需求具体设置，可将功能区域23沿第二方向的长度设置为长于弯折区域231沿第二方向的长度。如图14所示，弯折区域231位于功能区域23中，弯折区域231与功能区域23靠近中心区域211的一侧之间具有一定距离。第三连接线28位于弯折区域231与功能区域23靠近中心区域211的一侧之间。第三连接线28的两端分别与第二连接线段272和第一连接线26一一对应电连接。阵列基板上多条第三连接线28所在的区域形成扇形走线区29。电连接的第三连接线28和第二连接线段272可一体成型，电连接的第三连接线28和第一连接线26可一体成型。
将功能区域23沿第二方向的长度设置为长于弯折区域231沿第二方向的长度，能够尽量减少第二数据线25的数量，从而减少第二连接线27的数量，使得通过第一数据线24和第二数据线25传输的数据信号的电压、电流更加均一化，减少第一连接线26与第二连接线27在长度不同情况下带来的负载差异，保证包括该阵列基板的显示装置的显示效果。
而且，通过第二连接线27的弯折，使得第三连接线28形成的扇形走线区29的上底边即与功能区域23靠近中心区域211的一侧邻近的底边的 长度更短，更短的上底边长度，使得扇形走线区29的宽度与图1中的扇形走线区11的宽度相比更短，显示区21与弯折区域231之间的距离d5相对于图1中的扇形走线区11的宽度更小，本申请实施例的阵列基板依然能够进一步缩短非显示区NA的宽度，进而进一步减小显示装置的边框宽度，尤其是减小下边框的宽度。
在一些示例中，如图13和图14所示，阵列基板还可包括第四连接线30。第四连接线30可位于弯折区域231，沿第一方向延伸。第四连接线30可与第三连接线28一一对应电连接。
在一些示例中，第二数据线25可通过第二连接线27、其他结构和换线连接单元32，按照第二数据线25的排列顺序与连接端口连接，以实现与驱动集成电路芯片上对应的输出引脚电连接。其他结构可根据阵列基板的具体结构确定，在此并不限定。例如，在阵列基板包括第三连接线28的情况下，第二数据线25可通过第二连接线27、第三连接线28和换线连接单元32，按照第二数据线25的排列顺序与连接端口电连接。又例如，在阵列基板包括第三连接线28和第四连接线30的情况下，第二数据线25可通过第二连接线27、第三连接线28、第四连接线30和换线连接单元32，按照第二数据线25的排列顺序与连接端口电连接。
在一些实施例中，第二连接线27可与第二数据线25同层设置，即第二连接线27与第二数据线25可位于同一金属层。例如，以阵列基板为常规柔性阵列基板为例，阵列基板可包括第一金属层M1、第二金属层M2、第三金属层M3和第四金属层M4。第一金属层M1、第二金属层M2、第三金属层M3和第四金属层M4常作为信号线金属层使用。在一些示例中，第一数据线24和第二数据线25可位于第三金属层M3和/或第四金属层M4，对应地，第二连接线27也可位于第三金属层M3和/或第四金属层M4。
在另一些实施例中，第二连接线27与第二数据线25非同层设置。第二连接线27位于目标金属层，目标金属层可位于基底与有源层之间。具体可在阵列基板中增加一金属层即目标金属层来实现第二连接线。包括第一数据线24和第二数据线25的金属层可位于有源层与阳极金属层之间。 第二连接线27与第二数据线25非同层设置，使得第二连接线在显示区的布线更为自由灵活。在第二连接线27与第二数据线25非同层设置的情况下，第二连接线27与第二数据线25可通过通孔电连接。
本申请还提供一种显示模组。该显示模组可包括上述实施例中的阵列基板。本申请实施例中的显示模组可为采用COP封装方式、COF封装方式或COG封装方式的显示模组，在此并不限定。
在一些示例中，显示模组采用COG封装方式。如图15所示，显示模组具有显示区41和非显示区42。非显示区42包括功能区域43。驱动集成电路芯片31位于功能区域43。图15中显示区41与功能区域43之间的距离L1与图2、图4和图9中所示的距离d3基本相同。阵列基板的显示区21与功能区域23之间的距离d3能够进一步缩短，对应地，显示模组的显示区41与功能区域43之间的距离L1能够进一步缩短，从而能够进一步压缩显示模组的边框宽度，能够实现显示模组的更窄边框。
在另一些示例中，显示模组采用COF封装方式。如图16所示，显示模组具有显示区41和非显示区42。非显示区42包括功能区域43。功能区域43具体可包括上述实施例中的弯折区域。驱动集成电路芯片31位于弯折至阵列基板背面的排线上。图16中显示区41与功能区域43之间的距离L1与图2、图4、图9和图11中所示的距离d3基本相同。阵列基板的显示区21与功能区域23之间的距离d3能够进一步缩短，对应地，显示模组的显示区41与功能区域43之间的距离L1能够进一步缩短，从而能够进一步压缩显示模组的边框宽度，能够实现显示模组的更窄边框。
在又一些示例中，显示模组采用COP封装方式。如图17所示，显示模组具有显示区41和非显示区42。非显示区42包括功能区域43。功能区域43具体可包括上述实施例中的弯折区域。阵列基板为柔性阵列基板，可弯折至背面，驱动集成电路芯片31位于弯折至背面的柔性阵列基板上。图17中显示区41与功能区域43之间的距离L1与图2、图4、图9和图11中所示的距离d3基本相同。阵列基板的显示区21与功能区域23之间的距离d3能够进一步缩短，对应地，显示模组的显示区41与功能区域43之间的距离L1能够进一步缩短，从而能够进一步压缩显示模组的边 框宽度，能够实现显示模组的更窄边框。
本申请还提供一种显示装置。该显示装置包括上述实施例中的显示模组。显示装置具体可为手机、计算机、平板电脑、电视、电子纸等具有显示功能的装置，在此并不限定。
需要明确的是，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同或相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。对于显示模组实施例和显示装置实施例而言，相关之处可以参见阵列基板实施例的说明部分。本申请并不局限于上文所描述并在图中示出的特定步骤和结构。本领域的技术人员可以在领会本发明的精神之后，作出各种改变、修改和添加，或者改变步骤之间的顺序。并且，为了简明起见，这里省略对已知方法技术的详细描述。

Claims (18)

  1. 一种阵列基板，具有：
    显示区，包括中心区域和位于所述中心区域沿第二方向上的至少一侧的边缘区域；
    非显示区，所述非显示区包括功能区域，所述功能区域与所述显示区在第一方向间隔分布；
    多条第一数据线，在所述中心区域，沿所述第一方向延伸，且多条所述第一数据线沿所述第二方向间隔分布；
    多条第二数据线，在所述边缘区域，沿所述第一方向延伸，且多条所述第二数据线沿所述第二方向间隔分布；
    多条第一连接线，在所述中心区域与所述功能区域之间，沿所述第一方向延伸，所述第一连接线与所述第一数据线一一对应电连接；
    多条第二连接线，与所述第二数据线一一对应电连接，所述第二连接线包括连续分布的第一连接线段和第二连接线段，所述第一连接线段为在所述显示区延伸的弯折线，所述第二连接线段在所述中心区域与所述功能区域之间沿所述第一方向延伸；及
    多个换线连接单元，被配置为与所述第二连接线和连接端口电连接，用于使所述第二数据线通过第二连接线和所述换线连接单元，按照所述第二数据线的排列顺序与对应顺序排列的所述连接端口电连接，所述连接端口与驱动集成电路芯片电连接。
  2. 根据权利要求1所述的阵列基板，其中，所述多个第一连接线段包括沿所述第二方向延伸的多个第一连接子线段和沿所述第一方向延伸的多个第二连接子线段，所述多个第一连接子线段与所述多个第二连接子线段电连接。
  3. 根据权利要求1所述的阵列基板，其中，至少一条所述第一连接线段沿所述第一方向延伸的部分位于相邻的两条所述第一数据线之间。
  4. 根据权利要求1所述的阵列基板，其中，所述功能区域包括弯折区域，
    在所述弯折区域沿所述第二方向的长度等于所述功能区域沿所述第二方向的长度的情况下，所述第一连接线和所述第二连接线段沿所述第一方向延伸入所述弯折区域。
  5. 根据权利要求1所述的阵列基板，其中，所述功能区域包括弯折区域，
    在所述弯折区域沿所述第二方向的长度小于所述功能区域沿所述第二方向的长度的情况下，所述阵列基板还包括第三连接线，所述第三连接线两端分别与所述第二连接线段和所述第一连接线一一对应电连接，阵列基板上多条所述第三连接线所在区域形成扇形走线区。
  6. 根据权利要求5所述的阵列基板，其中，
    所述阵列基板还包括第四连接线，所述第四连接线在所述弯折区域，沿所述第一方向延伸，所述第四连接线与所述第三连接线一一对应电连接。
  7. 根据权利要求1所述的阵列基板，其中，所述换线连接单元包括：
    换线连接线，与所述第二连接线一一对应电连接，且与连接的所述第二连接线对应顺序的所述连接端口电连接。
  8. 根据权利要求7所述的阵列基板，其中，
    所述换线连接线包括沿所述第二方向延伸的第一换线连接线段和沿所述第一方向延伸的第二换线连接线段，所述第一换线连接线段与所述第二连接线以及所述第二换线连接线段电连接，所述第二换线连接线段与所述连接端口电连接。
  9. 根据权利要求7所述的阵列基板，其中，
    至少部分所述第一换线连接线段在由所述边缘区域指向所述中心区域的方向上延伸，并超出与所述第一换线连接线段连接的所述第二连接线。
  10. 根据权利要求7所述的阵列基板，其中，
    所述第一换线连接线段在由所述边缘区域指向所述中心区域的方向上延伸，并超出距离所述中心区域的中心最近的所述第二连接线。
  11. 根据权利要求1所述的阵列基板，还包括：
    补偿线，位于所述连接端口与驱动集成电路芯片之间，沿所述第一方向延伸，且所述补偿线与所述第一连接线电连接。
  12. 根据权利要求1所述的阵列基板，其中，所述第二连接线与所述第二数据线同层设置。
  13. 根据权利要求1所述的阵列基板，其中，所述第二连接线与所述第二数据线非同层设置，所述第二连接线位于目标金属层，所述目标金属层位于基底与有源层之间。
  14. 根据权利要求13所述的阵列基板，包括所述第二数据线的金属层位于所述有源层与阳极金属层之间。
  15. 根据权利要求13所述的阵列基板，其中，所述第二连接线与所述第二数据线通过通孔电连接。
  16. 根据权利要求1所述的阵列基板，其中，所述边缘为包括所述中心区域沿所述第二方向相对于所述功能区域凸出的区域。
  17. 一种显示模组，包括如权利要求1至16中任意一项所述的阵列基板。
  18. 一种显示装置，包括如权利要求17所述的显示模组。
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