WO2023236095A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2023236095A1
WO2023236095A1 PCT/CN2022/097588 CN2022097588W WO2023236095A1 WO 2023236095 A1 WO2023236095 A1 WO 2023236095A1 CN 2022097588 W CN2022097588 W CN 2022097588W WO 2023236095 A1 WO2023236095 A1 WO 2023236095A1
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WO
WIPO (PCT)
Prior art keywords
transfer
layer
source
drain metal
metal layer
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Application number
PCT/CN2022/097588
Other languages
English (en)
French (fr)
Inventor
王蓉
何帆
马宏伟
董向丹
樊聪
张振华
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/097588 priority Critical patent/WO2023236095A1/zh
Priority to CN202280001674.6A priority patent/CN117837298A/zh
Publication of WO2023236095A1 publication Critical patent/WO2023236095A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • the present disclosure relates to the field of display technology, and specifically, to a display panel and a display device.
  • OLED display panels have the advantages of self-illumination, wide color gamut, high contrast, flexibility, high response and flexibility, etc., and have broad application prospects.
  • OLED display panels have increasingly higher requirements for ultra-narrow bottom borders.
  • the width of the lower frame In order to reduce the width of the lower frame, consider introducing the data lines located in the peripheral area into the display area to reduce the width of the lower frame, but this will result in poor display uniformity of the display panel.
  • the present disclosure provides a display panel and a display device.
  • a display panel including a display area and a peripheral area at least partially surrounding the display area; along a first direction, the display area of the display panel includes a first display area and a first display area located on both sides of the first display area.
  • the second display area; the display panel includes a substrate substrate, a driving circuit layer, a pixel layer, a plurality of pads, a plurality of data lines and a plurality of transfer lines.
  • the driving circuit layer includes a first source-drain metal layer and a second source-drain metal layer.
  • the pixel layer includes a plurality of pixel groups, and the pixel groups It includes first sub-pixels, second sub-pixels and third sub-pixels with different colors; a plurality of pads are located in the peripheral area; a plurality of data traces are respectively connected to a plurality of first sub-pixels, a plurality of second sub-pixels and A plurality of third sub-pixels are electrically connected, and a plurality of data lines are located in the display area and extend along the second direction.
  • the plurality of data lines include a plurality of first data lines located in the first display area and a plurality of data lines located in the second display area.
  • the transfer lines include a plurality of first transfer lines and a plurality of second transfer lines.
  • the first transfer lines are connected to the second data lines corresponding to the first sub-pixel and the third sub-pixel, and the second transfer lines are connected to the second sub-pixel.
  • the second data wiring connection; the transfer line includes a first transfer section extending along the first direction and a second transfer section extending along the second direction, the first direction and the second direction intersect; wherein, at least one second transfer section The transfer section is arranged between two adjacent first data lines; the second transfer section of all the first transfer lines is arranged on the same layer as the first source-drain metal layer or the second source-drain metal layer, at least part of the third The second transfer section of the second transfer line is arranged on the same layer as the first source-drain layer or the second source-drain layer.
  • the second transfer sections of all the first transfer lines are arranged in the same layer as the first source-drain metal layer, and the second transfer sections of all the second transfer lines are in the same layer as the first source-drain metal layer. Layer settings.
  • the second transfer sections of all the first transfer lines are arranged on the same layer as the second source-drain metal layer, and the second transfer sections of all the second transfer lines are in the same layer as the second source-drain metal layer. Layer settings.
  • the second transfer sections of all the first transfer lines are arranged in the same layer as the second source-drain metal layer, and the second transfer sections of all the second transfer lines are in the same layer as the first source-drain metal layer. Layer settings.
  • the second transfer sections of all the first transfer lines are arranged on the same layer as the second source-drain metal layer, and the second transfer sections of some of the second transfer lines are in the same layer as the first source-drain metal layer. They are arranged on the same layer, and the second transfer section of the other part of the second transfer line is arranged on the same layer as the second source-drain metal layer.
  • the second transfer sections of the second transfer line are alternately distributed on the first source-drain metal layer and the second source-drain metal layer.
  • the second transfer sections of the two second transfer lines that are symmetrically arranged about a central axis extending in the second direction are arranged on the same layer.
  • a plurality of adjacent first data wiring lines are arranged into a plurality of first data wiring groups, a plurality of adjacent transfer lines are arranged into a plurality of transfer line groups, and a plurality of adjacent The second transfer section of the transfer line forms a second transfer section group.
  • the first data wiring group and the second transfer section group are alternately arranged one by one.
  • the second transfer section group includes at least one second transfer section of the first transfer line and at least one second transfer section of the second transfer line.
  • the second transfer section of the first transfer line The connecting sections and the second switching sections of the second switching cable are arranged alternately.
  • the second transfer section group includes at least one second transfer section of the first transfer line and at least two second transfer sections of the second transfer line, and all the first transfer lines
  • the second transfer section and the second source-drain metal layer are arranged on the same layer.
  • the second transfer section of at least one second transfer line is arranged on the same layer as the first source-drain metal layer.
  • the second transfer section of at least one second transfer line The segment is arranged in the same layer as the second source-drain metal layer, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel.
  • the display area is arranged symmetrically about a central axis extending along the second direction; among the two adjacent second data traces, the second data trace corresponding to the second data trace closer to the central axis is Two transfer sections, the second transfer section corresponding to the second data wiring away from the central axis is arranged away from the central axis.
  • the display area is arranged symmetrically about a central axis extending along the second direction; among the two adjacent second data traces, the second data trace corresponding to the second data trace located closer to the central axis is The first transfer section, the first transfer section corresponding to the second data trace away from the central axis is arranged close to the pad.
  • a plurality of first data lines located in the first display area are provided on the first source-drain metal layer or the second source-drain metal layer.
  • the driving circuit layer further includes a transistor layer.
  • the transistor layer is provided between the base substrate and the first source-drain metal layer.
  • the transistor layer is provided with a driving circuit.
  • the driving circuit includes a thin film transistor. The adapter line and Thin film transistors do not overlap.
  • the driving circuit layer includes driving circuit islands distributed in an array, and any driving circuit island includes one or more driving circuit areas corresponding to each driving circuit; at least part of the thin film transistor configuration of the driving circuit in the corresponding drive circuit area; the transfer line is arranged in the gap between the drive circuit islands.
  • each second transfer section is arranged into a plurality of second transfer section groups, and each second transfer section in any second transfer section group is arranged adjacent to each other in sequence and located at the same location. Between two adjacent drive circuit island rows; between any two adjacent second transfer section groups, they are all isolated by the drive circuit island row.
  • the transistor layer has a gate layer;
  • the driving circuit layer also includes an electrode initialization voltage line extending along the first direction, the electrode initialization voltage line extends along the first direction;
  • the electrode initialization voltage line includes alternately connected The first initial line and the second initial line; the first initial line is provided on the gate layer; the second initial line is provided on the first source and drain metal layer, and part of the second transfer section is provided on the first source and drain metal layer, located on the first A second transition section of a source-drain metal layer overlaps the first initial line.
  • all the first transfer sections are arranged in the same layer as the first source-drain metal layer or the gate layer, and at least part of the second transfer section is arranged in the same layer as the second source-drain metal layer, located at The second transfer section of the second source-drain metal layer is connected to the first transfer section through an adapter.
  • the portion of the first data line adjacent to the adapter is bent in a direction away from the adapter to form an avoidance section.
  • the avoidance section is connected to the first transfer section.
  • a transfer section overlaps.
  • a display device including the display panel according to one aspect of the present disclosure.
  • FIG. 1 is a schematic diagram of the film structure of a display panel in an embodiment of the present disclosure.
  • FIG. 2 is a schematic structural diagram of a display panel in an embodiment of the present disclosure.
  • FIG. 3 is a partial structural diagram of a display panel in an embodiment of the present disclosure.
  • FIG. 4 is a partial structural diagram of a display panel in an embodiment of the present disclosure.
  • FIG. 5 is a partial structural diagram of a display panel in an embodiment of the present disclosure.
  • FIG. 6 is a schematic distribution diagram of second transition sections corresponding to different sub-pixels of the display panel in an embodiment of the present disclosure.
  • FIG. 7 is another schematic diagram of the distribution of second transition sections corresponding to different sub-pixels of the display panel in an embodiment of the present disclosure.
  • FIG. 8 is another schematic diagram of the distribution of second transition sections corresponding to different sub-pixels of the display panel in an embodiment of the present disclosure.
  • FIG. 9 is another schematic diagram of the distribution of second transition sections corresponding to different sub-pixels of the display panel in an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of the distribution of four second transfer sections between two adjacent first data traces of a display panel in an embodiment of the present disclosure.
  • FIG. 11 is a waveform diagram of data lines corresponding to different sub-pixels of the display panel in an embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of the distribution of driving circuit islands in an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of the distribution of the drive circuit island and the second adapter line in an embodiment of the present disclosure.
  • FIG. 14 is a schematic diagram of the distribution of the drive circuit island and the second adapter line in an embodiment of the present disclosure.
  • FIG. 15 is a schematic distribution diagram of the drive circuit island and the second adapter wire in an embodiment of the present disclosure.
  • FIG. 16 is a schematic distribution diagram of the drive circuit island and the second adapter wire in an embodiment of the present disclosure.
  • FIG. 17 is a schematic distribution diagram of the drive circuit island and the second adapter line in an embodiment of the present disclosure.
  • FIG. 18 is a schematic distribution diagram of the drive circuit island and the second adapter wire in an embodiment of the present disclosure.
  • Figure 19 is a schematic distribution diagram of the drive circuit island and the second adapter line in an embodiment of the present disclosure.
  • FIG. 20 is a schematic diagram of the positions of the first patch cord wiring area and the second patch cord wiring area in an embodiment of the present disclosure.
  • FIG. 21 is a schematic diagram of the positions of the first patch cord wiring area and the second patch cord wiring area in an embodiment of the present disclosure.
  • FIG. 22 is a schematic diagram of the positions of the first patch cord wiring area and the second patch cord wiring area in an embodiment of the present disclosure.
  • FIG. 23 is an equivalent circuit diagram of a driving circuit in an embodiment of the present disclosure.
  • FIG. 24 is a schematic diagram of the driving timing of the driving circuit in an embodiment of the present disclosure.
  • FIG. 25 is a schematic diagram of the partial structure of the light-shielding layer in the driving circuit area in an embodiment of the present disclosure.
  • Figure 26 is a schematic diagram of a partial structure of the light shielding layer in the display area in an embodiment of the present disclosure.
  • FIG. 27 is a schematic diagram of the partial structure of the low-temperature polysilicon semiconductor layer and the metal oxide semiconductor layer in the driving circuit area in an embodiment of the present disclosure.
  • FIG. 28 is a schematic diagram of the partial structure of the low-temperature polysilicon semiconductor layer in the display area in an embodiment of the present disclosure.
  • FIG. 29 is a schematic diagram of the partial structure of the metal oxide semiconductor layer in the display area in an embodiment of the present disclosure.
  • FIG. 30 is a schematic diagram of the partial structure of the first gate layer in the driving circuit area in an embodiment of the present disclosure.
  • FIG. 31 is a schematic diagram of the partial structure of the first gate layer in the display area in an embodiment of the present disclosure.
  • FIG. 32 is a schematic diagram of the partial structure of the second gate layer in the driving circuit region in an embodiment of the present disclosure.
  • FIG. 33 is a schematic diagram of the partial structure of the second gate layer in the display area in an embodiment of the present disclosure.
  • FIG. 34 is a schematic diagram of the partial structure of the third gate layer in the driving circuit area in an embodiment of the present disclosure.
  • FIG. 35 is a schematic diagram of the partial structure of the third gate layer in the display area in an embodiment of the present disclosure.
  • FIG. 36 is a schematic diagram of the partial structure of the first source-drain metal layer in the driver circuit area in an embodiment of the present disclosure.
  • FIG. 37 is a partial structural diagram of the first source and drain metal layer in the display area in an embodiment of the present disclosure.
  • FIG. 38 is a schematic diagram of the partial structure of the second source-drain metal layer in the driver circuit area in an embodiment of the present disclosure.
  • Figure 39 is a partial structural diagram of the second source and drain metal layer in the display area in an embodiment of the present disclosure.
  • FIG. 40 is a structural layout of an area of the display panel in an embodiment of the present disclosure.
  • FIG. 41 is a structural layout of another area of the display panel in an embodiment of the present disclosure.
  • Figure 42 is a structural layout of another area of the display panel in an embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments.
  • the same reference numerals in the drawings indicate the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • the present disclosure provides a display panel.
  • the display panel includes a display area and a peripheral area at least partially surrounding the display area; along the first direction, the display area AA of the display panel includes a first display area AA1 and a second display area AA2 located on both sides of the first display area AA1.
  • the display panel includes a base substrate, a driving circuit layer, a pixel layer, a plurality of bonding pads, a plurality of data lines DL and a plurality of transfer lines TR.
  • the driving circuit layer includes a first source-drain metal layer LSD1 and a second source-drain metal layer. LSD2, the first source-drain metal layer LSD1 is provided on one side of the base substrate BP, and the second source-drain metal layer LSD2 is provided on the side of the first source-drain metal layer LSD1 away from the base substrate BP;
  • the pixel layer EE includes a plurality of pixel groups P, the pixel group P includes a first sub-pixel P1, at least one second sub-pixel P2 and a third sub-pixel P3, the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel
  • the colors of P3 are different from each other; a plurality of pads are located in the peripheral area; a plurality of data lines DL are electrically connected to a plurality of first sub-pixels P1, a plurality of second sub-pixels P2, and a plurality of third sub-pixels P3.
  • the plurality of data traces DL are located in the display area AA and extend along the second direction.
  • the plurality of data traces DL include a plurality of first data traces DL1 located in the first display area AA1 and a plurality of second data traces DL1 located in the second display area AA2.
  • the data trace DL2 and the plurality of first data traces DL1 are electrically connected to the plurality of pads.
  • the plurality of transfer lines TR are located in the display area AA and are electrically connected to the plurality of second data lines DL2 and the plurality of pads; the plurality of transfer lines include a plurality of first transfer lines and a plurality of second transfer lines.
  • the first transfer lines The second data line DL2 corresponding to the first sub-pixel P1 and the third sub-pixel P3 is connected, and the second transfer line is connected to the second data line DL2 corresponding to the second sub-pixel P2.
  • the transfer line includes a first transfer section TR1 extending along the first direction H1 and a second transfer section TR2 extending along the second direction H2.
  • the first direction and the second direction intersect; wherein, at least one second transfer section TR2 Disposed between two adjacent first data lines DL1; the second transfer sections TR2 of all first transfer lines are arranged on the same layer as the first source-drain metal layer LSD1 or the second source-drain metal layer LSD2, at least partially
  • the second transfer section TR2 of the second transfer line is arranged on the same layer as the first source-drain layer LSD1 or the second source-drain layer LSD1.
  • the first transfer line of the display panel is connected to the second data trace DL2 corresponding to the first sub-pixel P1 and the third sub-pixel P3, and the second transfer section TR2 of all the first transfer lines is connected to the first source-drain metal layer LSD1 Or if the second source-drain metal layer LSD2 is arranged on the same layer, the distance between the second transfer section TR2 of the first transfer line and the vertical scanning line at the bottom is the same, so the parasitic capacitance generated is the same.
  • the waveform transition of the second data line corresponding to the first sub-pixel P1 and the third sub-pixel P3 has the same impact on the parasitic capacitance, so that the brightness changes at different positions in the display area of the display panel are the same. , the display uniformity of the display panel is better.
  • the display panel includes a base substrate BP, a driving circuit layer DR and a pixel layer EE that are stacked in sequence.
  • the pixel layer EE is provided with multiple pixel groups distributed in an array.
  • the pixel groups include first sub-pixels, second sub-pixels and third sub-pixels with different colors.
  • the drive circuit layer DR is provided with a plurality of pixel groups one by one with each sub-pixel. Corresponding drive circuit; each sub-pixel is driven by the corresponding drive circuit to achieve display.
  • the display panel can be provided with scan lines extending in a first direction (generally as a row direction) and data lines DL extending in a second direction (generally as a column direction); the display panel can implement Line scan to display the screen.
  • each driving circuit may be arranged into a driving circuit row extending along the first direction and a driving circuit column extending along the second direction. The first direction and the second direction intersect, for example vertically.
  • the base substrate may be a base substrate of inorganic material or a base substrate of organic material.
  • the material of the substrate may be glass materials such as soda-lime glass, quartz glass, sapphire glass, or metals such as stainless steel, aluminum, and nickel. Material.
  • the material of the substrate may be polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP) ), polyether sulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), poly Polyethylene naphthalate (PEN) or combinations thereof.
  • the base substrate may also be a flexible base substrate.
  • the material of the base substrate may be polyimide (PI).
  • the base substrate may also be a composite of multiple layers of materials.
  • the base substrate may include a base film layer (Bottom Film), a pressure-sensitive adhesive layer, and a first film layer that are stacked in sequence. polyimide layer and a second polyimide layer.
  • the driving circuit layer is provided with a driving circuit for driving the sub-pixels.
  • any driver circuit may include a transistor and a storage capacitor.
  • the transistor may be a thin film transistor, and the thin film transistor may be selected from a top gate thin film transistor, a bottom gate thin film transistor, or a double gate thin film transistor;
  • the material of the active layer of the thin film transistor may be amorphous silicon semiconductor material, low temperature polysilicon Semiconductor materials, metal oxide semiconductor materials, organic semiconductor materials or other types of semiconductor materials; the thin film transistor can be an N-type thin film transistor or a P-type thin film transistor.
  • the types of any two transistors may be the same or different.
  • some transistors may be N-type transistors and some transistors may be P-type transistors.
  • the material of the active layer of some transistors may be a low-temperature polysilicon semiconductor material, and the material of the active layer of some of the transistors may be metal oxide. semiconductor materials.
  • the transistor may have a first terminal, a second terminal and a control terminal.
  • One of the first terminal and the second terminal may be a source of the transistor, the other may be a drain of the transistor, and the control terminal may be a gate of the transistor.
  • the source and drain of a transistor are two opposite and interchangeable concepts; when the working state of the transistor changes, for example, the direction of the current changes, the source and drain of the transistor can be interchanged.
  • the driving circuit layer may include a transistor layer, an interlayer dielectric layer ILD and a source and drain metal layer that are sequentially stacked on the base substrate.
  • the transistor layer is provided with an active layer and a gate electrode of the transistor, and the source-drain metal layer is electrically connected to the source electrode and drain electrode of the transistor.
  • the transistor layer may include a semiconductor layer, a gate insulating layer, and a gate layer stacked between the base substrate BP and the interlayer dielectric layer. The positional relationship of each film layer can be determined according to the film layer structure of the thin film transistor.
  • the semiconductor layer can be used to form the active layer of the transistor.
  • the active layer of the semiconductor includes a channel region and source and drain electrodes located on both sides of the channel region; wherein the channel region can maintain semiconductor characteristics.
  • the semiconductor materials of the source and drain electrodes are partially or completely conductive.
  • the gate layer can be used to form gate layer wiring such as scanning wiring, it can also be used to form the gate of a transistor, and it can also be used to form part or all of the electrode plates of the storage capacitor.
  • the source-drain metal layer can be used to form source-drain metal layer traces such as data traces and power traces.
  • the driving circuit layer may include a semiconductor layer, a gate insulating layer, a gate layer, an interlayer dielectric layer, and a source and drain metal layer that are stacked in sequence.
  • the thin film transistor thus formed It is a top gate thin film transistor.
  • the driving circuit layer may include a gate layer, a gate insulating layer, a semiconductor layer, an interlayer dielectric layer and a source and drain metal layer that are stacked in sequence.
  • the thin film thus formed The transistor is a bottom-gate thin film transistor.
  • the gate layer may be one gate layer, or two or three gate layers.
  • the gate layer may include a first gate layer LG1, a second gate layer LG2, and a third gate layer LG3.
  • the semiconductor layer may be one semiconductor layer or two semiconductor layers.
  • the semiconductor layer may include a low-temperature polysilicon semiconductor layer LPoly and a metal oxide semiconductor layer LOxide. It can be understood that when the gate layer or the semiconductor layer has a multi-layer structure, the insulating layer in the transistor layer can be adaptively increased or decreased. Exemplarily, in one embodiment of the present disclosure, referring to FIG.
  • the transistor layer may include a low-temperature polysilicon semiconductor layer LPoly, a first gate insulating layer LGI1, and a first gate layer that are sequentially stacked on the base substrate BP.
  • LG1 second insulating buffer layer Buff2 (such as silicon nitride, silicon oxide and other inorganic layers), second gate layer LG2, second gate insulating layer LGI2, metal oxide semiconductor layer LOxide, third gate insulating layer LGI3 , the third gate layer LG3, etc.
  • the source and drain metal layers may be one source and drain metal layer, or may be two source and drain metal layers.
  • the source-drain metal layer may include a first source-drain metal layer LSD1 and a second source-drain metal layer LSD2.
  • a passivation layer PVX and a first planarization layer PLN1 may be provided between the first source-drain metal layer LSD1 and the second source-drain metal layer LSD2, and a second planarization layer PLN2 may be provided between the LSD2 and the pixel layer.
  • the driving circuit layer may also include a first insulating buffer layer Buff1 disposed between the base substrate BP and the semiconductor layer, and the semiconductor layer, gate layer, etc. are located on the first insulating buffer layer Buff1 away from the base substrate. one side.
  • the material of the first insulating buffer layer Buff1 may be inorganic insulating materials such as silicon oxide and silicon nitride.
  • the buffer material layer may be one layer of inorganic material, or may be multiple layers of laminated inorganic material layers.
  • a light-shielding layer LBSM may also be provided between the first insulating buffer layer Buff1 and the base substrate BP.
  • the light-shielding layer LBSM may overlap with at least part of the channel region of the transistor to block the irradiation direction. The light from the transistor stabilizes the electrical properties of the transistor.
  • the pixel layer is provided with light-emitting elements distributed in an array (as sub-pixels), and each light-emitting element emits light under the control of a driving circuit.
  • the light-emitting element may be an organic electroluminescent diode (OLED), a micro-light emitting diode (Micro LED), a quantum dot-organic electroluminescent diode (QD-OLED), a quantum dot light-emitting diode (QLED), or other types light-emitting components.
  • the light-emitting element is an organic electroluminescent diode (OLED), then the display panel is an OLED display panel.
  • OLED organic electroluminescent diode
  • the pixel layer can be disposed on the side of the driving circuit layer away from the base substrate, which can include a pixel electrode layer LAn, a pixel definition layer PDL, and a support pillar layer that are stacked in sequence (not shown in Figure 1 out), organic light-emitting functional layer LEL and common electrode layer LCOM.
  • the pixel electrode layer LAn has multiple pixel electrodes in the display area of the display panel;
  • the pixel definition layer has multiple through pixel openings in the display area that are arranged in one-to-one correspondence with the multiple pixel electrodes, and any pixel opening exposes the corresponding pixel. At least part of the electrode area.
  • the support pillar layer includes a plurality of support pillars in the display area, and the support pillars are located on the surface of the pixel definition layer away from the base substrate to support the fine metal mask (FMM) during the evaporation process.
  • the organic light-emitting functional layer at least covers the pixel electrode exposed by the pixel defining layer.
  • the organic light-emitting functional layer may include an organic electroluminescent material layer, and may include one of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer and an electron injection layer, or Various.
  • Each layer of the organic light-emitting functional layer can be prepared through an evaporation process, and a fine metal mask or an open mask can be used to define the pattern of each layer during evaporation.
  • the common electrode layer can cover the organic light-emitting functional layer in the display area. In this way, the pixel electrode, the common electrode layer and the organic light-emitting functional layer located between the pixel electrode and the common electrode layer form an organic electroluminescent photodiode, and any organic electroluminescent diode can be used as a sub-pixel of the display panel.
  • the pixel layer may further include a light extraction layer located on a side of the common electrode layer away from the base substrate to enhance the light extraction efficiency of the organic light emitting diode.
  • the display panel may further include a thin film encapsulation layer TFE.
  • the thin film encapsulation layer is provided on the surface of the pixel layer away from the base substrate, and may include alternately stacked inorganic encapsulation layers and organic encapsulation layers.
  • the inorganic encapsulation layer can effectively block external moisture and oxygen, preventing water and oxygen from invading the organic light-emitting functional layer and causing material degradation.
  • the edge of the inorganic encapsulation layer may be located in the peripheral area.
  • the organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce the stress between the inorganic encapsulation layers.
  • the edge of the organic encapsulation layer may be located between the edge of the display area and the edge of the inorganic encapsulation layer.
  • the thin film encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer and a second inorganic encapsulation layer sequentially stacked on the side of the pixel layer away from the substrate.
  • the display panel may further include a touch functional layer.
  • the touch functional layer is provided on a side of the thin film encapsulation layer away from the base substrate, and is used to implement a touch operation of the display panel.
  • the display panel may also include an anti-reflection layer.
  • the anti-reflection layer may be disposed on a side of the film encapsulation layer away from the pixel layer to reduce the reflection of ambient light by the display panel, thereby reducing the impact of ambient light on the display effect. Influence.
  • the anti-reflection layer may include a stacked color filter layer and a black matrix layer, which can avoid reducing the light transmittance of the display panel while reducing ambient light interference.
  • the anti-reflection layer may be a polarizer, for example, a patterned coated circular polarizer. Further, the anti-reflection layer may be disposed on a side of the touch functional layer away from the base substrate.
  • the display panel may include a display area AA and a peripheral area BB at least partially surrounding the display area AA. Wherein, each sub-pixel can be disposed in the display area AA.
  • the display panel also has a binding area B1 in the peripheral area BB. This binding area is provided with a plurality of pads for binding the driver chip or the circuit board to drive the display panel.
  • one end of the display area AA close to the binding area B1 can be defined as the lower end; wherein, the lower end of the display area AA is its end in the second direction H2.
  • Each data trace DL is arranged in sequence along the first direction H1, and each needs to be electrically connected to the pad in the bonding area B1 in order to receive the driving data signal from the bonding area.
  • the display panel can be provided with pad connection lines FA that correspond one-to-one to each data trace DL (only some of the pad connection lines FA are illustrated in Figure 2).
  • One end of the pad connection lines FA extends into the binding One end of the area is electrically connected to the pad, and the other end is electrically connected to the corresponding data line DL. In this way, the data trace DL is electrically connected to the pad in the bonding area B1 through the corresponding pad connection line FA.
  • the display area AA may include a first display area AA1 and two second display areas AA2 respectively located on both sides of the first display area AA1.
  • the data trace DL includes a first data trace DL1 located in the first display area AA1 and a second data trace DL2 located in the second display area AA2.
  • the display panel also includes a transfer line TR arranged in one-to-one correspondence with each of the second data lines DL2.
  • One end of the transfer line TR is connected to the corresponding second data line DL2, and the other end extends from the first display area AA1 and is electrically connected to the pad connection line FA.
  • the second data trace DL2 is connected to the transfer lines TR.
  • These transfer lines TR extend from the first display area AA1 to the display area AA and are electrically connected to the bonding area through the pad connection lines FA.
  • the second data trace DL2 does not need to extend from the second display area AA2 to the display area AA and extend toward the binding area, which saves the wiring space at the lower end of the peripheral area BB, thereby helping to reduce the frame of the display panel.
  • the present disclosure can transfer the data traces DL away from the central axis MM of the display area AA (that is, located outside the display area AA) to the area close to the inside of the display area AA, and from the area close to the central axis MM of the display area AA It is electrically connected to the binding area, thereby reducing the wiring space of the pad connection line FA, so that the display panel has an ultra-narrow lower frame.
  • the second transfer line is electrically connected to the bonding pad through the corresponding bonding pad connection line; the first data trace is electrically connected to the bonding pad through the corresponding bonding pad connection line.
  • the central axis MM of the display area AA extends along the second direction H2, the number of columns of sub-pixels on both sides of the central axis MM can be the same, and the width of the display area is basically the same; at this time, it can be considered that the display area AA extends along the central axis MM.
  • the axis MM is set symmetrically.
  • the direction close to the central axis MM of the display area AA can be defined as the inside, and the direction away from the central axis MM of the display area AA can be defined as the outside.
  • the outer data line DL is further away from the central axis MM of the display area AA.
  • each patch cord TR is arranged symmetrically about the central axis MM. In this way, the design, preparation and driving of the display panel are facilitated.
  • the top corner (lower top corner) of the display panel close to the binding area may be a non-right angle, for example, it may be an arc-shaped top corner, especially a rounded corner.
  • each column of pixel driving circuits corresponding to the arc top corners can be located in the second display area AA2.
  • the distribution range of the arc vertex angle is within the distribution range of the second display area AA2.
  • the display panel of the present disclosure has lower rounded corners and an ultra-narrow lower frame, which can realize the large-angle bending function on four sides and can improve the problem of module fit and wrinkles.
  • the arc top angle may be an ultra-narrow rounded angle.
  • the distribution range of the arc-shaped vertex angle coincides with the distribution range of the second display area AA2.
  • the data traces DL connected to each column driving circuit corresponding to the arc top corner can be transferred to the first display area AA1 through the transfer line TR.
  • the display panel may be a flexible display panel; in this way, the flexible display panel can be bent at a large angle at the top corner, and wrinkles that occur when the display panel is attached can be reduced or eliminated. , thereby improving the yield of the display device based on the display panel.
  • the display panel by switching the corresponding data traces DL at the top corners to the first display area AA1, the display panel can achieve ultra-narrow lower rounded corners and ultra-narrow lower borders, further improving the screen quality of the display device. proportion.
  • the vertex corner (upper vertex corner) of the display panel away from the binding area may also be a non-right angle, for example, it may be an arc corner, especially a rounded corner.
  • the four top corners GG of the display panel are all rounded corners.
  • the transfer line TR may include a first transfer section TR1 extending along the first direction H1 and a second transfer section TR2 extending along the second direction H2. Wherein, at least one second transfer section TR2 is located between two adjacent first data lines DL1.
  • the first data line DL1 can directly extend out of the display area AA and be electrically connected to the pad connection line FA corresponding to the first data line DL1.
  • the present disclosure is equivalent to inserting part of the pad connection lines of the second data trace DL2 between the pad connection lines of the first data trace DL1.
  • the driver of the display device can operate according to the first data trace DL1 in the display panel. and the second transfer line TR2 to adaptively adjust the driving data signal to drive the display panel.
  • the outer second data trace DL2 corresponds to the second transfer line TR2 of the transfer line TR
  • the inner second data trace DL2 corresponds to the second transfer line TR2.
  • the outside of the second adapter line TR2 of the adapter line TR the closer the second data line DL2 is to the outside, the closer the second transfer line TR2 of the second data line DL2 is to the outside. In this way, the length difference of the transfer line TR connected to each second data line DL2 is small, and the difference in the impact on the impedance of each second data line DL2 is small, which is beneficial to driving data signals on each second data line DL2. compensation.
  • the outer second data trace DL2 corresponds to the first transition section TR1 of the transition line TR
  • the inner second data trace DL2 corresponds to the first transition section TR1
  • the first transfer section TR1 of TR is close to the side of the pad connection line FA. That is, the closer the second data line DL2 is to the outside, the closer the first transfer section TR1 connected to the second data line DL2 is to the binding end.
  • the adapter line can also be arranged in other ways.
  • the second data trace on the outer side corresponds to the second transfer line of the transfer line
  • the second data trace on the inside corresponds to the second transfer line of the transfer line. the inside of.
  • the first transfer section of the transfer line corresponding to the inner second data trace is located at the lower end of the first transfer section of the transfer line corresponding to the outer second data trace. one side.
  • the lengths of each transfer line TR may be substantially the same.
  • the length of the longest transfer line TR is between 1.0 and 1.2 times the length of the shortest transfer line TR. In this way, the length difference of each transfer line TR is small, and the impact on the driving data signal loaded on the second data line DL2 is small, which is beneficial to the compensation of the driving data signal on the second data line DL2.
  • the length of the first transfer section TR1 and the second transfer line TR2 can be adjusted by adjusting the position of the first transfer section TR1 and the position of the second transfer line TR2, thereby adjusting the length of the transfer line TR. length.
  • the pixel layer EE includes a plurality of pixel groups P.
  • the pixel group includes a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3.
  • the first sub-pixel P1, the second sub-pixel The colors of P2 and third sub-pixels P3 are different from each other.
  • a plurality of first sub-pixels P1 and a plurality of third sub-pixels P3 are alternately arranged into a first pixel column along the second direction H2.
  • a plurality of second sub-pixels P2 are arranged along the second direction H2.
  • the second direction H2 is arranged into a second pixel row.
  • the first pixel row and the second pixel row are alternately arranged along the first direction H1.
  • the second sub-pixel P2 is located at the first sub-pixel P1 and the third sub-pixel in the second direction H2. between P3.
  • the first sub-pixel P1 may be a red sub-pixel
  • the second sub-pixel P2 may be a green sub-pixel
  • the third sub-pixel P3 may be a blue sub-pixel.
  • the first sub-pixel P1 and the third sub-pixel P3 located in the first pixel column are connected through a data line DL, and the plurality of second sub-pixels P2 located in the second pixel column are connected through another data line DL.
  • a plurality of data lines DL respectively connected to the first pixel column and the plurality of second pixel columns are located in the display area and extend along the second direction H2.
  • the plurality of data traces DL include a plurality of first data traces DL1 located in the first display area and a plurality of second data traces DL2 located in the second display area.
  • the display panel also includes a transfer line TR arranged in one-to-one correspondence with each second data trace DL2.
  • One end of the plurality of transfer lines TR is connected to the corresponding second data line DL2, and the other end extends from the first display area AA1 and is electrically connected to the pad connection line FA.
  • the plurality of transfer lines TR include a plurality of first transfer lines and a plurality of second transfer lines.
  • One end of the first transfer lines is connected to the second data line DL2 corresponding to the first sub-pixel P1 and the third sub-pixel P3, and the other end is connected to the second data line DL2 corresponding to the first sub-pixel P1 and the third sub-pixel P3.
  • one end of the second transfer line is connected to the second data line DL2 corresponding to the second sub-pixel P2, and the other end extends from the first display area and is electrically connected to the pad connection line FA. Electrically connected to the pad connection line FA.
  • the driving circuit layer includes different conductive layers.
  • the data traces DL are provided on the same conductive layer, and the first transfer section TR1 of the transfer line TR is provided on the same conductive layer.
  • the second transfer section TR2 can include two different types: a first sub-transfer section and a second sub-transfer section.
  • the first sub-transfer section and the second sub-transfer section can be provided on the same conductive layer, or they can located on different conductive layers.
  • the first sub-transition section refers to the second transfer section TR2 of the first transfer line
  • the second sub-transition section specifically refers to the second transfer section TR2 of the second transfer line.
  • the driving circuit layer includes a gate layer, a first source-drain metal layer LSD1 and a second source-drain metal layer LSD2.
  • the gate layer is provided on one side of the base substrate BP.
  • the first gate layer LG1, the second gate layer LG2 and the second gate layer LG3 are arranged in order.
  • the first source and drain metal layer LSD1 is provided on the side of the gate layer away from the substrate BP.
  • the metal layer LSD2 is provided on the side of the first source-drain metal layer LSD1 away from the base substrate BP.
  • the data trace DL may be disposed on the first source-drain metal layer LSD1 or the second source-drain metal layer LSD2.
  • the first transfer section TR1 may be provided on the gate layer, or may be provided on the same layer as the first source-drain metal layer LSD1.
  • the first transfer line is represented by a thick line
  • the second transfer line is represented by a thin line.
  • the transfer line provided on the side of the second source-drain metal layer LSD2 away from the base substrate BP is represented by a solid line, and is provided on the second source-drain metal layer.
  • the transfer line on the conductive layer between LSD2 and the base substrate BP is represented by a dotted line. Because the first transfer section is located in the conductive layer below the second source-drain metal layer LSD2, the dotted line is used to represent the first connection section in Figures 6 to 10.
  • the first switching section TR1 of the switching wire and the first switching section TR1 of the second switching wire is used to represent the first connection section in Figures 6 to 10.
  • the first switching section TR1 of the switching wire and the first switching section TR1 of the second switching wire is used to represent the first connection section in Figures 6 to 10.
  • the first switching section TR1 of the switching wire and the first switching section TR1 of the second switching wire is used to represent the first connection section in
  • the first sub-transfer section and the second sub-transfer section when the first sub-transfer section and the second sub-transfer section are provided on the same conductive layer, the first sub-transfer section and the first source-drain metal layer LSD1 can be provided on the same layer,
  • the second sub-transfer section is arranged on the same layer as the first source-drain metal layer LSD1; the first sub-transfer section and the second source-drain metal layer LSD2 can also be arranged on the same layer, and the second sub-transfer section is arranged on the same layer as the second source-drain metal layer LSD2.
  • the metal layer LSD2 is set on the same layer.
  • the wiring space between two adjacent first data lines DL1 is a gap obtained by sub-pixel compression.
  • the transfer line is placed in the gap created by sub-pixel compression. Due to the Due to the limitation of pixel original pixel density (PPI), the space that can be compressed is limited.
  • PPI pixel original pixel density
  • the first sub-transfer section and the second sub-transfer section can usually be located in different conductive layer.
  • the first sub-transfer section and the second source-drain metal layer LSD2 are arranged on the same layer, the second sub-transfer section is arranged on the same layer as the first source-drain metal layer LSD1, and the first transfer section can also be arranged on the same layer as the first source-drain metal layer LSD1.
  • the second source-drain metal layer LSD2 is arranged on the same layer, and the second sub-transfer section and the first source-drain metal layer LSD1 are arranged on the same layer.
  • the scan line extends along the first direction and is provided between the base substrate and the first source and drain metal layer. It can be understood that although the resistance R of the first source-drain metal layer LSD1 and the second source-drain metal layer LSD2 is the same, the distance between the first source-drain metal layer LSD1 and the second source-drain metal layer LSD2 and the scanning line Different, therefore the parasitic capacitance between the first source-drain metal layer LSD1 and the scanning line is different from the parasitic capacitance between the second source-drain metal layer LSD2 and the scanning line.
  • the waveform W1 of the second data line DL2 connected to the first pixel column is transitional; the waveform W2 of the second data line DL2 connected to the second pixel column is a straight line.
  • the first sub-transition section can be set at the second source-drain metal layer, and the second sub-transition section is provided on the first source-drain metal layer.
  • the parasitic capacitance between the first sub-transfer section and the scan line is small, and the second data line DL2 connected to the first pixel column has a small parasitic capacitance.
  • the waveform jump has a small impact on the parasitic capacitance, so the fluctuation of the internal resistance voltage drop (RC Loading) is small, and the impact on the display effect of the display panel is small.
  • the distance between the second sub-transition section and the scanning line is small, although the parasitic capacitance generated is large, and the waveform of the second data line DL2 connected to the second pixel column is a straight line, the parasitic capacitance and internal resistance The voltage drop will not fluctuate and will have no impact on the display effect of the display panel.
  • the number of second data lines DL2 that need to be transferred or the number of second transfer sections that can be inserted between two columns of first data lines DL1 cannot be divisible by 2 or 4, depending on the size of the gap, it may be considered to One sub-transfer section is distributed in different conductive layers, or the second sub-transfer section is distributed in different conductive layers.
  • the parasitic capacitance and internal resistance voltage drop of the second data line connected to the second pixel column will not cause fluctuations.
  • the first sub-transfer section and the second source-drain metal layer LSD2 can be arranged on the same layer, a part of the second sub-transfer section and the first source-drain metal layer LSD1 can be arranged on the same layer, and the other part of the second sub-transfer section can be arranged on the same layer as the first source-drain metal layer LSD1.
  • the two sub-transfer sections are arranged on the same layer as the second source-drain metal layer.
  • the second sub-transition sections may be alternately distributed on the first source-drain metal layer LSD1 and the second source-drain metal layer LSD2.
  • the second transfer section group TR2S includes at least one second transfer section TR2 of the first transfer line and at least two second transfer sections TR2 of the second transfer line, and all the second transfer sections TR2 of the first transfer line
  • the second transfer section TR2 of at least one second transfer line is arranged on the same layer as the second source-drain metal layer LSD2 and the first source-drain metal layer LSD1.
  • the second transfer section TR2 of at least one second transfer line is arranged on the same layer as the first source-drain metal layer LSD1. It is arranged on the same layer as the second source-drain metal layer LSD2.
  • the first sub-pixel P1 is a red sub-pixel
  • the second sub-pixel P2 is a green sub-pixel
  • the third sub-pixel P3 is a blue sub-pixel. Therefore, the first transfer line is connected to the second data line DL2 corresponding to the red sub-pixel and the blue sub-pixel, and the second transfer line is connected to the second data line DL2 corresponding to the green sub-pixel.
  • the pixel group includes a first sub-pixel P1, two second sub-pixels P2 and a third sub-pixel P3, and the second transfer section group TR2S includes a corresponding first sub-pixel P1 and a third sub-pixel P3.
  • the transfer section TR2 is arranged on the same layer as the second source-drain metal layer LSD2.
  • the second transfer section TR2 of a second transfer line is arranged on the same layer as the first source-drain metal layer LSD1.
  • the second transfer section TR2 of the second transfer line is arranged on the same layer as the first source-drain metal layer LSD1.
  • the connection section TR2 is arranged on the same layer as the second source-drain metal layer LSD2.
  • the display panel when the number of transfer lines is small or the gap compressed by sub-pixels is large, the display panel generally tries to correspond to the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3.
  • the second transfer section TR2 of the second data trace is located on the same conductive layer.
  • the second source-drain metal layer LSD2 is used, which can reduce the number of data traces DL and the lower backplane signal lines, such as scan lines. crosstalk between data trace signals; when the crosstalk between data trace signals is acceptable, the first source-drain metal layer LSD1 can also be used.
  • the number of second transfer sections TR2 that can be inserted between two adjacent first data traces DL1 is limited. If the first source-drain metal layer LSD1 or the second source-drain metal layer LSD2 is used, it may not be possible to insert all the second transfer sections TR2 connected by the second data lines; in this case, the first sub-pixel P1 and the third
  • the second transfer section TR2 of the first transfer line corresponding to the sub-pixel P3 is provided on the second source-drain metal layer LSD2, and the second transfer section TR2 of the second transfer line corresponding to the second sub-pixel P2 is provided on the first source-drain metal layer LSD2.
  • the metal layer LSD1 can specifically distribute the second transfer section TR2 of the first transfer line and the second transfer section of the second transfer line TR2 alternately on the first source-drain metal layer LSD1 and the second source-drain metal layer LSD2;
  • the first transition segments corresponding to the first sub-pixel P1 and the third sub-pixel P3 are The second transfer section TR2 of the wiring is provided on the second source-drain metal layer LSD2, and the second transfer section TR2 of the second transfer line corresponding to the second sub-pixel P2 is provided on the first source-drain metal layer LSD1 or the second source-drain Metal layer LSD2.
  • the second transfer section TR2 of the first transfer line corresponding to the red sub-pixel and the blue sub-pixel that are sensitive to the human eye adopts the second source-drain metal layer LSD2, and the second transfer section TR2 of the second transfer line corresponding to the green sub-pixel is
  • the second transfer section TR2 is replaced with the first source-drain metal layer LSD1 at the position where the second source-drain metal layer LSD2 cannot be used, thereby achieving uniform display of the entire screen.
  • the two second sub-transfer sections symmetrically arranged with respect to the central axis extending along the second direction H2 are arranged on the same layer, so that the display brightness of the display panel at a symmetrical position with respect to the central axis extending along the second direction H2 tends to be same.
  • the other side of the central axis MM is symmetrical with the second second sub-transfer section
  • the second sub-transfer section is also provided on the first source-drain metal layer LSD1; when the third second sub-transfer section distributed on one side of the central axis is provided on the second source-drain metal layer LSD2, then the other side of the central axis
  • a second sub-transition section that is symmetrical to the fourth second sub-transition section is also provided in the second source-drain metal layer LSD2.
  • the driving circuit layer is provided with the thin film transistor of the driving circuit, and the transfer line TR does not overlap with the thin film transistor. Further, the position and gap of each thin film transistor can be adjusted as needed to reserve space for laying the transfer line TR.
  • the driving circuit layer is provided with driving circuits corresponding to each sub-pixel
  • the display panel may include a driving circuit area PDCA arranged in one-to-one correspondence with each driving circuit.
  • most or all transistors of the driving circuit may be located in the driving circuit area PDCA corresponding to the driving circuit, and a few transistors of the driving circuit may be located in the adjacent driving circuit area PDCA to facilitate the layout and multiplexing of signal lines.
  • the transfer line TR does not overlap with the drive circuit area PDCA.
  • the driving circuit layer may also include a transistor layer, and the transistor layer may include a semiconductor layer and a gate electrode layer.
  • the source-drain metal layer is provided with wiring and a conductive structure, and the conductive structure is used to electrically connect the transistor and the wiring.
  • the driving circuit area PDCA corresponding to the driving circuit can be defined according to the distribution range of the conductive structure of the driving circuit.
  • the drive circuit area PDCA is a rectangular area, the long sides of the rectangular area extend along the column square, and the short sides extend along the first direction; each conductive structure of the drive circuit is located in the drive circuit corresponding to the drive circuit. District PDCA.
  • the driving circuit has a storage capacitor, a driving transistor, and a data writing transistor connected to the data line DL; wherein, the storage capacitor, driving transistor, and data writing transistor of the driving circuit are all located at the corresponding driving position of the driving circuit.
  • the circuit area PDCA In the circuit area PDCA.
  • At least one thin film transistor of the upper row drive circuit is located in the drive circuit area PDCA corresponding to the next row drive circuit; the remaining thin film transistors of the upper row drive circuit Located in the drive circuit area PDCA corresponding to the drive circuit.
  • the driving circuit is provided with an electrode reset transistor for resetting the pixel electrode; the electrode reset transistor of the driving circuit may be located in the driving circuit area PDCA corresponding to the next row of driving circuits.
  • the electrode reset transistor of the driving circuit of the previous row is also provided inside.
  • the driving circuit layer includes driving circuit islands PDCC distributed in an array, and any driving circuit island PDCC includes one or more driving circuit areas PDCA corresponding to each driving circuit one-to-one; at least one of the driving circuits Some transistors are arranged in corresponding drive circuit areas PDCA.
  • the wiring space between two adjacent first data lines is a gap obtained by sub-pixel compression.
  • the transfer line is placed in the gap created by sub-pixel compression, specifically the driving circuit of the compressed sub-pixel.
  • each driving circuit area PDCA in a driving circuit island PDCC is arranged adjacent to each other in sequence, and there is a gap between the driving circuit islands PDCC.
  • the transfer line TR is disposed in the gap between the drive circuit islands PDCC.
  • the driving circuit island PDCCs may be arranged into a plurality of driving circuit island PDCC rows, and each driving circuit island PDCC row includes a plurality of driving circuit island PDCCs arranged along the first direction H1, each of which The PDCC rows of the driving circuit islands are arranged sequentially along the second direction H2.
  • a row gap CC is provided between two adjacent PDCC rows of driving circuit islands.
  • the driving circuit island PDCCs can be arranged into multiple driving circuit island PDCC columns.
  • Each driving circuit island PDCC column includes a plurality of driving circuit island PDCCs arranged along the second direction H2.
  • Each driving circuit island PDCC column is sequentially arranged along the first direction. arrangement.
  • a column gap DD is provided between two adjacent driving circuit island PDCC columns.
  • the transfer line TR is provided in the gap between the driving circuit islands PDCC.
  • the gap can be the row gap CC or the column gap DD as shown in Figure 12.
  • each driving circuit area PDCA in the driving circuit island PDCC can be arranged compactly, which facilitates the formation of a larger gap between the driving circuit islands PDCC, thereby facilitating the layout of the transfer line TR. It can be understood that when some thin film transistors of the driving circuit are not located in the driving circuit area PDCA corresponding to the driving circuit, these thin film transistors can be located in other driving circuit areas PDCA in the same driving circuit island PDCC, or can be located in adjacent driving circuits.
  • the driving circuit area PDCA in the island PDCC is not limited by this disclosure.
  • the driving circuits are arranged into a plurality of driving circuit groups, and each driving circuit group includes two driving circuits adjacent and mirrored along the first direction H1.
  • the two drive circuit areas PDCA corresponding to the two drive circuits of the drive circuit group are arranged adjacently and located in the same drive circuit island PDCC.
  • adjacent drive circuits may not adopt a mirror design, and the patterns of two adjacent drive circuits may be basically the same.
  • the driving circuit areas PDCA in the driving circuit island PDCC are arranged in multiple rows and columns, so that the driving circuit island PDCC has a larger area, thereby making the gap size between the driving circuit islands PDCC larger, which is beneficial to A transfer line TR is laid in the gap between the drive circuit islands PDCC.
  • the driving circuit areas PDCA in the driving circuit island PDCC are arranged in two rows and four columns.
  • the number of transfer lines TR set in the gap between the drive circuit islands PDCC can be adjusted according to the actual wiring requirements on the one hand, and on the other hand it is affected by the gap size, the width of the transfer lines TR, the spacing of the transfer lines TR, and the film layer of the transfer lines TR. constraints.
  • the smaller the gap between the driving circuit islands PDCC the smaller the number of transfer lines TR that can be laid in the gap.
  • the number of second transfer lines TR2 between the PDCC columns of the drive circuit island can be determined according to process requirements, and can be any number from 1 to 6, for example.
  • Dotted lines represent the wiring on the first source-drain metal layer LSD1
  • solid lines represent the wiring on the second source-drain metal layer LSD2.
  • the data trace DL is provided on the second source-drain metal layer LSD2;
  • the transfer line TR includes a first transfer section TR1 extending along the first direction H1 and a second transfer section TR2 extending along the second direction H2.
  • the section TR1 is provided on the first source-drain metal layer, and the second transfer section is provided on the first source-drain metal layer or the second source-drain metal layer.
  • the first sub-transfer section and the second sub-transfer section can be directly arranged on the second source-drain metal Layer LSD1.
  • the first sub-transfer section and the second sub-transfer section can also be directly provided on the second source-drain metal layer LSD2.
  • the first sub-transfer section TR2 may be entirely disposed on the second source-drain metal layer LSD2, and the second sub-transfer section TR2 may be entirely disposed on the first source-drain metal layer LSD1.
  • the first sub-transfer section TR2 can also be entirely provided on the second source-drain metal layer LSD2, and the second transfer line TR2 is alternately provided on the first source-drain metal layer LSD1 and the second source-drain metal layer Layer LSD2.
  • the end of the first data trace DL1 close to the bonding area is directly connected to the corresponding pad connection line FA.
  • the second data line DL2 is connected to the pad connection line FA through the transfer line TR.
  • the display panel further includes a transfer line TR electrically connected to at least part of the first data line DL1 in a one-to-one correspondence.
  • the transfer line TR is electrically connected to the second data line DL2 and at least part of the first data line DL1 in a one-to-one correspondence.
  • the transfer line TR corresponding to each data line DL is electrically connected to the pad connection line FA corresponding to the data line DL.
  • the first data line DL1 can be directly electrically connected to the pad connection line FA.
  • the source and drain metal layers have enough space to lay out enough transfer lines TR, for example, when the resolution of the display panel is low (for example, PPI is less than 410), this can further adjust the wiring sequence and position of the pad connection lines FA, which is beneficial to the display panel. preparation and optimization.
  • the arrangement order of the pad connection lines FA corresponding to each data line DL is consistent with the arrangement order of each data line DL. In this way, the structure of the external driving circuit, such as the structure of the driving chip, can be simplified.
  • the driving circuits arranged in the same row can be arranged in pairs to form multiple driving circuit groups, and the two driving circuits in one driving circuit group can be arranged in mirror images.
  • four drive circuit groups in two adjacent rows and two columns are used as a drive circuit island PDCC.
  • the minimum size of the driving circuit group in the first direction H1 can reach 49 microns.
  • the first display area AA1 is divided into two arrangement areas located on both sides of the central axis MM.
  • the arrangement of the data traces DL and the transfer lines TR can be symmetrical about the central axis MM, or they can be different.
  • the arrangement of the data traces DL and the transfer lines TR can be symmetrical about the central axis MM.
  • the number of data traces DL is n; in order from the outside to the inside, the i-th data trace DL is recorded as data trace DL(i).
  • the number of second data traces DL2 is x
  • the number of first data traces DL1 is n-x.
  • the data traces DL(1) to DL(x) are the second data traces DL2;
  • the data traces DL(x+1) to DL(n) are the first data traces DL1.
  • the second transfer section TR2 of the transfer line TR connected to the data line DL(i) can be recorded as the second transfer section TR(i).
  • the pixel density of the display panel is no higher than 410PPI (Pixels Per Inch).
  • the minimum size of the driving circuit group in the first direction H1 can be compressed to 49 microns. In this way, the width of the column gap DD of the driving circuit island PDCC in the first direction H1 can reach more than 13 microns.
  • the gaps between the PDCC columns of the driving circuit island can accommodate up to six second transfer sections TR2.
  • six second transfer sections TR2 in a second transfer section group TR2S are alternately distributed in the first source-drain metal layer LSD1 and the second source-drain metal layer LSD2.
  • the second transfer section of the first transfer line may be provided on the second source-drain metal layer LSD2, and at least part of the second transfer section of the second transfer line may be provided on the second source-drain metal layer LSD2.
  • the number of second data lines or the number of second transfer sections that can be inserted between two columns of first data lines can be divisible by 2 or 4, depending on the size of the gap, see Figure 18,
  • the second transfer section of all the second transfer lines is provided on the second source-drain metal layer LSD1; referring to Figure 19, it can also be considered to set the second transfer section of the second transfer line on the first source-drain metal layer LSD2.
  • Another part of the second transfer section is provided in the second source-drain metal layer LSD2.
  • the second transfer section of the first transfer line and the second transfer section of the second transfer line can both be provided on the second source-drain metal layer LSD2.
  • the lower end of the first data trace DL1 is connected to the corresponding pad connection line FA to be connected to the bonding area.
  • the lower end of the second data trace DL2 is not connected to the pad connection line FA, but is connected to each transfer line TR in one-to-one correspondence; the second transfer section TR2 of each transfer line TR is provided in the first display area AA1, and the second The end (lower end) of the transfer section TR2 close to the binding end is connected to the pad connection line FA to connect to the binding area.
  • at least part of the second transfer section TR2 is disposed in the gap between the driving circuit islands PDCC.
  • the second transfer section TR2 and the first data trace DL1 in an arrangement area can be arranged in the following order: a second transfer section The connection segment group TR2S, four first data traces DL1, one second transfer segment group TR2S, four first data traces DL1,... the last second transfer segment group TR2S, and the remaining second transfer segment group TR2S One data trace DL1.
  • the other second transfer section groups TR2S have six second transfer sections TR2; the second transfer section TR2 in the last second transfer section group TR2S No more than six in number.
  • the transfer lines TR and the first data traces DL1 in one arrangement area can be arranged in the following order: second transfer section TR(1) ⁇ second transfer section TR(6), data trace DL(x+1) ⁇ data trace DL(x+4), second transfer section TR(7) ⁇ second transfer section TR(12), data trace DL( x+5) ⁇ data trace DL(x+8) ⁇ The second transfer section TR(x) and the remaining first data trace DL1.
  • the second transfer section TR(1), the second transfer section TR(3), and the second transfer section TR(5) are the second transfer sections of the second transfer line.
  • the connection section is located at the first source-drain metal layer LSD1.
  • the second transfer section TR(2), the second transfer section TR(4), and the second transfer section TR(6) are the second transfer sections of the second transfer line.
  • the connection section is located in the second source-drain metal layer LSD2.
  • the difference from the first case is that the second transfer section TR(1) and the second transfer section TR(3) are located in the second source-drain metal layer LSD2
  • the second transfer section TR(5) is located on the first source-drain metal layer LSD1.
  • the number of transfer lines TR may exceed the second data traces DL2, so that the transfer lines TR are electrically connected to each data trace DL in a one-to-one correspondence.
  • the ends (lower ends) of the second data trace DL2 and the first data trace DL1 close to the binding end are not electrically connected to the pad connection line FA, but are both electrically connected to the pad connection line through the electrically connected transfer line TR. FA electrical connection.
  • each second transfer section TR2 may be disposed in the first display area AA1 and arranged in the same order as the respective connected data traces DL in the first direction H1. Specifically, in an arrangement area, along the direction from the outside to the inside, the second transfer section TR2 is arranged in the following order: the second transfer section TR(1), the second transfer section TR(2) , the second transfer section TR(3), the second transfer section TR(4)... the second transfer section TR(n).
  • the pixel density of the display panel is between 410 and 425PPI (Pixels Per Inch).
  • the minimum size of the driving circuit group in the first direction H1 can be compressed to 49 microns.
  • the column gap DD of the driving circuit island PDCC in the first direction H1 can reach 10.8 microns to 12.2 microns; the gap between the driving circuit island PDCC columns can accommodate up to 5 second transfer segments TR2.
  • as five second transfer sections TR2 in a second transfer section group TR2S they can be distributed alternately in the first source-drain metal layer LSD1 and the second source-drain metal layer LSD2.
  • the five second transfer sections TR2 can all be provided on the second source-drain metal layer LSD2.
  • one end (lower end) of the first data trace DL1 close to the bonding end is connected to the pad connection line FA to be connected to the bonding area.
  • the end of the second data trace DL2 close to the bonding area is not connected to the pad connection line FA, but is connected to each transfer line TR in a one-to-one correspondence; the second transfer section TR2 of each transfer line TR is provided in the first display area AA1, and the end of the second transfer section TR2 close to the bonding end is connected to the pad connection line FA to be connected to the bonding area.
  • at least part of the second transfer section TR2 is disposed in the gap between the driving circuit islands PDCC.
  • the transition lines TR and the first data traces DL1 in an arrangement area can be arranged in the following order: one second transition segment group TR2S, four first data traces Trace DL1, a second transfer segment group TR2S, four first data traces DL1,... the last second transfer segment group TR2S, and the remaining first data traces DL1.
  • the other second transfer section groups TR2S all have 5 second transfer sections TR2; the second transfer section TR2 in the last second transfer section group TR2S The quantity does not exceed 5.
  • the transfer lines TR and the first data traces DL1 in one arrangement area can be arranged in the following order: second transfer section TR(1) ⁇ second transfer section TR(5), data trace DL(x+1) ⁇ data trace DL(x+4), second transfer section TR(6) ⁇ second transfer section TR(10), data trace DL( x+5) ⁇ data trace DL(x+8) ⁇ The second transfer section TR(x) and the remaining first data trace DL1.
  • the pixel density of the display panel is between 425 and 430PPI (Pixels Per Inch).
  • the minimum size of the driving circuit group in the first direction H1 can be compressed to 49 microns.
  • the column gap DD of the driving circuit island PDCC in the first direction H1 can reach 10.1 microns; see Figure 16, the gap between the driving circuit island PDCC columns can accommodate up to four second transfer segments TR2.
  • the four second transfer sections TR2 may all be provided on the second source-drain metal layer LSD2.
  • one end of the first data trace DL1 close to the bonding end is connected to the pad connection line FA to be connected to the bonding area.
  • the end of the second data trace DL2 close to the bonding area is not connected to the pad connection line FA, but is connected to each transfer line TR in a one-to-one correspondence; the second transfer section TR2 of each transfer line TR is provided in the first display area AA1, and the end of the second transfer section TR2 close to the bonding end is connected to the pad connection line FA to be connected to the bonding area.
  • at least part of the second transfer section TR2 is disposed in the gap between the driving circuit islands PDCC.
  • the transition lines TR and the first data traces DL1 in an arrangement area can be arranged in the following order: one second transition segment group TR2S, four first data traces Trace DL1, a second transfer segment group TR2S, four first data traces DL1,... the last second transfer segment group TR2S, and the remaining first data traces DL1.
  • the other second transfer section groups TR2S all have four second transfer sections TR2; the second transfer section TR2 in the last second transfer section group TR2S The quantity does not exceed 4.
  • the transfer lines TR and the first data traces DL1 in one arrangement area can be arranged in the following order: second transfer section TR(1) ⁇ second transfer section TR(4), data trace DL(x+1) ⁇ data trace DL(x+4), second transfer section TR(5) ⁇ second transfer section TR(8), data trace DL( x+5) ⁇ data trace DL(x+8) ⁇ The second transfer section TR(x) and the remaining first data trace DL1.
  • the pixel density of the display panel is between 430 and 450PPI (Pixels Per Inch).
  • the minimum size of the driving circuit group in the first direction H1 can be compressed to 49 microns.
  • the column gap DD of the driving circuit island PDCC in the first direction H1 can reach 7.4 microns; see Figure 15, the gap between the driving circuit island PDCC columns can accommodate up to three second transfer segments TR2.
  • the three second transfer sections TR2 may all be provided on the second source-drain metal layer LSD2.
  • one end of the first data trace DL1 close to the bonding end is connected to the pad connection line FA to be connected to the bonding area.
  • the end of the second data trace DL2 close to the bonding area is not connected to the pad connection line FA, but is connected to each transfer line TR in a one-to-one correspondence; the second transfer section TR2 of each transfer line TR is provided in the first display area AA1, and the end of the second transfer section TR2 close to the bonding end is connected to the pad connection line FA to be connected to the bonding area.
  • at least part of the second transfer section TR2 is disposed in the gap between the driving circuit islands PDCC.
  • the transition lines TR and the first data traces DL1 in an arrangement area can be arranged in the following order: one second transition segment group TR2S, four first data traces Trace DL1, a second transfer segment group TR2S, four first data traces DL1,... the last second transfer segment group TR2S, and the remaining first data traces DL1.
  • the other second transfer section groups TR2S all have three second transfer sections TR2; the second transfer section TR2 in the last second transfer section group TR2S The quantity does not exceed 3.
  • the transfer lines TR and the first data traces DL1 in one arrangement area can be arranged in the following order: second transfer section TR(1) ⁇ second transfer section TR(3), data trace DL(x+1) ⁇ data trace DL(x+4), second transfer section TR(4) ⁇ second transfer section TR(6), data trace DL( x+5) ⁇ data trace DL(x+8) ⁇ The second transfer section TR(x) and the remaining first data trace DL1.
  • the pixel density of the display panel is between 450 and 465PPI (Pixels Per Inch).
  • the minimum size of the driving circuit group in the first direction H1 can be compressed to 49 microns.
  • the column gap DD of the driving circuit island PDCC in the first direction H1 can reach 5.6 microns; see Figure 14, the gap between the driving circuit island PDCC columns can accommodate up to two second transfer segments TR2.
  • the two second transfer sections TR2 may both be provided on the second source-drain metal layer LSD2.
  • one end of the first data trace DL1 close to the bonding end is connected to the pad connection line FA to be connected to the bonding area.
  • the end of the second data trace DL2 close to the bonding area is not connected to the pad connection line FA, but is connected to each transfer line TR in a one-to-one correspondence; the second transfer section TR2 of each transfer line TR is provided in the first display area AA1, and the end of the second transfer section TR2 close to the bonding end is connected to the pad connection line FA to be connected to the bonding area.
  • at least part of the second transfer section TR2 is disposed in the gap between the driving circuit islands PDCC.
  • the transition lines TR and the first data traces DL1 in an arrangement area can be arranged in the following order: one second transition segment group TR2S, four first data traces Trace DL1, a second transfer segment group TR2S, four first data traces DL1,... the last second transfer segment group TR2S, and the remaining first data traces DL1.
  • the other second transfer section groups TR2S all have three second transfer sections TR2; the second transfer section TR2 in the last second transfer section group TR2S The quantity does not exceed 3.
  • the transfer lines TR and the first data traces DL1 in one arrangement area can be arranged in the following order: second transfer section TR(1) ⁇ second transfer section TR(2), data trace DL(x+1) ⁇ data trace DL(x+4), second transfer section TR(3) ⁇ second transfer section TR(4), data trace DL( x+5) ⁇ data trace DL(x+8) ⁇ The second transfer section TR(x) and the remaining first data trace DL1.
  • the pixel density of the display panel is between 465 and 490PPI (Pixels Per Inch).
  • the minimum size of the driving circuit group in the first direction H1 can be compressed to 49 microns.
  • the gap between the driving circuit island PDCCs in the first direction H1 can reach 2.8 microns; see Figure 13, the gaps between the driving circuit island PDCC columns can accommodate at most one second transfer section TR2.
  • This second transfer section The segment TR2 may be disposed on the second source-drain metal layer LSD2.
  • one end of the first data trace DL1 close to the bonding end is connected to the pad connection line FA to be connected to the bonding area.
  • the end of the second data trace DL2 close to the bonding area is not connected to the pad connection line FA, but is connected to each transfer line TR in a one-to-one correspondence; the second transfer section TR2 of each transfer line TR is provided in the first display area AA1, and the end of the second transfer section TR2 close to the bonding end is connected to the pad connection line FA to be connected to the bonding area.
  • at least part of the second transfer section TR2 is disposed in the gap between the driving circuit islands PDCC.
  • the transition lines TR and the first data traces DL1 in an arrangement area can be arranged in the following order: one second transition segment group TR2S, four first data traces Trace DL1, a second transfer segment group TR2S, four first data traces DL1,... the last second transfer segment group TR2S, and the remaining first data traces DL1.
  • Each second transfer section group TR2S has only one second transfer section TR2.
  • the transfer lines TR and the first data traces DL1 in one arrangement area can be arranged in the following order: the second transfer section TR(1), the data traces DL( x+1) ⁇ data trace DL(x+4), second transfer section TR(2), data trace DL(x+5) ⁇ data trace DL(x+8) ⁇ The second transfer section TR(x), data wiring DL(5x-3) ⁇ data wiring DL(n).
  • each second transfer section TR2 may be disposed in the first display area AA1 and arranged in the same order as the respective connected data traces DL in the first direction H1.
  • the second transfer section TR2 is arranged in the following order: the second transfer section TR(1), the second transfer section TR(2) , the second transfer section TR(3), the second transfer section TR(4)... the second transfer section TR(n).
  • the first display area AA1 may include two arrangement areas respectively located on both sides of the central axis MM; wherein the central axis MM extends along the second direction H2.
  • the transfer line TR and the first data trace DL1 are arranged symmetrically about the central axis MM.
  • each second transfer section TR2 can be arranged into a plurality of second transfer section groups TR2S; each second transfer section TR2 in any second transfer section group TR2S is located in the same position. Between two adjacent drive circuit island PDCC columns (that is, located in the same column gap DD); any two adjacent second transfer section groups TR2S are isolated by the drive circuit island PDCC column; any second transfer section group TR2S The connection section group TR2S includes one or more second connection sections TR2.
  • each second transfer section TR2 in the second transfer section group TR2S is located between two adjacent data lines DL, for example, located on the data line DL numbered m (m ) and the data trace DL(m+1) numbered m+1.
  • the number of second transition sections TR2 in any second transition section group TR2S does not exceed six. In other words, the number of second transfer sections TR2 between two adjacent driving circuit island PDCC columns does not exceed six.
  • a plurality of second transfer sections are arranged into a plurality of second transfer section groups; each second transfer section group includes at least two adjacent second transfer sections;
  • the first data traces are arranged into a plurality of first data trace groups, and each first data trace group includes a plurality of adjacent first data traces; in at least part of the first display area, the first data traces
  • the wiring group and the second transfer segment group are set alternately one by one.
  • the number of second transfer sections TR2 of each second transfer section group TR2S is the same. In another embodiment of the present disclosure, in at least one arrangement area, one of the second transfer section groups TR2S has a smaller number of second transfer sections TR2 , and the remaining second transfer section groups TR2S have There are more and the same number of second transfer sections TR2.
  • the outermost or innermost second transfer section group TR2S has fewer second transfer section groups TR2, and the remaining second transfer section groups TR2S include more And the same number of second transfer sections TR2.
  • the number of second transfer sections TR2 in each second transfer section group TR2S can be independently set as needed, and the number of the second transfer section TR2 in any two second transfer section groups TR2S
  • the number of transition sections TR2 may be the same or different.
  • the area where each second transfer section group TR2S is distributed can be defined as the second transfer area TR2A.
  • the drive circuit island PDCC columns and the second transfer segment group TR2S are arranged in sequence at intervals. In this way, the size of the second transfer area TR2A in the first direction H1 can be compressed. The starting position or the ending position of the second transfer section group TR2S can be adjusted as needed.
  • the starting position of the second transfer area TR2A (that is, the starting position of the second transfer segment group TR2S arranged from the outside to the inside) may be close to the first display area AA1 outside.
  • the outermost second transfer section group TR2S is arranged adjacent to the outermost drive circuit island PDCC column.
  • the outermost second transfer segment group TR2S is located outside the outermost first data trace DL1.
  • the end position of the second transfer area TR2A (that is, the end position of the second transfer segment group TR2S arranged from the outside to the inside) may be close to the first display area AA1 Central axis MM; for example, in at least one arrangement area, the innermost second transfer section group TR2S is arranged adjacent to the innermost drive circuit island PDCC column.
  • the second transfer area TR2A in at least one arrangement area, may be distributed throughout the entire arrangement area.
  • the second transfer section group TR2S may be uniformly or non-uniformly distributed in the arrangement area along the first direction H1.
  • each second transfer segment group TR2S is distributed in the first display area AA1 along the first direction H1.
  • each first transfer section TR1 can be arranged into multiple first transfer section groups TR1S; each first transfer section TR1 in any first transfer section group TR1S is located in two adjacent drive sections. Between the circuit island PDCC rows (that is, located in the same row gap CC), and located in the same arrangement area; any two adjacent first transfer section groups TR1S are isolated by the driving circuit island PDCC row; any one of the first transfer section groups TR1S is isolated A transfer section group TR1S includes one or more first transfer sections TR1.
  • the number of first transition sections TR1 in any first transition section group TR1S does not exceed three. In other words, between two adjacent rows of drive circuit island PDCCs, the number of first transition sections TR1 does not exceed three.
  • the number of first transition sections TR1 of each first transition section group TR1S is the same.
  • one of the first transfer section groups TR1S has a smaller number of first transfer sections TR1 , and the remaining first transfer section groups TR1S have There are more and the same number of first transfer sections TR1.
  • the first transfer section group TR1S closest to the pad connection line FA or farthest from the pad connection line FA has fewer first transfer sections TR1, and the remaining The first transfer section group TR1S includes a larger and the same number of first transfer sections TR1.
  • first transfer sections TR1 in each first transfer section group TR1S can be independently set as needed, and the number of the first transfer section TR1 in any two first transfer section groups TR1S
  • the number of transfer sections TR1 may be the same or different.
  • the area where each first transfer section group TR1S is distributed can be defined as the first transfer area TR1A.
  • the drive circuit island PDCC rows and the first transfer section group TR1S are arranged in sequence at intervals. In this way, the size of the first transfer area in the second direction H2 can be compressed.
  • a specific structure of a display panel is used as an example to further explain and illustrate the structure and principles of the display panel of the present disclosure. It can be understood that in the display panel of the present disclosure, the structure of the driving circuit may be other structures than this example, as long as the driving of the sub-pixels can be realized.
  • the driving circuit may include a capacitance reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light emitting control transistor T5, a second light emitting control transistor T6, and electrode reset transistor T7, and includes storage capacitor C.
  • the capacitor reset transistor T1 and the threshold compensation transistor T2 are N-type thin film transistors, such as metal oxide thin film transistors; the remaining transistors TFT are P-type thin film transistors, such as low-temperature polysilicon thin film transistors.
  • the source of the capacitor reset transistor T1 is used to load the capacitor reset voltage Vinit1, the gate is used to load the capacitor reset control signal Re1, and the drain is connected to the first node N1.
  • the capacitor reset transistor T1 is used to load the capacitor reset voltage Vinit1 to the first node N1 in response to the capacitor reset control signal Re1.
  • the source of the threshold compensation transistor T2 is electrically connected to the third node N3, the drain is electrically connected to the first node N1, and the gate is used to load the first scan signal G1; the threshold compensation transistor T2 is used to conduct the signal in response to the first scan signal G1. to write the threshold voltage of the driving transistor T3 into the first node N1.
  • the source of the driving transistor T3 is connected to the second node N2, the drain is connected to the third node N3, and the gate is connected to the first node N1.
  • the source of the data writing transistor T4 is used to load the driving data signal Da, the drain is electrically connected to the second node N2, and the gate is used to load the second scanning signal G2.
  • the data writing transistor T4 is used to load the driving data signal Da to the second node N2 in response to the second scanning signal G2.
  • the source of the first light-emitting control transistor T5 is used to load the power supply voltage VDD, the drain is connected to the second node N2, and the gate is used to load the enable signal EM.
  • the source of the second light-emitting control transistor T6 is connected to the third node N3, the drain is connected to the sub-pixel (the organic electroluminescent diode OLED is used as an example in FIG. 23), and the gate is used to load the enable signal EM.
  • the first light emission control transistor T5 and the second light emission control transistor T6 are configured to be turned on in response to the enable signal EM.
  • the source of the electrode reset transistor T7 is used to load the electrode reset voltage Vinit2, the drain is connected to the light-emitting element, and the gate is used to load the electrode reset control signal Re2.
  • the electrode reset transistor T7 is used to respond to the electrode reset control signal Re2 to load the electrode reset voltage Vinit2 to the light-emitting unit.
  • the pixel electrode of the light-emitting element is electrically connected to the driving circuit, and the common electrode is used to load the common voltage VSS.
  • One end of the storage capacitor C is connected to the first node N1, and the other end is used to load the power supply voltage VDD.
  • FIG. 24 shows a driving timing diagram of the driving circuit of this example.
  • G1 represents the timing of the first scanning signal G1
  • G2 represents the timing of the second scanning signal G2
  • Re1 represents the timing of the capacitor reset control signal Re1
  • Re2 represents the timing of the electrode reset control signal Re2
  • EM represents the enable signal.
  • the timing of EM, Da represents the timing of driving data signal Da.
  • the pixel driving circuit can work in four stages: capacitance reset stage t1, threshold compensation stage t2, electrode reset stage t3, and light-emitting stage t4.
  • the capacitor reset signal Re1 is a high-level signal
  • the capacitor reset transistor T1 is turned on, and the capacitor reset voltage Vinit1 is loaded to the first node N1.
  • the driving transistor T3 is turned on.
  • the first scanning signal G1 is a high-level signal
  • the second scanning signal G2 is a low-level signal
  • the data writing transistor T4 and the threshold compensation transistor T2 are turned on, and the data writing transistor T4 will drive the data signal Da
  • the voltage Vdata is written to the second node N2, and finally the first node N1 is charged to the voltage of Vdata+Vth.
  • Vth is the threshold voltage of drive transistor T3.
  • the electrode reset control signal Re2 is a low-level signal
  • the electrode reset transistor T7 is turned on, and the electrode reset transistor T7 loads the capacitor reset voltage Vinit2 to the pixel electrode of the light-emitting element.
  • the enable signal EM is a low-level signal
  • the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, and the driving transistor T3 outputs a driving current under the control of the first node N1 to drive the light-emitting element to emit light.
  • the driving transistor output current formula I ( ⁇ WCox/2L)(Vgs-Vth) 2 , where ⁇ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, and L driver The length of the transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor.
  • the pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.
  • the display panel of this example may include a base substrate BP, a light-shielding layer LBSM, a first insulating buffer layer Buff1, a low-temperature polysilicon semiconductor layer LPoly, a first gate insulating layer LGI1, and a first gate layer that are stacked in sequence.
  • LG1 second insulating buffer layer Buff2 (such as silicon nitride, silicon oxide and other inorganic layers), second gate layer LG2, second gate insulating layer LGI2, metal oxide semiconductor layer LOxide, third gate insulating layer LGI3 , the third gate layer LG3, the interlayer dielectric layer ILD, the first source and drain metal layer LSD1, the passivation layer PVX, the first planarization layer PLN1, the second source and drain metal layer LSD2, the second planarization layer PLN2, and the pixel Electrode layer LAn, pixel definition layer PDL, organic light-emitting functional layer LEL, common electrode layer LCOM and thin film encapsulation layer TFE.
  • second insulating buffer layer Buff2 such as silicon nitride, silicon oxide and other inorganic layers
  • second gate layer LG2 such as silicon nitride, silicon oxide and other inorganic layers
  • second gate insulating layer LGI2 such as silicon nitride, silicon oxide and other inorganic layers
  • one drive circuit island PDCC can include eight drive circuit areas PDCA arranged in two rows and four columns; a wiring space PDCG is formed between the drive circuit islands PDCC, and the wiring space PDCG includes two adjacent areas.
  • the first transition section TR1 is disposed in the row gap CC
  • the second transition section TR2 is disposed in the column gap DD.
  • each driving circuit group includes two adjacent driving circuits in the first direction, and the two driving circuits are arranged in mirror images.
  • the film layer structure of one example of the driving circuit is further introduced.
  • the light shielding layer LBSM has light shielding blocks BSMP corresponding one-to-one to the channel regions T3A of each drive transistor T3, and shielding lines BSML connecting the respective light shielding blocks BSMP.
  • the light-shielding block BSMP can overlap with the corresponding channel region T3A of the driving transistor T3 to block the light irradiating the channel region T3A of the driving transistor T3 so that the electrical characteristics of T3 remain stable.
  • the shading lines BSML are arranged along the first direction and the second direction and connect the adjacent shading blocks BSMP, so that the shading layer LBSM is gridded as a whole.
  • the material of the light-shielding layer LBSM is metal, so that the light-shielding layer LBSM can also have an electromagnetic shielding effect.
  • the low-temperature polysilicon semiconductor layer LPoly is provided with sources of transistors such as a driving transistor T3, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, and an electrode reset transistor T7. , drain and channel regions.
  • the channel region T4A of the data writing transistor T4 and the channel region T5A of the first light emitting control transistor T5 are arranged along the second direction H2, and the channel region T5A of the first light emitting control transistor T5 and the second light emitting control transistor T6
  • the channel regions T6A are arranged along the first direction H1.
  • the channel region T3A of the driving transistor T3 and the channel region T7A of the electrode reset transistor T7 are located between the channel region T5A of the first emission control transistor T5 and the channel region T6A of the second emission control transistor T6.
  • the channel region T7A of the electrode reset transistor T7 and the channel region T3A of the driving transistor T3 are located on both sides of the channel region T5A of the first light emission control transistor T5.
  • the drain T4D of the data writing transistor T4, the drain T5D of the first light-emitting control transistor T5, and the source T3S of the driving transistor T3 are connected, and the drain T3D of the driving transistor T3 and the drain of the second light-emitting control transistor T6 are connected.
  • the drain T7D of the electrode reset transistor T7 and the source T6S of the second light emission control transistor T6 are electrically connected.
  • the channel region T7A of the electrode reset transistor T7 of the upper row driving circuit is adjacent to the channel region T4A of the data writing transistor T4 of the next row of driving circuits.
  • the low-temperature polysilicon semiconductor layer LPoly is also provided with auxiliary wiring PDUMMY, and the auxiliary wiring PDUMMY is located in the column gap DD to ensure process uniformity during the preparation of LPoly.
  • the first gate layer LG1 is provided with the second scanning line GL2 , the enable signal line EML and the first electrode CP1 of the storage capacitor C.
  • the second scan line GL2 extends along the first direction H1 and can be used to load the second scan signal G2.
  • the second scan line GL2 may overlap with the channel region T4A of the data writing transistor T4, and the overlapping portion is multiplexed as the gate of the data writing transistor T4.
  • the second scanning line GL2 may also overlap with the channel region T7A of the electrode reset transistor T7 of the previous row driving circuit, and the overlapping portion is multiplexed as the gate of the electrode reset transistor T7 of the previous row driving circuit.
  • the electrode reset control line RL2 connected to the driving circuit of the previous row and the second scanning line GL2 connected to the driving circuit of the next row are the same wiring.
  • the electrode reset control signal Re2 of the previous row driving circuit and the second scanning signal G2 of the next row driving circuit can be the same signal.
  • the enable signal line EML extends along the first direction H1 and sequentially overlaps the channel region T5A of the first light-emitting control transistor T5 and the channel region T6A of the second light-emitting control transistor T6 to multiplex it into the first light-emitting control transistor.
  • the enable signal line EML can be used to load the enable signal EM.
  • the first electrode CP1 of the storage capacitor C overlaps with the channel region T3A of the driving transistor T3, so as to be multiplexed as the gate electrode of the driving transistor T3.
  • the second gate layer LG2 is provided with a capacitor initialization voltage line Vinit1L, a lower capacitor reset control line RL11, a lower first scan line GL11 and a second electrode CP2 of the storage capacitor C.
  • the capacitor initialization voltage line Vinit1L extends along the first direction H1 and can be used to load the capacitor reset voltage Vinit1.
  • the lower capacitor reset control line RL11 extends along the first direction H1 for loading the capacitor reset control signal Re1.
  • the lower first scan line GL11 extends along the first direction H1 and is used to load the first scan signal G1.
  • the second electrode CP2 of the storage capacitor C overlaps with the first electrode CP1 of the storage capacitor C, and an escape hole HC is provided to expose a partial area of the first electrode CP1 of the storage capacitor C.
  • the metal oxide semiconductor layer LOxide is provided with the source, drain and channel regions of the capacitance reset transistor T1 and the threshold compensation transistor T2.
  • the channel region T1A of the capacitance reset transistor T1 is located on a side of the channel region T2A of the threshold compensation transistor T2 away from the channel region T3A of the driving transistor T3, and the channel region T2A of the threshold compensation transistor T2 is connected to
  • the channel region T5A of the first light emission control transistor T5 is located on both sides of the channel region T3A of the driving transistor T3.
  • the channel region T4A of the data writing transistor T4 of the next row driving circuit and the channel region T1A of the capacitive reset transistor T1 are located on both sides of the channel region T7A of the electrode reset transistor T7 of the previous row driving circuit.
  • the drain T1D of the capacitive reset transistor T1 and the drain T2D of the threshold compensation transistor T2 are connected to each other.
  • the channel region T1A of the capacitor reset transistor T1 overlaps with the lower capacitor reset control line RL11, so that at least part of the overlapping portion of the lower capacitor reset control line RL11 and the channel region T1A of the capacitor reset transistor T1 can be reused.
  • the lower first scanning line GL11 overlaps the channel region T2A of the threshold compensation transistor T2, so that at least part of the overlapping portion of the lower first scanning line GL11 and the channel region T2A of the threshold compensation transistor T2 can be multiplexed. is the first gate of the threshold compensation transistor T2.
  • the orthographic projection of the channel region T1A of the capacitive reset transistor T1 on the second gate layer is located within the lower capacitive reset control line RL11 , so that the lower capacitive reset control line RL11 is opposite to the channel of the capacitive reset transistor T1 Zone T1A is fully shaded.
  • the orthographic projection of the channel region T2A of the threshold compensation transistor T2 on the second gate layer is located within the lower first scanning line GL11 , so that the lower first scanning line GL11 has a negative impact on the threshold compensation transistor T2 The channel region T2A is fully shielded from light.
  • the third gate layer LG3 includes an upper capacitor reset control line RL12 and an upper first scanning line GL12.
  • the upper capacitor reset control line RL12 extends along the first direction H1 for loading the capacitor reset control signal Re1.
  • the upper first scan line GL12 extends along the first direction H1 and is used to load the first scan signal G1.
  • the upper capacitor reset control line RL12 overlaps with the channel region T1A of the capacitor reset transistor T1, and the overlapping portion thereof is multiplexed as the second gate of the capacitor reset transistor T1.
  • the upper first scanning line GL12 overlaps with the channel region T2A of the threshold compensation transistor T2, and the overlapping portion of the two is multiplexed as the second gate of the threshold compensation transistor T2.
  • the gate electrode of the capacitance reset transistor T1 includes the first gate electrode and the second gate electrode of the capacitance reset transistor T1;
  • the gate electrode of the threshold compensation transistor T2 includes the first gate electrode and the second gate electrode of the threshold compensation transistor T2.
  • the low-temperature polysilicon semiconductor layer LPoly, the first gate layer LG1, the second gate layer LG2 and the metal oxide semiconductor layer LOxide can be connected to the first source and drain metal through via holes.
  • Layer LSD1 is electrically connected.
  • the lower conductive film layer (the film layer close to the base substrate BP) has a lower via area aligned with the position of the via hole
  • the upper conductive film layer (The film layer away from the base substrate BP) has an upper via area aligned with the location of the via hole.
  • the upper via hole area of the upper conductive film layer is directly electrically connected to the lower via hole area of the lower conductive film layer through the via hole.
  • the low-temperature polysilicon semiconductor layer LPoly can be provided with first lower via areas HA1 to fifth lower via areas HA5; the first lower via area HA1 is located at the source T4S of the data writing transistor T4, and the second lower via area HA1 is located at the source T4S of the data writing transistor T4.
  • the hole area HA2 is located at the source T5S of the first light emitting control transistor T5, the third lower via hole area HA3 is located at the drain T6D of the second light emitting control transistor T6, and the fourth lower via hole area HA4 is located at the source electrode T7S of the electrode reset transistor T7.
  • the fifth lower via area HA5 is located at the source T6S of the second light emission control transistor T6.
  • the metal oxide semiconductor layer LOxide may be provided with a sixth lower via area HA6 to an eighth lower via area HA8, where the sixth lower via area HA6 is located at the source T2S of the threshold compensation transistor T2, and the seventh lower via area HA7 is located at the drain T2D of the threshold compensation transistor T2, and the eighth lower via region HA8 is located at the source T1S of the capacitive reset transistor T1.
  • the second electrode CP2 of the storage capacitor C is provided with a ninth lower via area HA9, and the first electrode CP1 of the storage capacitor C is provided with a tenth lower via area HA10.
  • the tenth lower via area HA10 is located in the avoidance gap HC of the second electrode CP2 of the storage capacitor C.
  • An eleventh lower via area HA11 may be provided on the capacitor initialization voltage line Vinit1L.
  • two drive circuits are connected to the capacitor initialization voltage line Vinit1L through the same via hole.
  • the display panel is also provided with an electrode initialization voltage line, which is zigzag along the first direction H1 as a whole to load the electrode reset voltage Vinit2.
  • the portion of the electrode initialization voltage line located between the drive circuit islands PDCC can be wired across the first gate layer LG1, and the remaining portion can be wired through the first source-drain metal layer LSD1. ; In this way, the second transition section TR2 located on the first source-drain metal layer LSD1 can be arranged in the gap between the two driving circuits.
  • the electrode initialization voltage lines may include the second initialization line Vinit2L2 located in the first source-drain metal layer LSD1, and the first initialization line Vinit2L1 located in the first gate layer LG1 .
  • the first initial line Vinit2L1 is located in the gap between the driving circuit islands PDCC
  • the second initial line electrode Vinit2L2 is basically located in the driving circuit island PDCC.
  • the end of the first initial line Vinit2L1 has a twelfth lower via area HA12
  • the end of the second initial line Vinit2L2 has a twelfth upper via area HB12 overlapping with the twelfth lower via area HA12; tenth
  • the second lower via area HA12 and the twelfth upper via area HB12 are connected through via holes.
  • the second initial line Vinit2L2 has a fourth upper via area HB4 that overlaps with the fourth lower via area HA4, and the fourth lower via area HA4 and the fourth upper via area HB4 are connected through via holes.
  • the source T7S of the electrode reset transistor T7 is electrically connected to the electrode initialization voltage line.
  • the electrode initialization voltage lines may all be provided in the first source-drain metal layer LSD1.
  • the first source-drain metal layer LSD1 is also provided with first to sixth conductive structures ML1 to ML6.
  • the first conductive structure ML1 has a first upper via area HB1 and a thirteenth lower via area HA13, where the first upper via area HB1 overlaps the first lower via area HA1 and is connected through a via hole.
  • the second source-drain metal layer LSD2 is provided with a data trace DL extending along the second direction H2, and the data trace DL is used to load the driving data signal Da.
  • the data trace DL is provided with a thirteenth upper via area HB13 that overlaps with the thirteenth lower via area HA13.
  • the thirteenth upper via area HB13 and the thirteenth lower via area HA13 are connected through via holes. In this way, the source T4S of the data writing transistor T4 is connected to the data line DL through the first conductive structure ML1.
  • the second conductive structure ML2 has a second upper via area HB2, a ninth upper via area HB9, and a fourteenth lower via area HA14.
  • the second upper via hole area HB2 overlaps with the second lower via hole area HA2 and is connected through via holes.
  • the ninth upper via hole area HB9 overlaps with the ninth lower via hole area HA9 and is connected through via holes.
  • the second source-drain metal layer LSD2 is provided with a power trace VDDL extending along the second direction H2, and the power trace VDDL is used to load the power supply voltage VDD.
  • the power trace VDDL has a fourteenth upper via area HB14 that overlaps with the fourteenth lower via area HA14.
  • the fourteenth upper via area HB14 and the fourteenth lower via area HA14 are connected through via holes.
  • the second electrode CP2 of the storage capacitor C, the power trace VDDL and the source T5S of the first light emission control transistor T5 are electrically connected to each other through the second conductive structure ML2.
  • the third conductive structure ML3 has a tenth upper via hole region HB10 and a seventh upper via hole region HB7.
  • the tenth upper via hole area HB10 overlaps with the tenth lower via hole area HA10 and is connected through via holes.
  • the seventh upper via hole area HB7 overlaps with the seventh lower via hole area HA7 and is connected through via holes.
  • the drain T1D of the capacitance reset transistor T1 and the drain T2D of the threshold compensation transistor T2 are electrically connected to the first electrode CP1 of the storage capacitor C (multiplexed as the gate of the driving transistor T3) through the third conductive structure ML3.
  • the fourth conductive structure ML4 is provided with an eighth upper via area HB8 and an eleventh upper via area HB11.
  • the eighth upper via area HB8 overlaps with the eighth lower via area HA8 and is connected through a via hole.
  • the upper via hole area HB11 overlaps with the eleventh lower via hole area HA11 and is connected through via holes.
  • the capacitance initializing voltage line Vinit1L is electrically connected to the source T1S of the capacitance reset transistor T1 through the fourth conductive structure ML4.
  • the fifth conductive structure ML5 has a fifth upper via area HB5 and a sixth upper via area HB6.
  • the fifth upper via area HB5 overlaps with the fifth lower via area HA5 and is connected through a via hole.
  • the sixth upper via hole overlaps with the sixth lower via hole area HA6 and is connected through via holes.
  • the drain T3D of the driving transistor T3 is electrically connected to the source T2S of the threshold compensation transistor T2 through the fifth conductive structure ML5.
  • the sixth conductive structure ML6 is provided with a third upper via area HB3 and a fifteenth lower via area HA15.
  • the third upper via area HB3 and the third lower via area HA3 overlap and are connected through via holes.
  • the second source-drain metal layer LSD2 is provided with a transfer electrode PA, and the transfer electrode PA is used to electrically connect with the pixel electrode of the sub-pixel.
  • the transfer electrode PA is provided with a fifteenth upper via area HB15 that overlaps with the fifteenth lower via area HA15.
  • the fifteenth lower via area HA15 and the fifteenth upper via area HB15 are connected through via holes. .
  • the transfer electrode PA is electrically connected to the drain T6D of the second light-emitting control transistor T6 through the sixth conductive structure ML6, so that the sub-pixel is electrically connected to the drain T6D of the second light-emitting control transistor T6.
  • the first conductive structure ML1 and the fourth conductive structure ML4 are located on one side of the second initial line Vinit2L2, and the second conductive structure ML2, the third conductive structure ML3, the fifth conductive structure ML5 and the sixth conductive structure ML6 are located on the first side of the second initial line Vinit2L2. The other side of the second initial line Vinit2L2.
  • the first conductive structure ML1 to the sixth conductive structure ML6 of the drive circuit are located in the drive circuit area PDCA corresponding to the drive circuit.
  • a rectangular area in which the first conductive structure ML1 to the sixth conductive structure ML6 of the drive circuit is distributed can be used to define the drive circuit area PDCA corresponding to the drive circuit.
  • T1 to T6 of the drive circuit are located in the drive circuit.
  • T7 of the drive circuit is located in the drive circuit area PDCA corresponding to the drive circuit in the next row.
  • the aforementioned electrode initialization voltage line includes an alternately connected first initial line Vinit2L1 and a second initial line Vinit2L2.
  • the first initial line Vinit2L1 is set on the gate layer; the second initial line Vinit2L2 is set on The first source-drain metal layer LSD1; the first initial line Vinit2L1 and the second initial line Vinit2L2 are connected through via holes.
  • Part of the second transfer section TR2 is disposed on the first source-drain metal layer LSD1.
  • the second transfer section TR2 overlaps the first initial line Vinit2L1 but does not overlap the second initial line Vinit2L2.
  • the electrode initialization voltage line can be routed to the second transition section TR2 of the first source-drain metal layer LSD1 through the first initialization line Vinit2L1. Further, the first initial line Vinit2L1 spans the gap between the driving circuit islands PDCC along the first direction.
  • the electrode initialization voltage line can be disposed on the first source-drain metal layer LSD1; the second transfer section TR2 can be disposed above the first source-drain metal layer LSD1 (away from the substrate).
  • the conductive film layer of the substrate BP) is, for example, provided on the second source-drain metal layer LSD2.

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Abstract

一种显示面板和显示装置。显示面板的第一转接线与第一子像素(P1)和第三子像素(P3)对应的第二数据走线(DL2)连接，所有的第一转接线的第二转接段(TR2)与第一源漏金属层(LSD1)或第二源漏金属层(LSD2)同层设置，使得第一转接线的第二转接段(TR2)与底部垂直的扫描走线之间的距离相同，因此所产生的寄生电容相同。在显示面板的显示区(AA)不同位置处，第一子像素(P1)和第三子像素(P3)对应的第二数据走线(DL2)的波形跳变对寄生电容的影响相同，使得显示面板的显示区(AA)不同位置的亮度变化相同，显示面板的显示均一性较好。

Description

显示面板及显示装置 技术领域
本公开涉及显示技术领域，具体而言，涉及一种显示面板及显示装置。
背景技术
有机电致发光二极管(Organic Light Emitting Diode，OLED)显示面板具有自发光、广色域、高对比度、可柔性化、高响应可柔性化等优点，具有广泛的应用前景。
当前，OLED显示面板对实现超窄下边框的要求越来越高。为了减小下边框的宽度，考虑将位于外围区的数据线引入显示区，以缩小下边框的宽度，但这样会导致显示面板的显示均一性较差。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开提供一种显示面板及显示装置。
根据本公开的一个方面，提供一种显示面板，包括显示区和至少部分围绕显示区的外围区；沿第一方向，显示面板的显示区包括第一显示区和位于第一显示区两侧的第二显示区；显示面板包括衬底基板、驱动电路层、像素层、多个焊盘、多条数据走线和多条转接线，驱动电路层包括第一源漏金属层和第二源漏金属层，第一源漏金属层设于衬底基板的一侧，第二源漏金属层设于第一源漏金属层远离衬底基板的一侧；像素层包括多个像素组，像素组包括颜色互不相同的第一子像素、第二子像素和第三子像素；多个焊盘位于外围区；多条数据走线分别与多个第一子像素、多个第二子像素和多个第三子像素电连接，多条数据走线位于显示区且沿第二方向延伸，多条数据走线包括位于第一显示区的多条第一数据走线和位于第二显示区的多条第二数据走线，多条第一数据走线与多个焊盘电连接； 多条转接线，位于显示区且与多条第二数据走线和多个焊盘电连接；多条转接线包括多条第一转接线和多条第二转接线，第一转接线与第一子像素和第三子像素对应的第二数据走线连接，第二转接线与第二子像素对应的第二数据走线连接；转接线包括沿第一方向延伸的第一转接段和沿第二方向延伸的第二转接段，第一方向和第二方向交叉；其中，至少一条第二转接段设置于相邻两条第一数据走线之间；所有的第一转接线的第二转接段与第一源漏金属层或第二源漏金属层同层设置，至少部分第二转接线的第二转接段与第一源漏层或第二源漏层同层设置。
根据本公开的一种实施方式，所有的第一转接线的第二转接段与第一源漏金属层同层设置，所有的第二转接线的第二转接段与第一源漏金属层同层设置。
根据本公开的一种实施方式，所有的第一转接线的第二转接段与第二源漏金属层同层设置，所有的第二转接线的第二转接段与第二源漏金属层同层设置。
根据本公开的一种实施方式，所有的第一转接线的第二转接段与第二源漏金属层同层设置，所有的第二转接线的第二转接段与第一源漏金属层同层设置。
根据本公开的一种实施方式，所有的第一转接线的第二转接段与第二源漏金属层同层设置，一部分第二转接线的第二转接段与第一源漏金属层同层设置，另一部分第二转接线的第二转接段与第二源漏金属层同层设置。
根据本公开的一种实施方式，第二转接线的第二转接段交替分布于第一源漏金属层和第二源漏金属层。
根据本公开的一种实施方式，关于沿第二方向延伸的中轴线对称设置的两条第二转接线的第二转接段同层设置。
根据本公开的一种实施方式，相邻的多条第一数据走线排列成多个第一数据走线组，相邻的多条转接线排列成多个转接线组，相邻的多条转接线的第二转接段形成第二转接段组，在第一显示区的至少部分区域，第一数据走线组和第二转接段组一一交替设置。
根据本公开的一种实施方式，第二转接段组包括至少一条第一转接线 的第二转接段和至少一条第二转接线的第二转接段，第一转接线的第二转接段与第二转接线的第二转接段交替排布。
根据本公开的一种实施方式，第二转接段组包括至少一条第一转接线的第二转接段和至少两条第二转接线的第二转接段，所有的第一转接线的第二转接段与第二源漏金属层同层设置，至少一条第二转接线的第二转接段与第一源漏金属层同层设置，至少一条第二转接线的第二转接段与第二源漏金属层同层设置，第一子像素为红色子像素，第二子像素为绿色子像素，第三子像素为蓝色子像素。
根据本公开的一种实施方式，显示区关于沿第二方向延伸的中轴线对称设置；在相邻两条第二数据走线中，相较于靠近中轴线的第二数据走线对应的第二转接段，远离中轴线的第二数据走线对应的第二转接段远离中轴线设置。
根据本公开的一种实施方式，显示区关于沿第二方向延伸的中轴线对称设置；在相邻两个第二数据走线中，相较于位于靠近中轴线的第二数据走线对应的第一转接段，远离中轴线的第二数据走线对应的第一转接段靠近焊盘设置。
根据本公开的一种实施方式，位于第一显示区的多条第一数据走线设于第一源漏金属层或第二源漏金属层。
根据本公开的一种实施方式，驱动电路层还包括晶体管层，晶体管层设于衬底基板与第一源漏金属层之间，晶体管层设有驱动电路，驱动电路包括薄膜晶体管，转接线与薄膜晶体管不交叠。
根据本公开的一种实施方式，驱动电路层包括阵列分布的驱动电路岛，任意一个驱动电路岛包括一个或者多个与各个驱动电路一一对应的驱动电路区；驱动电路的至少部分薄膜晶体管设置于对应的驱动电路区；转接线设置于驱动电路岛之间的间隙。
根据本公开的一种实施方式，各个第二转接段排列成多个第二转接段组，任意一个第二转接段组中的各个第二转接段，依次相邻设置且位于相邻的两个驱动电路岛列之间；任意相邻的两个第二转接段组之间，均被驱动电路岛列隔离。
根据本公开的一种实施方式，晶体管层具有栅极层；驱动电路层还包 括沿第一方向延伸的电极初始化电压线，电极初始化电压线沿第一方向延伸；电极初始化电压线包括交替连接的第一初始线和第二初始线；第一初始线设置于栅极层；第二初始线设置于第一源漏金属层，部分第二转接段设于第一源漏金属层，位于第一源漏金属层的第二转接段与第一初始线交叠。
根据本公开的一种实施方式，所有的第一转接段与第一源漏金属层或栅极层同层设置，至少部分第二转接段与第二源漏金属层同层设置，位于第二源漏金属层的第二转接段与第一转接段通过转接头连接，第一数据线与转接头相邻的部位向远离转接头的方向弯折形成避让段，避让段与第一转接段交叠。
根据本公开的另一个方面，提供一种显示装置，包括本公开的一个方面所述的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开的一种实施方式中，显示面板的膜层结构示意图。
图2为本公开的一种实施方式中，显示面板的结构示意图。
图3为本公开的一种实施方式中，显示面板的局部结构示意图。
图4为本公开的一种实施方式中，显示面板的局部结构示意图。
图5为本公开的一种实施方式中，显示面板的局部结构示意图。
图6为本公开的一种实施方式中，显示面板的不同子像素对应的第二转接段的一种分布示意图。
图7为本公开的一种实施方式中，显示面板的不同子像素对应的第二转接段的另一种分布示意图。
图8为本公开的一种实施方式中，显示面板的不同子像素对应的第二转接段的又一种分布示意图。
图9为本公开的一种实施方式中，显示面板的不同子像素对应的第二转接段的再一种分布示意图。
图10为本公开的一种实施方式中，显示面板的相邻两根第一数据走线之间设四条第二转接段的分布示意图。
图11为本公开的一种实施方式中，显示面板的不同子像素对应的数据线的波形图。
图12为本公开的一种实施方式中，驱动电路岛的分布示意图。
图13为本公开的一种实施方式中，驱动电路岛与第二转接线的分布示意图。
图14为本公开的一种实施方式中，驱动电路岛与第二转接线的分布示意图。
图15为本公开的一种实施方式中，驱动电路岛与第二转接线的分布示意图。
图16为本公开的一种实施方式中，驱动电路岛与第二转接线的分布示意图。
图17为本公开的一种实施方式中，驱动电路岛与第二转接线的分布示意图。
图18为本公开的一种实施方式中，驱动电路岛与第二转接线的分布示意图。
图19为本公开的一种实施方式中，驱动电路岛与第二转接线的分布示意图。
图20为本公开的一种实施方式中，第一转接线布线区和第二转接线布线区的位置示意图。
图21为本公开的一种实施方式中，第一转接线布线区和第二转接线布线区的位置示意图。
图22为本公开的一种实施方式中，第一转接线布线区和第二转接线布线区的位置示意图。
图23为本公开的一种实施方式中，驱动电路的等效电路图。
图24为本公开的一种实施方式中，驱动电路的驱动时序示意图。
图25为本公开的一种实施方式中，遮光层在驱动电路区的局部结构示意图。
图26为本公开的一种实施方式中，遮光层在显示区的局部结构示意图。
图27为本公开的一种实施方式中，低温多晶硅半导体层和金属氧化物半导体层在驱动电路区的局部结构示意图。
图28为本公开的一种实施方式中，低温多晶硅半导体层在显示区的局部结构示意图。
图29为本公开的一种实施方式中，金属氧化物半导体层在显示区的局部结构示意图。
图30为本公开的一种实施方式中，第一栅极层在驱动电路区的局部结构示意图。
图31为本公开的一种实施方式中，第一栅极层在显示区的局部结构示意图。
图32为本公开的一种实施方式中，第二栅极层在驱动电路区的局部结构示意图。
图33为本公开的一种实施方式中，第二栅极层在显示区的局部结构示意图。
图34为本公开的一种实施方式中，第三栅极层在驱动电路区的局部结构示意图。
图35为本公开的一种实施方式中，第三栅极层在显示区的局部结构示意图。
图36为本公开的一种实施方式中，第一源漏金属层在驱动电路区的局部结构示意图。
图37为本公开的一种实施方式中，第一源漏金属层在显示区的局部结构示意图。
图38为本公开的一种实施方式中，第二源漏金属层在驱动电路区的局部结构示意图。
图39为本公开的一种实施方式中，第二源漏金属层在显示区的局部 结构示意图。
图40为本公开的一种实施方式中，显示面板的一个区域的结构版图。
图41为本公开的一种实施方式中，显示面板的另一个区域的结构版图。
图42为本公开的一种实施方式中，显示面板的又一个区域的结构版图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
随着AMOLED的迅速发展，显示装置进入了全面屏以及窄边框时代。目前，扇出区域(Fanout)的数据走线都是放置于显示区外侧的外围区，从外围区提供给显示区的驱动像素电路的数据，数据走线放置在外围区无疑会增加下边框角和下边框的尺寸。所以考虑将扇出区域 (Fanout)的数据走线引入显示区。当数据走线都放置于显示区时，可以大幅度的减小下边框和下边框角，对于全面屏及窄边框的实现具有重要的意义。
基于此，本公开提供一种显示面板。该显示面板包括显示区和至少部分围绕显示区的外围区；沿第一方向，显示面板的显示区AA包括第一显示区AA1和位于第一显示区AA1两侧的第二显示区AA2。
显示面板包括衬底基板、驱动电路层、像素层、多个焊盘、多条数据走线DL和多条转接线TR，驱动电路层包括第一源漏金属层LSD1和第二源漏金属层LSD2，第一源漏金属层LSD1设于衬底基板BP的一侧，第二源漏金属层LSD2设于第一源漏金属层LSD1远离衬底基板BP的一侧；
像素层EE包括多个像素组P，像素组P包括第一子像素P1，至少一个第二子像素P2和第三子像素P3，第一子像素P1、第二子像素P2和第三子像素P3的颜色互不相同；多个焊盘位于外围区；多条数据走线DL分别与多个第一子像素P1、多个第二子像素P2，多个第三子像素P3电连接，多条数据走线DL位于显示区AA且沿第二方向延伸，多条数据走线DL包括位于第一显示区AA1的多条第一数据走线DL1和位于第二显示区AA2的多条第二数据走线DL2，多条第一数据走线DL1与多个焊盘电连接。
多条转接线TR位于显示区AA且与多条第二数据走线DL2和多个焊盘电连接；多条转接线包括多条第一转接线和多条第二转接线，第一转接线与第一子像素P1和第三子像素P3对应的第二数据走线DL2连接，第二转接线与第二子像素P2对应的第二数据走线DL2连接。
转接线包括沿第一方向H1延伸的第一转接段TR1和沿第二方向H2延伸的第二转接段TR2，第一方向和第二方向交叉；其中，至少一条第二转接段TR2设置于相邻两条第一数据走线DL1之间；所有的第一转接线的第二转接段TR2与第一源漏金属层LSD1或第二源漏金属层LSD2同层设置，至少部分第二转接线的第二转接段TR2与第一源漏层LSD1或第二源漏层LSD1同层设置。
显示面板的第一转接线与第一子像素P1和第三子像素P3对应的第二数据走线DL2连接，所有的第一转接线的第二转接段TR2与第一源漏金 属层LSD1或第二源漏金属层LSD2同层设置，则第一转接线的第二转接段TR2与底部垂直的扫描走线之间的距离相同，因此所产生的寄生电容相同。在显示面板的显示区不同位置处，第一子像素P1和第三子像素P3对应的第二数据走线的波形跳变对寄生电容的影响相同，使得显示面板显示区不同位置的亮度变化相同，显示面板的显示均一性较好。
参见图1，从显示面板的厚度方向，该显示面板包括依次层叠设置的衬底基板BP、驱动电路层DR和像素层EE。其中，像素层EE设置有阵列分布的多个像素组，像素组包括颜色互不相同的第一子像素、第二子像素和第三子像素，驱动电路层DR设置有与各个子像素一一对应的驱动电路；各个子像素在对应的驱动电路的驱动下实现显示。
在驱动电路层中，显示面板可以设置有沿第一方向(一般作为行方向)延伸的扫描走线和沿第二方向(一般作为列方向)延伸的数据走线DL；该显示面板可以实现逐行扫描以显示画面。相应的，各个驱动电路可以排列成沿第一方向延伸的驱动电路行和沿第二方向延伸的驱动电路列。第一方向和第二方向交叉，例如垂直。
衬底基板可以为无机材料的衬底基板，也可以为有机材料的衬底基板。举例而言，在本公开的一种实施方式中，衬底基板的材料可以为钠钙玻璃(soda-lime glass)、石英玻璃、蓝宝石玻璃等玻璃材料，或者可以为不锈钢、铝、镍等金属材料。在本公开的另一种实施方式中，衬底基板的材料可以为聚甲基丙烯酸甲酯(Polymethyl methacrylate，PMMA)、聚乙烯醇(Polyvinyl alcohol，PVA)、聚乙烯基苯酚(Polyvinyl phenol，PVP)、聚醚砜(Polyether sulfone，PES)、聚酰亚胺、聚酰胺、聚缩醛、聚碳酸酯(Poly carbonate，PC)、聚对苯二甲酸乙二酯(Polyethylene terephthalate，PET)、聚萘二甲酸乙二酯(Polyethylene naphthalate，PEN)或其组合。在本公开的另一种实施方式中，衬底基板也可以为柔性衬底基板，例如衬底基板的材料可以为聚酰亚胺(polyimide，PI)。衬底基板还可以为多层材料的复合，举例而言，在本公开的一种实施方式中，衬底基板可以包括依次层叠设置的底膜层(Bottom Film)、压敏胶层、第一聚酰亚胺层和第二聚酰亚胺层。
在本公开中，驱动电路层设置有用于驱动子像素的驱动电路。在驱动电路层中，任意一个驱动电路可以包括有晶体管和存储电容。进一步地， 晶体管可以为薄膜晶体管，薄膜晶体管可以选自顶栅型薄膜晶体管、底栅型薄膜晶体管或者双栅型薄膜晶体管；薄膜晶体管的有源层的材料可以为非晶硅半导体材料、低温多晶硅半导体材料、金属氧化物半导体材料、有机半导体材料或者其他类型的半导体材料；薄膜晶体管可以为N型薄膜晶体管或者P型薄膜晶体管。
可以理解的是，驱动电路中的各个晶体管中，任意两个晶体管之间的类型可以相同或者不相同。示例性地，在一种实施方式中，在一个驱动电路中，部分晶体管可以为N型晶体管且部分晶体管可以为P型晶体管。再示例性地，在本公开的另一种实施方式中，在一个驱动电路中，部分晶体管的有源层的材料可以为低温多晶硅半导体材料，且部分晶体管的有源层的材料可以为金属氧化物半导体材料。
晶体管可以具有第一端、第二端和控制端，第一端和第二端中的一个可以为晶体管的源极，另一个可以为晶体管的漏极，控制端可以为晶体管的栅极。可以理解的是，晶体管的源极和漏极为两个相对且可以相互转换的概念；当晶体管的工作状态改变时，例如电流方向改变时，晶体管的源极和漏极可以互换。
在本公开中，驱动电路层可以包括依次层叠于衬底基板的晶体管层、层间电介质层ILD和源漏金属层。其中，晶体管层中设置有晶体管的有源层和栅极，源漏金属层与晶体管的源极和漏极电连接。可选地，晶体管层可以包括层叠于衬底基板BP和层间电介质层之间的半导体层、栅极绝缘层、栅极层。其中，各个膜层的位置关系可以根据薄膜晶体管的膜层结构确定。
在一些实施方式中，半导体层可以用于形成晶体管的有源层，半导体的有源层包括沟道区和位于沟道区两侧的源极、漏极；其中，沟道区可以保持半导体特性，源极和漏极的半导体材料被局部或者全部导体化。栅极层可以用于形成扫描走线等栅极层走线，也可以用于形成晶体管的栅极，还可以用于形成存储电容的部分或者全部电极板。源漏金属层可以用于形成数据走线、电源走线等源漏金属层走线。
举例而言，在本公开的一些实施方式中，驱动电路层可以包括依次层叠设置的半导体层、栅极绝缘层、栅极层、层间电介质层和源漏金属层， 如此所形成的薄膜晶体管为顶栅型薄膜晶体管。
再举例而言，在本公开的一些实施方式中，驱动电路层可以包括依次层叠设置的栅极层、栅极绝缘层、半导体层、层间电介质层和源漏金属层，如此所形成的薄膜晶体管为底栅型薄膜晶体管。
栅极层可以为一层栅极层，也可以两层或者三层栅极层。示例性地，在一种实施方式中，参见图1，栅极层可以包括第一栅极层LG1、第二栅极层LG2和第三栅极层LG3。半导体层可以为一层半导体层，也可以为两层半导体层。示例性地，在一种实施方式中，参见图1，半导体层可以包括低温多晶硅半导体层LPoly和金属氧化物半导体层LOxide。可以理解的是，当栅极层或者半导体层等具有多层结构时，晶体管层中的绝缘层可以进行适应性地增减。示例性地，在本公开的一种实施方式中，参见图1，晶体管层可以包括依次层叠设置于衬底基板BP的低温多晶硅半导体层LPoly、第一栅极绝缘层LGI1、第一栅极层LG1、第二绝缘缓冲层Buff2(例如氮化硅、氧化硅等无机层)、第二栅极层LG2、第二栅极绝缘层LGI2、金属氧化物半导体层LOxide、第三栅极绝缘层LGI3、第三栅极层LG3等。
源漏金属层可以为一层源漏金属层，也可以为两层源漏金属层。示例性地，在本公开的一种实施方式中，参见图1，源漏金属层可以包括第一源漏金属层LSD1和第二源漏金属层LSD2。其中，第一源漏金属层LSD1和第二源漏金属层LSD2之间可以设置有钝化层PVX和第一平坦化层PLN1，LSD2与像素层之间设置有第二平坦化层PLN2。
可选地，驱动电路层还可以包括设于衬底基板BP与半导体层之间的第一绝缘缓冲层Buff1，且半导体层、栅极层等均位于第一绝缘缓冲层Buff1远离衬底基板的一侧。第一绝缘缓冲层Buff1的材料可以为氧化硅、氮化硅等无机绝缘材料。缓冲材料层可以为一层无机材料层，也可以为多层层叠的无机材料层。
可选地，参见图1，在第一绝缘缓冲层Buff1与衬底基板BP之间，还可以设置有遮光层LBSM，遮光层LBSM可以与至少部分晶体管的沟道区交叠，以遮蔽照射向晶体管的光线，使得晶体管的电学特性稳定。
像素层设置有阵列分布的发光元件(作为子像素)，且各个发光元件 在驱动电路的控制下发光。在本公开中，发光元件可以为有机电致发光二极管(OLED)、微发光二极管(Micro LED)、量子点-有机电致发光二极管(QD-OLED)、量子点发光二极管(QLED)或者其他类型的发光元件。示例性地，在本公开的一种实施方式中，发光元件为有机电致发光二极管(OLED)，则该显示面板为OLED显示面板。如下，以发光元件为有机电致发光二极管为例，对像素层的一种可行结构进行示例性的介绍。
可选地，参见图1，像素层可以设置于驱动电路层远离衬底基板的一侧，其可以包括依次层叠设置的像素电极层LAn、像素定义层PDL、支撑柱层(图1中未示出)、有机发光功能层LEL和公共电极层LCOM。其中，像素电极层LAn在显示面板的显示区具有多个像素电极；像素定义层在显示区具有与多个像素电极一一对应设置的多个贯通的像素开口，任意一个像素开口暴露对应的像素电极的至少部分区域。支撑柱层在显示区包括多个支撑柱，且支撑柱位于像素定义层远离衬底基板的表面，以便在蒸镀制程中支撑精细金属掩模版(Fine Metal Mask，FMM)。有机发光功能层至少覆盖被像素定义层所暴露的像素电极。其中，有机发光功能层可以包括有机电致发光材料层，以及可以包括有空穴注入层、空穴传输层、电子阻挡层、空穴阻挡层、电子传输层和电子注入层中的一种或者多种。可以通过蒸镀工艺制备有机发光功能层的各个膜层，且在蒸镀时可以采用精细金属掩模版或者开放式掩膜板(Open Mask)定义各个膜层的图案。公共电极层在显示区可以覆盖有机发光功能层。如此，像素电极、公共电极层和位于像素电极和公共电极层之间的有机发光功能层形成有机发电致光二极管，任意一个有机电致发光二极管可以作为显示面板的一个子像素。
在一些实施方式中，像素层还可以包括位于公共电极层远离衬底基板一侧的光取出层，以增强有机发光二极管的出光效率。
在一些实施方式中，参见图1，显示面板还可以包括薄膜封装层TFE。薄膜封装层设于像素层远离衬底基板的表面，可以包括交替层叠设置的无机封装层和有机封装层。其中，无机封装层可以有效的阻隔外界的水分和氧气，避免水氧入侵有机发光功能层而导致材料降解。可选地，无机封装层的边缘可以位于外围区。有机封装层位于相邻的两层无机封装层之间， 以便实现平坦化和减弱无机封装层之间的应力。其中，有机封装层的边缘，可以位于显示区的边缘和无机封装层的边缘之间。示例性地，薄膜封装层包括依次层叠于像素层远离衬底基板一侧的第一无机封装层、有机封装层和第二无机封装层。
在一些实施方式中，显示面板还可以包括触控功能层，触控功能层设于薄膜封装层远离衬底基板的一侧，用于实现显示面板的触控操作。
在一些实施方式中，显示面板还可以包括降反层，降反层可以设置于薄膜封装层远离像素层的一侧，用于降低显示面板对环境光线的反射，进而降低环境光线对显示效果的影响。在本公开的一种实施方式中，降反层可以包括层叠设置的彩膜层和黑矩阵层，如此可以在实现降低环境光线干扰的同时，可以避免降低显示面板的透光率。在本公开的另一种实施方式中，降反层可以为偏光片，例如可以为图案化的涂布型圆偏光片。进一步地，降反层可以设置于触控功能层远离衬底基板的一侧。
参见图2，从正视的角度看，显示面板可以包括显示区AA和至少部分围绕显示区AA的外围区BB。其中，各个子像素可以设置于显示区AA内。显示面板在外围区BB还具有绑定区B1，该绑定区设置有多个焊盘用于绑定驱动芯片或者绑定电路板，以便实现对显示面板的驱动。
在本公开中，可以将显示区AA靠近绑定区B1的一端定义为下端；其中，显示区AA的下端为其在第二方向H2上的一端。各个数据走线DL沿第一方向H1依次排列，且均需与绑定区B1中的焊盘电连接，以便从绑定区接收驱动数据信号。参见图2，显示面板可以设置有与各个数据走线DL一一对应的焊盘连接线FA(图2中仅仅示例了部分焊盘连接线FA)，焊盘连接线FA一端伸入至绑定区中以与焊盘电连接，另一端与对应的数据走线DL电连接。这样，数据走线DL通过对应的焊盘连接线FA与绑定区B1中的焊盘电连接。
在本公开中，参见图2，沿第一方向H1，显示区AA可以包括第一显示区AA1和分别位于第一显示区AA1两侧的两个第二显示区AA2。数据走线DL包括位于第一显示区AA1的第一数据走线DL1和位于第二显示区AA2的第二数据走线DL2。
参见图3～图5，显示面板还包括与各个第二数据走线DL2一一对应 设置的转接线TR。转接线TR的一端与对应的第二数据走线DL2连接，另一端从第一显示区AA1伸出并与焊盘连接线FA电连接。换言之，第二数据走线DL2连接有转接线TR，这些转接线TR从第一显示区AA1伸出显示区AA，并通过焊盘连接线FA电连接至绑定区。
这样，第二数据走线DL2无需从第二显示区AA2伸出显示区AA并向绑定区延伸，这节省了外围区BB在下端的布线空间，进而利于减小显示面板的边框。这样，本公开可以将远离显示区AA中轴线MM(即位于显示区AA的外侧)的数据走线DL转接至靠近显示区AA内侧的区域，并从靠近显示区AA的中轴线MM的区域电连接至绑定区，进而减小焊盘连接线FA的布线空间，使得显示面板具有超窄下边框。
示例性地，第二转接线通过对应的焊盘连接线与焊盘电连接；第一数据走线通过对应的焊盘连接线与焊盘电连接。
在本公开中，显示区AA的中轴线MM沿第二方向H2延伸，中轴线MM两侧的子像素的列数可以相同，显示区的宽度基本相同；此时，可以认为显示区AA沿中轴线MM对称设置。为了表述方便，可以在第一方向H1上，将靠近显示区AA的中轴线MM的方向定义为内侧，将远离显示区AA的中轴线MM的方向定义为外侧。换言之，在相邻两个数据走线DL中，外侧的数据走线DL更远离显示区AA的中轴线MM。
在一些实施方式中，各个转接线TR关于中轴线MM对称设置。这样，利于显示面板的设计、制备和驱动。
在一些实施方式中，参见图3，显示面板靠近绑定区的顶角(下端顶角)可以为非直角，例如可以为弧形顶角，尤其是可以为圆角。在该实施方式中，可以使得弧形顶角所对应的各列像素驱动电路均位于第二显示区AA2中。换言之，在第一方向H1上，弧形顶角的分布范围在第二显示区AA2的分布范围内。这样，本公开的显示面板具有下圆角和超窄下边框，能够实现四边大角度弯折功能，而且可以改善模组贴合褶皱问题。进一步地，弧形顶角可以为超窄圆角。
示例性地，在第一方向H1上，弧形顶角的分布范围与第二显示区AA2的分布范围重合。这样，弧形顶角对应的各列驱动电路所连接的数据走线DL，均可以通过转接线TR转接至第一显示区AA1中。
在本公开的一种实施方式中，显示面板可以为柔性显示面板；这样，该柔性显示面板可以在顶角处实现大角度的弯折，而且可以减少或者消除显示面板在贴合时出现的褶皱，进而提高基于该显示面板的显示装置的良率。在该实施方式中，通过将顶角处对应的数据走线DL转接至第一显示区AA1中，可以使得该显示面板实现超窄下圆角、超窄下边框，进一步提高显示装置的屏占比。
在本公开的一种实施方式中，显示面板远离绑定区的顶角(上端顶角)也可以为非直角，例如可以为弧形角，尤其是可以为圆角。示例性地，在本公开的一种实施方式中，参见图2，显示面板的四个顶角GG均为圆角。
在一些实施方式中，参见图3～图5，转接线TR可以包括沿第一方向H1延伸的第一转接段TR1和沿第二方向H2延伸的第二转接段TR2。其中，至少一个第二转接段TR2位于相邻两个第一数据走线DL1之间。第一数据走线DL1可以直接延伸出显示区AA并与该第一数据走线DL1对应的焊盘连接线FA电连接。
这样，本公开相当于将部分第二数据走线DL2的焊盘连接线穿插在第一数据走线DL1的焊盘连接线之间，显示装置的驱动器可以根据显示面板中第一数据走线DL1和第二转接线TR2来适应性的调整驱动数据信号，以便驱动显示面板。
在一些实施方式中，在相邻两个第二数据走线DL2中，外侧的第二数据走线DL2对应的转接线TR的第二转接线TR2，位于内侧的第二数据走线DL2对应的转接线TR的第二转接线TR2的外侧。换言之，第二数据走线DL2越靠近外侧，则第二数据走线DL2的第二转接线TR2越靠近外侧。这样，各个第二数据走线DL2所连接的转接线TR的长度差异较小，对各个第二数据走线DL2的阻抗的影响差异小，利于对各个第二数据走线DL2上的驱动数据信号的补偿。
相应的，在相邻两个第二数据走线DL2中，外侧的第二数据走线DL2对应的转接线TR的第一转接段TR1，位于内侧的第二数据走线DL2对应的转接线TR的第一转接段TR1靠近焊盘连接线FA的一侧。即，第二数据走线DL2越靠近外侧，则该第二数据走线DL2所连接的第一转接段TR1越靠近绑定端。
当然的，在本公开的其他实施方式中，转接线还可以采用其他的方式设置。示例性地，在相邻两个第二数据走线中，外侧的第二数据走线对应的转接线的第二转接线，位于内侧的第二数据走线对应的转接线的第二转接线的内侧。在相邻两个第二数据走线中，内侧的第二数据走线对应的转接线的第一转接段，位于外侧的第二数据走线对应的转接线的第一转接段的下端一侧。
在一些实施方式中，各个转接线TR的长度可以基本一致，例如最长的转接线TR的长度为最短的转接线TR的长度的1.0～1.2倍之间。如此，各个转接线TR的长度差异小，对加载至第二数据走线DL2上的驱动数据信号的影响差异小，利于第二数据走线DL2上的驱动数据信号的补偿。在本公开中，可以通过调整第一转接段TR1设置的位置和第二转接线TR2设置的位置，进而调整第一转接段TR1和第二转接线TR2的长度，进而调节转接线TR的长度。
如图6至图10所示，像素层EE包括多个像素组P，像素组包括第一子像素P1、第二子像素P2和第三子像素P3，第一子像素P1、第二子像素P2和第三子像素P3的颜色互不相同，多个第一子像素P1和多个第三子像素P3交替沿第二方向H2排布成第一像素列，多个第二子像素P2沿第二方向H2排成第二像素列，第一像素列与第二像素列沿第一方向H1交替排列，第二子像素P2在第二方向H2上位于第一子像素P1和第三子像素P3之间。其中，第一子像素P1可以为红色子像素，第二子像素P2可以为绿色子像素，第三子像素P3可以为蓝色子像素。
位于第一像素列的第一子像素P1和第三子像素P3通过一条数据走线DL连接，位于第二像素列的多个第二子像素P2通过另一条数据走线DL连接，与多个第一像素列和多个第二像素列分别连接的多条数据走线DL位于显示区且沿第二方向H2延伸。多条数据走线DL包括位于第一显示区的多条第一数据走线DL1和位于第二显示区的多条第二数据走线DL2，多条第一数据走线DL1与多个焊盘电连接。
显示面板还包括与各个第二数据走线DL2一一对应设置的转接线TR。多条转接线TR的一端与对应的第二数据走线DL2连接，另一端从第一显示区AA1伸出并与焊盘连接线FA电连接。多条转接线TR包括多条第一 转接线和多条第二转接线，第一转接线的一端与第一子像素P1和第三子像素P3对应的第二数据走线DL2连接，另一端从第一显示区AA1伸出并与焊盘连接线FA电连接；第二转接线的一端与第二子像素P2对应的第二数据走线DL2连接，另一端从第一显示区伸出并与焊盘连接线FA电连接。
在本公开中，驱动电路层包括不同的导电层，通常数据走线DL设于同一导电层，转接线TR的第一转接段TR1设于同一导电层。第二转接段TR2可以包括第一子转接段和第二子转接段两种不同的类型，第一子转接段和第二子转接段可以设于相同的导电层，也可以设于不同的导电层。需要说明的是，第一子转接段指的是第一转接线的第二转接段TR2，第二子转接段具体指的是第二转接线的第二转接段TR2。
具体地，驱动电路层包括栅极层、第一源漏金属层LSD1和第二源漏金属层LSD2，栅极层设于衬底基板BP的一侧，栅极层包括沿远离衬底基板BP方向依次设置的第一栅极层LG1、第二栅极层LG2和第二栅极层LG3，第一源漏金属层LSD1设于栅极层远离衬底基板BP的一侧，第二源漏金属层LSD2设于第一源漏金属层LSD1远离衬底基板BP的一侧。在本公开的一些实施方式中，数据走线DL可以设置于第一源漏金属层LSD1，也可以设置于第二源漏金属层LSD2。第一转接段TR1可以设于栅极层，也可以设于第一源漏金属层LSD1同层。
用粗线表示第一转接线，用细线表示第二转接线，设于第二源漏金属层LSD2远离衬底基板BP一侧的转接线用实线表示，设于第二源漏金属层LSD2与衬底基板BP之间的导电层上的转接线用虚线表示，因为第一转接段位于第二源漏金属层LSD2以下的导电层，因此图6至图10中用虚线表示第一转接线的第一转接段TR1和第二转接线的第一转接段TR1，下面对第一转接线的第一转接段TR1和第二转接线的第一转接段TR1的情况进行详细说明。
如图6和图7所示，当第一子转接段与第二子转接段设于同一导电层时，可以将第一子转接段与第一源漏金属层LSD1同层设置，第二子转接段与第一源漏金属层LSD1同层设置；也可以将第一子转接段与第二源漏金属层LSD2同层设置，第二子转接段与第二源漏金属层LSD2同层设置。
为了降低成本，不新增膜层，相邻两个第一数据线DL1之间的布线空间是通过子像素压缩的方式得到的间隙，将转接线放置于子像素压缩出的间隙中，由于受像素原始像素密度(PPI)的限制，能压缩出的空间有限，为了在间隙中尽可能多放置转接线，因此通常也可以将第一子转接段和第二子转接段设于不同的导电层。例如，将第一子转接段与第二源漏金属层LSD2同层设置，将第二子转接段与第一源漏金属LSD1层同层设置，还可以将第一转接段设与第二源漏金属LSD2层同层设置，将第二子转接段与第一源漏金属层LSD1同层设置。
如图1所示，扫描走线沿第一方向延伸，且设于衬底基板与第一源漏金属层之间。可以理解的是，第一源漏金属层LSD1和第二源漏金属层LSD2的电阻R虽然相同，但第一源漏金属层LSD1和第二源漏金属层LSD2与扫描走线之间的距离不同，因此第一源漏金属层LSD1与扫描走线之间的寄生电容不同于第二源漏金属层LSD2与扫描走线之间的寄生电容。
采用第一源漏金属层LSD1和第二源漏金属层LSD2交替走线时，必须考虑整体内阻压降(RC Loading)对于显示效果的影响。如图11所示，与第一像素列连接的第二数据线DL2的波形W1是跳变的；与第二像素列连接的第二数据线DL2的波形W2为一条直线。如图8所示，为了避免与第一像素列连接的第二数据线DL2的波形跳变进一步增大与扫描走线的寄生电容影响，可以将第一子转接段设于第二源漏金属层，第二子转接段设于第一源漏金属层。
因为第一子转接段与扫描走线之间的距离较大，因此第一子转接段与扫描走线之间的寄生电容较小，与第一像素列连接的第二数据线DL2的波形跳变对寄生电容产生的影响较小，则内阻压降(RC Loading)的波动较小，对显示面板的显示效果的影响较小。第二子转接段与扫描走线之间的距离较小，虽然所产生的寄生电容较大，而与第二像素列连接的第二数据线DL2的波形为一条直线，寄生电容及内阻压降不会产生波动，对显示面板的显示效果的没有影响。
当需要转接的第二数据线DL2的数量或两列第一数据线DL1之间能插入的第二转接段的数量不能被2或4整除时，根据间隙的大小不同，可 以考虑将第一子转接段分布于不同的导电层，或将第二子转接段分布于不同的导电层。
前面提到与第二像素列连接的第二数据线的寄生电容及内阻压降不会产生波动。则可以如图9所示，将第一子转接段与第二源漏金属层LSD2同层设置，将一部分第二子转接段与第一源漏金属层LSD1同层设置，另一部分第二子转接段与第二源漏金属层同层设置。进一步可以是，将第二子转接段交替分布于第一源漏金属层LSD1和第二源漏金属层LSD2。
第二转接段组TR2S包括至少一条第一转接线的第二转接段TR2和至少两条第二转接线的第二转接段TR2，所有的第一转接线的第二转接段TR2与第二源漏金属层LSD2同层设置，至少一条第二转接线的第二转接段TR2与第一源漏金属层LSD1同层设置，至少一条第二转接线的第二转接段TR2与第二源漏金属层LSD2同层设置。
本公开的实施例中，第一子像素P1为红色子像素，第二子像素P2为绿色子像素，第三子像素P3为蓝色子像素。因此，第一转接线与红色子像素和蓝色子像素对应的第二数据走线DL2连接，第二转接线与绿子像素对应的第二数据走线DL2连接。
具体如图10所示，像素组包括一个第一子像素P1、两个第二子像素P2和一个第三子像素P3，第二转接段组TR2S包括对应第一子像素P1和第三子像素P3的两条第一转接线的第二转接段TR2，以及对应两个第二子像素P2的两条第二转接线的第二转接段TR2，两条第一转接线的第二转接段TR2与第二源漏金属层LSD2同层设置，一条第二转接线的第二转接段TR2与第一源漏金属层LSD1同层设置，另一条第二转接线的第二转接段TR2与第二源漏金属层LSD2同层设置。
本公开实施例中，在转接线的数量较少或子像素压缩出的间隙较大时，该显示面板一般尽量是将与第一子像素P1、第二子像素P2和第三子像素P3对应的第二数据走线的第二转接段TR2都设于同一导电层，进一步的，采用第二源漏金属层LSD2，如此可以减少数据走线DL与下方背板信号线，如扫描线之间的串扰；当数据走线信号之间串扰可以接受时，也可以均采用第一源漏金属层LSD1。
本公开实施例中，当在转接线的数量较多或子像素压缩出的间隙较小 时，相邻两根第一数据走线DL1之间能插入的第二转接段TR2的数量受到限制，均采用第一源漏金属层LSD1或者第二源漏金属层LSD2，可能就无法插入所有的第二数据走线连接的第二转接段TR2；该情况下，第一子像素P1和第三子像素P3对应的第一转接线的第二转接段TR2设于第二源漏金属层LSD2，第二子像素P2对应的第二转接线的第二转接段TR2设于第一源漏金属层LSD1，具体可以是将第一转接线的第二转接段TR2与第二转接线TR2的第二转接段交替分布于第一源漏金属层LSD1和第二源漏金属层LSD2；
当相邻两根第一数据走线DL1之间能插入的第二转接段TR2的数量无法被2或4除尽时，将第一子像素P1和第三子像素P3对应的第一转接线的第二转接段TR2设于第二源漏金属层LSD2，第二子像素P2对应的第二转接线的第二转接段TR2设于第一源漏金属层LSD1或第二源漏金属层LSD2。
可以理解的是，人眼敏感的红色子像素和蓝色子像素对应的第一转接线的第二转接段TR2采用第二源漏金属层LSD2，绿色子像素对应的第二转接线的第二转接段TR2在无法使用第二源漏金属层LSD2层的位置，换成第一源漏金属层LSD1，从而实现整体画面显示均一。
需要强调的是，关于沿第二方向延伸的中轴线对称设置的两条第二子转接段同层设置，以使得显示面板关于沿第二方向H2延伸的中轴线对称位置的显示亮度趋于相同。例如：当分布于中轴线MM一侧的第一条第二子转接段设于第一源漏金属层LSD1时，则中轴线MM另一侧与第二条第二子转接段对称的第二子转接段也设于第一源漏金属层LSD1；当分布于中轴线一侧的第三条第二子转接段设于第二源漏金属层LSD2时，则中轴线另一侧与第四条第二子转接段对称的第二子转接段也设于第二源漏金属层LSD2。
在本公开中，驱动电路层设置有驱动电路的薄膜晶体管，转接线TR与薄膜晶体管不交叠。进一步地，可以根据需要调整各个薄膜晶体管的位置和间隙，以便为布设转接线TR预留空间。
在本公开中，当描述两个结构交叠时，指的是两个结构处于不同的膜层，且两个结构在衬底基板上的正投影至少部分重合。当描述两个结构不 交叠时，指的是两个结构处于不同的膜层，且两个结构在衬底基板上的正投影没有重合区域。
在本公开中，参见图12，驱动电路层设有与各个子像素一一对应的驱动电路，显示面板可以包括与各个驱动电路一一对应设置的驱动电路区PDCA。其中，驱动电路的多数或者全部晶体管可以位于该驱动电路对应的驱动电路区PDCA中，该驱动电路的少数晶体管可以位于相邻的驱动电路区PDCA中以利于信号走线的布设和复用。转接线TR与驱动电路区PDCA不交叠。
在一些实施方式中，驱动电路层除了第一源漏金属层和第二源漏金属层，还可以包括晶体管层，晶体管层可以包括半导体层和栅极层。源漏金属层设置有走线和导电结构，导电结构用于使得晶体管与走线之间电连接。
可以根据驱动电路的导电结构的分布范围，来界定该驱动电路所对应的驱动电路区PDCA。在本公开的一种实施方式中，驱动电路区PDCA为矩形区域，矩形区域的长边沿列方形延伸，短边沿第一方向延伸；驱动电路的各个导电结构，均位于该驱动电路对应的驱动电路区PDCA中。
在一些实施方式中，驱动电路具有存储电容、驱动晶体管、与数据走线DL连接的数据写入晶体管；其中，驱动电路的存储电容、驱动晶体管和数据写入晶体管均位于该驱动电路对应的驱动电路区PDCA中。
在一些实施方式中，在第二方向H2相邻的两个驱动电路中，上一行驱动电路的至少一个薄膜晶体管位于下一行驱动电路对应的驱动电路区PDCA中；上一行驱动电路的其余薄膜晶体管位于该驱动电路对应的驱动电路区PDCA。
作为一种示例，驱动电路设置有用于对像素电极进行复位的电极复位晶体管；驱动电路的电极复位晶体管，可以位于下一行驱动电路对应的驱动电路区PDCA中。相应的，对于不位于显示区AA边缘的驱动电路区PDCA，其内部也设置有上一行驱动电路的电极复位晶体管。
在一些实施方式中，参见图12，驱动电路层包括阵列分布的驱动电路岛PDCC，任意一个驱动电路岛PDCC包括一个或者多个与各个驱动电路一一对应的驱动电路区PDCA；驱动电路的至少部分晶体管设置于对应的驱动电路区PDCA。
前面提到，相邻两个第一数据线之间的布线空间是通过子像素压缩的方式得到的间隙，转接线放置于子像素压缩出的间隙中，具体是压缩子像素的驱动电路。参见图12，在一个驱动电路岛PDCC中的各个驱动电路区PDCA依次相邻设置，驱动电路岛PDCC之间具有间隙。转接线TR设置于驱动电路岛PDCC之间的间隙。
在本公开的一种实施方式中，驱动电路岛PDCC可以排列为多个驱动电路岛PDCC行，每个驱动电路岛PDCC行包括多个沿第一方向H1排列的多个驱动电路岛PDCC，各个驱动电路岛PDCC行沿第二方向H2依次排布。相邻两个驱动电路岛PDCC行之间，设置有行间隙CC。驱动电路岛PDCC可以排列为多个驱动电路岛PDCC列，每个驱动电路岛PDCC列包括多个沿第二方向H2排列的多个驱动电路岛PDCC，各个驱动电路岛PDCC列沿第一方向依次排布。相邻两个驱动电路岛PDCC列之间，设置有列间隙DD。参见图13～图19，转接线TR设置于驱动电路岛PDCC之间的间隙，间隙可以为如图12中所示的行间隙CC或者列间隙DD,。
参见图12，驱动电路岛PDCC中相邻驱动电路区PDCA之间可以没有间隙或者具有较小的间隙。这样，驱动电路岛PDCC中的各个驱动电路区PDCA可以紧凑排列，以利于在驱动电路岛PDCC之间形成较大尺寸的间隙，进而利于转接线TR的布设。可以理解的是，当驱动电路的部分薄膜晶体管不位于该驱动电路对应的驱动电路区PDCA时，这些薄膜晶体管可以位于同一驱动电路岛PDCC中的其他驱动电路区PDCA，也可以位于相邻驱动电路岛PDCC中的驱动电路区PDCA，本公开对此不做限制。
在一些实施方式中，驱动电路排列成多个驱动电路组，每个驱动电路组包括沿第一方向H1相邻且镜像设置的两个驱动电路。其中，驱动电路组的两个驱动电路各自对应的两个驱动电路区PDCA相邻设置且位于同一个驱动电路岛PDCC中。当然的，在本公开的其他实施方式中，相邻驱动电路也可以不采用镜像设计，同行相邻的两个驱动电路的图案可以基本相同。
在一些实施方式中，驱动电路岛PDCC中的驱动电路区PDCA排列成多行多列，以使得驱动电路岛PDCC具有较大的面积，进而使得驱动电路岛PDCC之间的间隙尺寸较大，利于在驱动电路岛PDCC之间的间隙中布 设转接线TR。在本公开的一种实施方式中，驱动电路岛PDCC中的驱动电路区PDCA排列成两行四列。
驱动电路岛PDCC之间的间隙所设置的转接线TR的数量，一方面可以根据实际布线需求进行调整，另一方面受到间隙尺寸、转接线TR宽度、转接线TR间距、转接线TR布设膜层的制约。在本公开中，驱动电路岛PDCC之间的间隙越小，则该间隙中所能够布设的转接线TR的数量越少。
参见图13～图19，驱动电路岛PDCC列之间的第二转接线TR2的数量，可以根据工艺要求来确定，例如可以为1～6个中的任意数量。用虚线表示第一源漏金属层LSD1上的走线，用实线表示第二源漏金属层LSD2上的走线。数据走线DL设置于第二源漏金属层LSD2；转接线TR包括沿第一方向H1延伸的第一转接段TR1和沿第二方向H2延伸的第二转接段TR2，第一转接段TR1设于第一源漏金属层，第二转接段设于第一源漏金属层或第二源漏金属层。
如图13至17所示，在驱动电路岛PDCC之间的间隙足够布设转接线TR的情况下，可以直接将第一子转接段和第二子转接段全部设于第二源漏金属层LSD1。也可以将第一子转接段和第二子转接段直接全部设于第二源漏金属层LSD2。
如图18所示，第一子转接段TR2可以全部设置于第二源漏金属层LSD2，第二子转接段TR2可以全部设置于第一源漏金属层LSD1。如图19所示，还可以将第一子转接段TR2可以全部设置于第二源漏金属层LSD2，第二转接线TR2交替地设置于第一源漏金属层LSD1和第二源漏金属层LSD2。
在本公开的一些实施方式中，第一数据走线DL1靠近绑定区的端部与对应的焊盘连接线FA直接连接。第二数据走线DL2通过转接线TR与焊盘连接线FA连接。这样，可以避免显示面板设置太多的转接线TR，进而利于转接线TR的布设，尤其是适用于高分辨率的显示面板和大圆角的显示面板。
在本公开的另外一些实施方式中，可以使得至少部分第一数据走线DL1也通过转接线TR转接至该第一数据走线DL1对应的焊盘连接线FA。换言之，显示面板还包括与至少部分第一数据走线DL1一一对应电连接 的转接线TR。这样，转接线TR与第二数据走线DL2、至少部分第一数据走线DL1一一对应的电连接。各个数据走线DL对应的转接线TR与数据走线DL对应的焊盘连接线FA电连接。当然的，如果一个第一数据走线DL1没有对应的转接线TR，则该第一数据走线DL1可以直接与焊盘连接线FA电连接。
当源漏金属层具有足够的空间布设足够的转接线TR，例如显示面板的分辨率较低(例如PPI小于410)时，这可以进一步调整焊盘连接线FA的布线顺序和位置，利于显示面板的制备和优化。在本公开的一种实施方式中，各个数据走线DL对应的焊盘连接线FA的排列顺序与各个数据走线DL的排列顺序一致。这样，可以简化外部驱动电路的结构，例如简化驱动芯片的结构。
如下，以显示面板具有不同的像素密度为例，对本公开提供的转接线TR的设置方式做进一步地解释和说明。
在该示例的显示面板中，同行设置的驱动电路可以两两一组形成多个驱动电路组，一个驱动电路组的两个驱动电路可以镜像设置。其中，将相邻两行两列的四个驱动电路组作为一个驱动电路岛PDCC。在该示例的显示面板中，驱动电路组为了满足工艺等需求，其在第一方向H1上的尺寸最小可以达到49微米。
将显示区AA中轴线MM其中任意一侧的半个第一显示区AA1作为一个排布区，则第一显示区AA1被分割为位于中轴线MM两侧的两个排布区。在该示例中，仅仅以其中一个排布区作为示例，来解释和说明一个排布区中数据走线DL和转接线TR的设置方式。两个排布区中，数据走线DL和转接线TR的排布可以关于中轴线MM对称，也可以不同。优选地，两个排布区中，数据走线DL和转接线TR的排布可以关于中轴线MM对称。
在该示例中，在一个排布区中，数据走线DL的数量为n；其中，按照从外侧向内侧的顺序，将第i个数据走线DL记做数据走线DL(i)。在一个排布区中，第二数据走线DL2的数量为x个，则第一数据走线DL1的数量为n-x个。换言之，数据走线DL(1)～数据走线DL(x)为第二数据走线DL2；数据走线DL(x+1)～数据走线DL(n)为第一数据走线DL1。在一个排 布区中，可以将数据走线DL(i)所连接的转接线TR的第二转接段TR2记做第二转接段TR(i)。
在第一种示例的显示面板中，显示面板的像素密度不高于410PPI(Pixels Per Inch)。驱动电路组在第一方向H1上的尺寸最小可以被压缩至49微米。这样，驱动电路岛PDCC在第一方向H1上的列间隙DD的宽度可以达到13微米以上。
如图18和图19所示，驱动电路岛PDCC列之间的间隙能够最多容置六根第二转接段TR2。进一步地，作为一个第二转接段组TR2S中的六个第二转接段TR2，依次交替地分布在第一源漏金属层LSD1和第二源漏金属层LSD2。可以是将第一转接线的第二转接段设于第二源漏金属层LSD2，将第二转接线的至少部分第二转接段设于第二源漏金属层LSD2。
具体可以是，当第二数据线的数量或两列第一数据线之间能插入的第二转接段的数量能被2或4整除时，根据间隙的大小不同，参见图18，可以将所有的第二转接线的第二转接段设于第二源漏金属层LSD1；参见图19，也可以考虑将第二转接线的第二转接段设于第一源漏金属层LSD2，另一部分第二转接段设于第二源漏金属层LSD2。
当列间隙DD的宽度足够大时，还可以是将第一转接线的第二转接段和第二转接线的第二转接段均设于第二源漏金属层LSD2。
在该示例的显示面板中，第一数据走线DL1下端连接至对应的焊盘连接线FA以连接至绑定区。第二数据走线DL2的下端不连接焊盘连接线FA，而是与各个转接线TR一一对应连接；各个转接线TR的第二转接段TR2设置于第一显示区AA1，且第二转接段TR2靠近绑定端的端部(下端)连接焊盘连接线FA以连接至绑定区。其中，至少部分第二转接段TR2设置在驱动电路岛PDCC之间的间隙中。
作为进一步的示例，参见图18和图19，沿从外侧指内侧的方向，一个排布区中的第二转接段TR2和第一数据走线DL1可以按照如下顺序排布：一个第二转接段组TR2S、四个第一数据走线DL1、一个第二转接段组TR2S、四个第一数据走线DL1、······最后一个第二转接段组TR2S、其余第一数据走线DL1。其中，除最后一个第二转接段组TR2S外，其余第二转接段组TR2S均具有六个第二转接段TR2；最后一个第二 转接段组TR2S中第二转接段TR2的数量不超过六个。
示例性地，沿从外侧指内侧的方向，一个排布区中的转接线TR和第一数据走线DL1可以按照如下顺序排布：第二转接段TR(1)～第二转接段TR(6)、数据走线DL(x+1)～数据走线DL(x+4)、第二转接段TR(7)～第二转接段TR(12)、数据走线DL(x+5)～数据走线DL(x+8)······第二转接段TR(x)、其余第一数据走线DL1。
举例说明，参见图18，第一种情况：第二转接段TR(1)、第二转接段TR(3)、第二转接段TR(5)为第二转接线的第二转接段，位于第一源漏金属层LSD1，第二转接段TR(2)、第二转接段TR(4)、第二转接段TR(6)为第二转接线的第二转接段，位于第二源漏金属层LSD2。参见图19，也可以是第二种情况：与第一种情况的不同之处在于，第二转接段TR(1)、第二转接段TR(3)位于第二源漏金属层LSD2，第二转接段TR(5)位于第一源漏金属层LSD1。
在该第一种示例的显示面板的另外一种实现方式中，转接线TR的数量可以超过第二数据走线DL2，使得转接线TR与各个数据走线DL一一对应的电连接。这样，第二数据走线DL2和第一数据走线DL1靠近绑定端的端部(下端)均不与焊盘连接线FA电连接，而是均通过电连接的转接线TR与焊盘连接线FA电连接。
在该中示例中，各个第二转接段TR2可以均设置于第一显示区AA1，且在第一方向H1上按照与各自连接的数据走线DL相同的顺序进行排列。具体的，在一个排布区内，沿从外侧向内侧的方向，第二转接段TR2按照如下的顺序进行排列：第二转接段TR(1)、第二转接段TR(2)、第二转接段TR(3)、第二转接段TR(4)······第二转接段TR(n)。
在第二种示例的显示面板中，显示面板的像素密度在410～425PPI(Pixels Per Inch)之间。驱动电路组在第一方向H1上的尺寸最小可以被压缩至49微米。这样，驱动电路岛PDCC在第一方向H1上的列间隙DD可以达到10.8微米～12.2微米；驱动电路岛PDCC列之间的间隙能够最多容置5根第二转接段TR2。在一种可选地方式中，作为一个第二转接段组TR2S中的5个第二转接段TR2，可以依次交替地分布在第一源漏金属层LSD1和第二源漏金属层LSD2，例如2个在第一源漏金属层LSD1且3 个在第二源漏金属层LSD2，或者3个在第一源漏金属层LSD1且2个在第二源漏金属层LSD2。参见图17，5个第二转接段TR2可以均设置在第二源漏金属层LSD2。
在该示例的显示面板中，第一数据走线DL1的靠近绑定端的一端(下端)连接至焊盘连接线FA以连接至绑定区。第二数据走线DL2靠近绑定区的端部不连接焊盘连接线FA，而是与各个转接线TR一一对应连接；各个转接线TR的第二转接段TR2设置于第一显示区AA1，且第二转接段TR2靠近绑定端的端部连接焊盘连接线FA以连接至绑定区。其中，至少部分第二转接段TR2设置在驱动电路岛PDCC之间的间隙中。
作为进一步的示例，沿从外侧指内侧的方向，一个排布区中的转接线TR和第一数据走线DL1可以按照如下顺序排布：一个第二转接段组TR2S、四个第一数据走线DL1、一个第二转接段组TR2S、四个第一数据走线DL1、······最后一个第二转接段组TR2S、其余第一数据走线DL1。其中，除最后一个第二转接段组TR2S外，其余第二转接段组TR2S均具有5个第二转接段TR2；最后一个第二转接段组TR2S中第二转接段TR2的数量不超过5个。
示例性地，沿从外侧指内侧的方向，一个排布区中的转接线TR和第一数据走线DL1可以按照如下顺序排布：第二转接段TR(1)～第二转接段TR(5)、数据走线DL(x+1)～数据走线DL(x+4)、第二转接段TR(6)～第二转接段TR(10)、数据走线DL(x+5)～数据走线DL(x+8)······第二转接段TR(x)、其余第一数据走线DL1。
在第三种示例的显示面板中，显示面板的像素密度在425～430PPI(Pixels Per Inch)之间。驱动电路组在第一方向H1上的尺寸最小可以被压缩至49微米。这样，驱动电路岛PDCC在第一方向H1上的列间隙DD可以达到10.1微米；参见图16，驱动电路岛PDCC列之间的间隙能够最多容置4根第二转接段TR2。在一种可选地方式中，4个第二转接段TR2可以均设置在第二源漏金属层LSD2。
在该示例的显示面板中，第一数据走线DL1的靠近绑定端的一端连接至焊盘连接线FA以连接至绑定区。第二数据走线DL2靠近绑定区的端部不连接焊盘连接线FA，而是与各个转接线TR一一对应连接；各个转接 线TR的第二转接段TR2设置于第一显示区AA1，且第二转接段TR2靠近绑定端的端部连接焊盘连接线FA以连接至绑定区。其中，至少部分第二转接段TR2设置在驱动电路岛PDCC之间的间隙中。
作为进一步的示例，沿从外侧指内侧的方向，一个排布区中的转接线TR和第一数据走线DL1可以按照如下顺序排布：一个第二转接段组TR2S、四个第一数据走线DL1、一个第二转接段组TR2S、四个第一数据走线DL1、······最后一个第二转接段组TR2S、其余第一数据走线DL1。其中，除最后一个第二转接段组TR2S外，其余第二转接段组TR2S均具有4个第二转接段TR2；最后一个第二转接段组TR2S中第二转接段TR2的数量不超过4个。
示例性地，沿从外侧指内侧的方向，一个排布区中的转接线TR和第一数据走线DL1可以按照如下顺序排布：第二转接段TR(1)～第二转接段TR(4)、数据走线DL(x+1)～数据走线DL(x+4)、第二转接段TR(5)～第二转接段TR(8)、数据走线DL(x+5)～数据走线DL(x+8)······第二转接段TR(x)、其余第一数据走线DL1。
在第四种示例的显示面板中，显示面板的像素密度在430～450PPI(Pixels Per Inch)之间。驱动电路组在第一方向H1上的尺寸最小可以被压缩至49微米。这样，驱动电路岛PDCC在第一方向H1上的列间隙DD可以达到7.4微米；参见图15，驱动电路岛PDCC列之间的间隙能够最多容置3根第二转接段TR2。在一种可选地方式中，3个第二转接段TR2可以均设置在第二源漏金属层LSD2。
在该示例的显示面板中，第一数据走线DL1的靠近绑定端的一端连接至焊盘连接线FA以连接至绑定区。第二数据走线DL2靠近绑定区的端部不连接焊盘连接线FA，而是与各个转接线TR一一对应连接；各个转接线TR的第二转接段TR2设置于第一显示区AA1，且第二转接段TR2靠近绑定端的端部连接焊盘连接线FA以连接至绑定区。其中，至少部分第二转接段TR2设置在驱动电路岛PDCC之间的间隙中。
作为进一步的示例，沿从外侧指内侧的方向，一个排布区中的转接线TR和第一数据走线DL1可以按照如下顺序排布：一个第二转接段组TR2S、四个第一数据走线DL1、一个第二转接段组TR2S、四个第一数据走线 DL1、······最后一个第二转接段组TR2S、其余第一数据走线DL1。其中，除最后一个第二转接段组TR2S外，其余第二转接段组TR2S均具有3个第二转接段TR2；最后一个第二转接段组TR2S中第二转接段TR2的数量不超过3个。
示例性地，沿从外侧指内侧的方向，一个排布区中的转接线TR和第一数据走线DL1可以按照如下顺序排布：第二转接段TR(1)～第二转接段TR(3)、数据走线DL(x+1)～数据走线DL(x+4)、第二转接段TR(4)～第二转接段TR(6)、数据走线DL(x+5)～数据走线DL(x+8)······第二转接段TR(x)、其余第一数据走线DL1。
在第五种示例的显示面板中，显示面板的像素密度在450～465PPI(Pixels Per Inch)之间。驱动电路组在第一方向H1上的尺寸最小可以被压缩至49微米。这样，驱动电路岛PDCC在第一方向H1上的列间隙DD可以达到5.6微米；参见图14，驱动电路岛PDCC列之间的间隙能够最多容置2根第二转接段TR2。在一种可选地方式中，2个第二转接段TR2可以均设置在第二源漏金属层LSD2。
在该示例的显示面板中，第一数据走线DL1的靠近绑定端的一端连接至焊盘连接线FA以连接至绑定区。第二数据走线DL2靠近绑定区的端部不连接焊盘连接线FA，而是与各个转接线TR一一对应连接；各个转接线TR的第二转接段TR2设置于第一显示区AA1，且第二转接段TR2靠近绑定端的端部连接焊盘连接线FA以连接至绑定区。其中，至少部分第二转接段TR2设置在驱动电路岛PDCC之间的间隙中。
作为进一步的示例，沿从外侧指内侧的方向，一个排布区中的转接线TR和第一数据走线DL1可以按照如下顺序排布：一个第二转接段组TR2S、四个第一数据走线DL1、一个第二转接段组TR2S、四个第一数据走线DL1、······最后一个第二转接段组TR2S、其余第一数据走线DL1。其中，除最后一个第二转接段组TR2S外，其余第二转接段组TR2S均具有3个第二转接段TR2；最后一个第二转接段组TR2S中第二转接段TR2的数量不超过3个。
示例性地，沿从外侧指内侧的方向，一个排布区中的转接线TR和第一数据走线DL1可以按照如下顺序排布：第二转接段TR(1)～第二转接段 TR(2)、数据走线DL(x+1)～数据走线DL(x+4)、第二转接段TR(3)～第二转接段TR(4)、数据走线DL(x+5)～数据走线DL(x+8)······第二转接段TR(x)、其余第一数据走线DL1。
在第五种示例的显示面板中，显示面板的像素密度在465～490PPI(Pixels Per Inch)之间。驱动电路组在第一方向H1上的尺寸最小可以被压缩至49微米。这样，驱动电路岛PDCC在第一方向H1上的间隙可以达到2.8微米；参见图13，驱动电路岛PDCC列之间的间隙能够最多容置1根第二转接段TR2，该第二转接段TR2可以设置在第二源漏金属层LSD2。
在该示例的显示面板中，第一数据走线DL1的靠近绑定端的一端连接至焊盘连接线FA以连接至绑定区。第二数据走线DL2靠近绑定区的端部不连接焊盘连接线FA，而是与各个转接线TR一一对应连接；各个转接线TR的第二转接段TR2设置于第一显示区AA1，且第二转接段TR2靠近绑定端的端部连接焊盘连接线FA以连接至绑定区。其中，至少部分第二转接段TR2设置在驱动电路岛PDCC之间的间隙中。
作为进一步的示例，沿从外侧指内侧的方向，一个排布区中的转接线TR和第一数据走线DL1可以按照如下顺序排布：一个第二转接段组TR2S、四个第一数据走线DL1、一个第二转接段组TR2S、四个第一数据走线DL1、······最后一个第二转接段组TR2S、其余第一数据走线DL1。其中，每个第二转接段组TR2S均只有一个第二转接段TR2。
示例性地，沿从外侧指内侧的方向，一个排布区中的转接线TR和第一数据走线DL1可以按照如下顺序排布：第二转接段TR(1)、数据走线DL(x+1)～数据走线DL(x+4)、第二转接段TR(2)、数据走线DL(x+5)～数据走线DL(x+8)······第二转接段TR(x)、数据走线DL(5x-3)～数据走线DL(n)。
在该示例的显示面板的另外一种可行方式中，转接线TR的数量超过第二数据走线DL2，使得转接线TR与各个数据走线DL一一对应的电连接。这样，第二数据走线DL2和第一数据走线DL1靠近绑定端的端部均不与焊盘连接线FA电连接，而是均通过电连接的转接线TR与焊盘连接线FA电连接。在该中示例中，各个第二转接段TR2可以均设置于第一显示区AA1，且在第一方向H1上按照与各自连接的数据走线DL相同的顺 序进行排列。具体的，在一个排布区内，沿从外侧向内侧的方向，第二转接段TR2按照如下的顺序进行排列：第二转接段TR(1)、第二转接段TR(2)、第二转接段TR(3)、第二转接段TR(4)······第二转接段TR(n)。
在本公开中，第一显示区AA1可以包括分别位于中轴线MM两侧的两个排布区；其中，中轴线MM沿第二方向H2延伸。在本公开的一种实施方式中，转接线TR和第一数据走线DL1关于中轴线MM对称设置。
在本公开中，参见图3，各个第二转接段TR2可以排列成多个第二转接段组TR2S；任意一个第二转接段组TR2S中的各个第二转接段TR2均位于相邻的两个驱动电路岛PDCC列之间(即位于同一列间隙DD中)；任意相邻的两个第二转接段组TR2S之间均被驱动电路岛PDCC列隔离；任意一个第二转接段组TR2S包括一个或者多个第二转接段TR2。
参见图3～图5可知，第二转接段组TR2S中的各个第二转接段TR2，位于相邻的两个数据走线DL之间，例如位于编号为m的数据走线DL(m)和编号为m+1的数据走线DL(m+1)之间。在本公开的一种实施方式中，任意一个第二转接段组TR2S中的第二转接段TR2的数量不超过六个。换言之，在相邻两个驱动电路岛PDCC列之间，第二转接段TR2的数量不超过六个。
在本公开的一种实施方式中，多条第二转接段排列成多个第二转接段组；每个第二转接段组包括相邻的至少两条第二转接段；多条第一数据走线排列成多个第一数据走线组，每个第一数据走线组包括多个相邻的第一数据走线；在第一显示区的至少部分区域，第一数据走线组和第二转接段组一一交替设置。
在本公开的一种实施方式中，在至少一个排布区中，各个第二转接段组TR2S的第二转接段TR2的数量相同。在本公开的另一种实施方式中，在至少一个排布区中，其中一个第二转接段组TR2S具有较少数量的第二转接段TR2，且其余第二转接段组TR2S具有较多且数量相同的第二转接段TR2。
示例性地，在位于在中轴线MM的同一侧，最外侧或者最内侧的第二转接段组TR2S具有较少的第二转接段TR2，且其余第二转接段组TR2S包含较多且相同数量的第二转接段TR2。当然的，在本公开的其他实施方 式中，各个第二转接段组TR2S中的第二转接段TR2的数量可以根据需要独自设置，任意两个第二转接段组TR2S中的第二转接段TR2的数量可以相同或者不同。
在本公开中，在至少一个排布区，参见图20～图22，可以将各个第二转接段组TR2S分布的区域定义为第二转接区TR2A。
在一些实施方式中，在第二转接区TR2A，沿第一方向H1，驱动电路岛PDCC列和第二转接段组TR2S依次间隔设置。如此，可以压缩第二转接区TR2A在第一方向H1上的尺寸。第二转接段组TR2S的起始位置或者终止位置可以根据需要进行调整。
在本公开的一种实施方式中，参见图20，第二转接区TR2A的起始位置(即第二转接段组TR2S从外侧向内侧排列的起始位置)可以靠近第一显示区AA1的外侧。举例而言，在至少一个排布区中，最外侧的第二转接段组TR2S与最外侧的驱动电路岛PDCC列相邻设置。作为一种示例，最外侧的第二转接段组TR2S位于最外侧的第一数据走线DL1的外侧。
在本公开的另一种实施方式中，参见图21，第二转接区TR2A的终止位置(即第二转接段组TR2S从外侧向内侧排列的终止位置)可以靠近第一显示区AA1的中轴线MM；例如，在至少一个排布区中，最内侧的第二转接段组TR2S与最内侧的驱动电路岛PDCC列相邻设置。
在本公开的另一种实施方式中，参见图22，在至少一个排布区中，第二转接区TR2A可以分布于整个排布区。换言之，在至少一个排布区中，第二转接段组TR2S可以沿第一方向H1均匀或者非均匀的分布于排布区。作为一种示例，各个第二转接段组TR2S沿第一方向H1分布于第一显示区AA1。
本公开中，各个第一转接段TR1可以排列成多个第一转接段组TR1S；任意一个第一转接段组TR1S中的各个第一转接段TR1均位于相邻的两个驱动电路岛PDCC行之间(即位于同一行间隙CC中)，且位于同一排布区；任意相邻的两个第一转接段组TR1S之间均被驱动电路岛PDCC行隔离；任意一个第一转接段组TR1S包括一个或者多个第一转接段TR1。
在本公开的一种实施方式中，任意一个第一转接段组TR1S中的第一转接段TR1的数量不超过三个。换言之，在相邻两个驱动电路岛PDCC 行之间，第一转接段TR1的数量不超过三个。
在本公开的一种实施方式中，在至少一个排布区中，各个第一转接段组TR1S的第一转接段TR1的数量相同。在本公开的另一种实施方式中，在至少一个排布区中，其中一个第一转接段组TR1S具有较少数量的第一转接段TR1，且其余第一转接段组TR1S具有较多且数量相同的第一转接段TR1。示例性地，在位于在中轴线MM的同一侧，最靠近焊盘连接线FA或者最远离焊盘连接线FA的第一转接段组TR1S具有较少的第一转接段TR1，且其余第一转接段组TR1S包含较多且相同数量的第一转接段TR1。当然的，在本公开的其他实施方式中，各个第一转接段组TR1S中的第一转接段TR1的数量可以根据需要独自设置，任意两个第一转接段组TR1S中的第一转接段TR1的数量可以相同或者不同。
在本公开中，在至少一个排布区，参见图20～图22，可以将各个第一转接段组TR1S分布的区域定义为第一转接区TR1A。在一些实施方式中，在第一转接区TR1A，沿第二方向H2，驱动电路岛PDCC行和第一转接段组TR1S依次间隔设置。如此，可以压缩第一转接区在第二方向H2上的尺寸。
如下，以一种显示面板的具体结构作为示例，以便对本公开的显示面板的结构及原理做进一步地解释和说明。可以理解的是，在本公开的显示面板中，驱动电路的结构可以为本示例以外的其他结构，以能够实现对子像素的驱动为准。
在该示例的显示面板中，参见图23，驱动电路可以包括电容复位晶体管T1、阈值补偿晶体管T2、驱动晶体管T3、数据写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6和电极复位晶体管T7，以及包括存储电容C。
其中，电容复位晶体管T1、阈值补偿晶体管T2为N型薄膜晶体管，如金属氧化物薄膜晶体管；其余晶体管TFT为P型薄膜晶体管，如低温多晶硅薄膜晶体管。
参见图23，电容复位晶体管T1的源极用于加载电容复位电压Vinit1，栅极用于加载电容复位控制信号Re1，漏极与第一节点N1连接。电容复位晶体管T1用于，响应电容复位控制信号Re1而向第一节点N1加载电 容复位电压Vinit1。阈值补偿晶体管T2的源极与第三节点N3电连接，漏极与第一节点N1电连接，栅极用于加载第一扫描信号G1；阈值补偿晶体管T2用于响应第一扫描信号G1而导通，以将驱动晶体管T3的阈值电压写入第一节点N1。驱动晶体管T3的源极连接第二节点N2，漏极连接第三节点N3，栅极连接第一节点N1。数据写入晶体管T4的源极用于加载驱动数据信号Da，漏极与第二节点N2电连接，栅极用于加载第二扫描信号G2。数据写入晶体管T4用于响应第二扫描信号G2，而将驱动数据信号Da加载至第二节点N2。第一发光控制晶体管T5的源极用于加载电源电压VDD，漏极与第二节点N2连接，栅极用于加载使能信号EM。第二发光控制晶体管T6的源极与第三节点N3连接，漏极与子像素(图23中以有机电致发光二极管OLED作为示例)连接，栅极用于加载使能信号EM。第一发光控制晶体管T5和第二发光控制晶体管T6用于响应使能信号EM而导通。电极复位晶体管T7的源极用于加载电极复位电压Vinit2，漏极与发光元件连接，栅极用于加载电极复位控制信号Re2。电极复位晶体管T7用于响应电极复位控制信号Re2，以向发光单元加载电极复位电压Vinit2。发光元件的像素电极与驱动电路电连接，公共电极用于加载公共电压VSS。存储电容C一端连接第一节点N1，另一端用于加载电源电压VDD。
图24示出了该示例的驱动电路的一种驱动时序示意图。在图24中，G1表示第一扫描信号G1的时序，G2表示第二扫描信号G2的时序，Re1表示电容复位控制信号Re1的时序，Re2表示电极复位控制信号Re2的时序，EM表示使能信号EM的时序，Da表示驱动数据信号Da的时序。
该像素驱动电路可以在电容复位阶段t1、阈值补偿阶段t2，电极复位阶段t3、发光阶段t4等四个阶段工作。
在电容复位阶段t1，电容复位信号Re1呈高电平信号，电容复位晶体管T1导通，电容复位电压Vinit1加载至第一节点N1。在第一节点N1的控制下，驱动晶体管T3导通。
在阈值补偿阶段t2，第一扫描信号G1呈高电平信号，第二扫描信号G2低电平信号，数据写入晶体管T4、阈值补偿晶体管T2导通，数据写入晶体管T4将驱动数据信号Da的电压Vdata写入至第二节点N2，并最 终使得第一节点N1被充电至电压为Vdata+Vth。Vth为驱动晶体管T3的阈值电压。
在电极复位阶段t3，电极复位控制信号Re2呈低电平信号，电极复位晶体管T7导通，电极复位晶体管T7将电容复位电压Vinit2加载至发光元件的像素电极。
发光阶段t4，使能信号EM呈低电平信号，第一发光控制晶体管T5、第二发光控制晶体管T6导通，驱动晶体管T3在第一节点N1的控制下输出驱动电流，以驱动发光元件发光。根据驱动晶体管输出电流公式I＝(μWCox/2L)(Vgs-Vth) 2，其中，μ为载流子迁移率；Cox为单位面积栅极电容量，W为驱动晶体管沟道的宽度，L驱动晶体管沟道的长度，Vgs为驱动晶体管栅源电压差，Vth为驱动晶体管阈值电压。本公开像素驱动电路中驱动晶体管的输出电流I＝(μWCox/2L)(Vdata+Vth-Vdd-Vth) 2。该像素驱动电路能够避免驱动晶体管阈值对其输出电流的影响。
参见图1，该示例的显示面板可以包括依次层叠设置的衬底基板BP、遮光层LBSM、第一绝缘缓冲层Buff1、低温多晶硅半导体层LPoly、第一栅极绝缘层LGI1、第一栅极层LG1、第二绝缘缓冲层Buff2(例如氮化硅、氧化硅等无机层)、第二栅极层LG2、第二栅极绝缘层LGI2、金属氧化物半导体层LOxide、第三栅极绝缘层LGI3、第三栅极层LG3、层间电介质层ILD、第一源漏金属层LSD1、钝化层PVX、第一平坦化层PLN1、第二源漏金属层LSD2、第二平坦化层PLN2、像素电极层LAn、像素定义层PDL、有机发光功能层LEL、公共电极层LCOM和薄膜封装层TFE。
参见图25～图42，一个驱动电路岛PDCC可以包括呈两行四列排列的八个驱动电路区PDCA；驱动电路岛PDCC之间，形成有布线空间PDCG，布线空间PDCG包括位于相邻两个驱动电路岛PDCC行之间的行间隙CC和位于相邻两个驱动电路岛PDCC列之间的列间隙DD。其中，第一转接段TR1设置于行间隙CC中，第二转接段TR2设置于列间隙DD中。
参见图25～图42，驱动电路排列成多个驱动电路组，每个驱动电路组包括第一方向相邻的两个驱动电路，且这两个驱动电路镜像设置。
如下，对其中一个示例的驱动电路的膜层结构做进一步地介绍。
参见图25和图26，遮光层LBSM具有与各个驱动晶体管T3的沟道 区T3A一一对应的遮光块BSMP，以及连接各个遮光块BSMP的遮光线BSML。其中，遮光块BSMP可以与对应的驱动晶体管T3的沟道区T3A交叠，以遮挡照射向驱动晶体管T3的沟道区T3A的光线，使得T3的电学特性保持稳定。遮光线BSML沿第一方向和第二方向设置并连接相邻的遮光块BSMP，使得遮光层LBSM整体上网格化。在本公开的一种实施方式中，遮光层LBSM的材料为金属，以使得遮光层LBSM还可以具有电磁屏蔽作用。
参见图27、图28和图40，低温多晶硅半导体层LPoly设置有驱动晶体管T3、数据写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6和电极复位晶体管T7等晶体管的源极、漏极和沟道区。其中，数据写入晶体管T4的沟道区T4A和第一发光控制晶体管T5的沟道区T5A沿第二方向H2排列，第一发光控制晶体管T5的沟道区T5A和第二发光控制晶体管T6的沟道区T6A沿第一方向H1排列。
沿第一方向H1，驱动晶体管T3的沟道区T3A和电极复位晶体管T7的沟道区T7A位于第一发光控制晶体管T5的沟道区T5A和第二发光控制晶体管T6的沟道区T6A之间；沿第二方向H2，电极复位晶体管T7的沟道区T7A和驱动晶体管T3的沟道区T3A位于第一发光控制晶体管T5的沟道区T5A的两侧。其中，数据写入晶体管T4的漏极T4D、第一发光控制晶体管T5的漏极T5D、驱动晶体管T3的源极T3S之间连接，驱动晶体管T3的漏极T3D和第二发光控制晶体管T6的漏极T6D之间电连接，电极复位晶体管T7的漏极T7D和第二发光控制晶体管T6的源极T6S之间电连接。
其中，在相邻两行驱动电路中，上一行驱动电路的电极复位晶体管T7的沟道区T7A与下一行驱动电路的数据写入晶体管T4的沟道区T4A相邻设置。低温多晶硅半导体层LPoly还设置有辅助布线PDUMMY，辅助布线PDUMMY位于列间隙DD中，以保证LPoly在制备时的工艺均一性。
参见图30、图31和图40，第一栅极层LG1设置有第二扫描走线GL2、使能信号线EML和存储电容C的第一电极CP1。其中，第二扫描走线GL2沿第一方向H1延伸，可以用于加载第二扫描信号G2。第二扫描走线GL2 可以与数据写入晶体管T4的沟道区T4A交叠，交叠部分复用为数据写入晶体管T4的栅极。第二扫描走线GL2也可以与上一行驱动电路的电极复位晶体管T7的沟道区T7A交叠，交叠部分复用为上一行驱动电路中的电极复位晶体管T7的栅极。
如此，上一行驱动电路所连接的电极复位控制线RL2与下一行驱动电路所连接的第二扫描走线GL2，为同一走线。这样，上一行驱动电路的电极复位控制信号Re2与下一行驱动电路的第二扫描信号G2，可以为同一信号。使能信号线EML沿第一方向H1延伸，且依次与第一发光控制晶体管T5的沟道区T5A和第二发光控制晶体管T6的沟道区T6A交叠，以复用为第一发光控制晶体管T5的栅极和第二发光控制晶体管T6的栅极。使能信号线EML可以用于加载使能信号EM。存储电容C的第一电极CP1与驱动晶体管T3的沟道区T3A交叠，以复用为驱动晶体管T3的栅极。
参见图32、图33和图40，第二栅极层LG2设置有电容初始化电压线Vinit1L、下电容复位控制线RL11、下第一扫描走线GL11和存储电容C的第二电极CP2。其中，电容初始化电压线Vinit1L沿第一方向H1延伸，可以用于加载电容复位电压Vinit1。下电容复位控制线RL11沿第一方向H1延伸，以用于加载电容复位控制信号Re1。下第一扫描走线GL11沿第一方向H1延伸，用于加载第一扫描信号G1。存储电容C的第二电极CP2与存储电容C的第一电极CP1交叠，且设置暴露存储电容C的第一电极CP1部分区域的避让孔HC。
参见图27、图29和图40，金属氧化物半导体层LOxide设置有电容复位晶体管T1和阈值补偿晶体管T2的源极、漏极和沟道区。其中，沿第二方向H2，电容复位晶体管T1的沟道区T1A位于阈值补偿晶体管T2的沟道区T2A远离驱动晶体管T3的沟道区T3A的一侧，阈值补偿晶体管T2的沟道区T2A与第一发光控制晶体管T5的沟道区T5A位于驱动晶体管T3的沟道区T3A的两侧。沿第一方向H1，下一行驱动电路的数据写入晶体管T4的沟道区T4A和电容复位晶体管T1的沟道区T1A位于上一行驱动电路的电极复位晶体管T7的沟道区T7A的两侧。电容复位晶体管T1的漏极T1D与阈值补偿晶体管T2的漏极T2D与相互连接。
其中，电容复位晶体管T1的沟道区T1A与下电容复位控制线RL11 交叠，以使得下电容复位控制线RL11与电容复位晶体管T1的沟道区T1A的交叠部分的至少部分区域可以复用为电容复位晶体管T1的第一栅极。下第一扫描走线GL11与阈值补偿晶体管T2的沟道区T2A交叠，以使得下第一扫描走线GL11与阈值补偿晶体管T2的沟道区T2A的交叠部分的至少部分区域可以复用为阈值补偿晶体管T2的第一栅极。在一些实施方式中，电容复位晶体管T1的沟道区T1A在第二栅极层上的正投影位于下电容复位控制线RL11以内，以使得下电容复位控制线RL11对电容复位晶体管T1的沟道区T1A充分遮光。在一些实施方式中，阈值补偿晶体管T2的沟道区T2A在第二栅极层上的正投影位于下第一扫描走线GL11以内，以使得下第一扫描走线GL11对阈值补偿晶体管T2的沟道区T2A充分遮光。
参见图34、图35和图40，第三栅极层LG3包括上电容复位控制线RL12和上第一扫描走线GL12。其中，上电容复位控制线RL12沿第一方向H1延伸，以用于加载电容复位控制信号Re1。上第一扫描走线GL12沿第一方向H1延伸，用于加载第一扫描信号G1。其中，上电容复位控制线RL12与电容复位晶体管T1的沟道区T1A交叠，两者交叠的部分复用为电容复位晶体管T1的第二栅极。上第一扫描走线GL12与阈值补偿晶体管T2的沟道区T2A交叠，两者交叠的部分复用为阈值补偿晶体管T2的第二栅极。如此，电容复位晶体管T1的栅极包括电容复位晶体管T1的第一栅极和第二栅极；阈值补偿晶体管T2的栅极包括阈值补偿晶体管T2的第一栅极和第二栅极。
参见图27、图30、图32和图40，低温多晶硅半导体层LPoly、第一栅极层LG1、第二栅极层LG2和金属氧化物半导体层LOxide，可以通过过孔与第一源漏金属层LSD1电连接。在本公开中，当两个导电膜层通过过孔连接时，下方的导电膜层(靠近衬底基板BP的膜层)具有与过孔位置对准的下过孔区，上方的导电膜层(远离衬底基板BP的膜层)具有与过孔位置对准的上过孔区。上方的导电膜层的上过孔区通过过孔与下方的导电膜层的下过孔区直接电连接。
参见图27，低温多晶硅半导体层LPoly可以设置有第一下过孔区HA1～第五下过孔区HA5；第一下过孔区HA1位于数据写入晶体管T4的 源极T4S，第二下过孔区HA2位于第一发光控制晶体管T5的源极T5S，第三下过孔区HA3位于第二发光控制晶体管T6的漏极T6D，第四下过孔区HA4位于电极复位晶体管T7的源极T7S，第五下过孔区HA5位于第二发光控制晶体管T6的源极T6S。金属氧化物半导体层LOxide可以设置有第六下过孔区HA6～第八下过孔区HA8，其中，第六下过孔区HA6位于阈值补偿晶体管T2的源极T2S，第七下过孔区HA7位于阈值补偿晶体管T2的漏极T2D，第八下过孔区HA8位于电容复位晶体管T1的源极T1S。
参见图30和图32，存储电容C的第二电极CP2设置有第九下过孔区HA9，存储电容C的第一电极CP1设置有第十下过孔区HA10。其中，第十下过孔区HA10位于存储电容C的第二电极CP2的避让缺口HC内。电容初始化电压线Vinit1L上可以设置有第十一下过孔区HA11。在本公开的一种实施方式中，在呈对称设置的一个驱动电路组中，两个驱动电路通过同一过孔连接至电容初始化电压线Vinit1L。
在本公开中，显示面板还设置有电极初始化电压线，电极初始化电压线整体上沿第一方向H1曲折设置，以加载电极复位电压Vinit2。在本公开的一种实施方式中，可以使得电极初始化电压线位于驱动电路岛PDCC之间部分的通过第一栅极层LG1进行跨接走线，其余部分通过第一源漏金属层LSD1进行布线；这样，在两个驱动电路之间的间隙可以布设位于第一源漏金属层LSD1的第二转接段TR2。
换言之，参见图30、图31、图36和图37，电极初始化电压线可以包括位于第一源漏金属层LSD1的第二初始线Vinit2L2，以及位于第一栅极层LG1的第一初始线Vinit2L1。其中，第一初始线Vinit2L1位于驱动电路岛PDCC之间的间隙，第二初始线电极Vinit2L2基本位于驱动电路岛PDCC中。第一初始线Vinit2L1的端部具有第十二下过孔区HA12，第二初始线Vinit2L2的端部具有与第十二下过孔区HA12交叠的第十二上过孔区HB12；第十二下过孔区HA12与第十二上过孔区HB12之间通过过孔连接。其中，第二初始线Vinit2L2具有与第四下过孔区HA4交叠的第四上过孔区HB4，第四下过孔区HA4和第四上过孔区HB4之间通过过孔连接。这样，电极复位晶体管T7的源极T7S电连接至电极初始化电压线。当然的，在本公开的其他实施方式中，电极初始化电压线可以全部设置于 第一源漏金属层LSD1中。
参见图36和图37，第一源漏金属层LSD1还设置有第一导电结构ML1～第六导电结构ML6。第一导电结构ML1具有第一上过孔区HB1和第十三下过孔区HA13，其中，第一上过孔区HB1与第一下过孔区HA1交叠，且通过过孔连接。第二源漏金属层LSD2设置有沿第二方向H2延伸的数据走线DL，数据走线DL用于加载驱动数据信号Da。数据走线DL设置有与第十三下过孔区HA13交叠的第十三上过孔区HB13，第十三上过孔区HB13与第十三下过孔区HA13通过过孔连接。这样，数据写入晶体管T4的源极T4S通过第一导电结构ML1与数据走线DL连接。
第二导电结构ML2具有第二上过孔区HB2、第九上过孔区HB9和第十四下过孔区HA14。第二上过孔区HB2与第二下过孔区HA2交叠且通过过孔连接，第九上过孔区HB9与第九下过孔区HA9交叠且通过过孔连接。第二源漏金属层LSD2设置有沿第二方向H2延伸的电源走线VDDL，电源走线VDDL用于加载电源电压VDD。电源走线VDDL具有与第十四下过孔区HA14交叠的第十四上过孔区HB14，第十四上过孔区HB14与第十四下过孔区HA14通过过孔连接。这样，存储电容C的第二电极CP2、电源走线VDDL和第一发光控制晶体管T5的源极T5S，通过第二导电结构ML2相互电连接。
第三导电结构ML3具有与第十上过孔区HB10和第七上过孔区HB7。第十上过孔区HB10与第十下过孔区HA10交叠且通过过孔连接，第七上过孔区HB7与第七下过孔区HA7交叠且通过过孔连接。这样，电容复位晶体管T1的漏极T1D和阈值补偿晶体管T2的漏极T2D通过第三导电结构ML3与存储电容C的第一电极CP1(复用为驱动晶体管T3的栅极)电连接。
第四导电结构ML4设置有第八上过孔区HB8和第十一上过孔区HB11，第八上过孔区HB8与第八下过孔区HA8交叠且通过过孔连接，第十一上过孔区HB11与第十一下过孔区HA11交叠且通过过孔连接。这样，电容初始化电压线Vinit1L通过第四导电结构ML4与电容复位晶体管T1的源极T1S电连接。
第五导电结构ML5具有第五上过孔区HB5和第六上过孔区HB6，第 五上过孔区HB5与第五下过孔区HA5交叠且通过过孔连接，第六上过孔区HB6与第六下过孔区HA6交叠且通过过孔连接。这样，驱动晶体管T3的漏极T3D通过第五导电结构ML5与阈值补偿晶体管T2的源极T2S电连接。
第六导电结构ML6设置有第三上过孔区HB3和第十五下过孔区HA15，第三上过孔区HB3与第三下过孔区HA3交叠且通过过孔连接。参见图38和图39，第二源漏金属层LSD2设置有转接电极PA，转接电极PA用于与子像素的像素电极电连接。其中，转接电极PA设置有与第十五下过孔区HA15交叠的第十五上过孔区HB15，第十五下过孔区HA15与第十五上过孔区HB15通过过孔连接。这样，转接电极PA通过第六导电结构ML6电连接至第二发光控制晶体管T6的漏极T6D，进而使得子像素电连接至第二发光控制晶体管T6的漏极T6D。
参见图36，第一导电结构ML1和第四导电结构ML4位于第二初始线Vinit2L2的一侧，第二导电结构ML2、第三导电结构ML3、第五导电结构ML5和第六导电结构ML6位于第二初始线Vinit2L2的另一侧。
参见图36，驱动电路的第一导电结构ML1～第六导电结构ML6，位于该驱动电路对应的驱动电路区PDCA中。在一些实施方式中，可以采用驱动电路的第一导电结构ML1～第六导电结构ML6分布的矩形区域来界定该驱动电路对应的驱动电路区PDCA，这样，驱动电路的T1～T6位于该驱动电路对应的驱动电路区PDCA中，驱动电路的T7位于下一行的驱动电路对应的驱动电路区PDCA中。
进一步结合37和图41可知，前面提到的电极初始化电压线包括交替连接的第一初始线Vinit2L1和第二初始线Vinit2L2，第一初始线Vinit2L1设置于栅极层；第二初始线Vinit2L2设置于第一源漏金属层LSD1；第一初始线Vinit2L1和第二初始线Vinit2L2通过过孔连接。其中，部分第二转接段TR2设置于第一源漏金属层LSD1，第二转接段TR2与第一初始线Vinit2L1交叠而与第二初始线Vinit2L2不交叠。
这样，电极初始化电压线可以通过第一初始线Vinit2L1避让位于第一源漏金属层LSD1的第二转接段TR2。进一步地，第一初始线Vinit2L1沿第一方向跨越驱动电路岛PDCC之间的间隙。当然的，在本公开的另外一 种实施方式中，电极初始化电压线可以设置于第一源漏金属层LSD1；第二转接段TR2可以设置于第一源漏金属层LSD1以上(远离衬底基板BP)的导电膜层，例如设置于第二源漏金属层LSD2。
结合图39和图42可知，所有的第一转接段TR1与第一源漏金属层LSD1或栅极层同层设置，至少部分第二转接段TR2与第二源漏金属层LSD2同层设置，位于第二源漏金属层LSD2的第二转接段TR2与第一转接段TR1通过转接头连接，第一数据线DL1与转接头相邻的部位向远离转接头的方向弯折形成避让段DL0，避让段DL0与第一转接段TR1交叠。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (19)

  1. 一种显示面板，包括显示区和至少部分围绕所述显示区的外围区；其中，沿第一方向，所述显示面板的显示区包括第一显示区和位于所述第一显示区两侧的第二显示区；所述显示面板包括：
    衬底基板；
    驱动电路层，包括第一源漏金属层和第二源漏金属层，所述第一源漏金属层设于所述衬底基板的一侧，所述第二源漏金属层设于所述第一源漏金属层远离所述衬底基板的一侧；
    像素层，包括多个像素组，所述像素组包括颜色互不相同的第一子像素、第二子像素和第三子像素；
    多个焊盘，位于所述外围区；
    多条数据走线，分别与多个所述第一子像素、多个所述第二子像素和多个所述第三子像素电连接，所述多条数据走线位于所述显示区且沿第二方向延伸，所述多条数据走线包括位于所述第一显示区的多条第一数据走线和位于所述第二显示区的多条第二数据走线，所述多条第一数据走线与所述多个焊盘电连接；
    多条转接线，位于所述显示区且与所述多条第二数据走线和所述多个焊盘电连接；所述多条转接线包括多条第一转接线和多条第二转接线，所述第一转接线与所述第一子像素和所述第三子像素对应的第二数据走线连接，所述第二转接线与所述第二子像素对应的第二数据走线连接；
    所述转接线包括沿所述第一方向延伸的第一转接段和沿所述第二方向延伸的第二转接段，所述第一方向和所述第二方向交叉；其中，至少一条所述第二转接段设置于相邻两条所述第一数据走线之间；所有的所述第一转接线的所述第二转接段与所述第一源漏金属层或所述第二源漏金属层同层设置，至少部分所述第二转接线的所述第二转接段与所述第一源漏层或所述第二源漏层同层设置。
  2. 根据权利要求1所述的显示面板，其中，所有的所述第一转接线的所述第二转接段与所述第一源漏金属层同层设置，所有的所述第二转接线的所述第二转接段与所述第一源漏金属层同层设置。
  3. 根据权利要求1所述的显示面板，其中，所有的所述第一转接线 的所述第二转接段与所述第二源漏金属层同层设置，所有的所述第二转接线的所述第二转接段与所述第二源漏金属层同层设置。
  4. 根据权利要求1所述的显示面板，其中，所有的所述第一转接线的所述第二转接段与所述第二源漏金属层同层设置，所有的所述第二转接线的所述第二转接段与所述第一源漏金属层同层设置。
  5. 根据权利要求1所述的显示面板，其中，所有的所述第一转接线的所述第二转接段与所述第二源漏金属层同层设置，一部分所述第二转接线的所述第二转接段与所述第一源漏金属层同层设置，另一部分所述第二转接线的所述第二转接段与所述第二源漏金属层同层设置。
  6. 根据权利要求5所述的显示面板，其中，所述第二转接线的所述第二转接段交替分布于所述第一源漏金属层和所述第二源漏金属层。
  7. 根据权利要求5所述的显示面板，其中，关于沿所述第二方向延伸的中轴线对称设置的所述两条所述第二转接线的所述第二转接段同层设置。
  8. 根据权利要求1所述的显示面板，其中，相邻的多条所述第一数据走线排列成多个第一数据走线组，相邻的多条所述转接线排列成多个转接线组，相邻的多条所述转接线的第二转接段形成第二转接段组，在所述第一显示区的至少部分区域，所述第一数据走线组和所述第二转接段组一一交替设置。
  9. 根据权利要求8所述的显示面板，其中，所述第二转接段组包括至少一条第一转接线的第二转接段和至少一条所述第二转接线的第二转接段，所述第一转接线的第二转接段与所述第二转接线的第二转接段交替排布。
  10. 根据权利要求8或9所述的显示面板，其中，所述第二转接段组包括至少一条第一转接线的第二转接段和至少两条所述第二转接线的第二转接段，所有的所述第一转接线的所述第二转接段与所述第二源漏金属层同层设置，至少一条所述第二转接线的所述第二转接段与所述第一源漏金属层同层设置，至少一条所述第二转接线的所述第二转接段与所述第二源漏金属层同层设置，所述第一子像素为红色子像素，所述第二子像素为绿色子像素，所述第三子像素为蓝色子像素。
  11. 根据权利要求1所述的显示面板，其中，所述显示区关于沿所述第二方向延伸的中轴线对称设置；在相邻两条所述第二数据走线中，相较于靠近所述中轴线的所述第二数据走线对应的所述第二转接段，远离所述中轴线的所述第二数据走线对应的所述第二转接段远离所述中轴线设置。
  12. 根据权利要求1所述的显示面板，其中，所述显示区关于沿所述第二方向延伸的中轴线对称设置；在相邻两个所述第二数据走线中，相较于位于靠近所述中轴线的所述第二数据走线对应的所述第一转接段，远离所述中轴线的所述第二数据走线对应的所述第一转接段靠近所述焊盘设置。
  13. 根据权利要求1所述的显示面板，其中，位于所述第一显示区的多条第一数据走线设于所述第一源漏金属层或所述第二源漏金属层。
  14. 根据权利要求1所述的显示面板，其中，所述驱动电路层还包括晶体管层，所述晶体管层设于所述衬底基板与所述第一源漏金属层之间，所述晶体管层设有驱动电路，所述驱动电路包括薄膜晶体管，所述转接线与所述薄膜晶体管不交叠。
  15. 根据权利要求14所述的显示面板，其中，所述驱动电路层包括阵列分布的驱动电路岛，任意一个所述驱动电路岛包括一个或者多个与各个所述驱动电路一一对应的驱动电路区；所述驱动电路的至少部分薄膜晶体管设置于对应的所述驱动电路区；所述转接线设置于所述驱动电路岛之间的间隙。
  16. 根据权利要求15所述的显示面板，其中，各个所述第二转接段排列成多个第二转接段组，任意一个所述第二转接段组中的各个所述第二转接段，依次相邻设置且位于相邻的两个驱动电路岛列之间；任意相邻的两个所述第二转接段组之间，均被所述驱动电路岛列隔离。
  17. 根据权利要求1所述的显示面板，其中，所述晶体管层具有栅极层；所述驱动电路层还包括沿第一方向延伸的电极初始化电压线，所述电极初始化电压线沿所述第一方向延伸；所述电极初始化电压线包括交替连接的第一初始线和第二初始线；所述第一初始线设置于所述栅极层；所述第二初始线设置于所述第一源漏金属层，部分所述第二转接段设于所述第一源漏金属层，位于所述第一源漏金属层的所述第二转接段与所述第一初 始线交叠。
  18. 根据权利要求17所述的显示面板，其中，所有的所述第一转接段与所述第一源漏金属层或所述栅极层同层设置，至少部分所述第二转接段与所述第二源漏金属层同层设置，位于所述第二源漏金属层的所述第二转接段与所述第一转接段通过转接头连接，所述第一数据线与转接头相邻的部位向远离所述转接头的方向弯折形成避让段，所述避让段与所述第一转接段交叠。
  19. 一种显示装置，其中，包括权利要求1至18任一项所述的显示面板。
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